* [PATCH v3 0/5] Add Microchip PolarFire Soc Support
@ 2020-12-04 8:58 Atish Patra
2020-12-04 8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Atish Patra @ 2020-12-04 8:58 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Alistair Francis, Anup Patel, Bin Meng,
devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara,
Conor.Dooley
This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
It is rebased on v5.10-rc6 and depends on clock support.
Only MMC and ethernet drivers are enabled via this series.
The idea here is to add the foundational patches so that other drivers
can be added to on top of this. The device tree may change based on
feedback on bindings of individual driver support patches.
This series has been tested on Qemu and Polar Fire Soc Icicle kit.
The following qemu series is necessary to test it on Qemu.
The series can also be found at.
https://github.com/atishp04/linux/tree/polarfire_support_upstream_v3
I noticed the latest version of mmc driver[2] hangs on the board with
the latest clock driver. That's why, I have tested with the old clock
driver available in the above github repo.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
[2] https://www.spinics.net/lists/devicetree/msg383626.html
Changes from v2->v3:
1. Fixed a typo in dt binding.
2. Included MAINTAINERS entry for PolarFire SoC.
3. Improved the dts file by using lowercase clock names and keeping phy
details in board specific dts file.
Changes from v1->v2:
1. Modified the DT to match the device tree in U-Boot.
2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled
as it allows larger storage option for linux distros.
Atish Patra (4):
RISC-V: Add Microchip PolarFire SoC kconfig option
dt-bindings: riscv: microchip: Add YAML documentation for the
PolarFire SoC
RISC-V: Initial DTS for Microchip ICICLE board
RISC-V: Enable Microchip PolarFire ICICLE SoC
Conor Dooley (1):
MAINTAINERS: add microchip polarfire soc support
.../devicetree/bindings/riscv/microchip.yaml | 28 ++
MAINTAINERS | 8 +
arch/riscv/Kconfig.socs | 7 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile | 2 +
.../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++
arch/riscv/configs/defconfig | 4 +
8 files changed, 453 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra @ 2020-12-04 8:58 ` Atish Patra 2021-01-07 11:39 ` Cyril.Jean 2020-12-04 8:58 ` [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra ` (4 subsequent siblings) 5 siblings, 1 reply; 16+ messages in thread From: Atish Patra @ 2020-12-04 8:58 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Bin Meng, Anup Patel, Albert Ou, Alistair Francis, Anup Patel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley Add Microchip PolarFire kconfig option which selects SoC specific and common drivers that is required for this SoC. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/Kconfig.socs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 8a55f6156661..148ab095966b 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,12 @@ menu "SoC selection" +config SOC_MICROCHIP_POLARFIRE + bool "Microchip PolarFire SoCs" + select MCHP_CLK_PFSOC + select SIFIVE_PLIC + help + This enables support for Microchip PolarFire SoC platforms. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option 2020-12-04 8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra @ 2021-01-07 11:39 ` Cyril.Jean 2021-01-07 19:21 ` Atish Patra 0 siblings, 1 reply; 16+ messages in thread From: Cyril.Jean @ 2021-01-07 11:39 UTC (permalink / raw) To: atish.patra, linux-kernel Cc: bin.meng, anup, aou, alistair.francis, anup.patel, devicetree, linux-riscv, palmer, paul.walmsley, robh+dt, Ivan.Griffin, Daire.McNamara, Conor.Dooley Hi Atish, On 12/4/20 8:58 AM, Atish Patra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Add Microchip PolarFire kconfig option which selects SoC specific > and common drivers that is required for this SoC. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Reviewed-by: Bin Meng <bin.meng@windriver.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > --- > arch/riscv/Kconfig.socs | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 8a55f6156661..148ab095966b 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -1,5 +1,12 @@ > menu "SoC selection" > > +config SOC_MICROCHIP_POLARFIRE > + bool "Microchip PolarFire SoCs" > + select MCHP_CLK_PFSOC Can you change MCHP_CLK_PFSOC to MCHP_CLK_MPFS to align with the v2 clock driver? > + select SIFIVE_PLIC > + help > + This enables support for Microchip PolarFire SoC platforms. > + > config SOC_SIFIVE > bool "SiFive SoCs" > select SERIAL_SIFIVE if TTY > -- > 2.25.1 > Regards, Cyril. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option 2021-01-07 11:39 ` Cyril.Jean @ 2021-01-07 19:21 ` Atish Patra 0 siblings, 0 replies; 16+ messages in thread From: Atish Patra @ 2021-01-07 19:21 UTC (permalink / raw) To: Cyril.Jean Cc: Atish Patra, linux-kernel@vger.kernel.org List, devicetree, Bin Meng, Daire McNamara, Anup Patel, Anup Patel, Conor.Dooley, Rob Herring, Ivan.Griffin, Albert Ou, Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv On Thu, Jan 7, 2021 at 3:40 AM <Cyril.Jean@microchip.com> wrote: > > Hi Atish, > > On 12/4/20 8:58 AM, Atish Patra wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Add Microchip PolarFire kconfig option which selects SoC specific > > and common drivers that is required for this SoC. > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > Reviewed-by: Bin Meng <bin.meng@windriver.com> > > Reviewed-by: Anup Patel <anup@brainfault.org> > > --- > > arch/riscv/Kconfig.socs | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > index 8a55f6156661..148ab095966b 100644 > > --- a/arch/riscv/Kconfig.socs > > +++ b/arch/riscv/Kconfig.socs > > @@ -1,5 +1,12 @@ > > menu "SoC selection" > > > > +config SOC_MICROCHIP_POLARFIRE > > + bool "Microchip PolarFire SoCs" > > + select MCHP_CLK_PFSOC > Can you change MCHP_CLK_PFSOC to MCHP_CLK_MPFS to align with the v2 > clock driver? Sure. Will do that. > > + select SIFIVE_PLIC > > + help > > + This enables support for Microchip PolarFire SoC platforms. > > + > > config SOC_SIFIVE > > bool "SiFive SoCs" > > select SERIAL_SIFIVE if TTY > > -- > > 2.25.1 > > > Regards, > > Cyril. > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Regards, Atish ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra 2020-12-04 8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra @ 2020-12-04 8:58 ` Atish Patra 2020-12-09 23:30 ` Rob Herring 2020-12-04 8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra ` (3 subsequent siblings) 5 siblings, 1 reply; 16+ messages in thread From: Atish Patra @ 2020-12-04 8:58 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Alistair Francis, Anup Patel, Bin Meng, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra <atish.patra@wdc.com> --- .../devicetree/bindings/riscv/microchip.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml new file mode 100644 index 000000000000..66e63c2bf359 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/microchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC-based boards device tree bindings + +maintainers: + - Cyril Jean <Cyril.Jean@microchip.com> + - Lewis Hanly <lewis.hanly@microchip.com> + +description: + Microchip PolarFire SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - microchip,mpfs-icicle-kit + - const: microchip,polarfire-soc + - const: microchip,mpfs + +additionalProperties: true + +... -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC 2020-12-04 8:58 ` [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra @ 2020-12-09 23:30 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2020-12-09 23:30 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Albert Ou, Alistair Francis, Anup Patel, Bin Meng, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley On Fri, Dec 04, 2020 at 12:58:32AM -0800, Atish Patra wrote: > Add YAML DT binding documentation for the Microchip PolarFire SoC. > It is documented at: > > https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > .../devicetree/bindings/riscv/microchip.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml > new file mode 100644 > index 000000000000..66e63c2bf359 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml > @@ -0,0 +1,28 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR MIT) See what checkpatch.pl says. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/microchip.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PolarFire SoC-based boards device tree bindings > + > +maintainers: > + - Cyril Jean <Cyril.Jean@microchip.com> > + - Lewis Hanly <lewis.hanly@microchip.com> > + > +description: > + Microchip PolarFire SoC-based boards > + > +properties: > + $nodename: > + const: '/' > + compatible: > + items: > + - enum: > + - microchip,mpfs-icicle-kit > + - const: microchip,polarfire-soc > + - const: microchip,mpfs Is this last compatible really useful? Usually better to just have SoC and board (or SoM plus baseboard) compatibles. Rob ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra 2020-12-04 8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra 2020-12-04 8:58 ` [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra @ 2020-12-04 8:58 ` Atish Patra 2020-12-10 11:06 ` Bin Meng 2021-01-07 11:43 ` Cyril.Jean 2020-12-04 8:58 ` [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra ` (2 subsequent siblings) 5 siblings, 2 replies; 16+ messages in thread From: Atish Patra @ 2020-12-04 8:58 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Alistair Francis, Anup Patel, Bin Meng, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley Add initial DTS for Microchip ICICLE board having only essential devices (clocks, sdhci, ethernet, serial, etc). The device tree is based on the U-Boot patch. https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ 4 files changed, 406 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/Makefile create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ca1f8cbd78c0..3ea94ea0a18a 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive subdir-y += kendryte +subdir-y += microchip obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..622b12771fd3 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts new file mode 100644 index 000000000000..5b51dad13c72 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +#include "microchip-mpfs.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit", "microchip,polarfire-soc"; + + chosen { + stdout-path = &serial0; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + clocks = <&clkcfg 26>; + }; + + soc { + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&sdcard { + status = "okay"; +}; + +&emac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x01>; + }; +}; + +&emac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x01>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi new file mode 100644 index 000000000000..7a076aa4c78d --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC"; + compatible = "microchip,polarfire-soc"; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + + clint@2000000 { + compatible = "riscv,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + }; + + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,pfsoc-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ + "mac0", "mac1", "mmc", "timer", /* 4-7 */ + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ + "i2c1", "can0", "can1", "usb", /* 16-19 */ + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + }; + + serial0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + current-speed = <115200>; + clocks = <&clkcfg 8>; + status = "disabled"; + }; + + serial1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + current-speed = <115200>; + clocks = <&clkcfg 9>; + status = "disabled"; + }; + + serial2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + current-speed = <115200>; + clocks = <&clkcfg 10>; + status = "disabled"; + }; + + serial3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + current-speed = <115200>; + clocks = <&clkcfg 11>; + status = "disabled"; + }; + + emmc: mmc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88 89>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + cap-mmc-highspeed; + mmc-ddr-3_3v; + max-frequency = <200000000>; + non-removable; + no-sd; + no-sdio; + voltage-ranges = <3300 3300>; + status = "disabled"; + }; + + sdcard: sdhc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + disable-wp; + no-1-8-v; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + status = "disabled"; + }; + + emac0: ethernet@20110000 { + compatible = "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <64 65 66 67>; + local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg 5>, <&clkcfg 2>; + clock-names = "pclk", "hclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg 5>, <&clkcfg 2>; + status = "disabled"; + clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2020-12-04 8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra @ 2020-12-10 11:06 ` Bin Meng 2021-01-07 11:43 ` Cyril.Jean 1 sibling, 0 replies; 16+ messages in thread From: Bin Meng @ 2020-12-10 11:06 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Albert Ou, Alistair Francis, Anup Patel, Bin Meng, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley On Fri, Dec 4, 2020 at 5:05 PM Atish Patra <atish.patra@wdc.com> wrote: > > Add initial DTS for Microchip ICICLE board having only > essential devices (clocks, sdhci, ethernet, serial, etc). > The device tree is based on the U-Boot patch. > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ There is a newer version of U-Boot patch. Probably needs to sync again. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ > 4 files changed, 406 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > Regards, Bin ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2020-12-04 8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra 2020-12-10 11:06 ` Bin Meng @ 2021-01-07 11:43 ` Cyril.Jean 2021-01-07 19:26 ` Atish Patra 1 sibling, 1 reply; 16+ messages in thread From: Cyril.Jean @ 2021-01-07 11:43 UTC (permalink / raw) To: atish.patra, linux-kernel Cc: aou, alistair.francis, anup.patel, bin.meng, devicetree, linux-riscv, palmer, paul.walmsley, robh+dt, Ivan.Griffin, Daire.McNamara, Conor.Dooley Hi Atish, On 12/4/20 8:58 AM, Atish Patra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Add initial DTS for Microchip ICICLE board having only > essential devices (clocks, sdhci, ethernet, serial, etc). > The device tree is based on the U-Boot patch. > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ > 4 files changed, 406 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ca1f8cbd78c0..3ea94ea0a18a 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > subdir-y += sifive > subdir-y += kendryte > +subdir-y += microchip > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > new file mode 100644 > index 000000000000..622b12771fd3 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > new file mode 100644 > index 000000000000..5b51dad13c72 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 Microchip Technology Inc */ > + > +/dts-v1/; > + > +#include "microchip-mpfs.dtsi" > + > +/* Clock frequency (in Hz) of the rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "Microchip PolarFire-SoC Icicle Kit"; > + compatible = "microchip,mpfs-icicle-kit", "microchip,polarfire-soc"; > + > + chosen { > + stdout-path = &serial0; > + }; > + > + cpus { > + timebase-frequency = <RTCCLK_FREQ>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x40000000>; > + clocks = <&clkcfg 26>; > + }; > + > + soc { > + }; > +}; > + > +&serial0 { > + status = "okay"; > +}; > + > +&serial1 { > + status = "okay"; > +}; > + > +&serial2 { > + status = "okay"; > +}; > + > +&serial3 { > + status = "okay"; > +}; > + > +&sdcard { > + status = "okay"; > +}; > + > +&emac0 { > + phy-mode = "sgmii"; > + phy-handle = <&phy0>; > + phy0: ethernet-phy@8 { > + reg = <8>; > + ti,fifo-depth = <0x01>; > + }; > +}; > + > +&emac1 { > + status = "okay"; > + phy-mode = "sgmii"; > + phy-handle = <&phy1>; > + phy1: ethernet-phy@9 { > + reg = <9>; > + ti,fifo-depth = <0x01>; > + }; > +}; > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > new file mode 100644 > index 000000000000..7a076aa4c78d > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -0,0 +1,331 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 Microchip Technology Inc */ > + > +/dts-v1/; > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "Microchip PolarFire-SoC"; > + compatible = "microchip,polarfire-soc"; > + > + chosen { > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + clock-frequency = <0>; > + compatible = "sifive,rocket0", "riscv"; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <16384>; > + reg = <0>; > + riscv,isa = "rv64imac"; > + status = "disabled"; > + > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@1 { > + clock-frequency = <0>; > + compatible = "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <1>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + > + cpu1_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@2 { > + clock-frequency = <0>; > + compatible = "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <2>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + > + cpu2_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@3 { > + clock-frequency = <0>; > + compatible = "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <3>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + > + cpu3_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@4 { > + clock-frequency = <0>; > + compatible = "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <4>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + cpu4_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + cache-controller@2010000 { > + compatible = "sifive,fu540-c000-ccache", "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <1024>; > + cache-size = <2097152>; > + cache-unified; > + interrupt-parent = <&plic>; > + interrupts = <1 2 3>; > + reg = <0x0 0x2010000 0x0 0x1000>; > + }; > + > + clint@2000000 { > + compatible = "riscv,clint0"; > + reg = <0x0 0x2000000 0x0 0xC000>; > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > + &cpu1_intc 3 &cpu1_intc 7 > + &cpu2_intc 3 &cpu2_intc 7 > + &cpu3_intc 3 &cpu3_intc 7 > + &cpu4_intc 3 &cpu4_intc 7>; > + }; > + > + plic: interrupt-controller@c000000 { > + #interrupt-cells = <1>; > + compatible = "sifive,plic-1.0.0"; > + reg = <0x0 0xc000000 0x0 0x4000000>; > + riscv,ndev = <186>; > + interrupt-controller; > + interrupts-extended = <&cpu0_intc 11 > + &cpu1_intc 11 &cpu1_intc 9 > + &cpu2_intc 11 &cpu2_intc 9 > + &cpu3_intc 11 &cpu3_intc 9 > + &cpu4_intc 11 &cpu4_intc 9>; > + }; > + > + dma@3000000 { > + compatible = "sifive,fu540-c000-pdma"; > + reg = <0x0 0x3000000 0x0 0x8000>; > + interrupt-parent = <&plic>; > + interrupts = <23 24 25 26 27 28 29 30>; > + #dma-cells = <1>; > + }; > + > + refclk: refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <600000000>; > + clock-output-names = "msspllclk"; > + }; > + > + clkcfg: clkcfg@20002000 { > + compatible = "microchip,pfsoc-clkcfg"; Can you please change "microchip,pfsoc-clkcfg" to "microchip,mpfs-clkcfg" to align with the v2 clock driver? > + reg = <0x0 0x20002000 0x0 0x1000>; > + reg-names = "mss_sysreg"; > + clocks = <&refclk>; > + #clock-cells = <1>; > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > + }; > + > + serial0: serial@20000000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20000000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <90>; > + current-speed = <115200>; > + clocks = <&clkcfg 8>; > + status = "disabled"; > + }; > + > + serial1: serial@20100000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20100000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <91>; > + current-speed = <115200>; > + clocks = <&clkcfg 9>; > + status = "disabled"; > + }; > + > + serial2: serial@20102000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20102000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <92>; > + current-speed = <115200>; > + clocks = <&clkcfg 10>; > + status = "disabled"; > + }; > + > + serial3: serial@20104000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20104000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <93>; > + current-speed = <115200>; > + clocks = <&clkcfg 11>; > + status = "disabled"; > + }; > + > + emmc: mmc@20008000 { > + compatible = "cdns,sd4hc"; > + reg = <0x0 0x20008000 0x0 0x1000>; > + interrupt-parent = <&plic>; > + interrupts = <88 89>; > + pinctrl-names = "default"; > + clocks = <&clkcfg 6>; > + bus-width = <4>; > + cap-mmc-highspeed; > + mmc-ddr-3_3v; > + max-frequency = <200000000>; > + non-removable; > + no-sd; > + no-sdio; > + voltage-ranges = <3300 3300>; > + status = "disabled"; > + }; > + > + sdcard: sdhc@20008000 { > + compatible = "cdns,sd4hc"; > + reg = <0x0 0x20008000 0x0 0x1000>; > + interrupt-parent = <&plic>; > + interrupts = <88>; > + pinctrl-names = "default"; > + clocks = <&clkcfg 6>; > + bus-width = <4>; > + disable-wp; > + no-1-8-v; > + cap-mmc-highspeed; > + cap-sd-highspeed; > + card-detect-delay = <200>; > + sd-uhs-sdr12; > + sd-uhs-sdr25; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > + max-frequency = <200000000>; > + status = "disabled"; > + }; > + > + emac0: ethernet@20110000 { > + compatible = "cdns,macb"; > + reg = <0x0 0x20110000 0x0 0x2000>; > + interrupt-parent = <&plic>; > + interrupts = <64 65 66 67>; > + local-mac-address = [00 00 00 00 00 00]; > + clocks = <&clkcfg 5>, <&clkcfg 2>; > + clock-names = "pclk", "hclk"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + emac1: ethernet@20112000 { > + compatible = "cdns,macb"; > + reg = <0x0 0x20112000 0x0 0x2000>; > + interrupt-parent = <&plic>; > + interrupts = <70 71 72 73>; > + mac-address = [00 00 00 00 00 00]; > + clocks = <&clkcfg 5>, <&clkcfg 2>; > + status = "disabled"; > + clock-names = "pclk", "hclk"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + }; > +}; > -- > 2.25.1 > Regards, Cyril ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-01-07 11:43 ` Cyril.Jean @ 2021-01-07 19:26 ` Atish Patra 0 siblings, 0 replies; 16+ messages in thread From: Atish Patra @ 2021-01-07 19:26 UTC (permalink / raw) To: Cyril.Jean Cc: Atish Patra, linux-kernel@vger.kernel.org List, devicetree, Anup Patel, Daire McNamara, Bin Meng, Conor.Dooley, Rob Herring, Ivan.Griffin, Albert Ou, Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv On Thu, Jan 7, 2021 at 3:44 AM <Cyril.Jean@microchip.com> wrote: > > Hi Atish, > > On 12/4/20 8:58 AM, Atish Patra wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Add initial DTS for Microchip ICICLE board having only > > essential devices (clocks, sdhci, ethernet, serial, etc). > > The device tree is based on the U-Boot patch. > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ > > 4 files changed, 406 insertions(+) > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > > index ca1f8cbd78c0..3ea94ea0a18a 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,5 +1,6 @@ > > # SPDX-License-Identifier: GPL-2.0 > > subdir-y += sifive > > subdir-y += kendryte > > +subdir-y += microchip > > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > > new file mode 100644 > > index 000000000000..622b12771fd3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > new file mode 100644 > > index 000000000000..5b51dad13c72 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > @@ -0,0 +1,72 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > + > > +/dts-v1/; > > + > > +#include "microchip-mpfs.dtsi" > > + > > +/* Clock frequency (in Hz) of the rtcclk */ > > +#define RTCCLK_FREQ 1000000 > > + > > +/ { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + model = "Microchip PolarFire-SoC Icicle Kit"; > > + compatible = "microchip,mpfs-icicle-kit", "microchip,polarfire-soc"; > > + > > + chosen { > > + stdout-path = &serial0; > > + }; > > + > > + cpus { > > + timebase-frequency = <RTCCLK_FREQ>; > > + }; > > + > > + memory@80000000 { > > + device_type = "memory"; > > + reg = <0x0 0x80000000 0x0 0x40000000>; > > + clocks = <&clkcfg 26>; > > + }; > > + > > + soc { > > + }; > > +}; > > + > > +&serial0 { > > + status = "okay"; > > +}; > > + > > +&serial1 { > > + status = "okay"; > > +}; > > + > > +&serial2 { > > + status = "okay"; > > +}; > > + > > +&serial3 { > > + status = "okay"; > > +}; > > + > > +&sdcard { > > + status = "okay"; > > +}; > > + > > +&emac0 { > > + phy-mode = "sgmii"; > > + phy-handle = <&phy0>; > > + phy0: ethernet-phy@8 { > > + reg = <8>; > > + ti,fifo-depth = <0x01>; > > + }; > > +}; > > + > > +&emac1 { > > + status = "okay"; > > + phy-mode = "sgmii"; > > + phy-handle = <&phy1>; > > + phy1: ethernet-phy@9 { > > + reg = <9>; > > + ti,fifo-depth = <0x01>; > > + }; > > +}; > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > new file mode 100644 > > index 000000000000..7a076aa4c78d > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > @@ -0,0 +1,331 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > + > > +/dts-v1/; > > + > > +/ { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + model = "Microchip PolarFire-SoC"; > > + compatible = "microchip,polarfire-soc"; > > + > > + chosen { > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu@0 { > > + clock-frequency = <0>; > > + compatible = "sifive,rocket0", "riscv"; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <16384>; > > + reg = <0>; > > + riscv,isa = "rv64imac"; > > + status = "disabled"; > > + > > + cpu0_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@1 { > > + clock-frequency = <0>; > > + compatible = "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <1>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + > > + cpu1_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@2 { > > + clock-frequency = <0>; > > + compatible = "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <2>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + > > + cpu2_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@3 { > > + clock-frequency = <0>; > > + compatible = "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <3>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + > > + cpu3_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@4 { > > + clock-frequency = <0>; > > + compatible = "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <4>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + cpu4_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + compatible = "simple-bus"; > > + ranges; > > + > > + cache-controller@2010000 { > > + compatible = "sifive,fu540-c000-ccache", "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <1024>; > > + cache-size = <2097152>; > > + cache-unified; > > + interrupt-parent = <&plic>; > > + interrupts = <1 2 3>; > > + reg = <0x0 0x2010000 0x0 0x1000>; > > + }; > > + > > + clint@2000000 { > > + compatible = "riscv,clint0"; > > + reg = <0x0 0x2000000 0x0 0xC000>; > > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > + &cpu1_intc 3 &cpu1_intc 7 > > + &cpu2_intc 3 &cpu2_intc 7 > > + &cpu3_intc 3 &cpu3_intc 7 > > + &cpu4_intc 3 &cpu4_intc 7>; > > + }; > > + > > + plic: interrupt-controller@c000000 { > > + #interrupt-cells = <1>; > > + compatible = "sifive,plic-1.0.0"; > > + reg = <0x0 0xc000000 0x0 0x4000000>; > > + riscv,ndev = <186>; > > + interrupt-controller; > > + interrupts-extended = <&cpu0_intc 11 > > + &cpu1_intc 11 &cpu1_intc 9 > > + &cpu2_intc 11 &cpu2_intc 9 > > + &cpu3_intc 11 &cpu3_intc 9 > > + &cpu4_intc 11 &cpu4_intc 9>; > > + }; > > + > > + dma@3000000 { > > + compatible = "sifive,fu540-c000-pdma"; > > + reg = <0x0 0x3000000 0x0 0x8000>; > > + interrupt-parent = <&plic>; > > + interrupts = <23 24 25 26 27 28 29 30>; > > + #dma-cells = <1>; > > + }; > > + > > + refclk: refclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <600000000>; > > + clock-output-names = "msspllclk"; > > + }; > > + > > + clkcfg: clkcfg@20002000 { > > + compatible = "microchip,pfsoc-clkcfg"; > > Can you please change "microchip,pfsoc-clkcfg" to > "microchip,mpfs-clkcfg" to align with the v2 clock driver? > Sure. > > > + reg = <0x0 0x20002000 0x0 0x1000>; > > + reg-names = "mss_sysreg"; > > + clocks = <&refclk>; > > + #clock-cells = <1>; > > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > > + }; > > + > > + serial0: serial@20000000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20000000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <90>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 8>; > > + status = "disabled"; > > + }; > > + > > + serial1: serial@20100000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20100000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <91>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 9>; > > + status = "disabled"; > > + }; > > + > > + serial2: serial@20102000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20102000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <92>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 10>; > > + status = "disabled"; > > + }; > > + > > + serial3: serial@20104000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20104000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <93>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 11>; > > + status = "disabled"; > > + }; > > + > > + emmc: mmc@20008000 { > > + compatible = "cdns,sd4hc"; > > + reg = <0x0 0x20008000 0x0 0x1000>; > > + interrupt-parent = <&plic>; > > + interrupts = <88 89>; > > + pinctrl-names = "default"; > > + clocks = <&clkcfg 6>; > > + bus-width = <4>; > > + cap-mmc-highspeed; > > + mmc-ddr-3_3v; > > + max-frequency = <200000000>; > > + non-removable; > > + no-sd; > > + no-sdio; > > + voltage-ranges = <3300 3300>; > > + status = "disabled"; > > + }; > > + > > + sdcard: sdhc@20008000 { > > + compatible = "cdns,sd4hc"; > > + reg = <0x0 0x20008000 0x0 0x1000>; > > + interrupt-parent = <&plic>; > > + interrupts = <88>; > > + pinctrl-names = "default"; > > + clocks = <&clkcfg 6>; > > + bus-width = <4>; > > + disable-wp; > > + no-1-8-v; > > + cap-mmc-highspeed; > > + cap-sd-highspeed; > > + card-detect-delay = <200>; > > + sd-uhs-sdr12; > > + sd-uhs-sdr25; > > + sd-uhs-sdr50; > > + sd-uhs-sdr104; > > + max-frequency = <200000000>; > > + status = "disabled"; > > + }; > > + > > + emac0: ethernet@20110000 { > > + compatible = "cdns,macb"; > > + reg = <0x0 0x20110000 0x0 0x2000>; > > + interrupt-parent = <&plic>; > > + interrupts = <64 65 66 67>; > > + local-mac-address = [00 00 00 00 00 00]; > > + clocks = <&clkcfg 5>, <&clkcfg 2>; > > + clock-names = "pclk", "hclk"; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + emac1: ethernet@20112000 { > > + compatible = "cdns,macb"; > > + reg = <0x0 0x20112000 0x0 0x2000>; > > + interrupt-parent = <&plic>; > > + interrupts = <70 71 72 73>; > > + mac-address = [00 00 00 00 00 00]; > > + clocks = <&clkcfg 5>, <&clkcfg 2>; > > + status = "disabled"; > > + clock-names = "pclk", "hclk"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + }; > > +}; > > -- > > 2.25.1 > > > Regards, > > Cyril > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Regards, Atish ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra ` (2 preceding siblings ...) 2020-12-04 8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra @ 2020-12-04 8:58 ` Atish Patra 2020-12-26 0:37 ` Aurelien Jarno 2020-12-04 8:58 ` [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra 2020-12-22 3:19 ` [PATCH v3 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt 5 siblings, 1 reply; 16+ messages in thread From: Atish Patra @ 2020-12-04 8:58 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Anup Patel, Bin Meng, Albert Ou, Alistair Francis, Anup Patel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley Enable Microchip PolarFire ICICLE soc config in defconfig. It allows the default upstream kernel to boot on PolarFire ICICLE board. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d222d353d86d..2660fa05451e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -16,6 +16,7 @@ CONFIG_EXPERT=y CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SMP=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y +CONFIG_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC=y CONFIG_MMC_SPI=y CONFIG_RTC_CLASS=y -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC 2020-12-04 8:58 ` [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra @ 2020-12-26 0:37 ` Aurelien Jarno 0 siblings, 0 replies; 16+ messages in thread From: Aurelien Jarno @ 2020-12-26 0:37 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, devicetree, Bin Meng, Cyril.Jean, Daire McNamara, Anup Patel, Anup Patel, Conor.Dooley, Rob Herring, Ivan.Griffin, Albert Ou, Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv On 2020-12-04 00:58, Atish Patra wrote: > Enable Microchip PolarFire ICICLE soc config in defconfig. > It allows the default upstream kernel to boot on PolarFire ICICLE board. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > Reviewed-by: Bin Meng <bin.meng@windriver.com> > --- > arch/riscv/configs/defconfig | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index d222d353d86d..2660fa05451e 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -16,6 +16,7 @@ CONFIG_EXPERT=y > CONFIG_BPF_SYSCALL=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > +CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_SMP=y > CONFIG_JUMP_LABEL=y > CONFIG_MODULES=y > @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y > CONFIG_USB_OHCI_HCD_PLATFORM=y > CONFIG_USB_STORAGE=y > CONFIG_USB_UAS=y > +CONFIG_SDHCI=y I guess this should be CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_PLTFM=y > +CONFIG_MMC_SDHCI_CADENCE=y > CONFIG_MMC=y > CONFIG_MMC_SPI=y > CONFIG_RTC_CLASS=y Regards, Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra ` (3 preceding siblings ...) 2020-12-04 8:58 ` [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra @ 2020-12-04 8:58 ` Atish Patra 2020-12-10 11:08 ` Bin Meng 2020-12-22 3:19 ` [PATCH v3 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt 5 siblings, 1 reply; 16+ messages in thread From: Atish Patra @ 2020-12-04 8:58 UTC (permalink / raw) To: linux-kernel Cc: Conor Dooley, Albert Ou, Alistair Francis, Anup Patel, Atish Patra, Bin Meng, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara, Conor.Dooley From: Conor Dooley <conor.dooley@microchip.com> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC directory Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2daa6ee673f7..cccb7d6c58aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14989,6 +14989,14 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT +M: Lewis Hanly <lewis.hanly@microchip.com> +M: Cyril Jean <cyril.jean@microchip.com> +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/soc/microchip/ +F: include/soc/microchip/mpfs.h + RNBD BLOCK DRIVERS M: Danil Kipnis <danil.kipnis@cloud.ionos.com> M: Jack Wang <jinpu.wang@cloud.ionos.com> -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support 2020-12-04 8:58 ` [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra @ 2020-12-10 11:08 ` Bin Meng 0 siblings, 0 replies; 16+ messages in thread From: Bin Meng @ 2020-12-10 11:08 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Conor Dooley, Albert Ou, Alistair Francis, Anup Patel, Bin Meng, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Ivan.Griffin, Cyril.Jean, Daire McNamara On Fri, Dec 4, 2020 at 5:07 PM Atish Patra <atish.patra@wdc.com> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC > directory > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > MAINTAINERS | 8 ++++++++ > 1 file changed, 8 insertions(+) > Reviewed-by: Bin Meng <bin.meng@windriver.com> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/5] Add Microchip PolarFire Soc Support 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra ` (4 preceding siblings ...) 2020-12-04 8:58 ` [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra @ 2020-12-22 3:19 ` Palmer Dabbelt 2020-12-22 20:14 ` Atish Patra 5 siblings, 1 reply; 16+ messages in thread From: Palmer Dabbelt @ 2020-12-22 3:19 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Atish Patra, aou, Alistair Francis, Anup Patel, bin.meng, devicetree, linux-riscv, Paul Walmsley, robh+dt, Ivan.Griffin, Cyril.Jean, daire.mcnamara, Conor.Dooley On Fri, 04 Dec 2020 00:58:30 PST (-0800), Atish Patra wrote: > This series adds minimal support for Microchip Polar Fire Soc Icicle kit. > It is rebased on v5.10-rc6 and depends on clock support. > Only MMC and ethernet drivers are enabled via this series. > The idea here is to add the foundational patches so that other drivers > can be added to on top of this. The device tree may change based on > feedback on bindings of individual driver support patches. > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. > The following qemu series is necessary to test it on Qemu. > > The series can also be found at. > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v3 > > I noticed the latest version of mmc driver[2] hangs on the board with > the latest clock driver. That's why, I have tested with the old clock > driver available in the above github repo. IIRC the previous version was an RFC, but this is a PATCH. I'd be generally happy to take it on for-next, but I don't want to merge something that doesn't boot and that I don't have any way to fix (I don't have one of the boards yet). > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html > [2] https://www.spinics.net/lists/devicetree/msg383626.html > > Changes from v2->v3: > 1. Fixed a typo in dt binding. > 2. Included MAINTAINERS entry for PolarFire SoC. > 3. Improved the dts file by using lowercase clock names and keeping phy > details in board specific dts file. > > Changes from v1->v2: > 1. Modified the DT to match the device tree in U-Boot. > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled > as it allows larger storage option for linux distros. > > Atish Patra (4): > RISC-V: Add Microchip PolarFire SoC kconfig option > dt-bindings: riscv: microchip: Add YAML documentation for the > PolarFire SoC > RISC-V: Initial DTS for Microchip ICICLE board > RISC-V: Enable Microchip PolarFire ICICLE SoC > > Conor Dooley (1): > MAINTAINERS: add microchip polarfire soc support > > .../devicetree/bindings/riscv/microchip.yaml | 28 ++ > MAINTAINERS | 8 + > arch/riscv/Kconfig.socs | 7 + > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ > arch/riscv/configs/defconfig | 4 + > 8 files changed, 453 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/5] Add Microchip PolarFire Soc Support 2020-12-22 3:19 ` [PATCH v3 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt @ 2020-12-22 20:14 ` Atish Patra 0 siblings, 0 replies; 16+ messages in thread From: Atish Patra @ 2020-12-22 20:14 UTC (permalink / raw) To: Daire McNamara Cc: Atish Patra, devicetree, Conor.Dooley, Anup Patel, Cyril.Jean, Bin Meng, linux-kernel@vger.kernel.org List, Rob Herring, Ivan.Griffin, Albert Ou, Alistair Francis, Paul Walmsley, linux-riscv, Palmer Dabbelt On Mon, Dec 21, 2020 at 7:19 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Fri, 04 Dec 2020 00:58:30 PST (-0800), Atish Patra wrote: > > This series adds minimal support for Microchip Polar Fire Soc Icicle kit. > > It is rebased on v5.10-rc6 and depends on clock support. > > Only MMC and ethernet drivers are enabled via this series. > > The idea here is to add the foundational patches so that other drivers > > can be added to on top of this. The device tree may change based on > > feedback on bindings of individual driver support patches. > > > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. > > The following qemu series is necessary to test it on Qemu. > > > > The series can also be found at. > > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v3 > > > > I noticed the latest version of mmc driver[2] hangs on the board with > > the latest clock driver. That's why, I have tested with the old clock > > driver available in the above github repo. > > IIRC the previous version was an RFC, but this is a PATCH. I'd be generally > happy to take it on for-next, but I don't want to merge something that doesn't > boot and that I don't have any way to fix (I don't have one of the boards yet). > Fair enough. We can wait for clock patches to be merged before merging this series. > > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html > > [2] https://www.spinics.net/lists/devicetree/msg383626.html > > > > Changes from v2->v3: > > 1. Fixed a typo in dt binding. > > 2. Included MAINTAINERS entry for PolarFire SoC. > > 3. Improved the dts file by using lowercase clock names and keeping phy > > details in board specific dts file. > > > > Changes from v1->v2: > > 1. Modified the DT to match the device tree in U-Boot. > > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled > > as it allows larger storage option for linux distros. > > > > Atish Patra (4): > > RISC-V: Add Microchip PolarFire SoC kconfig option > > dt-bindings: riscv: microchip: Add YAML documentation for the > > PolarFire SoC > > RISC-V: Initial DTS for Microchip ICICLE board > > RISC-V: Enable Microchip PolarFire ICICLE SoC > > > > Conor Dooley (1): > > MAINTAINERS: add microchip polarfire soc support > > > > .../devicetree/bindings/riscv/microchip.yaml | 28 ++ > > MAINTAINERS | 8 + > > arch/riscv/Kconfig.socs | 7 + > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ > > arch/riscv/configs/defconfig | 4 + > > 8 files changed, 453 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv @Daire McNamara Do you have a v2 of the clock patch series that works with the latest upstream. -- Regards, Atish ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-01-07 19:26 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra 2020-12-04 8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra 2021-01-07 11:39 ` Cyril.Jean 2021-01-07 19:21 ` Atish Patra 2020-12-04 8:58 ` [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra 2020-12-09 23:30 ` Rob Herring 2020-12-04 8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra 2020-12-10 11:06 ` Bin Meng 2021-01-07 11:43 ` Cyril.Jean 2021-01-07 19:26 ` Atish Patra 2020-12-04 8:58 ` [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra 2020-12-26 0:37 ` Aurelien Jarno 2020-12-04 8:58 ` [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra 2020-12-10 11:08 ` Bin Meng 2020-12-22 3:19 ` [PATCH v3 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt 2020-12-22 20:14 ` Atish Patra
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