* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number [not found] <loom.20160602T084340-509@post.gmane.org> @ 2016-08-17 17:20 ` Sean Paul 2016-08-18 9:08 ` Mark yao 0 siblings, 1 reply; 9+ messages in thread From: Sean Paul @ 2016-08-17 17:20 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul resolved conflict with name change from _3066 to _3036] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Fix typo from _3066 _3036 (Tomasz Figa) drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 919992c..44caf14 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3036_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3036_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3036_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3036_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-17 17:20 ` [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number Sean Paul @ 2016-08-18 9:08 ` Mark yao 2016-08-18 9:11 ` Daniel Vetter 0 siblings, 1 reply; 9+ messages in thread From: Mark yao @ 2016-08-18 9:08 UTC (permalink / raw) To: Sean Paul, tfiga, dri-devel Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko Hi Sean Thanks for send v3 patch for rk3399 vop support. But sorry for that, I had changed my mind, those patches are deprecated, I have new rk3399 patch on my downstream kernel, I will upstream soon. Thanks. On 2016年08月18日 01:20, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > No functional changes, sort the vop registers to make > code more readable. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul resolved conflict with name change from _3066 to _3036] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Changes in v3: > - Fix typo from _3066 _3036 (Tomasz Figa) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > 1 file changed, 84 insertions(+), 84 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 919992c..44caf14 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3036_win_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win1_data = { > + .data_formats = formats_win_lite, > + .nformats = ARRAY_SIZE(formats_win_lite), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > +}; > + > +static const struct vop_win_data rk3036_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3036_win0_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x00, .phy = &rk3036_win1_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const int rk3036_vop_intrs[] = { > + DSP_HOLD_VALID_INTR, > + FS_INTR, > + LINE_FLAG_INTR, > + BUS_ERROR_INTR, > +}; > + > +static const struct vop_intr rk3036_intr = { > + .intrs = rk3036_vop_intrs, > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > +}; > + > +static const struct vop_ctrl rk3036_ctrl_data = { > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > +}; > + > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > + {RK3036_DSP_CTRL1, 0x00000000}, > +}; > + > +static const struct vop_data rk3036_vop = { > + .init_table = rk3036_vop_init_reg_table, > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > + .ctrl = &rk3036_ctrl_data, > + .intr = &rk3036_intr, > + .win = rk3036_vop_win_data, > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > +}; > + > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win0_data = { > - .scl = &rk3036_win_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win1_data = { > - .data_formats = formats_win_lite, > - .nformats = ARRAY_SIZE(formats_win_lite), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > -}; > - > -static const struct vop_win_data rk3036_vop_win_data[] = { > - { .base = 0x00, .phy = &rk3036_win0_data, > - .type = DRM_PLANE_TYPE_PRIMARY }, > - { .base = 0x00, .phy = &rk3036_win1_data, > - .type = DRM_PLANE_TYPE_CURSOR }, > -}; > - > -static const int rk3036_vop_intrs[] = { > - DSP_HOLD_VALID_INTR, > - FS_INTR, > - LINE_FLAG_INTR, > - BUS_ERROR_INTR, > -}; > - > -static const struct vop_intr rk3036_intr = { > - .intrs = rk3036_vop_intrs, > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > -}; > - > -static const struct vop_ctrl rk3036_ctrl_data = { > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > -}; > - > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > - {RK3036_DSP_CTRL1, 0x00000000}, > -}; > - > -static const struct vop_data rk3036_vop = { > - .init_table = rk3036_vop_init_reg_table, > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > - .ctrl = &rk3036_ctrl_data, > - .intr = &rk3036_intr, > - .win = rk3036_vop_win_data, > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > -}; > - > static const struct of_device_id vop_driver_dt_match[] = { > - { .compatible = "rockchip,rk3288-vop", > - .data = &rk3288_vop }, > { .compatible = "rockchip,rk3036-vop", > .data = &rk3036_vop }, > + { .compatible = "rockchip,rk3288-vop", > + .data = &rk3288_vop }, > {}, > }; > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- Ｍark Yao ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-18 9:08 ` Mark yao @ 2016-08-18 9:11 ` Daniel Vetter 2016-08-18 10:02 ` Mark yao 0 siblings, 1 reply; 9+ messages in thread From: Daniel Vetter @ 2016-08-18 9:11 UTC (permalink / raw) To: Mark yao Cc: Sean Paul, tfiga, dri-devel, linux-rockchip, linux-kernel, linux-arm-kernel On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: > Hi Sean > > Thanks for send v3 patch for rk3399 vop support. > > But sorry for that, I had changed my mind, those patches are deprecated, > I have new rk3399 patch on my downstream kernel, I will upstream soon. Wut? Imo merge Sean's patch here, and then rebase your downstream patches on top of it. That you have a downstream tree which is out of sync with upstream shouldn't be a reason to stall upstream development. -Daniel > > Thanks. > > On 2016年08月18日 01:20, Sean Paul wrote: > > From: Mark Yao <mark.yao@rock-chips.com> > > > > No functional changes, sort the vop registers to make > > code more readable. > > > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > > [seanpaul resolved conflict with name change from _3066 to _3036] > > Signed-off-by: Sean Paul <seanpaul@chromium.org> > > --- > > > > Changes in v3: > > - Fix typo from _3066 _3036 (Tomasz Figa) > > > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > > 1 file changed, 84 insertions(+), 84 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > index 919992c..44caf14 100644 > > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > > DRM_FORMAT_BGR565, > > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win0_data = { > > + .scl = &rk3036_win_scl, > > + .data_formats = formats_win_full, > > + .nformats = ARRAY_SIZE(formats_win_full), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win1_data = { > > + .data_formats = formats_win_lite, > > + .nformats = ARRAY_SIZE(formats_win_lite), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > +}; > > + > > +static const struct vop_win_data rk3036_vop_win_data[] = { > > + { .base = 0x00, .phy = &rk3036_win0_data, > > + .type = DRM_PLANE_TYPE_PRIMARY }, > > + { .base = 0x00, .phy = &rk3036_win1_data, > > + .type = DRM_PLANE_TYPE_CURSOR }, > > +}; > > + > > +static const int rk3036_vop_intrs[] = { > > + DSP_HOLD_VALID_INTR, > > + FS_INTR, > > + LINE_FLAG_INTR, > > + BUS_ERROR_INTR, > > +}; > > + > > +static const struct vop_intr rk3036_intr = { > > + .intrs = rk3036_vop_intrs, > > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > +}; > > + > > +static const struct vop_ctrl rk3036_ctrl_data = { > > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > +}; > > + > > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > + {RK3036_DSP_CTRL1, 0x00000000}, > > +}; > > + > > +static const struct vop_data rk3036_vop = { > > + .init_table = rk3036_vop_init_reg_table, > > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > + .ctrl = &rk3036_ctrl_data, > > + .intr = &rk3036_intr, > > + .win = rk3036_vop_win_data, > > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > +}; > > + > > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win0_data = { > > - .scl = &rk3036_win_scl, > > - .data_formats = formats_win_full, > > - .nformats = ARRAY_SIZE(formats_win_full), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win1_data = { > > - .data_formats = formats_win_lite, > > - .nformats = ARRAY_SIZE(formats_win_lite), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > -}; > > - > > -static const struct vop_win_data rk3036_vop_win_data[] = { > > - { .base = 0x00, .phy = &rk3036_win0_data, > > - .type = DRM_PLANE_TYPE_PRIMARY }, > > - { .base = 0x00, .phy = &rk3036_win1_data, > > - .type = DRM_PLANE_TYPE_CURSOR }, > > -}; > > - > > -static const int rk3036_vop_intrs[] = { > > - DSP_HOLD_VALID_INTR, > > - FS_INTR, > > - LINE_FLAG_INTR, > > - BUS_ERROR_INTR, > > -}; > > - > > -static const struct vop_intr rk3036_intr = { > > - .intrs = rk3036_vop_intrs, > > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > -}; > > - > > -static const struct vop_ctrl rk3036_ctrl_data = { > > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > -}; > > - > > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > - {RK3036_DSP_CTRL1, 0x00000000}, > > -}; > > - > > -static const struct vop_data rk3036_vop = { > > - .init_table = rk3036_vop_init_reg_table, > > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > - .ctrl = &rk3036_ctrl_data, > > - .intr = &rk3036_intr, > > - .win = rk3036_vop_win_data, > > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > -}; > > - > > static const struct of_device_id vop_driver_dt_match[] = { > > - { .compatible = "rockchip,rk3288-vop", > > - .data = &rk3288_vop }, > > { .compatible = "rockchip,rk3036-vop", > > .data = &rk3036_vop }, > > + { .compatible = "rockchip,rk3288-vop", > > + .data = &rk3288_vop }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); > > > -- > Ｍark Yao > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-18 9:11 ` Daniel Vetter @ 2016-08-18 10:02 ` Mark yao 2016-08-22 20:30 ` Sean Paul 0 siblings, 1 reply; 9+ messages in thread From: Mark yao @ 2016-08-18 10:02 UTC (permalink / raw) To: Sean Paul, tfiga, dri-devel, linux-rockchip, linux-kernel, linux-arm-kernel On 2016年08月18日 17:11, Daniel Vetter wrote: > On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >> >Hi Sean >> > >> >Thanks for send v3 patch for rk3399 vop support. >> > >> >But sorry for that, I had changed my mind, those patches are deprecated, >> >I have new rk3399 patch on my downstream kernel, I will upstream soon. > Wut? Imo merge Sean's patch here, and then rebase your downstream patches > on top of it. That you have a downstream tree which is out of sync with > upstream shouldn't be a reason to stall upstream development. > -Daniel > Yeah, Sorry for that. In fact, on my downstream kernel, also have those patches, my new rk3399 patches are based on them, but the new rk3399 patches will cover the those patches, Sean's patches is old version. I just want to fast forward, don't want to send two version drivers to upstream. but if you and Dave feel ok for that, I have no problem:-) . merged Sean's patches and then apply new version patches. Thanks. -- Ｍark Yao ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-18 10:02 ` Mark yao @ 2016-08-22 20:30 ` Sean Paul 2016-08-23 0:40 ` Mark yao 0 siblings, 1 reply; 9+ messages in thread From: Sean Paul @ 2016-08-22 20:30 UTC (permalink / raw) To: Mark yao Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月18日 17:11, Daniel Vetter wrote: >> >> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>> >>> >Hi Sean >>> > >>> >Thanks for send v3 patch for rk3399 vop support. >>> > >>> >But sorry for that, I had changed my mind, those patches are deprecated, >>> >I have new rk3399 patch on my downstream kernel, I will upstream soon. >> >> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >> on top of it. That you have a downstream tree which is out of sync with >> upstream shouldn't be a reason to stall upstream development. >> -Daniel >> > Yeah, Sorry for that. > > In fact, on my downstream kernel, also have those patches, my new rk3399 > patches are based on them, > but the new rk3399 patches will cover the those patches, Sean's patches is > old version. > > I just want to fast forward, don't want to send two version drivers to > upstream. > but if you and Dave feel ok for that, I have no problem:-) . > > merged Sean's patches and then apply new version patches. > Ok, so can I get a review/ack for these revised patches then? Something is better than nothing, and there's a bunch of stuff that depends on these changes. Sean > Thanks. > > -- > Ｍark Yao > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-22 20:30 ` Sean Paul @ 2016-08-23 0:40 ` Mark yao 2016-08-23 13:13 ` Sean Paul 0 siblings, 1 reply; 9+ messages in thread From: Mark yao @ 2016-08-23 0:40 UTC (permalink / raw) To: Sean Paul Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On 2016年08月23日 04:30, Sean Paul wrote: > On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016年08月18日 17:11, Daniel Vetter wrote: >>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>> Hi Sean >>>>> >>>>> Thanks for send v3 patch for rk3399 vop support. >>>>> >>>>> But sorry for that, I had changed my mind, those patches are deprecated, >>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >>> on top of it. That you have a downstream tree which is out of sync with >>> upstream shouldn't be a reason to stall upstream development. >>> -Daniel >>> >> Yeah, Sorry for that. >> >> In fact, on my downstream kernel, also have those patches, my new rk3399 >> patches are based on them, >> but the new rk3399 patches will cover the those patches, Sean's patches is >> old version. >> >> I just want to fast forward, don't want to send two version drivers to >> upstream. >> but if you and Dave feel ok for that, I have no problem:-) . >> >> merged Sean's patches and then apply new version patches. >> > Ok, so can I get a review/ack for these revised patches then? > Something is better than nothing, and there's a bunch of stuff that > depends on these changes. > > Sean Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost patches use v2 version? > > >> Thanks. >> >> -- >> Ｍark Yao >> >> > > -- Ｍark Yao ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-23 0:40 ` Mark yao @ 2016-08-23 13:13 ` Sean Paul 2016-08-25 2:25 ` Mark yao 0 siblings, 1 reply; 9+ messages in thread From: Sean Paul @ 2016-08-23 13:13 UTC (permalink / raw) To: Mark yao Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月23日 04:30, Sean Paul wrote: >> >> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>> >>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>> >>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>> >>>>>> Hi Sean >>>>>> >>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>> >>>>>> But sorry for that, I had changed my mind, those patches are >>>>>> deprecated, >>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>> >>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>> patches >>>> on top of it. That you have a downstream tree which is out of sync with >>>> upstream shouldn't be a reason to stall upstream development. >>>> -Daniel >>>> >>> Yeah, Sorry for that. >>> >>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>> patches are based on them, >>> but the new rk3399 patches will cover the those patches, Sean's patches >>> is >>> old version. >>> >>> I just want to fast forward, don't want to send two version drivers to >>> upstream. >>> but if you and Dave feel ok for that, I have no problem:-) . >>> >>> merged Sean's patches and then apply new version patches. >>> >> Ok, so can I get a review/ack for these revised patches then? >> Something is better than nothing, and there's a bunch of stuff that >> depends on these changes. >> >> Sean > > Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost > patches use v2 version? > Yes, v2 4/5 was reviewed as-is, so I just applied it. Sean > >> >> >>> Thanks. >>> >>> -- >>> Ｍark Yao >>> >>> >> >> > > > -- > Ｍark Yao > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-23 13:13 ` Sean Paul @ 2016-08-25 2:25 ` Mark yao [not found] ` <CAOw6vbJi+yV11npBZYi2MHTccSL_0HuuxGidLhmwjV--U6q-wQ@mail.gmail.com> 0 siblings, 1 reply; 9+ messages in thread From: Mark yao @ 2016-08-25 2:25 UTC (permalink / raw) To: Sean Paul Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On 2016年08月23日 21:13, Sean Paul wrote: > On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016年08月23日 04:30, Sean Paul wrote: >>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>> Hi Sean >>>>>>> >>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>> >>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>> deprecated, >>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>> patches >>>>> on top of it. That you have a downstream tree which is out of sync with >>>>> upstream shouldn't be a reason to stall upstream development. >>>>> -Daniel >>>>> >>>> Yeah, Sorry for that. >>>> >>>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>>> patches are based on them, >>>> but the new rk3399 patches will cover the those patches, Sean's patches >>>> is >>>> old version. >>>> >>>> I just want to fast forward, don't want to send two version drivers to >>>> upstream. >>>> but if you and Dave feel ok for that, I have no problem:-) . >>>> >>>> merged Sean's patches and then apply new version patches. >>>> >>> Ok, so can I get a review/ack for these revised patches then? >>> Something is better than nothing, and there's a bunch of stuff that >>> depends on these changes. >>> >>> Sean >> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost >> patches use v2 version? >> > Yes, v2 4/5 was reviewed as-is, so I just applied it. > > Sean Applied this series to my drm-next. Thanks. >>> >>>> Thanks. >>>> >>>> -- >>>> Ｍark Yao >>>> >>>> >>> >> >> -- >> Ｍark Yao >> >> > > -- Ｍark Yao ^ permalink raw reply [flat|nested] 9+ messages in thread
[parent not found: <CAOw6vbJi+yV11npBZYi2MHTccSL_0HuuxGidLhmwjV--U6q-wQ@mail.gmail.com>]
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number [not found] ` <CAOw6vbJi+yV11npBZYi2MHTccSL_0HuuxGidLhmwjV--U6q-wQ@mail.gmail.com> @ 2016-08-25 17:17 ` Sean Paul 0 siblings, 0 replies; 9+ messages in thread From: Sean Paul @ 2016-08-25 17:17 UTC (permalink / raw) To: Mark yao Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On Thu, Aug 25, 2016 at 1:15 PM, Sean Paul <seanpaul@chromium.org> wrote: > > > On Wed, Aug 24, 2016 at 10:25 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> >> On 2016年08月23日 21:13, Sean Paul wrote: >>> >>> On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> >>> wrote: >>>> >>>> On 2016年08月23日 04:30, Sean Paul wrote: >>>>> >>>>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> >>>>> wrote: >>>>>> >>>>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>>>> >>>>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>>>> >>>>>>>>> Hi Sean >>>>>>>>> >>>>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>>>> >>>>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>>>> deprecated, >>>>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream >>>>>>>>> soon. >>>>>>> >>>>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>>>> patches >>>>>>> on top of it. That you have a downstream tree which is out of sync >>>>>>> with >>>>>>> upstream shouldn't be a reason to stall upstream development. >>>>>>> -Daniel >>>>>>> >>>>>> Yeah, Sorry for that. >>>>>> >>>>>> In fact, on my downstream kernel, also have those patches, my new >>>>>> rk3399 >>>>>> patches are based on them, >>>>>> but the new rk3399 patches will cover the those patches, Sean's >>>>>> patches >>>>>> is >>>>>> old version. >>>>>> >>>>>> I just want to fast forward, don't want to send two version drivers to >>>>>> upstream. >>>>>> but if you and Dave feel ok for that, I have no problem:-) . >>>>>> >>>>>> merged Sean's patches and then apply new version patches. >>>>>> >>>>> Ok, so can I get a review/ack for these revised patches then? >>>>> Something is better than nothing, and there's a bunch of stuff that >>>>> depends on these changes. >>>>> >>>>> Sean >>>> >>>> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the >>>> lost >>>> patches use v2 version? >>>> >>> Yes, v2 4/5 was reviewed as-is, so I just applied it. >>> >>> Sean >> >> Applied this series to my drm-next. >> > > You should probably just rebase your downstream kernel on top of my branch > here: https://cgit.freedesktop.org/~seanpaul/dogwood/log/?h=for-next > Resending in plain text. Sean > Sean > > >> Thanks. >> >> >>>>> >>>>>> Thanks. >>>>>> >>>>>> -- >>>>>> Ｍark Yao >>>>>> >>>>>> >>>>> >>>> >>>> -- >>>> Ｍark Yao >>>> >>>> >>> >>> >> >> >> -- >> Ｍark Yao >> >> > ^ permalink raw reply [flat|nested] 9+ messages in thread
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2016-08-17 17:20 ` [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number Sean Paul
2016-08-18 9:08 ` Mark yao
2016-08-18 9:11 ` Daniel Vetter
2016-08-18 10:02 ` Mark yao
2016-08-22 20:30 ` Sean Paul
2016-08-23 0:40 ` Mark yao
2016-08-23 13:13 ` Sean Paul
2016-08-25 2:25 ` Mark yao
[not found] ` <CAOw6vbJi+yV11npBZYi2MHTccSL_0HuuxGidLhmwjV--U6q-wQ@mail.gmail.com>
2016-08-25 17:17 ` Sean Paul
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