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From: Ulf Hansson <ulf.hansson@linaro.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: "Raju P.L.S.S.S.N" <rplsssn@codeaurora.org>,
	Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Kevin Hilman <khilman@kernel.org>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	linux-soc@vger.kernel.org, Rajendra Nayak <rnayak@codeaurora.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux PM <linux-pm@vger.kernel.org>,
	DTML <devicetree@vger.kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Evan Green <evgreen@chromium.org>,
	Doug Anderson <dianders@chromium.org>,
	mka@chromium.org, Lina Iyer <ilina@codeaurora.org>
Subject: Re: [PATCH RFC v1 4/8] drivers: qcom: cpu_pd: add cpu power domain support using genpd
Date: Fri, 12 Oct 2018 11:23:10 +0200	[thread overview]
Message-ID: <CAPDyKFoVv99HN080p_pV_Qbmrk9Jeq3kgYBrpTToP6jwuaUo5A@mail.gmail.com> (raw)
In-Reply-To: <20181011155956.GA28583@e107155-lin>

On 11 October 2018 at 17:59, Sudeep Holla <sudeep.holla@arm.com> wrote:
> On Thu, Oct 11, 2018 at 05:27:59PM +0200, Ulf Hansson wrote:
>> On 11 October 2018 at 13:13, Sudeep Holla <sudeep.holla@arm.com> wrote:
>> > On Thu, Oct 11, 2018 at 02:50:51AM +0530, Raju P.L.S.S.S.N wrote:
>> >> RPMH based targets require that the sleep and wake state request votes
>> >> be sent during system low power mode entry. The votes help reduce the
>> >> power consumption when the AP is not using them. The votes sent by the
>> >> clients are cached in RPMH controller and needs to be flushed when the
>> >> last cpu enters low power mode. So add cpu power domain using Linux
>> >> generic power domain infrastructure to perform necessary tasks as part
>> >> of domain power down.
>> >>
>> >
>> > You seem to have either randomly chosen just 3 patches from Lina/Ulf's
>> > CPU genpd series or this series doesn't entirely depend on it ?
>>
>> Yep, it not easy to follow. But I do understand what you are trying to do here.
>>
>> >
>> > If latter, how does this work with PSCI CPU_SUSPEND operations ?
>> >
>> > And why this can be part of PSCI firmware implementation. Only PSCI
>> > firmware needs if RPMH votes need to be flushed or not. So, honestly
>> > I don't see the need for this in Linux.
>>
>> I do think there is clear need for this in Linux. More precisely,
>> since the PSCI firmware have knowledge solely about CPUs (and clusters
>> of CPUs), but not about other shared resources/devices present on the
>> SoC.
>>
>
> I disagree. Even with OSI, you indicate the cluster power off though
> PSCI CPU_SUSPEND call. If for any async wakeup reasons, firmware decides
> not to enter cluster OFF, then it may skip flushing RPMH vote. So doing
> it in PSCI is more correct and elegant to avoid such corner cases.
>
>> What Raju is trying to do here, is to manage those resources which
>> needs special treatment, before and after the CPU (likely cluster) is
>> going idle and returns from idle.
>>
>
> OK I get that, but why is Linux better than PSCI. I have my reasoning
> above.

I assume Lina, in the other thread from Raju, have provided you the
details why PSCI is not the place to do this and why Linux need to be
involved. In any case, let's continue that discussion in that thread
rather than here.

>
>> One question here though, what particular idle state is relevant for
>> the QCOM SoC to take last-man-actions for? I assume it's only cluster
>> idle states, and not about cpu idle states, no? Raju, can you please
>> clarify?
>>
>
> I assume so. I did see some comment or commit message to indicate the
> same.
>
>> Historically, the typical solution have been to use the
>> cpu_cluster_pm_enter|exit() notifiers. Those could potentially be
>> replaced by instead building a hierarchical topology, using
>> master/subdomain of genpd/"power-domains", along the lines of what
>> Raju is doing. However, I am not sure if that is the correct approach,
>> at least we need to make sure it models the HW in DT correctly.
>>
>
> Indeed. I am not sure how to represent both PSCI and this power domains ?
> Though I believe the latter is not required at all.

After my re-work of the PSCI power domain series, I believe the
power-domain that Raju is adding, should then be modeled as the master
power-domain of the PSCI *cluster* power domain. But, as stated, I am
not sure if it's the correct way to model the HW/topology. Maybe it
is.

The other option is to explore the cpu_cluster_pm_enter|exit(), which
today is the only viable solution in the kernel. In principle we then
need to call cpu_cluster_pm_enter() from the PSCI's cluster PM domain
genpd ->power_off() callback, and cpu_cluster_pm_exit() from the
->power_on() callback.

Or maybe we simply need something entirely new, like genpd PM
domain-on/off notifiers, which may scale better. It has even been
suggested on the mailing list, long time ago.

Kind regards
Uffe

  reply	other threads:[~2018-10-12  9:23 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-10 21:20 [PATCH RFC v1 0/8] drivers: qcom: Add cpu power domain for SDM845 Raju P.L.S.S.S.N
2018-10-10 21:20 ` [PATCH RFC v1 1/8] PM / Domains: Add helper functions to attach/detach CPUs to/from genpd Raju P.L.S.S.S.N
2018-10-10 21:20 ` [PATCH RFC v1 2/8] kernel/cpu_pm: Manage runtime PM in the idle path for CPUs Raju P.L.S.S.S.N
2018-10-11 20:52   ` Rafael J. Wysocki
2018-10-11 22:08     ` Lina Iyer
2018-10-12  7:43       ` Rafael J. Wysocki
2018-10-12 10:20         ` Ulf Hansson
2018-10-12 15:20         ` Lina Iyer
2018-10-10 21:20 ` [PATCH RFC v1 3/8] timer: Export next wakeup time of a CPU Raju P.L.S.S.S.N
2018-10-29 22:36   ` Thomas Gleixner
2018-10-30 10:29     ` Ulf Hansson
2018-10-10 21:20 ` [PATCH RFC v1 4/8] drivers: qcom: cpu_pd: add cpu power domain support using genpd Raju P.L.S.S.S.N
2018-10-11 11:13   ` Sudeep Holla
2018-10-11 15:27     ` Ulf Hansson
2018-10-11 15:59       ` Sudeep Holla
2018-10-12  9:23         ` Ulf Hansson [this message]
2018-10-12 14:33   ` Sudeep Holla
2018-10-12 18:01     ` Raju P L S S S N
2018-10-10 21:20 ` [PATCH RFC v1 5/8] dt-bindings: introduce cpu power domain bindings for Qualcomm SoCs Raju P.L.S.S.S.N
2018-10-11 11:08   ` Sudeep Holla
2018-10-12 18:08     ` Raju P L S S S N
2018-10-10 21:20 ` [PATCH RFC v1 6/8] drivers: qcom: cpu_pd: program next wakeup to PDC timer Raju P.L.S.S.S.N
2018-10-10 21:20 ` [PATCH RFC v1 7/8] drivers: qcom: cpu_pd: Handle cpu hotplug in the domain Raju P.L.S.S.S.N
2018-10-11 11:20   ` Sudeep Holla
2018-10-11 16:00     ` Lina Iyer
2018-10-11 16:19       ` Sudeep Holla
2018-10-11 16:58         ` Lina Iyer
2018-10-11 17:37           ` Sudeep Holla
2018-10-11 21:06             ` Lina Iyer
2018-10-12 15:04               ` Sudeep Holla
2018-10-12 15:46                 ` Ulf Hansson
2018-10-12 16:16                   ` Lina Iyer
2018-10-12 16:33                   ` Sudeep Holla
2018-10-12 16:04                 ` Lina Iyer
2018-10-12 17:00                   ` Sudeep Holla
2018-10-12 17:19                     ` Lina Iyer
2018-10-12 17:25                       ` Sudeep Holla
2018-10-22 19:50                         ` Lina Iyer
2018-10-12 14:25   ` Sudeep Holla
2018-10-12 18:10     ` Raju P L S S S N
2018-10-10 21:20 ` [PATCH RFC v1 8/8] arm64: dtsi: sdm845: Add cpu power domain support Raju P.L.S.S.S.N
2018-10-12 17:35   ` Sudeep Holla
2018-10-12 17:52     ` Lina Iyer

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