* [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards compatibility issue at DDR50 mode
@ 2022-07-29 10:05 Chevron Li
2022-07-29 10:21 ` Adrian Hunter
2022-08-15 18:27 ` Ulf Hansson
0 siblings, 2 replies; 3+ messages in thread
From: Chevron Li @ 2022-07-29 10:05 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, linux-mmc, linux-kernel
Cc: shaper.liu, shirley.her, xiaoguang.yu
Bayhub chips have better compatibility support for SDR50 than DDR50
and both mode have the same R/W performance when clock frequency >= 100MHz.
Disable DDR50 mode and use SDR50 instead.
Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
---
Changes on V1:
1.Set quirks2 flag SDHCI_QUIRK2_BROKEN_DDR50 for bayhub chips.
2.Use bayhub hardware input tuning for SDR50 mode instead of standard tuning flow.
Changes on V2:
Update commit format and information.
---
drivers/mmc/host/sdhci-pci-o2micro.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index 0d4d343dbb77..ad457cd9cbaa 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -317,11 +317,12 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
u32 reg_val;
/*
- * This handler only implements the eMMC tuning that is specific to
+ * This handler implements the hardware tuning that is specific to
* this controller. Fall back to the standard method for other TIMING.
*/
if ((host->timing != MMC_TIMING_MMC_HS200) &&
- (host->timing != MMC_TIMING_UHS_SDR104))
+ (host->timing != MMC_TIMING_UHS_SDR104) &&
+ (host->timing != MMC_TIMING_UHS_SDR50))
return sdhci_execute_tuning(mmc, opcode);
if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
@@ -631,6 +632,8 @@ static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
if (reg & 0x1)
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
+ host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
+
sdhci_pci_o2_enable_msi(chip, host);
if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
base-commit: 68e77ffbfd06ae3ef8f2abf1c3b971383c866983
--
2.32.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards compatibility issue at DDR50 mode
2022-07-29 10:05 [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards compatibility issue at DDR50 mode Chevron Li
@ 2022-07-29 10:21 ` Adrian Hunter
2022-08-15 18:27 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Adrian Hunter @ 2022-07-29 10:21 UTC (permalink / raw)
To: Chevron Li, ulf.hansson, linux-mmc, linux-kernel
Cc: shaper.liu, shirley.her, xiaoguang.yu
On 29/07/22 13:05, Chevron Li wrote:
> Bayhub chips have better compatibility support for SDR50 than DDR50
> and both mode have the same R/W performance when clock frequency >= 100MHz.
> Disable DDR50 mode and use SDR50 instead.
>
> Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> Changes on V1:
> 1.Set quirks2 flag SDHCI_QUIRK2_BROKEN_DDR50 for bayhub chips.
> 2.Use bayhub hardware input tuning for SDR50 mode instead of standard tuning flow.
>
> Changes on V2:
> Update commit format and information.
> ---
> drivers/mmc/host/sdhci-pci-o2micro.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 0d4d343dbb77..ad457cd9cbaa 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -317,11 +317,12 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
> u32 reg_val;
>
> /*
> - * This handler only implements the eMMC tuning that is specific to
> + * This handler implements the hardware tuning that is specific to
> * this controller. Fall back to the standard method for other TIMING.
> */
> if ((host->timing != MMC_TIMING_MMC_HS200) &&
> - (host->timing != MMC_TIMING_UHS_SDR104))
> + (host->timing != MMC_TIMING_UHS_SDR104) &&
> + (host->timing != MMC_TIMING_UHS_SDR50))
> return sdhci_execute_tuning(mmc, opcode);
>
> if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
> @@ -631,6 +632,8 @@ static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
> if (reg & 0x1)
> host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
>
> + host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
> +
> sdhci_pci_o2_enable_msi(chip, host);
>
> if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
>
> base-commit: 68e77ffbfd06ae3ef8f2abf1c3b971383c866983
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards compatibility issue at DDR50 mode
2022-07-29 10:05 [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards compatibility issue at DDR50 mode Chevron Li
2022-07-29 10:21 ` Adrian Hunter
@ 2022-08-15 18:27 ` Ulf Hansson
1 sibling, 0 replies; 3+ messages in thread
From: Ulf Hansson @ 2022-08-15 18:27 UTC (permalink / raw)
To: Chevron Li
Cc: adrian.hunter, linux-mmc, linux-kernel, shaper.liu, shirley.her,
xiaoguang.yu
On Fri, 29 Jul 2022 at 12:05, Chevron Li <chevron.li@bayhubtech.com> wrote:
>
> Bayhub chips have better compatibility support for SDR50 than DDR50
> and both mode have the same R/W performance when clock frequency >= 100MHz.
> Disable DDR50 mode and use SDR50 instead.
>
> Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Changes on V1:
> 1.Set quirks2 flag SDHCI_QUIRK2_BROKEN_DDR50 for bayhub chips.
> 2.Use bayhub hardware input tuning for SDR50 mode instead of standard tuning flow.
>
> Changes on V2:
> Update commit format and information.
> ---
> drivers/mmc/host/sdhci-pci-o2micro.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 0d4d343dbb77..ad457cd9cbaa 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -317,11 +317,12 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
> u32 reg_val;
>
> /*
> - * This handler only implements the eMMC tuning that is specific to
> + * This handler implements the hardware tuning that is specific to
> * this controller. Fall back to the standard method for other TIMING.
> */
> if ((host->timing != MMC_TIMING_MMC_HS200) &&
> - (host->timing != MMC_TIMING_UHS_SDR104))
> + (host->timing != MMC_TIMING_UHS_SDR104) &&
> + (host->timing != MMC_TIMING_UHS_SDR50))
> return sdhci_execute_tuning(mmc, opcode);
>
> if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
> @@ -631,6 +632,8 @@ static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
> if (reg & 0x1)
> host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
>
> + host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
> +
> sdhci_pci_o2_enable_msi(chip, host);
>
> if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
>
> base-commit: 68e77ffbfd06ae3ef8f2abf1c3b971383c866983
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-08-15 18:52 UTC | newest]
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2022-07-29 10:05 [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards compatibility issue at DDR50 mode Chevron Li
2022-07-29 10:21 ` Adrian Hunter
2022-08-15 18:27 ` Ulf Hansson
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