* [PATCH] mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V
@ 2018-06-28 7:31 Stefan Agner
2018-07-02 14:36 ` Ulf Hansson
0 siblings, 1 reply; 2+ messages in thread
From: Stefan Agner @ 2018-06-28 7:31 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson
Cc: fabio.estevam, haibo.chen, aisheng.dong, michael, linux-mmc,
linux-kernel, Stefan Agner
The uSDHC supports DDR modes for eMMC devices running at 3.3V. This
allows to run eMMC with 3.3V signaling voltage at DDR52 mode:
# cat /sys/kernel/debug/mmc1/ios
clock: 52000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 8 (mmc DDR52)
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index b716b933f00a..6f444731754d 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1324,7 +1324,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
if (esdhc_is_usdhc(imx_data)) {
host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
- host->mmc->caps |= MMC_CAP_1_8V_DDR;
+ host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
--
2.18.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V
2018-06-28 7:31 [PATCH] mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V Stefan Agner
@ 2018-07-02 14:36 ` Ulf Hansson
0 siblings, 0 replies; 2+ messages in thread
From: Ulf Hansson @ 2018-07-02 14:36 UTC (permalink / raw)
To: Stefan Agner
Cc: Adrian Hunter, Fabio Estevam, Haibo Chen, Aisheng Dong,
Michael Trimarchi, linux-mmc, Linux Kernel Mailing List
On 28 June 2018 at 09:31, Stefan Agner <stefan@agner.ch> wrote:
> The uSDHC supports DDR modes for eMMC devices running at 3.3V. This
> allows to run eMMC with 3.3V signaling voltage at DDR52 mode:
>
> # cat /sys/kernel/debug/mmc1/ios
> clock: 52000000 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 3 (8 bits)
> timing spec: 8 (mmc DDR52)
> signal voltage: 0 (3.30 V)
> driver type: 0 (driver type B)
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Thanks, applied for next!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index b716b933f00a..6f444731754d 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -1324,7 +1324,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
>
> if (esdhc_is_usdhc(imx_data)) {
> host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
> - host->mmc->caps |= MMC_CAP_1_8V_DDR;
> + host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
> if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
> host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
>
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2018-07-02 14:36 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-28 7:31 [PATCH] mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V Stefan Agner
2018-07-02 14:36 ` Ulf Hansson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).