From: Nitin Gupta <ngupta@vflare.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Andrew Morton <akpm@linux-foundation.org>,
Andy Lutomirski <luto@amacapital.net>,
Cyrill Gorcunov <gorcunov@openvz.org>,
Borislav Petkov <bp@suse.de>, linux-mm <linux-mm@kvack.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Minchan Kim <minchan@kernel.org>,
Sergey Senozhatsky <sergey.senozhatsky.work@gmail.com>
Subject: Re: [PATCH 2/6] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
Date: Fri, 13 Oct 2017 17:00:12 -0700 [thread overview]
Message-ID: <CAPkvG_c3=78Yd5kQOeZM_yiv89HowjEthhZtysoGmxcDZMwunQ@mail.gmail.com> (raw)
In-Reply-To: <20170929140821.37654-3-kirill.shutemov@linux.intel.com>
On Fri, Sep 29, 2017 at 7:08 AM, Kirill A. Shutemov
<kirill.shutemov@linux.intel.com> wrote:
> With boot-time switching between paging mode we will have variable
> MAX_PHYSMEM_BITS.
>
> Let's use the maximum variable possible for CONFIG_X86_5LEVEL=y
> configuration to define zsmalloc data structures.
>
> The patch introduces MAX_POSSIBLE_PHYSMEM_BITS to cover such case.
> It also suits well to handle PAE special case.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Cc: Minchan Kim <minchan@kernel.org>
> Cc: Nitin Gupta <ngupta@vflare.org>
> Cc: Sergey Senozhatsky <sergey.senozhatsky.work@gmail.com>
> ---
> arch/x86/include/asm/pgtable-3level_types.h | 1 +
> arch/x86/include/asm/pgtable_64_types.h | 2 ++
> mm/zsmalloc.c | 13 +++++++------
> 3 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/include/asm/pgtable-3level_types.h b/arch/x86/include/asm/pgtable-3level_types.h
> index b8a4341faafa..3fe1d107a875 100644
> --- a/arch/x86/include/asm/pgtable-3level_types.h
> +++ b/arch/x86/include/asm/pgtable-3level_types.h
> @@ -43,5 +43,6 @@ typedef union {
> */
> #define PTRS_PER_PTE 512
>
> +#define MAX_POSSIBLE_PHYSMEM_BITS 36
>
> #endif /* _ASM_X86_PGTABLE_3LEVEL_DEFS_H */
> diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
> index 06470da156ba..39075df30b8a 100644
> --- a/arch/x86/include/asm/pgtable_64_types.h
> +++ b/arch/x86/include/asm/pgtable_64_types.h
> @@ -39,6 +39,8 @@ typedef struct { pteval_t pte; } pte_t;
> #define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
> #define P4D_MASK (~(P4D_SIZE - 1))
>
> +#define MAX_POSSIBLE_PHYSMEM_BITS 52
> +
> #else /* CONFIG_X86_5LEVEL */
>
> /*
> diff --git a/mm/zsmalloc.c b/mm/zsmalloc.c
> index 7c38e850a8fc..7bde01c55c90 100644
> --- a/mm/zsmalloc.c
> +++ b/mm/zsmalloc.c
> @@ -82,18 +82,19 @@
> * This is made more complicated by various memory models and PAE.
> */
>
> -#ifndef MAX_PHYSMEM_BITS
> -#ifdef CONFIG_HIGHMEM64G
> -#define MAX_PHYSMEM_BITS 36
> -#else /* !CONFIG_HIGHMEM64G */
> +#ifndef MAX_POSSIBLE_PHYSMEM_BITS
> +#ifdef MAX_PHYSMEM_BITS
> +#define MAX_POSSIBLE_PHYSMEM_BITS MAX_PHYSMEM_BITS
> +#else
> /*
> * If this definition of MAX_PHYSMEM_BITS is used, OBJ_INDEX_BITS will just
> * be PAGE_SHIFT
> */
> -#define MAX_PHYSMEM_BITS BITS_PER_LONG
> +#define MAX_POSSIBLE_PHYSMEM_BITS BITS_PER_LONG
> #endif
> #endif
> -#define _PFN_BITS (MAX_PHYSMEM_BITS - PAGE_SHIFT)
> +
> +#define _PFN_BITS (MAX_POSSIBLE_PHYSMEM_BITS - PAGE_SHIFT)
>
I think we can avoid using this new constant in zsmalloc.
The reason for trying to save on MAX_PHYSMEM_BITS is just to gain more
bits for OBJ_INDEX_BITS which would reduce ZS_MIN_ALLOC_SIZE. However,
for all practical values of ZS_MAX_PAGES_PER_ZSPAGE, this min size
would remain 32 bytes.
So, we can unconditionally use MAX_PHYSMEM_BITS = BITS_PER_LONG and
thus OBJ_INDEX_BITS = PAGE_SHIFT.
- Nitin
next prev parent reply other threads:[~2017-10-14 0:00 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-29 14:08 [PATCH 0/6] Boot-time switching between 4- and 5-level paging for 4.15, Part 1 Kirill A. Shutemov
2017-09-29 14:08 ` [PATCH 1/6] mm/sparsemem: Allocate mem_section at runtime for SPARSEMEM_EXTREME Kirill A. Shutemov
2017-10-20 12:27 ` [tip:x86/mm] mm/sparsemem: Allocate mem_section at runtime for CONFIG_SPARSEMEM_EXTREME=y tip-bot for Kirill A. Shutemov
2017-11-02 12:31 ` Sudeep Holla
2017-11-02 13:34 ` Kirill A. Shutemov
2017-11-02 13:42 ` Sudeep Holla
2017-11-02 14:12 ` Kirill A. Shutemov
2017-11-02 15:07 ` Sudeep Holla
2017-11-02 15:37 ` Thierry Reding
2017-11-06 19:00 ` Bjorn Andersson
2017-11-07 1:15 ` Will Deacon
2017-09-29 14:08 ` [PATCH 2/6] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS Kirill A. Shutemov
2017-10-14 0:00 ` Nitin Gupta [this message]
2017-10-16 14:44 ` Kirill A. Shutemov
2017-10-18 23:39 ` Nitin Gupta
2017-09-29 14:08 ` [PATCH 3/6] x86/kasan: Use the same shadow offset for 4- and 5-level paging Kirill A. Shutemov
2017-10-20 12:28 ` [tip:x86/mm] " tip-bot for Andrey Ryabinin
2017-09-29 14:08 ` [PATCH 4/6] x86/xen: Provide pre-built page tables only for XEN_PV and XEN_PVH Kirill A. Shutemov
2017-10-20 12:28 ` [tip:x86/mm] x86/xen: Provide pre-built page tables only for CONFIG_XEN_PV=y and CONFIG_XEN_PVH=y tip-bot for Kirill A. Shutemov
2017-09-29 14:08 ` [PATCH 5/6] x86/xen: Drop 5-level paging support code from XEN_PV code Kirill A. Shutemov
2017-10-20 12:29 ` [tip:x86/mm] x86/xen: Drop 5-level paging support code from the " tip-bot for Kirill A. Shutemov
2017-09-29 14:08 ` [PATCH 6/6] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Kirill A. Shutemov
2017-10-03 8:27 ` [PATCH 0/6] Boot-time switching between 4- and 5-level paging for 4.15, Part 1 Kirill A. Shutemov
2017-10-17 15:42 ` Kirill A. Shutemov
2017-10-20 8:18 ` Ingo Molnar
2017-10-20 9:41 ` Kirill A. Shutemov
2017-10-20 15:23 ` Ingo Molnar
2017-10-20 16:23 ` Kirill A. Shutemov
2017-10-23 11:56 ` Ingo Molnar
2017-10-23 12:21 ` Kirill A. Shutemov
2017-10-23 12:40 ` Ingo Molnar
2017-10-23 12:48 ` Kirill A. Shutemov
2017-10-24 9:40 ` Ingo Molnar
2017-10-24 11:38 ` Kirill A. Shutemov
2017-10-24 12:47 ` Ingo Molnar
2017-10-24 13:12 ` Kirill A. Shutemov
2017-10-26 7:37 ` Ingo Molnar
2017-10-26 14:40 ` Kirill A. Shutemov
2017-10-31 9:47 ` Ingo Molnar
2017-10-31 12:04 ` Kirill A. Shutemov
2017-10-20 9:49 ` Minchan Kim
2017-10-20 12:18 ` Kirill A. Shutemov
2017-10-24 11:32 ` hpa
2017-10-24 11:43 ` Kirill A. Shutemov
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