From: "Sia, Jee Heng" <jee.heng.sia@intel.com>
To: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: "andriy.shevchenko@linux.intel.com"
<andriy.shevchenko@linux.intel.com>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>
Subject: RE: [PATCH v4 11/15] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Date: Fri, 20 Nov 2020 00:40:26 +0000 [thread overview]
Message-ID: <CO1PR11MB50264ED208E2BCB9F5BA8B68DAFF0@CO1PR11MB5026.namprd11.prod.outlook.com> (raw)
In-Reply-To: <MWHPR1201MB0029278F2808FB55CEB8B3D5DEE10@MWHPR1201MB0029.namprd12.prod.outlook.com>
> -----Original Message-----
> From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> Sent: 19 November 2020 7:58 AM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; vkoul@kernel.org;
> robh+dt@kernel.org
> Subject: Re: [PATCH v4 11/15] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA
> register fields
>
> Hi Sia,
>
> > Subject: [PATCH v4 11/15] dmaengine: dw-axi-dmac: Add Intel KeemBay
> > DMA register fields
> >
> > Add support for Intel KeemBay DMA registers. These registers are
> > required to run data transfer between device to memory and memory to
> > device on Intel KeemBay SoC.
> >
> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> > ---
> > drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++++
> > drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++++++++++++++
> > 2 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> > b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> > index 7c97b58206bf..9f7f908b89d8 100644
> > --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> > +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> > @@ -1192,6 +1192,10 @@ static int dw_probe(struct platform_device *pdev)
> > if (IS_ERR(chip->regs))
> > return PTR_ERR(chip->regs);
> >
> > + chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
> > + if (IS_ERR(chip->apb_regs))
> > + dev_warn(&pdev->dev, "apb_regs not supported\n");
>
> There shouldn't be warning in case of compatible = "snps,axi-dma-1.01a" and
> apb_regs missing. Could you please try to do ioremap for this region only in case of
> intel,kmb-axi-dma?
[>>] The intention is to fallback to snps solution in case of apb_reg missing. Yes, I can include the intel,kmb-axi-dma condition check if this is the prefer solution.
>
> > +
> > chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> > if (IS_ERR(chip->core_clk))
> > return PTR_ERR(chip->core_clk); diff --git
> > a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> > b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> > index bdb66d775125..f64e8d33b127 100644
> > --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> > +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> > @@ -63,6 +63,7 @@ struct axi_dma_chip {
> > struct device *dev;
> > int irq;
> > void __iomem *regs;
> > + void __iomem *apb_regs;
> > struct clk *core_clk;
> > struct clk *cfgr_clk;
> > struct dw_axi_dma *dw;
> > @@ -169,6 +170,19 @@ static inline struct axi_dma_chan
> *dchan_to_axi_dma_chan(struct dma_chan *dchan)
> > #define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
> > #define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
> >
> > +/* Apb slave registers */
> Could you please add the comment that all this registers exist only in case of
> intel,kmb-axi-dma extension?
[>>] OK, will include the comment in v5
>
> > +#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
> > +#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
> > +#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status
> > +Register 0 */ #define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug
> Status Register 1 */
> > +#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
> > +#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
> > +#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
> > +#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
> > +#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write
> enables */
> > +
> > +#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
> > +#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
> >
> > /* DMAC_CFG */
> > #define DMAC_EN_POS 0
> > --
> > 2.18.0
> >
next prev parent reply other threads:[~2020-11-20 0:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-17 2:22 [PATCH v4 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 01/15] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 02/15] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 03/15] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 04/15] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 05/15] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 06/15] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 07/15] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 08/15] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-11-19 0:10 ` Eugeniy Paltsev
2020-11-20 0:47 ` Sia, Jee Heng
2020-11-17 2:22 ` [PATCH v4 09/15] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 10/15] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 11/15] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2020-11-18 23:58 ` Eugeniy Paltsev
2020-11-20 0:40 ` Sia, Jee Heng [this message]
2020-11-17 2:22 ` [PATCH v4 12/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 13/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-11-18 23:59 ` Eugeniy Paltsev
2020-11-20 0:46 ` Sia, Jee Heng
2020-11-20 8:56 ` Sia, Jee Heng
2020-11-17 2:22 ` [PATCH v4 14/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
2020-11-17 2:22 ` [PATCH v4 15/15] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
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