[PATCH 1/3] mtd: spi-nor: Use write_sr for write status

[PATCH 1/3] mtd: spi-nor: Use write_sr for write status

[Jagan Teki]

Use existing write_sr() call instead of decoding and
calling nor->write_reg separately.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 47516d3..3e198b4 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -869,8 +869,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
 	val = read_sr(nor);
 	write_enable(nor);
 
-	nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
-	nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
+	write_sr(nor, val | SR_QUAD_EN_MX);
 
 	if (spi_nor_wait_till_ready(nor))
 		return 1;
-- 
1.9.1

[PATCH 2/3] mtd: spi-nor: Zap unneeded write_enable from write_reg

[Jagan Teki]

Since write enabling shall do with buf and len without
need of exctra write_enable argument, hence removed the
same from write_reg.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Han Xu <han.xu@freescale.com>
---
 drivers/mtd/devices/m25p80.c      |  3 +--
 drivers/mtd/spi-nor/fsl-quadspi.c |  3 +--
 drivers/mtd/spi-nor/spi-nor.c     | 16 ++++++++--------
 include/linux/mtd/spi-nor.h       |  3 +--
 4 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 9cd3631..ab69d2d 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -62,8 +62,7 @@ static int m25p_cmdsz(struct spi_nor *nor)
 	return 1 + nor->addr_width;
 }
 
-static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
-			int wr_en)
+static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 {
 	struct m25p *flash = nor->priv;
 	struct spi_device *spi = flash->spi;
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index d32b7e0..2c8c578 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -798,8 +798,7 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 	return 0;
 }
 
-static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
-			int write_enable)
+static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 {
 	struct fsl_qspi *q = nor->priv;
 	int ret;
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3e198b4..f954d03 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -143,7 +143,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
 static inline int write_sr(struct spi_nor *nor, u8 val)
 {
 	nor->cmd_buf[0] = val;
-	return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
+	return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
 }
 
 /*
@@ -152,7 +152,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val)
  */
 static inline int write_enable(struct spi_nor *nor)
 {
-	return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
+	return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 }
 
 /*
@@ -160,7 +160,7 @@ static inline int write_enable(struct spi_nor *nor)
  */
 static inline int write_disable(struct spi_nor *nor)
 {
-	return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
+	return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
 }
 
 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
@@ -186,7 +186,7 @@ static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
 			write_enable(nor);
 
 		cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
-		status = nor->write_reg(nor, cmd, NULL, 0, 0);
+		status = nor->write_reg(nor, cmd, NULL, 0);
 		if (need_wren)
 			write_disable(nor);
 
@@ -194,7 +194,7 @@ static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
 	default:
 		/* Spansion style */
 		nor->cmd_buf[0] = enable << 7;
-		return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
+		return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
 	}
 }
 static inline int spi_nor_sr_ready(struct spi_nor *nor)
@@ -265,7 +265,7 @@ static int erase_chip(struct spi_nor *nor)
 {
 	dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
 
-	return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
+	return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
 }
 
 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
@@ -894,7 +894,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val)
 	nor->cmd_buf[0] = val & 0xff;
 	nor->cmd_buf[1] = (val >> 8);
 
-	return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
+	return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
 }
 
 static int spansion_quad_enable(struct spi_nor *nor)
@@ -936,7 +936,7 @@ static int micron_quad_enable(struct spi_nor *nor)
 
 	/* set EVCR, enable quad I/O */
 	nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
-	ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
+	ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
 	if (ret < 0) {
 		dev_err(nor->dev, "error while writing EVCR register\n");
 		return ret;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index e540952..c5a58c4 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -182,8 +182,7 @@ struct spi_nor {
 	int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
 			  u8 *buf, size_t len);
 	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
-	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
-			int write_enable);
+	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 
 	int (*read)(struct spi_nor *nor, loff_t from,
 			size_t len, size_t *retlen, u_char *read_buf);
-- 
1.9.1

[PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Jagan Teki]

The clear flag status register operation was required by Micron
SPI-NOR chips, which support FSR. And if an error bit of FSR
have been set like protection, voltage, erase, and program,
it must be cleared by the clear FSR operation.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Hou Zhiqiang <B48286@freescale.com>
Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 35 +++++++++++++++++++++++++++++++----
 include/linux/mtd/spi-nor.h   |  9 +++++++++
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f954d03..c5c472d5 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)
 }
 
 /*
+ * Read the clear flag status register.
+ * The clear flag status register operation was required by Micron
+ * SPI-NOR chips, which support FSR. And if an error bit of FSR
+ * have been set like protection, voltage, erase, and program,
+ * it must be cleared by the clear FSR operation.
+ * Returns zero for FSR bits cleared and negative if error occurred.
+ */
+static int read_cfsr(struct spi_nor *nor)
+{
+	int ret;
+	u8 val;
+
+	ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);
+	if (ret < 0) {
+		pr_err("error %d reading CFSR\n", ret);
+		return ret;
+	}
+
+	return val;
+}
+
+/*
  * Read configuration register, returning its value in the
  * location. Return the configuration register value.
  * Returns negative if error occured.
@@ -209,10 +231,15 @@ static inline int spi_nor_sr_ready(struct spi_nor *nor)
 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
 {
 	int fsr = read_fsr(nor);
-	if (fsr < 0)
-		return fsr;
-	else
-		return fsr & FSR_READY;
+	if (fsr & FSR_ERR_MASK) {
+		pr_err("flag status(0x%x) error occured\n", fsr);
+		int cfsr = read_cfsr(nor);
+		if (cfsr < 0)
+			return cfsr;
+		return -1;
+	}
+
+	return fsr & FSR_READY;
 }
 
 static int spi_nor_ready(struct spi_nor *nor)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index c5a58c4..36c1681 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -35,6 +35,7 @@
 #define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
 #define SPINOR_OP_RDCR		0x35	/* Read configuration register */
 #define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
+#define SPINOR_OP_RDCFSR	0x50	/* Read clear flag status register */
 
 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
 #define SPINOR_OP_READ4		0x13	/* Read data bytes (low frequency) */
@@ -74,6 +75,14 @@
 /* Enhanced Volatile Configuration Register bits */
 #define EVCR_QUAD_EN_MICRON    0x80    /* Micron Quad I/O */
 
+/* Flag Status Register Error bits */
+#define FSR_ERR_PROT		0x2	/* Protection */
+#define FSR_ERR_VOLT		0x8	/* Voltage on Vpp */
+#define FSR_ERR_PROG		0x10	/* Program operation */
+#define FSR_ERR_ERASE		0x20	/* Erase operation */
+#define FSR_ERR_MASK		(FSR_ERR_PROT | FSR_ERR_VOLT | \
+				FSR_ERR_PROG | FSR_ERR_ERASE)
+
 /* Flag Status Register bits */
 #define FSR_READY		0x80
 
-- 
1.9.1

RE: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Hou Zhiqiang]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 4114 bytes --]

Hi Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jteki@openedev.com]
> Sent: 2015Äê8ÔÂ19ÈÕ 17:57
> To: linux-mtd@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286; Hu
> Mingkai-B21284; David Woodhouse; Brian Norris
> Subject: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
> support
> 
> The clear flag status register operation was required by Micron SPI-NOR
> chips, which support FSR. And if an error bit of FSR have been set like
> protection, voltage, erase, and program, it must be cleared by the clear
> FSR operation.
> 
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> Cc: Hou Zhiqiang <B48286@freescale.com>
> Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Brian Norris <computersforpeace@gmail.com>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 35 +++++++++++++++++++++++++++++++----
>  include/linux/mtd/spi-nor.h   |  9 +++++++++
>  2 files changed, 40 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-
> nor.c index f954d03..c5c472d5 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)  }
> 
>  /*
> + * Read the clear flag status register.
> + * The clear flag status register operation was required by Micron
> + * SPI-NOR chips, which support FSR. And if an error bit of FSR
> + * have been set like protection, voltage, erase, and program,
> + * it must be cleared by the clear FSR operation.
> + * Returns zero for FSR bits cleared and negative if error occurred.
> + */
> +static int read_cfsr(struct spi_nor *nor) {
> +	int ret;
> +	u8 val;
> +
> +	ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);

There should be a write_reg instead of read_reg.
There isn¡¯t a register named CFSR, and the command SPINOR_OP_RDCFSR
is used to clear the FSR, another words reset FSR to default value.

> +	if (ret < 0) {
> +		pr_err("error %d reading CFSR\n", ret);
> +		return ret;
> +	}
> +
> +	return val;
> +}
> +
> +/*
>   * Read configuration register, returning its value in the
>   * location. Return the configuration register value.
>   * Returns negative if error occured.
> @@ -209,10 +231,15 @@ static inline int spi_nor_sr_ready(struct spi_nor
> *nor)  static inline int spi_nor_fsr_ready(struct spi_nor *nor)  {
>  	int fsr = read_fsr(nor);
> -	if (fsr < 0)
> -		return fsr;
> -	else
> -		return fsr & FSR_READY;
> +	if (fsr & FSR_ERR_MASK) {
> +		pr_err("flag status(0x%x) error occured\n", fsr);
> +		int cfsr = read_cfsr(nor);
> +		if (cfsr < 0)
> +			return cfsr;
> +		return -1;
> +	}
> +
> +	return fsr & FSR_READY;
>  }
> 
>  static int spi_nor_ready(struct spi_nor *nor) diff --git
> a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index
> c5a58c4..36c1681 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -35,6 +35,7 @@
>  #define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
>  #define SPINOR_OP_RDCR		0x35	/* Read configuration register */
>  #define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
> +#define SPINOR_OP_RDCFSR	0x50	/* Read clear flag status register */
> 
>  /* 4-byte address opcodes - used on Spansion and some Macronix flashes.
> */
>  #define SPINOR_OP_READ4		0x13	/* Read data bytes (low
> frequency) */
> @@ -74,6 +75,14 @@
>  /* Enhanced Volatile Configuration Register bits */
>  #define EVCR_QUAD_EN_MICRON    0x80    /* Micron Quad I/O */
> 
> +/* Flag Status Register Error bits */
> +#define FSR_ERR_PROT		0x2	/* Protection */
> +#define FSR_ERR_VOLT		0x8	/* Voltage on Vpp */
> +#define FSR_ERR_PROG		0x10	/* Program operation */
> +#define FSR_ERR_ERASE		0x20	/* Erase operation */
> +#define FSR_ERR_MASK		(FSR_ERR_PROT | FSR_ERR_VOLT | \
> +				FSR_ERR_PROG | FSR_ERR_ERASE)
> +
>  /* Flag Status Register bits */
>  #define FSR_READY		0x80
> 
> --
> 1.9.1

Thanks,
Zhiqiang
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Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Jagan Teki]

Hi Zhiqiang,

On 19 August 2015 at 17:42, Hou Zhiqiang <B48286@freescale.com> wrote:
> Hi Jagan,
>
>> -----Original Message-----
>> From: Jagan Teki [mailto:jteki@openedev.com]
>> Sent: 2015年8月19日 17:57
>> To: linux-mtd@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286; Hu
>> Mingkai-B21284; David Woodhouse; Brian Norris
>> Subject: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
>> support
>>
>> The clear flag status register operation was required by Micron SPI-NOR
>> chips, which support FSR. And if an error bit of FSR have been set like
>> protection, voltage, erase, and program, it must be cleared by the clear
>> FSR operation.
>>
>> Signed-off-by: Jagan Teki <jteki@openedev.com>
>> Cc: Hou Zhiqiang <B48286@freescale.com>
>> Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
>> Cc: David Woodhouse <dwmw2@infradead.org>
>> Cc: Brian Norris <computersforpeace@gmail.com>
>> ---
>>  drivers/mtd/spi-nor/spi-nor.c | 35 +++++++++++++++++++++++++++++++----
>>  include/linux/mtd/spi-nor.h   |  9 +++++++++
>>  2 files changed, 40 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-
>> nor.c index f954d03..c5c472d5 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)  }
>>
>>  /*
>> + * Read the clear flag status register.
>> + * The clear flag status register operation was required by Micron
>> + * SPI-NOR chips, which support FSR. And if an error bit of FSR
>> + * have been set like protection, voltage, erase, and program,
>> + * it must be cleared by the clear FSR operation.
>> + * Returns zero for FSR bits cleared and negative if error occurred.
>> + */
>> +static int read_cfsr(struct spi_nor *nor) {
>> +     int ret;
>> +     u8 val;
>> +
>> +     ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);
>
> There should be a write_reg instead of read_reg.
> There isn’t a register named CFSR, and the command SPINOR_OP_RDCFSR
> is used to clear the FSR, another words reset FSR to default value.

Yes, SPINOR_OP_RDCFSR is clear flag status register, for clearing errors bits
on fsr we need to read cfsr once.

>
>> +     if (ret < 0) {
>> +             pr_err("error %d reading CFSR\n", ret);
>> +             return ret;
>> +     }
>> +
>> +     return val;
>> +}
>> +
>> +/*
>>   * Read configuration register, returning its value in the
>>   * location. Return the configuration register value.
>>   * Returns negative if error occured.
>> @@ -209,10 +231,15 @@ static inline int spi_nor_sr_ready(struct spi_nor
>> *nor)  static inline int spi_nor_fsr_ready(struct spi_nor *nor)  {
>>       int fsr = read_fsr(nor);
>> -     if (fsr < 0)
>> -             return fsr;
>> -     else
>> -             return fsr & FSR_READY;
>> +     if (fsr & FSR_ERR_MASK) {
>> +             pr_err("flag status(0x%x) error occured\n", fsr);
>> +             int cfsr = read_cfsr(nor);
>> +             if (cfsr < 0)
>> +                     return cfsr;
>> +             return -1;
>> +     }
>> +
>> +     return fsr & FSR_READY;
>>  }
>>
>>  static int spi_nor_ready(struct spi_nor *nor) diff --git
>> a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index
>> c5a58c4..36c1681 100644
>> --- a/include/linux/mtd/spi-nor.h
>> +++ b/include/linux/mtd/spi-nor.h
>> @@ -35,6 +35,7 @@
>>  #define SPINOR_OP_RDID               0x9f    /* Read JEDEC ID */
>>  #define SPINOR_OP_RDCR               0x35    /* Read configuration register */
>>  #define SPINOR_OP_RDFSR              0x70    /* Read flag status register */
>> +#define SPINOR_OP_RDCFSR     0x50    /* Read clear flag status register */
>>
>>  /* 4-byte address opcodes - used on Spansion and some Macronix flashes.
>> */
>>  #define SPINOR_OP_READ4              0x13    /* Read data bytes (low
>> frequency) */
>> @@ -74,6 +75,14 @@
>>  /* Enhanced Volatile Configuration Register bits */
>>  #define EVCR_QUAD_EN_MICRON    0x80    /* Micron Quad I/O */
>>
>> +/* Flag Status Register Error bits */
>> +#define FSR_ERR_PROT         0x2     /* Protection */
>> +#define FSR_ERR_VOLT         0x8     /* Voltage on Vpp */
>> +#define FSR_ERR_PROG         0x10    /* Program operation */
>> +#define FSR_ERR_ERASE                0x20    /* Erase operation */
>> +#define FSR_ERR_MASK         (FSR_ERR_PROT | FSR_ERR_VOLT | \
>> +                             FSR_ERR_PROG | FSR_ERR_ERASE)
>> +
>>  /* Flag Status Register bits */
>>  #define FSR_READY            0x80

thanks!
-- 
Jagan | openedev.

RE: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Hou Zhiqiang]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 3340 bytes --]

Hello Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jteki@openedev.com]
> Sent: 2015年8月20日 1:49
> To: Hou Zhiqiang-B48286
> Cc: linux-mtd@lists.infradead.org; Hu Mingkai-B21284; Brian Norris; David
> Woodhouse; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
> support
> 
> Hi Zhiqiang,
> 
> On 19 August 2015 at 17:42, Hou Zhiqiang <B48286@freescale.com> wrote:
> > Hi Jagan,
> >
> >> -----Original Message-----
> >> From: Jagan Teki [mailto:jteki@openedev.com]
> >> Sent: 2015年8月19日 17:57
> >> To: linux-mtd@lists.infradead.org
> >> Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286; Hu
> >> Mingkai-B21284; David Woodhouse; Brian Norris
> >> Subject: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
> >> support
> >>
> >> The clear flag status register operation was required by Micron
> >> SPI-NOR chips, which support FSR. And if an error bit of FSR have
> >> been set like protection, voltage, erase, and program, it must be
> >> cleared by the clear FSR operation.
> >>
> >> Signed-off-by: Jagan Teki <jteki@openedev.com>
> >> Cc: Hou Zhiqiang <B48286@freescale.com>
> >> Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
> >> Cc: David Woodhouse <dwmw2@infradead.org>
> >> Cc: Brian Norris <computersforpeace@gmail.com>
> >> ---
> >>  drivers/mtd/spi-nor/spi-nor.c | 35 +++++++++++++++++++++++++++++++---
> -
> >>  include/linux/mtd/spi-nor.h   |  9 +++++++++
> >>  2 files changed, 40 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-
> >> nor.c index f954d03..c5c472d5 100644
> >> --- a/drivers/mtd/spi-nor/spi-nor.c
> >> +++ b/drivers/mtd/spi-nor/spi-nor.c
> >> @@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)  }
> >>
> >>  /*
> >> + * Read the clear flag status register.
> >> + * The clear flag status register operation was required by Micron
> >> + * SPI-NOR chips, which support FSR. And if an error bit of FSR
> >> + * have been set like protection, voltage, erase, and program,
> >> + * it must be cleared by the clear FSR operation.
> >> + * Returns zero for FSR bits cleared and negative if error occurred.
> >> + */
> >> +static int read_cfsr(struct spi_nor *nor) {
> >> +     int ret;
> >> +     u8 val;
> >> +
> >> +     ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);
> >
> > There should be a write_reg instead of read_reg.
> > There isn’t a register named CFSR, and the command SPINOR_OP_RDCFSR is
> > used to clear the FSR, another words reset FSR to default value.
> 
> Yes, SPINOR_OP_RDCFSR is clear flag status register, for clearing errors
> bits on fsr we need to read cfsr once.
> 

Sorry, I'm not clear for this operation. Please correct me if I'm wrong.
As far as I understand, this command is used to reset the FSR. Does a value
Will be read back? And there is not the register CFSR, so I don't know which
register will be read by SPINOR_OP_RDCFSR?

> >
> >> +     if (ret < 0) {
> >> +             pr_err("error %d reading CFSR\n", ret);
> >> +             return ret;
> >> +     }
> >> +
> >> +     return val;
> >> +}
> >> +
> >> +/*

Thanks,
Zhiqiang
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Jagan Teki]

Hi Zhiqiang,

On 20 August 2015 at 08:36, Hou Zhiqiang <B48286@freescale.com> wrote:
> Hello Jagan,
>
>> -----Original Message-----
>> From: Jagan Teki [mailto:jteki@openedev.com]
>> Sent: 2015年8月20日 1:49
>> To: Hou Zhiqiang-B48286
>> Cc: linux-mtd@lists.infradead.org; Hu Mingkai-B21284; Brian Norris; David
>> Woodhouse; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
>> support
>>
>> Hi Zhiqiang,
>>
>> On 19 August 2015 at 17:42, Hou Zhiqiang <B48286@freescale.com> wrote:
>> > Hi Jagan,
>> >
>> >> -----Original Message-----
>> >> From: Jagan Teki [mailto:jteki@openedev.com]
>> >> Sent: 2015年8月19日 17:57
>> >> To: linux-mtd@lists.infradead.org
>> >> Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286; Hu
>> >> Mingkai-B21284; David Woodhouse; Brian Norris
>> >> Subject: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
>> >> support
>> >>
>> >> The clear flag status register operation was required by Micron
>> >> SPI-NOR chips, which support FSR. And if an error bit of FSR have
>> >> been set like protection, voltage, erase, and program, it must be
>> >> cleared by the clear FSR operation.
>> >>
>> >> Signed-off-by: Jagan Teki <jteki@openedev.com>
>> >> Cc: Hou Zhiqiang <B48286@freescale.com>
>> >> Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
>> >> Cc: David Woodhouse <dwmw2@infradead.org>
>> >> Cc: Brian Norris <computersforpeace@gmail.com>
>> >> ---
>> >>  drivers/mtd/spi-nor/spi-nor.c | 35 +++++++++++++++++++++++++++++++---
>> -
>> >>  include/linux/mtd/spi-nor.h   |  9 +++++++++
>> >>  2 files changed, 40 insertions(+), 4 deletions(-)
>> >>
>> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-
>> >> nor.c index f954d03..c5c472d5 100644
>> >> --- a/drivers/mtd/spi-nor/spi-nor.c
>> >> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> >> @@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)  }
>> >>
>> >>  /*
>> >> + * Read the clear flag status register.
>> >> + * The clear flag status register operation was required by Micron
>> >> + * SPI-NOR chips, which support FSR. And if an error bit of FSR
>> >> + * have been set like protection, voltage, erase, and program,
>> >> + * it must be cleared by the clear FSR operation.
>> >> + * Returns zero for FSR bits cleared and negative if error occurred.
>> >> + */
>> >> +static int read_cfsr(struct spi_nor *nor) {
>> >> +     int ret;
>> >> +     u8 val;
>> >> +
>> >> +     ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);
>> >
>> > There should be a write_reg instead of read_reg.
>> > There isn’t a register named CFSR, and the command SPINOR_OP_RDCFSR is
>> > used to clear the FSR, another words reset FSR to default value.
>>
>> Yes, SPINOR_OP_RDCFSR is clear flag status register, for clearing errors
>> bits on fsr we need to read cfsr once.
>>
>
> Sorry, I'm not clear for this operation. Please correct me if I'm wrong.
> As far as I understand, this command is used to reset the FSR. Does a value
> Will be read back? And there is not the register CFSR, so I don't know which
> register will be read by SPINOR_OP_RDCFSR?

Sorry for the confusion in previous email.

If there is any error bits set during FSR operation, those will reset
back to original
values by reading CFSR ie means the bits on flag status register
revert back to original
state, so-that the flag status register is ready for next FSR operation.

I have defined this, SPINOR_OP_RDCFSR on the patch

diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index c5a58c4..36c1681 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -35,6 +35,7 @@
 #define SPINOR_OP_RDID         0x9f    /* Read JEDEC ID */
 #define SPINOR_OP_RDCR         0x35    /* Read configuration register */
 #define SPINOR_OP_RDFSR                0x70    /* Read flag status register */
+#define SPINOR_OP_RDCFSR       0x50    /* Read clear flag status register */

For more information pls- refer flash datasheet[1]

Page, 29: about fsr
Page, 41: about cfsr

[1] https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0CCIQFjABahUKEwjTwY3zzbnHAhXVj44KHdiWDVU&url=https%3A%2F%2Fwww.micron.com%2F~%2Fmedia%2Fdocuments%2Fproducts%2Fdata-sheet%2Fnor-flash%2Fserial-nor%2Fn25q%2Fn25q_512mb_1ce_3v_65nm.pdf&ei=Uc3WVZPVCNWfugTYrbaoBQ&usg=AFQjCNEN4dLie4U9OTSbNxN-h9jyN9InDQ&sig2=vRQTvlkbgsgJw1Fy9z1K8A

thanks!
-- 
Jagan | openedev.

RE: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Hou Zhiqiang]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 5460 bytes --]

Hi Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jteki@openedev.com]
> Sent: 2015年8月21日 15:12
> To: Hou Zhiqiang-B48286
> Cc: linux-mtd@lists.infradead.org; Hu Mingkai-B21284; Brian Norris; David
> Woodhouse; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
> support
> 
> Hi Zhiqiang,
> 
> On 20 August 2015 at 08:36, Hou Zhiqiang <B48286@freescale.com> wrote:
> > Hello Jagan,
> >
> >> -----Original Message-----
> >> From: Jagan Teki [mailto:jteki@openedev.com]
> >> Sent: 2015年8月20日 1:49
> >> To: Hou Zhiqiang-B48286
> >> Cc: linux-mtd@lists.infradead.org; Hu Mingkai-B21284; Brian Norris;
> >> David Woodhouse; linux-kernel@vger.kernel.org
> >> Subject: Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status
> >> register support
> >>
> >> Hi Zhiqiang,
> >>
> >> On 19 August 2015 at 17:42, Hou Zhiqiang <B48286@freescale.com> wrote:
> >> > Hi Jagan,
> >> >
> >> >> -----Original Message-----
> >> >> From: Jagan Teki [mailto:jteki@openedev.com]
> >> >> Sent: 2015年8月19日 17:57
> >> >> To: linux-mtd@lists.infradead.org
> >> >> Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286;
> >> >> Hu Mingkai-B21284; David Woodhouse; Brian Norris
> >> >> Subject: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status
> >> >> register support
> >> >>
> >> >> The clear flag status register operation was required by Micron
> >> >> SPI-NOR chips, which support FSR. And if an error bit of FSR have
> >> >> been set like protection, voltage, erase, and program, it must be
> >> >> cleared by the clear FSR operation.
> >> >>
> >> >> Signed-off-by: Jagan Teki <jteki@openedev.com>
> >> >> Cc: Hou Zhiqiang <B48286@freescale.com>
> >> >> Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
> >> >> Cc: David Woodhouse <dwmw2@infradead.org>
> >> >> Cc: Brian Norris <computersforpeace@gmail.com>
> >> >> ---
> >> >>  drivers/mtd/spi-nor/spi-nor.c | 35
> >> >> +++++++++++++++++++++++++++++++---
> >> -
> >> >>  include/linux/mtd/spi-nor.h   |  9 +++++++++
> >> >>  2 files changed, 40 insertions(+), 4 deletions(-)
> >> >>
> >> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c
> >> >> b/drivers/mtd/spi-nor/spi- nor.c index f954d03..c5c472d5 100644
> >> >> --- a/drivers/mtd/spi-nor/spi-nor.c
> >> >> +++ b/drivers/mtd/spi-nor/spi-nor.c
> >> >> @@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)  }
> >> >>
> >> >>  /*
> >> >> + * Read the clear flag status register.
> >> >> + * The clear flag status register operation was required by
> >> >> +Micron
> >> >> + * SPI-NOR chips, which support FSR. And if an error bit of FSR
> >> >> + * have been set like protection, voltage, erase, and program,
> >> >> + * it must be cleared by the clear FSR operation.
> >> >> + * Returns zero for FSR bits cleared and negative if error
> occurred.
> >> >> + */
> >> >> +static int read_cfsr(struct spi_nor *nor) {
> >> >> +     int ret;
> >> >> +     u8 val;
> >> >> +
> >> >> +     ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);
> >> >
> >> > There should be a write_reg instead of read_reg.
> >> > There isn’t a register named CFSR, and the command SPINOR_OP_RDCFSR
> >> > is used to clear the FSR, another words reset FSR to default value.
> >>
> >> Yes, SPINOR_OP_RDCFSR is clear flag status register, for clearing
> >> errors bits on fsr we need to read cfsr once.
> >>
> >
> > Sorry, I'm not clear for this operation. Please correct me if I'm wrong.
> > As far as I understand, this command is used to reset the FSR. Does a
> > value Will be read back? And there is not the register CFSR, so I
> > don't know which register will be read by SPINOR_OP_RDCFSR?
> 
> Sorry for the confusion in previous email.
> 
> If there is any error bits set during FSR operation, those will reset
> back to original values by reading CFSR ie means the bits on flag status
> register revert back to original state, so-that the flag status register
> is ready for next FSR operation.
> 
> I have defined this, SPINOR_OP_RDCFSR on the patch
> 
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index c5a58c4..36c1681 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -35,6 +35,7 @@
>  #define SPINOR_OP_RDID         0x9f    /* Read JEDEC ID */
>  #define SPINOR_OP_RDCR         0x35    /* Read configuration register */
>  #define SPINOR_OP_RDFSR                0x70    /* Read flag status
> register */
> +#define SPINOR_OP_RDCFSR       0x50    /* Read clear flag status
> register */
> 
> For more information pls- refer flash datasheet[1]
> 
> Page, 29: about fsr
> Page, 41: about cfsr

Upon page 41, I think, it is a CMD which is used to clear the FSR instead of
a CFSR Register. This section is to expound the "CLEAR FLAG STATUS REGISTER
Command", and it says execute this CMD to clear the error bits, rather than
read the CFSR to clear those bits.

> 
> [1]
> https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja
> &uact=8&ved=0CCIQFjABahUKEwjTwY3zzbnHAhXVj44KHdiWDVU&url=https%3A%2F%2Fww
> w.micron.com%2F~%2Fmedia%2Fdocuments%2Fproducts%2Fdata-sheet%2Fnor-
> flash%2Fserial-
> nor%2Fn25q%2Fn25q_512mb_1ce_3v_65nm.pdf&ei=Uc3WVZPVCNWfugTYrbaoBQ&usg=AFQ
> jCNEN4dLie4U9OTSbNxN-h9jyN9InDQ&sig2=vRQTvlkbgsgJw1Fy9z1K8A
> 
Thanks!
Zhiqiang
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register support

[Jagan Teki]

Hi Zhiqiang,

On 25 August 2015 at 07:52, Hou Zhiqiang <B48286@freescale.com> wrote:
> Hi Jagan,
>
>> -----Original Message-----
>> From: Jagan Teki [mailto:jteki@openedev.com]
>> Sent: 2015年8月21日 15:12
>> To: Hou Zhiqiang-B48286
>> Cc: linux-mtd@lists.infradead.org; Hu Mingkai-B21284; Brian Norris; David
>> Woodhouse; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status register
>> support
>>
>> Hi Zhiqiang,
>>
>> On 20 August 2015 at 08:36, Hou Zhiqiang <B48286@freescale.com> wrote:
>> > Hello Jagan,
>> >
>> >> -----Original Message-----
>> >> From: Jagan Teki [mailto:jteki@openedev.com]
>> >> Sent: 2015年8月20日 1:49
>> >> To: Hou Zhiqiang-B48286
>> >> Cc: linux-mtd@lists.infradead.org; Hu Mingkai-B21284; Brian Norris;
>> >> David Woodhouse; linux-kernel@vger.kernel.org
>> >> Subject: Re: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status
>> >> register support
>> >>
>> >> Hi Zhiqiang,
>> >>
>> >> On 19 August 2015 at 17:42, Hou Zhiqiang <B48286@freescale.com> wrote:
>> >> > Hi Jagan,
>> >> >
>> >> >> -----Original Message-----
>> >> >> From: Jagan Teki [mailto:jteki@openedev.com]
>> >> >> Sent: 2015年8月19日 17:57
>> >> >> To: linux-mtd@lists.infradead.org
>> >> >> Cc: linux-kernel@vger.kernel.org; Jagan Teki; Hou Zhiqiang-B48286;
>> >> >> Hu Mingkai-B21284; David Woodhouse; Brian Norris
>> >> >> Subject: [PATCH 3/3] mtd: spi-nor: sf: Add clear flag status
>> >> >> register support
>> >> >>
>> >> >> The clear flag status register operation was required by Micron
>> >> >> SPI-NOR chips, which support FSR. And if an error bit of FSR have
>> >> >> been set like protection, voltage, erase, and program, it must be
>> >> >> cleared by the clear FSR operation.
>> >> >>
>> >> >> Signed-off-by: Jagan Teki <jteki@openedev.com>
>> >> >> Cc: Hou Zhiqiang <B48286@freescale.com>
>> >> >> Cc: Mingkai.Hu <Mingkai.Hu@freescale.com>
>> >> >> Cc: David Woodhouse <dwmw2@infradead.org>
>> >> >> Cc: Brian Norris <computersforpeace@gmail.com>
>> >> >> ---
>> >> >>  drivers/mtd/spi-nor/spi-nor.c | 35
>> >> >> +++++++++++++++++++++++++++++++---
>> >> -
>> >> >>  include/linux/mtd/spi-nor.h   |  9 +++++++++
>> >> >>  2 files changed, 40 insertions(+), 4 deletions(-)
>> >> >>
>> >> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c
>> >> >> b/drivers/mtd/spi-nor/spi- nor.c index f954d03..c5c472d5 100644
>> >> >> --- a/drivers/mtd/spi-nor/spi-nor.c
>> >> >> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> >> >> @@ -100,6 +100,28 @@ static int read_fsr(struct spi_nor *nor)  }
>> >> >>
>> >> >>  /*
>> >> >> + * Read the clear flag status register.
>> >> >> + * The clear flag status register operation was required by
>> >> >> +Micron
>> >> >> + * SPI-NOR chips, which support FSR. And if an error bit of FSR
>> >> >> + * have been set like protection, voltage, erase, and program,
>> >> >> + * it must be cleared by the clear FSR operation.
>> >> >> + * Returns zero for FSR bits cleared and negative if error
>> occurred.
>> >> >> + */
>> >> >> +static int read_cfsr(struct spi_nor *nor) {
>> >> >> +     int ret;
>> >> >> +     u8 val;
>> >> >> +
>> >> >> +     ret = nor->read_reg(nor, SPINOR_OP_RDCFSR, &val, 1);
>> >> >
>> >> > There should be a write_reg instead of read_reg.
>> >> > There isn’t a register named CFSR, and the command SPINOR_OP_RDCFSR
>> >> > is used to clear the FSR, another words reset FSR to default value.
>> >>
>> >> Yes, SPINOR_OP_RDCFSR is clear flag status register, for clearing
>> >> errors bits on fsr we need to read cfsr once.
>> >>
>> >
>> > Sorry, I'm not clear for this operation. Please correct me if I'm wrong.
>> > As far as I understand, this command is used to reset the FSR. Does a
>> > value Will be read back? And there is not the register CFSR, so I
>> > don't know which register will be read by SPINOR_OP_RDCFSR?
>>
>> Sorry for the confusion in previous email.
>>
>> If there is any error bits set during FSR operation, those will reset
>> back to original values by reading CFSR ie means the bits on flag status
>> register revert back to original state, so-that the flag status register
>> is ready for next FSR operation.
>>
>> I have defined this, SPINOR_OP_RDCFSR on the patch
>>
>> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
>> index c5a58c4..36c1681 100644
>> --- a/include/linux/mtd/spi-nor.h
>> +++ b/include/linux/mtd/spi-nor.h
>> @@ -35,6 +35,7 @@
>>  #define SPINOR_OP_RDID         0x9f    /* Read JEDEC ID */
>>  #define SPINOR_OP_RDCR         0x35    /* Read configuration register */
>>  #define SPINOR_OP_RDFSR                0x70    /* Read flag status
>> register */
>> +#define SPINOR_OP_RDCFSR       0x50    /* Read clear flag status
>> register */
>>
>> For more information pls- refer flash datasheet[1]
>>
>> Page, 29: about fsr
>> Page, 41: about cfsr
>
> Upon page 41, I think, it is a CMD which is used to clear the FSR instead of
> a CFSR Register. This section is to expound the "CLEAR FLAG STATUS REGISTER
> Command", and it says execute this CMD to clear the error bits, rather than
> read the CFSR to clear those bits.

Agreed that it could be command (clear flag status register - 0x50)
write operation with
NULL data, will prepare next version and send the same.

thanks!
-- 
Jagan | openedev.

Re: [PATCH 1/3] mtd: spi-nor: Use write_sr for write status

[Jagan Teki]

On 19 August 2015 at 15:26, Jagan Teki <jteki@openedev.com> wrote:
> Use existing write_sr() call instead of decoding and
> calling nor->write_reg separately.
>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Brian Norris <computersforpeace@gmail.com>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 47516d3..3e198b4 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -869,8 +869,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
>         val = read_sr(nor);
>         write_enable(nor);
>
> -       nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
> -       nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
> +       write_sr(nor, val | SR_QUAD_EN_MX);
>
>         if (spi_nor_wait_till_ready(nor))
>                 return 1;
> --
> 1.9.1
>

Ping


-- 
Jagan | openedev.

Re: [PATCH 2/3] mtd: spi-nor: Zap unneeded write_enable from write_reg

[Jagan Teki]

On 19 August 2015 at 15:26, Jagan Teki <jteki@openedev.com> wrote:
> Since write enabling shall do with buf and len without
> need of exctra write_enable argument, hence removed the
> same from write_reg.
>
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: Han Xu <han.xu@freescale.com>
> ---
>  drivers/mtd/devices/m25p80.c      |  3 +--
>  drivers/mtd/spi-nor/fsl-quadspi.c |  3 +--
>  drivers/mtd/spi-nor/spi-nor.c     | 16 ++++++++--------
>  include/linux/mtd/spi-nor.h       |  3 +--
>  4 files changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index 9cd3631..ab69d2d 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -62,8 +62,7 @@ static int m25p_cmdsz(struct spi_nor *nor)
>         return 1 + nor->addr_width;
>  }
>
> -static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
> -                       int wr_en)
> +static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
>  {
>         struct m25p *flash = nor->priv;
>         struct spi_device *spi = flash->spi;
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
> index d32b7e0..2c8c578 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -798,8 +798,7 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
>         return 0;
>  }
>
> -static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
> -                       int write_enable)
> +static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
>  {
>         struct fsl_qspi *q = nor->priv;
>         int ret;
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 3e198b4..f954d03 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -143,7 +143,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
>  static inline int write_sr(struct spi_nor *nor, u8 val)
>  {
>         nor->cmd_buf[0] = val;
> -       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
> +       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
>  }
>
>  /*
> @@ -152,7 +152,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val)
>   */
>  static inline int write_enable(struct spi_nor *nor)
>  {
> -       return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
> +       return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
>  }
>
>  /*
> @@ -160,7 +160,7 @@ static inline int write_enable(struct spi_nor *nor)
>   */
>  static inline int write_disable(struct spi_nor *nor)
>  {
> -       return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
> +       return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
>  }
>
>  static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
> @@ -186,7 +186,7 @@ static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
>                         write_enable(nor);
>
>                 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
> -               status = nor->write_reg(nor, cmd, NULL, 0, 0);
> +               status = nor->write_reg(nor, cmd, NULL, 0);
>                 if (need_wren)
>                         write_disable(nor);
>
> @@ -194,7 +194,7 @@ static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
>         default:
>                 /* Spansion style */
>                 nor->cmd_buf[0] = enable << 7;
> -               return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
> +               return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
>         }
>  }
>  static inline int spi_nor_sr_ready(struct spi_nor *nor)
> @@ -265,7 +265,7 @@ static int erase_chip(struct spi_nor *nor)
>  {
>         dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
>
> -       return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
> +       return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
>  }
>
>  static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
> @@ -894,7 +894,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val)
>         nor->cmd_buf[0] = val & 0xff;
>         nor->cmd_buf[1] = (val >> 8);
>
> -       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
> +       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
>  }
>
>  static int spansion_quad_enable(struct spi_nor *nor)
> @@ -936,7 +936,7 @@ static int micron_quad_enable(struct spi_nor *nor)
>
>         /* set EVCR, enable quad I/O */
>         nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
> -       ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
> +       ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
>         if (ret < 0) {
>                 dev_err(nor->dev, "error while writing EVCR register\n");
>                 return ret;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index e540952..c5a58c4 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -182,8 +182,7 @@ struct spi_nor {
>         int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
>                           u8 *buf, size_t len);
>         int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
> -       int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
> -                       int write_enable);
> +       int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
>
>         int (*read)(struct spi_nor *nor, loff_t from,
>                         size_t len, size_t *retlen, u_char *read_buf);
> --
> 1.9.1
>

Ping

-- 
Jagan | openedev.

Re: [PATCH 1/3] mtd: spi-nor: Use write_sr for write status

[Brian Norris]

On Wed, Aug 19, 2015 at 03:26:43PM +0530, Jagan Teki wrote:
> Use existing write_sr() call instead of decoding and
> calling nor->write_reg separately.
> 
> Signed-off-by: Jagan Teki <jteki@openedev.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Brian Norris <computersforpeace@gmail.com>

Pushed this one to l2-mtd.git/next

Re: [PATCH 2/3] mtd: spi-nor: Zap unneeded write_enable from write_reg

[Brian Norris]

+ Joachim

On Wed, Aug 19, 2015 at 03:26:44PM +0530, Jagan Teki wrote:
> Since write enabling shall do with buf and len without
> need of exctra write_enable argument, hence removed the
> same from write_reg.

I rewrote this description a bit.

> Signed-off-by: Jagan Teki <jteki@openedev.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: Han Xu <han.xu@freescale.com>
> ---
>  drivers/mtd/devices/m25p80.c      |  3 +--
>  drivers/mtd/spi-nor/fsl-quadspi.c |  3 +--
>  drivers/mtd/spi-nor/spi-nor.c     | 16 ++++++++--------
>  include/linux/mtd/spi-nor.h       |  3 +--
>  4 files changed, 11 insertions(+), 14 deletions(-)
> 

You missed the new drivers/mtd/spi-nor/nxp-spifi.c driver:

  drivers/mtd/spi-nor/nxp-spifi.c: In function 'nxp_spifi_setup_flash':
  drivers/mtd/spi-nor/nxp-spifi.c:340:23: warning: assignment from incompatible pointer type
    spifi->nor.write_reg = nxp_spifi_write_reg;
                         ^

[...]
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index e540952..c5a58c4 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -182,8 +182,7 @@ struct spi_nor {
>  	int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
>  			  u8 *buf, size_t len);
>  	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
> -	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
> -			int write_enable);
> +	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
>  
>  	int (*read)(struct spi_nor *nor, loff_t from,
>  			size_t len, size_t *retlen, u_char *read_buf);

Squashed in the following diff and applied to l2-mtd.git/next:

diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
index ce7bf6b2916b..9e82098ae644 100644
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -149,8 +149,7 @@ static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 	return nxp_spifi_wait_for_cmd(spifi);
 }
 
-static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
-			       int len, int write_enable)
+static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 {
 	struct nxp_spifi *spifi = nor->priv;
 	u32 cmd;