From: "Odzioba, Lukasz" <lukasz.odzioba@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"Liang, Kan" <kan.liang@intel.com>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"eranian@google.com" <eranian@google.com>,
"acme@kernel.org" <acme@kernel.org>,
"alexander.shishkin@linux.intel.com"
<alexander.shishkin@linux.intel.com>, "bp@suse.de" <bp@suse.de>,
"Anaczkowski, Lukasz" <lukasz.anaczkowski@intel.com>
Subject: RE: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing
Date: Mon, 20 Jun 2016 10:26:30 +0000 [thread overview]
Message-ID: <D6EDEBF1F91015459DB866AC4EE162CC023FC273@IRSMSX103.ger.corp.intel.com> (raw)
In-Reply-To: <20160608064800.GN30154@twins.programming.kicks-ass.net>
On 08.06.2016 Peter Zijlstra wrote:
> How does this work in the light of intel_alt_er() ?
Hi Peter,
If the constrained bit is valid on only one of the OCR MSRs (like in case of KNL),
then OCR valid mask will forbid altering it by the other MSR in intel_alt_er.
If constrained bit is valid on both OCR MSR, so it can be safely altered by
intel_alt_er, but in this case it should be defined twice - for each MSR i.e:
INTEL_EEVENT_CONSTRAINT(0x01b7, 0, 0x1); // bit0 can be used only on PMC0
INTEL_EEVENT_CONSTRAINT(0x02b7, 0, 0x1); // bit0 can be used only on PMC0
I hope that answers your question.
Thanks,
Lukas
next prev parent reply other threads:[~2016-06-20 10:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-08 4:02 [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing Lukasz Odzioba
2016-06-08 6:48 ` Peter Zijlstra
2016-06-20 10:26 ` Odzioba, Lukasz [this message]
2016-06-21 9:37 ` Peter Zijlstra
2016-06-24 14:54 ` Odzioba, Lukasz
2016-06-24 17:04 ` Stephane Eranian
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