* Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
@ 2016-03-03 13:39 Bean Huo 霍斌斌 (beanhuo)
2016-03-18 10:08 ` Yunhui Cui
0 siblings, 1 reply; 6+ messages in thread
From: Bean Huo 霍斌斌 (beanhuo) @ 2016-03-03 13:39 UTC (permalink / raw)
To: Yunhui Cui
Cc: linux-mtd, dwmw2, computersforpeace, han.xu, linux-kernel,
linux-mtd, linux-arm-kernel, yao.yuan, yunhui.cui
> From: Yunhui Cui <B56489@freescale.com>
> To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> <han.xu@freescale.com>
> Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui
> Cui
> <yunhui.cui@nxp.com>
> Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> protection
> Message-ID: <1456988044-37061-4-git-send-email-B56489@freescale.com>
> Content-Type: text/plain
>
> From: Yunhui Cui <yunhui.cui@nxp.com>
>
> For Micron family ,The status register write enable/disable bit, provides
> hardware data protection for the device.
> When the enable/disable bit is set to 1, the status register nonvolatile bits
> become read-only and the WRITE STATUS REGISTER operation will not
> execute.
>
> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index ed0c19c..917f814 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -39,6 +39,7 @@
>
> #define SPI_NOR_MAX_ID_LEN 6
> #define SPI_NOR_MAX_ADDR_WIDTH 4
> +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
>
> struct flash_info {
> char *name;
> @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name, enum read_mode mode)
> write_sr(nor, 0);
> }
>
> + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> + ret = read_sr(nor);
> + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> +
For Micron the status register write enable/disable bit, its default/factory value is disable.
Can here first check ,then program?
> + write_enable(nor);
> + write_sr(nor, ret);
> + }
> +
> if (!mtd->name)
> mtd->name = dev_name(dev);
> mtd->priv = nor;
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
2016-03-03 13:39 [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Bean Huo 霍斌斌 (beanhuo)
@ 2016-03-18 10:08 ` Yunhui Cui
2016-03-21 2:55 ` Bean Huo 霍斌斌 (beanhuo)
0 siblings, 1 reply; 6+ messages in thread
From: Yunhui Cui @ 2016-03-18 10:08 UTC (permalink / raw)
To: Bean Huo 霍斌斌 (beanhuo), Yunhui Cui
Cc: linux-mtd, dwmw2, computersforpeace, han.xu, linux-kernel,
linux-mtd, linux-arm-kernel, Yao Yuan
Hi Bean,
Thanks for your suggestions very much.
Yes, the flash N25Q128A status register write enable/disable bit is disable in initial state.
But, This patch aims to clear status register bit[7](write enable/disable bit) to 0, which enables the bit.
Frankly speaking, I also don't want to add this patch.
The reason for this is that clear status register bit[7] to 0 is a must to set quad mode to Enhanced Volatile Configuration Register using command SPINOR_OP_WD_EVCR. Otherwise it will output "Micron EVCR Quad bit not clear" in spi-nor.c
I looked up the datasheet, but I really don't find out any connection between status register bit[7](write enable/disable bit) equals 0 and seting quad mode to Enhanced Volatile Configuration Register.
Just as I want to send the issue to Micron team , could you give me some solutions ?
Thanks
Yunhui
-----Original Message-----
From: Bean Huo 霍斌斌 (beanhuo) [mailto:beanhuo@micron.com]
Sent: Thursday, March 03, 2016 9:39 PM
To: Yunhui Cui
Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com; linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux-arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui
Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
> From: Yunhui Cui <B56489@freescale.com>
> To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> <han.xu@freescale.com>
> Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui
> Cui
> <yunhui.cui@nxp.com>
> Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> protection
> Message-ID: <1456988044-37061-4-git-send-email-B56489@freescale.com>
> Content-Type: text/plain
>
> From: Yunhui Cui <yunhui.cui@nxp.com>
>
> For Micron family ,The status register write enable/disable bit,
> provides hardware data protection for the device.
> When the enable/disable bit is set to 1, the status register
> nonvolatile bits become read-only and the WRITE STATUS REGISTER
> operation will not execute.
>
> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c
> b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..917f814 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -39,6 +39,7 @@
>
> #define SPI_NOR_MAX_ID_LEN 6
> #define SPI_NOR_MAX_ADDR_WIDTH 4
> +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
>
> struct flash_info {
> char *name;
> @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const
> char *name, enum read_mode mode)
> write_sr(nor, 0);
> }
>
> + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> + ret = read_sr(nor);
> + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> +
For Micron the status register write enable/disable bit, its default/factory value is disable.
Can here first check ,then program?
> + write_enable(nor);
> + write_sr(nor, ret);
> + }
> +
> if (!mtd->name)
> mtd->name = dev_name(dev);
> mtd->priv = nor;
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
2016-03-18 10:08 ` Yunhui Cui
@ 2016-03-21 2:55 ` Bean Huo 霍斌斌 (beanhuo)
2016-03-21 8:08 ` Yunhui Cui
2016-04-14 3:45 ` Yunhui Cui
0 siblings, 2 replies; 6+ messages in thread
From: Bean Huo 霍斌斌 (beanhuo) @ 2016-03-21 2:55 UTC (permalink / raw)
To: Yunhui Cui, Yunhui Cui
Cc: linux-mtd, dwmw2, computersforpeace, han.xu, linux-kernel,
linux-mtd, linux-arm-kernel, Yao Yuan
Hi, Yunhai
You mean that EVCR.bit7 cannot clear(enable quad mode) if not write SR.bit7 to 0?
They don't have any connection each other.
> -----Original Message-----
> From: Yunhui Cui [mailto:yunhui.cui@nxp.com]
> Sent: Friday, March 18, 2016 6:09 PM
> To: Bean Huo 霍斌斌 (beanhuo); Yunhui Cui
> Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> computersforpeace@gmail.com; han.xu@freescale.com;
> linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; Yao Yuan
> Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
>
> Hi Bean,
>
> Thanks for your suggestions very much.
> Yes, the flash N25Q128A status register write enable/disable bit is disable in
> initial state.
> But, This patch aims to clear status registerV bit[7](write enable/disable bit) to
> 0, which enables the bit.
> Frankly speaking, I also don't want to add this patch.
> The reason for this is that clear status register bit[7] to 0 is a must to set quad
> mode to Enhanced Volatile Configuration Register using command
> SPINOR_OP_WD_EVCR. Otherwise it will output "Micron EVCR Quad bit not
> clear" in spi-nor.c I looked up the datasheet, but I really don't find out any
> connection between status register bit[7](write enable/disable bit) equals 0
> and seting quad mode to Enhanced Volatile Configuration Register.
>
> Just as I want to send the issue to Micron team , could you give me some
> solutions ?
>
>
> Thanks
> Yunhui
>
> -----Original Message-----
> From: Bean Huo 霍斌斌 (beanhuo) [mailto:beanhuo@micron.com]
> Sent: Thursday, March 03, 2016 9:39 PM
> To: Yunhui Cui
> Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> computersforpeace@gmail.com; han.xu@freescale.com;
> linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui
> Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
>
> > From: Yunhui Cui <B56489@freescale.com>
> > To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> > <han.xu@freescale.com>
> > Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> > <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui
> > Cui
> > <yunhui.cui@nxp.com>
> > Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> > protection
> > Message-ID:
> <1456988044-37061-4-git-send-email-B56489@freescale.com>
> > Content-Type: text/plain
> >
> > From: Yunhui Cui <yunhui.cui@nxp.com>
> >
> > For Micron family ,The status register write enable/disable bit,
> > provides hardware data protection for the device.
> > When the enable/disable bit is set to 1, the status register
> > nonvolatile bits become read-only and the WRITE STATUS REGISTER
> > operation will not execute.
> >
> > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> > ---
> > drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..917f814 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -39,6 +39,7 @@
> >
> > #define SPI_NOR_MAX_ID_LEN 6
> > #define SPI_NOR_MAX_ADDR_WIDTH 4
> > +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
> >
> > struct flash_info {
> > char *name;
> > @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const
> > char *name, enum read_mode mode)
> > write_sr(nor, 0);
> > }
> >
> > + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> > + ret = read_sr(nor);
> > + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> > +
> For Micron the status register write enable/disable bit, its default/factory
> value is disable.
> Can here first check ,then program?
> > + write_enable(nor);
> > + write_sr(nor, ret);
> > + }
> > +
> > if (!mtd->name)
> > mtd->name = dev_name(dev);
> > mtd->priv = nor;
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
2016-03-21 2:55 ` Bean Huo 霍斌斌 (beanhuo)
@ 2016-03-21 8:08 ` Yunhui Cui
2016-04-14 3:45 ` Yunhui Cui
1 sibling, 0 replies; 6+ messages in thread
From: Yunhui Cui @ 2016-03-21 8:08 UTC (permalink / raw)
To: Bean Huo 霍斌斌 (beanhuo), Yunhui Cui
Cc: linux-mtd, dwmw2, computersforpeace, han.xu, linux-kernel,
linux-mtd, linux-arm-kernel, Yao Yuan
Hi Bean,
I tested with flash N25Q128A again.
In fact, It must output "Micron EVCR Quad bit not clear" in spi-nor.c, if the status register write enable/disable bit is set.
Could you give some suggestions about this ?
Thanks
Yunhui
-----Original Message-----
From: Bean Huo 霍斌斌 (beanhuo) [mailto:beanhuo@micron.com]
Sent: Monday, March 21, 2016 10:56 AM
To: Yunhui Cui; Yunhui Cui
Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com; linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux-arm-kernel@lists.infradead.org; Yao Yuan
Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
Hi, Yunhai
You mean that EVCR.bit7 cannot clear(enable quad mode) if not write SR.bit7 to 0?
They don't have any connection each other.
> -----Original Message-----
> From: Yunhui Cui [mailto:yunhui.cui@nxp.com]
> Sent: Friday, March 18, 2016 6:09 PM
> To: Bean Huo 霍斌斌 (beanhuo); Yunhui Cui
> Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> computersforpeace@gmail.com; han.xu@freescale.com;
> linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; Yao Yuan
> Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> protection
>
> Hi Bean,
>
> Thanks for your suggestions very much.
> Yes, the flash N25Q128A status register write enable/disable bit is
> disable in initial state.
> But, This patch aims to clear status registerV bit[7](write
> enable/disable bit) to 0, which enables the bit.
> Frankly speaking, I also don't want to add this patch.
> The reason for this is that clear status register bit[7] to 0 is a
> must to set quad mode to Enhanced Volatile Configuration Register
> using command SPINOR_OP_WD_EVCR. Otherwise it will output "Micron EVCR
> Quad bit not clear" in spi-nor.c I looked up the datasheet, but I
> really don't find out any connection between status register
> bit[7](write enable/disable bit) equals 0 and seting quad mode to Enhanced Volatile Configuration Register.
>
> Just as I want to send the issue to Micron team , could you give me
> some solutions ?
>
>
> Thanks
> Yunhui
>
> -----Original Message-----
> From: Bean Huo 霍斌斌 (beanhuo) [mailto:beanhuo@micron.com]
> Sent: Thursday, March 03, 2016 9:39 PM
> To: Yunhui Cui
> Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> computersforpeace@gmail.com; han.xu@freescale.com;
> linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui
> Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> protection
>
> > From: Yunhui Cui <B56489@freescale.com>
> > To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> > <han.xu@freescale.com>
> > Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> > <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui
> > Cui
> > <yunhui.cui@nxp.com>
> > Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> > protection
> > Message-ID:
> <1456988044-37061-4-git-send-email-B56489@freescale.com>
> > Content-Type: text/plain
> >
> > From: Yunhui Cui <yunhui.cui@nxp.com>
> >
> > For Micron family ,The status register write enable/disable bit,
> > provides hardware data protection for the device.
> > When the enable/disable bit is set to 1, the status register
> > nonvolatile bits become read-only and the WRITE STATUS REGISTER
> > operation will not execute.
> >
> > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> > ---
> > drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..917f814 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -39,6 +39,7 @@
> >
> > #define SPI_NOR_MAX_ID_LEN 6
> > #define SPI_NOR_MAX_ADDR_WIDTH 4
> > +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
> >
> > struct flash_info {
> > char *name;
> > @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const
> > char *name, enum read_mode mode)
> > write_sr(nor, 0);
> > }
> >
> > + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> > + ret = read_sr(nor);
> > + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> > +
> For Micron the status register write enable/disable bit, its
> default/factory value is disable.
> Can here first check ,then program?
> > + write_enable(nor);
> > + write_sr(nor, ret);
> > + }
> > +
> > if (!mtd->name)
> > mtd->name = dev_name(dev);
> > mtd->priv = nor;
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
2016-03-21 2:55 ` Bean Huo 霍斌斌 (beanhuo)
2016-03-21 8:08 ` Yunhui Cui
@ 2016-04-14 3:45 ` Yunhui Cui
1 sibling, 0 replies; 6+ messages in thread
From: Yunhui Cui @ 2016-04-14 3:45 UTC (permalink / raw)
To: Bean Huo 霍斌斌 (beanhuo),
linux-mtd, dwmw2, computersforpeace, han.xu
Cc: Yunhui Cui, Yao Yuan, linux-kernel, linux-mtd, linux-arm-kernel
Hi all,
I will send another patch set to replace this patch set. This patch set need not be reviewed more, Many thanks!
Thanks
Yunhui
-----Original Message-----
From: Bean Huo 霍斌斌 (beanhuo) [mailto:beanhuo@micron.com]
Sent: Monday, March 21, 2016 10:56 AM
To: Yunhui Cui; Yunhui Cui
Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com; linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux-arm-kernel@lists.infradead.org; Yao Yuan
Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
Hi, Yunhai
You mean that EVCR.bit7 cannot clear(enable quad mode) if not write SR.bit7 to 0?
They don't have any connection each other.
> -----Original Message-----
> From: Yunhui Cui [mailto:yunhui.cui@nxp.com]
> Sent: Friday, March 18, 2016 6:09 PM
> To: Bean Huo 霍斌斌 (beanhuo); Yunhui Cui
> Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> computersforpeace@gmail.com; han.xu@freescale.com;
> linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; Yao Yuan
> Subject: RE: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> protection
>
> Hi Bean,
>
> Thanks for your suggestions very much.
> Yes, the flash N25Q128A status register write enable/disable bit is
> disable in initial state.
> But, This patch aims to clear status registerV bit[7](write
> enable/disable bit) to 0, which enables the bit.
> Frankly speaking, I also don't want to add this patch.
> The reason for this is that clear status register bit[7] to 0 is a
> must to set quad mode to Enhanced Volatile Configuration Register
> using command SPINOR_OP_WD_EVCR. Otherwise it will output "Micron EVCR
> Quad bit not clear" in spi-nor.c I looked up the datasheet, but I
> really don't find out any connection between status register
> bit[7](write enable/disable bit) equals 0 and seting quad mode to Enhanced Volatile Configuration Register.
>
> Just as I want to send the issue to Micron team , could you give me
> some solutions ?
>
>
> Thanks
> Yunhui
>
> -----Original Message-----
> From: Bean Huo 霍斌斌 (beanhuo) [mailto:beanhuo@micron.com]
> Sent: Thursday, March 03, 2016 9:39 PM
> To: Yunhui Cui
> Cc: linux-mtd@lists.infradead.org; dwmw2@infradead.org;
> computersforpeace@gmail.com; han.xu@freescale.com;
> linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui
> Subject: Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> protection
>
> > From: Yunhui Cui <B56489@freescale.com>
> > To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> > <han.xu@freescale.com>
> > Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> > <linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui
> > Cui
> > <yunhui.cui@nxp.com>
> > Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> > protection
> > Message-ID:
> <1456988044-37061-4-git-send-email-B56489@freescale.com>
> > Content-Type: text/plain
> >
> > From: Yunhui Cui <yunhui.cui@nxp.com>
> >
> > For Micron family ,The status register write enable/disable bit,
> > provides hardware data protection for the device.
> > When the enable/disable bit is set to 1, the status register
> > nonvolatile bits become read-only and the WRITE STATUS REGISTER
> > operation will not execute.
> >
> > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> > ---
> > drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..917f814 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -39,6 +39,7 @@
> >
> > #define SPI_NOR_MAX_ID_LEN 6
> > #define SPI_NOR_MAX_ADDR_WIDTH 4
> > +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
> >
> > struct flash_info {
> > char *name;
> > @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const
> > char *name, enum read_mode mode)
> > write_sr(nor, 0);
> > }
> >
> > + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> > + ret = read_sr(nor);
> > + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> > +
> For Micron the status register write enable/disable bit, its
> default/factory value is disable.
> Can here first check ,then program?
> > + write_enable(nor);
> > + write_sr(nor, ret);
> > + }
> > +
> > if (!mtd->name)
> > mtd->name = dev_name(dev);
> > mtd->priv = nor;
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
2016-03-03 6:54 [PATCH v3 1/4] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
@ 2016-03-03 6:54 ` Yunhui Cui
0 siblings, 0 replies; 6+ messages in thread
From: Yunhui Cui @ 2016-03-03 6:54 UTC (permalink / raw)
To: dwmw2, computersforpeace, han.xu
Cc: linux-kernel, linux-mtd, linux-arm-kernel, yao.yuan, Yunhui Cui
From: Yunhui Cui <yunhui.cui@nxp.com>
For Micron family ,The status register write enable/disable bit,
provides hardware data protection for the device.
When the enable/disable bit is set to 1, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index ed0c19c..917f814 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -39,6 +39,7 @@
#define SPI_NOR_MAX_ID_LEN 6
#define SPI_NOR_MAX_ADDR_WIDTH 4
+#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
struct flash_info {
char *name;
@@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
write_sr(nor, 0);
}
+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
+ ret = read_sr(nor);
+ ret &= SPI_NOR_MICRON_WRITE_ENABLE;
+
+ write_enable(nor);
+ write_sr(nor, ret);
+ }
+
if (!mtd->name)
mtd->name = dev_name(dev);
mtd->priv = nor;
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-04-14 4:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-03 13:39 [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Bean Huo 霍斌斌 (beanhuo)
2016-03-18 10:08 ` Yunhui Cui
2016-03-21 2:55 ` Bean Huo 霍斌斌 (beanhuo)
2016-03-21 8:08 ` Yunhui Cui
2016-04-14 3:45 ` Yunhui Cui
-- strict thread matches above, loose matches on Subject: below --
2016-03-03 6:54 [PATCH v3 1/4] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
2016-03-03 6:54 ` [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Yunhui Cui
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