RE: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property

[Wei Fang <wei.fang@nxp.com>]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 2022年8月19日 17:14
> To: Wei Fang <wei.fang@nxp.com>; davem@davemloft.net;
> edumazet@google.com; kuba@kernel.org; pabeni@redhat.com;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; andrew@lunn.ch;
> f.fainelli@gmail.com; hkallweit1@gmail.com; linux@armlinux.org.uk
> Cc: netdev@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in
> property
> 
> On 19/08/2022 10:47, wei.fang@nxp.com wrote:
> > From: Wei Fang <wei.fang@nxp.com>
> >
> > TJA110x REF_CLK can be configured as interface reference clock intput
> > or output when the RMII mode enabled. This patch add the property to
> > make the REF_CLK can be configurable.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> > ---
> >  .../devicetree/bindings/net/nxp,tja11xx.yaml    | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > index d51da24f3505..c51ee52033e8 100644
> > --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > @@ -31,6 +31,22 @@ patternProperties:
> >          description:
> >            The ID number for the child PHY. Should be +1 of parent PHY.
> >
> > +      nxp,rmii_refclk_in:
> 
> No underscores in properties.
> 
Sorry, It's first time for me to know this.

> > +        type: boolean
> > +        description: |
> > +          The REF_CLK is provided for both transmitted and receivced
> > + data
> 
> typo: received
> 
> > +          in RMII mode. This clock signal is provided by the PHY and is
> > +          typically derived from an external 25MHz crystal. Alternatively,
> > +          a 50MHz clock signal generated by an external oscillator can be
> > +          connected to pin REF_CLK. A third option is to connect a 25MHz
> > +          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
> > +          as input or output according to the actual circuit connection.
> > +          If present, indicates that the REF_CLK will be configured as
> > +          interface reference clock input when RMII mode enabled.
> > +          If not present, the REF_CLK will be configured as interface
> > +          reference clock output when RMII mode enabled.
> > +          Only supported on TJA1100 and TJA1101.
> 
> Then disallow it on other variants.
> 
> Shouldn't this be just "clocks" property?
> 
> 
This property is to configure the pin REF_CLK of PHY as a input pin through phy register,
indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a
"clock" property.