[PATCH 0/9] dt-bindings: crypto: convert fsl-sec4 to DT schema

[PATCH 0/9] dt-bindings: crypto: convert fsl-sec4 to DT schema

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

This is effort towards SystemReady IR 2.0 to convert the txt binding to DT
schema.
Patch 1 is just to drop uneeded number since following DT schema will update the name

The fsl-sec4.txt binding has two parts, one is crypto, one is snvs, so I split
into two DT schema file. patch 2,3 is for crypto, patch 4,5,6 is for snvs,
patch 7 is to drop fsl-sec4.txt binding. patch 8,9 is to add new node

Peng Fan (9):
  ARM: dts: vfxxx: drop the number after jr
  dt-bindings: crypto: fsl-sec4: convert to DT schema
  dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL
  dt-bindings: crypto: add fsl-sec4-snvs DT schema
  dt-bindings: crypto: fsl-sec4-snvs: add simple-mfd compatible
  dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible
  dt-bindings: crypto: drop fsl-sec4 txt binding
  dt-bindings: crypto: fsl-sec4-snvs: add snvs-lpgpr support
  dt-bindings: crypto: fsl-sec4-snvs: add poweroff support

 .../bindings/crypto/fsl-sec4-snvs.yaml        | 181 ++++++
 .../devicetree/bindings/crypto/fsl-sec4.txt   | 553 ------------------
 .../devicetree/bindings/crypto/fsl-sec4.yaml  | 366 ++++++++++++
 arch/arm/boot/dts/vfxxx.dtsi                  |   4 +-
 4 files changed, 549 insertions(+), 555 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
 delete mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.txt
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.yaml

-- 
2.37.1

[PATCH 1/9] ARM: dts: vfxxx: drop the number after jr

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Drop the number after jr.  Use jr@xxxx, instead jr[0,1]@xxxx, and
the DT schema will reflect it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/boot/dts/vfxxx.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index ff4479994b60..61ab76c43a11 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -735,13 +735,13 @@ crypto: crypto@400f0000 {
 				clocks = <&clks VF610_CLK_CAAM>;
 				clock-names = "ipg";
 
-				sec_jr0: jr0@1000 {
+				sec_jr0: jr@1000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
 				};
 
-				sec_jr1: jr1@2000 {
+				sec_jr1: jr@2000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x2000 0x1000>;
 					interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.37.1

[PATCH 2/9] dt-bindings: crypto: fsl-sec4: convert to DT schema

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Convert the fsl-sec4 binding to DT schema

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../devicetree/bindings/crypto/fsl-sec4.yaml  | 324 ++++++++++++++++++
 1 file changed, 324 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.yaml

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
new file mode 100644
index 000000000000..678c8389ef49
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
@@ -0,0 +1,324 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-sec4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP SEC4 Crypto Binding
+
+description:
+  CONTENTS
+    -Overview
+    -SEC 4 Node
+    -Job Ring Node
+    -Run Time Integrity Check (RTIC) Node
+    -Run Time Integrity Check (RTIC) Memory Node
+  NOTE, the SEC 4 is also known as Freescale's Cryptographic Accelerator
+  Accelerator and Assurance Module (CAAM).
+  For information on SEC4 SNVS, ref fsl-sec4-snvs.yaml
+
+  =====================================================================
+  Overview
+
+  DESCRIPTION
+
+  SEC 4 h/w can process requests from 2 types of sources.
+  1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
+  2. Job Rings (HW interface between cores & SEC 4 registers).
+
+  High Speed Data Path Configuration,
+
+  HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
+  such as the P4080.  The number of simultaneous dequeues the QI can make is
+  equal to the number of Descriptor Controller (DECO) engines in a particular
+  SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
+  dequeue from 5 subportals simultaneously.
+
+  Job Ring Data Path Configuration,
+
+  Each JR is located on a separate 4k page, they may (or may not) be made visible
+  in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
+  up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
+
+maintainers:
+  - Peng Fan <peng.fan@nxp.com>
+
+properties:
+  compatible:
+    enum:
+      - fsl,sec-v4.0
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  ranges:
+    description:
+      A standard property. Specifies the physical address range of the SEC
+      4.0 register space (-SNVS not included).  A triplet that includes the
+      child address, parent address, & length.
+
+  interrupts:
+    description:
+      Specifies the interrupts generated by this device.  The value of the
+      interrupts property consists of one interrupt specifier. The format
+      of the specifier is defined by the binding document describing the
+      node's interrupt parent.
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    oneOf:
+      - items:
+          - const: mem
+          - const: aclk
+          - const: ipg
+          - const: emi_slow
+      - items:
+          - const: aclk
+          - const: ipg
+      - items:
+          - const: ipg
+          - const: aclk
+          - const: mem
+
+  fsl,sec-era:
+    description:
+      Optional. A standard property. Define the 'ERA' of the SEC device.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+  "jr@[0-9a-f]+$":
+    type: object
+    description:
+      Child of the crypto node defines data processing interface to SEC 4
+      across the peripheral bus for purposes of processing
+      cryptographic descriptors. The specified address
+      range can be made visible to one (or more) cores.
+      The interrupt defined for this node is controlled within
+      the address range of this node.
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-job-ring
+
+      reg:
+        maxItems: 1
+
+      interrupts:
+        description:
+          Specifies the interrupts generated by this device.  The value of the
+          interrupts property consists of one interrupt specifier. The format
+          of the specifier is defined by the binding document describing the
+          node's interrupt parent.
+        maxItems: 1
+
+      fsl,liodn:
+        description:
+          Specifies the LIODN to be used in conjunction with the ppid-to-liodn
+          table that specifies the PPID to LIODN mapping. Needed if the PAMU
+          is used.  Value is a 12 bit value where value is a LIODN ID for this
+          JR. This property is normally set by boot firmware.
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        maximum: 0x1
+
+    required:
+      - compatible
+      - reg
+      - interrupts
+
+  "rtic@[0-9a-f]+$":
+    type: object
+    description:
+      Run Time Integrity Check (RTIC) Node. Child node of the crypto node.
+      Defines a register space that contains up to 5 sets of addresses and
+      their lengths (sizes) that will be checked at run time.  After an
+      initial hash result is calculated, these addresses are checked by HW
+      to monitor any change.  If any memory is modified, a Security Violation
+      is triggered (see SNVS definition).
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-rtic
+
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 1
+
+      reg:
+        minItems: 1
+        maxItems: 2
+
+      ranges:
+        description:
+          A standard property.  Specifies the physical address range of the
+          SEC 4 register space (-SNVS not included).  A triplet that includes
+          the child address, parent address, & length.
+
+    required:
+      - compatible
+      - reg
+      - "#address-cells"
+      - "#size-cells"
+      - ranges
+
+    patternProperties:
+      "rtic-[a-f]@[0-9]+$":
+        type: object
+        description:
+          Run Time Integrity Check (RTIC) Memory Node. A child node that
+          defines individual RTIC memory regions that are used to perform
+          run-time integrity check of memory areas that should not modified.
+          The node defines a register that contains the memory address &
+          length (combined) and a second register that contains the hash
+          result in big endian format.
+
+        properties:
+          compatible:
+            enum:
+              - fsl,sec-v4.0-rtic-memory
+
+          reg:
+            minItems: 1
+            maxItems: 2
+
+          fsl,rtic-region:
+            description:
+              Specifies the HW address (36 bit address) for this region
+              followed by the length of the HW partition to be checked;
+              the address is represented as a 64 bit quantity followed
+              by a 32 bit length.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 1
+            maxItems: 3
+
+          fsl,liodn:
+            description:
+              Specifies the LIODN to be used in conjunction with
+              the ppid-to-liodn table that specifies the PPID to LIODN
+              mapping.  Needed if the PAMU is used.  Value is a 12 bit value
+              where value is a LIODN ID for this RTIC memory region. This
+              property is normally set by boot firmware.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 1
+            maxItems: 3
+
+        required:
+          - compatible
+          - reg
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  # iMX6QDL/SX requires four clocks
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx6qdl-clock.h>
+
+    crypto@300000 {
+        compatible = "fsl,sec-v4.0";
+        fsl,sec-era = <2>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x300000 0x10000>;
+        ranges = <0 0x300000 0x10000>;
+        interrupt-parent = <&mpic>;
+        interrupts = <92 2>;
+        clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+                 <&clks IMX6QDL_CLK_CAAM_ACLK>,
+                 <&clks IMX6QDL_CLK_CAAM_IPG>,
+                 <&clks IMX6QDL_CLK_EIM_SLOW>;
+        clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+        sec_jr0: jr@1000 {
+            compatible = "fsl,sec-v4.0-job-ring";
+            reg = <0x1000 0x1000>;
+            interrupt-parent = <&mpic>;
+            interrupts = <88 2>;
+        };
+
+        sec_jr1: jr@2000 {
+           compatible = "fsl,sec-v4.0-job-ring";
+           reg = <0x2000 0x1000>;
+           interrupt-parent = <&mpic>;
+           interrupts = <89 2>;
+        };
+
+        sec_jr2: jr@3000 {
+          compatible = "fsl,sec-v4.0-job-ring";
+          reg = <0x3000 0x1000>;
+          interrupt-parent = <&mpic>;
+          interrupts = <90 2>;
+        };
+
+        sec_jr3: jr@4000 {
+           compatible = "fsl,sec-v4.0-job-ring";
+           reg = <0x4000 0x1000>;
+           interrupt-parent = <&mpic>;
+           interrupts = <91 2>;
+        };
+
+        rtic@6000 {
+            compatible = "fsl,sec-v4.0-rtic";
+            #address-cells = <1>;
+            #size-cells = <1>;
+            reg = <0x6000 0x100>;
+            ranges = <0x0 0x6100 0xe00>;
+
+            rtic_a: rtic-a@0 {
+               compatible = "fsl,sec-v4.0-rtic-memory";
+               reg = <0x00 0x20 0x100 0x80>;
+            };
+
+            rtic_b: rtic-b@20 {
+                compatible = "fsl,sec-v4.0-rtic-memory";
+                reg = <0x20 0x20 0x200 0x80>;
+            };
+
+            rtic_c: rtic-c@40 {
+                compatible = "fsl,sec-v4.0-rtic-memory";
+                reg = <0x40 0x20 0x300 0x80>;
+            };
+
+            rtic_d: rtic-d@60 {
+                compatible = "fsl,sec-v4.0-rtic-memory";
+                reg = <0x60 0x20 0x500 0x80>;
+            };
+        };
+    };
+
+  # iMX6UL does only require three clocks
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx6ul-clock.h>
+
+    crypto: crypto@2140000 {
+        compatible = "fsl,sec-v4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x2140000 0x3c000>;
+        ranges = <0 0x2140000 0x3c000>;
+        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+
+        clocks = <&clks IMX6UL_CLK_CAAM_IPG>,
+                 <&clks IMX6UL_CLK_CAAM_ACLK>,
+                 <&clks IMX6UL_CLK_CAAM_MEM>;
+        clock-names = "ipg", "aclk", "mem";
+    };
+...
-- 
2.37.1

Re: [PATCH 2/9] dt-bindings: crypto: fsl-sec4: convert to DT schema

[Krzysztof Kozlowski]

On 01/03/2023 02:56, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Convert the fsl-sec4 binding to DT schema

I don't see the removal part of conversion.

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../devicetree/bindings/crypto/fsl-sec4.yaml  | 324 ++++++++++++++++++
>  1 file changed, 324 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.yaml

Filename matching compatible.

> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> new file mode 100644
> index 000000000000..678c8389ef49
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> @@ -0,0 +1,324 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/fsl-sec4.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP SEC4 Crypto Binding

Drop "Binding"

> +
> +description:
> +  CONTENTS
> +    -Overview
> +    -SEC 4 Node
> +    -Job Ring Node
> +    -Run Time Integrity Check (RTIC) Node
> +    -Run Time Integrity Check (RTIC) Memory Node

????

> +  NOTE, the SEC 4 is also known as Freescale's Cryptographic Accelerator
> +  Accelerator and Assurance Module (CAAM).
> +  For information on SEC4 SNVS, ref fsl-sec4-snvs.yaml
> +
> +  =====================================================================
> +  Overview
> +
> +  DESCRIPTION

Reformat it to look like normal text. Drop "====", fix title case.

> +
> +  SEC 4 h/w can process requests from 2 types of sources.
> +  1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
> +  2. Job Rings (HW interface between cores & SEC 4 registers).
> +
> +  High Speed Data Path Configuration,
> +
> +  HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
> +  such as the P4080.  The number of simultaneous dequeues the QI can make is
> +  equal to the number of Descriptor Controller (DECO) engines in a particular
> +  SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
> +  dequeue from 5 subportals simultaneously.
> +
> +  Job Ring Data Path Configuration,
> +
> +  Each JR is located on a separate 4k page, they may (or may not) be made visible
> +  in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
> +  up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
> +
> +maintainers:
> +  - Peng Fan <peng.fan@nxp.com>

Keep the order of properties like in example-schema.

> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,sec-v4.0
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +  ranges:
> +    description:
> +      A standard property. Specifies the physical address range of the SEC
> +      4.0 register space (-SNVS not included).  A triplet that includes the
> +      child address, parent address, & length.
> +
> +  interrupts:
> +    description:
> +      Specifies the interrupts generated by this device.  The value of the
> +      interrupts property consists of one interrupt specifier. The format
> +      of the specifier is defined by the binding document describing the
> +      node's interrupt parent.
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +
> +  clock-names:
> +    oneOf:
> +      - items:
> +          - const: mem
> +          - const: aclk
> +          - const: ipg
> +          - const: emi_slow
> +      - items:
> +          - const: aclk
> +          - const: ipg
> +      - items:
> +          - const: ipg
> +          - const: aclk
> +          - const: mem
> +
> +  fsl,sec-era:
> +    description:
> +      Optional. A standard property. Define the 'ERA' of the SEC device.

Drop redundant, free form text - optional.

What is a "standard property"? So all others are non-standard? They
violate standard? What does it mean?

I will actually skip the review as I really do not know if this is new
binding all conversion.

(...)

> +
> +required:
> +  - compatible
> +  - reg
> +
> +unevaluatedProperties: false

additionalProperties instead


Best regards,
Krzysztof

[PATCH 3/9] dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add i.MX6UL, SEC 5.0 and SEC 5.4 support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../devicetree/bindings/crypto/fsl-sec4.yaml  | 58 ++++++++++++++++---
 1 file changed, 50 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
index 678c8389ef49..1b801ae5ab51 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
@@ -45,8 +45,18 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - fsl,sec-v4.0
+    oneOf:
+      - enum:
+          - fsl,sec-v4.0
+      - items:
+          - enum:
+              - fsl,imx6ul-caam
+              - fsl,sec-v5.0
+          - const: fsl,sec-v4.0
+      - items:
+          - const: fsl,sec-v5.4
+          - const: fsl,sec-v5.0
+          - const: fsl,sec-v4.0
 
   "#address-cells":
     const: 1
@@ -77,6 +87,8 @@ properties:
 
   clock-names:
     oneOf:
+      - items:
+          - const: ipg
       - items:
           - const: mem
           - const: aclk
@@ -85,11 +97,17 @@ properties:
       - items:
           - const: aclk
           - const: ipg
+      - items:
+          - const: ipg
+          - const: aclk
       - items:
           - const: ipg
           - const: aclk
           - const: mem
 
+  dma-coherent:
+    type: boolean
+
   fsl,sec-era:
     description:
       Optional. A standard property. Define the 'ERA' of the SEC device.
@@ -108,8 +126,16 @@ patternProperties:
 
     properties:
       compatible:
-        enum:
-          - fsl,sec-v4.0-job-ring
+        oneOf:
+          - enum:
+              - fsl,sec-v4.0-job-ring
+          - items:
+              - const: fsl,sec-v5.0-job-ring
+              - const: fsl,sec-v4.0-job-ring
+          - items:
+              - const: fsl,sec-v5.4-job-ring
+              - const: fsl,sec-v5.0-job-ring
+              - const: fsl,sec-v4.0-job-ring
 
       reg:
         maxItems: 1
@@ -148,8 +174,16 @@ patternProperties:
 
     properties:
       compatible:
-        enum:
-          - fsl,sec-v4.0-rtic
+        oneOf:
+          - enum:
+              - fsl,sec-v4.0-rtic
+          - items:
+              - const: fsl,sec-v5.0-rtic
+              - const: fsl,sec-v4.0-rtic
+          - items:
+              - const: fsl,sec-v5.4-rtic
+              - const: fsl,sec-v5.0-rtic
+              - const: fsl,sec-v4.0-rtic
 
       "#address-cells":
         const: 1
@@ -187,8 +221,16 @@ patternProperties:
 
         properties:
           compatible:
-            enum:
-              - fsl,sec-v4.0-rtic-memory
+            oneOf:
+              - enum:
+                  - fsl,sec-v4.0-rtic-memory
+              - items:
+                  - const: fsl,sec-v5.0-rtic-memory
+                  - const: fsl,sec-v4.0-rtic-memory
+              - items:
+                  - const: fsl,sec-v5.4-rtic-memory
+                  - const: fsl,sec-v5.0-rtic-memory
+                  - const: fsl,sec-v4.0-rtic-memory
 
           reg:
             minItems: 1
-- 
2.37.1

Re: [PATCH 3/9] dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL

[Krzysztof Kozlowski]

On 01/03/2023 02:56, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add i.MX6UL, SEC 5.0 and SEC 5.4 support.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../devicetree/bindings/crypto/fsl-sec4.yaml  | 58 ++++++++++++++++---
>  1 file changed, 50 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> index 678c8389ef49..1b801ae5ab51 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> @@ -45,8 +45,18 @@ maintainers:
>  
>  properties:
>    compatible:
> -    enum:
> -      - fsl,sec-v4.0
> +    oneOf:
> +      - enum:
> +          - fsl,sec-v4.0
> +      - items:
> +          - enum:
> +              - fsl,imx6ul-caam
> +              - fsl,sec-v5.0
> +          - const: fsl,sec-v4.0
> +      - items:
> +          - const: fsl,sec-v5.4
> +          - const: fsl,sec-v5.0

What's the point of having all these versions? Better to use
SoC-compatibles.

> +          - const: fsl,sec-v4.0
>  
>    "#address-cells":
>      const: 1
> @@ -77,6 +87,8 @@ properties:
>  
>    clock-names:
>      oneOf:
> +      - items:
> +          - const: ipg
>        - items:
>            - const: mem
>            - const: aclk
> @@ -85,11 +97,17 @@ properties:
>        - items:
>            - const: aclk
>            - const: ipg
> +      - items:
> +          - const: ipg
> +          - const: aclk
>        - items:
>            - const: ipg
>            - const: aclk
>            - const: mem
>  
> +  dma-coherent:
> +    type: boolean
> +
>    fsl,sec-era:
>      description:
>        Optional. A standard property. Define the 'ERA' of the SEC device.
> @@ -108,8 +126,16 @@ patternProperties:
>  
>      properties:
>        compatible:
> -        enum:
> -          - fsl,sec-v4.0-job-ring
> +        oneOf:
> +          - enum:
> +              - fsl,sec-v4.0-job-ring
> +          - items:
> +              - const: fsl,sec-v5.0-job-ring
> +              - const: fsl,sec-v4.0-job-ring
> +          - items:
> +              - const: fsl,sec-v5.4-job-ring
> +              - const: fsl,sec-v5.0-job-ring
> +              - const: fsl,sec-v4.0-job-ring
>  
>        reg:
>          maxItems: 1
> @@ -148,8 +174,16 @@ patternProperties:
>  
>      properties:
>        compatible:
> -        enum:
> -          - fsl,sec-v4.0-rtic
> +        oneOf:
> +          - enum:
> +              - fsl,sec-v4.0-rtic
> +          - items:
> +              - const: fsl,sec-v5.0-rtic
> +              - const: fsl,sec-v4.0-rtic
> +          - items:
> +              - const: fsl,sec-v5.4-rtic
> +              - const: fsl,sec-v5.0-rtic
> +              - const: fsl,sec-v4.0-rtic

This is also a bit odd... why do you version children?

Best regards,
Krzysztof

RE: [PATCH 3/9] dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL

[Gaurav Jain]

> -----Original Message-----
> From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> Sent: Wednesday, March 1, 2023 7:27 AM
> To: herbert@gondor.apana.org.au; davem@davemloft.net;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; Horia Geanta
> <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Gaurav Jain
> <gaurav.jain@nxp.com>; shawnguo@kernel.org; s.hauer@pengutronix.de
> Cc: kernel@pengutronix.de; stefan@agner.ch; linux-crypto@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Peng Fan <peng.fan@nxp.com>
> Subject: [PATCH 3/9] dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL
> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add i.MX6UL, SEC 5.0 and SEC 5.4 support.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../devicetree/bindings/crypto/fsl-sec4.yaml  | 58 ++++++++++++++++---
>  1 file changed, 50 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> index 678c8389ef49..1b801ae5ab51 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> @@ -45,8 +45,18 @@ maintainers:
> 
>  properties:
>    compatible:
> -    enum:
> -      - fsl,sec-v4.0
> +    oneOf:
> +      - enum:
> +          - fsl,sec-v4.0
> +      - items:
> +          - enum:
> +              - fsl,imx6ul-caam
> +              - fsl,sec-v5.0
> +          - const: fsl,sec-v4.0
> +      - items:
> +          - const: fsl,sec-v5.4
> +          - const: fsl,sec-v5.0
> +          - const: fsl,sec-v4.0

fsl,sec-v5.2, fsl,sec-v5.3, fsl,sec-v6.0 also used in Qoriq

regards
Gaurav 
> 
>    "#address-cells":
>      const: 1
> @@ -77,6 +87,8 @@ properties:
> 
>    clock-names:
>      oneOf:
> +      - items:
> +          - const: ipg
>        - items:
>            - const: mem
>            - const: aclk
> @@ -85,11 +97,17 @@ properties:
>        - items:
>            - const: aclk
>            - const: ipg
> +      - items:
> +          - const: ipg
> +          - const: aclk
>        - items:
>            - const: ipg
>            - const: aclk
>            - const: mem
> 
> +  dma-coherent:
> +    type: boolean
> +
>    fsl,sec-era:
>      description:
>        Optional. A standard property. Define the 'ERA' of the SEC device.
> @@ -108,8 +126,16 @@ patternProperties:
> 
>      properties:
>        compatible:
> -        enum:
> -          - fsl,sec-v4.0-job-ring
> +        oneOf:
> +          - enum:
> +              - fsl,sec-v4.0-job-ring
> +          - items:
> +              - const: fsl,sec-v5.0-job-ring
> +              - const: fsl,sec-v4.0-job-ring
> +          - items:
> +              - const: fsl,sec-v5.4-job-ring
> +              - const: fsl,sec-v5.0-job-ring
> +              - const: fsl,sec-v4.0-job-ring
> 
>        reg:
>          maxItems: 1
> @@ -148,8 +174,16 @@ patternProperties:
> 
>      properties:
>        compatible:
> -        enum:
> -          - fsl,sec-v4.0-rtic
> +        oneOf:
> +          - enum:
> +              - fsl,sec-v4.0-rtic
> +          - items:
> +              - const: fsl,sec-v5.0-rtic
> +              - const: fsl,sec-v4.0-rtic
> +          - items:
> +              - const: fsl,sec-v5.4-rtic
> +              - const: fsl,sec-v5.0-rtic
> +              - const: fsl,sec-v4.0-rtic
> 
>        "#address-cells":
>          const: 1
> @@ -187,8 +221,16 @@ patternProperties:
> 
>          properties:
>            compatible:
> -            enum:
> -              - fsl,sec-v4.0-rtic-memory
> +            oneOf:
> +              - enum:
> +                  - fsl,sec-v4.0-rtic-memory
> +              - items:
> +                  - const: fsl,sec-v5.0-rtic-memory
> +                  - const: fsl,sec-v4.0-rtic-memory
> +              - items:
> +                  - const: fsl,sec-v5.4-rtic-memory
> +                  - const: fsl,sec-v5.0-rtic-memory
> +                  - const: fsl,sec-v4.0-rtic-memory
> 
>            reg:
>              minItems: 1
> --
> 2.37.1

[PATCH 4/9] dt-bindings: crypto: add fsl-sec4-snvs DT schema

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Convert fsl-sec4.txt SNVS RTC and PowerKey to DT schema

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../bindings/crypto/fsl-sec4-snvs.yaml        | 153 ++++++++++++++++++
 1 file changed, 153 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
new file mode 100644
index 000000000000..633e70f9b303
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-sec4-snvs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP SEC4 SNVS Binding
+
+description:
+  CONTENTS
+    -Secure Non-Volatile Storage (SNVS) Node
+    -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
+
+  Node defines address range and the associated interrupt for the SNVS
+  function.  This function monitors security state information & reports
+  security violations. This also included rtc, system power off and ON/OFF
+  key.
+
+  For more information on SEC4, ref fsl-sec4-crypto.yaml
+
+maintainers:
+  - Peng Fan <peng.fan@nxp.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: fsl,sec-v4.0-mon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges:
+    description:
+      A standard property. Specifies the physical address range of the SNVS
+      register space.  A triplet that includes the child address, parent
+      address, & length.
+
+  interrupts:
+    description:
+      Specifies the interrupts generated by this device.  The value of the
+      interrupts property consists of one interrupt specifier. The format
+      of the specifier is defined by the binding document describing the
+      node's interrupt parent.
+    minItems: 1
+    maxItems: 2
+
+  snvs-rtc-lp:
+    type: object
+    description:
+      Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node. A SNVS
+      child node that defines SNVS LP RTC.
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-mon-rtc-lp
+
+      interrupts:
+        minItems: 1
+        maxItems: 2
+
+      regmap:
+        description: This is phandle to the register map node.
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+      offset:
+        description: LP register offset. default it is 0x34.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      clocks:
+        maxItems: 1
+
+      clock-names:
+        items:
+          - const: snvs-rtc
+
+    required:
+      - compatible
+      - interrupts
+      - regmap
+
+  snvs-powerkey:
+    type: object
+    description:
+      The snvs-pwrkey is designed to enable POWER key function which
+      controlled by SNVS ONOFF, the driver can report the status of POWER
+      key and wakeup system if pressed after system suspend.
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-pwrkey
+
+      interrupts:
+        description: The SNVS ON/OFF interrupt number to the CPU(s).
+        maxItems: 1
+
+      linux,keycode:
+        description: Keycode to emit, KEY_POWER by default.
+        $ref: /schemas/types.yaml#/definitions/int32
+
+      regmap:
+        description: This is phandle to the register map node.
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+      wakeup-source:
+        description: Button can wake-up the system.
+        type: boolean
+
+    required:
+      - compatible
+      - interrupts
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx7d-clock.h>
+    sec_mon: sec_mon@314000 {
+        compatible = "fsl,sec-v4.0-mon", "syscon";
+        reg = <0x314000 0x1000>;
+
+        snvs-rtc-lp {
+            compatible = "fsl,sec-v4.0-mon-rtc-lp";
+            regmap = <&sec_mon>;
+            offset = <0x34>;
+            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clks IMX7D_SNVS_CLK>;
+            clock-names = "snvs-rtc";
+        };
+
+        snvs-powerkey {
+            compatible = "fsl,sec-v4.0-pwrkey";
+            regmap = <&sec_mon>;
+            interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+            linux,keycode = <116>; /* KEY_POWER */
+            wakeup-source;
+        };
+    };
-- 
2.37.1

Re: [PATCH 4/9] dt-bindings: crypto: add fsl-sec4-snvs DT schema

[Rob Herring]

On Wed, 01 Mar 2023 09:56:57 +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Convert fsl-sec4.txt SNVS RTC and PowerKey to DT schema
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../bindings/crypto/fsl-sec4-snvs.yaml        | 153 ++++++++++++++++++
>  1 file changed, 153 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.example.dtb: snvs@20cc000: compatible: 'oneOf' conditional failed, one must be fixed:
	['fsl,sec-v4.0-mon', 'syscon', 'simple-mfd'] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.example.dtb: snvs@20cc000: Unevaluated properties are not allowed ('compatible', 'snvs-lpgpr' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230301015702.3388458-5-peng.fan@oss.nxp.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 4/9] dt-bindings: crypto: add fsl-sec4-snvs DT schema

[Krzysztof Kozlowski]

On 01/03/2023 02:56, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Convert fsl-sec4.txt SNVS RTC and PowerKey to DT schema

This is a mess. Subject says add, commit msg says convert and body does
what?

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../bindings/crypto/fsl-sec4-snvs.yaml        | 153 ++++++++++++++++++
>  1 file changed, 153 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> new file mode 100644
> index 000000000000..633e70f9b303
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml

Filename matching compatibles.

> @@ -0,0 +1,153 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/fsl-sec4-snvs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP SEC4 SNVS Binding

Drop Binding.


> +
> +description:
> +  CONTENTS
> +    -Secure Non-Volatile Storage (SNVS) Node
> +    -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node

OK, this is some copy-paste from some poor other code. Please fix all
your bindings like I mentioned in previous emails.

> +
> +  Node defines address range and the associated interrupt for the SNVS
> +  function.  This function monitors security state information & reports
> +  security violations. This also included rtc, system power off and ON/OFF
> +  key.
> +
> +  For more information on SEC4, ref fsl-sec4-crypto.yaml
> +
> +maintainers:
> +  - Peng Fan <peng.fan@nxp.com>
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: fsl,sec-v4.0-mon
> +          - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  ranges:
> +    description:
> +      A standard property. Specifies the physical address range of the SNVS

So the rest are non-standard properties?


> +      register space.  A triplet that includes the child address, parent
> +      address, & length.
> +
> +  interrupts:
> +    description:
> +      Specifies the interrupts generated by this device.  The value of the
> +      interrupts property consists of one interrupt specifier. The format
> +      of the specifier is defined by the binding document describing the
> +      node's interrupt parent.

Please point me to any useful information in this description. Anything
useful. All interrupts are generated from the devices, aren't they?

> +    minItems: 1
> +    maxItems: 2

No, you need to describe the items instead.

> +

(...)

> +    sec_mon: sec_mon@314000 {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

No underscores in node names.

> +        compatible = "fsl,sec-v4.0-mon", "syscon";
> +        reg = <0x314000 0x1000>;
> +
> +        snvs-rtc-lp {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +            compatible = "fsl,sec-v4.0-mon-rtc-lp";
> +            regmap = <&sec_mon>;
> +            offset = <0x34>;
> +            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> +            clocks = <&clks IMX7D_SNVS_CLK>;
> +            clock-names = "snvs-rtc";
> +        };
> +
> +        snvs-powerkey {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation



Best regards,
Krzysztof

[PATCH 5/9] dt-bindings: crypto: fsl-sec4-snvs: add simple-mfd compatible

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

All the current vfxxx and i.MX device tree has simple-mfd as compatible,
and it indeed supports RTC and ON/OFF key multi function, so add the
compatible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
index 633e70f9b303..6878ae8127ec 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
@@ -27,6 +27,7 @@ properties:
       - items:
           - const: fsl,sec-v4.0-mon
           - const: syscon
+          - const: simple-mfd
 
   reg:
     maxItems: 1
-- 
2.37.1

Re: [PATCH 5/9] dt-bindings: crypto: fsl-sec4-snvs: add simple-mfd compatible

[Krzysztof Kozlowski]

On 01/03/2023 02:56, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> All the current vfxxx and i.MX device tree has simple-mfd as compatible,
> and it indeed supports RTC and ON/OFF key multi function, so add the
> compatible.

Paste it to Google Doc or Google GMail (with extended language
spellcheck/suggestions) and fix the grammar, please. Can be also any
other service, dunno.


Best regards,
Krzysztof

[PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add fsl sec 5.x compatible, which is used by layerscape SoCs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
index 6878ae8127ec..1a4b4975e1d9 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
@@ -24,6 +24,10 @@ maintainers:
 properties:
   compatible:
     oneOf:
+      - items:
+          - const: fsl,sec-v5.4-mon
+          - const: fsl,sec-v5.0-mon
+          - const: fsl,sec-v4.0-mon
       - items:
           - const: fsl,sec-v4.0-mon
           - const: syscon
-- 
2.37.1

Re: [PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible

[Krzysztof Kozlowski]

On 01/03/2023 02:56, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add fsl sec 5.x compatible, which is used by layerscape SoCs.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> index 6878ae8127ec..1a4b4975e1d9 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> @@ -24,6 +24,10 @@ maintainers:
>  properties:
>    compatible:
>      oneOf:
> +      - items:
> +          - const: fsl,sec-v5.4-mon
> +          - const: fsl,sec-v5.0-mon
> +          - const: fsl,sec-v4.0-mon

This is odd... all of these are the same version then? What's the point
of having versionable compatibles if they are compatible?

Best regards,
Krzysztof

RE: [PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible

[Gaurav Jain]

> -----Original Message-----
> From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> Sent: Wednesday, March 1, 2023 7:27 AM
> To: herbert@gondor.apana.org.au; davem@davemloft.net;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; Horia Geanta
> <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Gaurav Jain
> <gaurav.jain@nxp.com>; shawnguo@kernel.org; s.hauer@pengutronix.de
> Cc: kernel@pengutronix.de; stefan@agner.ch; linux-crypto@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Peng Fan <peng.fan@nxp.com>
> Subject: [PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x
> compatible
> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add fsl sec 5.x compatible, which is used by layerscape SoCs.
I can see sec-v5.2-mon, sec-v5.3-mon for Qoriq.

Regards
Gaurav
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> index 6878ae8127ec..1a4b4975e1d9 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> @@ -24,6 +24,10 @@ maintainers:
>  properties:
>    compatible:
>      oneOf:
> +      - items:
> +          - const: fsl,sec-v5.4-mon
> +          - const: fsl,sec-v5.0-mon
> +          - const: fsl,sec-v4.0-mon
>        - items:
>            - const: fsl,sec-v4.0-mon
>            - const: syscon
> --
> 2.37.1

RE: [PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible

[Peng Fan]

> Subject: RE: [PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x
> compatible
> 
> 
> 
> > -----Original Message-----
> > From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> > Sent: Wednesday, March 1, 2023 7:27 AM
> > To: herbert@gondor.apana.org.au; davem@davemloft.net;
> > robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; Horia Geanta
> > <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>;
> Gaurav
> > Jain <gaurav.jain@nxp.com>; shawnguo@kernel.org;
> > s.hauer@pengutronix.de
> > Cc: kernel@pengutronix.de; stefan@agner.ch;
> > linux-crypto@vger.kernel.org; devicetree@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org;
> > Peng Fan <peng.fan@nxp.com>
> > Subject: [PATCH 6/9] dt-bindings: crypto: fsl-sec4-snvs: add fsl sec
> > 5.x compatible
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add fsl sec 5.x compatible, which is used by layerscape SoCs.
> I can see sec-v5.2-mon, sec-v5.3-mon for Qoriq.

Please go with Rob's patch which is earlier than my patchset.

https://lore.kernel.org/lkml/d4c76900-1985-428b-4050-26fd4a0daaf8@oss.nxp.com/T/

Thanks,
Peng.

> 
> Regards
> Gaurav
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> > b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> > index 6878ae8127ec..1a4b4975e1d9 100644
> > --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> > @@ -24,6 +24,10 @@ maintainers:
> >  properties:
> >    compatible:
> >      oneOf:
> > +      - items:
> > +          - const: fsl,sec-v5.4-mon
> > +          - const: fsl,sec-v5.0-mon
> > +          - const: fsl,sec-v4.0-mon
> >        - items:
> >            - const: fsl,sec-v4.0-mon
> >            - const: syscon
> > --
> > 2.37.1

[PATCH 7/9] dt-bindings: crypto: drop fsl-sec4 txt binding

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Since we have convert it to two DT schema, fsl-sec4.yaml and
fsl-sec4-snvs.yaml, this txt binding could be removed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../devicetree/bindings/crypto/fsl-sec4.txt   | 553 ------------------
 1 file changed, 553 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.txt

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
deleted file mode 100644
index 8f359f473ada..000000000000
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ /dev/null
@@ -1,553 +0,0 @@
-=====================================================================
-SEC 4 Device Tree Binding
-Copyright (C) 2008-2011 Freescale Semiconductor Inc.
-
- CONTENTS
-   -Overview
-   -SEC 4 Node
-   -Job Ring Node
-   -Run Time Integrity Check (RTIC) Node
-   -Run Time Integrity Check (RTIC) Memory Node
-   -Secure Non-Volatile Storage (SNVS) Node
-   -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
-   -Full Example
-
-NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
-Accelerator and Assurance Module (CAAM).
-
-=====================================================================
-Overview
-
-DESCRIPTION
-
-SEC 4 h/w can process requests from 2 types of sources.
-1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
-2. Job Rings (HW interface between cores & SEC 4 registers).
-
-High Speed Data Path Configuration:
-
-HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
-such as the P4080.  The number of simultaneous dequeues the QI can make is
-equal to the number of Descriptor Controller (DECO) engines in a particular
-SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
-dequeue from 5 subportals simultaneously.
-
-Job Ring Data Path Configuration:
-
-Each JR is located on a separate 4k page, they may (or may not) be made visible
-in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
-up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
-
-=====================================================================
-SEC 4 Node
-
-Description
-
-    Node defines the base address of the SEC 4 block.
-    This block specifies the address range of all global
-    configuration registers for the SEC 4 block.  It
-    also receives interrupts from the Run Time Integrity Check
-    (RTIC) function within the SEC 4 block.
-
-PROPERTIES
-
-   - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0"
-
-   - fsl,sec-era
-      Usage: optional
-      Value type: <u32>
-      Definition: A standard property. Define the 'ERA' of the SEC
-          device.
-
-   - #address-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing physical addresses in child nodes.
-
-   - #size-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing the size of physical addresses in
-           child nodes.
-
-   - reg
-      Usage: required
-      Value type: <prop-encoded-array>
-      Definition: A standard property.  Specifies the physical
-          address and length of the SEC4 configuration registers.
-          registers
-
-   - ranges
-       Usage: required
-       Value type: <prop-encoded-array>
-       Definition: A standard property.  Specifies the physical address
-           range of the SEC 4.0 register space (-SNVS not included).  A
-           triplet that includes the child address, parent address, &
-           length.
-
-   - interrupts
-      Usage: required
-      Value type: <prop_encoded-array>
-      Definition:  Specifies the interrupts generated by this
-           device.  The value of the interrupts property
-           consists of one interrupt specifier. The format
-           of the specifier is defined by the binding document
-           describing the node's interrupt parent.
-
-   - clocks
-      Usage: required if SEC 4.0 requires explicit enablement of clocks
-      Value type: <prop_encoded-array>
-      Definition:  A list of phandle and clock specifier pairs describing
-          the clocks required for enabling and disabling SEC 4.0.
-
-   - clock-names
-      Usage: required if SEC 4.0 requires explicit enablement of clocks
-      Value type: <string>
-      Definition: A list of clock name strings in the same order as the
-          clocks property.
-
-   Note: All other standard properties (see the Devicetree Specification)
-   are allowed but are optional.
-
-
-EXAMPLE
-
-iMX6QDL/SX requires four clocks
-
-	crypto@300000 {
-		compatible = "fsl,sec-v4.0";
-		fsl,sec-era = <2>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x300000 0x10000>;
-		ranges = <0 0x300000 0x10000>;
-		interrupt-parent = <&mpic>;
-		interrupts = <92 2>;
-		clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
-			 <&clks IMX6QDL_CLK_CAAM_ACLK>,
-			 <&clks IMX6QDL_CLK_CAAM_IPG>,
-			 <&clks IMX6QDL_CLK_EIM_SLOW>;
-		clock-names = "mem", "aclk", "ipg", "emi_slow";
-	};
-
-
-iMX6UL does only require three clocks
-
-	crypto: crypto@2140000 {
-		compatible = "fsl,sec-v4.0";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x2140000 0x3c000>;
-		ranges = <0 0x2140000 0x3c000>;
-		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-
-		clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
-			 <&clks IMX6UL_CLK_CAAM_ACLK>,
-			 <&clks IMX6UL_CLK_CAAM_IPG>;
-		clock-names = "mem", "aclk", "ipg";
-	};
-
-=====================================================================
-Job Ring (JR) Node
-
-    Child of the crypto node defines data processing interface to SEC 4
-    across the peripheral bus for purposes of processing
-    cryptographic descriptors. The specified address
-    range can be made visible to one (or more) cores.
-    The interrupt defined for this node is controlled within
-    the address range of this node.
-
-  - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0-job-ring"
-
-  - reg
-      Usage: required
-      Value type: <prop-encoded-array>
-      Definition: Specifies a two JR parameters:  an offset from
-          the parent physical address and the length the JR registers.
-
-   - fsl,liodn
-       Usage: optional-but-recommended
-       Value type: <prop-encoded-array>
-       Definition:
-           Specifies the LIODN to be used in conjunction with
-           the ppid-to-liodn table that specifies the PPID to LIODN mapping.
-           Needed if the PAMU is used.  Value is a 12 bit value
-           where value is a LIODN ID for this JR. This property is
-           normally set by boot firmware.
-
-   - interrupts
-      Usage: required
-      Value type: <prop_encoded-array>
-      Definition:  Specifies the interrupts generated by this
-           device.  The value of the interrupts property
-           consists of one interrupt specifier. The format
-           of the specifier is defined by the binding document
-           describing the node's interrupt parent.
-
-EXAMPLE
-	jr@1000 {
-		compatible = "fsl,sec-v4.0-job-ring";
-		reg = <0x1000 0x1000>;
-		fsl,liodn = <0x081>;
-		interrupt-parent = <&mpic>;
-		interrupts = <88 2>;
-	};
-
-
-=====================================================================
-Run Time Integrity Check (RTIC) Node
-
-  Child node of the crypto node.  Defines a register space that
-  contains up to 5 sets of addresses and their lengths (sizes) that
-  will be checked at run time.  After an initial hash result is
-  calculated, these addresses are checked by HW to monitor any
-  change.  If any memory is modified, a Security Violation is
-  triggered (see SNVS definition).
-
-
-  - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0-rtic".
-
-   - #address-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing physical addresses in child nodes.  Must
-           have a value of 1.
-
-   - #size-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing the size of physical addresses in
-           child nodes.  Must have a value of 1.
-
-  - reg
-      Usage: required
-      Value type: <prop-encoded-array>
-      Definition: A standard property.  Specifies a two parameters:
-          an offset from the parent physical address and the length
-          the SEC4 registers.
-
-   - ranges
-       Usage: required
-       Value type: <prop-encoded-array>
-       Definition: A standard property.  Specifies the physical address
-           range of the SEC 4 register space (-SNVS not included).  A
-           triplet that includes the child address, parent address, &
-           length.
-
-EXAMPLE
-	rtic@6000 {
-		compatible = "fsl,sec-v4.0-rtic";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x6000 0x100>;
-		ranges = <0x0 0x6100 0xe00>;
-	};
-
-=====================================================================
-Run Time Integrity Check (RTIC) Memory Node
-  A child node that defines individual RTIC memory regions that are used to
-  perform run-time integrity check of memory areas that should not modified.
-  The node defines a register that contains the memory address &
-  length (combined) and a second register that contains the hash result
-  in big endian format.
-
-  - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0-rtic-memory".
-
-  - reg
-      Usage: required
-      Value type: <prop-encoded-array>
-      Definition: A standard property.  Specifies two parameters:
-          an offset from the parent physical address and the length:
-
-          1. The location of the RTIC memory address & length registers.
-          2. The location RTIC hash result.
-
-  - fsl,rtic-region
-       Usage: optional-but-recommended
-       Value type: <prop-encoded-array>
-       Definition:
-           Specifies the HW address (36 bit address) for this region
-           followed by the length of the HW partition to be checked;
-           the address is represented as a 64 bit quantity followed
-           by a 32 bit length.
-
-   - fsl,liodn
-       Usage: optional-but-recommended
-       Value type: <prop-encoded-array>
-       Definition:
-           Specifies the LIODN to be used in conjunction with
-           the ppid-to-liodn table that specifies the PPID to LIODN
-           mapping.  Needed if the PAMU is used.  Value is a 12 bit value
-           where value is a LIODN ID for this RTIC memory region. This
-           property is normally set by boot firmware.
-
-EXAMPLE
-	rtic-a@0 {
-		compatible = "fsl,sec-v4.0-rtic-memory";
-		reg = <0x00 0x20 0x100 0x80>;
-		fsl,liodn   = <0x03c>;
-		fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
-	};
-
-=====================================================================
-Secure Non-Volatile Storage (SNVS) Node
-
-    Node defines address range and the associated
-    interrupt for the SNVS function.  This function
-    monitors security state information & reports
-    security violations. This also included rtc,
-    system power off and ON/OFF key.
-
-  - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
-
-  - reg
-      Usage: required
-      Value type: <prop-encoded-array>
-      Definition: A standard property.  Specifies the physical
-          address and length of the SEC4 configuration
-          registers.
-
-   - #address-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing physical addresses in child nodes.  Must
-           have a value of 1.
-
-   - #size-cells
-       Usage: required
-       Value type: <u32>
-       Definition: A standard property.  Defines the number of cells
-           for representing the size of physical addresses in
-           child nodes.  Must have a value of 1.
-
-   - ranges
-       Usage: required
-       Value type: <prop-encoded-array>
-       Definition: A standard property.  Specifies the physical address
-           range of the SNVS register space.  A triplet that includes
-           the child address, parent address, & length.
-
-   - interrupts
-      Usage: optional
-      Value type: <prop_encoded-array>
-      Definition:  Specifies the interrupts generated by this
-           device.  The value of the interrupts property
-           consists of one interrupt specifier. The format
-           of the specifier is defined by the binding document
-           describing the node's interrupt parent.
-
-EXAMPLE
-	sec_mon@314000 {
-		compatible = "fsl,sec-v4.0-mon", "syscon";
-		reg = <0x314000 0x1000>;
-		ranges = <0 0x314000 0x1000>;
-		interrupt-parent = <&mpic>;
-		interrupts = <93 2>;
-	};
-
-=====================================================================
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
-
-  A SNVS child node that defines SNVS LP RTC.
-
-  - compatible
-      Usage: required
-      Value type: <string>
-      Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
-
-  - interrupts
-      Usage: required
-      Value type: <prop_encoded-array>
-      Definition: Specifies the interrupts generated by this
-	   device.  The value of the interrupts property
-	   consists of one interrupt specifier. The format
-	   of the specifier is defined by the binding document
-	   describing the node's interrupt parent.
-
- - regmap
-	Usage: required
-	Value type: <phandle>
-	Definition: this is phandle to the register map node.
-
- - offset
-	Usage: option
-	value type: <u32>
-	Definition: LP register offset. default it is 0x34.
-
-   - clocks
-      Usage: optional, required if SNVS LP RTC requires explicit
-          enablement of clocks
-      Value type: <prop_encoded-array>
-      Definition:  a clock specifier describing the clock required for
-          enabling and disabling SNVS LP RTC.
-
-   - clock-names
-      Usage: optional, required if SNVS LP RTC requires explicit
-          enablement of clocks
-      Value type: <string>
-      Definition: clock name string should be "snvs-rtc".
-
-EXAMPLE
-	sec_mon_rtc_lp@1 {
-		compatible = "fsl,sec-v4.0-mon-rtc-lp";
-		interrupts = <93 2>;
-		regmap = <&snvs>;
-		offset = <0x34>;
-		clocks = <&clks IMX7D_SNVS_CLK>;
-		clock-names = "snvs-rtc";
-	};
-
-=====================================================================
-System ON/OFF key driver
-
-  The snvs-pwrkey is designed to enable POWER key function which controlled
-  by SNVS ONOFF, the driver can report the status of POWER key and wakeup
-  system if pressed after system suspend.
-
-  - compatible:
-      Usage: required
-      Value type: <string>
-      Definition: Mush include "fsl,sec-v4.0-pwrkey".
-
-  - interrupts:
-      Usage: required
-      Value type: <prop_encoded-array>
-      Definition: The SNVS ON/OFF interrupt number to the CPU(s).
-
-  - linux,keycode:
-      Usage: option
-      Value type: <int>
-      Definition: Keycode to emit, KEY_POWER by default.
-
-  - wakeup-source:
-      Usage: option
-      Value type: <boo>
-      Definition: Button can wake-up the system.
-
- - regmap:
-      Usage: required:
-      Value type: <phandle>
-      Definition: this is phandle to the register map node.
-
-EXAMPLE:
-	snvs-pwrkey@020cc000 {
-		compatible = "fsl,sec-v4.0-pwrkey";
-		regmap = <&snvs>;
-		interrupts = <0 4 0x4>
-	        linux,keycode = <116>; /* KEY_POWER */
-		wakeup-source;
-	};
-
-=====================================================================
-FULL EXAMPLE
-
-	crypto: crypto@300000 {
-		compatible = "fsl,sec-v4.0";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x300000 0x10000>;
-		ranges = <0 0x300000 0x10000>;
-		interrupt-parent = <&mpic>;
-		interrupts = <92 2>;
-
-		sec_jr0: jr@1000 {
-			compatible = "fsl,sec-v4.0-job-ring";
-			reg = <0x1000 0x1000>;
-			interrupt-parent = <&mpic>;
-			interrupts = <88 2>;
-		};
-
-		sec_jr1: jr@2000 {
-			compatible = "fsl,sec-v4.0-job-ring";
-			reg = <0x2000 0x1000>;
-			interrupt-parent = <&mpic>;
-			interrupts = <89 2>;
-		};
-
-		sec_jr2: jr@3000 {
-			compatible = "fsl,sec-v4.0-job-ring";
-			reg = <0x3000 0x1000>;
-			interrupt-parent = <&mpic>;
-			interrupts = <90 2>;
-		};
-
-		sec_jr3: jr@4000 {
-			compatible = "fsl,sec-v4.0-job-ring";
-			reg = <0x4000 0x1000>;
-			interrupt-parent = <&mpic>;
-			interrupts = <91 2>;
-		};
-
-		rtic@6000 {
-			compatible = "fsl,sec-v4.0-rtic";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0x6000 0x100>;
-			ranges = <0x0 0x6100 0xe00>;
-
-			rtic_a: rtic-a@0 {
-				compatible = "fsl,sec-v4.0-rtic-memory";
-				reg = <0x00 0x20 0x100 0x80>;
-			};
-
-			rtic_b: rtic-b@20 {
-				compatible = "fsl,sec-v4.0-rtic-memory";
-				reg = <0x20 0x20 0x200 0x80>;
-			};
-
-			rtic_c: rtic-c@40 {
-				compatible = "fsl,sec-v4.0-rtic-memory";
-				reg = <0x40 0x20 0x300 0x80>;
-			};
-
-			rtic_d: rtic-d@60 {
-				compatible = "fsl,sec-v4.0-rtic-memory";
-				reg = <0x60 0x20 0x500 0x80>;
-			};
-		};
-	};
-
-	sec_mon: sec_mon@314000 {
-		compatible = "fsl,sec-v4.0-mon";
-		reg = <0x314000 0x1000>;
-		ranges = <0 0x314000 0x1000>;
-
-		sec_mon_rtc_lp@34 {
-			compatible = "fsl,sec-v4.0-mon-rtc-lp";
-			regmap = <&sec_mon>;
-			offset = <0x34>;
-			interrupts = <93 2>;
-			clocks = <&clks IMX7D_SNVS_CLK>;
-			clock-names = "snvs-rtc";
-		};
-
-		snvs-pwrkey@020cc000 {
-			compatible = "fsl,sec-v4.0-pwrkey";
-			regmap = <&sec_mon>;
-			interrupts = <0 4 0x4>;
-			linux,keycode = <116>; /* KEY_POWER */
-			wakeup-source;
-		};
-	};
-
-=====================================================================
-- 
2.37.1

Re: [PATCH 7/9] dt-bindings: crypto: drop fsl-sec4 txt binding

[kernel test robot]

Hi Peng,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on herbert-cryptodev-2.6/master]
[also build test WARNING on herbert-crypto-2.6/master shawnguo/for-next linus/master v6.2 next-20230302]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Peng-Fan-OSS/ARM-dts-vfxxx-drop-the-number-after-jr/20230301-095526
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
patch link:    https://lore.kernel.org/r/20230301015702.3388458-8-peng.fan%40oss.nxp.com
patch subject: [PATCH 7/9] dt-bindings: crypto: drop fsl-sec4 txt binding
reproduce:
        # https://github.com/intel-lab-lkp/linux/commit/be7a2d4765563d62ace0128d9497c0fbef9ffd1b
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Peng-Fan-OSS/ARM-dts-vfxxx-drop-the-number-after-jr/20230301-095526
        git checkout be7a2d4765563d62ace0128d9497c0fbef9ffd1b
        make menuconfig
        # enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS
        make htmldocs

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303022114.lkxW64dk-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> Warning: Documentation/devicetree/bindings/input/snvs-pwrkey.txt references a file that doesn't exist: Documentation/devicetree/bindings/crypto/fsl-sec4.txt
>> Warning: Documentation/devicetree/bindings/rtc/snvs-rtc.txt references a file that doesn't exist: Documentation/devicetree/bindings/crypto/fsl-sec4.txt
>> Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/crypto/fsl-sec4.txt

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

Re: [PATCH 7/9] dt-bindings: crypto: drop fsl-sec4 txt binding

[Krzysztof Kozlowski]

On 01/03/2023 02:57, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Since we have convert it to two DT schema, fsl-sec4.yaml and
> fsl-sec4-snvs.yaml, this txt binding could be removed.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

No. Conversion includes parts of removal. Don't split logical commits.
It also makes review difficult.

Best regards,
Krzysztof

[PATCH 8/9] dt-bindings: crypto: fsl-sec4-snvs: add snvs-lpgpr support

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add snvs-lpgpr support for fsl-sec4-snvs

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../bindings/crypto/fsl-sec4-snvs.yaml        | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
index 1a4b4975e1d9..688057ec5c97 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
@@ -124,6 +124,25 @@ properties:
       - compatible
       - interrupts
 
+  snvs-lpgpr:
+    type: object
+
+    properties:
+      compatible:
+        oneOf:
+          - enum:
+              - fsl,imx7d-snvs-lpgpr
+              - fsl,imx6q-snvs-lpgpr
+              - fsl,imx6ul-snvs-lpgpr
+          - items:
+              - enum:
+                  - fsl,imx8mm-snvs-lpgpr
+                  - fsl,imx8mp-snvs-lpgpr
+              - const: fsl,imx7d-snvs-lpgpr
+
+    required:
+      - compatible
+
 required:
   - compatible
   - reg
-- 
2.37.1

Re: [PATCH 8/9] dt-bindings: crypto: fsl-sec4-snvs: add snvs-lpgpr support

[Krzysztof Kozlowski]

On 01/03/2023 02:57, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add snvs-lpgpr support for fsl-sec4-snvs
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../bindings/crypto/fsl-sec4-snvs.yaml        | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> index 1a4b4975e1d9..688057ec5c97 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> @@ -124,6 +124,25 @@ properties:
>        - compatible
>        - interrupts
>  
> +  snvs-lpgpr:
> +    type: object

Why not ref to that binding? Much less code...

Best regards,
Krzysztof

[PATCH 9/9] dt-bindings: crypto: fsl-sec4-snvs: add poweroff support

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add snvs poweroff support for fsl-sec4-snvs

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
index 688057ec5c97..f08a7ddece96 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
@@ -124,6 +124,10 @@ properties:
       - compatible
       - interrupts
 
+  snvs-poweroff:
+    description: The snvs-poweroff is designed to enable POWEROFF function.
+    $ref: /schemas/power/reset/syscon-poweroff.yaml#
+
   snvs-lpgpr:
     type: object
 
-- 
2.37.1

Re: [PATCH 9/9] dt-bindings: crypto: fsl-sec4-snvs: add poweroff support

[Krzysztof Kozlowski]

On 01/03/2023 02:57, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add snvs poweroff support for fsl-sec4-snvs
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> index 688057ec5c97..f08a7ddece96 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> @@ -124,6 +124,10 @@ properties:
>        - compatible
>        - interrupts
>  
> +  snvs-poweroff:
> +    description: The snvs-poweroff is designed to enable POWEROFF function.

Your description says nothing. Poweroff is designed to enable poweroff.

Best regards,
Krzysztof

Re: [PATCH 0/9] dt-bindings: crypto: convert fsl-sec4 to DT schema

[Rob Herring]

On Wed, Mar 01, 2023 at 09:56:53AM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> This is effort towards SystemReady IR 2.0 to convert the txt binding to DT
> schema.
> Patch 1 is just to drop uneeded number since following DT schema will update the name
> 
> The fsl-sec4.txt binding has two parts, one is crypto, one is snvs, so I split
> into two DT schema file. patch 2,3 is for crypto, patch 4,5,6 is for snvs,
> patch 7 is to drop fsl-sec4.txt binding. patch 8,9 is to add new node
> 
> Peng Fan (9):
>   ARM: dts: vfxxx: drop the number after jr
>   dt-bindings: crypto: fsl-sec4: convert to DT schema
>   dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL
>   dt-bindings: crypto: add fsl-sec4-snvs DT schema
>   dt-bindings: crypto: fsl-sec4-snvs: add simple-mfd compatible
>   dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible
>   dt-bindings: crypto: drop fsl-sec4 txt binding
>   dt-bindings: crypto: fsl-sec4-snvs: add snvs-lpgpr support
>   dt-bindings: crypto: fsl-sec4-snvs: add poweroff support

I'll leave it to you to work out which one to take[1]. :(

>  .../bindings/crypto/fsl-sec4-snvs.yaml        | 181 ++++++
>  .../devicetree/bindings/crypto/fsl-sec4.txt   | 553 ------------------
>  .../devicetree/bindings/crypto/fsl-sec4.yaml  | 366 ++++++++++++
>  arch/arm/boot/dts/vfxxx.dtsi                  |   4 +-
>  4 files changed, 549 insertions(+), 555 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
>  delete mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.txt
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.yaml

Filenames based on compatible strings...

Rob

[1] https://lore.kernel.org/all/20230220213334.353779-1-robh@kernel.org/

RE: [PATCH 0/9] dt-bindings: crypto: convert fsl-sec4 to DT schema

[Peng Fan]

Hi Rob,

> Subject: Re: [PATCH 0/9] dt-bindings: crypto: convert fsl-sec4 to DT schema
> 
> On Wed, Mar 01, 2023 at 09:56:53AM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > This is effort towards SystemReady IR 2.0 to convert the txt binding
> > to DT schema.
> > Patch 1 is just to drop uneeded number since following DT schema will
> > update the name
> >
> > The fsl-sec4.txt binding has two parts, one is crypto, one is snvs, so
> > I split into two DT schema file. patch 2,3 is for crypto, patch 4,5,6
> > is for snvs, patch 7 is to drop fsl-sec4.txt binding. patch 8,9 is to
> > add new node
> >
> > Peng Fan (9):
> >   ARM: dts: vfxxx: drop the number after jr
> >   dt-bindings: crypto: fsl-sec4: convert to DT schema
> >   dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL
> >   dt-bindings: crypto: add fsl-sec4-snvs DT schema
> >   dt-bindings: crypto: fsl-sec4-snvs: add simple-mfd compatible
> >   dt-bindings: crypto: fsl-sec4-snvs: add fsl sec 5.x compatible
> >   dt-bindings: crypto: drop fsl-sec4 txt binding
> >   dt-bindings: crypto: fsl-sec4-snvs: add snvs-lpgpr support
> >   dt-bindings: crypto: fsl-sec4-snvs: add poweroff support
> 
> I'll leave it to you to work out which one to take[1]. :(

Thanks for working on it.  Let's go with your patchset.

Thanks,
Peng.
> 
> >  .../bindings/crypto/fsl-sec4-snvs.yaml        | 181 ++++++
> >  .../devicetree/bindings/crypto/fsl-sec4.txt   | 553 ------------------
> >  .../devicetree/bindings/crypto/fsl-sec4.yaml  | 366 ++++++++++++
> >  arch/arm/boot/dts/vfxxx.dtsi                  |   4 +-
> >  4 files changed, 549 insertions(+), 555 deletions(-)  create mode
> > 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
> >  delete mode 100644
> > Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/crypto/fsl-sec4.yaml
> 
> Filenames based on compatible strings...
> 
> Rob
> 
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.
> kernel.org%2Fall%2F20230220213334.353779-1-
> robh%40kernel.org%2F&data=05%7C01%7Cpeng.fan%40nxp.com%7C403af
> 158981344444a5c08db1a01f439%7C686ea1d3bc2b4c6fa92cd99c5c301635%
> 7C0%7C0%7C638132367911500608%7CUnknown%7CTWFpbGZsb3d8eyJWIj
> oiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> 3000%7C%7C%7C&sdata=KsKhl8M5Z9Mqy0%2BfW12WJ9MRw6lTWFYTN1Qi
> xnSagJo%3D&reserved=0