From: masonccyang@mxic.com.tw
To: "Pratyush Yadav" <me@yadavpratyush.com>
Cc: boris.brezillon@collabora.com, broonie@kernel.org,
juliensu@mxic.com.tw, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
matthias.bgg@gmail.com, miquel.raynal@bootlin.com,
p.yadav@ti.com, richard@nod.at, tudor.ambarus@microchip.com,
vigneshr@ti.com
Subject: Re: [PATCH v4 7/7] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for Macronix mx25uw51245g
Date: Fri, 5 Jun 2020 10:53:55 +0800 [thread overview]
Message-ID: <OF72696CF7.123ABE04-ON4825857E.000F9054-4825857E.000FEC12@mxic.com.tw> (raw)
In-Reply-To: <20200603055359.y35dwznglc7tlewq@yadavpratyush.com>
> > > >
> > > > +#define MXIC_CR2_DUMMY_SET_ADDR 0x300
> > > > +
> > > > +/* Fixup the dummy cycles to device and setup octa_dtr_enable()
*/
> > > > +static void mx25uw51245g_post_sfdp_fixups(struct spi_nor *nor)
> > > > +{
> > > > + struct spi_nor_flash_parameter *params = nor->params;
> > > > + int ret;
> > > > + u8 rdc, wdc;
> > > > +
> > > > + ret = spi_nor_read_cr2(nor, MXIC_CR2_DUMMY_SET_ADDR, &rdc);
> > > > + if (ret)
> > > > + return;
> > > > +
> > > > + /* Refer to dummy cycle and frequency table(MHz) */
> > > > + switch (params->dummy_cycles) {
> > > > + case 10: /* 10 dummy cycles for 104 MHz */
> > > > + wdc = 5;
> > > > + break;
> > > > + case 12: /* 12 dummy cycles for 133 MHz */
> > > > + wdc = 4;
> > > > + break;
> > > > + case 16: /* 16 dummy cycles for 166 MHz */
> > > > + wdc = 2;
> > > > + break;
> > > > + case 18: /* 18 dummy cycles for 173 MHz */
> > > > + wdc = 1;
> > > > + break;
> > > > + case 20: /* 20 dummy cycles for 200 MHz */
> > > > + default:
> > > > + wdc = 0;
> > > > + }
> > >
> > > I don't get the point of this. You already know the fastest the
> > > mx25uw51245g flash can run at. Why not just use the maximum dummy
> > > cycles? SPI NOR doesn't know the speed the controller is running at
so
> > > the best it can do is use the maximum dummy cycles possible so it
never
> > > falls short. Sure, it will be _slightly_ less performance, but we
will
> > > be sure to read the correct data, which is much much more important.
> >
> > In general, 200MHz needs 20 dummy cycles but some powerful device may
only
> >
> > needs 18 dummy cycles or less.
>
> Yes, but do different mx25uw51245g chips have different dummy cycle
> requirements? Shouldn't all the chips with the same ID have same
> performance?
>
Same chip ID but different grade,
i.e., commercial or industrial grade.
thanks & best regards,
Mason
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information
and/or personal data, which is protected by applicable laws. Please be
reminded that duplication, disclosure, distribution, or use of this e-mail
(and/or its attachments) or any part thereof is prohibited. If you receive
this e-mail in error, please notify us immediately and delete this mail as
well as its attachment(s) from your system. In addition, please be
informed that collection, processing, and/or use of personal data is
prohibited unless expressly permitted by personal data protection laws.
Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=====================================================================
============================================================================
CONFIDENTIALITY NOTE:
This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation.
Macronix International Co., Ltd.
=====================================================================
next prev parent reply other threads:[~2020-06-05 2:54 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 7:36 [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support Mason Yang
2020-05-29 7:36 ` [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from BFPT Mason Yang
2020-05-29 9:23 ` Pratyush Yadav
2020-06-02 6:32 ` masonccyang
2020-07-13 5:49 ` masonccyang
2020-10-27 16:57 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 2/7] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Mason Yang
2020-05-29 9:27 ` Pratyush Yadav
2020-07-13 5:52 ` masonccyang
2020-10-27 17:19 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 3/7] mtd: spi-nor: sfdp: parse command sequences to change octal DTR mode Mason Yang
2020-07-13 5:55 ` masonccyang
2020-10-28 9:45 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write support Mason Yang
2020-07-13 5:56 ` masonccyang
2020-10-28 10:18 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 5/7] mtd: spi-nor: core: execute command sequences to change octal DTR mode Mason Yang
2020-07-13 5:57 ` masonccyang
2020-05-29 7:36 ` [PATCH v4 6/7] spi: mxic: patch for octal DTR mode support Mason Yang
2020-07-13 5:58 ` masonccyang
2020-05-29 7:36 ` [PATCH v4 7/7] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for Macronix mx25uw51245g Mason Yang
2020-05-29 9:42 ` Pratyush Yadav
2020-06-02 6:44 ` masonccyang
2020-06-03 5:53 ` Pratyush Yadav
2020-06-05 2:53 ` masonccyang [this message]
2020-06-05 7:47 ` Pratyush Yadav
2020-07-13 5:59 ` masonccyang
2020-10-28 10:25 ` Tudor.Ambarus
2020-05-29 9:13 ` [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-07-13 5:47 ` masonccyang
2020-10-28 10:42 ` Tudor.Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=OF72696CF7.123ABE04-ON4825857E.000F9054-4825857E.000FEC12@mxic.com.tw \
--to=masonccyang@mxic.com.tw \
--cc=boris.brezillon@collabora.com \
--cc=broonie@kernel.org \
--cc=juliensu@mxic.com.tw \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=matthias.bgg@gmail.com \
--cc=me@yadavpratyush.com \
--cc=miquel.raynal@bootlin.com \
--cc=p.yadav@ti.com \
--cc=richard@nod.at \
--cc=tudor.ambarus@microchip.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).