From: masonccyang@mxic.com.tw
To: ycllin@mxic.com.tw
Cc: boris.brezillon@collabora.com, broonie@kernel.org,
juliensu@mxic.com.tw, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
matthias.bgg@gmail.com, miquel.raynal@bootlin.com,
p.yadav@ti.com, richard@nod.at, tudor.ambarus@microchip.com,
vigneshr@ti.com
Subject: Re: [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write support
Date: Mon, 13 Jul 2020 13:56:49 +0800 [thread overview]
Message-ID: <OFEB5FB2E6.05B846A9-ON482585A4.00209949-482585A4.0020AAF4@mxic.com.tw> (raw)
In-Reply-To: <1590737775-4798-5-git-send-email-masonccyang@mxic.com.tw>
+ YC Lin in loop,
--
>
> Subject
>
> [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read &
write support
>
> Configuration register 2 is to set the device operation condition like
> STR or DTR mode at address offset 0 and DQS mode at address offset
0x200.
>
> Each device has various address offset for it's specific operatoin
> setting.
>
> Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
> ---
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next prev parent reply other threads:[~2020-07-13 6:29 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 7:36 [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support Mason Yang
2020-05-29 7:36 ` [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from BFPT Mason Yang
2020-05-29 9:23 ` Pratyush Yadav
2020-06-02 6:32 ` masonccyang
2020-07-13 5:49 ` masonccyang
2020-10-27 16:57 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 2/7] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Mason Yang
2020-05-29 9:27 ` Pratyush Yadav
2020-07-13 5:52 ` masonccyang
2020-10-27 17:19 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 3/7] mtd: spi-nor: sfdp: parse command sequences to change octal DTR mode Mason Yang
2020-07-13 5:55 ` masonccyang
2020-10-28 9:45 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write support Mason Yang
2020-07-13 5:56 ` masonccyang [this message]
2020-10-28 10:18 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 5/7] mtd: spi-nor: core: execute command sequences to change octal DTR mode Mason Yang
2020-07-13 5:57 ` masonccyang
2020-05-29 7:36 ` [PATCH v4 6/7] spi: mxic: patch for octal DTR mode support Mason Yang
2020-07-13 5:58 ` masonccyang
2020-05-29 7:36 ` [PATCH v4 7/7] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for Macronix mx25uw51245g Mason Yang
2020-05-29 9:42 ` Pratyush Yadav
2020-06-02 6:44 ` masonccyang
2020-06-03 5:53 ` Pratyush Yadav
2020-06-05 2:53 ` masonccyang
2020-06-05 7:47 ` Pratyush Yadav
2020-07-13 5:59 ` masonccyang
2020-10-28 10:25 ` Tudor.Ambarus
2020-05-29 9:13 ` [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-07-13 5:47 ` masonccyang
2020-10-28 10:42 ` Tudor.Ambarus
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