Re: [PATCH/RFC] Enable HPET on VIA8237 southbridge

Re: [PATCH/RFC] Enable HPET on VIA8237 southbridge

[Clemens Ladisch]

Karsten Wiese wrote:
> if you have that chip on your mainboard and want to play with it's
> hpet, this might get you going.

I'm using similar code for my ICH5 southbridge, but I patched
arch/i386/kernel/acpi/boot.c instead so that the kernel can use it
for its own purposes.

> One exception: Timer1 says it can do PERIODIC mode,
> but this doesn't work here. One shot is ok.

This may be because your patch doesn't initialize the interrupt
routing registers (which would have been the BIOS' job).


Regards,
Clemens

Re: [PATCH/RFC] Enable HPET on VIA8237 southbridge

[Karsten Wiese]

Am Montag, 26. September 2005 17:49 schrieb Clemens Ladisch:
> Karsten Wiese wrote:
> > if you have that chip on your mainboard and want to play with it's
> > hpet, this might get you going.
> 
> I'm using similar code for my ICH5 southbridge, but I patched
> arch/i386/kernel/acpi/boot.c instead so that the kernel can use it
> for its own purposes.

The kernel uses the hpet here too with my patch.
Please send me your acpi/boot.c patch.

I guess you setup an ACPI_HPET entry, if none has been found?
Maybe your approach is safer/better, 'cause you can scan other ACPI
assigned Hardware addresses there.
> 
> > One exception: Timer1 says it can do PERIODIC mode,
> > but this doesn't work here. One shot is ok.
> 
> This may be because your patch doesn't initialize the interrupt
> routing registers (which would have been the BIOS' job).

No. Interrupt works fine (IRQ 8). Reliably @10000/s.

   Regards,
   Karsten

	

	
		
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Re: [PATCH/RFC] Enable HPET on VIA8237 southbridge

[Clemens Ladisch]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 933 bytes --]

Karsten Wiese wrote:
> Am Montag, 26. September 2005 17:49 schrieb Clemens Ladisch:
> > Karsten Wiese wrote:
> > > if you have that chip on your mainboard and want to play with it's
> > > hpet, this might get you going.
> >
> > I'm using similar code for my ICH5 southbridge, but I patched
> > arch/i386/kernel/acpi/boot.c instead so that the kernel can use it
> > for its own purposes.
>
> The kernel uses the hpet here too with my patch.

Uh, yes.  I wasn't sure where I could add a hook to be called early
enough so that the assignment to hpet_address still takes effect, so I
just unconditionally replaced acpi_parse_hpet.

> Please send me your acpi/boot.c patch.

Attached.

> I guess you setup an ACPI_HPET entry, if none has been found?

This would be a good idea for a patch that would have any chance of
being applied to the kernel.

> Maybe your approach is safer/better,

You didn't yet see it ... ;-)


Regards,
Clemens

[-- Attachment #2: Type: TEXT/PLAIN, Size: 1790 bytes --]

Index: linux-2.6.13/arch/i386/kernel/acpi/boot.c
===================================================================
--- linux-2.6.13.orig/arch/i386/kernel/acpi/boot.c	2005-08-30 19:21:00.000000000 +0200
+++ linux-2.6.13/arch/i386/kernel/acpi/boot.c	2005-09-27 21:18:03.000000000 +0200
@@ -591,6 +591,7 @@ static int __init acpi_parse_sbf(unsigne
 
 #ifdef CONFIG_HPET_TIMER
 
+#if 0
 static int __init acpi_parse_hpet(unsigned long phys, unsigned long size)
 {
 	struct acpi_table_hpet *hpet_tbl;
@@ -628,8 +629,41 @@ static int __init acpi_parse_hpet(unsign
 
 	return 0;
 }
+#endif
+
+static u32 __init read_pci_config_32(u32 address)
+{
+	outl(address, 0xcf8);
+	return inl(0xcfc);
+}
+
+static void __init write_pci_config_32(u32 address, u32 value)
+{
+	outl(address, 0xcf8);
+	outl(value, 0xcfc);
+}
+
+#define PCIADDR(bus, dev, fn, reg) (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | reg)
+
+static void __init hack_hpet(void)
+{
+	extern unsigned long hpet_address;
+	void __iomem *hpet;
+
+	u32 cfg = read_pci_config_32(PCIADDR(0, 31, 0, 0xd0));
+	cfg &= ~0x00018000; /* set address */
+	cfg |= 0x00020000; /* enable */
+	write_pci_config_32(PCIADDR(0, 31, 0, 0xd0), cfg);
+
+	hpet = __acpi_map_table(0xfed00000, 0x400);
+	writel(0x00000002, hpet + 0x10); /* legacy routing */
+	writel(0x00001600, hpet + 0x140); /* timer 2: interrupt 11 */
+	hpet_address = 0xfed00000;
+	printk(KERN_INFO PREFIX "HPET hack enabled, base: %#lx\n", hpet_address);
+}
 #else
 #define	acpi_parse_hpet	NULL
+#define hack_hpet()
 #endif
 
 #ifdef CONFIG_X86_PM_TIMER
@@ -1164,7 +1198,7 @@ int __init acpi_boot_init(void)
 	 */
 	acpi_process_madt();
 
-	acpi_table_parse(ACPI_HPET, acpi_parse_hpet);
+	hack_hpet();
 
 	return 0;
 }

[PATCH/RFC] Enable HPET on VIA8237 southbridge

[Karsten Wiese]

[-- Attachment #1: Type: text/plain, Size: 116 bytes --]

Hi,

if you have that chip on your mainboard and want to play with it's
hpet, this might get you going.

   Karsten

[-- Attachment #2: patch-via8237-hpet-i386 --]
[-- Type: text/x-diff, Size: 2179 bytes --]

Enable HPET on VIA8237 southbridge

Some BIOSs don't enable the hpet on that chip.
The patch enables it before all the other pci devices.

The hpet's hardware address is set to 0xFED00000,
if the VIA8237 has been identified.

This IS DANGEROUS.
I.e. because the hardware address might be assigned
later in the boot process to somthing else.

Tested succesfully on an K8T800/AMD64 Mobo.
One exception: Timer1 says it can do PERIODIC mode,
but this doesn't work here. One shot is ok.

Signed-off-by: Karsten Wiese <annabellesgraden@yahoo.de>


diff -ur linux-2.6.13-RT/arch/i386/kernel/time_hpet.c linux-2.6.13-RT-kw/arch/i386/kernel/time_hpet.c
--- linux-2.6.13-RT/arch/i386/kernel/time_hpet.c	2005-09-19 15:49:17.000000000 +0200
+++ linux-2.6.13-RT-kw/arch/i386/kernel/time_hpet.c	2005-09-24 00:58:37.000000000 +0200
@@ -223,11 +223,74 @@
 	return use_hpet;
 }
 
+#define HPET_HACK_ENABLE_DANGEROUS 1
+
+#ifdef HPET_HACK_ENABLE_DANGEROUS
+union conf_address {
+	struct {
+		u8	reg;
+		u8	func:	3;
+		u8	dev:	5;
+		u8	bus;
+		u8	reserved:7;
+		u8	enable:	1;
+	} bits;
+	u32	dword;
+};
+
+#include <linux/pci_ids.h>
+
+static void is_hpet_via8237(void)
+{
+	union conf_address ca = {
+		.bits.reg = 0,
+		.bits.dev = 17,
+		.bits.enable = 1
+	};
+	union {
+		struct {
+			u8 control;
+			u8 address[3];
+		} hpet;
+		unsigned raw;
+	} hpet;
+	u32 vendor_id, control;
+
+	control = inl(0xcf8);
+	printk("%X\n", control);
+	outl(ca.dword, 0xcf8);
+	vendor_id = inl(0xcfc);
+	if (vendor_id == (PCI_VENDOR_ID_VIA + (PCI_DEVICE_ID_VIA_8237 << 16))) {
+		hpet.raw = 0xFED00000;
+		hpet.hpet.control = 0x80;
+		ca.bits.reg = 0x68;
+		outl(ca.dword, 0xcf8);
+		outl(hpet.raw, 0xcfc);
+		outl(ca.dword, 0xcf8);
+		hpet_address = (inl(0xcfc) & 0xFFFFFF00);
+		printk(KERN_WARNING "time.c: WARNING: Enabled VIA8237 HPET "
+		       "at %#lx.\n", hpet_address);
+	}
+}
+
+#else
+
+static void is_hpet_via8237(void)
+{
+}
+
+#endif
+
+
 int is_hpet_capable(void)
 {
-	if (!boot_hpet_disable && hpet_address)
-		return 1;
-	return 0;
+	if (boot_hpet_disable)
+		return 0;
+
+        if (!hpet_address)
+		is_hpet_via8237();
+
+	return hpet_address;
 }
 
 static int __init hpet_setup(char* str)