BIOS, Duron4 specifics...

BIOS, Duron4 specifics...

[John Clemens]

Sorry if this is a little offtopic but I'm stumped...

I've got a new laptop with an AMD Duron in it, based on the Athlon4 core
(PowerNow, SSE, hardware prefetch, etc.. Palomino core)..  However, it
appears none of the useful features are enabled in the bios.  For example,
Nowhere does it appear to enable SSE or the APIC.  Is there anyway I can
get at least UP-APIC working without BIOS help?  I really don't like
having 4 things on IRQ11... and how about SSE (fully realizing i'd have
to hack the kernel)?  It may or may not be worth it, but i'd like to play
with it just to see.

Also, whats the state of powernow/clock throttling support? I know there
was talk of a generic power management/clock control interface a while
back, where is that project/whats it's status/etc?

john.c

-- 
John Clemens          http://www.deater.net/john
john@deater.net     ICQ: 7175925, IM: PianoManO8
      "I Hate Quotes" -- Samuel L. Clemens

Re: BIOS, Duron4 specifics...

[Dave Jones]

On Tue, 10 Jul 2001, John Clemens wrote:

> I've got a new laptop with an AMD Duron in it, based on the Athlon4 core
> (PowerNow, SSE, hardware prefetch, etc.. Palomino core)..  However, it
> appears none of the useful features are enabled in the bios.  For example,
> Nowhere does it appear to enable SSE or the APIC.

afair, the mobile Durons are not based upon the Athlon 4 core, and
hence won't have the features you mention. You can verify this with
my x86info tool which you can get from
ftp://ftp.suse.com/pub/people/davej/x86info/x86info-1.3.tgz

This will decode the PowerNOW capabilities register (if it exists)
and tell you if its capable of Bus speed division/Voltage ID control.

I'd be interested in getting the output of x86info -a on this
send to me by private mail btw.

Oh, and you'll need a kernel with the MSR/CPUID drivers loaded.

> Also, whats the state of powernow/clock throttling support? I know there
> was talk of a generic power management/clock control interface a while
> back, where is that project/whats it's status/etc?

The kernel side implementation of this lives in Russell King's CVS.
Grab it using..

cvs -d :pserver:cvs@pubcvs.arm.linux.org.uk:/mnt/src/cvsroot login
cvs -d :pserver:cvs@pubcvs.arm.linux.org.uk:/mnt/src/cvsroot checkout cpufreq

cvs commit list: http://www.linux.org.uk/mailman/listinfo/cpufreq-commit

Note, the Athlon 4 implementation of PowerNOW is currently unsupported,
I'm looking into this right now, after having a chance to talk with
some of the AMD guys at the UKUUG developers conference last week.
The PowerNOW implementation in the CVS tree is equivalent to that
available in my Powertweak program (http://www.powertweak.org) and
its derivative 'k6mult'.

As this implementation was largely reverse engineered, its incomplete
and only supports bus scaling, not voltage scaling. This is something
else we hope to get supported sometime.

The userspace support for this is about to commence, in both a standalone
utility, and a Powertweak plugin.

regards,

Dave.

-- 
| Dave Jones.        http://www.suse.de/~davej
| SuSE Labs

Re: BIOS, Duron4 specifics...

[Richard B. Johnson]

On Tue, 10 Jul 2001, John Clemens wrote:

> 
> Sorry if this is a little offtopic but I'm stumped...
>
[SNIPPED...] 
> Nowhere does it appear to enable SSE or the APIC.  Is there anyway I can
> get at least UP-APIC working without BIOS help?  I really don't like
> having 4 things on IRQ11... and how about SSE (fully realizing i'd have
         ^^^^^^^^^^^^^^^^^

I think you will find that this is a problem with the basic design,
not the APIC. Just like my COMPAQ Presario 1800, everything on the
PCI bus shares the same interrupt.

You can recompile the kernel for SMP. This will guarantee that
the kernel initializes the APIC (at least up to version 2.4.1).

If you find that everything is still on the same IRQ, that's the
way it is, only one PWB trace going to the devices.


Cheers,
Dick Johnson

Penguin : Linux version 2.4.1 on an i686 machine (799.53 BogoMips).

    I was going to compile a list of innovations that could be
    attributed to Microsoft. Once I realized that Ctrl-Alt-Del
    was handled in the BIOS, I found that there aren't any.

Re: BIOS, Duron4 specifics...

[John Clemens]

On Tue, 10 Jul 2001, Dave Jones wrote:

> On Tue, 10 Jul 2001, John Clemens wrote:
>
> > I've got a new laptop with an AMD Duron in it, based on the Athlon4 core
> > (PowerNow, SSE, hardware prefetch, etc.. Palomino core)..  However, it
> > appears none of the useful features are enabled in the bios.  For example,
> > Nowhere does it appear to enable SSE or the APIC.
>
> afair, the mobile Durons are not based upon the Athlon 4 core, and
> hence won't have the features you mention. You can verify this with
> my x86info tool which you can get from
> ftp://ftp.suse.com/pub/people/davej/x86info/x86info-1.3.tgz

Actually, CPUID reports Family 6, Model 6, Rev2, which corellates directly
to Athlon4/MP (Model 6) processors.  Whats surprising is that is doesn't
report model 7, which AMD claims is supposed to be the mobile Duron ;)..
make me wonder if it's really a neutered Athlon4.  Besides, I though the
origional mobile durons (T-bird core, model 3) didn't even support
powernow...?

FYI: This is an HP 5430 notebook.  Duron 850.
http://notebooks.hp-at-home.com/products/notebooks/overview.php?modelNumber=n5430

In either case, i think it really does have all these features, but feel
free to prove me wrong..

> I'd be interested in getting the output of x86info -a on this
> send to me by private mail btw.

will do.  By the way, nice utility!

> The kernel side implementation of this lives in Russell King's CVS.
> Grab it using..
>
> cvs -d :pserver:cvs@pubcvs.arm.linux.org.uk:/mnt/src/cvsroot login
> cvs -d :pserver:cvs@pubcvs.arm.linux.org.uk:/mnt/src/cvsroot checkout cpufreq
>
> cvs commit list: http://www.linux.org.uk/mailman/listinfo/cpufreq-commit

Thanks for the pointer.  I'll grab this and have a look at it

john.c

-- 
John Clemens          http://www.deater.net/john
john@deater.net     ICQ: 7175925, IM: PianoManO8
      "I Hate Quotes" -- Samuel L. Clemens

Re: BIOS, Duron4 specifics...

[Dave Jones]

On Tue, 10 Jul 2001, John Clemens wrote:

> Actually, CPUID reports Family 6, Model 6, Rev2, which corellates directly
> to Athlon4/MP (Model 6) processors.

*nod*

> make me wonder if it's really a neutered Athlon4.  Besides, I though the
> origional mobile durons (T-bird core, model 3) didn't even support
> powernow...?

That was my belief also. It appears you have a new type of Duron.
I was unaware of this stepping, which makes me even more curious
to see your x86info -a output :)

> FYI: This is an HP 5430 notebook.  Duron 850.
> http://notebooks.hp-at-home.com/products/notebooks/overview.php?modelNumber=n5430

Neat. I'm expecting this to be new style (Athlon 4) PowerNow rather than
the K6 style PowerNOW. I'll look into this some more.

regards,

Dave.

-- 
| Dave Jones.        http://www.suse.de/~davej
| SuSE Labs

Re: BIOS, Duron4 specifics...

[Eric W. Biederman]

John Clemens <john@deater.net> writes:

> On Tue, 10 Jul 2001, Dave Jones wrote:
> 
> > On Tue, 10 Jul 2001, John Clemens wrote:
> >
> > > I've got a new laptop with an AMD Duron in it, based on the Athlon4 core
> > > (PowerNow, SSE, hardware prefetch, etc.. Palomino core)..  However, it
> > > appears none of the useful features are enabled in the bios.  For example,
> > > Nowhere does it appear to enable SSE or the APIC.
> >
> > afair, the mobile Durons are not based upon the Athlon 4 core, and
> > hence won't have the features you mention. You can verify this with
> > my x86info tool which you can get from
> > ftp://ftp.suse.com/pub/people/davej/x86info/x86info-1.3.tgz
> 
> Actually, CPUID reports Family 6, Model 6, Rev2, which corellates directly
> to Athlon4/MP (Model 6) processors.  Whats surprising is that is doesn't
> report model 7, which AMD claims is supposed to be the mobile Duron ;)..
> make me wonder if it's really a neutered Athlon4.  Besides, I though the
> origional mobile durons (T-bird core, model 3) didn't even support
> powernow...?

To enable SSE you have to write a bit into a undocumented register.
For the APIC the procedure to enable it is the same as the P6 core.

Eric