* [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver
@ 2019-01-08 6:04 Ran Wang
2019-01-08 6:04 ` [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms Ran Wang
` (2 more replies)
0 siblings, 3 replies; 18+ messages in thread
From: Ran Wang @ 2019-01-08 6:04 UTC (permalink / raw)
To: Greg Kroah-Hartman, Alan Stern
Cc: linux-usb, linux-kernel, Rajesh Bhagat, Ran Wang
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
CONFIG_USB_EHCI_FSL is not dependent on FSL_SOC, it can be built on
non-PPC platforms.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
drivers/usb/host/Kconfig | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 16758b1..53cbc0c 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -179,8 +179,8 @@ config XPS_USB_HCD_XILINX
devices only.
config USB_EHCI_FSL
- tristate "Support for Freescale PPC on-chip EHCI USB controller"
- depends on FSL_SOC
+ tristate "Support for Freescale on-chip EHCI USB controller"
+ depends on USB_EHCI_HCD
select USB_EHCI_ROOT_HUB_TT
---help---
Variation of ARC USB block used in some Freescale chips.
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-08 6:04 [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Ran Wang @ 2019-01-08 6:04 ` Ran Wang 2019-01-08 15:45 ` Greg Kroah-Hartman 2019-01-08 16:20 ` Alan Stern 2019-01-08 6:04 ` [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code Ran Wang 2019-01-08 16:11 ` [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Alan Stern 2 siblings, 2 replies; 18+ messages in thread From: Ran Wang @ 2019-01-08 6:04 UTC (permalink / raw) To: Greg Kroah-Hartman, Alan Stern; +Cc: linux-usb, linux-kernel, Ran Wang arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which causing compile failure on some Layerscape Platforms (such as LS1021A and LS2012A which also integrates FSL EHCI controller). So use ioread32be()/iowrite32be() instead to make it workable on both powerpc and arm. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> --- drivers/usb/host/ehci-fsl.c | 64 ++++++++++++++++++++++++++++--------------- 1 files changed, 42 insertions(+), 22 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 0a9fd20..59ebe1b 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -23,6 +23,7 @@ #include <linux/platform_device.h> #include <linux/fsl_devices.h> #include <linux/of_platform.h> +#include <linux/io.h> #include "ehci.h" #include "ehci-fsl.h" @@ -50,6 +51,7 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) struct resource *res; int irq; int retval; + u32 tmp; pr_debug("initializing FSL-SOC USB Controller\n"); @@ -114,18 +116,23 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) } /* Enable USB controller, 83xx or 8536 */ - if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) - clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK, 0x4); - + if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) { + tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); + tmp &= ~CONTROL_REGISTER_W1C_MASK; + tmp |= 0x4; + iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); + } /* * Enable UTMI phy and program PTS field in UTMI mode before asserting * controller reset for USB Controller version 2.5 */ if (pdata->has_fsl_erratum_a007792) { - clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN); - writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); + tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); + tmp &= ~CONTROL_REGISTER_W1C_MASK; + tmp |= CTRL_UTMI_PHY_EN; + iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); + + iowrite32be(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); } /* Don't need to set host mode here. It will be done by tdi_reset() */ @@ -174,7 +181,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, enum fsl_usb2_phy_modes phy_mode, unsigned int port_offset) { - u32 portsc; + u32 portsc, tmp; struct ehci_hcd *ehci = hcd_to_ehci(hcd); void __iomem *non_ehci = hcd->regs; struct device *dev = hcd->self.controller; @@ -192,11 +199,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, case FSL_USB2_PHY_ULPI: if (pdata->have_sysif_regs && pdata->controller_ver) { /* controller version 1.6 or above */ - clrbits32(non_ehci + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK, - ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN); + /* turn off UTMI PHY first */ + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); + tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); + + /* then turn on ULPI and enable USB controller */ + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); + tmp &= ~(CONTROL_REGISTER_W1C_MASK); + tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); } portsc |= PORT_PTS_ULPI; break; @@ -210,16 +222,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, case FSL_USB2_PHY_UTMI_DUAL: if (pdata->have_sysif_regs && pdata->controller_ver) { /* controller version 1.6 or above */ - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN); + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); + tmp &= ~(CONTROL_REGISTER_W1C_MASK); + tmp |= UTMI_PHY_EN; + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); + mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to become stable - 10ms*/ } /* enable UTMI PHY */ - if (pdata->have_sysif_regs) - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK, - CTRL_UTMI_PHY_EN); + if (pdata->have_sysif_regs) { + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); + tmp &= ~CONTROL_REGISTER_W1C_MASK; + tmp |= CTRL_UTMI_PHY_EN; + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); + } portsc |= PORT_PTS_UTMI; break; case FSL_USB2_PHY_NONE: @@ -241,9 +258,12 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); - if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, - CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN); + if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); + tmp &= ~CONTROL_REGISTER_W1C_MASK; + tmp |= USB_CTRL_USB_EN; + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); + } return 0; } -- 1.7.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-08 6:04 ` [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms Ran Wang @ 2019-01-08 15:45 ` Greg Kroah-Hartman 2019-01-17 8:06 ` Ran Wang 2019-01-08 16:20 ` Alan Stern 1 sibling, 1 reply; 18+ messages in thread From: Greg Kroah-Hartman @ 2019-01-08 15:45 UTC (permalink / raw) To: Ran Wang; +Cc: Alan Stern, linux-usb, linux-kernel On Tue, Jan 08, 2019 at 06:04:26AM +0000, Ran Wang wrote: > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which > causing compile failure on some Layerscape Platforms (such as LS1021A and > LS2012A which also integrates FSL EHCI controller). So use > ioread32be()/iowrite32be() instead to make it workable on both > powerpc and arm. Shouldn't you have this patch before the Kconfig change, so that you do not break the build on ARM systems on that one and then fix it up on this one? thanks, greg k-h ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-08 15:45 ` Greg Kroah-Hartman @ 2019-01-17 8:06 ` Ran Wang 0 siblings, 0 replies; 18+ messages in thread From: Ran Wang @ 2019-01-17 8:06 UTC (permalink / raw) To: Greg Kroah-Hartman; +Cc: Alan Stern, linux-usb, linux-kernel Hi Greg, On 08, 2019 23:45, Greg Kroah-Hartman wrote: > > On Tue, Jan 08, 2019 at 06:04:26AM +0000, Ran Wang wrote: > > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), > > which causing compile failure on some Layerscape Platforms (such as > > LS1021A and LS2012A which also integrates FSL EHCI controller). So use > > ioread32be()/iowrite32be() instead to make it workable on both powerpc > > and arm. > > Shouldn't you have this patch before the Kconfig change, so that you do not > break the build on ARM systems on that one and then fix it up on this one? Yes, you are right, will adjust it in next version, thanks for pointing out. Regards, Ran ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-08 6:04 ` [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms Ran Wang 2019-01-08 15:45 ` Greg Kroah-Hartman @ 2019-01-08 16:20 ` Alan Stern 2019-01-09 3:37 ` Ran Wang 1 sibling, 1 reply; 18+ messages in thread From: Alan Stern @ 2019-01-08 16:20 UTC (permalink / raw) To: Ran Wang; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel On Tue, 8 Jan 2019, Ran Wang wrote: > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which > causing compile failure on some Layerscape Platforms (such as LS1021A and > LS2012A which also integrates FSL EHCI controller). So use > ioread32be()/iowrite32be() instead to make it workable on both > powerpc and arm. > > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > --- > drivers/usb/host/ehci-fsl.c | 64 ++++++++++++++++++++++++++++--------------- > 1 files changed, 42 insertions(+), 22 deletions(-) > > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c > index 0a9fd20..59ebe1b 100644 > --- a/drivers/usb/host/ehci-fsl.c > +++ b/drivers/usb/host/ehci-fsl.c > @@ -23,6 +23,7 @@ > #include <linux/platform_device.h> > #include <linux/fsl_devices.h> > #include <linux/of_platform.h> > +#include <linux/io.h> > > #include "ehci.h" > #include "ehci-fsl.h" > @@ -50,6 +51,7 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) > struct resource *res; > int irq; > int retval; > + u32 tmp; > > pr_debug("initializing FSL-SOC USB Controller\n"); > > @@ -114,18 +116,23 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) > } > > /* Enable USB controller, 83xx or 8536 */ > - if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) > - clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK, 0x4); > - > + if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) { > + tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > + tmp |= 0x4; > + iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); > + } > /* > * Enable UTMI phy and program PTS field in UTMI mode before asserting > * controller reset for USB Controller version 2.5 > */ > if (pdata->has_fsl_erratum_a007792) { > - clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN); > - writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); > + tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > + tmp |= CTRL_UTMI_PHY_EN; > + iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); > + > + iowrite32be(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); Why do you change this writel() into iowrite32be() but leave other instances of writel() unchanged? Was this a mistake? > } > > /* Don't need to set host mode here. It will be done by tdi_reset() */ > @@ -174,7 +181,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, > enum fsl_usb2_phy_modes phy_mode, > unsigned int port_offset) > { > - u32 portsc; > + u32 portsc, tmp; > struct ehci_hcd *ehci = hcd_to_ehci(hcd); > void __iomem *non_ehci = hcd->regs; > struct device *dev = hcd->self.controller; > @@ -192,11 +199,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, > case FSL_USB2_PHY_ULPI: > if (pdata->have_sysif_regs && pdata->controller_ver) { > /* controller version 1.6 or above */ > - clrbits32(non_ehci + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK, > - ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN); > + /* turn off UTMI PHY first */ > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > + tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > + > + /* then turn on ULPI and enable USB controller */ > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > + tmp &= ~(CONTROL_REGISTER_W1C_MASK); Unnecessary parens. > + tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > } > portsc |= PORT_PTS_ULPI; > break; > @@ -210,16 +222,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, > case FSL_USB2_PHY_UTMI_DUAL: > if (pdata->have_sysif_regs && pdata->controller_ver) { > /* controller version 1.6 or above */ > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN); > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > + tmp &= ~(CONTROL_REGISTER_W1C_MASK); Unnecessary parens. > + tmp |= UTMI_PHY_EN; > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > + > mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to > become stable - 10ms*/ > } > /* enable UTMI PHY */ > - if (pdata->have_sysif_regs) > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK, > - CTRL_UTMI_PHY_EN); > + if (pdata->have_sysif_regs) { > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > + tmp |= CTRL_UTMI_PHY_EN; > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > + } > portsc |= PORT_PTS_UTMI; > break; > case FSL_USB2_PHY_NONE: > @@ -241,9 +258,12 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, > > ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); > > - if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > - CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN); > + if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > + tmp |= USB_CTRL_USB_EN; > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > + } > > return 0; > } Alan Stern ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-08 16:20 ` Alan Stern @ 2019-01-09 3:37 ` Ran Wang 2019-01-09 15:14 ` Alan Stern 0 siblings, 1 reply; 18+ messages in thread From: Ran Wang @ 2019-01-09 3:37 UTC (permalink / raw) To: Alan Stern; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel Hi Alan, > -----Original Message----- > From: Alan Stern <stern@rowland.harvard.edu> > Sent: Wednesday, January 09, 2019 00:20 > To: Ran Wang <ran.wang_1@nxp.com> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux- > usb@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/3] usb: ehci: fsl: Update register accessing for > arm/arm64 platforms > > On Tue, 8 Jan 2019, Ran Wang wrote: > > > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), > > which causing compile failure on some Layerscape Platforms (such as > > LS1021A and LS2012A which also integrates FSL EHCI controller). So use > > ioread32be()/iowrite32be() instead to make it workable on both powerpc > > and arm. > > > > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > > --- > > drivers/usb/host/ehci-fsl.c | 64 ++++++++++++++++++++++++++++------------ > --- > > 1 files changed, 42 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c > > index 0a9fd20..59ebe1b 100644 > > --- a/drivers/usb/host/ehci-fsl.c > > +++ b/drivers/usb/host/ehci-fsl.c > > @@ -23,6 +23,7 @@ > > #include <linux/platform_device.h> > > #include <linux/fsl_devices.h> > > #include <linux/of_platform.h> > > +#include <linux/io.h> > > > > #include "ehci.h" > > #include "ehci-fsl.h" > > @@ -50,6 +51,7 @@ static int fsl_ehci_drv_probe(struct platform_device > *pdev) > > struct resource *res; > > int irq; > > int retval; > > + u32 tmp; > > > > pr_debug("initializing FSL-SOC USB Controller\n"); > > > > @@ -114,18 +116,23 @@ static int fsl_ehci_drv_probe(struct > platform_device *pdev) > > } > > > > /* Enable USB controller, 83xx or 8536 */ > > - if (pdata->have_sysif_regs && pdata->controller_ver < > FSL_USB_VER_1_6) > > - clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK, 0x4); > > - > > + if (pdata->have_sysif_regs && pdata->controller_ver < > FSL_USB_VER_1_6) { > > + tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); > > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > > + tmp |= 0x4; > > + iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); > > + } > > /* > > * Enable UTMI phy and program PTS field in UTMI mode before > asserting > > * controller reset for USB Controller version 2.5 > > */ > > if (pdata->has_fsl_erratum_a007792) { > > - clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK, > CTRL_UTMI_PHY_EN); > > - writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); > > + tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); > > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > > + tmp |= CTRL_UTMI_PHY_EN; > > + iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); > > + > > + iowrite32be(PORT_PTS_UTMI, hcd->regs + > FSL_SOC_USB_PORTSC1); > > Why do you change this writel() into iowrite32be() but leave other instances > of writel() unchanged? Was this a mistake? Yes, I didn't notice there are other writel() used in this file. However, as I know, on both powerpc and arm SoC, EHCI FSL IP's memory mapped register block is always Big-endian, so I'd like to replace all writel() with iowrite32be() in this file. Is it necessary? Or I just replace them with ehci_writel() and select CONFIG_USB_EHCI_BIG_ENDIAN_MMIO? > > } > > > > /* Don't need to set host mode here. It will be done by tdi_reset() > > */ @@ -174,7 +181,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd > *hcd, > > enum fsl_usb2_phy_modes phy_mode, > > unsigned int port_offset) > > { > > - u32 portsc; > > + u32 portsc, tmp; > > struct ehci_hcd *ehci = hcd_to_ehci(hcd); > > void __iomem *non_ehci = hcd->regs; > > struct device *dev = hcd->self.controller; @@ -192,11 +199,16 @@ > > static int ehci_fsl_setup_phy(struct usb_hcd *hcd, > > case FSL_USB2_PHY_ULPI: > > if (pdata->have_sysif_regs && pdata->controller_ver) { > > /* controller version 1.6 or above */ > > - clrbits32(non_ehci + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK | > UTMI_PHY_EN); > > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK, > > - ULPI_PHY_CLK_SEL | > USB_CTRL_USB_EN); > > + /* turn off UTMI PHY first */ > > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > > + tmp &= ~(CONTROL_REGISTER_W1C_MASK | > UTMI_PHY_EN); > > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > > + > > + /* then turn on ULPI and enable USB controller */ > > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > > + tmp &= ~(CONTROL_REGISTER_W1C_MASK); > > Unnecessary parens. Got it, fix it in next version. > > + tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; > > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > > } > > portsc |= PORT_PTS_ULPI; > > break; > > @@ -210,16 +222,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, > > case FSL_USB2_PHY_UTMI_DUAL: > > if (pdata->have_sysif_regs && pdata->controller_ver) { > > /* controller version 1.6 or above */ > > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK, > UTMI_PHY_EN); > > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > > + tmp &= ~(CONTROL_REGISTER_W1C_MASK); > > Unnecessary parens. Got it. Regards, Ran > > + tmp |= UTMI_PHY_EN; > > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > > + > > mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY > CLK to > > become stable - 10ms*/ > > } > > /* enable UTMI PHY */ > > - if (pdata->have_sysif_regs) > > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK, > > - CTRL_UTMI_PHY_EN); > > + if (pdata->have_sysif_regs) { > > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > > + tmp |= CTRL_UTMI_PHY_EN; > > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > > + } > > portsc |= PORT_PTS_UTMI; > > break; > > case FSL_USB2_PHY_NONE: > > @@ -241,9 +258,12 @@ static int ehci_fsl_setup_phy(struct usb_hcd > > *hcd, > > > > ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); > > > > - if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) > > - clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, > > - CONTROL_REGISTER_W1C_MASK, > USB_CTRL_USB_EN); > > + if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { > > + tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); > > + tmp &= ~CONTROL_REGISTER_W1C_MASK; > > + tmp |= USB_CTRL_USB_EN; > > + iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); > > + } > > > > return 0; > > } > > Alan Stern ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-09 3:37 ` Ran Wang @ 2019-01-09 15:14 ` Alan Stern 2019-01-10 3:41 ` Ran Wang 0 siblings, 1 reply; 18+ messages in thread From: Alan Stern @ 2019-01-09 15:14 UTC (permalink / raw) To: Ran Wang; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel On Wed, 9 Jan 2019, Ran Wang wrote: > > Why do you change this writel() into iowrite32be() but leave other instances > > of writel() unchanged? Was this a mistake? > > Yes, I didn't notice there are other writel() used in this file. > However, as I know, on both powerpc and arm SoC, EHCI FSL IP's memory mapped > register block is always Big-endian, so I'd like to replace all writel() with iowrite32be() > in this file. Is it necessary? > > Or I just replace them with ehci_writel() and select CONFIG_USB_EHCI_BIG_ENDIAN_MMIO? That should work okay. ehci_fsl_setup() sets ehci->big_endian_desc and ehci->big_endian_mmio according to the platform data, so you just have to make sure the platform data is initialized correctly. Alan Stern ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-09 15:14 ` Alan Stern @ 2019-01-10 3:41 ` Ran Wang 2019-01-10 15:29 ` Alan Stern 0 siblings, 1 reply; 18+ messages in thread From: Ran Wang @ 2019-01-10 3:41 UTC (permalink / raw) To: Alan Stern; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel Hi Alan, > -----Original Message----- > From: Alan Stern <stern@rowland.harvard.edu> > Sent: Wednesday, January 09, 2019 23:14 > To: Ran Wang <ran.wang_1@nxp.com> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux- > usb@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for > arm/arm64 platforms > > On Wed, 9 Jan 2019, Ran Wang wrote: > > > > Why do you change this writel() into iowrite32be() but leave other > > > instances of writel() unchanged? Was this a mistake? > > > > Yes, I didn't notice there are other writel() used in this file. > > However, as I know, on both powerpc and arm SoC, EHCI FSL IP's memory > > mapped register block is always Big-endian, so I'd like to replace all > > writel() with iowrite32be() in this file. Is it necessary? > > > > Or I just replace them with ehci_writel() and select > CONFIG_USB_EHCI_BIG_ENDIAN_MMIO? > > That should work okay. ehci_fsl_setup() sets ehci->big_endian_desc and > ehci->big_endian_mmio according to the platform data, so you just have > to make sure the platform data is initialized correctly. > OK, so I should not change writel() into iowrite32be() at that place you mentioned, and still using iowrite32be()/ioread32be() to replace clrsetbits_be32(), am I right? Regards, Ran > Alan Stern ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-10 3:41 ` Ran Wang @ 2019-01-10 15:29 ` Alan Stern 2019-01-11 9:10 ` Ran Wang 0 siblings, 1 reply; 18+ messages in thread From: Alan Stern @ 2019-01-10 15:29 UTC (permalink / raw) To: Ran Wang; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel On Thu, 10 Jan 2019, Ran Wang wrote: > Hi Alan, > > > -----Original Message----- > > From: Alan Stern <stern@rowland.harvard.edu> > > Sent: Wednesday, January 09, 2019 23:14 > > To: Ran Wang <ran.wang_1@nxp.com> > > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux- > > usb@vger.kernel.org; linux-kernel@vger.kernel.org > > Subject: RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for > > arm/arm64 platforms > > > > On Wed, 9 Jan 2019, Ran Wang wrote: > > > > > > Why do you change this writel() into iowrite32be() but leave other > > > > instances of writel() unchanged? Was this a mistake? > > > > > > Yes, I didn't notice there are other writel() used in this file. > > > However, as I know, on both powerpc and arm SoC, EHCI FSL IP's memory > > > mapped register block is always Big-endian, so I'd like to replace all > > > writel() with iowrite32be() in this file. Is it necessary? > > > > > > Or I just replace them with ehci_writel() and select > > CONFIG_USB_EHCI_BIG_ENDIAN_MMIO? > > > > That should work okay. ehci_fsl_setup() sets ehci->big_endian_desc and > > ehci->big_endian_mmio according to the platform data, so you just have > > to make sure the platform data is initialized correctly. > > > OK, so I should not change writel() into iowrite32be() at that > place you mentioned, and still using iowrite32be()/ioread32be() to replace > clrsetbits_be32(), am I right? Actually, I think it would be good to use ehci_writel() and ehci_readl() everywhere except in fsl_ehci_drv_probe(). But if you prefer to use iowrite32be() and ioread32be() instead, that's probably okay. (However, it won't work if anyone ever produces a little-endian version of the IP.) Alan Stern ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms 2019-01-10 15:29 ` Alan Stern @ 2019-01-11 9:10 ` Ran Wang 0 siblings, 0 replies; 18+ messages in thread From: Ran Wang @ 2019-01-11 9:10 UTC (permalink / raw) To: Alan Stern; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel Hi Alan, On Thursday, January 10, 2019, Alan wrote: > > On Thu, 10 Jan 2019, Ran Wang wrote: > > > Hi Alan, > > > > > -----Original Message----- > > > From: Alan Stern <stern@rowland.harvard.edu> > > > Sent: Wednesday, January 09, 2019 23:14 > > > To: Ran Wang <ran.wang_1@nxp.com> > > > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux- > > > usb@vger.kernel.org; linux-kernel@vger.kernel.org > > > Subject: RE: [PATCH 2/3] usb: ehci: fsl: Update register accessing > > > for > > > arm/arm64 platforms > > > > > > On Wed, 9 Jan 2019, Ran Wang wrote: > > > > > > > > Why do you change this writel() into iowrite32be() but leave > > > > > other instances of writel() unchanged? Was this a mistake? > > > > > > > > Yes, I didn't notice there are other writel() used in this file. > > > > However, as I know, on both powerpc and arm SoC, EHCI FSL IP's > > > > memory mapped register block is always Big-endian, so I'd like to > > > > replace all > > > > writel() with iowrite32be() in this file. Is it necessary? > > > > > > > > Or I just replace them with ehci_writel() and select > > > CONFIG_USB_EHCI_BIG_ENDIAN_MMIO? > > > > > > That should work okay. ehci_fsl_setup() sets ehci->big_endian_desc > > > and > > > ehci->big_endian_mmio according to the platform data, so you just > > > ehci->have > > > to make sure the platform data is initialized correctly. > > > > > OK, so I should not change writel() into iowrite32be() at that place > > you mentioned, and still using iowrite32be()/ioread32be() to replace > > clrsetbits_be32(), am I right? > > Actually, I think it would be good to use ehci_writel() and > ehci_readl() everywhere except in fsl_ehci_drv_probe(). > > But if you prefer to use iowrite32be() and ioread32be() instead, that's > probably okay. (However, it won't work if anyone ever produces a little- > endian version of the IP.) Got it, I'll verify with ehci_readl() then work out the v2 patch if pass. Thanks for advice. Regards, Ran ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code 2019-01-08 6:04 [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Ran Wang 2019-01-08 6:04 ` [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms Ran Wang @ 2019-01-08 6:04 ` Ran Wang 2019-01-08 15:44 ` Greg Kroah-Hartman ` (2 more replies) 2019-01-08 16:11 ` [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Alan Stern 2 siblings, 3 replies; 18+ messages in thread From: Ran Wang @ 2019-01-08 6:04 UTC (permalink / raw) To: Greg Kroah-Hartman, Alan Stern Cc: linux-usb, linux-kernel, Yinbo Zhu, Ran Wang From: yinbo.zhu <yinbo.zhu@nxp.com> Remove USB errata checking code from driver. Applicability of erratum is retrieved by reading corresponding property in device tree. This property is written during device tree fixup. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> --- drivers/usb/host/ehci-fsl.c | 7 +------ drivers/usb/host/fsl-mph-dr-of.c | 6 ++++++ include/linux/fsl_devices.h | 7 ++++--- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 59ebe1b..2aa408a 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -304,14 +304,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) return -EINVAL; if (pdata->operating_mode == FSL_USB2_MPH_HOST) { - unsigned int chip, rev, svr; - - svr = mfspr(SPRN_SVR); - chip = svr >> 16; - rev = (svr >> 4) & 0xf; /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) + if (pdata->has_fsl_erratum_14 == 1) ehci->has_fsl_port_bug = 1; if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c index 677f9d5..4f8b8a0 100644 --- a/drivers/usb/host/fsl-mph-dr-of.c +++ b/drivers/usb/host/fsl-mph-dr-of.c @@ -225,6 +225,12 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev) pdata->has_fsl_erratum_a005697 = of_property_read_bool(np, "fsl,usb_erratum-a005697"); + if (of_get_property(np, "fsl,usb_erratum_14", NULL)) + pdata->has_fsl_erratum_14 = 1; + else + pdata->has_fsl_erratum_14 = 0; + + /* * Determine whether phy_clk_valid needs to be checked * by reading property in device tree diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 60cef82..7aa51bc 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -98,10 +98,11 @@ struct fsl_usb2_platform_data { unsigned suspended:1; unsigned already_suspended:1; - unsigned has_fsl_erratum_a007792:1; - unsigned has_fsl_erratum_a005275:1; + unsigned has_fsl_erratum_a007792:1; + unsigned has_fsl_erratum_14:1; + unsigned has_fsl_erratum_a005275:1; unsigned has_fsl_erratum_a005697:1; - unsigned check_phy_clk_valid:1; + unsigned check_phy_clk_valid:1; /* register save area for suspend/resume */ u32 pm_command; -- 1.7.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code 2019-01-08 6:04 ` [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code Ran Wang @ 2019-01-08 15:44 ` Greg Kroah-Hartman 2019-01-09 2:35 ` Ran Wang 2019-01-08 16:22 ` Alan Stern 2019-01-08 16:59 ` kbuild test robot 2 siblings, 1 reply; 18+ messages in thread From: Greg Kroah-Hartman @ 2019-01-08 15:44 UTC (permalink / raw) To: Ran Wang; +Cc: Alan Stern, linux-usb, linux-kernel, Yinbo Zhu On Tue, Jan 08, 2019 at 06:04:29AM +0000, Ran Wang wrote: > From: yinbo.zhu <yinbo.zhu@nxp.com> I doubt Yinbo's name has a "." in it :) Can you please fix this up to have the correct name here? > Remove USB errata checking code from driver. Applicability of erratum > is retrieved by reading corresponding property in device tree. > This property is written during device tree fixup. > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> > Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> > Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> And here. thanks, greg k-h ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code 2019-01-08 15:44 ` Greg Kroah-Hartman @ 2019-01-09 2:35 ` Ran Wang 0 siblings, 0 replies; 18+ messages in thread From: Ran Wang @ 2019-01-09 2:35 UTC (permalink / raw) To: Greg Kroah-Hartman; +Cc: Alan Stern, linux-usb, linux-kernel, Yinbo Zhu Hi Greg, > -----Original Message----- > From: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Sent: Tuesday, January 08, 2019 23:45 > To: Ran Wang <ran.wang_1@nxp.com> > Cc: Alan Stern <stern@rowland.harvard.edu>; linux-usb@vger.kernel.org; > linux-kernel@vger.kernel.org; Yinbo Zhu <yinbo.zhu@nxp.com> > Subject: Re: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code > > On Tue, Jan 08, 2019 at 06:04:29AM +0000, Ran Wang wrote: > > From: yinbo.zhu <yinbo.zhu@nxp.com> > > I doubt Yinbo's name has a "." in it :) > > Can you please fix this up to have the correct name here? > > > Remove USB errata checking code from driver. Applicability of erratum > > is retrieved by reading corresponding property in device tree. > > This property is written during device tree fixup. > > > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> > > Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> > > Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> > > And here. Yes, this is a mistake (should be 'Yinbo Zhu'), I'll fix them in next version, thanks. Regards, Ran ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code 2019-01-08 6:04 ` [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code Ran Wang 2019-01-08 15:44 ` Greg Kroah-Hartman @ 2019-01-08 16:22 ` Alan Stern 2019-01-09 3:52 ` Ran Wang 2019-01-08 16:59 ` kbuild test robot 2 siblings, 1 reply; 18+ messages in thread From: Alan Stern @ 2019-01-08 16:22 UTC (permalink / raw) To: Ran Wang; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel, Yinbo Zhu On Tue, 8 Jan 2019, Ran Wang wrote: > From: yinbo.zhu <yinbo.zhu@nxp.com> > > Remove USB errata checking code from driver. Applicability of erratum > is retrieved by reading corresponding property in device tree. > This property is written during device tree fixup. > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> > Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> > Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > --- > drivers/usb/host/ehci-fsl.c | 7 +------ > drivers/usb/host/fsl-mph-dr-of.c | 6 ++++++ > include/linux/fsl_devices.h | 7 ++++--- > 3 files changed, 11 insertions(+), 9 deletions(-) > > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c > index 59ebe1b..2aa408a 100644 > --- a/drivers/usb/host/ehci-fsl.c > +++ b/drivers/usb/host/ehci-fsl.c > @@ -304,14 +304,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) > return -EINVAL; > > if (pdata->operating_mode == FSL_USB2_MPH_HOST) { > - unsigned int chip, rev, svr; > - > - svr = mfspr(SPRN_SVR); > - chip = svr >> 16; > - rev = (svr >> 4) & 0xf; > > /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ > - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) > + if (pdata->has_fsl_erratum_14 == 1) > ehci->has_fsl_port_bug = 1; > > if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) > diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c > index 677f9d5..4f8b8a0 100644 > --- a/drivers/usb/host/fsl-mph-dr-of.c > +++ b/drivers/usb/host/fsl-mph-dr-of.c > @@ -225,6 +225,12 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev) > pdata->has_fsl_erratum_a005697 = > of_property_read_bool(np, "fsl,usb_erratum-a005697"); > > + if (of_get_property(np, "fsl,usb_erratum_14", NULL)) > + pdata->has_fsl_erratum_14 = 1; > + else > + pdata->has_fsl_erratum_14 = 0; > + > + > /* > * Determine whether phy_clk_valid needs to be checked > * by reading property in device tree > diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h > index 60cef82..7aa51bc 100644 > --- a/include/linux/fsl_devices.h > +++ b/include/linux/fsl_devices.h > @@ -98,10 +98,11 @@ struct fsl_usb2_platform_data { > > unsigned suspended:1; > unsigned already_suspended:1; > - unsigned has_fsl_erratum_a007792:1; > - unsigned has_fsl_erratum_a005275:1; > + unsigned has_fsl_erratum_a007792:1; > + unsigned has_fsl_erratum_14:1; > + unsigned has_fsl_erratum_a005275:1; > unsigned has_fsl_erratum_a005697:1; > - unsigned check_phy_clk_valid:1; > + unsigned check_phy_clk_valid:1; You are using spaces here instead of tabs, which alters the alignment. Don't do that. Alan Stern > > /* register save area for suspend/resume */ > u32 pm_command; ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code 2019-01-08 16:22 ` Alan Stern @ 2019-01-09 3:52 ` Ran Wang 0 siblings, 0 replies; 18+ messages in thread From: Ran Wang @ 2019-01-09 3:52 UTC (permalink / raw) To: Alan Stern; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel, Yinbo Zhu Hi Alan, > -----Original Message----- > From: Alan Stern <stern@rowland.harvard.edu> > Sent: Wednesday, January 09, 2019 00:22 > To: Ran Wang <ran.wang_1@nxp.com> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux- > usb@vger.kernel.org; linux-kernel@vger.kernel.org; Yinbo Zhu > <yinbo.zhu@nxp.com> > Subject: Re: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code > > On Tue, 8 Jan 2019, Ran Wang wrote: > > > From: yinbo.zhu <yinbo.zhu@nxp.com> > > > > Remove USB errata checking code from driver. Applicability of erratum > > is retrieved by reading corresponding property in device tree. > > This property is written during device tree fixup. > > > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> > > Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> > > Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> > > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > > --- > > drivers/usb/host/ehci-fsl.c | 7 +------ > > drivers/usb/host/fsl-mph-dr-of.c | 6 ++++++ > > include/linux/fsl_devices.h | 7 ++++--- > > 3 files changed, 11 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c > > index 59ebe1b..2aa408a 100644 > > --- a/drivers/usb/host/ehci-fsl.c > > +++ b/drivers/usb/host/ehci-fsl.c > > @@ -304,14 +304,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) > > return -EINVAL; > > > > if (pdata->operating_mode == FSL_USB2_MPH_HOST) { > > - unsigned int chip, rev, svr; > > - > > - svr = mfspr(SPRN_SVR); > > - chip = svr >> 16; > > - rev = (svr >> 4) & 0xf; > > > > /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 > chips */ > > - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) > > + if (pdata->has_fsl_erratum_14 == 1) > > ehci->has_fsl_port_bug = 1; > > > > if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) diff -- > git > > a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c > > index 677f9d5..4f8b8a0 100644 > > --- a/drivers/usb/host/fsl-mph-dr-of.c > > +++ b/drivers/usb/host/fsl-mph-dr-of.c > > @@ -225,6 +225,12 @@ static int fsl_usb2_mph_dr_of_probe(struct > platform_device *ofdev) > > pdata->has_fsl_erratum_a005697 = > > of_property_read_bool(np, "fsl,usb_erratum-a005697"); > > > > + if (of_get_property(np, "fsl,usb_erratum_14", NULL)) > > + pdata->has_fsl_erratum_14 = 1; > > + else > > + pdata->has_fsl_erratum_14 = 0; > > + > > + > > /* > > * Determine whether phy_clk_valid needs to be checked > > * by reading property in device tree diff --git > > a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index > > 60cef82..7aa51bc 100644 > > --- a/include/linux/fsl_devices.h > > +++ b/include/linux/fsl_devices.h > > @@ -98,10 +98,11 @@ struct fsl_usb2_platform_data { > > > > unsigned suspended:1; > > unsigned already_suspended:1; > > - unsigned has_fsl_erratum_a007792:1; > > - unsigned has_fsl_erratum_a005275:1; > > + unsigned has_fsl_erratum_a007792:1; > > + unsigned has_fsl_erratum_14:1; > > + unsigned has_fsl_erratum_a005275:1; > > unsigned has_fsl_erratum_a005697:1; > > - unsigned check_phy_clk_valid:1; > > + unsigned check_phy_clk_valid:1; > > You are using spaces here instead of tabs, which alters the alignment. > Don't do that. Yes, will fix it in next version. Regards, Ran > Alan Stern > > > > > /* register save area for suspend/resume */ > > u32 pm_command; ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code 2019-01-08 6:04 ` [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code Ran Wang 2019-01-08 15:44 ` Greg Kroah-Hartman 2019-01-08 16:22 ` Alan Stern @ 2019-01-08 16:59 ` kbuild test robot 2 siblings, 0 replies; 18+ messages in thread From: kbuild test robot @ 2019-01-08 16:59 UTC (permalink / raw) To: Ran Wang Cc: kbuild-all, Greg Kroah-Hartman, Alan Stern, linux-usb, linux-kernel, Yinbo Zhu, Ran Wang [-- Attachment #1: Type: text/plain, Size: 2111 bytes --] Hi yinbo.zhu, Thank you for the patch! Yet something to improve: [auto build test ERROR on usb/usb-testing] [also build test ERROR on v5.0-rc1 next-20190108] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Ran-Wang/usb-kconfig-remove-dependency-FSL_SOC-for-ehci-fsl-driver/20190108-143252 base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=arm All errors (new ones prefixed by >>): drivers/usb/phy/phy-fsl-usb.o: In function `fsl_otg_ioctl': >> phy-fsl-usb.c:(.text+0x444): undefined reference to `otg_statemachine' drivers/usb/phy/phy-fsl-usb.o: In function `fsl_otg_start_srp': phy-fsl-usb.c:(.text+0x4c0): undefined reference to `otg_statemachine' drivers/usb/phy/phy-fsl-usb.o: In function `fsl_otg_set_host': phy-fsl-usb.c:(.text+0x5c0): undefined reference to `otg_statemachine' drivers/usb/phy/phy-fsl-usb.o: In function `fsl_otg_start_hnp': phy-fsl-usb.c:(.text+0x650): undefined reference to `otg_statemachine' drivers/usb/phy/phy-fsl-usb.o: In function `show_fsl_usb2_otg_state': >> phy-fsl-usb.c:(.text+0x754): undefined reference to `usb_otg_state_string' drivers/usb/phy/phy-fsl-usb.o: In function `a_wait_enum': phy-fsl-usb.c:(.text+0x1064): undefined reference to `otg_statemachine' drivers/usb/phy/phy-fsl-usb.o: In function `fsl_otg_set_peripheral': >> phy-fsl-usb.c:(.text+0x1648): undefined reference to `usb_gadget_vbus_disconnect' phy-fsl-usb.c:(.text+0x1658): undefined reference to `otg_statemachine' --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 68442 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver 2019-01-08 6:04 [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Ran Wang 2019-01-08 6:04 ` [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms Ran Wang 2019-01-08 6:04 ` [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code Ran Wang @ 2019-01-08 16:11 ` Alan Stern 2019-01-09 3:23 ` Ran Wang 2 siblings, 1 reply; 18+ messages in thread From: Alan Stern @ 2019-01-08 16:11 UTC (permalink / raw) To: Ran Wang; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel, Rajesh Bhagat On Tue, 8 Jan 2019, Ran Wang wrote: > From: Rajesh Bhagat <rajesh.bhagat@nxp.com> > > CONFIG_USB_EHCI_FSL is not dependent on FSL_SOC, it can be built on > non-PPC platforms. > > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > --- > drivers/usb/host/Kconfig | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index 16758b1..53cbc0c 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -179,8 +179,8 @@ config XPS_USB_HCD_XILINX > devices only. > > config USB_EHCI_FSL > - tristate "Support for Freescale PPC on-chip EHCI USB controller" > - depends on FSL_SOC > + tristate "Support for Freescale on-chip EHCI USB controller" > + depends on USB_EHCI_HCD This line is not needed. The entire entry lies within an "if USB_EHCI_HCD" block. Alan Stern > select USB_EHCI_ROOT_HUB_TT > ---help--- > Variation of ARC USB block used in some Freescale chips. > ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver 2019-01-08 16:11 ` [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Alan Stern @ 2019-01-09 3:23 ` Ran Wang 0 siblings, 0 replies; 18+ messages in thread From: Ran Wang @ 2019-01-09 3:23 UTC (permalink / raw) To: Alan Stern; +Cc: Greg Kroah-Hartman, linux-usb, linux-kernel, Rajesh Bhagat Hi Alan, > -----Original Message----- > From: Alan Stern <stern@rowland.harvard.edu> > Sent: Wednesday, January 09, 2019 00:12 > To: Ran Wang <ran.wang_1@nxp.com> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux- > usb@vger.kernel.org; linux-kernel@vger.kernel.org; Rajesh Bhagat > <rajesh.bhagat@nxp.com> > Subject: Re: [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci > fsl driver > > On Tue, 8 Jan 2019, Ran Wang wrote: > > > From: Rajesh Bhagat <rajesh.bhagat@nxp.com> > > > > CONFIG_USB_EHCI_FSL is not dependent on FSL_SOC, it can be built on > > non-PPC platforms. > > > > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> > > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > > --- > > drivers/usb/host/Kconfig | 4 ++-- > > 1 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index > > 16758b1..53cbc0c 100644 > > --- a/drivers/usb/host/Kconfig > > +++ b/drivers/usb/host/Kconfig > > @@ -179,8 +179,8 @@ config XPS_USB_HCD_XILINX > > devices only. > > > > config USB_EHCI_FSL > > - tristate "Support for Freescale PPC on-chip EHCI USB controller" > > - depends on FSL_SOC > > + tristate "Support for Freescale on-chip EHCI USB controller" > > + depends on USB_EHCI_HCD > > This line is not needed. The entire entry lies within an "if USB_EHCI_HCD" > block. Got it, will remove it in next version, thanks. Regards, Ran > Alan Stern > > > select USB_EHCI_ROOT_HUB_TT > > ---help--- > > Variation of ARC USB block used in some Freescale chips. > > ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2019-01-17 8:06 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-01-08 6:04 [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Ran Wang 2019-01-08 6:04 ` [PATCH 2/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms Ran Wang 2019-01-08 15:45 ` Greg Kroah-Hartman 2019-01-17 8:06 ` Ran Wang 2019-01-08 16:20 ` Alan Stern 2019-01-09 3:37 ` Ran Wang 2019-01-09 15:14 ` Alan Stern 2019-01-10 3:41 ` Ran Wang 2019-01-10 15:29 ` Alan Stern 2019-01-11 9:10 ` Ran Wang 2019-01-08 6:04 ` [PATCH 3/3] drivers: usb :fsl: Remove USB Errata checking code Ran Wang 2019-01-08 15:44 ` Greg Kroah-Hartman 2019-01-09 2:35 ` Ran Wang 2019-01-08 16:22 ` Alan Stern 2019-01-09 3:52 ` Ran Wang 2019-01-08 16:59 ` kbuild test robot 2019-01-08 16:11 ` [PATCH 1/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver Alan Stern 2019-01-09 3:23 ` Ran Wang
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