From: Paul Cercueil <paul@crapouillou.net>
To: 周琰杰 <zhouyanjie@wanyeetech.com>
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
hns@goldelico.com, paul@boddie.org.uk, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, sernia.zhou@foxmail.com
Subject: Re: [PATCH v2 3/6] pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups.
Date: Fri, 12 Mar 2021 13:32:50 +0000 [thread overview]
Message-ID: <QYYUPQ.N7I5SFVLO0943@crapouillou.net> (raw)
In-Reply-To: <1615476112-113101-4-git-send-email-zhouyanjie@wanyeetech.com>
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> Adjust the sequence of X1830's SSI related codes to make it consistent
> with other Ingenic SoCs.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> ---
>
> Notes:
> v2:
> New patch.
>
> drivers/pinctrl/pinctrl-ingenic.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-ingenic.c
> b/drivers/pinctrl/pinctrl-ingenic.c
> index 0a88aab..607ba0b 100644
> --- a/drivers/pinctrl/pinctrl-ingenic.c
> +++ b/drivers/pinctrl/pinctrl-ingenic.c
> @@ -1473,16 +1473,16 @@ static int x1830_ssi0_gpc_pins[] = { 0x4d, };
> static int x1830_ssi0_ce0_pins[] = { 0x50, };
> static int x1830_ssi0_ce1_pins[] = { 0x4e, };
> static int x1830_ssi1_dt_c_pins[] = { 0x53, };
> -static int x1830_ssi1_dr_c_pins[] = { 0x54, };
> -static int x1830_ssi1_clk_c_pins[] = { 0x57, };
> -static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
> -static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
> -static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
> static int x1830_ssi1_dt_d_pins[] = { 0x62, };
> +static int x1830_ssi1_dr_c_pins[] = { 0x54, };
> static int x1830_ssi1_dr_d_pins[] = { 0x63, };
> +static int x1830_ssi1_clk_c_pins[] = { 0x57, };
> static int x1830_ssi1_clk_d_pins[] = { 0x66, };
> +static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
> static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
> +static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
> static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
> +static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
> static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
> static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
> static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-03-12 13:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 15:21 [PATCH v2 0/6] Fix bugs and add support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-03-11 15:21 ` [PATCH v2 1/6] pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group 周琰杰 (Zhou Yanjie)
2021-03-12 13:05 ` Paul Cercueil
2021-03-13 8:07 ` Zhou Yanjie
2021-03-11 15:21 ` [PATCH v2 2/6] pinctrl: Ingenic: Add support for read the pin configuration of X1830 周琰杰 (Zhou Yanjie)
2021-03-12 13:31 ` Paul Cercueil
2021-03-13 8:07 ` Zhou Yanjie
2021-03-11 15:21 ` [PATCH v2 3/6] pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups 周琰杰 (Zhou Yanjie)
2021-03-12 13:32 ` Paul Cercueil [this message]
2021-03-11 15:21 ` [PATCH v2 4/6] pinctrl: Ingenic: Reformat the code 周琰杰 (Zhou Yanjie)
2021-03-12 13:33 ` Paul Cercueil
2021-03-11 15:21 ` [PATCH v2 5/6] dt-bindings: pinctrl: Add bindings for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-03-11 15:21 ` [PATCH v2 6/6] pinctrl: Ingenic: Add support " 周琰杰 (Zhou Yanjie)
2021-03-12 12:50 ` Andy Shevchenko
2021-03-12 13:42 ` Paul Cercueil
2021-03-13 8:07 ` Zhou Yanjie
2021-03-12 12:51 ` [PATCH v2 0/6] Fix bugs and add " Andy Shevchenko
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