* [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-11 2:24 [PATCH v5 0/6] Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
@ 2023-01-11 2:24 ` Yuji Ishikawa
2023-01-11 9:19 ` Krzysztof Kozlowski
2023-01-17 15:26 ` Laurent Pinchart
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
` (4 subsequent siblings)
5 siblings, 2 replies; 42+ messages in thread
From: Yuji Ishikawa @ 2023-01-11 2:24 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree, yuji2.ishikawa
Adds the Device Tree binding documentation that allows to describe
the Video Input Interface found in Toshiba Visconti SoCs.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
Changelog v2:
- no change
Changelog v3:
- no change
Changelog v4:
- fix style problems at the v3 patch
- remove "index" member
- update example
Changelog v5:
- no change
---
.../bindings/media/toshiba,visconti-viif.yaml | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
diff --git a/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
new file mode 100644
index 00000000000..71442724d1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/toshiba,visconti-viif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba Visconti5 SoC Video Input Interface Device Tree Bindings
+
+maintainers:
+ - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
+
+description:
+ Toshiba Visconti5 SoC Video Input Interface (VIIF)
+ receives MIPI CSI2 video stream,
+ processes the stream with embedded image signal processor (L1ISP, L2ISP),
+ then stores pictures to main memory.
+
+properties:
+ compatible:
+ const: toshiba,visconti-viif
+
+ reg:
+ items:
+ - description: registers for capture control
+ - description: registers for CSI2 receiver control
+
+ interrupts:
+ items:
+ - description: Sync Interrupt
+ - description: Status (Error) Interrupt
+ - description: CSI2 Receiver Interrupt
+ - description: L1ISP Interrupt
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Input port, single endpoint describing the CSI-2 transmitter.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ description: VIIF supports 2 or 4 data lines
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 4
+ items:
+ minimum: 1
+ maximum: 4
+
+ clock-lanes:
+ description: VIIF supports 1 clock line
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ viif@1c000000 {
+ compatible = "toshiba,visconti-viif";
+ reg = <0 0x1c000000 0 0x6000>,
+ <0 0x1c008000 0 0x400>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_in0: endpoint {
+ remote-endpoint = <&imx219_out0>;
+ bus-type = <4>;
+ data-lanes = <1 2>;
+ clock-lanes = <0>;
+ clock-noncontinuous;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-11 2:24 ` [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings Yuji Ishikawa
@ 2023-01-11 9:19 ` Krzysztof Kozlowski
2023-01-11 12:48 ` yuji2.ishikawa
2023-01-17 15:26 ` Laurent Pinchart
1 sibling, 1 reply; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-11 9:19 UTC (permalink / raw)
To: Yuji Ishikawa, Hans Verkuil, Laurent Pinchart,
Mauro Carvalho Chehab, Nobuhiro Iwamatsu, Rob Herring,
Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
On 11/01/2023 03:24, Yuji Ishikawa wrote:
> Adds the Device Tree binding documentation that allows to describe
> the Video Input Interface found in Toshiba Visconti SoCs.
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> ---
> Changelog v2:
> - no change
>
> Changelog v3:
> - no change
>
> Changelog v4:
> - fix style problems at the v3 patch
> - remove "index" member
> - update example
>
> Changelog v5:
> - no change
No change? so all comments got ignored?
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-11 9:19 ` Krzysztof Kozlowski
@ 2023-01-11 12:48 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-11 12:48 UTC (permalink / raw)
To: krzysztof.kozlowski, hverkuil, laurent.pinchart, mchehab,
nobuhiro1.iwamatsu, robh+dt, krzysztof.kozlowski+dt,
rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, January 11, 2023 6:20 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; Hans Verkuil <hverkuil@xs4all.nl>; Laurent
> Pinchart <laurent.pinchart@ideasonboard.com>; Mauro Carvalho Chehab
> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>
> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba
> Visconti Video Input Interface bindings
>
> On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > Adds the Device Tree binding documentation that allows to describe the
> > Video Input Interface found in Toshiba Visconti SoCs.
> >
> > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> > ---
> > Changelog v2:
> > - no change
> >
> > Changelog v3:
> > - no change
> >
> > Changelog v4:
> > - fix style problems at the v3 patch
> > - remove "index" member
> > - update example
> >
> > Changelog v5:
> > - no change
>
> No change? so all comments got ignored?
>
> This is a friendly reminder during the review process.
>
> It seems my previous comments were not fully addressed. Maybe my feedback
> got lost between the quotes, maybe you just forgot to apply it.
> Please go back to the previous discussion and either implement all requested
> changes or keep discussing them.
I'm very sorry. I was upset about the recipient list and totally missed your comment.
I'll make a reply to v4 thread.
>
> Thank you.
>
> Best regards,
> Krzysztof
Regards,
Yuji
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-11 2:24 ` [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings Yuji Ishikawa
2023-01-11 9:19 ` Krzysztof Kozlowski
@ 2023-01-17 15:26 ` Laurent Pinchart
2023-01-17 15:42 ` Krzysztof Kozlowski
1 sibling, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-17 15:26 UTC (permalink / raw)
To: Yuji Ishikawa
Cc: Hans Verkuil, Mauro Carvalho Chehab, Nobuhiro Iwamatsu,
Rob Herring, Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown,
linux-media, linux-arm-kernel, linux-kernel, devicetree
Hi Yuji,
Thank you for the patch.
On Wed, Jan 11, 2023 at 11:24:28AM +0900, Yuji Ishikawa wrote:
> Adds the Device Tree binding documentation that allows to describe
> the Video Input Interface found in Toshiba Visconti SoCs.
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> ---
> Changelog v2:
> - no change
>
> Changelog v3:
> - no change
>
> Changelog v4:
> - fix style problems at the v3 patch
> - remove "index" member
> - update example
>
> Changelog v5:
> - no change
> ---
> .../bindings/media/toshiba,visconti-viif.yaml | 98 +++++++++++++++++++
> 1 file changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
> new file mode 100644
> index 00000000000..71442724d1a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/toshiba,visconti-viif.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Toshiba Visconti5 SoC Video Input Interface Device Tree Bindings
> +
> +maintainers:
> + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> +
> +description:
> + Toshiba Visconti5 SoC Video Input Interface (VIIF)
> + receives MIPI CSI2 video stream,
> + processes the stream with embedded image signal processor (L1ISP, L2ISP),
> + then stores pictures to main memory.
> +
> +properties:
> + compatible:
> + const: toshiba,visconti-viif
> +
> + reg:
> + items:
> + - description: registers for capture control
> + - description: registers for CSI2 receiver control
Nitpicking, s/registers/Registers/ in the two lines above as you
capitalize the descriptions below.
> +
> + interrupts:
> + items:
> + - description: Sync Interrupt
> + - description: Status (Error) Interrupt
> + - description: CSI2 Receiver Interrupt
> + - description: L1ISP Interrupt
> +
> + port:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Input port, single endpoint describing the CSI-2 transmitter.
I would write
description:
CSI-2 input port, with a single endpoint connected to the CSI-2
transmitter.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + description: VIIF supports 2 or 4 data lines
s/lines/lanes/
> + $ref: /schemas/types.yaml#/definitions/uint32-array
You can drop this line, it's already handled by video-interfaces.yaml.
> + minItems: 1
> + maxItems: 4
If only 2 or 4 data lanes are supported, shouldn't minItems be 2 ?
> + items:
> + minimum: 1
> + maximum: 4
Can the CSI-2 receiver reorder the data lanes ? If not, I think you can
write
items:
- const: 1
- const: 2
- const: 3
- const: 4
> +
> + clock-lanes:
> + description: VIIF supports 1 clock line
s/line/lane/
> + const: 0
I would also add
clock-noncontinuous: true
link-frequencies: true
to indicate that the above two properties are used by this device.
Also, mark the properties that are required:
required:
- data-lanes
- clock-lanes
I'm wondering, though, if clock-lanes shouldn't be simply omitted. If
the hardware doesn't support any other option than using lane 0 for the
clock lane (as in, no lane remapping), then you can drop the clock-lanes
property completely.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + viif@1c000000 {
> + compatible = "toshiba,visconti-viif";
> + reg = <0 0x1c000000 0 0x6000>,
> + <0 0x1c008000 0 0x400>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + csi_in0: endpoint {
> + remote-endpoint = <&imx219_out0>;
> + bus-type = <4>;
Does the hardware support any other bus type ? If not, you can drop the
bus-type. If it does, bus-type should be added to the binding, with the
value set to "const: 4".
> + data-lanes = <1 2>;
> + clock-lanes = <0>;
> + clock-noncontinuous;
> + link-frequencies = /bits/ 64 <456000000>;
> + };
> + };
> + };
> + };
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-17 15:26 ` Laurent Pinchart
@ 2023-01-17 15:42 ` Krzysztof Kozlowski
2023-01-17 15:58 ` Laurent Pinchart
0 siblings, 1 reply; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-17 15:42 UTC (permalink / raw)
To: Laurent Pinchart, Yuji Ishikawa
Cc: Hans Verkuil, Mauro Carvalho Chehab, Nobuhiro Iwamatsu,
Rob Herring, Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown,
linux-media, linux-arm-kernel, linux-kernel, devicetree
On 17/01/2023 16:26, Laurent Pinchart wrote:
>
>> +
>> + clock-lanes:
>> + description: VIIF supports 1 clock line
>
> s/line/lane/
>
>> + const: 0
>
> I would also add
>
> clock-noncontinuous: true
> link-frequencies: true
>
> to indicate that the above two properties are used by this device.
No, these are coming from other schema and there is never need to
mention some property to indicate it is more used than other case. None
of the bindings are created such way, so this should not be exception.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-17 15:42 ` Krzysztof Kozlowski
@ 2023-01-17 15:58 ` Laurent Pinchart
2023-01-17 17:01 ` Krzysztof Kozlowski
0 siblings, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-17 15:58 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Yuji Ishikawa, Hans Verkuil, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown, linux-media, linux-arm-kernel,
linux-kernel, devicetree
Hi Krzysztof,
On Tue, Jan 17, 2023 at 04:42:51PM +0100, Krzysztof Kozlowski wrote:
> On 17/01/2023 16:26, Laurent Pinchart wrote:
> >
> >> +
> >> + clock-lanes:
> >> + description: VIIF supports 1 clock line
> >
> > s/line/lane/
> >
> >> + const: 0
> >
> > I would also add
> >
> > clock-noncontinuous: true
> > link-frequencies: true
> >
> > to indicate that the above two properties are used by this device.
>
> No, these are coming from other schema and there is never need to
> mention some property to indicate it is more used than other case. None
> of the bindings are created such way, so this should not be exception.
There are some bindings that do so, but that may not be a good enough
reason, as there's a chance I wrote those myself :-)
I would have sworn that at some point in the past the schema wouldn't
have validated the example with this omitted. I'm not sure if something
changed or if I got this wrong.
video-interfaces.yaml defines lots of properties applicable to
endpoints. For a given device, those properties should be required
(easy, that's defined in the bindings), optional, or forbidden. How do
we differentiate between the latter two cases ?
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-17 15:58 ` Laurent Pinchart
@ 2023-01-17 17:01 ` Krzysztof Kozlowski
2023-01-22 19:25 ` Laurent Pinchart
0 siblings, 1 reply; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-17 17:01 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Yuji Ishikawa, Hans Verkuil, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown, linux-media, linux-arm-kernel,
linux-kernel, devicetree
On 17/01/2023 16:58, Laurent Pinchart wrote:
> Hi Krzysztof,
>
> On Tue, Jan 17, 2023 at 04:42:51PM +0100, Krzysztof Kozlowski wrote:
>> On 17/01/2023 16:26, Laurent Pinchart wrote:
>>>
>>>> +
>>>> + clock-lanes:
>>>> + description: VIIF supports 1 clock line
>>>
>>> s/line/lane/
>>>
>>>> + const: 0
>>>
>>> I would also add
>>>
>>> clock-noncontinuous: true
>>> link-frequencies: true
>>>
>>> to indicate that the above two properties are used by this device.
>>
>> No, these are coming from other schema and there is never need to
>> mention some property to indicate it is more used than other case. None
>> of the bindings are created such way, so this should not be exception.
>
> There are some bindings that do so, but that may not be a good enough
> reason, as there's a chance I wrote those myself :-)
>
> I would have sworn that at some point in the past the schema wouldn't
> have validated the example with this omitted. I'm not sure if something
> changed or if I got this wrong.
You probably think about case when using additionalProperties:false,
where one has to explicitly list all valid properties. But not for
unevaluatedProperties:false.
>
> video-interfaces.yaml defines lots of properties applicable to
> endpoints. For a given device, those properties should be required
required:
- foo
> (easy, that's defined in the bindings), optional,
by default (with unevaluatedProperties:false)
or explicitly mention "foo: true (with additionalProperties:false)
> or forbidden. How do
foo: false (with unevaluatedProperties:false)
or by default (with additionalProperties:false)
> we differentiate between the latter two cases ?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-17 17:01 ` Krzysztof Kozlowski
@ 2023-01-22 19:25 ` Laurent Pinchart
2023-01-30 9:06 ` yuji2.ishikawa
0 siblings, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-22 19:25 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Yuji Ishikawa, Hans Verkuil, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown, linux-media, linux-arm-kernel,
linux-kernel, devicetree
Hi Krzysztof,
On Tue, Jan 17, 2023 at 06:01:27PM +0100, Krzysztof Kozlowski wrote:
> On 17/01/2023 16:58, Laurent Pinchart wrote:
> > On Tue, Jan 17, 2023 at 04:42:51PM +0100, Krzysztof Kozlowski wrote:
> >> On 17/01/2023 16:26, Laurent Pinchart wrote:
> >>>
> >>>> +
> >>>> + clock-lanes:
> >>>> + description: VIIF supports 1 clock line
> >>>
> >>> s/line/lane/
> >>>
> >>>> + const: 0
> >>>
> >>> I would also add
> >>>
> >>> clock-noncontinuous: true
> >>> link-frequencies: true
> >>>
> >>> to indicate that the above two properties are used by this device.
> >>
> >> No, these are coming from other schema and there is never need to
> >> mention some property to indicate it is more used than other case. None
> >> of the bindings are created such way, so this should not be exception.
> >
> > There are some bindings that do so, but that may not be a good enough
> > reason, as there's a chance I wrote those myself :-)
> >
> > I would have sworn that at some point in the past the schema wouldn't
> > have validated the example with this omitted. I'm not sure if something
> > changed or if I got this wrong.
>
> You probably think about case when using additionalProperties:false,
> where one has to explicitly list all valid properties. But not for
> unevaluatedProperties:false.
Possibly, yes.
> > video-interfaces.yaml defines lots of properties applicable to
> > endpoints. For a given device, those properties should be required
>
> required:
> - foo
>
> > (easy, that's defined in the bindings), optional,
>
> by default (with unevaluatedProperties:false)
> or explicitly mention "foo: true (with additionalProperties:false)
>
> > or forbidden. How do
>
> foo: false (with unevaluatedProperties:false)
> or by default (with additionalProperties:false)
I think we should default to the latter. video-interfaces.yaml contains
lots of properties endpoint properties, most bindings will use less than
half of them, so having to explicitly list all the ones that are not
used with "foo: false" would be quite inconvenient. Furthermore, I
expect more properties to be added to video-interfaces.yaml over time,
and those shouldn't be accepted by default in existing bindings.
> > we differentiate between the latter two cases ?
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-22 19:25 ` Laurent Pinchart
@ 2023-01-30 9:06 ` yuji2.ishikawa
2023-02-01 9:45 ` Laurent Pinchart
0 siblings, 1 reply; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-30 9:06 UTC (permalink / raw)
To: laurent.pinchart, krzysztof.kozlowski
Cc: hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Monday, January 23, 2023 4:26 AM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Cc: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; Hans Verkuil <hverkuil@xs4all.nl>; Mauro
> Carvalho Chehab <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □Ｓ
> ＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring
> <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>;
> linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba
> Visconti Video Input Interface bindings
>
> Hi Krzysztof,
>
> On Tue, Jan 17, 2023 at 06:01:27PM +0100, Krzysztof Kozlowski wrote:
> > On 17/01/2023 16:58, Laurent Pinchart wrote:
> > > On Tue, Jan 17, 2023 at 04:42:51PM +0100, Krzysztof Kozlowski wrote:
> > >> On 17/01/2023 16:26, Laurent Pinchart wrote:
> > >>>
> > >>>> +
> > >>>> + clock-lanes:
> > >>>> + description: VIIF supports 1 clock line
> > >>>
> > >>> s/line/lane/
Sorry for a late reply.
I'll fix the description.
> > >>>
> > >>>> + const: 0
> > >>>
> > >>> I would also add
> > >>>
> > >>> clock-noncontinuous: true
> > >>> link-frequencies: true
> > >>>
> > >>> to indicate that the above two properties are used by this device.
> > >>
> > >> No, these are coming from other schema and there is never need to
> > >> mention some property to indicate it is more used than other case.
> > >> None of the bindings are created such way, so this should not be
> exception.
> > >
> > > There are some bindings that do so, but that may not be a good
> > > enough reason, as there's a chance I wrote those myself :-)
> > >
> > > I would have sworn that at some point in the past the schema
> > > wouldn't have validated the example with this omitted. I'm not sure
> > > if something changed or if I got this wrong.
> >
> > You probably think about case when using additionalProperties:false,
> > where one has to explicitly list all valid properties. But not for
> > unevaluatedProperties:false.
>
> Possibly, yes.
>
> > > video-interfaces.yaml defines lots of properties applicable to
> > > endpoints. For a given device, those properties should be required
> >
> > required:
> > - foo
> >
> > > (easy, that's defined in the bindings), optional,
> >
> > by default (with unevaluatedProperties:false) or explicitly mention
> > "foo: true (with additionalProperties:false)
> >
> > > or forbidden. How do
> >
> > foo: false (with unevaluatedProperties:false) or by default (with
> > additionalProperties:false)
>
> I think we should default to the latter. video-interfaces.yaml contains lots of
> properties endpoint properties, most bindings will use less than half of them, so
> having to explicitly list all the ones that are not used with "foo: false" would be
> quite inconvenient. Furthermore, I expect more properties to be added to
> video-interfaces.yaml over time, and those shouldn't be accepted by default in
> existing bindings.
>
I caught up with this discussion after some exercise on JSON schema validator.
I'll remove "unevaluatedProperties: false" at the "endpoint" and add "aditionalProperties: false" instead.
Furthermore, I'll explicitly declare required properties (required: ["foo"]) and optional properties (properties: {foo: true}) for Visconti.
Is this correct understanding?
Are these changes also applied to "port", which is the parent node of the "endpoint" ?
> > > we differentiate between the latter two cases ?
>
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-01-30 9:06 ` yuji2.ishikawa
@ 2023-02-01 9:45 ` Laurent Pinchart
2023-02-01 11:24 ` yuji2.ishikawa
0 siblings, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-02-01 9:45 UTC (permalink / raw)
To: yuji2.ishikawa
Cc: krzysztof.kozlowski, hverkuil, mchehab, nobuhiro1.iwamatsu,
robh+dt, krzysztof.kozlowski+dt, rafael.j.wysocki, broonie,
linux-media, linux-arm-kernel, linux-kernel, devicetree
On Mon, Jan 30, 2023 at 09:06:25AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> On Monday, January 23, 2023 4:26 AM, Laurent Pinchart wrote:
> > On Tue, Jan 17, 2023 at 06:01:27PM +0100, Krzysztof Kozlowski wrote:
> > > On 17/01/2023 16:58, Laurent Pinchart wrote:
> > > > On Tue, Jan 17, 2023 at 04:42:51PM +0100, Krzysztof Kozlowski wrote:
> > > >> On 17/01/2023 16:26, Laurent Pinchart wrote:
> > > >>>
> > > >>>> +
> > > >>>> + clock-lanes:
> > > >>>> + description: VIIF supports 1 clock line
> > > >>>
> > > >>> s/line/lane/
>
> Sorry for a late reply.
> I'll fix the description.
>
> > > >>>
> > > >>>> + const: 0
> > > >>>
> > > >>> I would also add
> > > >>>
> > > >>> clock-noncontinuous: true
> > > >>> link-frequencies: true
> > > >>>
> > > >>> to indicate that the above two properties are used by this device.
> > > >>
> > > >> No, these are coming from other schema and there is never need to
> > > >> mention some property to indicate it is more used than other case.
> > > >> None of the bindings are created such way, so this should not be exception.
> > > >
> > > > There are some bindings that do so, but that may not be a good
> > > > enough reason, as there's a chance I wrote those myself :-)
> > > >
> > > > I would have sworn that at some point in the past the schema
> > > > wouldn't have validated the example with this omitted. I'm not sure
> > > > if something changed or if I got this wrong.
> > >
> > > You probably think about case when using additionalProperties:false,
> > > where one has to explicitly list all valid properties. But not for
> > > unevaluatedProperties:false.
> >
> > Possibly, yes.
> >
> > > > video-interfaces.yaml defines lots of properties applicable to
> > > > endpoints. For a given device, those properties should be required
> > >
> > > required:
> > > - foo
> > >
> > > > (easy, that's defined in the bindings), optional,
> > >
> > > by default (with unevaluatedProperties:false) or explicitly mention
> > > "foo: true (with additionalProperties:false)
> > >
> > > > or forbidden. How do
> > >
> > > foo: false (with unevaluatedProperties:false) or by default (with
> > > additionalProperties:false)
> >
> > I think we should default to the latter. video-interfaces.yaml contains lots of
> > properties endpoint properties, most bindings will use less than half of them, so
> > having to explicitly list all the ones that are not used with "foo: false" would be
> > quite inconvenient. Furthermore, I expect more properties to be added to
> > video-interfaces.yaml over time, and those shouldn't be accepted by default in
> > existing bindings.
> >
>
> I caught up with this discussion after some exercise on JSON schema validator.
> I'll remove "unevaluatedProperties: false" at the "endpoint" and add "aditionalProperties: false" instead.
> Furthermore, I'll explicitly declare required properties (required: ["foo"]) and optional properties (properties: {foo: true}) for Visconti.
> Is this correct understanding?
Looks very good to me !
> Are these changes also applied to "port", which is the parent node of
> the "endpoint" ?
That shouldn't be needed, as the "port" node should only have "endpoint"
children and no other properties (except for reg, and possibly
#address-cells and #size-cells of course).
> > > > we differentiate between the latter two cases ?
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings
2023-02-01 9:45 ` Laurent Pinchart
@ 2023-02-01 11:24 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-01 11:24 UTC (permalink / raw)
To: laurent.pinchart
Cc: krzysztof.kozlowski, hverkuil, mchehab, nobuhiro1.iwamatsu,
robh+dt, krzysztof.kozlowski+dt, rafael.j.wysocki, broonie,
linux-media, linux-arm-kernel, linux-kernel, devicetree
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Wednesday, February 1, 2023 6:46 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>
> Cc: krzysztof.kozlowski@linaro.org; hverkuil@xs4all.nl; mchehab@kernel.org;
> iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; rafael.j.wysocki@intel.com;
> broonie@kernel.org; linux-media@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba
> Visconti Video Input Interface bindings
>
> On Mon, Jan 30, 2023 at 09:06:25AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> > On Monday, January 23, 2023 4:26 AM, Laurent Pinchart wrote:
> > > On Tue, Jan 17, 2023 at 06:01:27PM +0100, Krzysztof Kozlowski wrote:
> > > > On 17/01/2023 16:58, Laurent Pinchart wrote:
> > > > > On Tue, Jan 17, 2023 at 04:42:51PM +0100, Krzysztof Kozlowski wrote:
> > > > >> On 17/01/2023 16:26, Laurent Pinchart wrote:
> > > > >>>
> > > > >>>> +
> > > > >>>> + clock-lanes:
> > > > >>>> + description: VIIF supports 1 clock line
> > > > >>>
> > > > >>> s/line/lane/
> >
> > Sorry for a late reply.
> > I'll fix the description.
> >
> > > > >>>
> > > > >>>> + const: 0
> > > > >>>
> > > > >>> I would also add
> > > > >>>
> > > > >>> clock-noncontinuous: true
> > > > >>> link-frequencies: true
> > > > >>>
> > > > >>> to indicate that the above two properties are used by this device.
> > > > >>
> > > > >> No, these are coming from other schema and there is never need
> > > > >> to mention some property to indicate it is more used than other case.
> > > > >> None of the bindings are created such way, so this should not be
> exception.
> > > > >
> > > > > There are some bindings that do so, but that may not be a good
> > > > > enough reason, as there's a chance I wrote those myself :-)
> > > > >
> > > > > I would have sworn that at some point in the past the schema
> > > > > wouldn't have validated the example with this omitted. I'm not
> > > > > sure if something changed or if I got this wrong.
> > > >
> > > > You probably think about case when using
> > > > additionalProperties:false, where one has to explicitly list all
> > > > valid properties. But not for unevaluatedProperties:false.
> > >
> > > Possibly, yes.
> > >
> > > > > video-interfaces.yaml defines lots of properties applicable to
> > > > > endpoints. For a given device, those properties should be
> > > > > required
> > > >
> > > > required:
> > > > - foo
> > > >
> > > > > (easy, that's defined in the bindings), optional,
> > > >
> > > > by default (with unevaluatedProperties:false) or explicitly
> > > > mention
> > > > "foo: true (with additionalProperties:false)
> > > >
> > > > > or forbidden. How do
> > > >
> > > > foo: false (with unevaluatedProperties:false) or by default (with
> > > > additionalProperties:false)
> > >
> > > I think we should default to the latter. video-interfaces.yaml
> > > contains lots of properties endpoint properties, most bindings will
> > > use less than half of them, so having to explicitly list all the
> > > ones that are not used with "foo: false" would be quite
> > > inconvenient. Furthermore, I expect more properties to be added to
> > > video-interfaces.yaml over time, and those shouldn't be accepted by default
> in existing bindings.
> > >
> >
> > I caught up with this discussion after some exercise on JSON schema
> validator.
> > I'll remove "unevaluatedProperties: false" at the "endpoint" and add
> "aditionalProperties: false" instead.
> > Furthermore, I'll explicitly declare required properties (required: ["foo"]) and
> optional properties (properties: {foo: true}) for Visconti.
> > Is this correct understanding?
>
> Looks very good to me !
>
> > Are these changes also applied to "port", which is the parent node of
> > the "endpoint" ?
>
> That shouldn't be needed, as the "port" node should only have "endpoint"
> children and no other properties (except for reg, and possibly #address-cells and
> #size-cells of course).
All right. I'll apply the change to "endpoint".
> > > > > we differentiate between the latter two cases ?
>
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 [PATCH v5 0/6] Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
2023-01-11 2:24 ` [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings Yuji Ishikawa
@ 2023-01-11 2:24 ` Yuji Ishikawa
2023-01-11 15:30 ` kernel test robot
` (4 more replies)
2023-01-11 2:24 ` [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace Yuji Ishikawa
` (3 subsequent siblings)
5 siblings, 5 replies; 42+ messages in thread
From: Yuji Ishikawa @ 2023-01-11 2:24 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree, yuji2.ishikawa
Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
The interface device includes CSI2 Receiver,
frame grabber, video DMAC and image signal processor.
This patch provides operations to handle registers of HW listed above.
The Video DMACs have 32bit address space
and currently corresponding IOMMU driver is not provided.
Therefore, memory-block address for captured image is 32bit IOVA
which is equal to 32bit-truncated phisical address.
When the Visconti IOMMU driver (currently under development) is accepted,
the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
---
Changelog v2:
- Resend v1 because a patch exceeds size limit.
Changelog v3:
- Adapted to media control framework
- Introduced ISP subdevice, capture device
- Remove private IOCTLs and add vendor specific V4L2 controls
- Change function name avoiding camelcase and uppercase letters
Changelog v4:
- Split patches because the v3 patch exceeds size limit
- Stop using ID number to identify driver instance:
- Use dynamically allocated structure to hold driver's context,
instead of static one indexed by ID number.
- Functions accept driver's context structure instead of ID number.
Changelog v5:
- no change
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 1 +
drivers/media/platform/visconti/Kconfig | 9 +
drivers/media/platform/visconti/Makefile | 8 +
drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
drivers/media/platform/visconti/hwd_viif.h | 710 +++++
.../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
.../platform/visconti/hwd_viif_internal.h | 340 ++
.../media/platform/visconti/hwd_viif_reg.h | 2802 +++++++++++++++++
include/uapi/linux/visconti_viif.h | 1724 ++++++++++
10 files changed, 7895 insertions(+)
create mode 100644 drivers/media/platform/visconti/Kconfig
create mode 100644 drivers/media/platform/visconti/Makefile
create mode 100644 drivers/media/platform/visconti/hwd_viif.c
create mode 100644 drivers/media/platform/visconti/hwd_viif.h
create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
create mode 100644 include/uapi/linux/visconti_viif.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index a9334263fa9..0908158036d 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -83,6 +83,7 @@ source "drivers/media/platform/sunxi/Kconfig"
source "drivers/media/platform/ti/Kconfig"
source "drivers/media/platform/verisilicon/Kconfig"
source "drivers/media/platform/via/Kconfig"
+source "drivers/media/platform/visconti/Kconfig"
source "drivers/media/platform/xilinx/Kconfig"
endif # MEDIA_PLATFORM_DRIVERS
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index a91f4202427..1c67cb56244 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -26,6 +26,7 @@ obj-y += sunxi/
obj-y += ti/
obj-y += verisilicon/
obj-y += via/
+obj-y += visconti/
obj-y += xilinx/
# Please place here only ancillary drivers that aren't SoC-specific
diff --git a/drivers/media/platform/visconti/Kconfig b/drivers/media/platform/visconti/Kconfig
new file mode 100644
index 00000000000..031e4610809
--- /dev/null
+++ b/drivers/media/platform/visconti/Kconfig
@@ -0,0 +1,9 @@
+config VIDEO_VISCONTI_VIIF
+ tristate "Visconti Camera Interface driver"
+ depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER && VIDEO_DEV
+ depends on ARCH_VISCONTI
+ select VIDEOBUF2_DMA_CONTIG
+ select V4L2_FWNODE
+ help
+ This is V4L2 driver for Toshiba Visconti Camera Interface driver
+
diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
new file mode 100644
index 00000000000..e14b904df75
--- /dev/null
+++ b/drivers/media/platform/visconti/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the Visconti video input device driver
+#
+
+visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
+
+obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
diff --git a/drivers/media/platform/visconti/hwd_viif.c b/drivers/media/platform/visconti/hwd_viif.c
new file mode 100644
index 00000000000..260293fa4d0
--- /dev/null
+++ b/drivers/media/platform/visconti/hwd_viif.c
@@ -0,0 +1,1690 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "hwd_viif.h"
+#include "hwd_viif_internal.h"
+
+/* MIPI CSI2 DataType definition */
+#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
+#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
+#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
+#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
+#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
+#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
+#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
+#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
+
+struct hwd_viif_res *allocate_viif_res(struct device *dev, void *csi2host_vaddr,
+ void *capture_vaddr)
+{
+ struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res), GFP_KERNEL);
+
+ res->csi2host_reg = csi2host_vaddr;
+ res->capture_reg = capture_vaddr;
+ res->run_flag_main = (bool)false;
+ return res;
+}
+
+/* Convert the unit of time-period (from sysclk, to num lines in the image) */
+static u32 sysclk_to_numlines(u64 time_in_sysclk, const struct hwd_viif_input_img *img)
+{
+ u64 v1 = time_in_sysclk * (u64)img->pixel_clock;
+ u64 v2 = (u64)img->htotal_size * HWD_VIIF_SYS_CLK;
+
+ return (u32)(v1 / v2);
+}
+
+static u32 lineperiod_in_sysclk(u64 hsize, u64 pixel_clock)
+{
+ return (u32)(hsize * HWD_VIIF_SYS_CLK / pixel_clock);
+}
+
+/**
+ * hwd_viif_main_set_unit() - Set static configuration of MAIN unit(CH0 or CH1)
+ *
+ * @dt_image: DT of image [0x10-0x17, 0x1B, 0x1E, 0x1F, 0x22, 0x24-0x27, 0x2A-0x3F])
+ * @in_img: Pointer to input image information
+ * @color_type: Color type of image [0x0, 0x1E, 0x1F, 0x22, 0x24, 0x2A-0x2D]
+ * @rawpack: RAW pack mode. For more refer @ref hwd_viif_raw_pack_mode
+ * @yuv_conv: YUV422 to YUV444 conversion mode. For more refer @ref hwd_viif_yuv_conversion_mode
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "dt_image" is out of range
+ * - [2] "in_img" is NULL
+ * - [3] member of "in_img" is invalid
+ * - [4] "color_type" is out of range
+ * - [5] "color_type" doesn't meet the condition shown in the below note
+ * - [6] "rawpack" is out of range
+ * - [7] "rawpack" is not HWD_VIIF_RAWPACK_DISABLE when color_type is other than RAW(0x2A-0x2C)
+ * - [8] "yuv_conv" is out of range
+ * - [9] "yuv_conv" is not HWD_VIIF_YUV_CONV_REPEAT
+ * when color_type is other than YUV422(0x1E or 0x1F)
+ *
+ * Note: valid combination between "dt_image" and "color_type" is
+ * - when "dt_image" is [0x10-0x17, 0x1B, 0x25-0x27, 0x2E-0x3F], "color_type" must be [0x2A-0x2D].
+ * - when "dt_image" is valid value and other than [0x10-0x17, 0x1B, 0x25-0x27, 0x2E-0x3F],
+ * "color_type" must be "dt_image"
+ */
+s32 hwd_viif_main_set_unit(struct hwd_viif_res *res, u32 dt_image,
+ const struct hwd_viif_input_img *in_img, u32 color_type, u32 rawpack,
+ u32 yuv_conv)
+{
+ u32 total_hact_size = 0U, total_vact_size = 0U;
+ u32 sw_delay0, sw_delay1, hw_delay;
+ u32 val, color, sysclk_num;
+ u32 i;
+
+ /*
+ * 0x00-0x09: ShortPacket/Undefined
+ * 0x18-0x1A: YUV420
+ * 0x1C,0x1D: YUV420 CSPS
+ * 0x20,0x21,0x23: RGB444, RGB555, RGB666
+ * 0x28,0x29: RAW6, RAW7
+ */
+ if (dt_image <= 0x09U || (dt_image >= 0x18U && dt_image <= 0x1AU) || dt_image == 0x1CU ||
+ dt_image == 0x1DU || dt_image == 0x20U || dt_image == 0x21U || dt_image == 0x23U ||
+ dt_image == 0x28U || dt_image == 0x29U || dt_image > HWD_VIIF_CSI2_MAX_DT) {
+ return -EINVAL;
+ }
+
+ /*Case: Generic Long Packet, Reserved, User-Defined*/
+ if ((dt_image >= 0x10U && dt_image <= 0x17U) || dt_image == 0x1bU ||
+ (dt_image >= 0x25U && dt_image <= 0x27U) || dt_image >= 0x2eU) {
+ if (color_type != CSI2_DT_RAW8 && color_type != CSI2_DT_RAW10 &&
+ color_type != CSI2_DT_RAW12 && color_type != CSI2_DT_RAW14) {
+ return -EINVAL;
+ }
+ } else {
+ /*Case: Otherwise: YUV, RGB, RAW*/
+ /*Constraint: color_type must be dt_image*/
+ if (color_type != dt_image)
+ return -EINVAL;
+ }
+
+ if (!in_img)
+ return -EINVAL;
+ if (rawpack != HWD_VIIF_RAWPACK_DISABLE && rawpack != HWD_VIIF_RAWPACK_MSBFIRST &&
+ rawpack != HWD_VIIF_RAWPACK_LSBFIRST) {
+ return -EINVAL;
+ }
+ if (color_type != CSI2_DT_RAW8 && color_type != CSI2_DT_RAW10 &&
+ color_type != CSI2_DT_RAW12 && rawpack != HWD_VIIF_RAWPACK_DISABLE) {
+ return -EINVAL;
+ }
+
+ if (in_img->pixel_clock < HWD_VIIF_MIN_PIXEL_CLOCK ||
+ in_img->pixel_clock > HWD_VIIF_MAX_PIXEL_CLOCK ||
+ in_img->htotal_size < HWD_VIIF_MIN_HTOTAL_PIXEL ||
+ in_img->htotal_size > HWD_VIIF_MAX_HTOTAL_PIXEL ||
+ in_img->vtotal_size < HWD_VIIF_MIN_VTOTAL_LINE ||
+ in_img->vtotal_size > HWD_VIIF_MAX_VTOTAL_LINE ||
+ in_img->vbp_size < HWD_VIIF_MIN_VBP_LINE || in_img->vbp_size > HWD_VIIF_MAX_VBP_LINE ||
+ ((in_img->hactive_size % 2U) != 0U) || ((in_img->vactive_size % 2U) != 0U)) {
+ return -EINVAL;
+ }
+
+ if (in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_LINE &&
+ in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL) {
+ return -EINVAL;
+ }
+
+ if (in_img->input_num < HWD_VIIF_L1_INPUT_NUM_MIN ||
+ in_img->input_num > HWD_VIIF_L1_INPUT_NUM_MAX) {
+ return -EINVAL;
+ }
+
+ if (in_img->hobc_width != 0U && in_img->hobc_width != 16U && in_img->hobc_width != 32U &&
+ in_img->hobc_width != 64U && in_img->hobc_width != 128U) {
+ return -EINVAL;
+ }
+
+ if (in_img->hobc_margin > 30U || ((in_img->hobc_margin % 2U) != 0U))
+ return -EINVAL;
+
+ if (in_img->hobc_width == 0U && in_img->hobc_margin != 0U)
+ return -EINVAL;
+
+ if (in_img->hobc_width != 0U && in_img->hobc_margin == 0U)
+ return -EINVAL;
+
+ if (color_type == CSI2_DT_RAW8 || color_type == CSI2_DT_RAW10 ||
+ color_type == CSI2_DT_RAW12 || color_type == CSI2_DT_RAW14) {
+ /* parameter check in case of L1ISP(in case of RAW) */
+ if (in_img->hactive_size < HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP ||
+ in_img->hactive_size > HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP ||
+ in_img->vactive_size < HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP ||
+ in_img->vactive_size > HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP ||
+ ((in_img->hactive_size % 8U) != 0U)) {
+ return -EINVAL;
+ }
+
+ /* check vbp range in case of L1ISP on */
+ /* the constant value "7" is configuration margin */
+ val = sysclk_to_numlines(
+ HWD_VIIF_TABLE_LOAD_TIME + HWD_VIIF_REGBUF_ACCESS_TIME * 2U, in_img) +
+ HWD_VIIF_L1_DELAY_W_HDRC + 7U;
+ if (in_img->vbp_size < val)
+ return -EINVAL;
+
+ /* calculate total of horizontal active size and vertical active size */
+ if (rawpack != HWD_VIIF_RAWPACK_DISABLE) {
+ val = (in_img->hactive_size + in_img->hobc_width + in_img->hobc_margin) *
+ 2U;
+ } else {
+ val = in_img->hactive_size + in_img->hobc_width + in_img->hobc_margin;
+ }
+ if (in_img->interpolation_mode == HWD_VIIF_L1_INPUT_INTERPOLATION_LINE) {
+ total_hact_size = val;
+ total_vact_size = in_img->vactive_size * in_img->input_num;
+ } else {
+ total_hact_size = val * in_img->input_num;
+ total_vact_size = in_img->vactive_size;
+ }
+ } else {
+ /* OTHER input than RAW(L1ISP is off) */
+ if (in_img->hactive_size < HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP ||
+ in_img->hactive_size > HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP ||
+ in_img->vactive_size < HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP ||
+ in_img->vactive_size > HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP ||
+ in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_LINE ||
+ in_img->input_num != HWD_VIIF_L1_INPUT_NUM_MIN || in_img->hobc_width != 0U) {
+ return -EINVAL;
+ }
+
+ /* check vbp range in case of L1ISP off */
+ /* the constant value "16" is configuration margin */
+ val = sysclk_to_numlines(HWD_VIIF_TABLE_LOAD_TIME + HWD_VIIF_REGBUF_ACCESS_TIME,
+ in_img) +
+ 16U;
+ if (in_img->vbp_size < val)
+ return -EINVAL;
+
+ total_hact_size = in_img->hactive_size;
+ total_vact_size = in_img->vactive_size;
+ }
+
+ if (in_img->htotal_size <= total_hact_size ||
+ (in_img->vtotal_size <= (in_img->vbp_size + total_vact_size))) {
+ return -EINVAL;
+ }
+
+ if (yuv_conv != HWD_VIIF_YUV_CONV_REPEAT && yuv_conv != HWD_VIIF_YUV_CONV_INTERPOLATION)
+ return -EINVAL;
+
+ if (color_type != CSI2_DT_YUV4228B && color_type != CSI2_DT_YUV42210B &&
+ yuv_conv != HWD_VIIF_YUV_CONV_REPEAT) {
+ return -EINVAL;
+ }
+
+ /* Set DT and color type of image data */
+ writel((color_type << 8U) | dt_image, &res->capture_reg->sys.IPORTM_MAIN_DT);
+ writel(0x00, &res->capture_reg->sys.IPORTM_OTHER);
+ res->dt_image_main_w_isp = dt_image;
+
+ /* Set back porch*/
+ writel((in_img->vbp_size << 16U) | HWD_VIIF_HBP_SYSCLK,
+ &res->capture_reg->sys.BACK_PORCH_M);
+
+ /* single pulse of vsync is input to DPGM */
+ writel(HWD_VIIF_DPGM_VSYNC_PULSE, &res->capture_reg->sys.DPGM_VSYNC_SOURCE);
+
+ /* image data will be input */
+ /* set preprocess type before L2ISP based on color_type. */
+ if (color_type == CSI2_DT_YUV4228B || color_type == CSI2_DT_YUV42210B) {
+ /* YUV422 */
+ color = 3U;
+ } else if (color_type == CSI2_DT_RGB565 || color_type == CSI2_DT_RGB888) {
+ /* RGB */
+ color = 0U;
+ } else {
+ /* RGB or YUV444 from L1ISP */
+ color = 1U;
+ }
+ writel(color << 4U, &res->capture_reg->sys.PREPROCCESS_FMTM);
+
+ /* set Total size and valid size information of image data */
+ sysclk_num = lineperiod_in_sysclk(in_img->htotal_size, in_img->pixel_clock);
+ sysclk_num &= GENMASK(15, 0);
+ writel((in_img->vtotal_size << 16U) | sysclk_num, &res->capture_reg->sys.TOTALSIZE_M);
+ writel((total_vact_size << 16U) | total_hact_size, &res->capture_reg->sys.VALSIZE_M);
+
+ /* set image size information to L2ISP */
+ writel(in_img->vactive_size, &res->capture_reg->l2isp.L2_SENSOR_CROP_VSIZE);
+ writel(in_img->hactive_size, &res->capture_reg->l2isp.L2_SENSOR_CROP_HSIZE);
+
+ /* RAW input case */
+ if (color_type >= CSI2_DT_RAW8) {
+ val = (in_img->interpolation_mode << 3U) | (in_img->input_num);
+ writel(val, &res->capture_reg->l1isp.L1_IBUF_INPUT_ORDER);
+ writel(in_img->vactive_size, &res->capture_reg->l1isp.L1_SYSM_HEIGHT);
+ writel(in_img->hactive_size, &res->capture_reg->l1isp.L1_SYSM_WIDTH);
+ val = (in_img->hobc_margin << 8U) | in_img->hobc_width;
+ writel(val, &res->capture_reg->l1isp.L1_HOBC_MARGIN);
+ }
+
+ /* Set rawpack */
+ writel(rawpack, &res->capture_reg->sys.IPORTM_MAIN_RAW);
+
+ /* Set yuv_conv */
+ writel(yuv_conv, &res->capture_reg->sys.PREPROCCESS_C24M);
+
+ /* Set vsync delay */
+ hw_delay = in_img->vbp_size - sysclk_to_numlines(HWD_VIIF_TABLE_LOAD_TIME, in_img) + 4U;
+ hw_delay = min(hw_delay, 255U);
+
+ sw_delay0 = hw_delay - sysclk_to_numlines(HWD_VIIF_REGBUF_ACCESS_TIME, in_img) + 2U;
+
+ if (color_type == CSI2_DT_RAW8 || color_type == CSI2_DT_RAW10 ||
+ color_type == CSI2_DT_RAW12 || color_type == CSI2_DT_RAW14) {
+ sw_delay1 = sysclk_to_numlines(HWD_VIIF_REGBUF_ACCESS_TIME, in_img) +
+ HWD_VIIF_L1_DELAY_WO_HDRC + 1U;
+ } else {
+ sw_delay1 = 10U;
+ }
+ writel(sw_delay0 << 16U, &res->capture_reg->sys.INT_M0_LINE);
+ writel((sw_delay1 << 16U) | hw_delay, &res->capture_reg->sys.INT_M1_LINE);
+
+ /* M2_LINE is the same condition as M1_LINE */
+ writel((sw_delay1 << 16U) | hw_delay, &res->capture_reg->sys.INT_M2_LINE);
+
+ /* Update internal information of pixel clock, htotal_size, information of L2 ROI */
+ res->pixel_clock = in_img->pixel_clock;
+ res->htotal_size = in_img->htotal_size;
+ res->l2_roi_path_info.roi_num = 0;
+ for (i = 0; i < HWD_VIIF_MAX_POST_NUM; i++) {
+ res->l2_roi_path_info.post_enable_flag[i] = false;
+ res->l2_roi_path_info.post_crop_x[i] = 0;
+ res->l2_roi_path_info.post_crop_y[i] = 0;
+ res->l2_roi_path_info.post_crop_w[i] = 0;
+ res->l2_roi_path_info.post_crop_h[i] = 0;
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_main_mask_vlatch() - Control Vlatch mask of MAIN unit
+ *
+ * @enable: or disable Vlatch mask of MAIN unit. For more refer @ref hwd_viif_enable_flag.
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - "enable" is out of range
+ */
+s32 hwd_viif_main_mask_vlatch(struct hwd_viif_res *res, u32 enable)
+{
+ if (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
+ return -EINVAL;
+
+ if (enable == HWD_VIIF_ENABLE)
+ enable |= HWD_VIIF_ISP_VLATCH_MASK;
+
+ /* Control Vlatch mask */
+ writel(enable, &res->capture_reg->sys.IPORTM0_LD);
+ writel(enable, &res->capture_reg->sys.IPORTM1_LD);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_main_status_err_set_irq_mask() - Set mask condition for STATUS error of MAIN unit
+ *
+ * @mask: STATUS error mask condition
+ * Return: None
+ */
+void hwd_viif_main_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask)
+{
+ writel(mask, &res->capture_reg->sys.INT_M_MASK);
+}
+
+/**
+ * hwd_viif_main_vsync_set_irq_mask() - Set mask condition for Vsync of MAIN unit
+ *
+ * @mask: Vsync mask condition
+ * Return: None
+ */
+void hwd_viif_main_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask)
+{
+ writel(mask, &res->capture_reg->sys.INT_M_SYNC_MASK);
+}
+
+#define VDM_BIT_W00 BIT(0)
+#define VDM_BIT_W01 BIT(1)
+#define VDM_BIT_W02 BIT(2)
+#define VDM_BIT_W03 BIT(3)
+#define VDM_BIT_W04 BIT(4)
+#define VDM_BIT_W05 BIT(5)
+#define VDM_BIT_R00 BIT(0)
+#define VDM_BIT_R01 BIT(1)
+#define VDM_BIT_R02 BIT(2)
+
+#define VDM_ABORT_MASK_SUB_W (VDM_BIT_W03 | VDM_BIT_W04 | VDM_BIT_W05)
+#define VDM_ABORT_MASK_MAIN_W (VDM_BIT_W00 | VDM_BIT_W01 | VDM_BIT_W02)
+#define VDM_ABORT_MASK_MAIN_R (VDM_BIT_R00 | VDM_BIT_R01 | VDM_BIT_R02)
+
+/**
+ * hwd_viif_sub_set_unit() - Set static configuration of SUB unit
+ *
+ * @dt_image: DT of image [0x1E, 0x1F, 0x22, 0x24, 0x2A-0x2D]
+ * @in_img: Pointer to input image information
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "dt_image" is out of range
+ * - [2] "in_img" is NULL
+ * - [3] member of "in_img" is invalid
+ */
+s32 hwd_viif_sub_set_unit(struct hwd_viif_res *res, u32 dt_image,
+ const struct hwd_viif_input_img *in_img)
+{
+ u32 sysclk_num, temp_delay;
+
+ if (dt_image < 0x2aU || dt_image > 0x2dU)
+ return -EINVAL;
+
+ if (!in_img)
+ return -EINVAL;
+
+ if (in_img->hactive_size != 0U ||
+ in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_LINE ||
+ in_img->input_num != HWD_VIIF_L1_INPUT_NUM_MIN || in_img->hobc_width != 0U ||
+ in_img->hobc_margin != 0U) {
+ return -EINVAL;
+ }
+
+ if (in_img->pixel_clock < HWD_VIIF_MIN_PIXEL_CLOCK ||
+ in_img->pixel_clock > HWD_VIIF_MAX_PIXEL_CLOCK ||
+ in_img->htotal_size < HWD_VIIF_MIN_HTOTAL_PIXEL ||
+ in_img->htotal_size > HWD_VIIF_MAX_HTOTAL_PIXEL ||
+ in_img->vtotal_size < HWD_VIIF_MIN_VTOTAL_LINE ||
+ in_img->vtotal_size > HWD_VIIF_MAX_VTOTAL_LINE ||
+ in_img->vbp_size < HWD_VIIF_MIN_VBP_LINE || in_img->vbp_size > HWD_VIIF_MAX_VBP_LINE ||
+ in_img->vactive_size < HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP ||
+ in_img->vactive_size > HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP ||
+ ((in_img->vactive_size % 2U) != 0U)) {
+ return -EINVAL;
+ }
+
+ if (in_img->vtotal_size <= (in_img->vbp_size + in_img->vactive_size))
+ return -EINVAL;
+
+ /* Set DT of image data and DT of long packet data*/
+ writel(dt_image, &res->capture_reg->sys.IPORTS_MAIN_DT);
+ writel(0x00, &res->capture_reg->sys.IPORTS_OTHER);
+
+ /* Set line size and delay value of delayed Vsync */
+ sysclk_num = lineperiod_in_sysclk(in_img->htotal_size, in_img->pixel_clock);
+ writel(sysclk_num & GENMASK(15, 0), &res->capture_reg->sys.INT_SA0_LINE);
+ temp_delay = in_img->vbp_size - 4U;
+ if (temp_delay > 255U) {
+ /* Replace the value with HW max spec */
+ temp_delay = 255U;
+ }
+ writel(temp_delay, &res->capture_reg->sys.INT_SA1_LINE);
+
+ return 0;
+}
+
+/* DMA settings */
+#define VDMAC_SRAM_BASE_ADDR_W03 0x440U
+#define SRAM_SIZE_W_PORT 0x200
+#define PORT_SEL_SUB_IMAGE 3
+
+/**
+ * hwd_viif_sub_set_img_transmission() - Set image transfer condition of SUB unit
+ *
+ * @img: Pointer to output image information
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] Member of "img" is invalid
+ */
+s32 hwd_viif_sub_set_img_transmission(struct hwd_viif_res *res, const struct hwd_viif_img *img)
+{
+ struct hwd_viif_vdm_write_port_reg *wport;
+ u32 img_start_addr, img_end_addr;
+ u32 data_width, pitch, height;
+ u32 k, port_control;
+
+ /* disable VDMAC when img is NULL */
+ if (!img) {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
+ port_control = ~((u32)1U << 3U) & readl(&res->capture_reg->vdm.VDM_W_ENABLE);
+ writel(port_control, &res->capture_reg->vdm.VDM_W_ENABLE);
+ return 0;
+ }
+
+ if (((img->width % 2U) != 0U) || ((img->height % 2U) != 0U))
+ return -EINVAL;
+
+ if (img->width < HWD_VIIF_MIN_OUTPUT_IMG_WIDTH ||
+ img->height < HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT ||
+ img->width > HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB ||
+ img->height > HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB) {
+ return -EINVAL;
+ }
+
+ img_start_addr = (u32)img->pixelmap[0].pmap_paddr;
+ pitch = img->pixelmap[0].pitch;
+ height = img->height;
+
+ switch (img->format) {
+ case HWD_VIIF_ONE_COLOR_8:
+ data_width = 0U;
+ img_end_addr = img_start_addr + img->width - 1U;
+ k = 1;
+ break;
+ case HWD_VIIF_ONE_COLOR_16:
+ data_width = 1U;
+ img_end_addr = img_start_addr + (img->width * 2U) - 1U;
+ k = 2;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if ((img_start_addr % 4U) != 0U)
+ return -EINVAL;
+
+ if ((pitch < (img->width * k)) || pitch > HWD_VIIF_MAX_PITCH || ((pitch % 4U) != 0U))
+ return -EINVAL;
+
+ wport = &res->capture_reg->vdm.w_port[PORT_SEL_SUB_IMAGE];
+ writel(VDMAC_SRAM_BASE_ADDR_W03, &wport->VDM_W_SRAM_BASE);
+ writel(SRAM_SIZE_W_PORT, &wport->VDM_W_SRAM_SIZE);
+ writel(img_start_addr, &wport->VDM_W_STADR);
+ writel(img_end_addr, &wport->VDM_W_ENDADR);
+ writel(height, &wport->VDM_W_HEIGHT);
+ writel(pitch, &wport->VDM_W_PITCH);
+ writel(data_width << 8U, &wport->VDM_W_CFG0);
+ port_control = BIT(3) | readl(&res->capture_reg->vdm.VDM_W_ENABLE);
+ writel(port_control, &res->capture_reg->vdm.VDM_W_ENABLE);
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->sys.IPORTS_IMGEN);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_sub_status_err_set_irq_mask() -
+ * Set mask condition for STATUS error of SUB unit or VOIF loopback
+ *
+ * @mask: STATUS error mask condition
+ * Return: None
+ */
+void hwd_viif_sub_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask)
+{
+ writel(mask, &res->capture_reg->sys.INT_S_MASK);
+}
+
+/**
+ * hwd_viif_sub_vsync_set_irq_mask() - Set mask condition for Vsync of SUB unit or VOIF loopback
+ *
+ * @mask: Vsync mask condition
+ * Return: None
+ */
+void hwd_viif_sub_vsync_set_irq_mask(struct hwd_viif_res *res, const u32 mask)
+{
+ writel(mask, &res->capture_reg->sys.INT_S_SYNC_MASK);
+}
+
+/**
+ * hwd_viif_isp_set_regbuf_auto_transmission() - Set register buffer auto transmission
+ *
+ * Return: None
+ */
+void hwd_viif_isp_set_regbuf_auto_transmission(struct hwd_viif_res *res)
+{
+ u32 val;
+
+ /* Set parameters for auto read transmission of register buffer */
+
+ if (res->dt_image_main_w_isp != 0x0U) {
+ /*
+ * configuration is done
+ * only when dt_image is not 0, means image data is input to ISP.
+ */
+ writel(0x0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
+ writel(0x0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
+ writel(HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT,
+ &res->capture_reg->l1isp.L1_CRGBF_TRN_RBADDR);
+ writel(HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT,
+ &res->capture_reg->l1isp.L1_CRGBF_TRN_READDR);
+ writel(HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT,
+ &res->capture_reg->l2isp.L2_CRGBF_TRN_RBADDR);
+ writel(HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT,
+ &res->capture_reg->l2isp.L2_CRGBF_TRN_READDR);
+ val = BIT(16);
+ writel(val, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
+ writel(val, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
+ }
+}
+
+/**
+ * hwd_viif_isp_disable_regbuf_auto_transmission() - Disable register buffer auto transmission
+ *
+ * Return: None
+ */
+void hwd_viif_isp_disable_regbuf_auto_transmission(struct hwd_viif_res *res)
+{
+ if (res->dt_image_main_w_isp != 0x0U) {
+ writel(0x0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
+ writel(0x0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
+ }
+}
+
+/**
+ * hwd_viif_isp_guard_start() - stop register auto update
+ *
+ *
+ * This function call stops update of some hardware registers
+ * while the manual setup of VIIF, L1ISP registers is in progress.
+ *
+ * * regbuf control: load/store HW register (settings, status) values to backup SRAM.
+ * * vlatch control: copy timer-counter register value to status register.
+ */
+void hwd_viif_isp_guard_start(struct hwd_viif_res *res)
+{
+ hwd_viif_isp_disable_regbuf_auto_transmission(res);
+ ndelay(500);
+ hwd_viif_main_mask_vlatch(res, HWD_VIIF_ENABLE);
+}
+
+/**
+ * hwd_viif_isp_guard_start() - restart register auto update
+ *
+ *
+ * see also hwd_viif_isp_guard_start().
+ */
+void hwd_viif_isp_guard_end(struct hwd_viif_res *res)
+{
+ hwd_viif_main_mask_vlatch(res, HWD_VIIF_DISABLE);
+ hwd_viif_isp_set_regbuf_auto_transmission(res);
+}
+
+#define L2_STATUS_REPORT_MASK 0x1eU
+
+/**
+ * hwd_viif_isp_get_info() - Get processing information of L1ISP and L2ISP
+ *
+ * @l1_info: L1ISP processing information
+ * @l2_transfer_status: status of L2ISP transmission
+ * Return: None
+ */
+void hwd_viif_isp_get_info(struct hwd_viif_res *res, struct hwd_viif_l1_info *l1_info,
+ u32 *l2_transfer_status)
+{
+ u32 val, l2_status;
+ int i, j;
+
+ if (l1_info) {
+ /* change register buffer to regbuf0 where driver gets information */
+ writel(HWD_VIIF_ISP_REGBUF_MODE_BUFFER, &res->capture_reg->l1isp.L1_CRGBF_ACC_CONF);
+
+ /* get AWB info */
+ l1_info->awb_ave_u = readl(&res->capture_reg->l1isp.L1_AWHB_AVE_USIG);
+ l1_info->awb_ave_v = readl(&res->capture_reg->l1isp.L1_AWHB_AVE_VSIG);
+ l1_info->awb_accumulated_pixel = readl(&res->capture_reg->l1isp.L1_AWHB_NUM_UVON);
+ l1_info->awb_gain_r = readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAINR);
+ l1_info->awb_gain_g = readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAING);
+ l1_info->awb_gain_b = readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAINB);
+ val = readl(&res->capture_reg->l1isp.L1_AWHB_R_CTR_STOP);
+ l1_info->awb_status_u = (FIELD_GET(BIT(1), val) != 0);
+ l1_info->awb_status_v = (FIELD_GET(BIT(0), val) != 0);
+
+ /* get average luminance info */
+ l1_info->avg_lum_weight = readl(&res->capture_reg->l1isp.L1_AEXP_RESULT_AVE);
+ val = readl(&res->capture_reg->l1isp.L1_AEXP_SATUR_BLACK_PIXNUM);
+ l1_info->avg_satur_pixnum = FIELD_GET(GENMASK(31, 16), val);
+ l1_info->avg_black_pixnum = FIELD_GET(GENMASK(15, 0), val);
+ for (i = 0; i < 8; i++) {
+ for (j = 0; j < 8; j++) {
+ l1_info->avg_lum_block[i][j] =
+ readl(&res->capture_reg->l1isp.L1_AEXP_AVE[i][j]);
+ }
+ }
+ l1_info->avg_lum_four_line_lum[0] =
+ readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES0);
+ l1_info->avg_lum_four_line_lum[1] =
+ readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES1);
+ l1_info->avg_lum_four_line_lum[2] =
+ readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES2);
+ l1_info->avg_lum_four_line_lum[3] =
+ readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES3);
+
+ /* revert to register access from register buffer access */
+ writel(HWD_VIIF_ISP_REGBUF_MODE_BYPASS, &res->capture_reg->l1isp.L1_CRGBF_ACC_CONF);
+ }
+
+ if (l2_transfer_status) {
+ /* get L2ISP abort information */
+ l2_status = readl(&res->capture_reg->l2isp.L2_CRGBF_ISP_INT);
+ writel(l2_status, &res->capture_reg->l2isp.L2_CRGBF_ISP_INT);
+ *l2_transfer_status = l2_status & L2_STATUS_REPORT_MASK;
+ }
+}
+
+/**
+ * hwd_viif_isp_set_regbuf_irq_mask() - Set mask condition for ISP register buffer
+ *
+ * @mask_l1: Pointer to mask configuration for L1ISP register buffer interruption
+ * @mask_l2: Pointer to mask configuration for L2ISP register buffer interruption
+ * Return: None
+ */
+void hwd_viif_isp_set_regbuf_irq_mask(struct hwd_viif_res *res, const u32 *mask_l1,
+ const u32 *mask_l2)
+{
+ writel(*mask_l1, &res->capture_reg->l1isp.L1_CRGBF_INT_MASK);
+ writel(*mask_l2, &res->capture_reg->l2isp.L2_CRGBF_INT_MASK);
+}
+
+/**
+ * hwd_viif_l2_set_input_csc() - Set input CSC parameters of L2ISP
+ *
+ * @param: Pointer to input csc parameters of L2ISP
+ * @is_l1_rgb: input information of L2ISP
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] Member of "param" is invalid
+ */
+s32 hwd_viif_l2_set_input_csc(struct hwd_viif_res *res, const struct hwd_viif_csc_param *param,
+ bool is_l1_rgb)
+{
+ struct hwd_viif_csc_param hwd_param;
+ u32 enable = HWD_VIIF_ENABLE;
+ bool csc_enable_flag = true;
+ u32 i, val;
+
+ if (param) {
+ if (param->r_cr_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->g_y_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->b_cb_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->r_cr_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->g_y_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->b_cb_out_offset > HWD_VIIF_CSC_MAX_OFFSET) {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < HWD_VIIF_CSC_MAX_COEF_NUM; i++) {
+ if (param->coef[i] > HWD_VIIF_CSC_MAX_COEF_VALUE)
+ return -EINVAL;
+ }
+
+ if (is_l1_rgb) {
+ /* translated parameters are used */
+ hwd_param.r_cr_in_offset = param->b_cb_in_offset;
+ hwd_param.g_y_in_offset = param->r_cr_in_offset;
+ hwd_param.b_cb_in_offset = param->g_y_in_offset;
+ hwd_param.r_cr_out_offset = param->r_cr_out_offset;
+ hwd_param.g_y_out_offset = param->g_y_out_offset;
+ hwd_param.b_cb_out_offset = param->b_cb_out_offset;
+ hwd_param.coef[0] = param->coef[2];
+ hwd_param.coef[1] = param->coef[0];
+ hwd_param.coef[2] = param->coef[1];
+ hwd_param.coef[3] = param->coef[5];
+ hwd_param.coef[4] = param->coef[3];
+ hwd_param.coef[5] = param->coef[4];
+ hwd_param.coef[6] = param->coef[8];
+ hwd_param.coef[7] = param->coef[6];
+ hwd_param.coef[8] = param->coef[7];
+ } else {
+ /* original parameters are used */
+ hwd_param.r_cr_in_offset = param->r_cr_in_offset;
+ hwd_param.g_y_in_offset = param->g_y_in_offset;
+ hwd_param.b_cb_in_offset = param->b_cb_in_offset;
+ hwd_param.r_cr_out_offset = param->r_cr_out_offset;
+ hwd_param.g_y_out_offset = param->g_y_out_offset;
+ hwd_param.b_cb_out_offset = param->b_cb_out_offset;
+ hwd_param.coef[0] = param->coef[0];
+ hwd_param.coef[1] = param->coef[1];
+ hwd_param.coef[2] = param->coef[2];
+ hwd_param.coef[3] = param->coef[3];
+ hwd_param.coef[4] = param->coef[4];
+ hwd_param.coef[5] = param->coef[5];
+ hwd_param.coef[6] = param->coef[6];
+ hwd_param.coef[7] = param->coef[7];
+ hwd_param.coef[8] = param->coef[8];
+ }
+ } else {
+ if (is_l1_rgb) {
+ /* fixed parameters are used */
+ hwd_param.r_cr_in_offset = 0U;
+ hwd_param.g_y_in_offset = 0U;
+ hwd_param.b_cb_in_offset = 0U;
+ hwd_param.r_cr_out_offset = 0U;
+ hwd_param.g_y_out_offset = 0U;
+ hwd_param.b_cb_out_offset = 0U;
+ hwd_param.coef[0] = 0U;
+ hwd_param.coef[1] = 0x1000U;
+ hwd_param.coef[2] = 0U;
+ hwd_param.coef[3] = 0U;
+ hwd_param.coef[4] = 0U;
+ hwd_param.coef[5] = 0x1000U;
+ hwd_param.coef[6] = 0x1000U;
+ hwd_param.coef[7] = 0U;
+ hwd_param.coef[8] = 0U;
+ } else {
+ /* csc is disabled */
+ enable = HWD_VIIF_DISABLE;
+ csc_enable_flag = false;
+ }
+ }
+
+ if (csc_enable_flag) {
+ writel(hwd_param.g_y_in_offset,
+ &res->capture_reg->sys.l2isp_input_csc.MTB_YG_OFFSETI);
+ writel(hwd_param.coef[0], &res->capture_reg->sys.l2isp_input_csc.MTB_YG1);
+ val = (hwd_param.coef[1] << HWD_VIIF_MTB_CB_YG_COEF_OFFSET) |
+ (hwd_param.coef[2] << HWD_VIIF_MTB_CR_YG_COEF_OFFSET);
+ writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_YG2);
+ writel(hwd_param.g_y_out_offset,
+ &res->capture_reg->sys.l2isp_input_csc.MTB_YG_OFFSETO);
+ writel(hwd_param.b_cb_in_offset,
+ &res->capture_reg->sys.l2isp_input_csc.MTB_CB_OFFSETI);
+ writel(hwd_param.coef[3], &res->capture_reg->sys.l2isp_input_csc.MTB_CB1);
+ val = (hwd_param.coef[4] << HWD_VIIF_MTB_CB_CB_COEF_OFFSET) |
+ (hwd_param.coef[5] << HWD_VIIF_MTB_CR_CB_COEF_OFFSET);
+ writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_CB2);
+ writel(hwd_param.b_cb_out_offset,
+ &res->capture_reg->sys.l2isp_input_csc.MTB_CB_OFFSETO);
+ writel(hwd_param.r_cr_in_offset,
+ &res->capture_reg->sys.l2isp_input_csc.MTB_CR_OFFSETI);
+ writel(hwd_param.coef[6], &res->capture_reg->sys.l2isp_input_csc.MTB_CR1);
+ val = (hwd_param.coef[7] << HWD_VIIF_MTB_CB_CR_COEF_OFFSET) |
+ (hwd_param.coef[8] << HWD_VIIF_MTB_CR_CR_COEF_OFFSET);
+ writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_CR2);
+ writel(hwd_param.r_cr_out_offset,
+ &res->capture_reg->sys.l2isp_input_csc.MTB_CR_OFFSETO);
+ }
+
+ writel(enable, &res->capture_reg->sys.l2isp_input_csc.MTB);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_undist() - Set undistortion parameters of L2ISP
+ *
+ * @param: Pointer to undistortion parameters of L2ISP
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "param" is NULL
+ * - [2] Member of "param" is invalid
+ */
+s32 hwd_viif_l2_set_undist(struct hwd_viif_res *res, const struct viif_l2_undist *param)
+{
+ u32 grid_num_h, grid_num_v;
+ u32 i, val;
+
+ if (!param)
+ return -EINVAL;
+
+ if (param->through_mode != HWD_VIIF_ENABLE && param->through_mode != HWD_VIIF_DISABLE)
+ return -EINVAL;
+
+ if (param->roi_mode[0] != HWD_VIIF_L2_UNDIST_POLY &&
+ param->roi_mode[0] != HWD_VIIF_L2_UNDIST_GRID &&
+ param->roi_mode[0] != HWD_VIIF_L2_UNDIST_POLY_TO_GRID &&
+ param->roi_mode[0] != HWD_VIIF_L2_UNDIST_GRID_TO_POLY) {
+ return -EINVAL;
+ }
+ if (param->roi_mode[1] != HWD_VIIF_L2_UNDIST_POLY &&
+ param->roi_mode[1] != HWD_VIIF_L2_UNDIST_GRID &&
+ param->roi_mode[1] != HWD_VIIF_L2_UNDIST_POLY_TO_GRID &&
+ param->roi_mode[1] != HWD_VIIF_L2_UNDIST_GRID_TO_POLY) {
+ return -EINVAL;
+ }
+ if (param->roi_write_area_delta[0] >= HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA ||
+ param->roi_write_area_delta[1] >= HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA ||
+ param->sensor_crop_ofs_h < HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H ||
+ param->sensor_crop_ofs_h > HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H ||
+ param->sensor_crop_ofs_v < HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V ||
+ param->sensor_crop_ofs_v > HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V ||
+ param->norm_scale > HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE ||
+ param->valid_r_norm2_poly >= HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2 ||
+ param->valid_r_norm2_grid >= HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2) {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < HWD_VIIF_L2_UNDIST_POLY_NUM; i++) {
+ if (param->poly_write_g_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
+ param->poly_write_g_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
+ param->poly_read_b_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
+ param->poly_read_b_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
+ param->poly_read_g_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
+ param->poly_read_g_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
+ param->poly_read_r_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
+ param->poly_read_r_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF) {
+ return -EINVAL;
+ }
+ }
+
+ if (param->grid_node_num_h < HWD_VIIF_L2_UNDIST_MIN_GRID_NUM ||
+ param->grid_node_num_h > HWD_VIIF_L2_UNDIST_MAX_GRID_NUM ||
+ param->grid_node_num_v < HWD_VIIF_L2_UNDIST_MIN_GRID_NUM ||
+ param->grid_node_num_v > HWD_VIIF_L2_UNDIST_MAX_GRID_NUM) {
+ return -EINVAL;
+ }
+
+ grid_num_h = param->grid_node_num_h;
+ grid_num_v = param->grid_node_num_v;
+ if ((grid_num_h % 2U) != 0U)
+ grid_num_h += 1U;
+
+ if ((grid_num_v % 2U) != 0U)
+ grid_num_v += 1U;
+
+ if ((grid_num_v * grid_num_h) > HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM ||
+ param->grid_patch_hsize_inv >= HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV ||
+ param->grid_patch_vsize_inv >= HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV) {
+ return -EINVAL;
+ }
+
+ val = readl(&res->capture_reg->l2isp.L2_SENSOR_CROP_HSIZE) & GENMASK(12, 0);
+ if (((param->sensor_crop_ofs_h / 2) + ((s16)val)) > 4095)
+ return -EINVAL;
+
+ val = readl(&res->capture_reg->l2isp.L2_SENSOR_CROP_VSIZE) & GENMASK(11, 0);
+ if (((param->sensor_crop_ofs_v / 2) + ((s16)val)) > 2047)
+ return -EINVAL;
+
+ /* set parameters related to L2ISP UNDIST */
+ if (param->through_mode == HWD_VIIF_ENABLE) {
+ /* Enable through mode */
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l2isp.L2_MODE);
+ } else {
+ val = (param->roi_mode[0] << 1U) | (param->roi_mode[1] << 3U);
+ writel(val, &res->capture_reg->l2isp.L2_MODE);
+ val = (u32)param->sensor_crop_ofs_h & GENMASK(13, 0);
+ writel(val, &res->capture_reg->l2isp.L2_SENSOR_CROP_OFS_H);
+ val = (u32)param->sensor_crop_ofs_v & GENMASK(12, 0);
+ writel(val, &res->capture_reg->l2isp.L2_SENSOR_CROP_OFS_V);
+ writel(param->norm_scale, &res->capture_reg->l2isp.L2_NORM_SCALE);
+ writel(param->valid_r_norm2_poly, &res->capture_reg->l2isp.L2_VALID_R_NORM2_POLY);
+ writel(param->valid_r_norm2_grid, &res->capture_reg->l2isp.L2_VALID_R_NORM2_GRID);
+ writel(param->roi_write_area_delta[0],
+ &res->capture_reg->l2isp.L2_ROI_WRITE_AREA_DELTA[0]);
+ writel(param->roi_write_area_delta[1],
+ &res->capture_reg->l2isp.L2_ROI_WRITE_AREA_DELTA[1]);
+
+ for (i = 0; i < HWD_VIIF_L2_UNDIST_POLY_NUM; i++) {
+ val = (u32)param->poly_write_g_coef[i];
+ writel(val, &res->capture_reg->l2isp.L2_POLY10_WRITE_G_COEF[i]);
+ val = (u32)param->poly_read_b_coef[i];
+ writel(val, &res->capture_reg->l2isp.L2_POLY10_READ_B_COEF[i]);
+ val = (u32)param->poly_read_g_coef[i];
+ writel(val, &res->capture_reg->l2isp.L2_POLY10_READ_G_COEF[i]);
+ val = (u32)param->poly_read_r_coef[i];
+ writel(val, &res->capture_reg->l2isp.L2_POLY10_READ_R_COEF[i]);
+ }
+ writel(param->grid_node_num_h, &res->capture_reg->l2isp.L2_GRID_NODE_NUM_H);
+ writel(param->grid_node_num_v, &res->capture_reg->l2isp.L2_GRID_NODE_NUM_V);
+ writel(param->grid_patch_hsize_inv,
+ &res->capture_reg->l2isp.L2_GRID_PATCH_HSIZE_INV);
+ writel(param->grid_patch_vsize_inv,
+ &res->capture_reg->l2isp.L2_GRID_PATCH_VSIZE_INV);
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_undist_table_transmission() -
+ * Configure L2ISP transferring grid table for undistortion.
+ *
+ * @write_g: grid table address for G-WRITE(physical address)
+ * @read_b: grid table address for B-READ(physical address)
+ * @read_g: grid table address for G-READ(physical address)
+ * @read_r: grid table address for R-READ(physical address)
+ * @size: of each table [1024..8192] [byte]
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "write_g", "read_b", "read_g" or "read_r" is not 4byte alignment
+ * - "size" is out of range
+ * - "size" is not 0 when all table addresses are 0
+ */
+s32 hwd_viif_l2_set_undist_table_transmission(struct hwd_viif_res *res, uintptr_t write_g,
+ uintptr_t read_b, uintptr_t read_g, uintptr_t read_r,
+ u32 size)
+{
+ u32 val = 0U;
+
+ if (((write_g % HWD_VIIF_L2_VDM_ALIGN) != 0U) || ((read_b % HWD_VIIF_L2_VDM_ALIGN) != 0U) ||
+ ((read_g % HWD_VIIF_L2_VDM_ALIGN) != 0U) || ((read_r % HWD_VIIF_L2_VDM_ALIGN) != 0U)) {
+ return -EINVAL;
+ }
+
+ if ((size != 0U && size < HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE) ||
+ size > HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE) {
+ return -EINVAL;
+ }
+
+ if ((size % 4U) != 0U)
+ return -EINVAL;
+
+ if (write_g == 0U && read_b == 0U && read_g == 0U && read_r == 0U && size != 0U)
+ return -EINVAL;
+
+ if ((write_g != 0U || read_b != 0U || read_g != 0U || read_r != 0U) && size == 0U)
+ return -EINVAL;
+
+ /* read_b: t_port[8], read_g: t_port[9], read_r: t_port[10], write_g: t_port[11] */
+ if (read_b != 0U) {
+ writel((u32)read_b, &res->capture_reg->vdm.t_port[8].VDM_T_STADR);
+ writel(size, &res->capture_reg->vdm.t_port[8].VDM_T_SIZE);
+ val |= BIT(8);
+ }
+ if (read_g != 0U) {
+ writel((u32)read_g, &res->capture_reg->vdm.t_port[9].VDM_T_STADR);
+ writel(size, &res->capture_reg->vdm.t_port[9].VDM_T_SIZE);
+ val |= BIT(9);
+ }
+ if (read_r != 0U) {
+ writel((u32)read_r, &res->capture_reg->vdm.t_port[10].VDM_T_STADR);
+ writel(size, &res->capture_reg->vdm.t_port[10].VDM_T_SIZE);
+ val |= BIT(10);
+ }
+ if (write_g != 0U) {
+ writel((u32)write_g, &res->capture_reg->vdm.t_port[11].VDM_T_STADR);
+ writel(size, &res->capture_reg->vdm.t_port[11].VDM_T_SIZE);
+ val |= BIT(11);
+ }
+
+ if (val != 0U) {
+ /*
+ * Set SRAM base address and size.
+ * t_group[1] is used only to transfer UNDIST table
+ */
+ writel(HWD_VIIF_VDM_CFG_PARAM, &res->capture_reg->vdm.t_group[1].VDM_T_CFG);
+ writel(HWD_VIIF_L2_VDM_GRID_SRAM_BASE,
+ &res->capture_reg->vdm.t_group[1].VDM_T_SRAM_BASE);
+ writel(HWD_VIIF_L2_VDM_GRID_SRAM_SIZE,
+ &res->capture_reg->vdm.t_group[1].VDM_T_SRAM_SIZE);
+ }
+
+ val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) & ~((u32)0xfU << 8U));
+ writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_roi_num_1() - Set ROI path condition when ROI num is 1
+ */
+static void hwd_viif_l2_set_roi_num_1(struct hwd_viif_res *res)
+{
+ struct hwd_viif_l2_roi_path_info *info = &res->l2_roi_path_info;
+ u32 val, x_min, x_max, y_min, y_max;
+ u32 i, x, y, w, h;
+
+ /* ROI0 is input to POST0 and POST1 */
+ if (info->post_enable_flag[0]) {
+ /* POST0 is enabled */
+ x_min = info->post_crop_x[0];
+ x_max = info->post_crop_x[0] + info->post_crop_w[0];
+ y_min = info->post_crop_y[0];
+ y_max = info->post_crop_y[0] + info->post_crop_h[0];
+ if (info->post_enable_flag[1]) {
+ /* POST1 is enabled */
+ x_min = min(x_min, info->post_crop_x[1]);
+ val = info->post_crop_x[1] + info->post_crop_w[1];
+ x_max = max(x_max, val);
+ y_min = min(y_min, info->post_crop_y[1]);
+ val = info->post_crop_y[1] + info->post_crop_h[1];
+ y_max = max(y_max, val);
+ }
+ x = x_min;
+ y = y_min;
+ w = x_max - x_min;
+ h = y_max - y_min;
+ } else if (info->post_enable_flag[1]) {
+ /* POST0 is disabled and POST1 is enabled */
+ x = info->post_crop_x[1];
+ w = info->post_crop_w[1];
+ y = info->post_crop_y[1];
+ h = info->post_crop_h[1];
+ } else {
+ /* All POSTs are disabled */
+ x = 0;
+ y = 0;
+ w = HWD_VIIF_CROP_MIN_W;
+ h = HWD_VIIF_CROP_MIN_H;
+ }
+ writel(x, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_OFS_H);
+ writel(y, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_OFS_V);
+ writel(w, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_HSIZE);
+ writel(h, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_VSIZE);
+
+ for (i = 0; i < HWD_VIIF_MAX_POST_NUM; i++) {
+ if (info->post_enable_flag[i])
+ writel(0, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
+ else
+ writel(HWD_VIIF_L2_ROI_NONE, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
+ }
+}
+
+/**
+ * hwd_viif_l2_set_roi_num_2() - Set ROI path condition when ROI num is 2
+ */
+static void hwd_viif_l2_set_roi_num_2(struct hwd_viif_res *res)
+{
+ struct hwd_viif_l2_roi_path_info *info = &res->l2_roi_path_info;
+ u32 i;
+
+ for (i = 0; i < HWD_VIIF_L2_ROI_MAX_NUM; i++) {
+ /* ROI-n is the same as CROP area of POST-n */
+ if (info->post_enable_flag[i]) {
+ writel(info->post_crop_x[i],
+ &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_H);
+ writel(info->post_crop_y[i],
+ &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_V);
+ writel(info->post_crop_w[i],
+ &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_HSIZE);
+ writel(info->post_crop_h[i],
+ &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_VSIZE);
+ writel(i, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
+ } else {
+ writel(0, &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_H);
+ writel(0, &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_V);
+ writel(HWD_VIIF_CROP_MIN_W,
+ &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_HSIZE);
+ writel(HWD_VIIF_CROP_MIN_H,
+ &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_VSIZE);
+ writel(HWD_VIIF_L2_ROI_NONE, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
+ }
+ }
+}
+
+/**
+ * hwd_viif_l2_set_roi_path() - Set ROI path condition
+ */
+static void hwd_viif_l2_set_roi_path(struct hwd_viif_res *res)
+{
+ if (res->l2_roi_path_info.roi_num == 1U)
+ hwd_viif_l2_set_roi_num_1(res);
+ else
+ hwd_viif_l2_set_roi_num_2(res);
+}
+
+/**
+ * hwd_viif_l2_set_roi() - Set ROI parameters of L2ISP
+ *
+ * @param: Pointer to ROI parameters of L2ISP
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "param" is NULL
+ * - [2] Member of "param" is invalid
+ *
+ * see also: #hwd_viif_l2_set_roi_path
+ */
+s32 hwd_viif_l2_set_roi(struct hwd_viif_res *res, const struct viif_l2_roi_config *param)
+{
+ u32 val;
+ int i;
+
+ if (!param)
+ return -EINVAL;
+
+ if (param->roi_num < 1 || param->roi_num > 2)
+ return -EINVAL;
+
+ for (i = 0; i < 2; i++) {
+ if (param->roi_scale[i] < HWD_VIIF_L2_ROI_MIN_SCALE ||
+ param->roi_scale[i] > HWD_VIIF_L2_ROI_MAX_SCALE ||
+ param->roi_scale_inv[i] < HWD_VIIF_L2_ROI_MIN_SCALE_INV ||
+ param->roi_scale_inv[i] > HWD_VIIF_L2_ROI_MAX_SCALE_INV ||
+ param->corrected_wo_scale_hsize[i] <
+ HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE ||
+ param->corrected_wo_scale_hsize[i] >
+ HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE ||
+ param->corrected_wo_scale_vsize[i] <
+ HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE ||
+ param->corrected_wo_scale_vsize[i] >
+ HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE ||
+ param->corrected_hsize[i] < HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE ||
+ param->corrected_hsize[i] > HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE ||
+ param->corrected_vsize[i] < HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE ||
+ param->corrected_vsize[i] > HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE) {
+ return -EINVAL;
+ }
+ }
+
+ /* Set the number of ROI and update resource info with roi_num */
+ writel(param->roi_num, &res->capture_reg->l2isp.L2_ROI_NUM);
+ res->l2_roi_path_info.roi_num = param->roi_num;
+
+ /* Update ROI area and input to each POST */
+ hwd_viif_l2_set_roi_path(res);
+
+ /* Set the remaining parameters */
+ for (i = 0; i < 2; i++) {
+ writel(param->roi_scale[i], &res->capture_reg->l2isp.roi[i].L2_ROI_SCALE);
+ writel(param->roi_scale_inv[i], &res->capture_reg->l2isp.roi[i].L2_ROI_SCALE_INV);
+ val = (param->corrected_wo_scale_hsize[i] << 13U) | param->corrected_hsize[i];
+ writel(val, &res->capture_reg->l2isp.roi[i].L2_ROI_CORRECTED_HSIZE);
+ val = (param->corrected_wo_scale_vsize[i] << 12U) | param->corrected_vsize[i];
+ writel(val, &res->capture_reg->l2isp.roi[i].L2_ROI_CORRECTED_VSIZE);
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_gamma() - Set Gamma correction parameters of L2ISP
+ *
+ * @post_id: POST ID [0..1]
+ * @enable: or disable gamma correction of L2ISP. For more refer @ref hwd_viif_enable_flag.
+ * @vsplit: changing line position from 1st table to 2nd table [0..4094]
+ * @mode: Gamma correction mode. For more refer @ref hwd_viif_gamma_table_mode.
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "post_id", "enable", "vsplit" or "mode" is out of range
+ * - [2] "vsplit" is not 0 when "enable" is HWD_VIIF_DISABLE
+ * - [3] "mode" is not HWD_VIIF_GAMMA_COMPRESSED when enable is HWD_VIIF_DISABLE
+ *
+ * see also: #hwd_viif_l2_set_gamma
+ */
+s32 hwd_viif_l2_set_gamma(struct hwd_viif_res *res, u32 post_id, u32 enable, u32 vsplit, u32 mode)
+{
+ u32 val;
+
+ if (post_id >= HWD_VIIF_MAX_POST_NUM ||
+ (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE) ||
+ vsplit > HWD_VIIF_GAMMA_MAX_VSPLIT ||
+ (mode != HWD_VIIF_GAMMA_COMPRESSED && mode != HWD_VIIF_GAMMA_LINEAR) ||
+ (enable == HWD_VIIF_DISABLE && vsplit != 0x0U) ||
+ (enable == HWD_VIIF_DISABLE && mode != HWD_VIIF_GAMMA_COMPRESSED)) {
+ return -EINVAL;
+ }
+
+ /* Set gamma parameters of L2ISP */
+ val = (vsplit << 16U) | (mode << 4U) | enable;
+ writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_GAMMA_M);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_gamma_table_transmission() - Configure L2ISP transferring gamma table.
+ *
+ * @post_id: POST ID [0..1]
+ * @gamma_table: Pointer to gamma table information
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "post_id" is out of range
+ * - [2] Member of "gamma_table" is invalid
+ */
+s32 hwd_viif_l2_set_gamma_table_transmission(struct hwd_viif_res *res, u32 post_id,
+ const struct hwd_viif_l2_gamma_table *gamma_table)
+{
+ u32 vdm_enable = 0U;
+ u32 i, base_addr;
+
+ if (post_id >= HWD_VIIF_MAX_POST_NUM)
+ return -EINVAL;
+
+ for (i = 0; i < 6U; i++) {
+ if ((gamma_table->table[i] % HWD_VIIF_L2_VDM_ALIGN) != 0U)
+ return -EINVAL;
+ }
+
+ /* table[0]: LUT0-G/Y: t_port[12 + post_id * 6] */
+ /* table[1]: LUT1-G/Y: t_port[13 + post_id * 6] */
+ /* table[2]: LUT0-B/U: t_port[14 + post_id * 6] */
+ /* table[3]: LUT1-B/U: t_port[15 + post_id * 6] */
+ /* table[4]: LUT0-R/V: t_port[16 + post_id * 6] */
+ /* table[5]: LUT1-R/V: t_port[17 + post_id * 6] */
+ for (i = 0; i < 6U; i++) {
+ if (gamma_table->table[i] != 0U) {
+ int idx = 12U + i + post_id * 6U;
+
+ writel((u32)gamma_table->table[i],
+ &res->capture_reg->vdm.t_port[idx].VDM_T_STADR);
+ writel(HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE,
+ &res->capture_reg->vdm.t_port[idx].VDM_T_SIZE);
+ vdm_enable |= BIT(i);
+ }
+ }
+ if (vdm_enable != 0U) {
+ /* t_group[2..3] is used only to transfer GAMMA table */
+ /* [2]: POST0, [3]: POST1 */
+ writel(HWD_VIIF_VDM_CFG_PARAM,
+ &res->capture_reg->vdm.t_group[(post_id + 2U)].VDM_T_CFG);
+ base_addr = HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE +
+ (HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE * post_id);
+ writel(base_addr, &res->capture_reg->vdm.t_group[(post_id + 2U)].VDM_T_SRAM_BASE);
+ writel(HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE,
+ &res->capture_reg->vdm.t_group[(post_id + 2U)].VDM_T_SRAM_SIZE);
+ vdm_enable = vdm_enable << (12U + (post_id * 6U));
+ }
+ vdm_enable |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) &
+ ~((u32)0x3fU << (12U + (post_id * 6U))));
+ writel(vdm_enable, &res->capture_reg->vdm.VDM_T_ENABLE);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_output_csc() - Set output CSC parameters of L2ISP
+ *
+ * @post_id: POST ID [0..1]
+ * @param: Pointer to output csc parameters of L2ISP
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "post_id" is out of range
+ * - [2] Member of "param" is invalid
+ */
+s32 hwd_viif_l2_set_output_csc(struct hwd_viif_res *res, u32 post_id,
+ const struct hwd_viif_csc_param *param)
+{
+ struct hwd_viif_l2isp_post_reg *reg_l2isp_post;
+ u32 i, val;
+
+ if (post_id >= HWD_VIIF_MAX_POST_NUM)
+ return -EINVAL;
+
+ /* disable csc matrix when param is NULL */
+ if (!param) {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l2isp.post[post_id].csc.MTB);
+ return 0;
+ }
+
+ /* param is specified: go further check */
+ if (param->r_cr_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->g_y_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->b_cb_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->r_cr_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->g_y_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
+ param->b_cb_out_offset > HWD_VIIF_CSC_MAX_OFFSET) {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < HWD_VIIF_CSC_MAX_COEF_NUM; i++) {
+ if (param->coef[i] > HWD_VIIF_CSC_MAX_COEF_VALUE)
+ return -EINVAL;
+ }
+
+ reg_l2isp_post = &res->capture_reg->l2isp.post[post_id];
+
+ writel(param->g_y_in_offset, ®_l2isp_post->csc.MTB_YG_OFFSETI);
+ writel(param->coef[0], ®_l2isp_post->csc.MTB_YG1);
+ val = (param->coef[1] << HWD_VIIF_MTB_CB_YG_COEF_OFFSET) |
+ (param->coef[2] << HWD_VIIF_MTB_CR_YG_COEF_OFFSET);
+ writel(val, ®_l2isp_post->csc.MTB_YG2);
+ writel(param->g_y_out_offset, ®_l2isp_post->csc.MTB_YG_OFFSETO);
+ writel(param->b_cb_in_offset, ®_l2isp_post->csc.MTB_CB_OFFSETI);
+ writel(param->coef[3], ®_l2isp_post->csc.MTB_CB1);
+ val = (param->coef[4] << HWD_VIIF_MTB_CB_CB_COEF_OFFSET) |
+ (param->coef[5] << HWD_VIIF_MTB_CR_CB_COEF_OFFSET);
+ writel(val, ®_l2isp_post->csc.MTB_CB2);
+ writel(param->b_cb_out_offset, ®_l2isp_post->csc.MTB_CB_OFFSETO);
+ writel(param->r_cr_in_offset, ®_l2isp_post->csc.MTB_CR_OFFSETI);
+ writel(param->coef[6], ®_l2isp_post->csc.MTB_CR1);
+ val = (param->coef[7] << HWD_VIIF_MTB_CB_CR_COEF_OFFSET) |
+ (param->coef[8] << HWD_VIIF_MTB_CR_CR_COEF_OFFSET);
+ writel(val, ®_l2isp_post->csc.MTB_CR2);
+ writel(param->r_cr_out_offset, ®_l2isp_post->csc.MTB_CR_OFFSETO);
+ writel(HWD_VIIF_ENABLE, ®_l2isp_post->csc.MTB);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l2_set_img_transmission() - Set image transfer condition of L2ISP
+ *
+ * @post_id: POST ID [0..1]
+ * @enable: or disable image transfer of MAIN unit. For more refer @ref hwd_viif_enable_flag.
+ * @src: Pointer to crop area information
+ * @out_process: Pointer to output process information
+ * @img: Pointer to output image information
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "post_id" or "enable" is out of range
+ * - [2] "src" or "out_process" is NULL when "enable" is HWD_VIIF_ENABLE
+ * - [3] "src" or "out_process" is not NULL when "enable" is HWD_VIIF_DISABLE
+ * - [4] Member of "src" is out of range
+ * - [5] "w" of "src" is not equal to 2 * "width" of "image"
+ * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
+ * - [6] "h" of "src" is not equal to 2 * "height" of "image"
+ * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
+ * - [7] "w" of "src" is not equal to "width" of "image"
+ * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
+ * - [8] "h" of "src" is not equal to "height" of "image"
+ * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
+ * - [9] Member of "out_process" is invalid
+ * - [10] "alpha" of "out_process" is not 0 when "format" of "img" is not HWD_VIIF_ARGB8888_PACKED
+ * - [11] "format" of "img" is not HWD_VIIF_ONE_COLOR_8 or HWD_VIIF_ONE_COLOR_16
+ * when "select_color" of "out_process"
+ * is HWD_VIIF_COLOR_Y_G, HWD_VIIF_COLOR_U_B or HWD_VIIF_COLOR_V_R
+ * - [12] Member of "img" is invalid
+ *
+ * see also: #hwd_viif_l2_set_roi_path
+ */
+s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id, u32 enable,
+ const struct hwd_viif_img_area *src,
+ const struct hwd_viif_out_process *out_process,
+ const struct hwd_viif_img *img)
+{
+ u32 pitch[HWD_VIIF_MAX_PLANE_NUM], img_start_addr[HWD_VIIF_MAX_PLANE_NUM];
+ u32 i, val, loop, k, r[HWD_VIIF_MAX_PLANE_NUM];
+ s32 ret = 0;
+
+ /* pitch alignment for planar or one color format */
+ u32 pitch_align = 128U;
+
+ if (post_id >= HWD_VIIF_MAX_POST_NUM ||
+ (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE) ||
+ (enable == HWD_VIIF_ENABLE && (!src || !out_process)) ||
+ (enable == HWD_VIIF_DISABLE && (src || out_process))) {
+ return -EINVAL;
+ }
+
+ /* DISABLE: no DMA transmission setup, set minimum crop rectangle */
+ if (enable == HWD_VIIF_DISABLE) {
+ res->l2_roi_path_info.post_enable_flag[post_id] = false;
+ res->l2_roi_path_info.post_crop_x[post_id] = 0U;
+ res->l2_roi_path_info.post_crop_y[post_id] = 0U;
+ res->l2_roi_path_info.post_crop_w[post_id] = HWD_VIIF_CROP_MIN_W;
+ res->l2_roi_path_info.post_crop_h[post_id] = HWD_VIIF_CROP_MIN_H;
+ hwd_viif_l2_set_roi_path(res);
+
+ return 0;
+ }
+
+ /* further parameter check for ENABLE */
+ if (out_process->half_scale != HWD_VIIF_ENABLE &&
+ out_process->half_scale != HWD_VIIF_DISABLE) {
+ return -EINVAL;
+ }
+
+ if (out_process->select_color != HWD_VIIF_COLOR_Y_G &&
+ out_process->select_color != HWD_VIIF_COLOR_U_B &&
+ out_process->select_color != HWD_VIIF_COLOR_V_R &&
+ out_process->select_color != HWD_VIIF_COLOR_YUV_RGB) {
+ return -EINVAL;
+ }
+
+ if (img->format != HWD_VIIF_ARGB8888_PACKED && out_process->alpha != 0U)
+ return -EINVAL;
+
+ if (((img->width % 2U) != 0U) || ((img->height % 2U) != 0U) ||
+ img->width < HWD_VIIF_MIN_OUTPUT_IMG_WIDTH ||
+ img->height < HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT ||
+ img->width > HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP ||
+ img->height > HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP) {
+ return -EINVAL;
+ }
+
+ if (src->x > HWD_VIIF_CROP_MAX_X_ISP || src->y > HWD_VIIF_CROP_MAX_Y_ISP ||
+ src->w < HWD_VIIF_CROP_MIN_W || src->w > HWD_VIIF_CROP_MAX_W_ISP ||
+ src->h < HWD_VIIF_CROP_MIN_H || src->h > HWD_VIIF_CROP_MAX_H_ISP) {
+ return -EINVAL;
+ }
+
+ if (out_process->half_scale == HWD_VIIF_ENABLE) {
+ if ((src->w != (img->width * 2U)) || (src->h != (img->height * 2U)))
+ return -EINVAL;
+ } else {
+ if (src->w != img->width || src->h != img->height)
+ return -EINVAL;
+ }
+
+ if (out_process->select_color == HWD_VIIF_COLOR_Y_G ||
+ out_process->select_color == HWD_VIIF_COLOR_U_B ||
+ out_process->select_color == HWD_VIIF_COLOR_V_R) {
+ if (img->format != HWD_VIIF_ONE_COLOR_8 && img->format != HWD_VIIF_ONE_COLOR_16)
+ return -EINVAL;
+ }
+
+ /* build DMAC parameter */
+ switch (img->format) {
+ case HWD_VIIF_YCBCR422_8_PACKED:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ loop = 1U;
+ k = 2U;
+ r[0] = 1U;
+ pitch_align = 256U;
+ break;
+ case HWD_VIIF_RGB888_PACKED:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ loop = 1U;
+ k = 3U;
+ r[0] = 1U;
+ pitch_align = 384U;
+ break;
+ case HWD_VIIF_ARGB8888_PACKED:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ loop = 1U;
+ k = 4U;
+ r[0] = 1U;
+ pitch_align = 512U;
+ break;
+ case HWD_VIIF_ONE_COLOR_8:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ loop = 1U;
+ k = 1U;
+ r[0] = 1U;
+ break;
+ case HWD_VIIF_ONE_COLOR_16:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ loop = 1U;
+ k = 2U;
+ r[0] = 1U;
+ break;
+ case HWD_VIIF_YCBCR422_8_PLANAR:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
+ img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ pitch[1] = img->pixelmap[1].pitch;
+ pitch[2] = img->pixelmap[2].pitch;
+ loop = HWD_VIIF_MAX_PLANE_NUM;
+ k = 1U;
+ r[0] = 1U;
+ r[1] = 2U;
+ r[2] = 2U;
+ break;
+ case HWD_VIIF_RGB888_YCBCR444_8_PLANAR:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
+ img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ pitch[1] = img->pixelmap[1].pitch;
+ pitch[2] = img->pixelmap[2].pitch;
+ loop = HWD_VIIF_MAX_PLANE_NUM;
+ k = 1U;
+ r[0] = 1U;
+ r[1] = 1U;
+ r[2] = 1U;
+ break;
+ case HWD_VIIF_YCBCR422_16_PLANAR:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
+ img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ pitch[1] = img->pixelmap[1].pitch;
+ pitch[2] = img->pixelmap[2].pitch;
+ loop = HWD_VIIF_MAX_PLANE_NUM;
+ k = 2U;
+ r[0] = 1U;
+ r[1] = 2U;
+ r[2] = 2U;
+ break;
+ case HWD_VIIF_RGB161616_YCBCR444_16_PLANAR:
+ img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
+ img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
+ img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
+ pitch[0] = img->pixelmap[0].pitch;
+ pitch[1] = img->pixelmap[1].pitch;
+ pitch[2] = img->pixelmap[2].pitch;
+ loop = HWD_VIIF_MAX_PLANE_NUM;
+ k = 2U;
+ r[0] = 1U;
+ r[1] = 1U;
+ r[2] = 1U;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = 0; i < loop; i++) {
+ val = max(((img->width * k) / r[i]), 128U);
+ if (pitch[i] < val || pitch[i] > HWD_VIIF_MAX_PITCH_ISP ||
+ ((pitch[i] % pitch_align) != 0U) || ((img_start_addr[i] % 4U) != 0U)) {
+ return -EINVAL;
+ }
+ }
+
+ writel(img_start_addr[0], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_G);
+ writel(pitch[0], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_G);
+ if (loop == HWD_VIIF_MAX_PLANE_NUM) {
+ writel(img_start_addr[1],
+ &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_B);
+ writel(img_start_addr[2],
+ &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_R);
+ writel(pitch[1], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_B);
+ writel(pitch[2], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_R);
+ }
+
+ /* Set CROP */
+ val = (src->y << 16U) | src->x;
+ writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_OFFSET);
+ val = (src->h << 16U) | src->w;
+ writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_SIZE);
+
+ /* Set output process */
+ writel(out_process->half_scale,
+ &res->capture_reg->l2isp.post[post_id].L2_POST_HALF_SCALE_EN);
+ writel(out_process->select_color, &res->capture_reg->l2isp.post[post_id].L2_POST_C_SELECT);
+ writel((u32)out_process->alpha, &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTALP);
+ writel(img->format, &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTFMT);
+
+ /* Update ROI area and input to each POST */
+ res->l2_roi_path_info.post_enable_flag[post_id] = true;
+ res->l2_roi_path_info.post_crop_x[post_id] = src->x;
+ res->l2_roi_path_info.post_crop_y[post_id] = src->y;
+ res->l2_roi_path_info.post_crop_w[post_id] = src->w;
+ res->l2_roi_path_info.post_crop_h[post_id] = src->h;
+ hwd_viif_l2_set_roi_path(res);
+
+ return ret;
+}
+
+/**
+ * hwd_viif_l2_set_irq_mask() - Set mask condition for L2ISP
+ *
+ * @mask: L2ISP mask condition
+ * Return: None
+ */
+void hwd_viif_l2_set_irq_mask(struct hwd_viif_res *res, u32 mask)
+{
+ writel(mask, &res->capture_reg->l2isp.L2_CRGBF_ISP_INT_MASK);
+}
+
+/**
+ * hwd_viif_csi2rx_err_irq_handler() - CSI-2 RX error interruption handler
+ *
+ * Return: event information of CSI-2 RX error interruption
+ */
+u32 hwd_viif_csi2rx_err_irq_handler(struct hwd_viif_res *res)
+{
+ return readl(&res->csi2host_reg->CSI2RX_INT_ST_MAIN);
+}
+
+/**
+ * hwd_viif_status_err_irq_handler() - STATUS error interruption handler
+ *
+ * @event_main: information of STATUS error interruption of MAIN unit
+ * @event_sub: information of STATUS error interruption of SUB unit(CH0 and CH1)
+ * Return: None
+ */
+void hwd_viif_status_err_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub)
+{
+ u32 val, mask;
+
+ *event_main = HWD_VIIF_NO_EVENT;
+ *event_sub = HWD_VIIF_NO_EVENT;
+
+ val = readl(&res->capture_reg->sys.INT_M_STATUS);
+ mask = readl(&res->capture_reg->sys.INT_M_MASK);
+ val = val & ~mask;
+ if (val != HWD_VIIF_NO_EVENT) {
+ writel(val, &res->capture_reg->sys.INT_M_STATUS);
+ *event_main = val;
+ }
+
+ val = readl(&res->capture_reg->sys.INT_S_STATUS);
+ mask = readl(&res->capture_reg->sys.INT_S_MASK);
+ val = val & ~mask;
+ if (val != HWD_VIIF_NO_EVENT) {
+ writel(val, &res->capture_reg->sys.INT_S_STATUS);
+ *event_sub = val;
+ }
+}
+
+/**
+ * hwd_viif_vsync_irq_handler() - Vsync interruption handler
+ *
+ * @event_main: information of Vsync interruption of MAIN unit
+ * @event_sub: information of Vsync interruption of SUB unit(CH0 and CH1)
+ * Return: None
+ */
+void hwd_viif_vsync_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub)
+{
+ u32 val, mask;
+
+ *event_main = HWD_VIIF_NO_EVENT;
+ *event_sub = HWD_VIIF_NO_EVENT;
+
+ val = readl(&res->capture_reg->sys.INT_M_SYNC);
+ mask = readl(&res->capture_reg->sys.INT_M_SYNC_MASK);
+ val = val & ~mask;
+ if (val != HWD_VIIF_NO_EVENT) {
+ writel(val, &res->capture_reg->sys.INT_M_SYNC);
+ *event_main = val;
+ }
+
+ val = readl(&res->capture_reg->sys.INT_S_SYNC);
+ mask = readl(&res->capture_reg->sys.INT_S_SYNC_MASK);
+ val = val & ~mask;
+ if (val != HWD_VIIF_NO_EVENT) {
+ writel(val, &res->capture_reg->sys.INT_S_SYNC);
+ *event_sub = val;
+ }
+}
+
+/**
+ * hwd_viif_isp_regbuf_irq_handler() - ISP register buffer interruption handler
+ *
+ * @event_l1: information of register buffer interruption of L1ISP
+ * @event_l2: information of register buffer interruption of L2ISP
+ * Return: None
+ */
+void hwd_viif_isp_regbuf_irq_handler(struct hwd_viif_res *res, u32 *event_l1, u32 *event_l2)
+{
+ u32 val;
+
+ *event_l1 = HWD_VIIF_NO_EVENT;
+ *event_l2 = HWD_VIIF_NO_EVENT;
+
+ val = readl(&res->capture_reg->l1isp.L1_CRGBF_INT_MASKED_STAT);
+ if (val != HWD_VIIF_NO_EVENT) {
+ *event_l1 = val;
+ writel(val, &res->capture_reg->l1isp.L1_CRGBF_INT_STAT);
+ }
+
+ val = readl(&res->capture_reg->l2isp.L2_CRGBF_INT_MASKED_STAT);
+ if (val != HWD_VIIF_NO_EVENT) {
+ *event_l2 = val;
+ writel(val, &res->capture_reg->l2isp.L2_CRGBF_INT_STAT);
+ }
+}
diff --git a/drivers/media/platform/visconti/hwd_viif.h b/drivers/media/platform/visconti/hwd_viif.h
new file mode 100644
index 00000000000..100afda8436
--- /dev/null
+++ b/drivers/media/platform/visconti/hwd_viif.h
@@ -0,0 +1,710 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#ifndef HWD_VIIF_H
+#define HWD_VIIF_H
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+#include <linux/visconti_viif.h>
+
+enum hwd_power_ctrl {
+ HWD_POWER_OFF = 0, /**< Power off */
+ HWD_POWER_ON /**< Power on */
+};
+
+/* MIPI CSI2 Data Types */
+#define VISCONTI_CSI2_DT_YUV4228B 0x1E
+#define VISCONTI_CSI2_DT_YUV42210B 0x1F
+#define VISCONTI_CSI2_DT_RGB565 0x22
+#define VISCONTI_CSI2_DT_RGB888 0x24
+#define VISCONTI_CSI2_DT_RAW8 0x2A
+#define VISCONTI_CSI2_DT_RAW10 0x2B
+#define VISCONTI_CSI2_DT_RAW12 0x2C
+#define VISCONTI_CSI2_DT_RAW14 0x2D
+
+/* hwd_viif_enable_flag */
+#define HWD_VIIF_DISABLE (0U)
+#define HWD_VIIF_ENABLE (1U)
+
+/* hwd_viif_memory_sync_type */
+#define HWD_VIIF_MEM_SYNC_INTERNAL (0U)
+#define HWD_VIIF_MEM_SYNC_CSI2 (1U)
+
+/* hwd_viif_color_format */
+#define HWD_VIIF_YCBCR422_8_PACKED (0U)
+#define HWD_VIIF_RGB888_PACKED (1U)
+#define HWD_VIIF_ARGB8888_PACKED (3U)
+#define HWD_VIIF_YCBCR422_8_PLANAR (8U)
+#define HWD_VIIF_RGB888_YCBCR444_8_PLANAR (9U)
+#define HWD_VIIF_ONE_COLOR_8 (11U)
+#define HWD_VIIF_YCBCR422_16_PLANAR (12U)
+#define HWD_VIIF_RGB161616_YCBCR444_16_PLANAR (13U)
+#define HWD_VIIF_ONE_COLOR_16 (15U)
+
+/* hwd_viif_raw_pack_mode */
+#define HWD_VIIF_RAWPACK_DISABLE (0U)
+#define HWD_VIIF_RAWPACK_MSBFIRST (2U)
+#define HWD_VIIF_RAWPACK_LSBFIRST (3U)
+
+/* hwd_viif_yuv_conversion_mode */
+#define HWD_VIIF_YUV_CONV_REPEAT (0U)
+#define HWD_VIIF_YUV_CONV_INTERPOLATION (1U)
+
+/* hwd_viif_gamma_table_mode */
+#define HWD_VIIF_GAMMA_COMPRESSED (0U)
+#define HWD_VIIF_GAMMA_LINEAR (1U)
+
+/* hwd_viif_output_color_mode */
+#define HWD_VIIF_COLOR_Y_G (0U)
+#define HWD_VIIF_COLOR_U_B (1U)
+#define HWD_VIIF_COLOR_V_R (2U)
+#define HWD_VIIF_COLOR_YUV_RGB (4U)
+
+/* hwd_viif_hw_params */
+#define HWD_VIIF_MAX_CH (6U)
+#define HWD_VIIF_MAX_PLANE_NUM (3U)
+
+/**
+ * enum hwd_viif_csi2_dphy - D-PHY Lane assignment
+ *
+ * specifies which line(L0-L3) is assigned to D0-D3
+ */
+enum hwd_viif_csi2_dphy {
+ HWD_VIIF_CSI2_DPHY_L0L1L2L3 = 0U,
+ HWD_VIIF_CSI2_DPHY_L0L3L1L2 = 1U,
+ HWD_VIIF_CSI2_DPHY_L0L2L3L1 = 2U,
+ HWD_VIIF_CSI2_DPHY_L0L1L3L2 = 4U,
+ HWD_VIIF_CSI2_DPHY_L0L3L2L1 = 5U,
+ HWD_VIIF_CSI2_DPHY_L0L2L1L3 = 6U
+};
+
+/* hwd_viif_csi2rx_cal_status */
+#define HWD_VIIF_CSI2_CAL_NOT_DONE (0U)
+#define HWD_VIIF_CSI2_CAL_SUCCESS (1U)
+#define HWD_VIIF_CSI2_CAL_FAIL (2U)
+
+/* hwd_viif_csi2rx_not_capture */
+#define HWD_VIIF_CSI2_NOT_CAPTURE (-1) /**< csi2 not capture */
+
+/* hwd_viif_l1_input_mode */
+#define HWD_VIIF_L1_INPUT_HDR (0U)
+#define HWD_VIIF_L1_INPUT_PWL (1U)
+#define HWD_VIIF_L1_INPUT_SDR (2U)
+#define HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT (3U)
+#define HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT (4U)
+
+/* hwd_viif_l1_raw_color_filter_mode */
+#define HWD_VIIF_L1_RAW_GR_R_B_GB (0U)
+#define HWD_VIIF_L1_RAW_R_GR_GB_B (1U)
+#define HWD_VIIF_L1_RAW_B_GB_GR_R (2U)
+#define HWD_VIIF_L1_RAW_GB_B_R_GR (3U)
+
+/* hwd_viif_l1_input_interpolation_mode */
+#define HWD_VIIF_L1_INPUT_INTERPOLATION_LINE (0U)
+#define HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL (1U)
+
+/* hwd_viif_l1_img_sens */
+#define HWD_VIIF_L1_IMG_SENSITIVITY_HIGH (0U)
+#define HWD_VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED (1U)
+#define HWD_VIIF_L1_IMG_SENSITIVITY_LOW (2U)
+
+/* hwd_viif_l1_dpc */
+#define HWD_VIIF_L1_DPC_1PIXEL (0U)
+#define HWD_VIIF_L1_DPC_2PIXEL (1U)
+
+/* hwd_viif_l1_rcnr_hry_type */
+#define HWD_VIIF_L1_RCNR_LOW_RESOLUTION (0U)
+#define HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION (1U)
+#define HWD_VIIF_L1_RCNR_HIGH_RESOLUTION (2U)
+#define HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION (3U)
+
+/* hwd_viif_l1_rcnr_msf_blend_ratio */
+#define HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 (0U)
+#define HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 (1U)
+#define HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 (2U)
+
+/* hwd_viif_l1_hdrs */
+#define HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE (0U)
+#define HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE (1U)
+
+/* hwd_viif_l1_lsc_para_mag */
+#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH (0U)
+#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH (1U)
+#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND (2U)
+#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST (3U)
+
+/* hwd_viif_l1_lsc_grid_mag */
+#define HWD_VIIF_L1_GRID_COEF_GAIN_X1 (0U)
+#define HWD_VIIF_L1_GRID_COEF_GAIN_X2 (1U)
+
+/* hwd_viif_l1_demosaic */
+#define HWD_VIIF_L1_DEMOSAIC_ACPI (0U)
+#define HWD_VIIF_L1_DEMOSAIC_DMG (1U)
+
+/* hwd_viif_l1_awb_restart_cond */
+/* macros for L1ISP condition to restart auto white balance */
+#define HWD_VIIF_L1_AWB_RESTART_NO (0U)
+#define HWD_VIIF_L1_AWB_RESTART_128FRAME (1U)
+#define HWD_VIIF_L1_AWB_RESTART_64FRAME (2U)
+#define HWD_VIIF_L1_AWB_RESTART_32FRAME (3U)
+#define HWD_VIIF_L1_AWB_RESTART_16FRAME (4U)
+#define HWD_VIIF_L1_AWB_RESTART_8FRAME (5U)
+#define HWD_VIIF_L1_AWB_RESTART_4FRAME (6U)
+#define HWD_VIIF_L1_AWB_RESTART_2FRAME (7U)
+
+/* hwd_viif_l1_awb_mag */
+#define HWD_VIIF_L1_AWB_ONE_SECOND (0U)
+#define HWD_VIIF_L1_AWB_X1 (1U)
+#define HWD_VIIF_L1_AWB_X2 (2U)
+#define HWD_VIIF_L1_AWB_X4 (3U)
+
+/* hwd_viif_l1_awb_area_mode */
+#define HWD_VIIF_L1_AWB_AREA_MODE0 (0U)
+#define HWD_VIIF_L1_AWB_AREA_MODE1 (1U)
+#define HWD_VIIF_L1_AWB_AREA_MODE2 (2U)
+#define HWD_VIIF_L1_AWB_AREA_MODE3 (3U)
+
+/* hwd_viif_l1_hdrc_tone_type */
+#define HWD_VIIF_L1_HDRC_TONE_USER (0U)
+#define HWD_VIIF_L1_HDRC_TONE_PRESET (1U)
+
+/* hwd_viif_l1_bin_mode */
+#define HWD_VIIF_L1_HIST_BIN_MODE_LINEAR (0U)
+#define HWD_VIIF_L1_HIST_BIN_MODE_LOG (1U)
+
+/* hwd_viif_l2_undist_mode */
+#define HWD_VIIF_L2_UNDIST_POLY (0U)
+#define HWD_VIIF_L2_UNDIST_GRID (1U)
+#define HWD_VIIF_L2_UNDIST_POLY_TO_GRID (2U)
+#define HWD_VIIF_L2_UNDIST_GRID_TO_POLY (3U)
+
+/**
+ * struct hwd_viif_csi2rx_line_err_target
+ *
+ * Virtual Channel and Data Type pair for CSI2RX line error monitor
+ *
+ * When 0 is set to dt, line error detection is disabled.
+ *
+ * * VC can be 0 .. 3
+ * * DT can be 0 or 0x10 .. 0x3F
+ */
+#define VISCONTI_CSI2_ERROR_MONITORS_NUM 8
+struct hwd_viif_csi2rx_line_err_target {
+ u32 vc[VISCONTI_CSI2_ERROR_MONITORS_NUM];
+ u32 dt[VISCONTI_CSI2_ERROR_MONITORS_NUM];
+};
+
+/**
+ * struct hwd_viif_csi2rx_irq_mask
+ * @mask: mask setting for CSI2RX error interruption
+ *
+ * * mask[0]: D-PHY fatal error
+ * * mask[1]: Packet fatal error
+ * * mask[2]: Frame fatal error
+ * * mask[3]: D-PHY error
+ * * mask[4]: Packet error
+ * * mask[5]: Line error
+ */
+#define VISCONTI_CSI2RX_IRQ_MASKS_NUM 6
+#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_FATAL 0
+#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_FATAL 1
+#define VISCONTI_CSI2RX_IRQ_MASK_FRAME_FATAL 2
+#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_ERROR 3
+#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_ERROR 4
+#define VISCONTI_CSI2RX_IRQ_MASK_LINE_ERROR 5
+struct hwd_viif_csi2rx_irq_mask {
+ u32 mask[VISCONTI_CSI2RX_IRQ_MASKS_NUM];
+};
+
+/**
+ * struct hwd_viif_csi2rx_packet - CSI2 packet information
+ * @word_count: word count included in one packet[byte] [0..16384]
+ * @packet_num: the number of packet included in one packet [0..8192]
+ *
+ * each element means as below.
+ * * [0]: embedded data of MAIN unit
+ * * [1]: long packet data of MAIN unit
+ * * [2]: embedded data of SUB unit
+ * * [3]: long packet data of SUB unit
+ *
+ * Regarding word_count of long packet data,
+ * word count of odd line needs to be set in case of DT = 0x18, 0x19, 0x1C or 0x1D.
+ */
+#define VISCONTI_CSI2RX_PACKET_TYPES_NUM 4
+#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN 0
+#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN 1
+#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB 2
+#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB 3
+struct hwd_viif_csi2rx_packet {
+ u32 word_count[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
+ u32 packet_num[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
+};
+
+/**
+ * struct hwd_viif_pixelmap - pixelmap information
+ * @pmap_paddr: start address of pixel data(physical address). 4byte alignment.
+ * @pitch: pitch size of pixel map[byte]
+ *
+ * Condition of pitch in case of L2ISP output is as below.
+ * * max: 32704[byte]
+ * * min: the larger value of (active width of image * k / r) and 128[byte]
+ * * alignment: 64[byte]
+ *
+ * Condition of pitch in the other cases is as below.
+ * * max: 65536[byte]
+ * * min: active width of image * k / r[byte]
+ * * alignment: 4[byte]
+ *
+ * k is the size of 1 pixel and the value is as below.
+ * * HWD_VIIF_YCBCR422_8_PACKED: 2
+ * * HWD_VIIF_RGB888_PACKED: 3
+ * * HWD_VIIF_ARGB8888_PACKED: 4
+ * * HWD_VIIF_YCBCR422_8_PLANAR: 1
+ * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR: 1
+ * * HWD_VIIF_ONE_COLOR_8: 1
+ * * HWD_VIIF_YCBCR422_16_PLANAR: 2
+ * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR: 2
+ * * HWD_VIIF_ONE_COLOR_16: 2
+ *
+ * r is the correction factor for Cb or Cr of YCbCr422 planar and the value is as below.
+ * * YCbCr422 Cb-planar: 2
+ * * YCbCr422 Cr-planar: 2
+ * * others: 1
+ *
+ */
+struct hwd_viif_pixelmap {
+ uintptr_t pmap_paddr;
+ u32 pitch;
+};
+
+/**
+ * struct hwd_viif_img - image information
+ * @width: active width of image[pixel]
+ * * [128..5760](output from L2ISP)
+ * * [128..4096](input to MAIN unit(memory input))
+ * * [128..4096](output from SUB unit)
+ * * The value should be even.
+ *
+ * @height: active height of image[line]
+ * * [128..3240](output from L2ISP)
+ * * [128..2160](input to MAIN unit(memory input))
+ * * [128..2160](output from SUB unit)
+ * * The value should be even.
+ *
+ * @format: hwd_viif_color_format "color format"
+ * * Below color formats are supported for input and output of MAIN unit
+ * * HWD_VIIF_YCBCR422_8_PACKED
+ * * HWD_VIIF_RGB888_PACKED
+ * * HWD_VIIF_ARGB8888_PACKED
+ * * HWD_VIIF_YCBCR422_8_PLANAR
+ * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR
+ * * HWD_VIIF_ONE_COLOR_8
+ * * HWD_VIIF_YCBCR422_16_PLANAR
+ * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR
+ * * HWD_VIIF_ONE_COLOR_16
+ * * Below color formats are supported for output of SUB unit
+ * * HWD_VIIF_ONE_COLOR_8
+ * * HWD_VIIF_ONE_COLOR_16
+ *
+ * @pixelmap: pixelmap information
+ * * [0]: Y/G-planar, packed/Y/RAW
+ * * [1]: Cb/B-planar
+ * * [2]: Cr/R-planar
+ */
+struct hwd_viif_img {
+ u32 width;
+ u32 height;
+ u32 format;
+ struct hwd_viif_pixelmap pixelmap[3];
+};
+
+/**
+ * struct hwd_viif_input_img - input image information
+ * @pixel_clock: pixel clock [3375..600000] [kHz]. 0 needs to be set for long packet data.
+ * @htotal_size: horizontal total size
+ * * [143..65535] [pixel] for image data
+ * * [239..109225] [ns] for long packet data
+ * @hactive_size: horizontal active size [pixel]
+ * * [128..4096] without L1ISP
+ * * [640..3840] with L1ISP
+ * * The value should be even. In addition, the value should be a multiple of 8 with L1ISP
+ * * 0 needs to be set for the configuration of long packet data or SUB unit output.
+ * @vtotal_size: vertical total size [line]
+ * * [144..16383] for image data
+ * * 0 needs to be set for the configuration of long packet data.
+ * @vbp_size: vertical back porch size
+ * * [5..4095] [line] for image data
+ * * [5..4095] [the number of packet] for long packet data
+ * @vactive_size: vertical active size [line]
+ * * [128..2160] without L1ISP
+ * * [480..2160] with L1ISP
+ * * The value should be even.
+ * * 0 needs to be set for the configuration of long packet data.
+ * @interpolation_mode: input image interpolation mode for hwd_viif_l1_input_interpolation_mode
+ * * HWD_VIIF_L1_INPUT_INTERPOLATION_LINE needs to be set in the below cases.
+ * * image data(without L1ISP) or long packet data
+ * * image data or long packet data of SUB unit
+ * @input_num: the number of input images [1..3]
+ * * 1 needs to be set in the below cases.
+ * * image data(without L1ISP) or long packet data
+ * * image data or long packet data of SUB unit
+ * @hobc_width: the number of horizontal optical black pixels [0,16,32,64 or 128]
+ * * 0 needs to be set in the below cases.
+ * * in case of hobc_margin = 0
+ * * image data(without L1ISP) or long packet data
+ * * image data or long packet data of SUB unit
+ * @hobc_margin: the number of horizontal optical black margin[0..30] (even number)
+ * * 0 needs to be set in the below cases.
+ * * in case of hobc_width = 0
+ * * image data(without L1ISP) or long packet data
+ * * image data or long packet data of SUB unit
+ *
+ * Below conditions need to be satisfied.
+ * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_LINE:
+ * (htotal_size > (hactive_size + hobc_width + hobc_margin)) &&
+ * (vtotal_size > (vbp_size + vactive_size * input_num))
+ * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL:
+ * (htotal_size > ((hactive_size + hobc_width + hobc_margin) * input_num)) &&
+ * (vtotal_size > (vbp_size + vactive_size))
+ * * L1ISP is used:
+ * vbp_size >= (54720[cycle] / 500000[kHz]) * (pixel_clock / htotal_size) + 38 + ISST time
+ * * L1ISP is not used:
+ * vbp_size >= (39360[cycle] / 500000[kHz]) * (pixel_clock / htotal_size) + 16 + ISST time
+ *
+ * Note: L1ISP is used when RAW data is input to MAIN unit
+ */
+struct hwd_viif_input_img {
+ u32 pixel_clock;
+ u32 htotal_size;
+ u32 hactive_size;
+ u32 vtotal_size;
+ u32 vbp_size;
+ u32 vactive_size;
+ u32 interpolation_mode;
+ u32 input_num;
+ u32 hobc_width;
+ u32 hobc_margin;
+};
+
+/**
+ * struct hwd_viif_csc_param - color conversion information
+ * @r_cr_in_offset: input offset of R/Cr[pix value] [0x0..0x1FFFF]
+ * @g_y_in_offset: input offset of G/Y[pix value] [0x0..0x1FFFF]
+ * @b_cb_in_offset: input offset of B/Cb[pix value] [0x0..0x1FFFF]
+ * @coef: coefficient of matrix [0x0..0xFFFF]
+ * * [0] : c00(YG_YG), [1] : c01(UB_YG), [2] : c02(VR_YG),
+ * * [3] : c10(YG_UB), [4] : c11(UB_UB), [5] : c12(VR_UB),
+ * * [6] : c20(YG_VR), [7] : c21(UB_VR), [8] : c22(VR_VR)
+ * @r_cr_out_offset: output offset of R/Cr[pix value] [0x0..0x1FFFF]
+ * @g_y_out_offset: output offset of G/Y[pix value] [0x0..0x1FFFF]
+ * @b_cb_out_offset: output offset of B/Cb[pix value] [0x0..0x1FFFF]
+ */
+struct hwd_viif_csc_param {
+ u32 r_cr_in_offset;
+ u32 g_y_in_offset;
+ u32 b_cb_in_offset;
+ u32 coef[9];
+ u32 r_cr_out_offset;
+ u32 g_y_out_offset;
+ u32 b_cb_out_offset;
+};
+
+/**
+ * struct hwd_viif_img_area - image area definition
+ * @x: x position [0..8062] [pixel]
+ * @y: y position [0..3966] [line]
+ * @w: image width [128..8190] [pixel]
+ * @h: image height [128..4094] [line]
+ */
+struct hwd_viif_img_area {
+ u32 x;
+ u32 y;
+ u32 w;
+ u32 h;
+};
+
+/**
+ * struct hwd_viif_out_process - configuration of output process of MAIN unit and L2ISP
+ * @half_scale: hwd_viif_enable_flag "enable or disable half scale"
+ * @select_color: hwd_viif_output_color_mode "select output color"
+ * @alpha: alpha value used in case of ARGB8888 output [0..255]
+ */
+struct hwd_viif_out_process {
+ u32 half_scale;
+ u32 select_color;
+ u8 alpha;
+};
+
+/**
+ * struct hwd_viif_l1_lsc - HWD L1ISP lens shading correction parameters
+ * @lssc_parabola_param: parabola shading correction parameter
+ * * NULL: disable parabola shading correction
+ * * not NULL: enable parabola shading correction
+ * @lssc_grid_param: grid shading correction parameter
+ * * NULL: disable grid shading correction
+ * * not NULL: enable grid shading correction
+ * @lssc_pwhb_r_gain_max: maximum R gain of preset white balance correction
+ * @lssc_pwhb_r_gain_min: minimum R gain of preset white balance correction
+ * @lssc_pwhb_gr_gain_max: maximum Gr gain of preset white balance correction
+ * @lssc_pwhb_gr_gain_min: minimum Gr gain of preset white balance correction
+ * @lssc_pwhb_gb_gain_max: maximum Gb gain of preset white balance correction
+ * @lssc_pwhb_gb_gain_min: minimum Gb gain of preset white balance correction
+ * @lssc_pwhb_b_gain_max: maximum B gain of preset white balance correction
+ * @lssc_pwhb_b_gain_min: minimum B gain of preset white balance correction
+ *
+ * Range and accuracy of lssc_pwhb_xxx_gain_xxx are as below.
+ * - range: [0x0..0x7FF]
+ * - accuracy : 1/256
+ */
+struct hwd_viif_l1_lsc {
+ struct viif_l1_lsc_parabola_param *lssc_parabola_param;
+ struct viif_l1_lsc_grid_param *lssc_grid_param;
+ u32 lssc_pwhb_r_gain_max;
+ u32 lssc_pwhb_r_gain_min;
+ u32 lssc_pwhb_gr_gain_max;
+ u32 lssc_pwhb_gr_gain_min;
+ u32 lssc_pwhb_gb_gain_max;
+ u32 lssc_pwhb_gb_gain_min;
+ u32 lssc_pwhb_b_gain_max;
+ u32 lssc_pwhb_b_gain_min;
+};
+
+/**
+ * struct hwd_viif_l1_img_quality_adjustment - HWD L1ISP image quality adjustment parameters
+ * @coef_cb: Cb coefficient [0x0..0xffff] accuracy: 1/65536
+ * @coef_cr: Cr coefficient [0x0..0xffff] accuracy: 1/65536
+ * @brightness: brightness value [-32768..32767] (0 means off.)
+ * @linear_contrast: linear contrast value [0x0..0xff] accuracy: 1/128 (128 means off.)
+ * @*nonlinear_contrast: pointer to nonlinear contrast parameter
+ * @*lum_noise_reduction: pointer to luminance noise reduction parameter
+ * @*edge_enhancement: pointer to edge enhancement parameter
+ * @*uv_suppression: pointer to UV suppression parameter
+ * @*coring_suppression: pointer to coring suppression parameter
+ * @*edge_suppression: pointer to edge enhancement parameter
+ * @*color_level: pointer to color level adjustment parameter
+ * @color_noise_reduction_enable: enable/disable color noise reduction @ref hwd_viif_enable_flag
+ */
+struct hwd_viif_l1_img_quality_adjustment {
+ u16 coef_cb;
+ u16 coef_cr;
+ s16 brightness;
+ u8 linear_contrast;
+ struct viif_l1_nonlinear_contrast *nonlinear_contrast;
+ struct viif_l1_lum_noise_reduction *lum_noise_reduction;
+ struct viif_l1_edge_enhancement *edge_enhancement;
+ struct viif_l1_uv_suppression *uv_suppression;
+ struct viif_l1_coring_suppression *coring_suppression;
+ struct viif_l1_edge_suppression *edge_suppression;
+ struct viif_l1_color_level *color_level;
+ u32 color_noise_reduction_enable;
+};
+
+/**
+ * struct hwd_viif_l1_info - HWD L1ISP processing information
+ * @context_id: context id
+ * @ag_cont_hobc_high: analog gain for high sensitivity image of OBCC
+ * @ag_cont_hobc_middle_led: analog gain for middle sensitivity or led image of OBCC
+ * @ag_cont_hobc_low: analog gain for low sensitivity image of OBCC
+ * @ag_cont_abpc_high: analog gain for high sensitivity image of ABPC
+ * @ag_cont_abpc_middle_led: analog gain for middle sensitivity or led image of ABPC
+ * @ag_cont_abpc_low: analog gain for low sensitivity image of ABPC
+ * @ag_cont_rcnr_high: analog gain for high sensitivity image of RCNR
+ * @ag_cont_rcnr_middle_led: analog gain for middle sensitivity or led image of RCNR
+ * @ag_cont_rcnr_low: analog gain for low sensitivity image of RCNR
+ * @ag_cont_lssc: analog gain for LSSC
+ * @ag_cont_mpro: analog gain for color matrix correction
+ * @ag_cont_vpro: analog gain for image quality adjustment
+ * @dpc_defect_num_h:
+ * the number of dynamically corrected defective pixel(high sensitivity image)
+ * @dpc_defect_num_m:
+ * the number of dynamically corrected defective pixel(middle sensitivity or led image)
+ * @dpc_defect_num_l:
+ * the number of dynamically corrected defective pixel(low sensitivity image)
+ * @hdrc_tnp_fb_smth_max: the maximum value of luminance information after smoothing filter at HDRC
+ * @avg_lum_weight: weighted average luminance value at average luminance generation
+ * @avg_lum_block[8][8]:
+ * average luminance of each block [y][x]:
+ * y means vertical position and x means horizontal position.
+ * @avg_lum_four_line_lum[4]:
+ * 4-lines average luminance. avg_lum_four_line_lum[n] corresponds to aexp_ave4linesy[n]
+ * @avg_satur_pixnum: the number of saturated pixel at average luminance generation
+ * @avg_black_pixnum: the number of black pixel at average luminance generation
+ * @awb_ave_u: average U at AWHB [pixel]
+ * @awb_ave_v: average V at AWHB [pixel]
+ * @awb_accumulated_pixel: the number of accumulated pixel at AWHB
+ * @awb_gain_r: R gain applied in the next frame at AWHB
+ * @awb_gain_g: G gain applied in the next frame at AWHB
+ * @awb_gain_b: B gain applied in the next frame at AWHB
+ * @awb_status_u: status of U convergence at AWHB (true: converged, false: not converged)
+ * @awb_status_v: status of V convergence at AWHB (true: converged, false: not converged)
+ */
+struct hwd_viif_l1_info {
+ u32 context_id;
+ u8 ag_cont_hobc_high;
+ u8 ag_cont_hobc_middle_led;
+ u8 ag_cont_hobc_low;
+ u8 ag_cont_abpc_high;
+ u8 ag_cont_abpc_middle_led;
+ u8 ag_cont_abpc_low;
+ u8 ag_cont_rcnr_high;
+ u8 ag_cont_rcnr_middle_led;
+ u8 ag_cont_rcnr_low;
+ u8 ag_cont_lssc;
+ u8 ag_cont_mpro;
+ u8 ag_cont_vpro;
+ u32 dpc_defect_num_h;
+ u32 dpc_defect_num_m;
+ u32 dpc_defect_num_l;
+ u32 hdrc_tnp_fb_smth_max;
+ u32 avg_lum_weight;
+ u32 avg_lum_block[8][8];
+ u32 avg_lum_four_line_lum[4];
+ u16 avg_satur_pixnum;
+ u16 avg_black_pixnum;
+ u32 awb_ave_u;
+ u32 awb_ave_v;
+ u32 awb_accumulated_pixel;
+ u32 awb_gain_r;
+ u32 awb_gain_g;
+ u32 awb_gain_b;
+ bool awb_status_u;
+ bool awb_status_v;
+};
+
+/**
+ * struct hwd_viif_l2_gamma_table - HWD L2ISP Gamma table physical address
+ * @table[6]: table address(physical address) 4byte alignment
+ *
+ * relation between element and table is as below.
+ * * [0]: G/Y(1st table)
+ * * [1]: G/Y(2nd table)
+ * * [2]: B/U(1st table)
+ * * [3]: B/U(2nd table)
+ * * [4]: R/V(1st table)
+ * * [5]: R/V(2nd table)
+ *
+ * when 0 is set to table address, table transfer is disabled.
+ */
+struct hwd_viif_l2_gamma_table {
+ uintptr_t table[6];
+};
+
+struct hwd_viif_res;
+
+/* VIIF common */
+u32 hwd_viif_csi2rx_err_irq_handler(struct hwd_viif_res *res);
+void hwd_viif_status_err_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub);
+void hwd_viif_vsync_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub);
+void hwd_viif_isp_regbuf_irq_handler(struct hwd_viif_res *res, u32 *event_l1, u32 *event_l2);
+
+/* control MAIN unit */
+s32 hwd_viif_main_set_unit(struct hwd_viif_res *res, u32 dt_image,
+ const struct hwd_viif_input_img *in_img, u32 color_type, u32 rawpack,
+ u32 yuv_conv);
+s32 hwd_viif_main_mask_vlatch(struct hwd_viif_res *res, u32 enable);
+void hwd_viif_main_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask);
+void hwd_viif_main_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask);
+
+/* conrol SUB unit */
+s32 hwd_viif_sub_set_unit(struct hwd_viif_res *res, u32 dt_image,
+ const struct hwd_viif_input_img *in_img);
+s32 hwd_viif_sub_set_img_transmission(struct hwd_viif_res *res, const struct hwd_viif_img *img);
+void hwd_viif_sub_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask);
+void hwd_viif_sub_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask);
+
+/* control MIPI CSI2 Receiver unit */
+s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32 lane_assign,
+ u32 dphy_rate, u32 rext_calibration,
+ const struct hwd_viif_csi2rx_line_err_target *err_target,
+ const struct hwd_viif_csi2rx_irq_mask *mask);
+s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res);
+s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
+ const struct hwd_viif_csi2rx_packet *packet);
+s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res);
+s32 hwd_viif_csi2rx_get_calibration_status(
+ struct hwd_viif_res *res, struct viif_csi2rx_dphy_calibration_status *calibration_status);
+s32 hwd_viif_csi2rx_get_err_status(struct hwd_viif_res *res, u32 *err_phy_fatal, u32 *err_pkt_fatal,
+ u32 *err_frame_fatal, u32 *err_phy, u32 *err_pkt, u32 *err_line);
+
+/* control L1 Image Signal Processor */
+void hwd_viif_isp_set_regbuf_auto_transmission(struct hwd_viif_res *res);
+void hwd_viif_isp_disable_regbuf_auto_transmission(struct hwd_viif_res *res);
+void hwd_viif_isp_get_info(struct hwd_viif_res *res, struct hwd_viif_l1_info *l1_info,
+ u32 *l2_transfer_status);
+void hwd_viif_isp_set_regbuf_irq_mask(struct hwd_viif_res *res, const u32 *mask_l1,
+ const u32 *mask_l2);
+
+s32 hwd_viif_l1_set_input_mode(struct hwd_viif_res *res, u32 mode, u32 depth, u32 raw_color_filter);
+s32 hwd_viif_l1_set_rgb_to_y_coef(struct hwd_viif_res *res, u16 coef_r, u16 coef_g, u16 coef_b);
+s32 hwd_viif_l1_set_ag_mode(struct hwd_viif_res *res, const struct viif_l1_ag_mode_config *param);
+s32 hwd_viif_l1_set_ag(struct hwd_viif_res *res, u16 gain_h, u16 gain_m, u16 gain_l);
+s32 hwd_viif_l1_set_hdre(struct hwd_viif_res *res, const struct viif_l1_hdre_config *param);
+s32 hwd_viif_l1_set_img_extraction(struct hwd_viif_res *res, u32 input_black_gr, u32 input_black_r,
+ u32 input_black_b, u32 input_black_gb);
+s32 hwd_viif_l1_set_dpc(struct hwd_viif_res *res, const struct viif_l1_dpc *param_h,
+ const struct viif_l1_dpc *param_m, const struct viif_l1_dpc *param_l);
+s32 hwd_viif_l1_set_dpc_table_transmission(struct hwd_viif_res *res, uintptr_t table_h,
+ uintptr_t table_m, uintptr_t table_l);
+s32 hwd_viif_l1_set_preset_white_balance(struct hwd_viif_res *res, u32 dstmaxval,
+ const struct viif_l1_preset_wb *param_h,
+ const struct viif_l1_preset_wb *param_m,
+ const struct viif_l1_preset_wb *param_l);
+s32 hwd_viif_l1_set_raw_color_noise_reduction(
+ struct hwd_viif_res *res, const struct viif_l1_raw_color_noise_reduction *param_h,
+ const struct viif_l1_raw_color_noise_reduction *param_m,
+ const struct viif_l1_raw_color_noise_reduction *param_l);
+s32 hwd_viif_l1_set_hdrs(struct hwd_viif_res *res, const struct viif_l1_hdrs_config *param);
+s32 hwd_viif_l1_set_black_level_correction(
+ struct hwd_viif_res *res, const struct viif_l1_black_level_correction_config *param);
+s32 hwd_viif_l1_set_lsc(struct hwd_viif_res *res, const struct hwd_viif_l1_lsc *param);
+s32 hwd_viif_l1_set_lsc_table_transmission(struct hwd_viif_res *res, uintptr_t table_gr,
+ uintptr_t table_r, uintptr_t table_b,
+ uintptr_t table_gb);
+s32 hwd_viif_l1_set_main_process(struct hwd_viif_res *res, u32 demosaic_mode, u32 damp_lsbsel,
+ const struct viif_l1_color_matrix_correction *color_matrix,
+ u32 dst_maxval);
+s32 hwd_viif_l1_set_awb(struct hwd_viif_res *res, const struct viif_l1_awb *param, u32 awhb_wbmrg,
+ u32 awhb_wbmgg, u32 awhb_wbmbg);
+s32 hwd_viif_l1_lock_awb_gain(struct hwd_viif_res *res, u32 enable);
+s32 hwd_viif_l1_set_hdrc(struct hwd_viif_res *res, const struct viif_l1_hdrc *param,
+ u32 hdrc_thr_sft_amt);
+s32 hwd_viif_l1_set_hdrc_ltm(struct hwd_viif_res *res, const struct viif_l1_hdrc_ltm_config *param);
+s32 hwd_viif_l1_set_gamma(struct hwd_viif_res *res, const struct viif_l1_gamma *param);
+s32 hwd_viif_l1_set_img_quality_adjustment(struct hwd_viif_res *res,
+ const struct hwd_viif_l1_img_quality_adjustment *param);
+s32 hwd_viif_l1_set_avg_lum_generation(struct hwd_viif_res *res,
+ const struct viif_l1_avg_lum_generation_config *param);
+void hwd_viif_l1_set_irq_mask(struct hwd_viif_res *res, u32 mask);
+
+/* control L2 Image Signal Processor */
+s32 hwd_viif_l2_set_input_csc(struct hwd_viif_res *res, const struct hwd_viif_csc_param *param,
+ bool is_l1_rgb);
+s32 hwd_viif_l2_set_undist(struct hwd_viif_res *res, const struct viif_l2_undist *param);
+s32 hwd_viif_l2_set_undist_table_transmission(struct hwd_viif_res *res, uintptr_t write_g,
+ uintptr_t read_b, uintptr_t read_g, uintptr_t read_r,
+ u32 size);
+s32 hwd_viif_l2_set_roi(struct hwd_viif_res *res, const struct viif_l2_roi_config *param);
+s32 hwd_viif_l2_set_gamma(struct hwd_viif_res *res, u32 post_id, u32 enable, u32 vsplit, u32 mode);
+s32 hwd_viif_l2_set_gamma_table_transmission(struct hwd_viif_res *res, u32 post_id,
+ const struct hwd_viif_l2_gamma_table *gamma_table);
+s32 hwd_viif_l2_set_output_csc(struct hwd_viif_res *res, u32 post_id,
+ const struct hwd_viif_csc_param *param);
+s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id, u32 enable,
+ const struct hwd_viif_img_area *src,
+ const struct hwd_viif_out_process *out_process,
+ const struct hwd_viif_img *img);
+void hwd_viif_l2_set_irq_mask(struct hwd_viif_res *res, u32 mask);
+
+void hwd_viif_isp_guard_start(struct hwd_viif_res *res);
+void hwd_viif_isp_guard_end(struct hwd_viif_res *res);
+
+struct hwd_viif_res *allocate_viif_res(struct device *dev, void *csi2host_vaddr,
+ void *capture_vaddr);
+
+#endif /* HWD_VIIF_H */
diff --git a/drivers/media/platform/visconti/hwd_viif_csi2rx.c b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
new file mode 100644
index 00000000000..f49869c5bdd
--- /dev/null
+++ b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/timekeeping.h>
+#include "hwd_viif.h"
+#include "hwd_viif_internal.h"
+
+#define CSI2_DT_YUV4208 0x18
+#define CSI2_DT_YUV42010 0x19
+#define CSI2_DT_YUV4208L 0x1A
+#define CSI2_DT_YUV4208C 0x1C
+#define CSI2_DT_YUV42010C 0x1D
+#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
+#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
+#define CSI2_DT_RGB444 0x20
+#define CSI2_DT_RGB555 0x21
+#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
+#define CSI2_DT_RGB666 0x23
+#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
+#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
+#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
+#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
+#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
+
+#define TESTCTRL0_PHY_TESTCLK_1 0x2
+#define TESTCTRL0_PHY_TESTCLK_0 0x0
+#define TESTCTRL1_PHY_TESTEN 0x10000
+#define TESTCTRL1_PHY_TESTDOUT_SHIFT 8U
+
+/**
+ * write_dphy_param() - Write CSI2RX DPHY params
+ *
+ * @test_mode: test code address
+ * @test_in: test code data
+ * Return: None
+ */
+static void write_dphy_param(u32 test_mode, u8 test_in, struct hwd_viif_res *res)
+{
+ /* select MSB address register */
+ writel(TESTCTRL1_PHY_TESTEN, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* set MSB address of test_mode */
+ writel(FIELD_GET(0xF00, test_mode), &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* select and set LSB address register */
+ writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
+ &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* set the test code data */
+ writel((u32)test_in, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+}
+
+/**
+ * read_dphy_param() - Read CSI2RX DPHY params
+ *
+ * @test_mode: test code address
+ * Return: test code data
+ */
+static u8 read_dphy_param(u32 test_mode, struct hwd_viif_res *res)
+{
+ u32 read_data;
+
+ /* select MSB address register */
+ writel(TESTCTRL1_PHY_TESTEN, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* set MSB address of test_mode */
+ writel(FIELD_GET(0xF00, test_mode), &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* select and set LSB address register */
+ writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
+ &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+
+ /* rise and clear the testclk */
+ writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* read the test code data */
+ read_data = readl(&res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
+ return (u8)(read_data >> TESTCTRL1_PHY_TESTDOUT_SHIFT);
+}
+
+/**
+ * enum dphy_testcode - DPHY registers via the local communication path
+ */
+enum dphy_testcode {
+ DIG_RDWR_RX_SYS_0 = 0x001,
+ DIG_RDWR_RX_SYS_1 = 0x002,
+ DIG_RDWR_RX_SYS_3 = 0x004,
+ DIG_RDWR_RX_SYS_7 = 0x008,
+ DIG_RDWR_RX_RX_STARTUP_OVR_2 = 0x0E2,
+ DIG_RDWR_RX_RX_STARTUP_OVR_3 = 0x0E3,
+ DIG_RDWR_RX_RX_STARTUP_OVR_4 = 0x0E4,
+ DIG_RDWR_RX_RX_STARTUP_OVR_5 = 0x0E5,
+ DIG_RDWR_RX_CB_2 = 0x1AC,
+ DIG_RD_RX_TERM_CAL_0 = 0x220,
+ DIG_RD_RX_TERM_CAL_1 = 0x221,
+ DIG_RD_RX_TERM_CAL_2 = 0x222,
+ DIG_RDWR_RX_CLKLANE_LANE_6 = 0x307,
+ DIG_RD_RX_CLKLANE_OFFSET_CAL_0 = 0x39D,
+ DIG_RD_RX_LANE0_OFFSET_CAL_0 = 0x59F,
+ DIG_RD_RX_LANE0_DDL_0 = 0x5E0,
+ DIG_RD_RX_LANE1_OFFSET_CAL_0 = 0x79F,
+ DIG_RD_RX_LANE1_DDL_0 = 0x7E0,
+ DIG_RD_RX_LANE2_OFFSET_CAL_0 = 0x99F,
+ DIG_RD_RX_LANE2_DDL_0 = 0x9E0,
+ DIG_RD_RX_LANE3_OFFSET_CAL_0 = 0xB9F,
+ DIG_RD_RX_LANE3_DDL_0 = 0xBE0,
+};
+
+#define SYS_0_HSFREQRANGE_OVR BIT(5)
+#define SYS_7_RESERVED FIELD_PREP(0x1F, 0x0C)
+#define SYS_7_DESKEW_POL BIT(5)
+#define STARTUP_OVR_4_CNTVAL FIELD_PREP(0x70, 0x01)
+#define STARTUP_OVR_4_DDL_EN BIT(0)
+#define STARTUP_OVR_5_BYPASS BIT(0)
+#define CB_2_LPRX_BIAS BIT(6)
+#define CB_2_RESERVED FIELD_PREP(0x3F, 0x0B)
+#define CLKLANE_RXHS_PULL_LONG BIT(7)
+
+static const struct hwd_viif_dphy_hs_info dphy_hs_info[] = {
+ { 80, 0x0, 0x1cc }, { 85, 0x10, 0x1cc }, { 95, 0x20, 0x1cc }, { 105, 0x30, 0x1cc },
+ { 115, 0x1, 0x1cc }, { 125, 0x11, 0x1cc }, { 135, 0x21, 0x1cc }, { 145, 0x31, 0x1cc },
+ { 155, 0x2, 0x1cc }, { 165, 0x12, 0x1cc }, { 175, 0x22, 0x1cc }, { 185, 0x32, 0x1cc },
+ { 198, 0x3, 0x1cc }, { 213, 0x13, 0x1cc }, { 228, 0x23, 0x1cc }, { 243, 0x33, 0x1cc },
+ { 263, 0x4, 0x1cc }, { 288, 0x14, 0x1cc }, { 313, 0x25, 0x1cc }, { 338, 0x35, 0x1cc },
+ { 375, 0x5, 0x1cc }, { 425, 0x16, 0x1cc }, { 475, 0x26, 0x1cc }, { 525, 0x37, 0x1cc },
+ { 575, 0x7, 0x1cc }, { 625, 0x18, 0x1cc }, { 675, 0x28, 0x1cc }, { 725, 0x39, 0x1cc },
+ { 775, 0x9, 0x1cc }, { 825, 0x19, 0x1cc }, { 875, 0x29, 0x1cc }, { 925, 0x3a, 0x1cc },
+ { 975, 0xa, 0x1cc }, { 1025, 0x1a, 0x1cc }, { 1075, 0x2a, 0x1cc }, { 1125, 0x3b, 0x1cc },
+ { 1175, 0xb, 0x1cc }, { 1225, 0x1b, 0x1cc }, { 1275, 0x2b, 0x1cc }, { 1325, 0x3c, 0x1cc },
+ { 1375, 0xc, 0x1cc }, { 1425, 0x1c, 0x1cc }, { 1475, 0x2c, 0x1cc }
+};
+
+/**
+ * get_dphy_hs_transfer_info() - Get DPHY HS info from table
+ *
+ * @dphy_rate: DPHY clock in MHz
+ * @hsfreqrange: HS Frequency Range
+ * @osc_freq_target: OSC Frequency Target
+ * Return: None
+ */
+static void get_dphy_hs_transfer_info(u32 dphy_rate, u32 *hsfreqrange, u32 *osc_freq_target,
+ struct hwd_viif_res *res)
+{
+ int table_size = ARRAY_SIZE(dphy_hs_info);
+ int i;
+
+ for (i = 1; i < table_size; i++) {
+ if (dphy_rate < dphy_hs_info[i].rate) {
+ *hsfreqrange = dphy_hs_info[i - 1].hsfreqrange;
+ *osc_freq_target = dphy_hs_info[i - 1].osc_freq_target;
+ return;
+ }
+ }
+
+ /* not found; return the largest entry */
+ *hsfreqrange = dphy_hs_info[table_size - 1].hsfreqrange;
+ *osc_freq_target = dphy_hs_info[table_size - 1].osc_freq_target;
+}
+
+/**
+ * hwd_viif_csi2rx_set_dphy_rate() - Set D-PHY rate
+ *
+ * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
+ * Return: None
+ */
+static void hwd_viif_csi2rx_set_dphy_rate(u32 dphy_rate, struct hwd_viif_res *res)
+{
+ u32 hsfreqrange, osc_freq_target;
+
+ get_dphy_hs_transfer_info(dphy_rate, &hsfreqrange, &osc_freq_target, res);
+
+ write_dphy_param(DIG_RDWR_RX_SYS_1, (u8)hsfreqrange, res);
+ write_dphy_param(DIG_RDWR_RX_SYS_0, SYS_0_HSFREQRANGE_OVR, res);
+ write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_5, STARTUP_OVR_5_BYPASS, res);
+ write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4, STARTUP_OVR_4_CNTVAL, res);
+ write_dphy_param(DIG_RDWR_RX_CB_2, CB_2_LPRX_BIAS | CB_2_RESERVED, res);
+ write_dphy_param(DIG_RDWR_RX_SYS_7, SYS_7_DESKEW_POL | SYS_7_RESERVED, res);
+ write_dphy_param(DIG_RDWR_RX_CLKLANE_LANE_6, CLKLANE_RXHS_PULL_LONG, res);
+ write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_2, FIELD_GET(0xff, osc_freq_target), res);
+ write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_3, FIELD_GET(0xf00, osc_freq_target), res);
+ write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4, STARTUP_OVR_4_CNTVAL | STARTUP_OVR_4_DDL_EN,
+ res);
+
+ writel(HWD_VIIF_DPHY_CFG_CLK_25M, &res->capture_reg->sys.DPHY_FREQRANGE);
+}
+
+/**
+ * check_dphy_calibration_status() - Check D-PHY calibration status
+ *
+ * @test_mode: test code related to calibration information
+ * @shift_val_err: shift value related to error information
+ * @shift_val_done: shift value related to done information
+ * Return: HWD_VIIF_CSI2_CAL_NOT_DONE calibration is not done(out of target or not completed)
+ * Return: HWD_VIIF_CSI2_CAL_FAIL calibration was failed
+ * Return: HWD_VIIF_CSI2_CAL_SUCCESS calibration was succeeded
+ */
+static u32 check_dphy_calibration_status(u32 test_mode, u32 shift_val_err, u32 shift_val_done,
+ struct hwd_viif_res *res)
+{
+ u32 read_data = (u32)read_dphy_param(test_mode, res);
+
+ if (!(read_data & BIT(shift_val_done)))
+ return HWD_VIIF_CSI2_CAL_NOT_DONE;
+
+ /* error check is not required for termination calibration with REXT(0x221) */
+ if (test_mode == DIG_RD_RX_TERM_CAL_1)
+ return HWD_VIIF_CSI2_CAL_SUCCESS;
+
+ /* done with error */
+ if (read_data & BIT(shift_val_err))
+ return HWD_VIIF_CSI2_CAL_FAIL;
+
+ return HWD_VIIF_CSI2_CAL_SUCCESS;
+}
+
+/**
+ * hwd_viif_csi2rx_initialize() - Initialize CSI-2 RX driver
+ *
+ * @num_lane: [1..4](VIIF CH0-CH1)
+ * @lane_assign: lane connection. For more refer @ref hwd_viif_dphy_lane_assignment
+ * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
+ * @rext_calibration: enable or disable rext calibration.
+ * For more refer @ref hwd_viif_csi2rx_cal_status
+ * @err_target: Pointer to configuration for Line error detection.
+ * @mask: MASK of CSI-2 RX error interruption
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "num_lane", "lane_assign", "dphy_rate", "rext_calibration" or "input_mode" is out of range
+ * - [2] "err_target" is NULL
+ * - [3] member of "err_target" is invalid
+ */
+s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32 lane_assign,
+ u32 dphy_rate, u32 rext_calibration,
+ const struct hwd_viif_csi2rx_line_err_target *err_target,
+ const struct hwd_viif_csi2rx_irq_mask *mask)
+{
+ u32 i, val;
+
+ if (num_lane == 0U || num_lane > 4U || lane_assign > HWD_VIIF_CSI2_DPHY_L0L2L1L3)
+ return -EINVAL;
+
+ if (dphy_rate < HWD_VIIF_DPHY_MIN_DATA_RATE || dphy_rate > HWD_VIIF_DPHY_MAX_DATA_RATE ||
+ (rext_calibration != HWD_VIIF_ENABLE && rext_calibration != HWD_VIIF_DISABLE) ||
+ !err_target) {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < 8U; i++) {
+ if (err_target->vc[i] > HWD_VIIF_CSI2_MAX_VC ||
+ err_target->dt[i] > HWD_VIIF_CSI2_MAX_DT ||
+ (err_target->dt[i] < HWD_VIIF_CSI2_MIN_DT && err_target->dt[i] != 0U)) {
+ return -EINVAL;
+ }
+ }
+
+ /* 1st phase of initialization */
+ writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_RESETN);
+ writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
+ writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
+ writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ ndelay(15U);
+ writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+
+ /* Configure D-PHY frequency range */
+ hwd_viif_csi2rx_set_dphy_rate(dphy_rate, res);
+
+ /* 2nd phase of initialization */
+ writel((num_lane - 1U), &res->csi2host_reg->CSI2RX_NLANES);
+ ndelay(5U);
+
+ /* configuration not to use rext */
+ if (rext_calibration == HWD_VIIF_DISABLE) {
+ write_dphy_param(0x004, 0x10, res);
+ ndelay(5U);
+ }
+
+ /* Release D-PHY from Reset */
+ writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
+ ndelay(5U);
+ writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
+
+ /* configuration of line error target */
+ val = (err_target->vc[3] << 30U) | (err_target->dt[3] << 24U) | (err_target->vc[2] << 22U) |
+ (err_target->dt[2] << 16U) | (err_target->vc[1] << 14U) | (err_target->dt[1] << 8U) |
+ (err_target->vc[0] << 6U) | (err_target->dt[0]);
+ writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_1);
+ val = (err_target->vc[7] << 30U) | (err_target->dt[7] << 24U) | (err_target->vc[6] << 22U) |
+ (err_target->dt[6] << 16U) | (err_target->vc[5] << 14U) | (err_target->dt[5] << 8U) |
+ (err_target->vc[4] << 6U) | (err_target->dt[4]);
+ writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_2);
+
+ /* configuration of mask */
+ writel(mask->mask[0], &res->csi2host_reg->CSI2RX_INT_MSK_PHY_FATAL);
+ writel(mask->mask[1], &res->csi2host_reg->CSI2RX_INT_MSK_PKT_FATAL);
+ writel(mask->mask[2], &res->csi2host_reg->CSI2RX_INT_MSK_FRAME_FATAL);
+ writel(mask->mask[3], &res->csi2host_reg->CSI2RX_INT_MSK_PHY);
+ writel(mask->mask[4], &res->csi2host_reg->CSI2RX_INT_MSK_PKT);
+ writel(mask->mask[5], &res->csi2host_reg->CSI2RX_INT_MSK_LINE);
+
+ /* configuration of lane assignment */
+ writel(lane_assign, &res->capture_reg->sys.DPHY_LANE);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_csi2rx_uninitialize() - Uninitialize CSI-2 RX driver
+ *
+ * Return: 0 Operation completes successfully
+ */
+s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res)
+{
+ writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
+ writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
+ writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
+ writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_RESETN);
+
+ return 0;
+}
+
+#define PORT_SEL_MAIN_LONG 0
+#define PORT_SEL_MAIN_EMBED 1
+#define PORT_SEL_SUB_LONG 4
+#define PORT_SEL_SUB_EMBED 5
+
+static void config_vdm_wport(struct hwd_viif_res *res, int port_sel, u32 height, u32 pitch)
+{
+ struct hwd_viif_vdm_write_port_reg *wport;
+ u32 start_addr, end_addr;
+
+ wport = &res->capture_reg->vdm.w_port[port_sel];
+
+ writel(pitch, &wport->VDM_W_PITCH);
+ writel(height, &wport->VDM_W_HEIGHT);
+ start_addr = readl(&wport->VDM_W_STADR);
+ end_addr = start_addr + pitch - 1U;
+ writel(end_addr, &wport->VDM_W_ENDADR);
+}
+
+/**
+ * hwd_viif_csi2rx_start() - Start CSI-2 input
+ *
+ * @vc_main: control CSI-2 input of MAIN unit.
+ * enable with configured VC: 0, 1, 2 or 3, keep disabling:
+ * @vc_sub: control CSI-2 input of SUB unit.
+ * enable with configured VC: 0, 1, 2 or 3, keep disabling:
+ * @packet: Pointer to packet information of embedded data and long packet data
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * HWD_VIIF_CSI2_NOT_CAPTURE
+ * HWD_VIIF_CSI2_NOT_CAPTURE
+ * - [1] "vc_main" or "vc_sub" is out of range
+ * - [2] member of "packet" is invalid
+ */
+s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
+ const struct hwd_viif_csi2rx_packet *packet)
+{
+ u32 val, i, pitch, height, dt;
+ u32 enable_vc0 = HWD_VIIF_DISABLE;
+ u32 enable_vc1 = HWD_VIIF_DISABLE;
+
+ if (vc_main > 3 || vc_main < HWD_VIIF_CSI2_NOT_CAPTURE || vc_sub > 3 ||
+ vc_sub < HWD_VIIF_CSI2_NOT_CAPTURE) {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < VISCONTI_CSI2RX_PACKET_TYPES_NUM; i++) {
+ if (packet->word_count[i] > HWD_VIIF_CSI2_MAX_WORD_COUNT ||
+ packet->packet_num[i] > HWD_VIIF_CSI2_MAX_PACKET_NUM) {
+ return -EINVAL;
+ }
+ }
+
+ writel(HWD_VIIF_INPUT_CSI2, &res->capture_reg->sys.IPORTM);
+
+ if (vc_main != HWD_VIIF_CSI2_NOT_CAPTURE) {
+ writel((u32)vc_main, &res->capture_reg->sys.VCID0SELECT);
+ enable_vc0 = HWD_VIIF_ENABLE;
+ }
+ if (vc_sub != HWD_VIIF_CSI2_NOT_CAPTURE) {
+ writel((u32)vc_sub, &res->capture_reg->sys.VCID1SELECT);
+ enable_vc1 = HWD_VIIF_ENABLE;
+ }
+
+ /* configure Embedded Data transfer of MAIN unit */
+ height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN];
+ pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN], 4);
+ config_vdm_wport(res, PORT_SEL_MAIN_EMBED, height, pitch);
+
+ /* configure Long Packet transfer of MAIN unit */
+ dt = readl(&res->capture_reg->sys.IPORTM_OTHER);
+ if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208C ||
+ dt == CSI2_DT_YUV42010C) {
+ pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN], 4) +
+ ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] * 2U, 4);
+ height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] >> 1U;
+ } else {
+ pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN], 4);
+ height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN];
+ }
+ config_vdm_wport(res, PORT_SEL_MAIN_LONG, height, pitch);
+
+ /* configure Embedded Data transfer of SUB unit */
+ height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB];
+ pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB], 4);
+ config_vdm_wport(res, PORT_SEL_SUB_EMBED, height, pitch);
+
+ /* configure Long Packet transfer of SUB unit */
+ dt = readl(&res->capture_reg->sys.IPORTS_OTHER);
+ if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV42010 || dt == CSI2_DT_YUV4208C ||
+ dt == CSI2_DT_YUV42010C) {
+ pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB], 4) +
+ ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] * 2U, 4);
+ height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] >> 1U;
+ } else {
+ pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB], 4);
+ height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB];
+ }
+ config_vdm_wport(res, PORT_SEL_SUB_LONG, height, pitch);
+
+ /* Control VC port enable */
+ val = enable_vc0 | (enable_vc1 << 4U);
+ writel(val, &res->capture_reg->sys.VCPORTEN);
+
+ if (enable_vc0 == HWD_VIIF_ENABLE) {
+ /* Update flag information for run status of MAIN unit */
+ res->run_flag_main = true;
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_csi2rx_stop() - Stop CSI-2 input
+ *
+ * Return: 0 Operation completes successfully
+ * Return: -ETIMEDOUT Driver timeout error
+ */
+s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res)
+{
+ u32 status_r, status_w, status_t, l2_status;
+ u64 timeout_ns, cur_ns;
+ bool run_flag = true;
+ s32 ret = 0;
+
+ /* Disable auto transmission of register buffer */
+ writel(0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
+ writel(0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
+
+ /* Wait for completion of register buffer transmission */
+ udelay(HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME);
+
+ /* Stop all VCs, long packet input and emb data input of MAIN unit */
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.VCPORTEN);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTM_OTHEREN);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTM_EMBEN);
+
+ /* Stop image data input, long packet input and emb data input of SUB unit */
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_OTHEREN);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_EMBEN);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
+
+ /* Stop VDMAC for all table ports, input ports and write ports */
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_T_ENABLE);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_R_ENABLE);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_W_ENABLE);
+
+ /* Stop all groups(g00, g01 and g02) of VDMAC */
+ writel(0x7, &res->capture_reg->vdm.VDM_ABORTSET);
+
+ timeout_ns = ktime_get_ns() + HWD_VIIF_WAIT_ABORT_COMPLETE_TIME * 1000;
+
+ do {
+ /* Get VDMAC transfer status */
+ status_r = readl(&res->capture_reg->vdm.VDM_R_RUN);
+ status_w = readl(&res->capture_reg->vdm.VDM_W_RUN);
+ status_t = readl(&res->capture_reg->vdm.VDM_T_RUN);
+
+ l2_status = readl(&res->capture_reg->l2isp.L2_BUS_L2_STATUS);
+
+ if (status_r == 0U && status_w == 0U && status_t == 0U && l2_status == 0U)
+ run_flag = false;
+
+ cur_ns = ktime_get_ns();
+
+ if (cur_ns > timeout_ns) {
+ ret = -ETIMEDOUT;
+ run_flag = false;
+ }
+ } while (run_flag);
+
+ if (ret == 0) {
+ /* Clear run flag of MAIN unit */
+ res->run_flag_main = false;
+ }
+
+ return ret;
+}
+
+/**
+ * hwd_viif_csi2rx_get_calibration_status() - Get CSI-2 RX calibration status
+ *
+ * @calibration_status: Pointer to D-PHY calibration status information
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error
+ * - [1] "calibration_status" is NULL
+ */
+s32 hwd_viif_csi2rx_get_calibration_status(
+ struct hwd_viif_res *res, struct viif_csi2rx_dphy_calibration_status *calibration_status)
+{
+ if (!calibration_status)
+ return -EINVAL;
+
+ /* arg0; test register, arg1: error bit, arg2: done bit */
+ /* 0x221: termination calibration with REXT */
+ calibration_status->term_cal_with_rext =
+ check_dphy_calibration_status(DIG_RD_RX_TERM_CAL_1, 0, 7, res);
+ /* 0x39D: clock lane offset calibration */
+ calibration_status->clock_lane_offset_cal =
+ check_dphy_calibration_status(DIG_RD_RX_CLKLANE_OFFSET_CAL_0, 4, 0, res);
+ /* 0x59F: data lane0 offset calibration */
+ calibration_status->data_lane0_offset_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE0_OFFSET_CAL_0, 2, 1, res);
+ /* 0x79F: data lane1 offset calibration */
+ calibration_status->data_lane1_offset_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE1_OFFSET_CAL_0, 2, 1, res);
+ /* 0x99F: data lane2 offset calibration */
+ calibration_status->data_lane2_offset_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE2_OFFSET_CAL_0, 2, 1, res);
+ /* 0xB9F: data lane3 offset calibration */
+ calibration_status->data_lane3_offset_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE3_OFFSET_CAL_0, 2, 1, res);
+
+ /* 0x5E0: data lane0 DDL(Digital Delay Line) calibration */
+ calibration_status->data_lane0_ddl_tuning_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE0_DDL_0, 1, 2, res);
+ /* 0x7E0: data lane1 DDL calibration */
+ calibration_status->data_lane1_ddl_tuning_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE1_DDL_0, 1, 2, res);
+ /* 0x9E0: data lane2 DDL calibration */
+ calibration_status->data_lane2_ddl_tuning_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE2_DDL_0, 1, 2, res);
+ /* 0xBE0: data lane3 DDL calibration */
+ calibration_status->data_lane3_ddl_tuning_cal =
+ check_dphy_calibration_status(DIG_RD_RX_LANE3_DDL_0, 1, 2, res);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_csi2rx_get_err_status() - Get CSI-2 RX error status
+ *
+ * @err_phy_fatal: Pointer to D-PHY fatal error information
+ * @err_pkt_fatal: Pointer to Packet fatal error information
+ * @err_frame_fatal: Pointer to Frame fatal error information
+ * @err_phy: Pointer to D-PHY error information
+ * @err_pkt: Pointer to Packet error information
+ * @err_line: Pointer to Line error information
+ * Return: 0 Operation completes successfully
+ * Return: -EINVAL Parameter error,
+ * when "err_phy_fatal", "err_pkt_fatal", "err_frame_fatal",
+ * "err_phy", "err_pkt" or "err_line" is NULL
+ */
+s32 hwd_viif_csi2rx_get_err_status(struct hwd_viif_res *res, u32 *err_phy_fatal, u32 *err_pkt_fatal,
+ u32 *err_frame_fatal, u32 *err_phy, u32 *err_pkt, u32 *err_line)
+{
+ if (!err_phy_fatal || !err_pkt_fatal || !err_frame_fatal || !err_phy || !err_pkt ||
+ !err_line) {
+ return -EINVAL;
+ }
+ *err_phy_fatal = readl(&res->csi2host_reg->CSI2RX_INT_ST_PHY_FATAL);
+ *err_pkt_fatal = readl(&res->csi2host_reg->CSI2RX_INT_ST_PKT_FATAL);
+ *err_frame_fatal = readl(&res->csi2host_reg->CSI2RX_INT_ST_FRAME_FATAL);
+ *err_phy = readl(&res->csi2host_reg->CSI2RX_INT_ST_PHY);
+ *err_pkt = readl(&res->csi2host_reg->CSI2RX_INT_ST_PKT);
+ *err_line = readl(&res->csi2host_reg->CSI2RX_INT_ST_LINE);
+
+ return 0;
+}
diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h b/drivers/media/platform/visconti/hwd_viif_internal.h
new file mode 100644
index 00000000000..c954e804946
--- /dev/null
+++ b/drivers/media/platform/visconti/hwd_viif_internal.h
@@ -0,0 +1,340 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#ifndef HWD_VIIF_INTERNAL_H
+#define HWD_VIIF_INTERNAL_H
+
+#include "hwd_viif_reg.h"
+
+#define HWD_VIIF_CSI2_MAX_VC (3U)
+#define HWD_VIIF_CSI2_MIN_DT (0x10U)
+#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
+#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
+#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
+#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
+#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
+#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
+#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
+
+/* maximum horizontal/vertical position/dimension of CROP with ISP */
+#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
+#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
+#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
+#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
+
+/* maximum horizontal/vertical position/dimension of CROP without ISP */
+#define HWD_VIIF_CROP_MAX_X (1920U)
+#define HWD_VIIF_CROP_MAX_Y (1408U)
+#define HWD_VIIF_CROP_MIN_W (128U)
+#define HWD_VIIF_CROP_MAX_W (2048U)
+#define HWD_VIIF_CROP_MIN_H (128U)
+#define HWD_VIIF_CROP_MAX_H (1536U)
+
+/* pixel clock: [kHz] */
+#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
+#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
+
+/* picture size: [pixel], [ns] */
+#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
+#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
+#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
+#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
+
+/* horizontal back porch size: [system clock] */
+#define HWD_VIIF_HBP_SYSCLK (10U)
+
+/* active picture size: [pixel] */
+#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
+#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
+#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
+#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
+
+/* picture vertical size: [line], [packet] */
+#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
+#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
+#define HWD_VIIF_MIN_VBP_LINE (5U)
+#define HWD_VIIF_MAX_VBP_LINE (4095U)
+#define HWD_VIIF_MIN_VBP_PACKET (5U)
+#define HWD_VIIF_MAX_VBP_PACKET (4095U)
+#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
+#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
+#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
+#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
+
+/* image source select */
+#define HWD_VIIF_INPUT_CSI2 (0U)
+
+#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
+#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
+#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
+#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
+#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
+#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
+#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
+#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
+#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
+#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
+#define HWD_VIIF_MAX_PITCH_ISP (32704U)
+#define HWD_VIIF_MAX_PITCH (65536U)
+
+/* size of minimum/maximum input image */
+#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
+#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
+#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
+#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
+#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
+#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
+#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
+
+/* size of minimum/maximum output image */
+#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
+#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
+#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
+
+#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
+#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
+#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
+
+#define HWD_VIIF_NO_EVENT (0x0U)
+
+/* System clock: [kHz] */
+#define HWD_VIIF_SYS_CLK (500000UL)
+
+/*
+ * wait time for force abort to complete(max 1line time = 1228.8[us]
+ * when width = 4096, RAW24, 80Mbps
+ */
+#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
+
+/*
+ * complete time of register buffer transfer.
+ * actual time is about 30us in case of L1ISP
+ */
+#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
+
+/* internal operation latencies: [system clock]*/
+#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
+#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
+
+/* offset of Vsync delay: [line] */
+#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
+#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
+
+/* data width is 32bit */
+#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
+
+/* vsync mode is pulse */
+#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
+
+/* Vlatch mask bit for L1ISP and L2ISP */
+#define HWD_VIIF_ISP_VLATCH_MASK (2U)
+
+/* Register buffer */
+#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
+#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
+#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
+#define HWD_VIIF_ISP_REGBUF_READ (1U)
+
+/* constants for L1 ISP*/
+#define HWD_VIIF_L1_INPUT_MODE_NUM (5U)
+#define HWD_VIIF_L1_INPUT_DEPTH_MIN (8U)
+#define HWD_VIIF_L1_INPUT_DEPTH_MAX (24U)
+#define HWD_VIIF_L1_INPUT_DEPTH_SDR_MAX (12U)
+#define HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX (14U)
+#define HWD_VIIF_L1_RAW_MODE_NUM (4U)
+#define HWD_VIIF_L1_INPUT_NUM_MIN (1U)
+#define HWD_VIIF_L1_INPUT_NUM_MAX (3U)
+#define HWD_VIIF_L1_AG_ID_NUM (4U)
+#define HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM (3U)
+#define HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL (0x3fffU)
+#define HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL (0xffffffU)
+#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO (0x400000U)
+#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL (0xffffffU)
+#define HWD_VIIF_L1_OBCC_MAX_AG_VAL (511U)
+#define HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL (0xffffffU)
+#define HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL (1023U)
+#define HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL (1U)
+#define HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL (31U)
+#define HWD_VIIF_L1_VDM_ALIGN (0x8U) /* port interface width is 64bit */
+#define HWD_VIIF_L1_VDM_CFG_PARAM (0x00000310U) /* data width is 64bit */
+#define HWD_VIIF_L1_VDM_SRAM_BASE (0x00000600U)
+#define HWD_VIIF_L1_VDM_SRAM_SIZE (0x00000020U)
+#define HWD_VIIF_L1_VDM_DPC_TABLE_SIZE (0x2000U)
+#define HWD_VIIF_L1_VDM_LSC_TABLE_SIZE (0x600U)
+#define HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL (4095U)
+#define HWD_VIIF_L1_PWHB_MAX_GAIN_VAL (0x80000U)
+#define HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL (63U)
+#define HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL (31U)
+#define HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL (3U)
+#define HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL (256U)
+#define HWD_VIIF_L1_RCNR_MAX_BLEND_VAL (16U)
+#define HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL (64U)
+#define HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL (4U)
+#define HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL (16U)
+#define HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL (32U)
+#define HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL (2U)
+#define HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO (15U)
+#define HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO (0x400U)
+#define HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO (0x400000U)
+#define HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL (0x400000U)
+#define HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL (0xffffffU)
+#define HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL (4095U)
+#define HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL (0xffffffU)
+#define HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL (0x100000U)
+#define HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL (0xffffffU)
+#define HWD_VIIF_LSC_MIN_GAIN (-4096)
+#define HWD_VIIF_LSC_MAX_GAIN (4096)
+#define HWD_VIIF_LSC_GRID_MIN_COORDINATE (1U)
+#define HWD_VIIF_LSC_PWB_MAX_COEF_VAL (0x800U)
+#define HWD_VIIF_DAMP_MAX_LSBSEL (15U)
+#define HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL (0xffffffU)
+#define HWD_VIIF_AWB_MIN_GAIN (64U)
+#define HWD_VIIF_AWB_MAX_GAIN (1024U)
+#define HWD_VIIF_AWB_GATE_LOWER (-127)
+#define HWD_VIIF_AWB_GATE_UPPER (127)
+#define HWD_VIIF_AWB_UNSIGNED_GATE_UPPER (127U)
+#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED (15U)
+#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL (31U)
+#define HWD_VIIF_AWB_INTEGRATION_STOP_TH (1023U)
+#define HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL (8U)
+#define HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH (10U)
+#define HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH (24U)
+#define HWD_VIIF_L1_HDRC_MAX_PT_SLOPE (13U)
+#define HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO (256U)
+#define HWD_VIIF_L1_HDRC_MAX_FLARE_VAL (0xffffffU)
+#define HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA (16U)
+#define HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO (0x400000U)
+#define HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION (0x4000U)
+#define HWD_VIIF_L1_HDRC_RATIO_OFFSET (10U)
+#define HWD_VIIF_L1_GAMMA_MAX_VAL (8191U)
+#define HWD_VIIF_L1_SUPPRESSION_MAX_VAL (0x4000U)
+#define HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT (15U)
+#define HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN (0x1000U)
+#define HWD_VIIF_L1_AEXP_MAX_WEIGHT (3U)
+#define HWD_VIIF_L1_AEXP_MAX_BLOCK_TH (256U)
+#define HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH (0xffffffU)
+#define HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH (64U)
+#define HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT (64U)
+#define HWD_VIIF_L1_HIST_COLOR_RGBY (2U)
+#define HWD_VIIF_L1_HIST_MAX_BLOCK_NUM (8U)
+#define HWD_VIIF_L1_HIST_MAX_STEP (15U)
+#define HWD_VIIF_L1_HIST_MAX_BIN_SHIFT (31U)
+#define HWD_VIIF_L1_HIST_MAX_COEF (65536U)
+#define HWD_VIIF_L1_HIST_MIN_ADD_B_COEF (-65536)
+#define HWD_VIIF_L1_HIST_MIN_ADD_A_COEF (-16777216)
+#define HWD_VIIF_L1_HIST_MAX_ADD_A_COEF (16777216)
+#define HWD_VIIF_L1_HIST_VDM_SIZE (4096U)
+#define HWD_VIIF_L1_HIST_VDM_SRAM_BASE (0x00000400U)
+#define HWD_VIIF_L1_HIST_VDM_SRAM_SIZE (0x00000040U)
+#define HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT (0x0200U)
+#define HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT (0x10BFU)
+#define HWD_VIIF_L1_COEF_MIN (256U)
+#define HWD_VIIF_L1_COEF_MAX (65024U)
+
+/* constants for L2 ISP */
+#define HWD_VIIF_L2_VDM_ALIGN (0x4U)
+#define HWD_VIIF_L2_VDM_GRID_SRAM_BASE (0x00000620U)
+#define HWD_VIIF_L2_VDM_GRID_SRAM_SIZE (0x00000020U)
+#define HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE (0x00000640U)
+#define HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE (0x00000020U)
+#define HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE (0x00000200U)
+#define HWD_VIIF_L2_UNDIST_POLY_NUM (11U)
+#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H (-4296)
+#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H (4296)
+#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V (-2360)
+#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V (2360)
+#define HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE (1677721U)
+#define HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2 (0x4000000U)
+#define HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA (0x800U)
+#define HWD_VIIF_L2_UNDIST_MIN_POLY_COEF (-2147352576)
+#define HWD_VIIF_L2_UNDIST_MAX_POLY_COEF (2147352576)
+#define HWD_VIIF_L2_UNDIST_MIN_GRID_NUM (16U)
+#define HWD_VIIF_L2_UNDIST_MAX_GRID_NUM (64U)
+#define HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM (2048U)
+#define HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV (0x800000U)
+#define HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE (0x400U)
+#define HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE (0x2000U)
+#define HWD_VIIF_L2_ROI_MIN_NUM (1U)
+#define HWD_VIIF_L2_ROI_MAX_NUM (2U)
+#define HWD_VIIF_L2_ROI_MIN_SCALE (32768U)
+#define HWD_VIIF_L2_ROI_MAX_SCALE (131072U)
+#define HWD_VIIF_L2_ROI_MIN_SCALE_INV (32768U)
+#define HWD_VIIF_L2_ROI_MAX_SCALE_INV (131072U)
+#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE (128U)
+#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE (8190U)
+#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE (128U)
+#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE (4094U)
+#define HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE (128U)
+#define HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE (8190U)
+#define HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE (128U)
+#define HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE (4094U)
+#define HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT (0x1CU)
+#define HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT (0x1FU)
+#define HWD_VIIF_L2_ROI_NONE (3U)
+#define HWD_VIIF_MAX_POST_NUM (2U)
+#define HWD_VIIF_L2_INPUT_OTHER_CH (0x50U)
+
+/**
+ * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
+ *
+ * @roi_num: the number of ROIs which are used.
+ * @post_enable_flag: flag to show which of POST is enabled.
+ * @post_crop_x: CROP x of each L2ISP POST
+ * @post_crop_y: CROP y of each L2ISP POST
+ * @post_crop_w: CROP w of each L2ISP POST
+ * @post_crop_h: CROP h of each L2ISP POST
+ */
+struct hwd_viif_l2_roi_path_info {
+ u32 roi_num;
+ bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
+ u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
+ u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
+ u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
+ u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
+};
+
+/**
+ * struct hwd_viif_res - driver internal resource structure
+ *
+ * @clock_id: clock ID of each unit
+ * @csi2_clock_id: clock ID of CSI-2 RX
+ * @csi2_reset_id: reset ID of CSI-2 RX
+ * @pixel_clock: pixel clock
+ * @htotal_size: horizontal total size
+ * @dt_image_main_w_isp: Data type of image data for ISP path
+ * @csi2host_reg: pointer to register access structure of CSI-2 RX host controller
+ * @capture_reg: pointer to register access structure of capture unit
+ * @l2_roi_path_info: ROI path information of L2ISP
+ * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
+ */
+struct hwd_viif_res {
+ //u32 clock_id;
+ //u32 csi2_clock_id;
+ //u32 csi2_reset_id;
+ u32 pixel_clock;
+ u32 htotal_size;
+ u32 dt_image_main_w_isp;
+ struct hwd_viif_csi2host_reg *csi2host_reg;
+ struct hwd_viif_capture_reg *capture_reg;
+ struct hwd_viif_l2_roi_path_info l2_roi_path_info;
+ bool run_flag_main;
+};
+
+/**
+ * struct hwd_viif_dphy_hs_info - dphy hs information
+ *
+ * @rate: Data rate [Mbps]
+ * @hsfreqrange: IP operating frequency(hsfreqrange)
+ * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
+ */
+struct hwd_viif_dphy_hs_info {
+ u32 rate;
+ u32 hsfreqrange;
+ u32 osc_freq_target;
+};
+
+#endif /* HWD_VIIF_INTERNAL_H */
diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h b/drivers/media/platform/visconti/hwd_viif_reg.h
new file mode 100644
index 00000000000..b7f43c5fe95
--- /dev/null
+++ b/drivers/media/platform/visconti/hwd_viif_reg.h
@@ -0,0 +1,2802 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#ifndef HWD_VIIF_REG_H
+#define HWD_VIIF_REG_H
+
+/**
+ * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST control
+ */
+struct hwd_viif_csi2host_reg {
+ u32 RESERVED_A_1;
+ u32 CSI2RX_NLANES;
+ u32 CSI2RX_RESETN;
+ u32 CSI2RX_INT_ST_MAIN;
+ u32 CSI2RX_DATA_IDS_1;
+ u32 CSI2RX_DATA_IDS_2;
+ u32 RESERVED_B_1[10];
+ u32 CSI2RX_PHY_SHUTDOWNZ;
+ u32 CSI2RX_PHY_RSTZ;
+ u32 CSI2RX_PHY_RX;
+ u32 CSI2RX_PHY_STOPSTATE;
+ u32 CSI2RX_PHY_TESTCTRL0;
+ u32 CSI2RX_PHY_TESTCTRL1;
+ u32 RESERVED_B_2[34];
+ u32 CSI2RX_INT_ST_PHY_FATAL;
+ u32 CSI2RX_INT_MSK_PHY_FATAL;
+ u32 CSI2RX_INT_FORCE_PHY_FATAL;
+ u32 RESERVED_B_3[1];
+ u32 CSI2RX_INT_ST_PKT_FATAL;
+ u32 CSI2RX_INT_MSK_PKT_FATAL;
+ u32 CSI2RX_INT_FORCE_PKT_FATAL;
+ u32 RESERVED_B_4[1];
+ u32 CSI2RX_INT_ST_FRAME_FATAL;
+ u32 CSI2RX_INT_MSK_FRAME_FATAL;
+ u32 CSI2RX_INT_FORCE_FRAME_FATAL;
+ u32 RESERVED_B_5[1];
+ u32 CSI2RX_INT_ST_PHY;
+ u32 CSI2RX_INT_MSK_PHY;
+ u32 CSI2RX_INT_FORCE_PHY;
+ u32 RESERVED_B_6[1];
+ u32 CSI2RX_INT_ST_PKT;
+ u32 CSI2RX_INT_MSK_PKT;
+ u32 CSI2RX_INT_FORCE_PKT;
+ u32 RESERVED_B_7[1];
+ u32 CSI2RX_INT_ST_LINE;
+ u32 CSI2RX_INT_MSK_LINE;
+ u32 CSI2RX_INT_FORCE_LINE;
+ u32 RESERVED_B_8[113];
+ u32 RESERVED_A_2;
+ u32 RESERVED_A_3;
+ u32 RESERVED_A_4;
+ u32 RESERVED_A_5;
+ u32 RESERVED_A_6;
+ u32 RESERVED_B_9[58];
+ u32 RESERVED_A_7;
+};
+
+/**
+ * struct hwd_viif_csc_reg - Registers for VIIF system control
+ */
+struct hwd_viif_csc_reg {
+ u32 MTB;
+ u32 RESERVED_B_16[3];
+ u32 MTB_YG_OFFSETI;
+ u32 MTB_YG1;
+ u32 MTB_YG2;
+ u32 MTB_YG_OFFSETO;
+ u32 MTB_CB_OFFSETI;
+ u32 MTB_CB1;
+ u32 MTB_CB2;
+ u32 MTB_CB_OFFSETO;
+ u32 MTB_CR_OFFSETI;
+ u32 MTB_CR1;
+ u32 MTB_CR2;
+ u32 MTB_CR_OFFSETO;
+};
+
+struct hwd_viif_system_reg {
+ u32 IPORTM0_LD;
+ u32 IPORTM1_LD;
+ u32 RESERVED_B_1[6];
+ u32 IPORTS0_LD;
+ u32 RESERVED_A_1;
+ u32 RESERVED_B_2[2];
+ u32 VCID0SELECT;
+ u32 VCID1SELECT;
+ u32 RESERVED_A_2;
+ u32 VCPORTEN;
+ u32 CSI2SELECT;
+ u32 CSI2THROUGHEN;
+ u32 RESERVED_B_3[2];
+ u32 IPORTM_TEST;
+ u32 IPORTM;
+ u32 IPORTM_MAIN_DT;
+ u32 IPORTM_MAIN_RAW;
+ u32 IPORTM_OTHER;
+ u32 IPORTM_OTHEREN;
+ u32 IPORTM_EMBEN;
+ u32 RESERVED_B_4[2];
+ u32 IPORTS;
+ u32 IPORTS_MAIN_DT;
+ u32 IPORTS_MAIN_RAW;
+ u32 IPORTS_OTHER;
+ u32 IPORTS_OTHEREN;
+ u32 IPORTS_EMBEN;
+ u32 IPORTS_IMGEN;
+ u32 RESERVED_A_3;
+ u32 RESERVED_A_4;
+ u32 RESERVED_B_5[2];
+ u32 IPORTI_M_SYNCEN;
+ u32 IPORTI_M_SYNCMODE;
+ u32 IPORTI_M_PIXFMT;
+ u32 RESERVED_B_6[5];
+ u32 TOTALSIZE_M;
+ u32 VALSIZE_M;
+ u32 BACK_PORCH_M;
+ u32 RESERVED_B_7[5];
+ u32 MAINIMG_PKTSIZE;
+ u32 MAINIMG_HEIGHT;
+ u32 MAINOTHER_PKTSIZE;
+ u32 MAINOTHER_HEIGHT;
+ u32 MAINEMBTOP_SIZE;
+ u32 MAINEMBBOT_SIZE;
+ u32 RESERVED_B_8[2];
+ u32 SUBIMG_PKTSIZE;
+ u32 SUBIMG_HEIGHT;
+ u32 SUBOTHER_PKTSIZE;
+ u32 SUBOTHER_HEIGHT;
+ u32 SUBEMBTOP_SIZE;
+ u32 SUBEMBBOT_SIZE;
+ u32 RESERVED_A_5;
+ u32 RESERVED_A_6;
+ u32 TESTAREA_M_START;
+ u32 TESTAREA_M_SIZE;
+ u32 RESERVED_B_9[2];
+ u32 INT_M_SYNC;
+ u32 INT_M_SYNC_MASK;
+ u32 INT_S_SYNC;
+ u32 INT_S_SYNC_MASK;
+ u32 INT_M0_LINE;
+ u32 INT_M1_LINE;
+ u32 INT_M2_LINE;
+ u32 RESERVED_B_10[5];
+ u32 INT_SA0_LINE;
+ u32 INT_SA1_LINE;
+ u32 RESERVED_B_11[2];
+ u32 RESERVED_A_9;
+ u32 RESERVED_A_10;
+ u32 RESERVED_B_12[2];
+ u32 INT_M_STATUS;
+ u32 INT_M_MASK;
+ u32 INT_S_STATUS;
+ u32 INT_S_MASK;
+ u32 RESERVED_B_13[28];
+ u32 MAIN_TEST_DEN;
+ u32 RESERVED_B_14[3];
+ u32 PREPROCCESS_FMTM;
+ u32 PREPROCCESS_C24M;
+ u32 FRAMEPACK_M;
+ u32 RESERVED_B_15[1];
+ struct hwd_viif_csc_reg l2isp_input_csc;
+ u32 COM0_CK_ENABLE;
+ u32 RESERVED_A_13;
+ u32 RESERVED_A_14;
+ u32 RESERVED_B_17[1];
+ u32 COM0EN;
+ u32 RESERVED_A_16;
+ u32 RESERVED_A_17;
+ u32 RESERVED_B_18[33];
+ u32 COM0_CAP_OFFSET;
+ u32 COM0_CAP_SIZE;
+ u32 RESERVED_B_19[18];
+ u32 GAMMA_M;
+ u32 RESERVED_B_20[3];
+ u32 COM0_C_SELECT;
+ u32 RESERVED_B_21[3];
+ struct hwd_viif_csc_reg com0_csc;
+ u32 COM0_OPORTALP;
+ u32 COM0_OPORTFMT;
+ u32 RESERVED_B_23[2];
+ u32 RESERVED_A_37;
+ u32 RESERVED_A_38;
+ u32 RESERVED_A_39;
+ u32 RESERVED_B_24[1];
+ u32 RESERVED_A_40;
+ u32 RESERVED_A_41;
+ u32 RESERVED_A_42;
+ u32 RESERVED_B_25[1];
+ u32 RESERVED_A_43;
+ u32 RESERVED_A_44;
+ u32 RESERVED_A_45;
+ u32 RESERVED_B_26[1];
+ u32 RESERVED_A_46;
+ u32 RESERVED_B_27[3];
+ u32 RESERVED_A_47;
+ u32 RESERVED_A_48;
+ u32 RESERVED_B_28[18];
+ u32 RESERVED_A_49;
+ u32 RESERVED_B_29[3];
+ u32 RESERVED_A_50;
+ u32 RESERVED_B_30[3];
+ u32 RESERVED_A_51;
+ u32 RESERVED_B_31[3];
+ u32 RESERVED_A_52;
+ u32 RESERVED_A_53;
+ u32 RESERVED_A_54;
+ u32 RESERVED_A_55;
+ u32 RESERVED_A_56;
+ u32 RESERVED_A_57;
+ u32 RESERVED_A_58;
+ u32 RESERVED_A_59;
+ u32 RESERVED_A_60;
+ u32 RESERVED_A_61;
+ u32 RESERVED_A_62;
+ u32 RESERVED_A_63;
+ u32 RESERVED_A_64;
+ u32 RESERVED_A_65;
+ u32 RESERVED_B_32[2];
+ u32 RESERVED_A_66;
+ u32 RESERVED_A_67;
+ u32 RESERVED_A_68;
+ u32 RESERVED_B_33[1];
+ u32 RESERVED_A_69;
+ u32 RESERVED_A_70;
+ u32 RESERVED_A_71;
+ u32 RESERVED_B_34[1];
+ u32 RESERVED_A_72;
+ u32 RESERVED_A_73;
+ u32 RESERVED_A_74;
+ u32 RESERVED_B_35[1];
+ u32 RESERVED_A_75;
+ u32 RESERVED_B_36[3];
+ u32 RESERVED_A_76;
+ u32 RESERVED_A_77;
+ u32 RESERVED_B_37[18];
+ u32 RESERVED_A_78;
+ u32 RESERVED_B_38[3];
+ u32 RESERVED_A_79;
+ u32 RESERVED_B_39[3];
+ u32 RESERVED_A_80;
+ u32 RESERVED_B_40[3];
+ u32 RESERVED_A_81;
+ u32 RESERVED_A_82;
+ u32 RESERVED_A_83;
+ u32 RESERVED_A_84;
+ u32 RESERVED_A_85;
+ u32 RESERVED_A_86;
+ u32 RESERVED_A_87;
+ u32 RESERVED_A_88;
+ u32 RESERVED_A_89;
+ u32 RESERVED_A_90;
+ u32 RESERVED_A_91;
+ u32 RESERVED_A_92;
+ u32 RESERVED_A_93;
+ u32 RESERVED_A_94;
+ u32 RESERVED_B_41[2];
+ u32 RESERVED_A_95;
+ u32 RESERVED_A_96;
+ u32 RESERVED_A_97;
+ u32 RESERVED_B_42[1];
+ u32 RESERVED_A_98;
+ u32 RESERVED_A_99;
+ u32 RESERVED_A_100;
+ u32 RESERVED_B_43[1];
+ u32 RESERVED_A_101;
+ u32 RESERVED_A_102;
+ u32 RESERVED_A_103;
+ u32 RESERVED_B_44[1];
+ u32 RESERVED_A_104;
+ u32 RESERVED_B_45[3];
+ u32 FN_M0;
+ u32 FN_M1;
+ u32 FN_M2;
+ u32 RESERVED_B_46[5];
+ u32 FN_SA0;
+ u32 FN_SA1;
+ u32 RESERVED_B_47[2];
+ u32 RESERVED_A_105;
+ u32 RESERVED_A_106;
+ u32 RESERVED_B_48[18];
+ u32 LBIST_STAT;
+ u32 MEM_ECC_DCLS_ALARM;
+ u32 RESERVED_B_49[30];
+ u32 DPHY_FREQRANGE;
+ u32 RESERVED_B_50[3];
+ u32 DPHY_LANE;
+ u32 RESERVED_B_51[59];
+ u32 INT_SOURCE;
+ u32 DPGM_VSYNC_SOURCE;
+ u32 RESERVED_B_52[23];
+ u32 RESERVED_A_107;
+ u32 RESERVED_A_108;
+ u32 RESERVED_B_53[6];
+ u32 RESERVED_A_109;
+ u32 RESERVED_A_110;
+ u32 RESERVED_A_111;
+ u32 RESERVED_B_54[1];
+ u32 RESERVED_A_112;
+ u32 RESERVED_B_55[35];
+ u32 RESERVED_A_113;
+ u32 RESERVED_B_56[54];
+ u32 RESERVED_A_114;
+ u32 RESERVED_B_57[3];
+ u32 RESERVED_A_115;
+ u32 RESERVED_A_116;
+ u32 RESERVED_A_117;
+ u32 RESERVED_B_58[1];
+ u32 RESERVED_A_118;
+ u32 RESERVED_B_59[3];
+ u32 RESERVED_A_119;
+ u32 RESERVED_A_120;
+ u32 RESERVED_A_121;
+ u32 RESERVED_A_122;
+ u32 RESERVED_A_123;
+ u32 RESERVED_A_124;
+ u32 RESERVED_A_125;
+ u32 RESERVED_A_126;
+ u32 RESERVED_A_127;
+ u32 RESERVED_A_128;
+ u32 RESERVED_A_129;
+ u32 RESERVED_A_130;
+ u32 RESERVED_B_60[4];
+ u32 RESERVED_A_131;
+ u32 RESERVED_A_132;
+ u32 RESERVED_A_133;
+ u32 RESERVED_B_61[33];
+ u32 RESERVED_A_134;
+ u32 RESERVED_A_135;
+ u32 RESERVED_B_62[18];
+ u32 RESERVED_A_136;
+ u32 RESERVED_B_63[3];
+ u32 RESERVED_A_137;
+ u32 RESERVED_B_64[3];
+ u32 RESERVED_A_138;
+ u32 RESERVED_B_65[3];
+ u32 RESERVED_A_139;
+ u32 RESERVED_A_140;
+ u32 RESERVED_A_141;
+ u32 RESERVED_A_142;
+ u32 RESERVED_A_143;
+ u32 RESERVED_A_144;
+ u32 RESERVED_A_145;
+ u32 RESERVED_A_146;
+ u32 RESERVED_A_147;
+ u32 RESERVED_A_148;
+ u32 RESERVED_A_149;
+ u32 RESERVED_A_150;
+ u32 RESERVED_A_151;
+ u32 RESERVED_A_152;
+ u32 RESERVED_B_66[2];
+ u32 RESERVED_A_153;
+ u32 RESERVED_A_154;
+ u32 RESERVED_A_155;
+ u32 RESERVED_B_67[1];
+ u32 RESERVED_A_156;
+ u32 RESERVED_A_157;
+ u32 RESERVED_A_158;
+ u32 RESERVED_B_68[1];
+ u32 RESERVED_A_159;
+ u32 RESERVED_A_160;
+ u32 RESERVED_A_161;
+ u32 RESERVED_B_69[1];
+ u32 RESERVED_A_162;
+ u32 RESERVED_B_70[3];
+ u32 RESERVED_A_163;
+ u32 RESERVED_A_164;
+ u32 RESERVED_B_71[18];
+ u32 RESERVED_A_165;
+ u32 RESERVED_B_72[3];
+ u32 RESERVED_A_166;
+ u32 RESERVED_B_73[3];
+ u32 RESERVED_A_167;
+ u32 RESERVED_B_74[3];
+ u32 RESERVED_A_168;
+ u32 RESERVED_A_169;
+ u32 RESERVED_A_170;
+ u32 RESERVED_A_171;
+ u32 RESERVED_A_172;
+ u32 RESERVED_A_173;
+ u32 RESERVED_A_174;
+ u32 RESERVED_A_175;
+ u32 RESERVED_A_176;
+ u32 RESERVED_A_177;
+ u32 RESERVED_A_178;
+ u32 RESERVED_A_179;
+ u32 RESERVED_A_180;
+ u32 RESERVED_A_181;
+ u32 RESERVED_B_75[2];
+ u32 RESERVED_A_182;
+ u32 RESERVED_A_183;
+ u32 RESERVED_A_184;
+ u32 RESERVED_B_76[1];
+ u32 RESERVED_A_185;
+ u32 RESERVED_A_186;
+ u32 RESERVED_A_187;
+ u32 RESERVED_B_77[1];
+ u32 RESERVED_A_188;
+ u32 RESERVED_A_189;
+ u32 RESERVED_A_190;
+ u32 RESERVED_B_78[1];
+ u32 RESERVED_A_191;
+ u32 RESERVED_B_79[3];
+ u32 RESERVED_A_192;
+ u32 RESERVED_A_193;
+ u32 RESERVED_B_80[18];
+ u32 RESERVED_A_194;
+ u32 RESERVED_B_81[3];
+ u32 RESERVED_A_195;
+ u32 RESERVED_B_82[3];
+ u32 RESERVED_A_196;
+ u32 RESERVED_B_83[3];
+ u32 RESERVED_A_197;
+ u32 RESERVED_A_198;
+ u32 RESERVED_A_199;
+ u32 RESERVED_A_200;
+ u32 RESERVED_A_201;
+ u32 RESERVED_A_202;
+ u32 RESERVED_A_203;
+ u32 RESERVED_A_204;
+ u32 RESERVED_A_205;
+ u32 RESERVED_A_206;
+ u32 RESERVED_A_207;
+ u32 RESERVED_A_208;
+ u32 RESERVED_A_209;
+ u32 RESERVED_A_210;
+ u32 RESERVED_B_84[2];
+ u32 RESERVED_A_211;
+ u32 RESERVED_A_212;
+ u32 RESERVED_A_213;
+ u32 RESERVED_B_85[1];
+ u32 RESERVED_A_214;
+ u32 RESERVED_A_215;
+ u32 RESERVED_A_216;
+ u32 RESERVED_B_86[1];
+ u32 RESERVED_A_217;
+ u32 RESERVED_A_218;
+ u32 RESERVED_A_219;
+ u32 RESERVED_B_87[1];
+ u32 RESERVED_A_220;
+ u32 RESERVED_B_88[130];
+ u32 RESERVED_A_221;
+};
+
+/**
+ * struct hwd_viif_vdm_table_group_reg - Registers for VIIF vdm control
+ */
+struct hwd_viif_vdm_table_group_reg {
+ u32 VDM_T_CFG;
+ u32 VDM_T_SRAM_BASE;
+ u32 VDM_T_SRAM_SIZE;
+ u32 RESERVED_A_4;
+};
+
+struct hwd_viif_vdm_table_port_reg {
+ u32 VDM_T_STADR;
+ u32 VDM_T_SIZE;
+};
+
+struct hwd_viif_vdm_read_port_reg {
+ u32 VDM_R_STADR;
+ u32 VDM_R_ENDADR;
+ u32 VDM_R_HEIGHT;
+ u32 VDM_R_PITCH;
+ u32 VDM_R_CFG0;
+ u32 RESERVED_A_11;
+ u32 VDM_R_SRAM_BASE;
+ u32 VDM_R_SRAM_SIZE;
+ u32 RESERVED_A_12;
+ u32 RESERVED_B_5[7];
+};
+
+struct hwd_viif_vdm_write_port_reg {
+ u32 VDM_W_STADR;
+ u32 VDM_W_ENDADR;
+ u32 VDM_W_HEIGHT;
+ u32 VDM_W_PITCH;
+ u32 VDM_W_CFG0;
+ u32 RESERVED_A_17;
+ u32 VDM_W_SRAM_BASE;
+ u32 VDM_W_SRAM_SIZE;
+ u32 RESERVED_A_18;
+ u32 RESERVED_B_8[7];
+};
+
+struct hwd_viif_vdm_write_port_buf_reg {
+ u32 VDM_W_STADR_BUF;
+ u32 RESERVED_A_120;
+ u32 RESERVED_A_121;
+ u32 RESERVED_A_122;
+ u32 RESERVED_A_123;
+ u32 RESERVED_A_124;
+ u32 RESERVED_B_20[2];
+};
+
+struct hwd_viif_vdm_reg {
+ u32 RESERVED_A_1;
+ u32 RESERVED_A_2;
+ u32 RESERVED_B_1[4];
+ u32 RESERVED_A_3;
+ u32 VDM_CFG;
+ u32 VDM_INT_MASK;
+ u32 RESERVED_B_2[3];
+ u32 VDM_R_ENABLE;
+ u32 VDM_W_ENABLE;
+ u32 VDM_T_ENABLE;
+ u32 VDM_ABORTSET;
+ struct hwd_viif_vdm_table_group_reg t_group[4];
+ u32 RESERVED_A_8;
+ u32 RESERVED_A_9;
+ u32 RESERVED_A_10;
+ u32 RESERVED_A_11;
+ u32 RESERVED_B_3[28];
+ struct hwd_viif_vdm_table_port_reg t_port[24];
+ u32 RESERVED_A_14;
+ u32 RESERVED_A_15;
+ u32 RESERVED_A_16;
+ u32 RESERVED_A_17;
+ u32 RESERVED_A_18;
+ u32 RESERVED_A_19;
+ u32 RESERVED_A_20;
+ u32 RESERVED_A_21;
+ u32 RESERVED_A_22;
+ u32 RESERVED_A_23;
+ u32 RESERVED_A_24;
+ u32 RESERVED_A_25;
+ u32 RESERVED_B_4[4];
+ struct hwd_viif_vdm_read_port_reg r_port[3];
+ u32 RESERVED_B_7[16];
+ struct hwd_viif_vdm_write_port_reg w_port[6];
+ u32 RESERVED_A_29;
+ u32 RESERVED_A_30;
+ u32 RESERVED_A_31;
+ u32 RESERVED_A_32;
+ u32 RESERVED_A_33;
+ u32 RESERVED_A_34;
+ u32 RESERVED_A_35;
+ u32 RESERVED_A_36;
+ u32 RESERVED_A_37;
+ u32 RESERVED_B_14[215];
+ u32 RESERVED_A_38;
+ u32 RESERVED_A_39;
+ u32 RESERVED_A_40;
+ u32 RESERVED_B_15[61];
+ u32 RESERVED_A_41;
+ u32 RESERVED_A_42;
+ u32 RESERVED_A_43;
+ u32 RESERVED_A_44;
+ u32 RESERVED_A_45;
+ u32 RESERVED_A_46;
+ u32 RESERVED_A_47;
+ u32 RESERVED_A_48;
+ u32 RESERVED_A_49;
+ u32 RESERVED_A_50;
+ u32 RESERVED_A_51;
+ u32 RESERVED_A_52;
+ u32 RESERVED_A_53;
+ u32 RESERVED_A_54;
+ u32 RESERVED_A_55;
+ u32 RESERVED_A_56;
+ u32 RESERVED_A_57;
+ u32 RESERVED_A_58;
+ u32 RESERVED_A_59;
+ u32 RESERVED_A_60;
+ u32 RESERVED_A_61;
+ u32 RESERVED_A_62;
+ u32 RESERVED_A_63;
+ u32 RESERVED_A_64;
+ u32 RESERVED_A_65;
+ u32 RESERVED_A_66;
+ u32 RESERVED_A_67;
+ u32 RESERVED_A_68;
+ u32 RESERVED_A_69;
+ u32 RESERVED_A_70;
+ u32 RESERVED_A_71;
+ u32 RESERVED_A_72;
+ u32 RESERVED_A_73;
+ u32 RESERVED_A_74;
+ u32 RESERVED_A_75;
+ u32 RESERVED_A_76;
+ u32 RESERVED_A_77;
+ u32 RESERVED_A_78;
+ u32 RESERVED_A_79;
+ u32 RESERVED_A_80;
+ u32 RESERVED_A_81;
+ u32 RESERVED_A_82;
+ u32 RESERVED_A_83;
+ u32 RESERVED_A_84;
+ u32 RESERVED_A_85;
+ u32 RESERVED_A_86;
+ u32 RESERVED_A_87;
+ u32 RESERVED_A_88;
+ u32 RESERVED_A_89;
+ u32 RESERVED_A_90;
+ u32 RESERVED_A_91;
+ u32 RESERVED_A_92;
+ u32 RESERVED_A_93;
+ u32 RESERVED_A_94;
+ u32 RESERVED_A_95;
+ u32 RESERVED_A_96;
+ u32 RESERVED_A_97;
+ u32 RESERVED_A_98;
+ u32 RESERVED_A_99;
+ u32 RESERVED_A_100;
+ u32 RESERVED_B_16[4];
+ u32 RESERVED_A_101;
+ u32 RESERVED_A_102;
+ u32 RESERVED_A_103;
+ u32 RESERVED_A_104;
+ u32 RESERVED_A_105;
+ u32 RESERVED_A_106;
+ u32 RESERVED_B_17[2];
+ u32 RESERVED_A_107;
+ u32 RESERVED_A_108;
+ u32 RESERVED_A_109;
+ u32 RESERVED_A_110;
+ u32 RESERVED_A_111;
+ u32 RESERVED_A_112;
+ u32 RESERVED_B_18[2];
+ u32 RESERVED_A_113;
+ u32 RESERVED_A_114;
+ u32 RESERVED_A_115;
+ u32 RESERVED_A_116;
+ u32 RESERVED_A_117;
+ u32 RESERVED_A_118;
+ u32 RESERVED_B_19[42];
+ struct hwd_viif_vdm_write_port_buf_reg w_port_buf[6];
+ u32 RESERVED_A_155;
+ u32 RESERVED_A_156;
+ u32 RESERVED_A_157;
+ u32 RESERVED_A_158;
+ u32 RESERVED_A_159;
+ u32 RESERVED_A_160;
+ u32 RESERVED_B_26[138];
+ u32 RESERVED_A_161;
+ u32 VDM_INT;
+ u32 RESERVED_A_162;
+ u32 RESERVED_A_163;
+ u32 VDM_R_STOP;
+ u32 VDM_W_STOP;
+ u32 VDM_R_RUN;
+ u32 VDM_W_RUN;
+ u32 VDM_T_RUN;
+ u32 RESERVED_B_27[7];
+ u32 RESERVED_A_164;
+ u32 RESERVED_A_165;
+ u32 RESERVED_A_166;
+ u32 RESERVED_A_167;
+ u32 RESERVED_B_28[12];
+ u32 RESERVED_A_168;
+ u32 RESERVED_A_169;
+ u32 RESERVED_A_170;
+ u32 RESERVED_A_171;
+ u32 RESERVED_A_172;
+ u32 RESERVED_B_29[27];
+ u32 RESERVED_A_173;
+ u32 RESERVED_A_174;
+ u32 RESERVED_A_175;
+ u32 RESERVED_A_176;
+ u32 RESERVED_A_177;
+ u32 RESERVED_A_178;
+ u32 RESERVED_B_30[10];
+ u32 RESERVED_A_179;
+ u32 RESERVED_A_180;
+ u32 RESERVED_A_181;
+ u32 RESERVED_A_182;
+ u32 RESERVED_A_183;
+ u32 RESERVED_A_184;
+ u32 RESERVED_A_185;
+ u32 RESERVED_A_186;
+ u32 RESERVED_A_187;
+ u32 RESERVED_A_188;
+ u32 RESERVED_A_189;
+ u32 RESERVED_A_190;
+ u32 RESERVED_A_191;
+ u32 RESERVED_A_192;
+ u32 RESERVED_B_31[33];
+ u32 RESERVED_A_193;
+};
+
+/**
+ * struct hwd_viif_l1isp_reg - Registers for VIIF L1ISP control
+ */
+struct hwd_viif_l1isp_reg {
+ u32 L1_SYSM_WIDTH;
+ u32 L1_SYSM_HEIGHT;
+ u32 L1_SYSM_START_COLOR;
+ u32 L1_SYSM_INPUT_MODE;
+ u32 RESERVED_A_1;
+ u32 L1_SYSM_YCOEF_R;
+ u32 L1_SYSM_YCOEF_G;
+ u32 L1_SYSM_YCOEF_B;
+ u32 L1_SYSM_INT_STAT;
+ u32 L1_SYSM_INT_MASKED_STAT;
+ u32 L1_SYSM_INT_MASK;
+ u32 RESERVED_A_2;
+ u32 RESERVED_A_3;
+ u32 RESERVED_A_4;
+ u32 RESERVED_B_1[2];
+ u32 L1_SYSM_AG_H;
+ u32 L1_SYSM_AG_M;
+ u32 L1_SYSM_AG_L;
+ u32 L1_SYSM_AG_PARAM_A;
+ u32 L1_SYSM_AG_PARAM_B;
+ u32 L1_SYSM_AG_PARAM_C;
+ u32 L1_SYSM_AG_PARAM_D;
+ u32 L1_SYSM_AG_SEL_HOBC;
+ u32 L1_SYSM_AG_SEL_ABPC;
+ u32 L1_SYSM_AG_SEL_RCNR;
+ u32 L1_SYSM_AG_SEL_LSSC;
+ u32 L1_SYSM_AG_SEL_MPRO;
+ u32 L1_SYSM_AG_SEL_VPRO;
+ u32 L1_SYSM_AG_CONT_HOBC01_EN;
+ u32 L1_SYSM_AG_CONT_HOBC2_EN;
+ u32 L1_SYSM_AG_CONT_ABPC01_EN;
+ u32 L1_SYSM_AG_CONT_ABPC2_EN;
+ u32 L1_SYSM_AG_CONT_RCNR01_EN;
+ u32 L1_SYSM_AG_CONT_RCNR2_EN;
+ u32 L1_SYSM_AG_CONT_LSSC_EN;
+ u32 L1_SYSM_AG_CONT_MPRO_EN;
+ u32 L1_SYSM_AG_CONT_VPRO_EN;
+ u32 L1_SYSM_CTXT;
+ u32 L1_SYSM_MAN_CTXT;
+ u32 RESERVED_A_5;
+ u32 RESERVED_B_2[7];
+ u32 RESERVED_A_6;
+ u32 L1_HDRE_SRCPOINT00;
+ u32 L1_HDRE_SRCPOINT01;
+ u32 L1_HDRE_SRCPOINT02;
+ u32 L1_HDRE_SRCPOINT03;
+ u32 L1_HDRE_SRCPOINT04;
+ u32 L1_HDRE_SRCPOINT05;
+ u32 L1_HDRE_SRCPOINT06;
+ u32 L1_HDRE_SRCPOINT07;
+ u32 L1_HDRE_SRCPOINT08;
+ u32 L1_HDRE_SRCPOINT09;
+ u32 L1_HDRE_SRCPOINT10;
+ u32 L1_HDRE_SRCPOINT11;
+ u32 L1_HDRE_SRCPOINT12;
+ u32 L1_HDRE_SRCPOINT13;
+ u32 L1_HDRE_SRCPOINT14;
+ u32 L1_HDRE_SRCPOINT15;
+ u32 L1_HDRE_SRCBASE00;
+ u32 L1_HDRE_SRCBASE01;
+ u32 L1_HDRE_SRCBASE02;
+ u32 L1_HDRE_SRCBASE03;
+ u32 L1_HDRE_SRCBASE04;
+ u32 L1_HDRE_SRCBASE05;
+ u32 L1_HDRE_SRCBASE06;
+ u32 L1_HDRE_SRCBASE07;
+ u32 L1_HDRE_SRCBASE08;
+ u32 L1_HDRE_SRCBASE09;
+ u32 L1_HDRE_SRCBASE10;
+ u32 L1_HDRE_SRCBASE11;
+ u32 L1_HDRE_SRCBASE12;
+ u32 L1_HDRE_SRCBASE13;
+ u32 L1_HDRE_SRCBASE14;
+ u32 L1_HDRE_SRCBASE15;
+ u32 L1_HDRE_SRCBASE16;
+ u32 L1_HDRE_RATIO00;
+ u32 L1_HDRE_RATIO01;
+ u32 L1_HDRE_RATIO02;
+ u32 L1_HDRE_RATIO03;
+ u32 L1_HDRE_RATIO04;
+ u32 L1_HDRE_RATIO05;
+ u32 L1_HDRE_RATIO06;
+ u32 L1_HDRE_RATIO07;
+ u32 L1_HDRE_RATIO08;
+ u32 L1_HDRE_RATIO09;
+ u32 L1_HDRE_RATIO10;
+ u32 L1_HDRE_RATIO11;
+ u32 L1_HDRE_RATIO12;
+ u32 L1_HDRE_RATIO13;
+ u32 L1_HDRE_RATIO14;
+ u32 L1_HDRE_RATIO15;
+ u32 L1_HDRE_RATIO16;
+ u32 L1_HDRE_DSTBASE00;
+ u32 L1_HDRE_DSTBASE01;
+ u32 L1_HDRE_DSTBASE02;
+ u32 L1_HDRE_DSTBASE03;
+ u32 L1_HDRE_DSTBASE04;
+ u32 L1_HDRE_DSTBASE05;
+ u32 L1_HDRE_DSTBASE06;
+ u32 L1_HDRE_DSTBASE07;
+ u32 L1_HDRE_DSTBASE08;
+ u32 L1_HDRE_DSTBASE09;
+ u32 L1_HDRE_DSTBASE10;
+ u32 L1_HDRE_DSTBASE11;
+ u32 L1_HDRE_DSTBASE12;
+ u32 L1_HDRE_DSTBASE13;
+ u32 L1_HDRE_DSTBASE14;
+ u32 L1_HDRE_DSTBASE15;
+ u32 L1_HDRE_DSTBASE16;
+ u32 L1_HDRE_DSTMAXVAL;
+ u32 RESERVED_B_3[11];
+ u32 L1_AEXP_ON;
+ u32 L1_AEXP_RESULT_AVE;
+ u32 RESERVED_A_7;
+ u32 L1_AEXP_FORCE_INTERRUPT_Y;
+ u32 L1_AEXP_START_X;
+ u32 L1_AEXP_START_Y;
+ u32 L1_AEXP_BLOCK_WIDTH;
+ u32 L1_AEXP_BLOCK_HEIGHT;
+ u32 L1_AEXP_WEIGHT_0;
+ u32 L1_AEXP_WEIGHT_1;
+ u32 L1_AEXP_WEIGHT_2;
+ u32 L1_AEXP_WEIGHT_3;
+ u32 L1_AEXP_WEIGHT_4;
+ u32 L1_AEXP_WEIGHT_5;
+ u32 L1_AEXP_WEIGHT_6;
+ u32 L1_AEXP_WEIGHT_7;
+ u32 L1_AEXP_SATUR_RATIO;
+ u32 L1_AEXP_BLACK_RATIO;
+ u32 L1_AEXP_SATUR_LEVEL;
+ u32 RESERVED_A_8;
+ /* [y][x] */
+ u32 L1_AEXP_AVE[8][8];
+ u32 L1_AEXP_SATUR_BLACK_PIXNUM;
+ u32 L1_AEXP_AVE4LINESY0;
+ u32 L1_AEXP_AVE4LINESY1;
+ u32 L1_AEXP_AVE4LINESY2;
+ u32 L1_AEXP_AVE4LINESY3;
+ u32 L1_AEXP_AVE4LINES0;
+ u32 L1_AEXP_AVE4LINES1;
+ u32 L1_AEXP_AVE4LINES2;
+ u32 L1_AEXP_AVE4LINES3;
+ u32 RESERVED_B_4[3];
+ u32 L1_IBUF_DEPTH;
+ u32 L1_IBUF_INPUT_ORDER;
+ u32 RESERVED_B_5[2];
+ u32 L1_SLIC_SRCBLACKLEVEL_GR;
+ u32 L1_SLIC_SRCBLACKLEVEL_R;
+ u32 L1_SLIC_SRCBLACKLEVEL_B;
+ u32 L1_SLIC_SRCBLACKLEVEL_GB;
+ u32 RESERVED_A_9;
+ u32 RESERVED_A_10;
+ u32 RESERVED_A_11;
+ u32 RESERVED_A_12;
+ u32 RESERVED_A_13;
+ u32 RESERVED_B_6[19];
+ u32 RESERVED_A_14;
+ u32 RESERVED_A_15;
+ u32 L1_ABPC012_AG_CONT;
+ u32 L1_ABPC012_STA_EN;
+ u32 L1_ABPC012_DYN_EN;
+ u32 L1_ABPC012_DYN_MODE;
+ u32 RESERVED_A_16;
+ u32 RESERVED_A_17;
+ u32 RESERVED_A_18;
+ u32 L1_ABPC0_RATIO_LIMIT;
+ u32 RESERVED_A_19;
+ u32 L1_ABPC0_DARK_LIMIT;
+ u32 L1_ABPC0_SN_COEF_W_AG_MIN;
+ u32 L1_ABPC0_SN_COEF_W_AG_MID;
+ u32 L1_ABPC0_SN_COEF_W_AG_MAX;
+ u32 L1_ABPC0_SN_COEF_W_TH_MIN;
+ u32 L1_ABPC0_SN_COEF_W_TH_MAX;
+ u32 L1_ABPC0_SN_COEF_B_AG_MIN;
+ u32 L1_ABPC0_SN_COEF_B_AG_MID;
+ u32 L1_ABPC0_SN_COEF_B_AG_MAX;
+ u32 L1_ABPC0_SN_COEF_B_TH_MIN;
+ u32 L1_ABPC0_SN_COEF_B_TH_MAX;
+ u32 RESERVED_A_20;
+ u32 L1_ABPC0_DETECT;
+ u32 L1_ABPC1_RATIO_LIMIT;
+ u32 RESERVED_A_21;
+ u32 L1_ABPC1_DARK_LIMIT;
+ u32 L1_ABPC1_SN_COEF_W_AG_MIN;
+ u32 L1_ABPC1_SN_COEF_W_AG_MID;
+ u32 L1_ABPC1_SN_COEF_W_AG_MAX;
+ u32 L1_ABPC1_SN_COEF_W_TH_MIN;
+ u32 L1_ABPC1_SN_COEF_W_TH_MAX;
+ u32 L1_ABPC1_SN_COEF_B_AG_MIN;
+ u32 L1_ABPC1_SN_COEF_B_AG_MID;
+ u32 L1_ABPC1_SN_COEF_B_AG_MAX;
+ u32 L1_ABPC1_SN_COEF_B_TH_MIN;
+ u32 L1_ABPC1_SN_COEF_B_TH_MAX;
+ u32 RESERVED_A_22;
+ u32 L1_ABPC1_DETECT;
+ u32 L1_ABPC2_RATIO_LIMIT;
+ u32 RESERVED_A_23;
+ u32 L1_ABPC2_DARK_LIMIT;
+ u32 L1_ABPC2_SN_COEF_W_AG_MIN;
+ u32 L1_ABPC2_SN_COEF_W_AG_MID;
+ u32 L1_ABPC2_SN_COEF_W_AG_MAX;
+ u32 L1_ABPC2_SN_COEF_W_TH_MIN;
+ u32 L1_ABPC2_SN_COEF_W_TH_MAX;
+ u32 L1_ABPC2_SN_COEF_B_AG_MIN;
+ u32 L1_ABPC2_SN_COEF_B_AG_MID;
+ u32 L1_ABPC2_SN_COEF_B_AG_MAX;
+ u32 L1_ABPC2_SN_COEF_B_TH_MIN;
+ u32 L1_ABPC2_SN_COEF_B_TH_MAX;
+ u32 RESERVED_A_24;
+ u32 L1_ABPC2_DETECT;
+ u32 RESERVED_B_7[42];
+ u32 RESERVED_A_25;
+ u32 L1_PWHB_H_GR;
+ u32 L1_PWHB_HR;
+ u32 L1_PWHB_HB;
+ u32 L1_PWHB_H_GB;
+ u32 L1_PWHB_M_GR;
+ u32 L1_PWHB_MR;
+ u32 L1_PWHB_MB;
+ u32 L1_PWHB_M_GB;
+ u32 L1_PWHB_L_GR;
+ u32 L1_PWHB_LR;
+ u32 L1_PWHB_LB;
+ u32 L1_PWHB_L_GB;
+ u32 L1_PWHB_DSTMAXVAL;
+ u32 RESERVED_B_8[18];
+ u32 L1_RCNR0_AG_CONT;
+ u32 RESERVED_A_26;
+ u32 L1_RCNR0_SW;
+ u32 L1_RCNR0_CNF_DARK_AG0;
+ u32 L1_RCNR0_CNF_DARK_AG1;
+ u32 L1_RCNR0_CNF_DARK_AG2;
+ u32 L1_RCNR0_CNF_RATIO_AG0;
+ u32 L1_RCNR0_CNF_RATIO_AG1;
+ u32 L1_RCNR0_CNF_RATIO_AG2;
+ u32 L1_RCNR0_CNF_CLIP_GAIN_R;
+ u32 L1_RCNR0_CNF_CLIP_GAIN_G;
+ u32 L1_RCNR0_CNF_CLIP_GAIN_B;
+ u32 L1_RCNR0_A1L_DARK_AG0;
+ u32 L1_RCNR0_A1L_DARK_AG1;
+ u32 L1_RCNR0_A1L_DARK_AG2;
+ u32 L1_RCNR0_A1L_RATIO_AG0;
+ u32 L1_RCNR0_A1L_RATIO_AG1;
+ u32 L1_RCNR0_A1L_RATIO_AG2;
+ u32 L1_RCNR0_INF_ZERO_CLIP;
+ u32 RESERVED_A_27;
+ u32 L1_RCNR0_MERGE_D2BLEND_AG0;
+ u32 L1_RCNR0_MERGE_D2BLEND_AG1;
+ u32 L1_RCNR0_MERGE_D2BLEND_AG2;
+ u32 L1_RCNR0_MERGE_BLACK;
+ u32 L1_RCNR0_MERGE_MINDIV;
+ u32 L1_RCNR0_HRY_TYPE;
+ u32 L1_RCNR0_ANF_BLEND_AG0;
+ u32 L1_RCNR0_ANF_BLEND_AG1;
+ u32 L1_RCNR0_ANF_BLEND_AG2;
+ u32 RESERVED_A_28;
+ u32 L1_RCNR0_LPF_THRESHOLD;
+ u32 L1_RCNR0_MERGE_HLBLEND_AG0;
+ u32 L1_RCNR0_MERGE_HLBLEND_AG1;
+ u32 L1_RCNR0_MERGE_HLBLEND_AG2;
+ u32 L1_RCNR0_GNR_SW;
+ u32 L1_RCNR0_GNR_RATIO;
+ u32 L1_RCNR0_GNR_WIDE_EN;
+ u32 L1_RCNR1_AG_CONT;
+ u32 RESERVED_A_29;
+ u32 L1_RCNR1_SW;
+ u32 L1_RCNR1_CNF_DARK_AG0;
+ u32 L1_RCNR1_CNF_DARK_AG1;
+ u32 L1_RCNR1_CNF_DARK_AG2;
+ u32 L1_RCNR1_CNF_RATIO_AG0;
+ u32 L1_RCNR1_CNF_RATIO_AG1;
+ u32 L1_RCNR1_CNF_RATIO_AG2;
+ u32 L1_RCNR1_CNF_CLIP_GAIN_R;
+ u32 L1_RCNR1_CNF_CLIP_GAIN_G;
+ u32 L1_RCNR1_CNF_CLIP_GAIN_B;
+ u32 L1_RCNR1_A1L_DARK_AG0;
+ u32 L1_RCNR1_A1L_DARK_AG1;
+ u32 L1_RCNR1_A1L_DARK_AG2;
+ u32 L1_RCNR1_A1L_RATIO_AG0;
+ u32 L1_RCNR1_A1L_RATIO_AG1;
+ u32 L1_RCNR1_A1L_RATIO_AG2;
+ u32 L1_RCNR1_INF_ZERO_CLIP;
+ u32 RESERVED_A_30;
+ u32 L1_RCNR1_MERGE_D2BLEND_AG0;
+ u32 L1_RCNR1_MERGE_D2BLEND_AG1;
+ u32 L1_RCNR1_MERGE_D2BLEND_AG2;
+ u32 L1_RCNR1_MERGE_BLACK;
+ u32 L1_RCNR1_MERGE_MINDIV;
+ u32 L1_RCNR1_HRY_TYPE;
+ u32 L1_RCNR1_ANF_BLEND_AG0;
+ u32 L1_RCNR1_ANF_BLEND_AG1;
+ u32 L1_RCNR1_ANF_BLEND_AG2;
+ u32 RESERVED_A_31;
+ u32 L1_RCNR1_LPF_THRESHOLD;
+ u32 L1_RCNR1_MERGE_HLBLEND_AG0;
+ u32 L1_RCNR1_MERGE_HLBLEND_AG1;
+ u32 L1_RCNR1_MERGE_HLBLEND_AG2;
+ u32 L1_RCNR1_GNR_SW;
+ u32 L1_RCNR1_GNR_RATIO;
+ u32 L1_RCNR1_GNR_WIDE_EN;
+ u32 L1_RCNR2_AG_CONT;
+ u32 RESERVED_A_32;
+ u32 L1_RCNR2_SW;
+ u32 L1_RCNR2_CNF_DARK_AG0;
+ u32 L1_RCNR2_CNF_DARK_AG1;
+ u32 L1_RCNR2_CNF_DARK_AG2;
+ u32 L1_RCNR2_CNF_RATIO_AG0;
+ u32 L1_RCNR2_CNF_RATIO_AG1;
+ u32 L1_RCNR2_CNF_RATIO_AG2;
+ u32 L1_RCNR2_CNF_CLIP_GAIN_R;
+ u32 L1_RCNR2_CNF_CLIP_GAIN_G;
+ u32 L1_RCNR2_CNF_CLIP_GAIN_B;
+ u32 L1_RCNR2_A1L_DARK_AG0;
+ u32 L1_RCNR2_A1L_DARK_AG1;
+ u32 L1_RCNR2_A1L_DARK_AG2;
+ u32 L1_RCNR2_A1L_RATIO_AG0;
+ u32 L1_RCNR2_A1L_RATIO_AG1;
+ u32 L1_RCNR2_A1L_RATIO_AG2;
+ u32 L1_RCNR2_INF_ZERO_CLIP;
+ u32 RESERVED_A_33;
+ u32 L1_RCNR2_MERGE_D2BLEND_AG0;
+ u32 L1_RCNR2_MERGE_D2BLEND_AG1;
+ u32 L1_RCNR2_MERGE_D2BLEND_AG2;
+ u32 L1_RCNR2_MERGE_BLACK;
+ u32 L1_RCNR2_MERGE_MINDIV;
+ u32 L1_RCNR2_HRY_TYPE;
+ u32 L1_RCNR2_ANF_BLEND_AG0;
+ u32 L1_RCNR2_ANF_BLEND_AG1;
+ u32 L1_RCNR2_ANF_BLEND_AG2;
+ u32 RESERVED_A_34;
+ u32 L1_RCNR2_LPF_THRESHOLD;
+ u32 L1_RCNR2_MERGE_HLBLEND_AG0;
+ u32 L1_RCNR2_MERGE_HLBLEND_AG1;
+ u32 L1_RCNR2_MERGE_HLBLEND_AG2;
+ u32 L1_RCNR2_GNR_SW;
+ u32 L1_RCNR2_GNR_RATIO;
+ u32 L1_RCNR2_GNR_WIDE_EN;
+ u32 RESERVED_B_9[49];
+ u32 RESERVED_A_35;
+ u32 L1_HDRS_HDRRATIO_M;
+ u32 L1_HDRS_HDRRATIO_L;
+ u32 L1_HDRS_HDRRATIO_E;
+ u32 RESERVED_A_36;
+ u32 RESERVED_A_37;
+ u32 L1_HDRS_BLENDEND_H;
+ u32 L1_HDRS_BLENDEND_M;
+ u32 L1_HDRS_BLENDEND_E;
+ u32 L1_HDRS_BLENDBEG_H;
+ u32 L1_HDRS_BLENDBEG_M;
+ u32 L1_HDRS_BLENDBEG_E;
+ u32 RESERVED_A_38;
+ u32 RESERVED_A_39;
+ u32 RESERVED_A_40;
+ u32 RESERVED_A_41;
+ u32 RESERVED_A_42;
+ u32 RESERVED_A_43;
+ u32 L1_HDRS_DG_H;
+ u32 L1_HDRS_DG_M;
+ u32 L1_HDRS_DG_L;
+ u32 L1_HDRS_DG_E;
+ u32 L1_HDRS_LEDMODE_ON;
+ u32 L1_HDRS_HDRMODE;
+ u32 RESERVED_A_44;
+ u32 RESERVED_A_45;
+ u32 RESERVED_A_46;
+ u32 L1_HDRS_DSTMAXVAL;
+ u32 RESERVED_B_10[4];
+ u32 L1_BLVC_SRCBLACKLEVEL_GR;
+ u32 L1_BLVC_SRCBLACKLEVEL_R;
+ u32 L1_BLVC_SRCBLACKLEVEL_B;
+ u32 L1_BLVC_SRCBLACKLEVELGB;
+ u32 L1_BLVC_MULTVAL_GR;
+ u32 L1_BLVC_MULTVAL_R;
+ u32 L1_BLVC_MULTVAL_B;
+ u32 L1_BLVC_MULTVAL_GB;
+ u32 L1_BLVC_DSTMAXVAL;
+ u32 RESERVED_A_47;
+ u32 RESERVED_A_48;
+ u32 RESERVED_A_49;
+ u32 RESERVED_A_50;
+ u32 RESERVED_A_51;
+ u32 RESERVED_A_52;
+ u32 RESERVED_B_11[17];
+ u32 L1_LSSC_EN;
+ u32 L1_LSSC_AG_CONT;
+ u32 RESERVED_A_53;
+ u32 RESERVED_A_54;
+ u32 L1_LSSC_PWHB_R_GAIN;
+ u32 L1_LSSC_PWHB_GR_GAIN;
+ u32 L1_LSSC_PWHB_GB_GAIN;
+ u32 L1_LSSC_PWHB_B_GAIN;
+ u32 L1_LSSC_PARA_EN;
+ u32 L1_LSSC_PARA_H_CENTER;
+ u32 L1_LSSC_PARA_V_CENTER;
+ u32 L1_LSSC_PARA_H_GAIN;
+ u32 L1_LSSC_PARA_V_GAIN;
+ u32 L1_LSSC_PARA_MGSEL2;
+ u32 L1_LSSC_PARA_MGSEL4;
+ u32 L1_LSSC_PARA_R_COEF_2D_H_L;
+ u32 L1_LSSC_PARA_R_COEF_2D_H_R;
+ u32 L1_LSSC_PARA_R_COEF_2D_V_U;
+ u32 L1_LSSC_PARA_R_COEF_2D_V_D;
+ u32 L1_LSSC_PARA_R_COEF_2D_HV_LU;
+ u32 L1_LSSC_PARA_R_COEF_2D_HV_RU;
+ u32 L1_LSSC_PARA_R_COEF_2D_HV_LD;
+ u32 L1_LSSC_PARA_R_COEF_2D_HV_RD;
+ u32 L1_LSSC_PARA_R_COEF_4D_H_L;
+ u32 L1_LSSC_PARA_R_COEF_4D_H_R;
+ u32 L1_LSSC_PARA_R_COEF_4D_V_U;
+ u32 L1_LSSC_PARA_R_COEF_4D_V_D;
+ u32 L1_LSSC_PARA_R_COEF_4D_HV_LU;
+ u32 L1_LSSC_PARA_R_COEF_4D_HV_RU;
+ u32 L1_LSSC_PARA_R_COEF_4D_HV_LD;
+ u32 L1_LSSC_PARA_R_COEF_4D_HV_RD;
+ u32 L1_LSSC_PARA_GR_COEF_2D_H_L;
+ u32 L1_LSSC_PARA_GR_COEF_2D_H_R;
+ u32 L1_LSSC_PARA_GR_COEF_2D_V_U;
+ u32 L1_LSSC_PARA_GR_COEF_2D_V_D;
+ u32 L1_LSSC_PARA_GR_COEF_2D_HV_LU;
+ u32 L1_LSSC_PARA_GR_COEF_2D_HV_RU;
+ u32 L1_LSSC_PARA_GR_COEF_2D_HV_LD;
+ u32 L1_LSSC_PARA_GR_COEF_2D_HV_RD;
+ u32 L1_LSSC_PARA_GR_COEF_4D_H_L;
+ u32 L1_LSSC_PARA_GR_COEF_4D_H_R;
+ u32 L1_LSSC_PARA_GR_COEF_4D_V_U;
+ u32 L1_LSSC_PARA_GR_COEF_4D_V_D;
+ u32 L1_LSSC_PARA_GR_COEF_4D_HV_LU;
+ u32 L1_LSSC_PARA_GR_COEF_4D_HV_RU;
+ u32 L1_LSSC_PARA_GR_COEF_4D_HV_LD;
+ u32 L1_LSSC_PARA_GR_COEF_4D_HV_RD;
+ u32 L1_LSSC_PARA_GB_COEF_2D_H_L;
+ u32 L1_LSSC_PARA_GB_COEF_2D_H_R;
+ u32 L1_LSSC_PARA_GB_COEF_2D_V_U;
+ u32 L1_LSSC_PARA_GB_COEF_2D_V_D;
+ u32 L1_LSSC_PARA_GB_COEF_2D_HV_LU;
+ u32 L1_LSSC_PARA_GB_COEF_2D_HV_RU;
+ u32 L1_LSSC_PARA_GB_COEF_2D_HV_LD;
+ u32 L1_LSSC_PARA_GB_COEF_2D_HV_RD;
+ u32 L1_LSSC_PARA_GB_COEF_4D_H_L;
+ u32 L1_LSSC_PARA_GB_COEF_4D_H_R;
+ u32 L1_LSSC_PARA_GB_COEF_4D_V_U;
+ u32 L1_LSSC_PARA_GB_COEF_4D_V_D;
+ u32 L1_LSSC_PARA_GB_COEF_4D_HV_LU;
+ u32 L1_LSSC_PARA_GB_COEF_4D_HV_RU;
+ u32 L1_LSSC_PARA_GB_COEF_4D_HV_LD;
+ u32 L1_LSSC_PARA_GB_COEF_4D_HV_RD;
+ u32 L1_LSSC_PARA_B_COEF_2D_H_L;
+ u32 L1_LSSC_PARA_B_COEF_2D_H_R;
+ u32 L1_LSSC_PARA_B_COEF_2D_V_U;
+ u32 L1_LSSC_PARA_B_COEF_2D_V_D;
+ u32 L1_LSSC_PARA_B_COEF_2D_HV_LU;
+ u32 L1_LSSC_PARA_B_COEF_2D_HV_RU;
+ u32 L1_LSSC_PARA_B_COEF_2D_HV_LD;
+ u32 L1_LSSC_PARA_B_COEF_2D_HV_RD;
+ u32 L1_LSSC_PARA_B_COEF_4D_H_L;
+ u32 L1_LSSC_PARA_B_COEF_4D_H_R;
+ u32 L1_LSSC_PARA_B_COEF_4D_V_U;
+ u32 L1_LSSC_PARA_B_COEF_4D_V_D;
+ u32 L1_LSSC_PARA_B_COEF_4D_HV_LU;
+ u32 L1_LSSC_PARA_B_COEF_4D_HV_RU;
+ u32 L1_LSSC_PARA_B_COEF_4D_HV_LD;
+ u32 L1_LSSC_PARA_B_COEF_4D_HV_RD;
+ u32 L1_LSSC_GRID_EN;
+ u32 L1_LSSC_GRID_H_CENTER;
+ u32 L1_LSSC_GRID_V_CENTER;
+ u32 L1_LSSC_GRID_H_SIZE;
+ u32 L1_LSSC_GRID_V_SIZE;
+ u32 L1_LSSC_GRID_MGSEL;
+ u32 RESERVED_B_12[11];
+ u32 L1_MPRO_SW;
+ u32 L1_MPRO_CONF;
+ u32 RESERVED_A_55;
+ u32 L1_MPRO_DST_MINVAL;
+ u32 L1_MPRO_DST_MAXVAL;
+ u32 L1_MPRO_AG_CONT;
+ u32 RESERVED_A_56;
+ u32 RESERVED_A_57;
+ u32 L1_MPRO_LM0_RMG_MIN;
+ u32 L1_MPRO_LM0_RMB_MIN;
+ u32 L1_MPRO_LM0_GMR_MIN;
+ u32 L1_MPRO_LM0_GMB_MIN;
+ u32 L1_MPRO_LM0_BMR_MIN;
+ u32 L1_MPRO_LM0_BMG_MIN;
+ u32 L1_MPRO_LM0_RMG_MAX;
+ u32 L1_MPRO_LM0_RMB_MAX;
+ u32 L1_MPRO_LM0_GMR_MAX;
+ u32 L1_MPRO_LM0_GMB_MAX;
+ u32 L1_MPRO_LM0_BMR_MAX;
+ u32 L1_MPRO_LM0_BMG_MAX;
+ u32 RESERVED_A_58;
+ u32 RESERVED_A_59;
+ u32 RESERVED_A_60;
+ u32 RESERVED_A_61;
+ u32 RESERVED_A_62;
+ u32 RESERVED_A_63;
+ u32 RESERVED_A_64;
+ u32 RESERVED_A_65;
+ u32 RESERVED_A_66;
+ u32 RESERVED_A_67;
+ u32 RESERVED_A_68;
+ u32 RESERVED_A_69;
+ u32 RESERVED_A_70;
+ u32 RESERVED_A_71;
+ u32 RESERVED_A_72;
+ u32 RESERVED_A_73;
+ u32 RESERVED_A_74;
+ u32 RESERVED_A_75;
+ u32 RESERVED_A_76;
+ u32 RESERVED_A_77;
+ u32 RESERVED_A_78;
+ u32 RESERVED_A_79;
+ u32 RESERVED_A_80;
+ u32 RESERVED_A_81;
+ u32 RESERVED_A_82;
+ u32 RESERVED_A_83;
+ u32 RESERVED_A_84;
+ u32 RESERVED_A_85;
+ u32 RESERVED_A_86;
+ u32 RESERVED_A_87;
+ u32 RESERVED_A_88;
+ u32 RESERVED_A_89;
+ u32 RESERVED_A_90;
+ u32 RESERVED_A_91;
+ u32 RESERVED_A_92;
+ u32 RESERVED_A_93;
+ u32 RESERVED_A_94;
+ u32 RESERVED_A_95;
+ u32 RESERVED_A_96;
+ u32 RESERVED_B_13[1];
+ u32 L1_MPRO_LCS_MODE;
+ u32 RESERVED_A_97;
+ u32 RESERVED_A_98;
+ u32 RESERVED_A_99;
+ u32 RESERVED_A_100;
+ u32 RESERVED_A_101;
+ u32 RESERVED_A_102;
+ u32 RESERVED_A_103;
+ u32 RESERVED_A_104;
+ u32 RESERVED_A_105;
+ u32 RESERVED_A_106;
+ u32 RESERVED_A_107;
+ u32 RESERVED_A_108;
+ u32 RESERVED_A_109;
+ u32 RESERVED_A_110;
+ u32 RESERVED_A_111;
+ u32 RESERVED_A_112;
+ u32 RESERVED_A_113;
+ u32 RESERVED_A_114;
+ u32 RESERVED_A_115;
+ u32 RESERVED_A_116;
+ u32 RESERVED_A_117;
+ u32 RESERVED_A_118;
+ u32 RESERVED_A_119;
+ u32 RESERVED_A_120;
+ u32 RESERVED_A_121;
+ u32 RESERVED_A_122;
+ u32 RESERVED_A_123;
+ u32 RESERVED_A_124;
+ u32 RESERVED_A_125;
+ u32 RESERVED_B_14[70];
+ u32 L1_VPRO_PGC_SW;
+ u32 RESERVED_A_126;
+ u32 L1_VPRO_YUVC_SW;
+ u32 L1_VPRO_YNR_SW;
+ u32 L1_VPRO_ETE_SW;
+ u32 L1_VPRO_CSUP_UVSUP_SW;
+ u32 L1_VPRO_CSUP_CORING_SW;
+ u32 L1_VPRO_BRIGHT_SW;
+ u32 L1_VPRO_LCNT_SW;
+ u32 L1_VPRO_NLCNT_SW;
+ u32 RESERVED_A_127;
+ u32 L1_VPRO_EDGE_SUP_SW;
+ u32 L1_VPRO_CNR_SW;
+ u32 L1_VPRO_AG_CONT;
+ u32 L1_VPRO_BLKADJ;
+ u32 L1_VPRO_GAM01P;
+ u32 L1_VPRO_GAM02P;
+ u32 L1_VPRO_GAM03P;
+ u32 L1_VPRO_GAM04P;
+ u32 L1_VPRO_GAM05P;
+ u32 L1_VPRO_GAM06P;
+ u32 L1_VPRO_GAM07P;
+ u32 L1_VPRO_GAM08P;
+ u32 L1_VPRO_GAM09P;
+ u32 L1_VPRO_GAM10P;
+ u32 L1_VPRO_GAM11P;
+ u32 L1_VPRO_GAM12P;
+ u32 L1_VPRO_GAM13P;
+ u32 L1_VPRO_GAM14P;
+ u32 L1_VPRO_GAM15P;
+ u32 L1_VPRO_GAM16P;
+ u32 L1_VPRO_GAM17P;
+ u32 L1_VPRO_GAM18P;
+ u32 L1_VPRO_GAM19P;
+ u32 L1_VPRO_GAM20P;
+ u32 L1_VPRO_GAM21P;
+ u32 L1_VPRO_GAM22P;
+ u32 L1_VPRO_GAM23P;
+ u32 L1_VPRO_GAM24P;
+ u32 L1_VPRO_GAM25P;
+ u32 L1_VPRO_GAM26P;
+ u32 L1_VPRO_GAM27P;
+ u32 L1_VPRO_GAM28P;
+ u32 L1_VPRO_GAM29P;
+ u32 L1_VPRO_GAM30P;
+ u32 L1_VPRO_GAM31P;
+ u32 L1_VPRO_GAM32P;
+ u32 L1_VPRO_GAM33P;
+ u32 L1_VPRO_GAM34P;
+ u32 L1_VPRO_GAM35P;
+ u32 L1_VPRO_GAM36P;
+ u32 L1_VPRO_GAM37P;
+ u32 L1_VPRO_GAM38P;
+ u32 L1_VPRO_GAM39P;
+ u32 L1_VPRO_GAM40P;
+ u32 L1_VPRO_GAM41P;
+ u32 L1_VPRO_GAM42P;
+ u32 L1_VPRO_GAM43P;
+ u32 L1_VPRO_GAM44P;
+ u32 L1_VPRO_CB_MAT;
+ u32 L1_VPRO_CR_MAT;
+ u32 L1_VPRO_BRIGHT;
+ u32 L1_VPRO_LCONT_LEV;
+ u32 L1_VPRO_BLK_KNEE;
+ u32 L1_VPRO_WHT_KNEE;
+ u32 L1_VPRO_BLK_CONT0;
+ u32 L1_VPRO_BLK_CONT1;
+ u32 L1_VPRO_BLK_CONT2;
+ u32 L1_VPRO_WHT_CONT0;
+ u32 L1_VPRO_WHT_CONT1;
+ u32 L1_VPRO_WHT_CONT2;
+ u32 RESERVED_A_128;
+ u32 RESERVED_A_129;
+ u32 RESERVED_A_130;
+ u32 RESERVED_A_131;
+ u32 RESERVED_A_132;
+ u32 RESERVED_A_133;
+ u32 L1_VPRO_YNR_GAIN_MIN;
+ u32 L1_VPRO_YNR_GAIN_MAX;
+ u32 L1_VPRO_YNR_LIM_MIN;
+ u32 L1_VPRO_YNR_LIM_MAX;
+ u32 L1_VPRO_ETE_GAIN_MIN;
+ u32 L1_VPRO_ETE_GAIN_MAX;
+ u32 L1_VPRO_ETE_LIM_MIN;
+ u32 L1_VPRO_ETE_LIM_MAX;
+ u32 L1_VPRO_ETE_CORING_MIN;
+ u32 L1_VPRO_ETE_CORING_MAX;
+ u32 L1_VPRO_CB_GAIN;
+ u32 L1_VPRO_CR_GAIN;
+ u32 L1_VPRO_CBR_MGAIN_MIN;
+ u32 L1_VPRO_CB_P_GAIN_MAX;
+ u32 L1_VPRO_CB_M_GAIN_MAX;
+ u32 L1_VPRO_CR_P_GAIN_MAX;
+ u32 L1_VPRO_CR_M_GAIN_MAX;
+ u32 L1_VPRO_CSUP_CORING_LV_MIN;
+ u32 L1_VPRO_CSUP_CORING_LV_MAX;
+ u32 L1_VPRO_CSUP_CORING_GAIN_MIN;
+ u32 L1_VPRO_CSUP_CORING_GAIN_MAX;
+ u32 L1_VPRO_CSUP_BK_SLV;
+ u32 L1_VPRO_CSUP_BK_MP;
+ u32 L1_VPRO_CSUP_BLACK;
+ u32 L1_VPRO_CSUP_WH_SLV;
+ u32 L1_VPRO_CSUP_WH_MP;
+ u32 L1_VPRO_CSUP_WHITE;
+ u32 L1_VPRO_EDGE_SUP_GAIN;
+ u32 L1_VPRO_EDGE_SUP_LIM;
+ u32 RESERVED_B_15[22];
+ u32 L1_AWHB_SW;
+ u32 RESERVED_A_134;
+ u32 L1_AWHB_WBMRG;
+ u32 L1_AWHB_WBMGG;
+ u32 L1_AWHB_WBMBG;
+ u32 L1_AWHB_GATE_CONF0;
+ u32 L1_AWHB_GATE_CONF1;
+ u32 L1_AWHB_AREA_HSIZE;
+ u32 L1_AWHB_AREA_VSIZE;
+ u32 L1_AWHB_AREA_HOFS;
+ u32 L1_AWHB_AREA_VOFS;
+ u32 L1_AWHB_AREA_MASKH;
+ u32 L1_AWHB_AREA_MASKL;
+ u32 L1_AWHB_SQ_CONF;
+ u32 L1_AWHB_YGATEH;
+ u32 L1_AWHB_YGATEL;
+ u32 RESERVED_A_135;
+ u32 RESERVED_A_136;
+ u32 L1_AWHB_BYCUT0P;
+ u32 L1_AWHB_BYCUT0N;
+ u32 L1_AWHB_RYCUT0P;
+ u32 L1_AWHB_RYCUT0N;
+ u32 L1_AWHB_RBCUT0H;
+ u32 L1_AWHB_RBCUT0L;
+ u32 RESERVED_A_137;
+ u32 RESERVED_A_138;
+ u32 RESERVED_A_139;
+ u32 RESERVED_A_140;
+ u32 RESERVED_A_141;
+ u32 RESERVED_A_142;
+ u32 L1_AWHB_BYCUT1H;
+ u32 L1_AWHB_BYCUT1L;
+ u32 L1_AWHB_RYCUT1H;
+ u32 L1_AWHB_RYCUT1L;
+ u32 L1_AWHB_BYCUT2H;
+ u32 L1_AWHB_BYCUT2L;
+ u32 L1_AWHB_RYCUT2H;
+ u32 L1_AWHB_RYCUT2L;
+ u32 L1_AWHB_BYCUT3H;
+ u32 L1_AWHB_BYCUT3L;
+ u32 L1_AWHB_RYCUT3H;
+ u32 L1_AWHB_RYCUT3L;
+ u32 L1_AWHB_AWBSFTU;
+ u32 L1_AWHB_AWBSFTV;
+ u32 L1_AWHB_AWBSPD;
+ u32 L1_AWHB_AWBULV;
+ u32 L1_AWHB_AWBVLV;
+ u32 L1_AWHB_AWBWAIT;
+ u32 L1_AWHB_AWBONDOT;
+ u32 L1_AWHB_AWBFZTIM;
+ u32 L1_AWHB_WBGRMAX;
+ u32 L1_AWHB_WBGRMIN;
+ u32 L1_AWHB_WBGBMAX;
+ u32 L1_AWHB_WBGBMIN;
+ u32 RESERVED_A_143;
+ u32 RESERVED_A_144;
+ u32 RESERVED_A_145;
+ u32 RESERVED_A_146;
+ u32 RESERVED_A_147;
+ u32 RESERVED_A_148;
+ u32 RESERVED_A_149;
+ u32 RESERVED_A_150;
+ u32 RESERVED_A_151;
+ u32 RESERVED_A_152;
+ u32 RESERVED_A_153;
+ u32 RESERVED_A_154;
+ u32 RESERVED_A_155;
+ u32 L1_AWHB_AVE_USIG;
+ u32 L1_AWHB_AVE_VSIG;
+ u32 L1_AWHB_NUM_UVON;
+ u32 L1_AWHB_AWBGAINR;
+ u32 L1_AWHB_AWBGAING;
+ u32 L1_AWHB_AWBGAINB;
+ u32 RESERVED_A_156;
+ u32 RESERVED_A_157;
+ u32 RESERVED_A_158;
+ u32 L1_AWHB_R_CTR_STOP;
+ u32 RESERVED_A_159;
+ u32 RESERVED_B_16[2];
+ u32 L1_HOBC_EN;
+ u32 L1_HOBC_MARGIN;
+ u32 L1_HOBC01_AG_CONT;
+ u32 L1_HOBC2_AG_CONT;
+ u32 L1_HOBC0_LOB_REFLV_GR;
+ u32 L1_HOBC0_LOB_WIDTH_GR;
+ u32 L1_HOBC0_LOB_REFLV_R;
+ u32 L1_HOBC0_LOB_WIDTH_R;
+ u32 L1_HOBC0_LOB_REFLV_B;
+ u32 L1_HOBC0_LOB_WIDTH_B;
+ u32 L1_HOBC0_LOB_REFLV_GB;
+ u32 L1_HOBC0_LOB_WIDTH_GB;
+ u32 L1_HOBC1_LOB_REFLV_GR;
+ u32 L1_HOBC1_LOB_WIDTH_GR;
+ u32 L1_HOBC1_LOB_REFLV_R;
+ u32 L1_HOBC1_LOB_WIDTH_R;
+ u32 L1_HOBC1_LOB_REFLV_B;
+ u32 L1_HOBC1_LOB_WIDTH_B;
+ u32 L1_HOBC1_LOB_REFLV_GB;
+ u32 L1_HOBC1_LOB_WIDTH_GB;
+ u32 L1_HOBC2_LOB_REFLV_GR;
+ u32 L1_HOBC2_LOB_WIDTH_GR;
+ u32 L1_HOBC2_LOB_REFLV_R;
+ u32 L1_HOBC2_LOB_WIDTH_R;
+ u32 L1_HOBC2_LOB_REFLV_B;
+ u32 L1_HOBC2_LOB_WIDTH_B;
+ u32 L1_HOBC2_LOB_REFLV_GB;
+ u32 L1_HOBC2_LOB_WIDTH_GB;
+ u32 L1_HOBC0_SRC_BLKLV_GR;
+ u32 L1_HOBC0_SRC_BLKLV_R;
+ u32 L1_HOBC0_SRC_BLKLV_B;
+ u32 L1_HOBC0_SRC_BLKLV_GB;
+ u32 L1_HOBC1_SRC_BLKLV_GR;
+ u32 L1_HOBC1_SRC_BLKLV_R;
+ u32 L1_HOBC1_SRC_BLKLV_B;
+ u32 L1_HOBC1_SRC_BLKLV_GB;
+ u32 L1_HOBC2_SRC_BLKLV_GR;
+ u32 L1_HOBC2_SRC_BLKLV_R;
+ u32 L1_HOBC2_SRC_BLKLV_B;
+ u32 L1_HOBC2_SRC_BLKLV_GB;
+ u32 RESERVED_A_160;
+ u32 RESERVED_A_161;
+ u32 RESERVED_A_162;
+ u32 RESERVED_A_163;
+ u32 RESERVED_A_164;
+ u32 RESERVED_A_165;
+ u32 L1_HOBC_MAX_VAL;
+ u32 RESERVED_B_17[33];
+ u32 L1_HDRC_EN;
+ u32 L1_HDRC_THR_SFT_AMT;
+ u32 RESERVED_A_166;
+ u32 L1_HDRC_RATIO;
+ u32 RESERVED_A_167;
+ u32 RESERVED_A_168;
+ u32 RESERVED_A_169;
+ u32 L1_HDRC_PT_RATIO;
+ u32 L1_HDRC_PT_BLEND;
+ u32 L1_HDRC_PT_BLEND2;
+ u32 L1_HDRC_PT_SAT;
+ u32 L1_HDRC_TN_TYPE;
+ u32 L1_HDRC_TNP_MAX;
+ u32 L1_HDRC_TNP_MAG;
+ u32 L1_HDRC_TNP_FB_SMTH_MAX0;
+ u32 L1_HDRC_TNP_FB_SMTH_MAX1;
+ u32 L1_HDRC_TNP_FB_SMTH_MAX2;
+ u32 L1_HDRC_TNP_FB_SMTH_MAX3;
+ u32 L1_HDRC_TNP_FIL0;
+ u32 L1_HDRC_TNP_FIL1;
+ u32 L1_HDRC_TNP_FIL2;
+ u32 L1_HDRC_TNP_FIL3;
+ u32 L1_HDRC_TNP_FIL4;
+ u32 L1_HDRC_UTN_TBL0;
+ u32 L1_HDRC_UTN_TBL1;
+ u32 L1_HDRC_UTN_TBL2;
+ u32 L1_HDRC_UTN_TBL3;
+ u32 L1_HDRC_UTN_TBL4;
+ u32 L1_HDRC_UTN_TBL5;
+ u32 L1_HDRC_UTN_TBL6;
+ u32 L1_HDRC_UTN_TBL7;
+ u32 L1_HDRC_UTN_TBL8;
+ u32 L1_HDRC_UTN_TBL9;
+ u32 L1_HDRC_UTN_TBL10;
+ u32 L1_HDRC_UTN_TBL11;
+ u32 L1_HDRC_UTN_TBL12;
+ u32 L1_HDRC_UTN_TBL13;
+ u32 L1_HDRC_UTN_TBL14;
+ u32 L1_HDRC_UTN_TBL15;
+ u32 L1_HDRC_UTN_TBL16;
+ u32 L1_HDRC_UTN_TBL17;
+ u32 L1_HDRC_UTN_TBL18;
+ u32 L1_HDRC_UTN_TBL19;
+ u32 L1_HDRC_FLR_VAL;
+ u32 L1_HDRC_FLR_ADP;
+ u32 RESERVED_A_170;
+ u32 RESERVED_A_171;
+ u32 RESERVED_A_172;
+ u32 RESERVED_A_173;
+ u32 RESERVED_A_174;
+ u32 RESERVED_A_175;
+ u32 RESERVED_A_176;
+ u32 RESERVED_A_177;
+ u32 RESERVED_A_178;
+ u32 RESERVED_A_179;
+ u32 RESERVED_A_180;
+ u32 RESERVED_A_181;
+ u32 RESERVED_A_182;
+ u32 RESERVED_A_183;
+ u32 L1_HDRC_YBR_OFF;
+ u32 L1_HDRC_ORGY_BLEND;
+ u32 RESERVED_A_184;
+ u32 RESERVED_A_185;
+ u32 RESERVED_A_186;
+ u32 L1_HDRC_MAR_TOP;
+ u32 L1_HDRC_MAR_LEFT;
+ u32 RESERVED_A_187;
+ u32 RESERVED_A_188;
+ u32 RESERVED_B_18[28];
+ u32 L1_HIST_EN;
+ u32 L1_HIST_MODE;
+ u32 L1_HIST_BLOCK_OFST;
+ u32 L1_HIST_BLOCK_SIZE;
+ u32 L1_HIST_BLOCK_NUM;
+ u32 L1_HIST_BLOCK_STEP;
+ u32 L1_HIST_LINEAR_SFT;
+ u32 L1_HIST_MULT_A_R;
+ u32 L1_HIST_ADD_A_R;
+ u32 L1_HIST_MULT_B_R;
+ u32 L1_HIST_ADD_B_R;
+ u32 L1_HIST_MULT_A_G;
+ u32 L1_HIST_ADD_A_G;
+ u32 L1_HIST_MULT_B_G;
+ u32 L1_HIST_ADD_B_G;
+ u32 L1_HIST_MULT_A_B;
+ u32 L1_HIST_ADD_A_B;
+ u32 L1_HIST_MULT_B_B;
+ u32 L1_HIST_ADD_B_B;
+ u32 L1_HIST_MULT_A_Y;
+ u32 L1_HIST_ADD_A_Y;
+ u32 L1_HIST_MULT_B_Y;
+ u32 L1_HIST_ADD_B_Y;
+ u32 RESERVED_B_19[201];
+ u32 L1_CRGBF_ACC_CONF;
+ u32 L1_CRGBF_TRN_M_RUN;
+ u32 L1_CRGBF_TRN_M_CONF;
+ u32 L1_CRGBF_TRN_A_CONF;
+ u32 L1_CRGBF_TRN_STAT_CLR;
+ u32 L1_CRGBF_TRN_STAT;
+ u32 L1_CRGBF_INT_STAT;
+ u32 L1_CRGBF_INT_MASK;
+ u32 L1_CRGBF_INT_MASKED_STAT;
+ u32 L1_CRGBF_TRN_WBADDR;
+ u32 L1_CRGBF_TRN_WEADDR;
+ u32 L1_CRGBF_TRN_RBADDR;
+ u32 L1_CRGBF_TRN_READDR;
+ u32 L1_CRGBF_ISP_INT;
+ u32 L1_CRGBF_ISP_INT_MASK;
+ u32 L1_CRGBF_ISP_INT_MASKED_STAT;
+ u32 RESERVED_A_189;
+ u32 RESERVED_B_20[47];
+ u32 L1_VLATCH_SYSM_WIDTH;
+ u32 L1_VLATCH_SYSM_HEIGHT;
+ u32 L1_VLATCH_SYSM_START_COLOR;
+ u32 L1_VLATCH_SYSM_INPUT_MODE;
+ u32 RESERVED_A_190;
+ u32 L1_VLATCH_SYSM_YCOEF_R;
+ u32 L1_VLATCH_SYSM_YCOEF_G;
+ u32 L1_VLATCH_SYSM_YCOEF_B;
+ u32 RESERVED_A_191;
+ u32 RESERVED_A_192;
+ u32 RESERVED_A_193;
+ u32 RESERVED_A_194;
+ u32 RESERVED_A_195;
+ u32 RESERVED_A_196;
+ u32 RESERVED_B_21[2];
+ u32 L1_VLATCH_SYSM_AG_H;
+ u32 L1_VLATCH_SYSM_AG_M;
+ u32 L1_VLATCH_SYSM_AG_L;
+ u32 L1_VLATCH_SYSM_AG_PARAM_A;
+ u32 L1_VLATCH_SYSM_AG_PARAM_B;
+ u32 L1_VLATCH_SYSM_AG_PARAM_C;
+ u32 L1_VLATCH_SYSM_AG_PARAM_D;
+ u32 L1_VLATCH_SYSM_AG_SEL_HOBC;
+ u32 L1_VLATCH_SYSM_AG_SEL_ABPC;
+ u32 L1_VLATCH_SYSM_AG_SEL_RCNR;
+ u32 L1_VLATCH_SYSM_AG_SEL_LSSC;
+ u32 L1_VLATCH_SYSM_AG_SEL_MPRO;
+ u32 L1_VLATCH_SYSM_AG_SEL_VPRO;
+ u32 L1_VLATCH_SYSM_AG_CONT_HOBC01_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_HOBC2_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_ABPC01_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_ABPC2_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_RCNR01_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_RCNR2_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_LSSC_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_MPRO_EN;
+ u32 L1_VLATCH_SYSM_AG_CONT_VPRO_EN;
+ u32 RESERVED_A_197;
+ u32 L1_VLATCH_SYSM_MAN_CTXT;
+ u32 RESERVED_A_198;
+ u32 RESERVED_B_22[7];
+ u32 RESERVED_A_199;
+ u32 L1_VLATCH_HDRE_SRCPOINT00;
+ u32 L1_VLATCH_HDRE_SRCPOINT01;
+ u32 L1_VLATCH_HDRE_SRCPOINT02;
+ u32 L1_VLATCH_HDRE_SRCPOINT03;
+ u32 L1_VLATCH_HDRE_SRCPOINT04;
+ u32 L1_VLATCH_HDRE_SRCPOINT05;
+ u32 L1_VLATCH_HDRE_SRCPOINT06;
+ u32 L1_VLATCH_HDRE_SRCPOINT07;
+ u32 L1_VLATCH_HDRE_SRCPOINT08;
+ u32 L1_VLATCH_HDRE_SRCPOINT09;
+ u32 L1_VLATCH_HDRE_SRCPOINT10;
+ u32 L1_VLATCH_HDRE_SRCPOINT11;
+ u32 L1_VLATCH_HDRE_SRCPOINT12;
+ u32 L1_VLATCH_HDRE_SRCPOINT13;
+ u32 L1_VLATCH_HDRE_SRCPOINT14;
+ u32 L1_VLATCH_HDRE_SRCPOINT15;
+ u32 L1_VLATCH_HDRE_SRCBASE00;
+ u32 L1_VLATCH_HDRE_SRCBASE01;
+ u32 L1_VLATCH_HDRE_SRCBASE02;
+ u32 L1_VLATCH_HDRE_SRCBASE03;
+ u32 L1_VLATCH_HDRE_SRCBASE04;
+ u32 L1_VLATCH_HDRE_SRCBASE05;
+ u32 L1_VLATCH_HDRE_SRCBASE06;
+ u32 L1_VLATCH_HDRE_SRCBASE07;
+ u32 L1_VLATCH_HDRE_SRCBASE08;
+ u32 L1_VLATCH_HDRE_SRCBASE09;
+ u32 L1_VLATCH_HDRE_SRCBASE10;
+ u32 L1_VLATCH_HDRE_SRCBASE11;
+ u32 L1_VLATCH_HDRE_SRCBASE12;
+ u32 L1_VLATCH_HDRE_SRCBASE13;
+ u32 L1_VLATCH_HDRE_SRCBASE14;
+ u32 L1_VLATCH_HDRE_SRCBASE15;
+ u32 L1_VLATCH_HDRE_SRCBASE16;
+ u32 L1_VLATCH_HDRE_RATIO00;
+ u32 L1_VLATCH_HDRE_RATIO01;
+ u32 L1_VLATCH_HDRE_RATIO02;
+ u32 L1_VLATCH_HDRE_RATIO03;
+ u32 L1_VLATCH_HDRE_RATIO04;
+ u32 L1_VLATCH_HDRE_RATIO05;
+ u32 L1_VLATCH_HDRE_RATIO06;
+ u32 L1_VLATCH_HDRE_RATIO07;
+ u32 L1_VLATCH_HDRE_RATIO08;
+ u32 L1_VLATCH_HDRE_RATIO09;
+ u32 L1_VLATCH_HDRE_RATIO10;
+ u32 L1_VLATCH_HDRE_RATIO11;
+ u32 L1_VLATCH_HDRE_RATIO12;
+ u32 L1_VLATCH_HDRE_RATIO13;
+ u32 L1_VLATCH_HDRE_RATIO14;
+ u32 L1_VLATCH_HDRE_RATIO15;
+ u32 L1_VLATCH_HDRE_RATIO16;
+ u32 L1_VLATCH_HDRE_DSTBASE00;
+ u32 L1_VLATCH_HDRE_DSTBASE01;
+ u32 L1_VLATCH_HDRE_DSTBASE02;
+ u32 L1_VLATCH_HDRE_DSTBASE03;
+ u32 L1_VLATCH_HDRE_DSTBASE04;
+ u32 L1_VLATCH_HDRE_DSTBASE05;
+ u32 L1_VLATCH_HDRE_DSTBASE06;
+ u32 L1_VLATCH_HDRE_DSTBASE07;
+ u32 L1_VLATCH_HDRE_DSTBASE08;
+ u32 L1_VLATCH_HDRE_DSTBASE09;
+ u32 L1_VLATCH_HDRE_DSTBASE10;
+ u32 L1_VLATCH_HDRE_DSTBASE11;
+ u32 L1_VLATCH_HDRE_DSTBASE12;
+ u32 L1_VLATCH_HDRE_DSTBASE13;
+ u32 L1_VLATCH_HDRE_DSTBASE14;
+ u32 L1_VLATCH_HDRE_DSTBASE15;
+ u32 L1_VLATCH_HDRE_DSTBASE16;
+ u32 L1_VLATCH_HDRE_DSTMAXVAL;
+ u32 RESERVED_B_23[11];
+ u32 L1_VLATCH_AEXP_ON;
+ u32 RESERVED_A_200;
+ u32 RESERVED_A_201;
+ u32 L1_VLATCH_AEXP_FORCE_INTERRUPT_Y;
+ u32 L1_VLATCH_AEXP_START_X;
+ u32 L1_VLATCH_AEXP_START_Y;
+ u32 L1_VLATCH_AEXP_BLOCK_WIDTH;
+ u32 L1_VLATCH_AEXP_BLOCK_HEIGHT;
+ u32 L1_VLATCH_AEXP_WEIGHT_0;
+ u32 L1_VLATCH_AEXP_WEIGHT_1;
+ u32 L1_VLATCH_AEXP_WEIGHT_2;
+ u32 L1_VLATCH_AEXP_WEIGHT_3;
+ u32 L1_VLATCH_AEXP_WEIGHT_4;
+ u32 L1_VLATCH_AEXP_WEIGHT_5;
+ u32 L1_VLATCH_AEXP_WEIGHT_6;
+ u32 L1_VLATCH_AEXP_WEIGHT_7;
+ u32 L1_VLATCH_AEXP_SATUR_RATIO;
+ u32 L1_VLATCH_AEXP_BLACK_RATIO;
+ u32 L1_VLATCH_AEXP_SATUR_LEVEL;
+ u32 RESERVED_A_202;
+ u32 RESERVED_A_203;
+ u32 RESERVED_A_204;
+ u32 RESERVED_A_205;
+ u32 RESERVED_A_206;
+ u32 RESERVED_A_207;
+ u32 RESERVED_A_208;
+ u32 RESERVED_A_209;
+ u32 RESERVED_A_210;
+ u32 RESERVED_A_211;
+ u32 RESERVED_A_212;
+ u32 RESERVED_A_213;
+ u32 RESERVED_A_214;
+ u32 RESERVED_A_215;
+ u32 RESERVED_A_216;
+ u32 RESERVED_A_217;
+ u32 RESERVED_A_218;
+ u32 RESERVED_A_219;
+ u32 RESERVED_A_220;
+ u32 RESERVED_A_221;
+ u32 RESERVED_A_222;
+ u32 RESERVED_A_223;
+ u32 RESERVED_A_224;
+ u32 RESERVED_A_225;
+ u32 RESERVED_A_226;
+ u32 RESERVED_A_227;
+ u32 RESERVED_A_228;
+ u32 RESERVED_A_229;
+ u32 RESERVED_A_230;
+ u32 RESERVED_A_231;
+ u32 RESERVED_A_232;
+ u32 RESERVED_A_233;
+ u32 RESERVED_A_234;
+ u32 RESERVED_A_235;
+ u32 RESERVED_A_236;
+ u32 RESERVED_A_237;
+ u32 RESERVED_A_238;
+ u32 RESERVED_A_239;
+ u32 RESERVED_A_240;
+ u32 RESERVED_A_241;
+ u32 RESERVED_A_242;
+ u32 RESERVED_A_243;
+ u32 RESERVED_A_244;
+ u32 RESERVED_A_245;
+ u32 RESERVED_A_246;
+ u32 RESERVED_A_247;
+ u32 RESERVED_A_248;
+ u32 RESERVED_A_249;
+ u32 RESERVED_A_250;
+ u32 RESERVED_A_251;
+ u32 RESERVED_A_252;
+ u32 RESERVED_A_253;
+ u32 RESERVED_A_254;
+ u32 RESERVED_A_255;
+ u32 RESERVED_A_256;
+ u32 RESERVED_A_257;
+ u32 RESERVED_A_258;
+ u32 RESERVED_A_259;
+ u32 RESERVED_A_260;
+ u32 RESERVED_A_261;
+ u32 RESERVED_A_262;
+ u32 RESERVED_A_263;
+ u32 RESERVED_A_264;
+ u32 RESERVED_A_265;
+ u32 RESERVED_A_266;
+ u32 RESERVED_A_267;
+ u32 L1_VLATCH_AEXP_AVE4LINESY0;
+ u32 L1_VLATCH_AEXP_AVE4LINESY1;
+ u32 L1_VLATCH_AEXP_AVE4LINESY2;
+ u32 L1_VLATCH_AEXP_AVE4LINESY3;
+ u32 RESERVED_A_268;
+ u32 RESERVED_A_269;
+ u32 RESERVED_A_270;
+ u32 RESERVED_A_271;
+ u32 RESERVED_B_24[3];
+ u32 L1_VLATCH_IBUF_DEPTH;
+ u32 L1_VLATCH_IBUF_INPUT_ORDER;
+ u32 RESERVED_B_25[2];
+ u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_GR;
+ u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_R;
+ u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_B;
+ u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_GB;
+ u32 RESERVED_A_272;
+ u32 RESERVED_A_273;
+ u32 RESERVED_A_274;
+ u32 RESERVED_A_275;
+ u32 RESERVED_A_276;
+ u32 RESERVED_B_26[19];
+ u32 RESERVED_A_277;
+ u32 RESERVED_A_278;
+ u32 RESERVED_A_279;
+ u32 L1_VLATCH_ABPC012_STA_EN;
+ u32 L1_VLATCH_ABPC012_DYN_EN;
+ u32 L1_VLATCH_ABPC012_DYN_MODE;
+ u32 RESERVED_A_280;
+ u32 RESERVED_A_281;
+ u32 RESERVED_A_282;
+ u32 L1_VLATCH_ABPC0_RATIO_LIMIT;
+ u32 RESERVED_A_283;
+ u32 L1_VLATCH_ABPC0_DARK_LIMIT;
+ u32 L1_VLATCH_ABPC0_SN_COEF_W_AG_MIN;
+ u32 L1_VLATCH_ABPC0_SN_COEF_W_AG_MID;
+ u32 L1_VLATCH_ABPC0_SN_COEF_W_AG_MAX;
+ u32 L1_VLATCH_ABPC0_SN_COEF_W_TH_MIN;
+ u32 L1_VLATCH_ABPC0_SN_COEF_W_TH_MAX;
+ u32 L1_VLATCH_ABPC0_SN_COEF_B_AG_MIN;
+ u32 L1_VLATCH_ABPC0_SN_COEF_B_AG_MID;
+ u32 L1_VLATCH_ABPC0_SN_COEF_B_AG_MAX;
+ u32 L1_VLATCH_ABPC0_SN_COEF_B_TH_MIN;
+ u32 L1_VLATCH_ABPC0_SN_COEF_B_TH_MAX;
+ u32 RESERVED_A_284;
+ u32 RESERVED_A_285;
+ u32 L1_VLATCH_ABPC1_RATIO_LIMIT;
+ u32 RESERVED_A_286;
+ u32 L1_VLATCH_ABPC1_DARK_LIMIT;
+ u32 L1_VLATCH_ABPC1_SN_COEF_W_AG_MIN;
+ u32 L1_VLATCH_ABPC1_SN_COEF_W_AG_MID;
+ u32 L1_VLATCH_ABPC1_SN_COEF_W_AG_MAX;
+ u32 L1_VLATCH_ABPC1_SN_COEF_W_TH_MIN;
+ u32 L1_VLATCH_ABPC1_SN_COEF_W_TH_MAX;
+ u32 L1_VLATCH_ABPC1_SN_COEF_B_AG_MIN;
+ u32 L1_VLATCH_ABPC1_SN_COEF_B_AG_MID;
+ u32 L1_VLATCH_ABPC1_SN_COEF_B_AG_MAX;
+ u32 L1_VLATCH_ABPC1_SN_COEF_B_TH_MIN;
+ u32 L1_VLATCH_ABPC1_SN_COEF_B_TH_MAX;
+ u32 RESERVED_A_287;
+ u32 RESERVED_A_288;
+ u32 L1_VLATCH_ABPC2_RATIO_LIMIT;
+ u32 RESERVED_A_289;
+ u32 L1_VLATCH_ABPC2_DARK_LIMIT;
+ u32 L1_VLATCH_ABPC2_SN_COEF_W_AG_MIN;
+ u32 L1_VLATCH_ABPC2_SN_COEF_W_AG_MID;
+ u32 L1_VLATCH_ABPC2_SN_COEF_W_AG_MAX;
+ u32 L1_VLATCH_ABPC2_SN_COEF_W_TH_MIN;
+ u32 L1_VLATCH_ABPC2_SN_COEF_W_TH_MAX;
+ u32 L1_VLATCH_ABPC2_SN_COEF_B_AG_MIN;
+ u32 L1_VLATCH_ABPC2_SN_COEF_B_AG_MID;
+ u32 L1_VLATCH_ABPC2_SN_COEF_B_AG_MAX;
+ u32 L1_VLATCH_ABPC2_SN_COEF_B_TH_MIN;
+ u32 L1_VLATCH_ABPC2_SN_COEF_B_TH_MAX;
+ u32 RESERVED_A_290;
+ u32 RESERVED_A_291;
+ u32 RESERVED_B_27[42];
+ u32 RESERVED_A_292;
+ u32 L1_VLATCH_PWHB_H_GR;
+ u32 L1_VLATCH_PWHB_HR;
+ u32 L1_VLATCH_PWHB_HB;
+ u32 L1_VLATCH_PWHB_H_GB;
+ u32 L1_VLATCH_PWHB_M_GR;
+ u32 L1_VLATCH_PWHB_MR;
+ u32 L1_VLATCH_PWHB_MB;
+ u32 L1_VLATCH_PWHB_M_GB;
+ u32 L1_VLATCH_PWHB_L_GR;
+ u32 L1_VLATCH_PWHB_LR;
+ u32 L1_VLATCH_PWHB_LB;
+ u32 L1_VLATCH_PWHB_L_GB;
+ u32 L1_VLATCH_PWHB_DSTMAXVAL;
+ u32 RESERVED_B_28[18];
+ u32 RESERVED_A_293;
+ u32 RESERVED_A_294;
+ u32 L1_VLATCH_RCNR0_SW;
+ u32 L1_VLATCH_RCNR0_CNF_DARK_AG0;
+ u32 L1_VLATCH_RCNR0_CNF_DARK_AG1;
+ u32 L1_VLATCH_RCNR0_CNF_DARK_AG2;
+ u32 L1_VLATCH_RCNR0_CNF_RATIO_AG0;
+ u32 L1_VLATCH_RCNR0_CNF_RATIO_AG1;
+ u32 L1_VLATCH_RCNR0_CNF_RATIO_AG2;
+ u32 L1_VLATCH_RCNR0_CNF_CLIP_GAIN_R;
+ u32 L1_VLATCH_RCNR0_CNF_CLIP_GAIN_G;
+ u32 L1_VLATCH_RCNR0_CNF_CLIP_GAIN_B;
+ u32 L1_VLATCH_RCNR0_A1L_DARK_AG0;
+ u32 L1_VLATCH_RCNR0_A1L_DARK_AG1;
+ u32 L1_VLATCH_RCNR0_A1L_DARK_AG2;
+ u32 L1_VLATCH_RCNR0_A1L_RATIO_AG0;
+ u32 L1_VLATCH_RCNR0_A1L_RATIO_AG1;
+ u32 L1_VLATCH_RCNR0_A1L_RATIO_AG2;
+ u32 L1_VLATCH_RCNR0_INF_ZERO_CLIP;
+ u32 RESERVED_A_295;
+ u32 L1_VLATCH_RCNR0_MERGE_D2BLEND_AG0;
+ u32 L1_VLATCH_RCNR0_MERGE_D2BLEND_AG1;
+ u32 L1_VLATCH_RCNR0_MERGE_D2BLEND_AG2;
+ u32 L1_VLATCH_RCNR0_MERGE_BLACK;
+ u32 L1_VLATCH_RCNR0_MERGE_MINDIV;
+ u32 L1_VLATCH_RCNR0_HRY_TYPE;
+ u32 L1_VLATCH_RCNR0_ANF_BLEND_AG0;
+ u32 L1_VLATCH_RCNR0_ANF_BLEND_AG1;
+ u32 L1_VLATCH_RCNR0_ANF_BLEND_AG2;
+ u32 RESERVED_A_296;
+ u32 L1_VLATCH_RCNR0_LPF_THRESHOLD;
+ u32 L1_VLATCH_RCNR0_MERGE_HLBLEND_AG0;
+ u32 L1_VLATCH_RCNR0_MERGE_HLBLEND_AG1;
+ u32 L1_VLATCH_RCNR0_MERGE_HLBLEND_AG2;
+ u32 L1_VLATCH_RCNR0_GNR_SW;
+ u32 L1_VLATCH_RCNR0_GNR_RATIO;
+ u32 L1_VLATCH_RCNR0_GNR_WIDE_EN;
+ u32 RESERVED_A_297;
+ u32 RESERVED_A_298;
+ u32 L1_VLATCH_RCNR1_SW;
+ u32 L1_VLATCH_RCNR1_CNF_DARK_AG0;
+ u32 L1_VLATCH_RCNR1_CNF_DARK_AG1;
+ u32 L1_VLATCH_RCNR1_CNF_DARK_AG2;
+ u32 L1_VLATCH_RCNR1_CNF_RATIO_AG0;
+ u32 L1_VLATCH_RCNR1_CNF_RATIO_AG1;
+ u32 L1_VLATCH_RCNR1_CNF_RATIO_AG2;
+ u32 L1_VLATCH_RCNR1_CNF_CLIP_GAIN_R;
+ u32 L1_VLATCH_RCNR1_CNF_CLIP_GAIN_G;
+ u32 L1_VLATCH_RCNR1_CNF_CLIP_GAIN_B;
+ u32 L1_VLATCH_RCNR1_A1L_DARK_AG0;
+ u32 L1_VLATCH_RCNR1_A1L_DARK_AG1;
+ u32 L1_VLATCH_RCNR1_A1L_DARK_AG2;
+ u32 L1_VLATCH_RCNR1_A1L_RATIO_AG0;
+ u32 L1_VLATCH_RCNR1_A1L_RATIO_AG1;
+ u32 L1_VLATCH_RCNR1_A1L_RATIO_AG2;
+ u32 L1_VLATCH_RCNR1_INF_ZERO_CLIP;
+ u32 RESERVED_A_299;
+ u32 L1_VLATCH_RCNR1_MERGE_D2BLEND_AG0;
+ u32 L1_VLATCH_RCNR1_MERGE_D2BLEND_AG1;
+ u32 L1_VLATCH_RCNR1_MERGE_D2BLEND_AG2;
+ u32 L1_VLATCH_RCNR1_MERGE_BLACK;
+ u32 L1_VLATCH_RCNR1_MERGE_MINDIV;
+ u32 L1_VLATCH_RCNR1_HRY_TYPE;
+ u32 L1_VLATCH_RCNR1_ANF_BLEND_AG0;
+ u32 L1_VLATCH_RCNR1_ANF_BLEND_AG1;
+ u32 L1_VLATCH_RCNR1_ANF_BLEND_AG2;
+ u32 RESERVED_A_300;
+ u32 L1_VLATCH_RCNR1_LPF_THRESHOLD;
+ u32 L1_VLATCH_RCNR1_MERGE_HLBLEND_AG0;
+ u32 L1_VLATCH_RCNR1_MERGE_HLBLEND_AG1;
+ u32 L1_VLATCH_RCNR1_MERGE_HLBLEND_AG2;
+ u32 L1_VLATCH_RCNR1_GNR_SW;
+ u32 L1_VLATCH_RCNR1_GNR_RATIO;
+ u32 L1_VLATCH_RCNR1_GNR_WIDE_EN;
+ u32 RESERVED_A_301;
+ u32 RESERVED_A_302;
+ u32 L1_VLATCH_RCNR2_SW;
+ u32 L1_VLATCH_RCNR2_CNF_DARK_AG0;
+ u32 L1_VLATCH_RCNR2_CNF_DARK_AG1;
+ u32 L1_VLATCH_RCNR2_CNF_DARK_AG2;
+ u32 L1_VLATCH_RCNR2_CNF_RATIO_AG0;
+ u32 L1_VLATCH_RCNR2_CNF_RATIO_AG1;
+ u32 L1_VLATCH_RCNR2_CNF_RATIO_AG2;
+ u32 L1_VLATCH_RCNR2_CNF_CLIP_GAIN_R;
+ u32 L1_VLATCH_RCNR2_CNF_CLIP_GAIN_G;
+ u32 L1_VLATCH_RCNR2_CNF_CLIP_GAIN_B;
+ u32 L1_VLATCH_RCNR2_A1L_DARK_AG0;
+ u32 L1_VLATCH_RCNR2_A1L_DARK_AG1;
+ u32 L1_VLATCH_RCNR2_A1L_DARK_AG2;
+ u32 L1_VLATCH_RCNR2_A1L_RATIO_AG0;
+ u32 L1_VLATCH_RCNR2_A1L_RATIO_AG1;
+ u32 L1_VLATCH_RCNR2_A1L_RATIO_AG2;
+ u32 L1_VLATCH_RCNR2_INF_ZERO_CLIP;
+ u32 RESERVED_A_303;
+ u32 L1_VLATCH_RCNR2_MERGE_D2BLEND_AG0;
+ u32 L1_VLATCH_RCNR2_MERGE_D2BLEND_AG1;
+ u32 L1_VLATCH_RCNR2_MERGE_D2BLEND_AG2;
+ u32 L1_VLATCH_RCNR2_MERGE_BLACK;
+ u32 L1_VLATCH_RCNR2_MERGE_MINDIV;
+ u32 L1_VLATCH_RCNR2_HRY_TYPE;
+ u32 L1_VLATCH_RCNR2_ANF_BLEND_AG0;
+ u32 L1_VLATCH_RCNR2_ANF_BLEND_AG1;
+ u32 L1_VLATCH_RCNR2_ANF_BLEND_AG2;
+ u32 RESERVED_A_304;
+ u32 L1_VLATCH_RCNR2_LPF_THRESHOLD;
+ u32 L1_VLATCH_RCNR2_MERGE_HLBLEND_AG0;
+ u32 L1_VLATCH_RCNR2_MERGE_HLBLEND_AG1;
+ u32 L1_VLATCH_RCNR2_MERGE_HLBLEND_AG2;
+ u32 L1_VLATCH_RCNR2_GNR_SW;
+ u32 L1_VLATCH_RCNR2_GNR_RATIO;
+ u32 L1_VLATCH_RCNR2_GNR_WIDE_EN;
+ u32 RESERVED_B_29[49];
+ u32 RESERVED_A_305;
+ u32 L1_VLATCH_HDRS_HDRRATIO_M;
+ u32 L1_VLATCH_HDRS_HDRRATIO_L;
+ u32 L1_VLATCH_HDRS_HDRRATIO_E;
+ u32 RESERVED_A_306;
+ u32 RESERVED_A_307;
+ u32 L1_VLATCH_HDRS_BLENDEND_H;
+ u32 L1_VLATCH_HDRS_BLENDEND_M;
+ u32 L1_VLATCH_HDRS_BLENDEND_E;
+ u32 L1_VLATCH_HDRS_BLENDBEG_H;
+ u32 L1_VLATCH_HDRS_BLENDBEG_M;
+ u32 L1_VLATCH_HDRS_BLENDBEG_E;
+ u32 RESERVED_A_308;
+ u32 RESERVED_A_309;
+ u32 RESERVED_A_310;
+ u32 RESERVED_A_311;
+ u32 RESERVED_A_312;
+ u32 RESERVED_A_313;
+ u32 L1_VLATCH_HDRS_DgH;
+ u32 L1_VLATCH_HDRS_DgM;
+ u32 L1_VLATCH_HDRS_DgL;
+ u32 L1_VLATCH_HDRS_DgE;
+ u32 L1_VLATCH_HDRS_LEDMODE_ON;
+ u32 L1_VLATCH_HDRS_HDRMODE;
+ u32 RESERVED_A_314;
+ u32 RESERVED_A_315;
+ u32 RESERVED_A_316;
+ u32 L1_VLATCH_HDRS_DSTMAXVAL;
+ u32 RESERVED_B_30[4];
+ u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_GR;
+ u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_R;
+ u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_B;
+ u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_GB;
+ u32 L1_VLATCH_BLVC_MULTVAL_GR;
+ u32 L1_VLATCH_BLVC_MULTVALR;
+ u32 L1_VLATCH_BLVC_MULTVALB;
+ u32 L1_VLATCH_BLVC_MULTVAL_GB;
+ u32 L1_VLATCH_BLVC_DSTMAXVAL;
+ u32 RESERVED_A_317;
+ u32 RESERVED_A_318;
+ u32 RESERVED_A_319;
+ u32 RESERVED_A_320;
+ u32 RESERVED_A_321;
+ u32 RESERVED_A_322;
+ u32 RESERVED_B_31[17];
+ u32 L1_VLATCH_LSSC_EN;
+ u32 RESERVED_A_323;
+ u32 RESERVED_A_324;
+ u32 RESERVED_A_325;
+ u32 L1_VLATCH_LSSC_PWHB_R_GAIN;
+ u32 L1_VLATCH_LSSC_PWHB_GR_GAIN;
+ u32 L1_VLATCH_LSSC_PWHB_GB_GAIN;
+ u32 L1_VLATCH_LSSC_PWHB_B_GAIN;
+ u32 L1_VLATCH_LSSC_PARA_EN;
+ u32 L1_VLATCH_LSSC_PARA_H_CENTER;
+ u32 L1_VLATCH_LSSC_PARA_V_CENTER;
+ u32 L1_VLATCH_LSSC_PARA_H_GAIN;
+ u32 L1_VLATCH_LSSC_PARA_V_GAIN;
+ u32 L1_VLATCH_LSSC_PARA_MGSEL2;
+ u32 L1_VLATCH_LSSC_PARA_MGSEL4;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_RD;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_H_L;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_H_R;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_V_U;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_V_D;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_LU;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_RU;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_LD;
+ u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_RD;
+ u32 L1_VLATCH_LSSC_GRID_EN;
+ u32 L1_VLATCH_LSSC_GRID_H_CENTER;
+ u32 L1_VLATCH_LSSC_GRID_V_CENTER;
+ u32 L1_VLATCH_LSSC_GRID_H_SIZE;
+ u32 L1_VLATCH_LSSC_GRID_V_SIZE;
+ u32 L1_VLATCH_LSSC_GRID_MGSEL;
+ u32 RESERVED_B_32[11];
+ u32 L1_VLATCH_MPRO_SW;
+ u32 L1_VLATCH_MPRO_CONF;
+ u32 RESERVED_A_326;
+ u32 L1_VLATCH_MPRO_DST_MINVAL;
+ u32 L1_VLATCH_MPRO_DST_MAXVAL;
+ u32 RESERVED_A_327;
+ u32 RESERVED_A_328;
+ u32 RESERVED_A_329;
+ u32 L1_VLATCH_MPRO_LM0_RMG_MIN;
+ u32 L1_VLATCH_MPRO_LM0_RMB_MIN;
+ u32 L1_VLATCH_MPRO_LM0_GMR_MIN;
+ u32 L1_VLATCH_MPRO_LM0_GMB_MIN;
+ u32 L1_VLATCH_MPRO_LM0_BMR_MIN;
+ u32 L1_VLATCH_MPRO_LM0_BMG_MIN;
+ u32 L1_VLATCH_MPRO_LM0_RMG_MAX;
+ u32 L1_VLATCH_MPRO_LM0_RMB_MAX;
+ u32 L1_VLATCH_MPRO_LM0_GMR_MAX;
+ u32 L1_VLATCH_MPRO_LM0_GMB_MAX;
+ u32 L1_VLATCH_MPRO_LM0_BMR_MAX;
+ u32 L1_VLATCH_MPRO_LM0_BMG_MAX;
+ u32 RESERVED_A_330;
+ u32 RESERVED_A_331;
+ u32 RESERVED_A_332;
+ u32 RESERVED_A_333;
+ u32 RESERVED_A_334;
+ u32 RESERVED_A_335;
+ u32 RESERVED_A_336;
+ u32 RESERVED_A_337;
+ u32 RESERVED_A_338;
+ u32 RESERVED_A_339;
+ u32 RESERVED_A_340;
+ u32 RESERVED_A_341;
+ u32 RESERVED_A_342;
+ u32 RESERVED_A_343;
+ u32 RESERVED_A_344;
+ u32 RESERVED_A_345;
+ u32 RESERVED_A_346;
+ u32 RESERVED_A_347;
+ u32 RESERVED_A_348;
+ u32 RESERVED_A_349;
+ u32 RESERVED_A_350;
+ u32 RESERVED_A_351;
+ u32 RESERVED_A_352;
+ u32 RESERVED_A_353;
+ u32 RESERVED_A_354;
+ u32 RESERVED_A_355;
+ u32 RESERVED_A_356;
+ u32 RESERVED_A_357;
+ u32 RESERVED_A_358;
+ u32 RESERVED_A_359;
+ u32 RESERVED_A_360;
+ u32 RESERVED_A_361;
+ u32 RESERVED_A_362;
+ u32 RESERVED_A_363;
+ u32 RESERVED_A_364;
+ u32 RESERVED_A_365;
+ u32 RESERVED_A_366;
+ u32 RESERVED_A_367;
+ u32 RESERVED_A_368;
+ u32 RESERVED_B_33[1];
+ u32 L1_VLATCH_MPRO_LCS_MODE;
+ u32 RESERVED_A_369;
+ u32 RESERVED_A_370;
+ u32 RESERVED_A_371;
+ u32 RESERVED_A_372;
+ u32 RESERVED_A_373;
+ u32 RESERVED_A_374;
+ u32 RESERVED_A_375;
+ u32 RESERVED_A_376;
+ u32 RESERVED_A_377;
+ u32 RESERVED_A_378;
+ u32 RESERVED_A_379;
+ u32 RESERVED_A_380;
+ u32 RESERVED_A_381;
+ u32 RESERVED_A_382;
+ u32 RESERVED_A_383;
+ u32 RESERVED_A_384;
+ u32 RESERVED_A_385;
+ u32 RESERVED_A_386;
+ u32 RESERVED_A_387;
+ u32 RESERVED_A_388;
+ u32 RESERVED_A_389;
+ u32 RESERVED_A_390;
+ u32 RESERVED_A_391;
+ u32 RESERVED_A_392;
+ u32 RESERVED_A_393;
+ u32 RESERVED_A_394;
+ u32 RESERVED_A_395;
+ u32 RESERVED_A_396;
+ u32 RESERVED_A_397;
+ u32 RESERVED_B_34[70];
+ u32 L1_VLATCH_VPRO_PGC_SW;
+ u32 RESERVED_A_398;
+ u32 L1_VLATCH_VPRO_YUVC_SW;
+ u32 L1_VLATCH_VPRO_YNR_SW;
+ u32 L1_VLATCH_VPRO_ETE_SW;
+ u32 L1_VLATCH_VPRO_CSUP_UVSUP_SW;
+ u32 L1_VLATCH_VPRO_CSUP_CORING_SW;
+ u32 L1_VLATCH_VPRO_BRIGHT_SW;
+ u32 L1_VLATCH_VPRO_LCNT_SW;
+ u32 L1_VLATCH_VPRO_NLCNT_SW;
+ u32 RESERVED_A_399;
+ u32 L1_VLATCH_VPRO_EDGE_SUP_SW;
+ u32 L1_VLATCH_VPRO_CNR_SW;
+ u32 RESERVED_A_400;
+ u32 L1_VLATCH_VPRO_BLKADJ;
+ u32 L1_VLATCH_VPRO_GAM01P;
+ u32 L1_VLATCH_VPRO_GAM02P;
+ u32 L1_VLATCH_VPRO_GAM03P;
+ u32 L1_VLATCH_VPRO_GAM04P;
+ u32 L1_VLATCH_VPRO_GAM05P;
+ u32 L1_VLATCH_VPRO_GAM06P;
+ u32 L1_VLATCH_VPRO_GAM07P;
+ u32 L1_VLATCH_VPRO_GAM08P;
+ u32 L1_VLATCH_VPRO_GAM09P;
+ u32 L1_VLATCH_VPRO_GAM10P;
+ u32 L1_VLATCH_VPRO_GAM11P;
+ u32 L1_VLATCH_VPRO_GAM12P;
+ u32 L1_VLATCH_VPRO_GAM13P;
+ u32 L1_VLATCH_VPRO_GAM14P;
+ u32 L1_VLATCH_VPRO_GAM15P;
+ u32 L1_VLATCH_VPRO_GAM16P;
+ u32 L1_VLATCH_VPRO_GAM17P;
+ u32 L1_VLATCH_VPRO_GAM18P;
+ u32 L1_VLATCH_VPRO_GAM19P;
+ u32 L1_VLATCH_VPRO_GAM20P;
+ u32 L1_VLATCH_VPRO_GAM21P;
+ u32 L1_VLATCH_VPRO_GAM22P;
+ u32 L1_VLATCH_VPRO_GAM23P;
+ u32 L1_VLATCH_VPRO_GAM24P;
+ u32 L1_VLATCH_VPRO_GAM25P;
+ u32 L1_VLATCH_VPRO_GAM26P;
+ u32 L1_VLATCH_VPRO_GAM27P;
+ u32 L1_VLATCH_VPRO_GAM28P;
+ u32 L1_VLATCH_VPRO_GAM29P;
+ u32 L1_VLATCH_VPRO_GAM30P;
+ u32 L1_VLATCH_VPRO_GAM31P;
+ u32 L1_VLATCH_VPRO_GAM32P;
+ u32 L1_VLATCH_VPRO_GAM33P;
+ u32 L1_VLATCH_VPRO_GAM34P;
+ u32 L1_VLATCH_VPRO_GAM35P;
+ u32 L1_VLATCH_VPRO_GAM36P;
+ u32 L1_VLATCH_VPRO_GAM37P;
+ u32 L1_VLATCH_VPRO_GAM38P;
+ u32 L1_VLATCH_VPRO_GAM39P;
+ u32 L1_VLATCH_VPRO_GAM40P;
+ u32 L1_VLATCH_VPRO_GAM41P;
+ u32 L1_VLATCH_VPRO_GAM42P;
+ u32 L1_VLATCH_VPRO_GAM43P;
+ u32 L1_VLATCH_VPRO_GAM44P;
+ u32 L1_VLATCH_VPRO_CB_MAT;
+ u32 L1_VLATCH_VPRO_CR_MAT;
+ u32 L1_VLATCH_VPRO_BRIGHT;
+ u32 L1_VLATCH_VPRO_LCONT_LEV;
+ u32 L1_VLATCH_VPRO_BLK_KNEE;
+ u32 L1_VLATCH_VPRO_WHT_KNEE;
+ u32 L1_VLATCH_VPRO_BLK_CONT0;
+ u32 L1_VLATCH_VPRO_BLK_CONT1;
+ u32 L1_VLATCH_VPRO_BLK_CONT2;
+ u32 L1_VLATCH_VPRO_WHT_CONT0;
+ u32 L1_VLATCH_VPRO_WHT_CONT1;
+ u32 L1_VLATCH_VPRO_WHT_CONT2;
+ u32 RESERVED_A_401;
+ u32 RESERVED_A_402;
+ u32 RESERVED_A_403;
+ u32 RESERVED_A_404;
+ u32 RESERVED_A_405;
+ u32 RESERVED_A_406;
+ u32 L1_VLATCH_VPRO_YNR_GAIN_MIN;
+ u32 L1_VLATCH_VPRO_YNR_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_YNR_LIM_MIN;
+ u32 L1_VLATCH_VPRO_YNR_LIM_MAX;
+ u32 L1_VLATCH_VPRO_ETE_GAIN_MIN;
+ u32 L1_VLATCH_VPRO_ETE_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_ETE_LIM_MIN;
+ u32 L1_VLATCH_VPRO_ETE_LIM_MAX;
+ u32 L1_VLATCH_VPRO_ETE_CORING_MIN;
+ u32 L1_VLATCH_VPRO_ETE_CORING_MAX;
+ u32 L1_VLATCH_VPRO_CB_GAIN;
+ u32 L1_VLATCH_VPRO_CR_GAIN;
+ u32 L1_VLATCH_VPRO_CBR_MGAIN_MIN;
+ u32 L1_VLATCH_VPRO_CbP_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_CbM_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_CrP_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_CrM_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_CSUP_CORING_LV_MIN;
+ u32 L1_VLATCH_VPRO_CSUP_CORING_LV_MAX;
+ u32 L1_VLATCH_VPRO_CSUP_CORING_GAIN_MIN;
+ u32 L1_VLATCH_VPRO_CSUP_CORING_GAIN_MAX;
+ u32 L1_VLATCH_VPRO_CSUP_BK_SLV;
+ u32 L1_VLATCH_VPRO_CSUP_BK_MP;
+ u32 L1_VLATCH_VPRO_CSUP_BLACK;
+ u32 L1_VLATCH_VPRO_CSUP_WH_SLV;
+ u32 L1_VLATCH_VPRO_CSUP_WH_MP;
+ u32 L1_VLATCH_VPRO_CSUP_WHITE;
+ u32 L1_VLATCH_VPRO_EDGE_SUP_GAIN;
+ u32 L1_VLATCH_VPRO_EDGE_SUP_LIM;
+ u32 RESERVED_B_35[22];
+ u32 L1_VLATCH_AWHB_SW;
+ u32 RESERVED_A_407;
+ u32 L1_VLATCH_AWHB_WBMRG;
+ u32 L1_VLATCH_AWHB_WBMGG;
+ u32 L1_VLATCH_AWHB_WBMBG;
+ u32 L1_VLATCH_AWHB_GATE_CONF0;
+ u32 L1_VLATCH_AWHB_GATE_CONF1;
+ u32 L1_VLATCH_AWHB_AREA_HSIZE;
+ u32 L1_VLATCH_AWHB_AREA_VSIZE;
+ u32 L1_VLATCH_AWHB_AREA_HOFS;
+ u32 L1_VLATCH_AWHB_AREA_VOFS;
+ u32 L1_VLATCH_AWHB_AREA_MASKH;
+ u32 L1_VLATCH_AWHB_AREA_MASKL;
+ u32 L1_VLATCH_AWHB_SQ_CONF;
+ u32 L1_VLATCH_AWHB_YGATEH;
+ u32 L1_VLATCH_AWHB_YGATEL;
+ u32 RESERVED_A_408;
+ u32 RESERVED_A_409;
+ u32 L1_VLATCH_AWHB_BYCUT0P;
+ u32 L1_VLATCH_AWHB_BYCUT0N;
+ u32 L1_VLATCH_AWHB_RYCUT0P;
+ u32 L1_VLATCH_AWHB_RYCUT0N;
+ u32 L1_VLATCH_AWHB_RBCUT0H;
+ u32 L1_VLATCH_AWHB_RBCUT0L;
+ u32 RESERVED_A_410;
+ u32 RESERVED_A_411;
+ u32 RESERVED_A_412;
+ u32 RESERVED_A_413;
+ u32 RESERVED_A_414;
+ u32 RESERVED_A_415;
+ u32 L1_VLATCH_AWHB_BYCUT1H;
+ u32 L1_VLATCH_AWHB_BYCUT1L;
+ u32 L1_VLATCH_AWHB_RYCUT1H;
+ u32 L1_VLATCH_AWHB_RYCUT1L;
+ u32 L1_VLATCH_AWHB_BYCUT2H;
+ u32 L1_VLATCH_AWHB_BYCUT2L;
+ u32 L1_VLATCH_AWHB_RYCUT2H;
+ u32 L1_VLATCH_AWHB_RYCUT2L;
+ u32 L1_VLATCH_AWHB_BYCUT3H;
+ u32 L1_VLATCH_AWHB_BYCUT3L;
+ u32 L1_VLATCH_AWHB_RYCUT3H;
+ u32 L1_VLATCH_AWHB_RYCUT3L;
+ u32 L1_VLATCH_AWHB_AWBSFTU;
+ u32 L1_VLATCH_AWHB_AWBSFTV;
+ u32 L1_VLATCH_AWHB_AWBSPD;
+ u32 L1_VLATCH_AWHB_AWBULV;
+ u32 L1_VLATCH_AWHB_AWBVLV;
+ u32 L1_VLATCH_AWHB_AWBWAIT;
+ u32 L1_VLATCH_AWHB_AWBONDOT;
+ u32 L1_VLATCH_AWHB_AWBFZTIM;
+ u32 L1_VLATCH_AWHB_WBGRMAX;
+ u32 L1_VLATCH_AWHB_WBGRMIN;
+ u32 L1_VLATCH_AWHB_WBGBMAX;
+ u32 L1_VLATCH_AWHB_WBGBMIN;
+ u32 RESERVED_A_416;
+ u32 RESERVED_A_417;
+ u32 RESERVED_A_418;
+ u32 RESERVED_A_419;
+ u32 RESERVED_A_420;
+ u32 RESERVED_A_421;
+ u32 RESERVED_A_422;
+ u32 RESERVED_A_423;
+ u32 RESERVED_A_424;
+ u32 RESERVED_A_425;
+ u32 RESERVED_A_426;
+ u32 RESERVED_A_427;
+ u32 RESERVED_A_428;
+ u32 RESERVED_A_429;
+ u32 RESERVED_A_430;
+ u32 RESERVED_A_431;
+ u32 RESERVED_A_432;
+ u32 RESERVED_A_433;
+ u32 RESERVED_A_434;
+ u32 RESERVED_A_435;
+ u32 RESERVED_A_436;
+ u32 RESERVED_A_437;
+ u32 RESERVED_A_438;
+ u32 RESERVED_A_439;
+ u32 RESERVED_B_36[2];
+ u32 L1_VLATCH_HOBC_EN;
+ u32 L1_VLATCH_HOBC_MARGIN;
+ u32 RESERVED_A_440;
+ u32 RESERVED_A_441;
+ u32 L1_VLATCH_HOBC0_LOB_REFLV_GR;
+ u32 L1_VLATCH_HOBC0_LOB_WIDTH_GR;
+ u32 L1_VLATCH_HOBC0_LOB_REFLV_R;
+ u32 L1_VLATCH_HOBC0_LOB_WIDTH_R;
+ u32 L1_VLATCH_HOBC0_LOB_REFLV_B;
+ u32 L1_VLATCH_HOBC0_LOB_WIDTH_B;
+ u32 L1_VLATCH_HOBC0_LOB_REFLV_GB;
+ u32 L1_VLATCH_HOBC0_LOB_WIDTH_GB;
+ u32 L1_VLATCH_HOBC1_LOB_REFLV_GR;
+ u32 L1_VLATCH_HOBC1_LOB_WIDTH_GR;
+ u32 L1_VLATCH_HOBC1_LOB_REFLV_R;
+ u32 L1_VLATCH_HOBC1_LOB_WIDTH_R;
+ u32 L1_VLATCH_HOBC1_LOB_REFLV_B;
+ u32 L1_VLATCH_HOBC1_LOB_WIDTH_B;
+ u32 L1_VLATCH_HOBC1_LOB_REFLV_GB;
+ u32 L1_VLATCH_HOBC1_LOB_WIDTH_GB;
+ u32 L1_VLATCH_HOBC2_LOB_REFLV_GR;
+ u32 L1_VLATCH_HOBC2_LOB_WIDTH_GR;
+ u32 L1_VLATCH_HOBC2_LOB_REFLV_R;
+ u32 L1_VLATCH_HOBC2_LOB_WIDTH_R;
+ u32 L1_VLATCH_HOBC2_LOB_REFLV_B;
+ u32 L1_VLATCH_HOBC2_LOB_WIDTH_B;
+ u32 L1_VLATCH_HOBC2_LOB_REFLV_GB;
+ u32 L1_VLATCH_HOBC2_LOB_WIDTH_GB;
+ u32 L1_VLATCH_HOBC0_SRC_BLKLV_GR;
+ u32 L1_VLATCH_HOBC0_SRC_BLKLV_R;
+ u32 L1_VLATCH_HOBC0_SRC_BLKLV_B;
+ u32 L1_VLATCH_HOBC0_SRC_BLKLV_GB;
+ u32 L1_VLATCH_HOBC1_SRC_BLKLV_GR;
+ u32 L1_VLATCH_HOBC1_SRC_BLKLV_R;
+ u32 L1_VLATCH_HOBC1_SRC_BLKLV_B;
+ u32 L1_VLATCH_HOBC1_SRC_BLKLV_GB;
+ u32 L1_VLATCH_HOBC2_SRC_BLKLV_GR;
+ u32 L1_VLATCH_HOBC2_SRC_BLKLV_R;
+ u32 L1_VLATCH_HOBC2_SRC_BLKLV_B;
+ u32 L1_VLATCH_HOBC2_SRC_BLKLV_GB;
+ u32 RESERVED_A_442;
+ u32 RESERVED_A_443;
+ u32 RESERVED_A_444;
+ u32 RESERVED_A_445;
+ u32 RESERVED_A_446;
+ u32 RESERVED_A_447;
+ u32 L1_VLATCH_HOBC_MAX_VAL;
+ u32 RESERVED_B_37[33];
+ u32 L1_VLATCH_HDRC_EN;
+ u32 L1_VLATCH_HDRC_THR_SFT_AMT;
+ u32 RESERVED_A_448;
+ u32 L1_VLATCH_HDRC_RATIO;
+ u32 RESERVED_A_449;
+ u32 RESERVED_A_450;
+ u32 RESERVED_A_451;
+ u32 L1_VLATCH_HDRC_PT_RATIO;
+ u32 L1_VLATCH_HDRC_PT_BLEND;
+ u32 L1_VLATCH_HDRC_PT_BLEND2;
+ u32 L1_VLATCH_HDRC_PT_SAT;
+ u32 L1_VLATCH_HDRC_TN_TYPE;
+ u32 L1_VLATCH_HDRC_TNP_MAX;
+ u32 L1_VLATCH_HDRC_TNP_MAG;
+ u32 RESERVED_A_452;
+ u32 RESERVED_A_453;
+ u32 RESERVED_A_454;
+ u32 RESERVED_A_455;
+ u32 L1_VLATCH_HDRC_TNP_FIL0;
+ u32 L1_VLATCH_HDRC_TNP_FIL1;
+ u32 L1_VLATCH_HDRC_TNP_FIL2;
+ u32 L1_VLATCH_HDRC_TNP_FIL3;
+ u32 L1_VLATCH_HDRC_TNP_FIL4;
+ u32 L1_VLATCH_HDRC_UTN_TBL0;
+ u32 L1_VLATCH_HDRC_UTN_TBL1;
+ u32 L1_VLATCH_HDRC_UTN_TBL2;
+ u32 L1_VLATCH_HDRC_UTN_TBL3;
+ u32 L1_VLATCH_HDRC_UTN_TBL4;
+ u32 L1_VLATCH_HDRC_UTN_TBL5;
+ u32 L1_VLATCH_HDRC_UTN_TBL6;
+ u32 L1_VLATCH_HDRC_UTN_TBL7;
+ u32 L1_VLATCH_HDRC_UTN_TBL8;
+ u32 L1_VLATCH_HDRC_UTN_TBL9;
+ u32 L1_VLATCH_HDRC_UTN_TBL10;
+ u32 L1_VLATCH_HDRC_UTN_TBL11;
+ u32 L1_VLATCH_HDRC_UTN_TBL12;
+ u32 L1_VLATCH_HDRC_UTN_TBL13;
+ u32 L1_VLATCH_HDRC_UTN_TBL14;
+ u32 L1_VLATCH_HDRC_UTN_TBL15;
+ u32 L1_VLATCH_HDRC_UTN_TBL16;
+ u32 L1_VLATCH_HDRC_UTN_TBL17;
+ u32 L1_VLATCH_HDRC_UTN_TBL18;
+ u32 L1_VLATCH_HDRC_UTN_TBL19;
+ u32 L1_VLATCH_HDRC_FLR_VAL;
+ u32 L1_VLATCH_HDRC_FLR_ADP;
+ u32 RESERVED_A_456;
+ u32 RESERVED_A_457;
+ u32 RESERVED_A_458;
+ u32 RESERVED_A_459;
+ u32 RESERVED_A_460;
+ u32 RESERVED_A_461;
+ u32 RESERVED_A_462;
+ u32 RESERVED_A_463;
+ u32 RESERVED_A_464;
+ u32 RESERVED_A_465;
+ u32 RESERVED_A_466;
+ u32 RESERVED_A_467;
+ u32 RESERVED_A_468;
+ u32 RESERVED_A_469;
+ u32 L1_VLATCH_HDRC_YBR_OFF;
+ u32 L1_VLATCH_HDRC_ORGY_BLEND;
+ u32 RESERVED_A_470;
+ u32 RESERVED_A_471;
+ u32 RESERVED_A_472;
+ u32 L1_VLATCH_HDRC_MAR_TOP;
+ u32 L1_VLATCH_HDRC_MAR_LEFT;
+ u32 RESERVED_A_473;
+ u32 RESERVED_A_474;
+ u32 RESERVED_B_38[28];
+ u32 L1_VLATCH_HIST_EN;
+ u32 L1_VLATCH_HIST_MODE;
+ u32 L1_VLATCH_HIST_BLOCK_OFST;
+ u32 L1_VLATCH_HIST_BLOCK_SIZE;
+ u32 L1_VLATCH_HIST_BLOCK_NUM;
+ u32 L1_VLATCH_HIST_BLOCK_STEP;
+ u32 L1_VLATCH_HIST_LINEAR_SFT;
+ u32 L1_VLATCH_HIST_MULT_A_R;
+ u32 L1_VLATCH_HIST_ADD_A_R;
+ u32 L1_VLATCH_HIST_MULT_B_R;
+ u32 L1_VLATCH_HIST_ADD_B_R;
+ u32 L1_VLATCH_HIST_MULT_A_G;
+ u32 L1_VLATCH_HIST_ADD_A_G;
+ u32 L1_VLATCH_HIST_MULT_B_G;
+ u32 L1_VLATCH_HIST_ADD_B_G;
+ u32 L1_VLATCH_HIST_MULT_A_B;
+ u32 L1_VLATCH_HIST_ADD_A_B;
+ u32 L1_VLATCH_HIST_MULT_B_B;
+ u32 L1_VLATCH_HIST_ADD_B_B;
+ u32 L1_VLATCH_HIST_MULT_A_Y;
+ u32 L1_VLATCH_HIST_ADD_A_Y;
+ u32 L1_VLATCH_HIST_MULT_B_Y;
+ u32 L1_VLATCH_HIST_ADD_B_Y;
+ u32 RESERVED_B_39[265];
+};
+
+/**
+ * struct hwd_viif_l2isp_stadr_buf_reg - Registers for L2ISP control
+ */
+struct hwd_viif_l2isp_stadr_buf_reg {
+ u32 L2_POST_OUT_STADR_B_BUF;
+ u32 L2_POST_OUT_STADR_G_BUF;
+ u32 L2_POST_OUT_STADR_R_BUF;
+};
+
+struct hwd_viif_l2isp_roi_reg {
+ u32 L2_ROI_SCALE;
+ u32 L2_ROI_SCALE_INV;
+ u32 L2_ROI_CORRECTED_HSIZE;
+ u32 L2_ROI_CORRECTED_VSIZE;
+ u32 L2_ROI_OUT_OFS_H;
+ u32 L2_ROI_OUT_OFS_V;
+ u32 L2_ROI_OUT_HSIZE;
+ u32 L2_ROI_OUT_VSIZE;
+};
+
+struct hwd_viif_l2isp_post_reg {
+ u32 L2_POST_CAP_OFFSET;
+ u32 L2_POST_CAP_SIZE;
+ u32 L2_POST_HALF_SCALE_EN;
+ u32 RESERVED_B_47[17];
+ u32 L2_POST_GAMMA_M;
+ u32 RESERVED_B_48[3];
+ u32 L2_POST_C_SELECT;
+ u32 RESERVED_B_49[3];
+ struct hwd_viif_csc_reg csc;
+ u32 L2_POST_OPORTALP;
+ u32 L2_POST_OPORTFMT;
+ u32 L2_POST_OUT_STADR_B;
+ u32 L2_POST_OUT_STADR_G;
+ u32 L2_POST_OUT_STADR_R;
+ u32 L2_POST_OUT_PITCH_B;
+ u32 L2_POST_OUT_PITCH_G;
+ u32 L2_POST_OUT_PITCH_R;
+ u32 L2_POST_DUMMY_READ_EN;
+ u32 RESERVED_B_51[11];
+};
+
+struct hwd_viif_l2isp_reg {
+ u32 L2_SENSOR_CROP_OFS_H;
+ u32 L2_SENSOR_CROP_OFS_V;
+ u32 L2_SENSOR_CROP_HSIZE;
+ u32 L2_SENSOR_CROP_VSIZE;
+ u32 RESERVED_A_475;
+ u32 L2_L2_STATUS;
+ u32 L2_BUS_L2_STATUS;
+ /* [0]: POST0, [1]: POST1 */
+ struct hwd_viif_l2isp_stadr_buf_reg stadr_buf[2];
+ u32 RESERVED_B_40[3];
+ u32 L2_ROI_NUM;
+ /* [0]: POST0, [1]: POST1 */
+ u32 L2_ROI_TO_POST[2];
+ u32 RESERVED_B_41;
+ /* [0]: ROI0, [1]: ROI1 */
+ struct hwd_viif_l2isp_roi_reg roi[2];
+ u32 RESERVED_B_42[8];
+ u32 L2_VALID_R_NORM2_POLY;
+ u32 L2_VALID_R_NORM2_GRID;
+ u32 RESERVED_A_476;
+ u32 RESERVED_B_43[17];
+ u32 L2_MODE;
+ u32 L2_NORM_SCALE;
+ u32 RESERVED_B_44;
+ /* [0]: ROI0, [1]: ROI1 */
+ u32 L2_ROI_WRITE_AREA_DELTA[2];
+ u32 RESERVED_B_45;
+ u32 L2_GRID_NODE_NUM_H;
+ u32 L2_GRID_NODE_NUM_V;
+ u32 L2_GRID_PATCH_HSIZE_INV;
+ u32 L2_GRID_PATCH_VSIZE_INV;
+ u32 L2_POLY10_WRITE_G_COEF[11];
+ u32 L2_POLY10_READ_B_COEF[11];
+ u32 L2_POLY10_READ_G_COEF[11];
+ u32 L2_POLY10_READ_R_COEF[11];
+ u32 RESERVED_B_46[10];
+ /* [0]: POST0, [1]: POST1 */
+ struct hwd_viif_l2isp_post_reg post[2];
+ u32 RESERVED_B_56[192];
+ u32 L2_CRGBF_ACC_CONF;
+ u32 L2_CRGBF_TRN_M_RUN;
+ u32 L2_CRGBF_TRN_M_CONF;
+ u32 L2_CRGBF_TRN_A_CONF;
+ u32 L2_CRGBF_TRN_STAT_CLR;
+ u32 L2_CRGBF_TRN_STAT;
+ u32 L2_CRGBF_INT_STAT;
+ u32 L2_CRGBF_INT_MASK;
+ u32 L2_CRGBF_INT_MASKED_STAT;
+ u32 L2_CRGBF_TRN_WBADDR;
+ u32 L2_CRGBF_TRN_WEADDR;
+ u32 L2_CRGBF_TRN_RBADDR;
+ u32 L2_CRGBF_TRN_READDR;
+ u32 L2_CRGBF_ISP_INT;
+ u32 L2_CRGBF_ISP_INT_MASK;
+ u32 L2_CRGBF_ISP_INT_MASKED_STAT;
+ u32 RESERVED_A_477;
+ u32 RESERVED_B_57[47];
+ u32 L2_SENSOR_CROP_OFS_H_BUF;
+ u32 L2_SENSOR_CROP_OFS_V_BUF;
+ u32 L2_SENSOR_CROP_HSIZE_BUF;
+ u32 L2_SENSOR_CROP_VSIZE_BUF;
+ u32 RESERVED_A_478;
+ u32 RESERVED_B_58[11];
+ u32 L2_ROI_NUM_BUF;
+ u32 L2_ROI_TO_POST0_BUF;
+ u32 L2_ROI_TO_POST1_BUF;
+ u32 RESERVED_B_59;
+ u32 L2_ROI0_SCALE_BUF;
+ u32 L2_ROI0_SCALE_INV_BUF;
+ u32 L2_ROI0_CORRECTED_HSIZE_BUF;
+ u32 L2_ROI0_CORRECTED_VSIZE_BUF;
+ u32 L2_ROI0_OUT_OFS_H_BUF;
+ u32 L2_ROI0_OUT_OFS_V_BUF;
+ u32 L2_ROI0_OUT_HSIZE_BUF;
+ u32 L2_ROI0_OUT_VSIZE_BUF;
+ u32 L2_ROI1_SCALE_BUF;
+ u32 L2_ROI1_SCALE_INV_BUF;
+ u32 L2_ROI1_CORRECTED_HSIZE_BUF;
+ u32 L2_ROI1_CORRECTED_VSIZE_BUF;
+ u32 L2_ROI1_OUT_OFS_H_BUF;
+ u32 L2_ROI1_OUT_OFS_V_BUF;
+ u32 L2_ROI1_OUT_HSIZE_BUF;
+ u32 L2_ROI1_OUT_VSIZE_BUF;
+ u32 RESERVED_B_60[8];
+ u32 L2_VALID_R_NORM2_POLY_BUF;
+ u32 L2_VALID_R_NORM2_GRID_BUF;
+ u32 RESERVED_A_479;
+ u32 RESERVED_B_61[17];
+ u32 L2_MODE_BUF;
+ u32 L2_NORM_SCALE_BUF;
+ u32 RESERVED_B_62;
+ u32 L2_ROI0_WRITE_AREA_DELTA_BUF;
+ u32 L2_ROI1_WRITE_AREA_DELTA_BUF;
+ u32 RESERVED_B_63;
+ u32 L2_GRID_NODE_NUM_H_BUF;
+ u32 L2_GRID_NODE_NUM_V_BUF;
+ u32 L2_GRID_PATCH_HSIZE_INV_BUF;
+ u32 L2_GRID_PATCH_VSIZE_INV_BUF;
+ u32 L2_POLY10_WRITE_G_COEF00_BUF;
+ u32 L2_POLY10_WRITE_G_COEF01_BUF;
+ u32 L2_POLY10_WRITE_G_COEF02_BUF;
+ u32 L2_POLY10_WRITE_G_COEF03_BUF;
+ u32 L2_POLY10_WRITE_G_COEF04_BUF;
+ u32 L2_POLY10_WRITE_G_COEF05_BUF;
+ u32 L2_POLY10_WRITE_G_COEF06_BUF;
+ u32 L2_POLY10_WRITE_G_COEF07_BUF;
+ u32 L2_POLY10_WRITE_G_COEF08_BUF;
+ u32 L2_POLY10_WRITE_G_COEF09_BUF;
+ u32 L2_POLY10_WRITE_G_COEF10_BUF;
+ u32 L2_POLY10_READ_B_COEF00_BUF;
+ u32 L2_POLY10_READ_B_COEF01_BUF;
+ u32 L2_POLY10_READ_B_COEF02_BUF;
+ u32 L2_POLY10_READ_B_COEF03_BUF;
+ u32 L2_POLY10_READ_B_COEF04_BUF;
+ u32 L2_POLY10_READ_B_COEF05_BUF;
+ u32 L2_POLY10_READ_B_COEF06_BUF;
+ u32 L2_POLY10_READ_B_COEF07_BUF;
+ u32 L2_POLY10_READ_B_COEF08_BUF;
+ u32 L2_POLY10_READ_B_COEF09_BUF;
+ u32 L2_POLY10_READ_B_COEF10_BUF;
+ u32 L2_POLY10_READ_G_COEF00_BUF;
+ u32 L2_POLY10_READ_G_COEF01_BUF;
+ u32 L2_POLY10_READ_G_COEF02_BUF;
+ u32 L2_POLY10_READ_G_COEF03_BUF;
+ u32 L2_POLY10_READ_G_COEF04_BUF;
+ u32 L2_POLY10_READ_G_COEF05_BUF;
+ u32 L2_POLY10_READ_G_COEF06_BUF;
+ u32 L2_POLY10_READ_G_COEF07_BUF;
+ u32 L2_POLY10_READ_G_COEF08_BUF;
+ u32 L2_POLY10_READ_G_COEF09_BUF;
+ u32 L2_POLY10_READ_G_COEF10_BUF;
+ u32 L2_POLY10_READ_R_COEF00_BUF;
+ u32 L2_POLY10_READ_R_COEF01_BUF;
+ u32 L2_POLY10_READ_R_COEF02_BUF;
+ u32 L2_POLY10_READ_R_COEF03_BUF;
+ u32 L2_POLY10_READ_R_COEF04_BUF;
+ u32 L2_POLY10_READ_R_COEF05_BUF;
+ u32 L2_POLY10_READ_R_COEF06_BUF;
+ u32 L2_POLY10_READ_R_COEF07_BUF;
+ u32 L2_POLY10_READ_R_COEF08_BUF;
+ u32 L2_POLY10_READ_R_COEF09_BUF;
+ u32 L2_POLY10_READ_R_COEF10_BUF;
+ u32 RESERVED_B_64[10];
+ u32 L2_POST0_CAP_OFFSET_BUF;
+ u32 L2_POST0_CAP_SIZE_BUF;
+ u32 L2_POST0_HALF_SCALE_EN_BUF;
+ u32 RESERVED_B_65[17];
+ u32 L2_POST0_GAMMA_M_BUF;
+ u32 RESERVED_B_66[3];
+ u32 L2_POST0_C_SELECT_BUF;
+ u32 RESERVED_B_67[3];
+ u32 L2_POST0_MTB_BUF;
+ u32 RESERVED_B_68[3];
+ u32 L2_POST0_MTB_YG_OFFSETI_BUF;
+ u32 L2_POST0_MTB_YG1_BUF;
+ u32 L2_POST0_MTB_YG2_BUF;
+ u32 L2_POST0_MTB_YG_OFFSETO_BUF;
+ u32 L2_POST0_MTB_CB_OFFSETI_BUF;
+ u32 L2_POST0_MTB_CB1_BUF;
+ u32 L2_POST0_MTB_CB2_BUF;
+ u32 L2_POST0_MTB_CB_OFFSETO_BUF;
+ u32 L2_POST0_MTB_CR_OFFSETI_BUF;
+ u32 L2_POST0_MTB_CR1_BUF;
+ u32 L2_POST0_MTB_CR2_BUF;
+ u32 L2_POST0_MTB_CR_OFFSETO_BUF;
+ u32 L2_POST0_OPORTALP_BUF;
+ u32 L2_POST0_OPORTFMT_BUF;
+ u32 RESERVED_B_69[3];
+ u32 L2_POST0_OUT_PITCH_B_BUF;
+ u32 L2_POST0_OUT_PITCH_G_BUF;
+ u32 L2_POST0_OUT_PITCH_R_BUF;
+ u32 L2_POST0_DUMMY_READ_EN_BUF;
+ u32 RESERVED_B_70[11];
+ u32 L2_POST1_CAP_OFFSET_BUF;
+ u32 L2_POST1_CAP_SIZE_BUF;
+ u32 L2_POST1_HALF_SCALE_EN_BUF;
+ u32 RESERVED_B_71[17];
+ u32 L2_POST1_GAMMA_M_BUF;
+ u32 RESERVED_B_72[3];
+ u32 L2_POST1_C_SELECT_BUF;
+ u32 RESERVED_B_73[3];
+ u32 L2_POST1_MTB_BUF;
+ u32 RESERVED_B_74[3];
+ u32 L2_POST1_MTB_YG_OFFSETI_BUF;
+ u32 L2_POST1_MTB_YG1_BUF;
+ u32 L2_POST1_MTB_YG2_BUF;
+ u32 L2_POST1_MTB_YG_OFFSETO_BUF;
+ u32 L2_POST1_MTB_CB_OFFSETI_BUF;
+ u32 L2_POST1_MTB_CB1_BUF;
+ u32 L2_POST1_MTB_CB2_BUF;
+ u32 L2_POST1_MTB_CB_OFFSETO_BUF;
+ u32 L2_POST1_MTB_CR_OFFSETI_BUF;
+ u32 L2_POST1_MTB_CR1_BUF;
+ u32 L2_POST1_MTB_CR2_BUF;
+ u32 L2_POST1_MTB_CR_OFFSETO_BUF;
+ u32 L2_POST1_OPORTALP_BUF;
+ u32 L2_POST1_OPORTFMT_BUF;
+ u32 RESERVED_B_75[3];
+ u32 L2_POST1_OUT_PITCH_B_BUF;
+ u32 L2_POST1_OUT_PITCH_G_BUF;
+ u32 L2_POST1_OUT_PITCH_R_BUF;
+ u32 L2_POST1_DUMMY_READ_EN_BUF;
+ u32 RESERVED_B_76[64];
+};
+
+/**
+ * struct hwd_viif_capture_reg - Registers for VIIF CAPTURE control
+ */
+struct hwd_viif_capture_reg {
+ struct hwd_viif_system_reg sys;
+ struct hwd_viif_vdm_reg vdm;
+ struct hwd_viif_l1isp_reg l1isp;
+ struct hwd_viif_l2isp_reg l2isp;
+};
+
+#endif /* HWD_VIIF_REG_H */
diff --git a/include/uapi/linux/visconti_viif.h b/include/uapi/linux/visconti_viif.h
new file mode 100644
index 00000000000..f92278425b7
--- /dev/null
+++ b/include/uapi/linux/visconti_viif.h
@@ -0,0 +1,1724 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#ifndef __UAPI_VISCONTI_VIIF_H_
+#define __UAPI_VISCONTI_VIIF_H_
+
+#include <linux/types.h>
+#include <linux/videodev2.h>
+
+/* Visconti specific compound controls */
+#define V4L2_CID_VISCONTI_VIIF_BASE (V4L2_CID_USER_BASE + 0x1000)
+#define V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 1)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 2)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF (V4L2_CID_VISCONTI_VIIF_BASE + 3)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 4)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG (V4L2_CID_VISCONTI_VIIF_BASE + 5)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE (V4L2_CID_VISCONTI_VIIF_BASE + 6)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION (V4L2_CID_VISCONTI_VIIF_BASE + 7)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC (V4L2_CID_VISCONTI_VIIF_BASE + 8)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE (V4L2_CID_VISCONTI_VIIF_BASE + 9)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION \
+ (V4L2_CID_VISCONTI_VIIF_BASE + 10)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS (V4L2_CID_VISCONTI_VIIF_BASE + 11)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION (V4L2_CID_VISCONTI_VIIF_BASE + 12)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC (V4L2_CID_VISCONTI_VIIF_BASE + 13)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS (V4L2_CID_VISCONTI_VIIF_BASE + 14)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB (V4L2_CID_VISCONTI_VIIF_BASE + 15)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN (V4L2_CID_VISCONTI_VIIF_BASE + 16)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC (V4L2_CID_VISCONTI_VIIF_BASE + 17)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM (V4L2_CID_VISCONTI_VIIF_BASE + 18)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 19)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT (V4L2_CID_VISCONTI_VIIF_BASE + 20)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION (V4L2_CID_VISCONTI_VIIF_BASE + 21)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST (V4L2_CID_VISCONTI_VIIF_BASE + 22)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI (V4L2_CID_VISCONTI_VIIF_BASE + 23)
+#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 24)
+#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 25)
+#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 26)
+#define V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 27)
+#define V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS (V4L2_CID_VISCONTI_VIIF_BASE + 28)
+
+/* Enable/Disable flag */
+#define VIIF_DISABLE (0U)
+#define VIIF_ENABLE (1U)
+
+/**
+ * enum viif_rawpack_mode - RAW pack mode for ioctl(VIDIOC_VIIF_MAIN_SET_RAWPACK_MODE)
+ *
+ * @VIIF_RAWPACK_DISABLE: RAW pack disable
+ * @VIIF_RAWPACK_MSBFIRST: RAW pack enable (MSB First)
+ * @VIIF_RAWPACK_LSBFIRST: RAW pack enable (LSB First)
+ */
+enum viif_rawpack_mode {
+ VIIF_RAWPACK_DISABLE = 0,
+ VIIF_RAWPACK_MSBFIRST = 2,
+ VIIF_RAWPACK_LSBFIRST = 3,
+};
+
+/**
+ * enum viif_l1_input - L1ISP preprocessing mode
+ *
+ * @VIIF_L1_INPUT_HDR: bypass(HDR input)
+ * @VIIF_L1_INPUT_PWL: HDRE(PWL input)
+ * @VIIF_L1_INPUT_HDR_IMG_CORRECT: SLIC-ABPC-PWHB-RCNR-HDRS
+ * @VIIF_L1_INPUT_PWL_IMG_CORRECT: HDRE-SLIC-ABPC-PWHB-RCNR-HDRS
+ */
+enum viif_l1_input {
+ VIIF_L1_INPUT_HDR = 0,
+ VIIF_L1_INPUT_PWL = 1,
+ VIIF_L1_INPUT_HDR_IMG_CORRECT = 3,
+ VIIF_L1_INPUT_PWL_IMG_CORRECT = 4,
+};
+
+/**
+ * enum viif_l1_raw - L1ISP RAW color filter mode
+ *
+ * @VIIF_L1_RAW_GR_R_B_GB: Gr-R-B-Gb
+ * @VIIF_L1_RAW_R_GR_GB_B: R-Gr-Gb-B
+ * @VIIF_L1_RAW_B_GB_GR_R: B-Gb-Gr-R
+ * @VIIF_L1_RAW_GB_B_R_GR: Gb-B-R-Gr
+ */
+enum viif_l1_raw {
+ VIIF_L1_RAW_GR_R_B_GB = 0,
+ VIIF_L1_RAW_R_GR_GB_B = 1,
+ VIIF_L1_RAW_B_GB_GR_R = 2,
+ VIIF_L1_RAW_GB_B_R_GR = 3,
+};
+
+/**
+ * struct viif_l1_input_mode_config - L1ISP INPUT MODE parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE`
+ * @mode: &enum viif_l1_input value.
+ * @depth: Color depth (even only). Range for each L1ISP pre-processing mode is:
+ *
+ * * VIIF_L1_INPUT_HDR/HDR_IMG_CORRECT: Range: [8..24].
+ * * VIIF_L1_INPUT_PWL/PWL_IMG_CORRECT: Range: [8..14].
+ * @raw_color_filter: &enum viif_l1_raw value.
+ */
+struct viif_l1_input_mode_config {
+ __u32 mode;
+ __u32 depth;
+ __u32 raw_color_filter;
+};
+
+/**
+ * struct viif_l1_rgb_to_y_coef_config - L1ISP coefficient for calculating
+ * Y from RGB parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF`
+ * @coef_r: R co-efficient [256..65024] accuracy: 1/65536
+ * @coef_g: R co-efficient [256..65024] accuracy: 1/65536
+ * @coef_b: R co-efficient [256..65024] accuracy: 1/65536
+ */
+struct viif_l1_rgb_to_y_coef_config {
+ __u16 coef_r;
+ __u16 coef_g;
+ __u16 coef_b;
+};
+
+/**
+ * enum viif_l1_img_sensitivity_mode - L1ISP image sensitivity
+ *
+ * @VIIF_L1_IMG_SENSITIVITY_HIGH: high sensitivity
+ * @VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED: middle sensitivity or led
+ * @VIIF_L1_IMG_SENSITIVITY_LOW: low sensitivity
+ */
+enum viif_l1_img_sensitivity_mode {
+ VIIF_L1_IMG_SENSITIVITY_HIGH = 0,
+ VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED = 1,
+ VIIF_L1_IMG_SENSITIVITY_LOW = 2,
+};
+
+/**
+ * struct viif_l1_ag_mode_config - L1ISP AG mode parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE`
+ * @sysm_ag_grad: Analog gain slope [0..255] (element is id)
+ * @sysm_ag_ofst: Analog gain offset [0..65535] (element is id)
+ * @sysm_ag_cont_hobc_en_high: 1:enable/0:disable to control analog gain
+ * for high sensitivity image of OBCC
+ * @sysm_ag_psel_hobc_high: Analog gain id for high sensitivity image of OBCC [0..3]
+ * @sysm_ag_cont_hobc_en_middle_led: 1:enable/0:disable to control analog gain
+ * for middle sensitivity or LED image of OBCC
+ * @sysm_ag_psel_hobc_middle_led: Analog gain id for middle sensitivity
+ * or LED image of OBCC [0..3]
+ * @sysm_ag_cont_hobc_en_low: 1:enable/0:disable to control analog gain
+ * for low sensitivity image of OBCC
+ * @sysm_ag_psel_hobc_low: Analog gain id for low sensitivity image of OBCC [0..3]
+ * @sysm_ag_cont_abpc_en_high: 1:enable/0:disable to control analog gain
+ * for high sensitivity image of ABPC
+ * @sysm_ag_psel_abpc_high: Analog gain id for high sensitivity image of ABPC [0..3]
+ * @sysm_ag_cont_abpc_en_middle_led: 1:enable/0:disable to control analog gain
+ * for middle sensitivity or LED image of ABPC
+ * @sysm_ag_psel_abpc_middle_led: Analog gain id for middle sensitivity
+ * or LED image of ABPC [0..3]
+ * @sysm_ag_cont_abpc_en_low: 1:enable/0:disable to control analog gain
+ * for low sensitivity image of ABPC
+ * @sysm_ag_psel_abpc_low: Analog gain id for low sensitivity image of ABPC [0..3]
+ * @sysm_ag_cont_rcnr_en_high: 1:enable/0:disable to control analog gain
+ * for high sensitivity image of RCNR
+ * @sysm_ag_psel_rcnr_high: Analog gain id for high sensitivity image of RCNR [0..3]
+ * @sysm_ag_cont_rcnr_en_middle_led: 1:enable/0:disable to control analog gain
+ * for middle sensitivity or LED image of RCNR
+ * @sysm_ag_psel_rcnr_middle_led: Analog gain id for middle sensitivity
+ * or LED image of RCNR [0..3]
+ * @sysm_ag_cont_rcnr_en_low: 1:enable/0:disable to control analog gain
+ * for low sensitivity image of RCNR
+ * @sysm_ag_psel_rcnr_low: Analog gain id for low sensitivity image of RCNR [0..3]
+ * @sysm_ag_cont_lssc_en: 1:enable/0:disable to control analog gain for LSC
+ * @sysm_ag_ssel_lssc: &enum viif_l1_img_sensitivity_mode value. Sensitive image used for LSC.
+ * @sysm_ag_psel_lssc: Analog gain id for LSC [0..3]
+ * @sysm_ag_cont_mpro_en: 1:enable/0:disable to control analog gain for color matrix
+ * @sysm_ag_ssel_mpro: &enum viif_l1_img_sensitivity_mode value.
+ * Sensitive image used for color matrix.
+ * @sysm_ag_psel_mpro:Aanalog gain id for color matrix [0..3]
+ * @sysm_ag_cont_vpro_en: 1:enable/0:disable to control analog gain for image adjustment
+ * @sysm_ag_ssel_vpro: &enum viif_l1_img_sensitivity_mode value.
+ * Sensitive image used for image adjustment.
+ * @sysm_ag_psel_vpro: Analog gain id for image adjustment [0..3]
+ * @sysm_ag_cont_hobc_test_high: Manual analog gain for high sensitivity image
+ * of OBCC [0..255]
+ * @sysm_ag_cont_hobc_test_middle_led: Manual analog gain for middle sensitivity
+ * or led image of OBCC [0..255]
+ * @sysm_ag_cont_hobc_test_low: Manual analog gain for low sensitivity image
+ * of OBCC [0..255]
+ * @sysm_ag_cont_abpc_test_high: Manual analog gain for high sensitivity image
+ * of ABPC [0..255]
+ * @sysm_ag_cont_abpc_test_middle_led: Manual analog gain for middle sensitivity
+ * or led image of ABPC [0..255]
+ * @sysm_ag_cont_abpc_test_low: Manual analog gain for low sensitivity image
+ * of ABPC [0..255]
+ * @sysm_ag_cont_rcnr_test_high: Manual analog gain for high sensitivity image
+ * of RCNR [0..255]
+ * @sysm_ag_cont_rcnr_test_middle_led: Manual analog gain for middle sensitivity
+ * or led image of RCNR [0..255]
+ * @sysm_ag_cont_rcnr_test_low: Manual analog gain for low sensitivity image
+ * of RCNR [0..255]
+ * @sysm_ag_cont_lssc_test: Manual analog gain for LSSC [0..255]
+ * @sysm_ag_cont_mpro_test: Manual analog gain for color matrix [0..255]
+ * @sysm_ag_cont_vpro_test: Manual analog gain for image adjustment [0..255]
+ *
+ * Operation setting of L1ISP analog gain function.
+ * Analog gain control is disabled if following settings are done.
+ * "sysm_ag_cont_*_en = DRV_VIIF_DISABLE" and "sysm_ag_cont_*_test = 0"
+ * In case "VIIF_L1_INPUT_HDR" or "VIIF_L1_INPUT_PWL" is set to "mode" which is
+ * an &struct viif_l1_input_mode_config, analog gain control needs to be disabled.
+ * Even if this condition is not satisfied, this driver doesn't return error.
+ *
+ * The value set in sysm_ag_psel_xxx indicates analog gain system to be used and
+ * corresponds to the element number of sysm_ag_grad and sysm_ag_ofst.
+ * For example, if sysm_ag_psel_hobc_high is set to 2, then values set in
+ * sysm_ag_grad[2] and sysm_ag_ofst[2] are used for high sensitivity images
+ * in OBCC processing.
+ */
+struct viif_l1_ag_mode_config {
+ __u8 sysm_ag_grad[4];
+ __u16 sysm_ag_ofst[4];
+ __u32 sysm_ag_cont_hobc_en_high;
+ __u32 sysm_ag_psel_hobc_high;
+ __u32 sysm_ag_cont_hobc_en_middle_led;
+ __u32 sysm_ag_psel_hobc_middle_led;
+ __u32 sysm_ag_cont_hobc_en_low;
+ __u32 sysm_ag_psel_hobc_low;
+ __u32 sysm_ag_cont_abpc_en_high;
+ __u32 sysm_ag_psel_abpc_high;
+ __u32 sysm_ag_cont_abpc_en_middle_led;
+ __u32 sysm_ag_psel_abpc_middle_led;
+ __u32 sysm_ag_cont_abpc_en_low;
+ __u32 sysm_ag_psel_abpc_low;
+ __u32 sysm_ag_cont_rcnr_en_high;
+ __u32 sysm_ag_psel_rcnr_high;
+ __u32 sysm_ag_cont_rcnr_en_middle_led;
+ __u32 sysm_ag_psel_rcnr_middle_led;
+ __u32 sysm_ag_cont_rcnr_en_low;
+ __u32 sysm_ag_psel_rcnr_low;
+ __u32 sysm_ag_cont_lssc_en;
+ __u32 sysm_ag_ssel_lssc;
+ __u32 sysm_ag_psel_lssc;
+ __u32 sysm_ag_cont_mpro_en;
+ __u32 sysm_ag_ssel_mpro;
+ __u32 sysm_ag_psel_mpro;
+ __u32 sysm_ag_cont_vpro_en;
+ __u32 sysm_ag_ssel_vpro;
+ __u32 sysm_ag_psel_vpro;
+ __u8 sysm_ag_cont_hobc_test_high;
+ __u8 sysm_ag_cont_hobc_test_middle_led;
+ __u8 sysm_ag_cont_hobc_test_low;
+ __u8 sysm_ag_cont_abpc_test_high;
+ __u8 sysm_ag_cont_abpc_test_middle_led;
+ __u8 sysm_ag_cont_abpc_test_low;
+ __u8 sysm_ag_cont_rcnr_test_high;
+ __u8 sysm_ag_cont_rcnr_test_middle_led;
+ __u8 sysm_ag_cont_rcnr_test_low;
+ __u8 sysm_ag_cont_lssc_test;
+ __u8 sysm_ag_cont_mpro_test;
+ __u8 sysm_ag_cont_vpro_test;
+};
+
+/**
+ * struct viif_l1_ag_config - L1ISP AG parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG`
+ * @gain_h: Analog gain for high sensitive image [0..65535]
+ * @gain_m: Analog gain for middle sensitive image or LED image [0..65535]
+ * @gain_l: Analog gain for low sensitive image [0..65535]
+ */
+struct viif_l1_ag_config {
+ __u16 gain_h;
+ __u16 gain_m;
+ __u16 gain_l;
+};
+
+/**
+ * struct viif_l1_hdre_config - L1ISP HDRE parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE`
+ * @hdre_src_point: Knee point N value of PWL compressed signal [0..0x3FFF]
+ * @hdre_dst_base: Offset value of HDR signal in Knee area M [0..0xFFFFFF]
+ * @hdre_ratio: Slope of output pixel value in Knee area M
+ * [0..0x3FFFFF], accuracy: 1/64
+ * @hdre_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
+ */
+struct viif_l1_hdre_config {
+ __u32 hdre_src_point[16];
+ __u32 hdre_dst_base[17];
+ __u32 hdre_ratio[17];
+ __u32 hdre_dst_max_val;
+};
+
+/**
+ * struct viif_l1_img_extraction_config - L1ISP image extraction parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION`
+ * @input_black_gr: Black level of input pixel (Gr) [0..0xFFFFFF]
+ * @input_black_r: Black level of input pixel (R) [0..0xFFFFFF]
+ * @input_black_b: Black level of input pixel (B) [0..0xFFFFFF]
+ * @input_black_gb: Black level of input pixel (Gb) [0..0xFFFFFF]
+ */
+struct viif_l1_img_extraction_config {
+ __u32 input_black_gr;
+ __u32 input_black_r;
+ __u32 input_black_b;
+ __u32 input_black_gb;
+};
+
+/**
+ * enum viif_l1_dpc_mode - L1ISP defect pixel correction mode
+ * @VIIF_L1_DPC_1PIXEL: 1 pixel correction mode
+ * @VIIF_L1_DPC_2PIXEL: 2 pixel correction mode
+ */
+enum viif_l1_dpc_mode {
+ VIIF_L1_DPC_1PIXEL = 0,
+ VIIF_L1_DPC_2PIXEL = 1,
+};
+
+/**
+ * struct viif_l1_dpc - L1ISP defect pixel correction parameters
+ * for &struct viif_l1_dpc_config
+ * @abpc_sta_en: 1:enable/0:disable setting of Static DPC
+ * @abpc_dyn_en: 1:enable/0:disable setting of Dynamic DPC
+ * @abpc_dyn_mode: &enume viif_l1_dpc_mode value. Sets dynamic DPC mode.
+ * @abpc_ratio_limit: Variation adjustment of dynamic DPC [0..1023]
+ * @abpc_dark_limit: White defect judgment limit of dark area [0..1023]
+ * @abpc_sn_coef_w_ag_min: Luminance difference adjustment of white DPC
+ * (undere lower threshold) [1..31]
+ * @abpc_sn_coef_w_ag_mid: Luminance difference adjustment of white DPC
+ * (between lower and upper threshold) [1..31]
+ * @abpc_sn_coef_w_ag_max: Luminance difference adjustment of white DPC
+ * (over upper threshold) [1..31]
+ * @abpc_sn_coef_b_ag_min: Luminance difference adjustment of black DPC
+ * (undere lower threshold) [1..31]
+ * @abpc_sn_coef_b_ag_mid: Luminance difference adjustment of black DPC
+ * (between lower and upper threshold) [1..31]
+ * @abpc_sn_coef_b_ag_max: Luminance difference adjustment of black DPC
+ * (over upper threshold) [1..31]
+ * @abpc_sn_coef_w_th_min: Luminance difference adjustment of white DPC
+ * analog gain lower threshold [0..255]
+ * @abpc_sn_coef_w_th_max: Luminance difference adjustment of white DPC
+ * analog gain upper threshold [0..255]
+ * @abpc_sn_coef_b_th_min: Luminance difference adjustment of black DPC
+ * analog gain lower threshold [0..255]
+ * @abpc_sn_coef_b_th_max: Luminance difference adjustment of black DPC
+ * analog gain upper threshold [0..255]
+ *
+ * Parameters should meet the following conditions.
+ * "abpc_sn_coef_w_th_min < abpc_sn_coef_w_th_max" and
+ * "abpc_sn_coef_b_th_min < abpc_sn_coef_b_th_max"
+ */
+struct viif_l1_dpc {
+ __u32 abpc_sta_en;
+ __u32 abpc_dyn_en;
+ __u32 abpc_dyn_mode;
+ __u32 abpc_ratio_limit;
+ __u32 abpc_dark_limit;
+ __u32 abpc_sn_coef_w_ag_min;
+ __u32 abpc_sn_coef_w_ag_mid;
+ __u32 abpc_sn_coef_w_ag_max;
+ __u32 abpc_sn_coef_b_ag_min;
+ __u32 abpc_sn_coef_b_ag_mid;
+ __u32 abpc_sn_coef_b_ag_max;
+ __u8 abpc_sn_coef_w_th_min;
+ __u8 abpc_sn_coef_w_th_max;
+ __u8 abpc_sn_coef_b_th_min;
+ __u8 abpc_sn_coef_b_th_max;
+};
+
+/**
+ * struct viif_l1_dpc_config - L1ISP defect pixel correction parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC`
+ * @param_h: DPC parameter for high sensitive image. Refer to &struct viif_l1_dpc
+ * @param_m: DPC parameter for middle sensitive image. Refer to &struct viif_l1_dpc
+ * @param_l: DPC parameter for low sensitive image. Refer to &struct viif_l1_dpc
+ * @table_h_addr: DPC table address for high sensitive image.
+ * The table size is sizeof(u32) * 2048.
+ * Set zero to disable this table.
+ * @table_m_addr: DPC table address for middle sensitive image or LED image.
+ * The table size is sizeof(u32) * 2048.
+ * Set zero to disable this table.
+ * @table_l_addr: DPC table address for low sensitive image.
+ * The table size is sizeof(u32) * 2048.
+ * Set zero to disable this table.
+ *
+ * The size of each table is fixed at 8192 Byte.
+ * Application should make sure that the table data is based on HW specification
+ * since this driver does not check the DPC table.
+ */
+struct viif_l1_dpc_config {
+ struct viif_l1_dpc param_h;
+ struct viif_l1_dpc param_m;
+ struct viif_l1_dpc param_l;
+ __u64 table_h_addr;
+ __u64 table_m_addr;
+ __u64 table_l_addr;
+};
+
+/**
+ * struct viif_l1_preset_wb - L1ISP preset white balance parameters
+ * for &struct viif_l1_preset_white_balance_config
+ * @gain_gr: Gr gain [0..524287], accuracy 1/16384
+ * @gain_r: R gain [0..524287], accuracy 1/16384
+ * @gain_b: B gain [0..524287], accuracy 1/16384
+ * @gain_gb: Gb gain [0..524287], accuracy 1/16384
+ */
+struct viif_l1_preset_wb {
+ __u32 gain_gr;
+ __u32 gain_r;
+ __u32 gain_b;
+ __u32 gain_gb;
+};
+
+/**
+ * struct viif_l1_preset_white_balance_config - L1ISP preset white balance
+ * parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE`
+ * @dstmaxval: Maximum value of output pixel [pixel] [0..4095]
+ * @param_h: Preset white balance parameter for high sensitive image.
+ * Refer to &struct viif_l1_preset_wb
+ * @param_m: Preset white balance parameters for middle sensitive image or LED image.
+ * Refer to &struct viif_l1_preset_wb
+ * @param_l: Preset white balance parameters for low sensitive image.
+ * Refer to &struct viif_l1_preset_wb
+ */
+struct viif_l1_preset_white_balance_config {
+ __u32 dstmaxval;
+ struct viif_l1_preset_wb param_h;
+ struct viif_l1_preset_wb param_m;
+ struct viif_l1_preset_wb param_l;
+};
+
+/**
+ * enum viif_l1_rcnr_type - L1ISP high resolution luminance filter type
+ *
+ * @VIIF_L1_RCNR_LOW_RESOLUTION: low resolution
+ * @VIIF_L1_RCNR_MIDDLE_RESOLUTION: middle resolution
+ * @VIIF_L1_RCNR_HIGH_RESOLUTION: high resolution
+ * @VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION: ultra high resolution
+ */
+enum viif_l1_rcnr_type {
+ VIIF_L1_RCNR_LOW_RESOLUTION = 0,
+ VIIF_L1_RCNR_MIDDLE_RESOLUTION = 1,
+ VIIF_L1_RCNR_HIGH_RESOLUTION = 2,
+ VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION = 3,
+};
+
+/**
+ * enum viif_l1_msf_blend_ratio - L1ISP MSF blend ratio
+ *
+ * @VIIF_L1_MSF_BLEND_RATIO_0_DIV_64: 0/64
+ * @VIIF_L1_MSF_BLEND_RATIO_1_DIV_64: 1/64
+ * @VIIF_L1_MSF_BLEND_RATIO_2_DIV_64: 2/64
+ */
+enum viif_l1_msf_blend_ratio {
+ VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 = 0,
+ VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 = 1,
+ VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 = 2,
+};
+
+/**
+ * struct viif_l1_raw_color_noise_reduction - L1ISP RCNR parameters
+ * for &struct viif_l1_raw_color_noise_reduction_config
+ * @rcnr_sw: 1:Enable/0:Disable setting of RAW color noise reduction
+ * @rcnr_cnf_dark_ag0: Maximum value of LSF dark noise adjustment[0..63]
+ * @rcnr_cnf_dark_ag1: Middle value of LSF dark noise adjustment [0..63]
+ * @rcnr_cnf_dark_ag2: Minimum value of LSF dark noise adjustment [0..63]
+ * @rcnr_cnf_ratio_ag0: Maximum value of LSF luminance interlocking noise adjustment [0..31]
+ * @rcnr_cnf_ratio_ag1: Middle value of LSF luminance interlocking noise adjustment [0..31]
+ * @rcnr_cnf_ratio_ag2: Minimum value of LSF luminance interlocking noise adjustment [0..31]
+ * @rcnr_cnf_clip_gain_r: LSF color correction limit adjustment gain R [0..3]
+ * @rcnr_cnf_clip_gain_g: LSF color correction limit adjustment gain G [0..3]
+ * @rcnr_cnf_clip_gain_b: LSF color correction limit adjustment gain B [0..3]
+ * @rcnr_a1l_dark_ag0: Maximum value of MSF dark noise adjustment [0..63]
+ * @rcnr_a1l_dark_ag1: Middle value of MSF dark noise adjustment [0..63]
+ * @rcnr_a1l_dark_ag2: Minimum value of MSF dark noise adjustment [0..63]
+ * @rcnr_a1l_ratio_ag0: Maximum value of MSF luminance interlocking noise adjustment [0..31]
+ * @rcnr_a1l_ratio_ag1: Middle value of MSF luminance interlocking noise adjustment [0..31]
+ * @rcnr_a1l_ratio_ag2: Minimum value of MSF luminance interlocking noise adjustment [0..31]
+ * @rcnr_inf_zero_clip: Input stage zero clip setting [0..256]
+ * @rcnr_merge_d2blend_ag0: Maximum value of filter results and input blend ratio [0..16]
+ * @rcnr_merge_d2blend_ag1: Middle value of filter results and input blend ratio [0..16]
+ * @rcnr_merge_d2blend_ag2: Minimum value of filter results and input blend ratio [0..16]
+ * @rcnr_merge_black: Black level minimum value [0..64]
+ * @rcnr_merge_mindiv: 0 div guard value of inverse arithmetic unit [4..16]
+ * @rcnr_hry_type: &enum viif_l1_rcnr_type value. Filter type for HSF filter process.
+ * @rcnr_anf_blend_ag0: &enum viif_l1_msf_blend_ratio value.
+ * Maximum value of MSF result blend ratio in write back data to line memory.
+ * @rcnr_anf_blend_ag1: &enum viif_l1_msf_blend_ratio value.
+ * Middle value of MSF result blend ratio in write back data to line memory.
+ * @rcnr_anf_blend_ag2: &enum viif_l1_msf_blend_ratio value.
+ * Minimum value of MSF result blend ratio in write back data to line memory.
+ * @rcnr_lpf_threshold: Multiplier value for calculating dark noise / luminance
+ * interlock noise of MSF [0..31], accuracy: 1/8
+ * @rcnr_merge_hlblend_ag0: Maximum value of luminance signal generation blend [0..2]
+ * @rcnr_merge_hlblend_ag1: Middle value of luminance signal generation blend [0..2]
+ * @rcnr_merge_hlblend_ag2: Minimum value of luminance signal generation blend [0..2]
+ * @rcnr_gnr_sw: 1:Enable/0:Disable setting of Gr/Gb sensitivity ratio
+ * correction function switching
+ * @rcnr_gnr_ratio: Upper limit of Gr/Gb sensitivity ratio correction factor [0..15]
+ * @rcnr_gnr_wide_en: 1:Enable/0:Disable setting of the function to double
+ * correction upper limit ratio of rcnr_gnr_ratio
+ */
+struct viif_l1_raw_color_noise_reduction {
+ __u32 rcnr_sw;
+ __u32 rcnr_cnf_dark_ag0;
+ __u32 rcnr_cnf_dark_ag1;
+ __u32 rcnr_cnf_dark_ag2;
+ __u32 rcnr_cnf_ratio_ag0;
+ __u32 rcnr_cnf_ratio_ag1;
+ __u32 rcnr_cnf_ratio_ag2;
+ __u32 rcnr_cnf_clip_gain_r;
+ __u32 rcnr_cnf_clip_gain_g;
+ __u32 rcnr_cnf_clip_gain_b;
+ __u32 rcnr_a1l_dark_ag0;
+ __u32 rcnr_a1l_dark_ag1;
+ __u32 rcnr_a1l_dark_ag2;
+ __u32 rcnr_a1l_ratio_ag0;
+ __u32 rcnr_a1l_ratio_ag1;
+ __u32 rcnr_a1l_ratio_ag2;
+ __u32 rcnr_inf_zero_clip;
+ __u32 rcnr_merge_d2blend_ag0;
+ __u32 rcnr_merge_d2blend_ag1;
+ __u32 rcnr_merge_d2blend_ag2;
+ __u32 rcnr_merge_black;
+ __u32 rcnr_merge_mindiv;
+ __u32 rcnr_hry_type;
+ __u32 rcnr_anf_blend_ag0;
+ __u32 rcnr_anf_blend_ag1;
+ __u32 rcnr_anf_blend_ag2;
+ __u32 rcnr_lpf_threshold;
+ __u32 rcnr_merge_hlblend_ag0;
+ __u32 rcnr_merge_hlblend_ag1;
+ __u32 rcnr_merge_hlblend_ag2;
+ __u32 rcnr_gnr_sw;
+ __u32 rcnr_gnr_ratio;
+ __u32 rcnr_gnr_wide_en;
+};
+
+/**
+ * struct viif_l1_raw_color_noise_reduction_config - L1ISP RCNR parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION`
+ * @param_h: RAW color noise reduction parameter for high sensitive image.
+ * Refer to &struct viif_l1_raw_color_noise_reduction
+ * @param_m: RAW color noise reduction parameter for middle sensitive image or LED image.
+ * Refer to &struct viif_l1_raw_color_noise_reduction
+ * @param_l: RAW color noise reduction parameter for low sensitive image.
+ * Refer to &struct viif_l1_raw_color_noise_reduction
+ */
+struct viif_l1_raw_color_noise_reduction_config {
+ struct viif_l1_raw_color_noise_reduction param_h;
+ struct viif_l1_raw_color_noise_reduction param_m;
+ struct viif_l1_raw_color_noise_reduction param_l;
+};
+
+/**
+ * enum viif_l1_hdrs_middle_img_mode - L1ISP HDR setting
+ *
+ * @VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE: not use middle image
+ * @VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE: use middle image
+ */
+enum viif_l1_hdrs_middle_img_mode {
+ VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE = 0,
+ VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE = 1,
+};
+
+/**
+ * struct viif_l1_hdrs_config - L1ISP HDRS parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS`
+ * @hdrs_hdr_mode: &enum viif_l1_hdrs_middle_img_mode value.
+ * Use/No use settings of middle sensitivity image in HDRS.
+ * @hdrs_hdr_ratio_m: Magnification ratio of middle sensitivity image for high
+ * sensitivity image [0x400..0x400000] accuracy: 1/1024
+ * @hdrs_hdr_ratio_l: Magnification ratio of low sensitivity image for high
+ * sensitivity image [0x400..0x400000], accuracy: 1/1024
+ * @hdrs_hdr_ratio_e: Magnification ratio of LED image for high sensitivity image
+ * [0x400..0x400000], accuracy: 1/1024
+ * @hdrs_dg_h: High sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
+ * @hdrs_dg_m: Middle sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
+ * @hdrs_dg_l: Low sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
+ * @hdrs_dg_e: LED image digital gain [0..0x3FFFFF], accuracy: 1/1024
+ * @hdrs_blendend_h: Maximum luminance used for blend high sensitivity image [0..4095]
+ * @hdrs_blendend_m: Maximum luminance used for blend middle sensitivity image [0..4095]
+ * @hdrs_blendend_e: Maximum luminance used for blend LED image [0..4095]
+ * @hdrs_blendbeg_h: Minimum luminance used for blend high sensitivity image [0..4095]
+ * @hdrs_blendbeg_m: Minimum luminance used for blend middle sensitivity image [0..4095]
+ * @hdrs_blendbeg_e: Minimum luminance used for blend LED image [0..4095]
+ * @hdrs_led_mode_on: 1:Enable/0:Disable settings of LED mode
+ * @hdrs_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
+ *
+ * parameter error needs to be returned in the below condition.
+ * (hdrs_hdr_mode == VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) && (hdrs_led_mode_on == 1)
+ */
+struct viif_l1_hdrs_config {
+ __u32 hdrs_hdr_mode;
+ __u32 hdrs_hdr_ratio_m;
+ __u32 hdrs_hdr_ratio_l;
+ __u32 hdrs_hdr_ratio_e;
+ __u32 hdrs_dg_h;
+ __u32 hdrs_dg_m;
+ __u32 hdrs_dg_l;
+ __u32 hdrs_dg_e;
+ __u32 hdrs_blendend_h;
+ __u32 hdrs_blendend_m;
+ __u32 hdrs_blendend_e;
+ __u32 hdrs_blendbeg_h;
+ __u32 hdrs_blendbeg_m;
+ __u32 hdrs_blendbeg_e;
+ __u32 hdrs_led_mode_on;
+ __u32 hdrs_dst_max_val;
+};
+
+/**
+ * struct viif_l1_black_level_correction_config - L1ISP image level conversion
+ * parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION`
+ * @srcblacklevel_gr: Black level of Gr input pixel [pixel] [0..0xFFFFFF]
+ * @srcblacklevel_r: Black level of R input pixel [pixel] [0..0xFFFFFF]
+ * @srcblacklevel_b: Black level of B input pixel [pixel] [0..0xFFFFFF]
+ * @srcblacklevel_gb: Black level of Gb input pixel [pixel] [0..0xFFFFFF]
+ * @mulval_gr: Gr gain [0..0xFFFFF], accuracy: 1/256
+ * @mulval_r: R gain [0..0xFFFFF], accuracy: 1/256
+ * @mulval_b: B gain [0..0xFFFFF], accuracy: 1/256
+ * @mulval_gb: Gb gain [0..0xFFFFF], accuracy: 1/256
+ * @dstmaxval: Maximum value of output pixel [pixel] [0..0xFFFFFF]
+ */
+struct viif_l1_black_level_correction_config {
+ __u32 srcblacklevel_gr;
+ __u32 srcblacklevel_r;
+ __u32 srcblacklevel_b;
+ __u32 srcblacklevel_gb;
+ __u32 mulval_gr;
+ __u32 mulval_r;
+ __u32 mulval_b;
+ __u32 mulval_gb;
+ __u32 dstmaxval;
+};
+
+/**
+ * enum viif_l1_para_coef_gain - L1ISP parabola shading correction coefficient ratio
+ *
+ * @VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH: 1/8
+ * @VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH: 1/4
+ * @VIIF_L1_PARA_COEF_GAIN_ONE_SECOND: 1/2
+ * @VIIF_L1_PARA_COEF_GAIN_ONE_FIRST: 1/1
+ */
+enum viif_l1_para_coef_gain {
+ VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH = 0, /* 1/8 */
+ VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH = 1, /* 1/4 */
+ VIIF_L1_PARA_COEF_GAIN_ONE_SECOND = 2, /* 1/2 */
+ VIIF_L1_PARA_COEF_GAIN_ONE_FIRST = 3, /* 1/1 */
+};
+
+/**
+ * enum viif_l1_grid_coef_gain - L1ISP grid shading correction coefficient ratio
+ *
+ * @VIIF_L1_GRID_COEF_GAIN_X1: x1
+ * @VIIF_L1_GRID_COEF_GAIN_X2: x2
+ */
+enum viif_l1_grid_coef_gain {
+ VIIF_L1_GRID_COEF_GAIN_X1 = 0,
+ VIIF_L1_GRID_COEF_GAIN_X2 = 1,
+};
+
+/**
+ * struct viif_l1_lsc_parabola_ag_param - L2ISP parabola shading parameters
+ * for &struct viif_l1_lsc_parabola_param
+ * @lssc_paracoef_h_l_max: Parabola coefficient left maximum gain value
+ * @lssc_paracoef_h_l_min: Parabola coefficient left minimum gain value
+ * @lssc_paracoef_h_r_max: Parabola coefficient right maximum gain value
+ * @lssc_paracoef_h_r_min: Parabola coefficient right minimum gain value
+ * @lssc_paracoef_v_u_max: Parabola coefficient upper maximum gain value
+ * @lssc_paracoef_v_u_min: Parabola coefficient upper minimum gain value
+ * @lssc_paracoef_v_d_max: Parabola coefficient lower maximum gain value
+ * @lssc_paracoef_v_d_min: Parabola coefficient lower minimum gain value
+ * @lssc_paracoef_hv_lu_max: Parabola coefficient upper left gain maximum value
+ * @lssc_paracoef_hv_lu_min: Parabola coefficient upper left gain minimum value
+ * @lssc_paracoef_hv_ru_max: Parabola coefficient upper right gain maximum value
+ * @lssc_paracoef_hv_ru_min: Parabola coefficient upper right minimum gain value
+ * @lssc_paracoef_hv_ld_max: Parabola coefficient lower left gain maximum value
+ * @lssc_paracoef_hv_ld_min: Parabola coefficient lower left gain minimum value
+ * @lssc_paracoef_hv_rd_max: Parabola coefficient lower right gain maximum value
+ * @lssc_paracoef_hv_rd_min: Parabola coefficient lower right minimum gain value
+ *
+ * The range and accuracy of each coefficient are as
+ * "range: [-4096..4095], accuracy: 1/256 "
+ *
+ * Each coefficient should meet the following conditions.
+ * "lssc_paracoef_xx_xx_min <= lssc_paracoef_xx_xx_max"
+ */
+struct viif_l1_lsc_parabola_ag_param {
+ __s16 lssc_paracoef_h_l_max;
+ __s16 lssc_paracoef_h_l_min;
+ __s16 lssc_paracoef_h_r_max;
+ __s16 lssc_paracoef_h_r_min;
+ __s16 lssc_paracoef_v_u_max;
+ __s16 lssc_paracoef_v_u_min;
+ __s16 lssc_paracoef_v_d_max;
+ __s16 lssc_paracoef_v_d_min;
+ __s16 lssc_paracoef_hv_lu_max;
+ __s16 lssc_paracoef_hv_lu_min;
+ __s16 lssc_paracoef_hv_ru_max;
+ __s16 lssc_paracoef_hv_ru_min;
+ __s16 lssc_paracoef_hv_ld_max;
+ __s16 lssc_paracoef_hv_ld_min;
+ __s16 lssc_paracoef_hv_rd_max;
+ __s16 lssc_paracoef_hv_rd_min;
+};
+
+/**
+ * struct viif_l1_lsc_parabola_param - L2ISP parabola shading parameters
+ * for &struct viif_l1_lsc
+ * @lssc_para_h_center: Horizontal coordinate of central optical axis [pixel]
+ * [0..(Input image width - 1)]
+ * @lssc_para_v_center: Vertical coordinate of central optical axis [line]
+ * [0..(Input image height - 1)]
+ * @lssc_para_h_gain: Horizontal distance gain with the optical axis
+ * [0..4095], accuracy: 1/256
+ * @lssc_para_v_gain: Vertical distance gain with the optical axis
+ * [0..4095], accuracy: 1/256
+ * @lssc_para_mgsel2: &enum viif_l1_para_coef_gain value.
+ * Parabola 2D correction coefficient gain magnification ratio.
+ * @lssc_para_mgsel4: &enum viif_l1_para_coef_gain value.
+ * Parabola 4D correction coefficient gain magnification ratio.
+ * @r_2d: 2D parabola coefficient for R.
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @r_4d: 4D parabola coefficient for R.
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @gr_2d: 2D parabola coefficient for Gr
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @gr_4d: 4D parabola coefficient for Gr
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @gb_2d: 2D parabola coefficient for Gb
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @gb_4d: 4D parabola coefficient for Gb
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @b_2d: 2D parabola coefficient for B
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ * @b_4d: 4D parabola coefficient for B
+ * Refer to &struct viif_l1_lsc_parabola_ag_param
+ */
+struct viif_l1_lsc_parabola_param {
+ __u32 lssc_para_h_center;
+ __u32 lssc_para_v_center;
+ __u32 lssc_para_h_gain;
+ __u32 lssc_para_v_gain;
+ __u32 lssc_para_mgsel2;
+ __u32 lssc_para_mgsel4;
+ struct viif_l1_lsc_parabola_ag_param r_2d;
+ struct viif_l1_lsc_parabola_ag_param r_4d;
+ struct viif_l1_lsc_parabola_ag_param gr_2d;
+ struct viif_l1_lsc_parabola_ag_param gr_4d;
+ struct viif_l1_lsc_parabola_ag_param gb_2d;
+ struct viif_l1_lsc_parabola_ag_param gb_4d;
+ struct viif_l1_lsc_parabola_ag_param b_2d;
+ struct viif_l1_lsc_parabola_ag_param b_4d;
+};
+
+/**
+ * struct viif_l1_lsc_grid_param - L2ISP grid shading parameters
+ * for &struct viif_l1_lsc
+ * @lssc_grid_h_size: Grid horizontal direction pixel count [32, 64, 128, 256, 512]
+ * @lssc_grid_v_size: Grid vertical direction pixel count [32, 64, 128, 256, 512]
+ * @lssc_grid_h_center: Horizontal coordinates of grid (1, 1) [pixel] [1..lssc_grid_h_size]
+ * Should meet the following condition.
+ * "Input image width <= lssc_grid_h_center + lssc_grid_h_size * 31"
+ * @lssc_grid_v_center: Vertical coordinates of grid (1, 1) [line] [1..lssc_grid_v_size]
+ * Should meet the following condition.
+ * "Input image height <= lssc_grid_v_center + lssc_grid_v_size * 23"
+ * @lssc_grid_mgsel: &enum viif_l1_grid_coef_gain value.
+ * Grid correction coefficient gain value magnification ratio.
+ */
+struct viif_l1_lsc_grid_param {
+ __u32 lssc_grid_h_size;
+ __u32 lssc_grid_v_size;
+ __u32 lssc_grid_h_center;
+ __u32 lssc_grid_v_center;
+ __u32 lssc_grid_mgsel;
+};
+
+/**
+ * struct viif_l1_lsc - L2ISP LSC parameters for &struct viif_l1_lsc_config
+ * @lssc_parabola_param_addr: Address of a &struct viif_l1_lsc_parabola_param instance.
+ * Set 0 to disable parabola shading correction.
+ * @lssc_grid_param_addr: Address of a &struct viif_l1_lsc_grid_param instance,
+ * Set 0 to disable grid shading correction.
+ * @lssc_pwhb_r_gain_max: PWB R correction processing coefficient maximum value
+ * @lssc_pwhb_r_gain_min: PWB R correction processing coefficient minimum value
+ * @lssc_pwhb_gr_gain_max: PWB Gr correction processing coefficient maximum value
+ * @lssc_pwhb_gr_gain_min: PWB Gr correction processing coefficient minimum value
+ * @lssc_pwhb_gb_gain_max: PWB Gb correction processing coefficient maximum value
+ * @lssc_pwhb_gb_gain_min: PWB Gb correction processing coefficient minimum value
+ * @lssc_pwhb_b_gain_max: PWB B correction processing coefficient maximum value
+ * @lssc_pwhb_b_gain_min: PWB B correction processing coefficient minimum value
+ *
+ * The range and accuracy of preset white balance (PWB) correction process
+ * coefficient (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) are as below.
+ * "range: [0..2047], accuracy: 1/256"
+ *
+ * PWB correction process coefficient
+ * (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) should meet the following conditions.
+ * "lssc_pwhb_{r/gr/gb/b}_gain_min <= lssc_pwhb_{r/gr/gb/b}_gain_max"
+ */
+struct viif_l1_lsc {
+ __u64 lssc_parabola_param_addr;
+ __u64 lssc_grid_param_addr;
+ __u32 lssc_pwhb_r_gain_max;
+ __u32 lssc_pwhb_r_gain_min;
+ __u32 lssc_pwhb_gr_gain_max;
+ __u32 lssc_pwhb_gr_gain_min;
+ __u32 lssc_pwhb_gb_gain_max;
+ __u32 lssc_pwhb_gb_gain_min;
+ __u32 lssc_pwhb_b_gain_max;
+ __u32 lssc_pwhb_b_gain_min;
+};
+
+/**
+ * struct viif_l1_lsc_config - L2ISP LSC parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC`
+ * @param_addr: Address of a &struct viif_l1_lsc instance.
+ * Set 0 to disable LSC operation.
+ * @table_gr_addr: Address of the grid table for LSC of Gr component.
+ * The table size is sizeof(u16) * 768.
+ * Set 0 to disable this table.
+ * @table_r_addr: Address of the grid table for LSC of R component.
+ * The table size is sizeof(u16) * 768.
+ * Set 0 to disable this table.
+ * @table_b_addr: Address of the grid table for LSC of B component.
+ * The table size is sizeof(u16) * 768.
+ * Set 0 to disable this table.
+ * @table_gb_addr: Address of the grid table for LSC of Gb component.
+ * The table size is sizeof(u16) * 768.
+ * Set 0 to disable this table.
+ *
+ * The size of each table is fixed to 1,536 Bytes.
+ * Application should make sure that the table data is based on HW specification
+ * since this driver does not check the grid table.
+ */
+struct viif_l1_lsc_config {
+ __u64 param_addr;
+ __u64 table_gr_addr;
+ __u64 table_r_addr;
+ __u64 table_b_addr;
+ __u64 table_gb_addr;
+};
+
+/**
+ * enum viif_l1_demosaic_mode - L1ISP demosaic modeenum viif_l1_demosaic_mode
+ *
+ * @VIIF_L1_DEMOSAIC_ACPI: Toshiba ACPI algorithm
+ * @VIIF_L1_DEMOSAIC_DMG: DMG algorithm
+ */
+enum viif_l1_demosaic_mode {
+ VIIF_L1_DEMOSAIC_ACPI = 0,
+ VIIF_L1_DEMOSAIC_DMG = 1,
+};
+
+/**
+ * struct viif_l1_color_matrix_correction - L1ISP color matrix correction
+ * parameters for &struct viif_l1_main_process_config
+ * @coef_rmg_min: (R-G) Minimum coefficient
+ * @coef_rmg_max: (R-G) Maximum coefficient
+ * @coef_rmb_min: (R-B) Minimum coefficient
+ * @coef_rmb_max: (R-B) Maximum coefficient
+ * @coef_gmr_min: (G-R) Minimum coefficient
+ * @coef_gmr_max: (G-R) Maximum coefficient
+ * @coef_gmb_min: (G-B) Minimum coefficient
+ * @coef_gmb_max: (G-B) Maximum coefficient
+ * @coef_bmr_min: (B-R) Minimum coefficient
+ * @coef_bmr_max: (B-R) Maximum coefficient
+ * @coef_bmg_min: (B-G) Minimum coefficient
+ * @coef_bmg_max: (B-G) Maximum coefficient
+ * @dst_minval: Minimum value of output pixel [0..0xFFFF] [pixel]
+ *
+ * The range and accuracy of each coefficient are as
+ * "range: [-32768..32767], accuracy: 1/ 4096"
+ *
+ * Also, each coefficient should meet "coef_xxx_min <= coef_xxx_max" condition
+ */
+struct viif_l1_color_matrix_correction {
+ __s16 coef_rmg_min;
+ __s16 coef_rmg_max;
+ __s16 coef_rmb_min;
+ __s16 coef_rmb_max;
+ __s16 coef_gmr_min;
+ __s16 coef_gmr_max;
+ __s16 coef_gmb_min;
+ __s16 coef_gmb_max;
+ __s16 coef_bmr_min;
+ __s16 coef_bmr_max;
+ __s16 coef_bmg_min;
+ __s16 coef_bmg_max;
+ __u16 dst_minval;
+};
+
+/**
+ * struct viif_l1_main_process_config - L1ISP Main process operating parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS`
+ * @demosaic_mode: &enum viif_l1_demosaic_mode value. Sets demosaic mode.
+ * @damp_lsbsel: Clipping range of output pixel value to AWB adjustment function [0..15]
+ * @param_addr: Address to a &struct viif_l1_color_matrix_correction instance.
+ * Set 0 to disable color matrix correction.
+ * @dst_maxval: Maximum value of output pixel [0..0xFFFFFF].
+ * Applicable to output of each process (digital amplifier,
+ * demosaicing and color matrix correction) in L1ISP Main process.
+ */
+struct viif_l1_main_process_config {
+ __u32 demosaic_mode;
+ __u32 damp_lsbsel;
+ __u64 param_addr;
+ __u32 dst_maxval;
+};
+
+/**
+ * enum viif_l1_awb_mag - L1ISP signal magnification before AWB adjustment
+ *
+ * @VIIF_L1_AWB_ONE_SECOND: x 1/2
+ * @VIIF_L1_AWB_X1: 1 times
+ * @VIIF_L1_AWB_X2: 2 times
+ * @VIIF_L1_AWB_X4: 4 times
+ */
+enum viif_l1_awb_mag {
+ VIIF_L1_AWB_ONE_SECOND = 0,
+ VIIF_L1_AWB_X1 = 1,
+ VIIF_L1_AWB_X2 = 2,
+ VIIF_L1_AWB_X4 = 3,
+};
+
+/**
+ * enum viif_l1_awb_area_mode - L1ISP AWB detection target area
+ *
+ * @VIIF_L1_AWB_AREA_MODE0: only center area
+ * @VIIF_L1_AWB_AREA_MODE1: center area when uv is in square gate
+ * @VIIF_L1_AWB_AREA_MODE2: all area except center area
+ * @VIIF_L1_AWB_AREA_MODE3: all area
+ */
+enum viif_l1_awb_area_mode {
+ VIIF_L1_AWB_AREA_MODE0 = 0,
+ VIIF_L1_AWB_AREA_MODE1 = 1,
+ VIIF_L1_AWB_AREA_MODE2 = 2,
+ VIIF_L1_AWB_AREA_MODE3 = 3,
+};
+
+/**
+ * enum viif_l1_awb_restart_cond - L1ISP AWB adjustment restart conditions
+ *
+ * @VIIF_L1_AWB_RESTART_NO: no restart
+ * @VIIF_L1_AWB_RESTART_128FRAME: restart after 128 frame
+ * @VIIF_L1_AWB_RESTART_64FRAME: restart after 64 frame
+ * @VIIF_L1_AWB_RESTART_32FRAME: restart after 32 frame
+ * @VIIF_L1_AWB_RESTART_16FRAME: restart after 16 frame
+ * @VIIF_L1_AWB_RESTART_8FRAME: restart after 8 frame
+ * @VIIF_L1_AWB_RESTART_4FRAME: restart after 4 frame
+ * @VIIF_L1_AWB_RESTART_2FRAME: restart after 2 frame
+ */
+enum viif_l1_awb_restart_cond {
+ VIIF_L1_AWB_RESTART_NO = 0,
+ VIIF_L1_AWB_RESTART_128FRAME = 1,
+ VIIF_L1_AWB_RESTART_64FRAME = 2,
+ VIIF_L1_AWB_RESTART_32FRAME = 3,
+ VIIF_L1_AWB_RESTART_16FRAME = 4,
+ VIIF_L1_AWB_RESTART_8FRAME = 5,
+ VIIF_L1_AWB_RESTART_4FRAME = 6,
+ VIIF_L1_AWB_RESTART_2FRAME = 7,
+};
+
+/**
+ * struct viif_l1_awb - L1ISP AWB adjustment parameters
+ * for &struct viif_l1_awb_config
+ * @awhb_ygate_sel: 1:Enable/0:Disable to fix Y value at YUV conversion
+ * @awhb_ygate_data: Y value in case Y value is fixed [64, 128, 256, 512]
+ * @awhb_cgrange: &enum viif_l1_awb_mag value.
+ * Signal output magnification ratio before AWB adjustment.
+ * @awhb_ygatesw: 1:Enable/0:Disable settings of luminance gate
+ * @awhb_hexsw: 1:Enable/0:Disable settings of hexa-gate
+ * @awhb_areamode: &enum viif_l1_awb_area_mode value.
+ * Final selection of accumulation area for detection target area.
+ * @awhb_area_hsize: Horizontal size per block in central area [pixel]
+ * [1..(Input image width -8)/8]
+ * @awhb_area_vsize: Vertical size per block in central area [line]
+ * [1..(Input image height -4)/8]
+ * @awhb_area_hofs: Horizontal offset of block [0] in central area [pixel]
+ * [0..(Input image width -9)]
+ * @awhb_area_vofs: Vertical offset of block [0] in central area [line]
+ * [0..(Input image height -5)]
+ * @awhb_area_maskh: Setting 1:Enable/0:Disable( of accumulated selection.
+ * Each bit implies the following.
+ * [31:0] = {
+ * (7, 3),(6, 3),(5, 3),(4, 3),(3, 3),(2, 3),(1, 3),(0, 3),
+ * (7, 2),(6, 2),(5, 2),(4, 2),(3, 2),(2, 2),(1, 2),(0, 2),
+ * (7, 1),(6, 1),(5, 1),(4, 1),(3, 1),(2, 1),(1, 1),(0, 1),
+ * (7, 0),(6, 0),(5, 0),(4, 0),(3, 0),(2, 0),(1, 0),(0, 0)}
+ * @awhb_area_maskl: Setting 1:Enable/0:Disable of accumulated selection.
+ * Each bit implies the following.
+ * [31:0] = {
+ * (7, 7),(6, 7),(5, 7),(4, 7),(3, 7),(2, 7),(1, 7),(0, 7),
+ * (7, 6),(6, 6),(5, 6),(4, 6),(3, 6),(2, 6),(1, 6),(0, 6),
+ * (7, 5),(6, 5),(5, 5),(4, 5),(3, 5),(2, 5),(1, 5),(0, 5),
+ * (7, 4),(6, 4),(5, 4),(4, 4),(3, 4),(2, 4),(1, 4),(0, 4)}
+ * @awhb_sq_sw: 1:Enable/0:Disable each square gate
+ * @awhb_sq_pol: 1:Enable/0:Disable to add accumulated gate for each square gate
+ * @awhb_bycut0p: U upper end value [pixel] [0..127]
+ * @awhb_bycut0n: U lower end value [pixel] [0..127]
+ * @awhb_rycut0p: V upper end value [pixel] [0..127]
+ * @awhb_rycut0n: V lower end value [pixel] [0..127]
+ * @awhb_rbcut0h: V-axis intercept upper end [pixel] [-127..127]
+ * @awhb_rbcut0l: V-axis intercept lower end [pixel] [-127..127]
+ * @awhb_bycut_h: U direction center value of each square gate [-127..127]
+ * @awhb_bycut_l: U direction width of each square gate [0..127]
+ * @awhb_rycut_h: V direction center value of each square gate [-127..127]
+ * @awhb_rycut_l: V direction width of each square gate [0..127]
+ * @awhb_awbsftu: U gain offset [-127..127]
+ * @awhb_awbsftv: V gain offset [-127..127]
+ * @awhb_awbhuecor: 1:Enable/0:Disable setting of color correlation retention function
+ * @awhb_awbspd: UV convergence speed [0..15] [times] (0 means "stop")
+ * @awhb_awbulv: U convergence point level [0..31]
+ * @awhb_awbvlv: V convergence point level [0..31]
+ * @awhb_awbondot: Accumulation operation stop pixel count threshold [pixel] [0..1023]
+ * @awhb_awbfztim: &enum viif_l1_awb_restart_cond value. Condition to restart AWB process.
+ * @awhb_wbgrmax: B gain adjustment range (Width from center to upper limit)
+ * [0..255], accuracy: 1/64
+ * @awhb_wbgbmax: R gain adjustment range (Width from center to upper limit)
+ * [0..255], accuracy: 1/64
+ * @awhb_wbgrmin: B gain adjustment range (Width from center to lower limit)
+ * [0..255], accuracy: 1/64
+ * @awhb_wbgbmin: R gain adjustment range (Width from center to lower limit)
+ * [0..255], accuracy: 1/64
+ * @awhb_ygateh: Luminance gate maximum value [pixel] [0..255]
+ * @awhb_ygatel: Luminance gate minimum value [pixel] [0..255]
+ * @awhb_awbwait: Number of restart frames after UV convergence freeze [0..255]
+ */
+struct viif_l1_awb {
+ __u32 awhb_ygate_sel;
+ __u32 awhb_ygate_data;
+ __u32 awhb_cgrange;
+ __u32 awhb_ygatesw;
+ __u32 awhb_hexsw;
+ __u32 awhb_areamode;
+ __u32 awhb_area_hsize;
+ __u32 awhb_area_vsize;
+ __u32 awhb_area_hofs;
+ __u32 awhb_area_vofs;
+ __u32 awhb_area_maskh;
+ __u32 awhb_area_maskl;
+ __u32 awhb_sq_sw[3];
+ __u32 awhb_sq_pol[3];
+ __u32 awhb_bycut0p;
+ __u32 awhb_bycut0n;
+ __u32 awhb_rycut0p;
+ __u32 awhb_rycut0n;
+ __s32 awhb_rbcut0h;
+ __s32 awhb_rbcut0l;
+ __s32 awhb_bycut_h[3];
+ __u32 awhb_bycut_l[3];
+ __s32 awhb_rycut_h[3];
+ __u32 awhb_rycut_l[3];
+ __s32 awhb_awbsftu;
+ __s32 awhb_awbsftv;
+ __u32 awhb_awbhuecor;
+ __u32 awhb_awbspd;
+ __u32 awhb_awbulv;
+ __u32 awhb_awbvlv;
+ __u32 awhb_awbondot;
+ __u32 awhb_awbfztim;
+ __u8 awhb_wbgrmax;
+ __u8 awhb_wbgbmax;
+ __u8 awhb_wbgrmin;
+ __u8 awhb_wbgbmin;
+ __u8 awhb_ygateh;
+ __u8 awhb_ygatel;
+ __u8 awhb_awbwait;
+};
+
+/**
+ * struct viif_l1_awb_config - L1ISP AWB parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB`
+ * @param_addr: Address to a &struct viif_l1_awb instance.
+ * Set 0 to disable AWB adjustment.
+ * @awhb_wbmrg: White balance adjustment R gain [64..1023], accuracy: 1/256
+ * @awhb_wbmgg: White balance adjustment G gain [64..1023], accuracy: 1/256
+ * @awhb_wbmbg: White balance adjustment B gain [64..1023], accuracy: 1/256
+ */
+struct viif_l1_awb_config {
+ __u64 param_addr;
+ __u32 awhb_wbmrg;
+ __u32 awhb_wbmgg;
+ __u32 awhb_wbmbg;
+};
+
+/**
+ * enum viif_l1_hdrc_tone_type - L1ISP HDRC tone type
+ *
+ * @VIIF_L1_HDRC_TONE_USER: User Tone
+ * @VIIF_L1_HDRC_TONE_PRESET: Preset Tone
+ */
+enum viif_l1_hdrc_tone_type {
+ VIIF_L1_HDRC_TONE_USER = 0,
+ VIIF_L1_HDRC_TONE_PRESET = 1,
+};
+
+/**
+ * struct viif_l1_hdrc - L1ISP HDRC parameters for &struct viif_l1_hdrc_config
+ * @hdrc_ratio: Data width of input image [bit] [10..24]
+ * @hdrc_pt_ratio: Preset Tone curve slope [0..13]
+ * @hdrc_pt_blend: Preset Tone0 curve blend ratio [0..256], accuracy: 1/256
+ * @hdrc_pt_blend2: Preset Tone2 curve blend ratio [0..256], accuracy: 1/256
+ * @hdrc_tn_type: &enum viif_l1_hdrc_tone_type value. L1ISP HDRC tone type.
+ * @hdrc_utn_tbl: HDRC value of User Tone curve [0..0xFFFF]
+ * @hdrc_flr_val: Constant flare value [0..0xFFFFFF]
+ * @hdrc_flr_adp: 1:Enable/0:Disable setting of dynamic flare measurement
+ * @hdrc_ybr_off: 1:Enable(function OFF) / 0:Disable(function ON) settings
+ * of bilateral luminance filter function OFF
+ * @hdrc_orgy_blend: Blend settings of luminance correction data after HDRC
+ * and data before luminance correction [0..16].
+ * (0:Luminance correction 100%, 8:Luminance correction 50%,
+ * 16:Luminance correction 0%)
+ * @hdrc_pt_sat: Preset Tone saturation value [0..0xFFFF]
+ *
+ * Parameter error needs to be returned in
+ * "hdrc_pt_blend + hdrc_pt_blend2 > 256" condition.
+ *
+ * In case application enables dynamic flare control, input image height should
+ * satisfy the following condition. Even if this condition is not satisfied,
+ * this driver doesn't return error in case other conditions for each parameter
+ * are satisfied. "Input image height % 64 != 18, 20, 22, 24, 26"
+ *
+ * hdrc_utn_tbl should satisfy the following condition. Even if this condition
+ * is not satisfied, this driver doesn't return error in case other conditions
+ * for each parameter are satisfied. "hdrc_utn_tbl[N] <= hdrc_utn_tbl[N+1]"
+ */
+struct viif_l1_hdrc {
+ __u32 hdrc_ratio;
+ __u32 hdrc_pt_ratio;
+ __u32 hdrc_pt_blend;
+ __u32 hdrc_pt_blend2;
+ __u32 hdrc_tn_type;
+ __u16 hdrc_utn_tbl[20];
+ __u32 hdrc_flr_val;
+ __u32 hdrc_flr_adp;
+ __u32 hdrc_ybr_off;
+ __u32 hdrc_orgy_blend;
+ __u16 hdrc_pt_sat;
+};
+
+/**
+ * struct viif_l1_hdrc_config - L1ISP HDRC parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC`
+ * @param_addr: Address to a &struct viif_l1_hdrc instance.
+ * Set 0 to disable HDR compression.
+ * @hdrc_thr_sft_amt: Amount of right shift in through mode (HDRC disabled) [0..8].
+ * Should set 0 if HDRC is enabled
+ */
+struct viif_l1_hdrc_config {
+ __u64 param_addr;
+ __u32 hdrc_thr_sft_amt;
+};
+
+/**
+ * struct viif_l1_hdrc_ltm_config - L1ISP HDRC LTM parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM`
+ * @tnp_max: Tone blend rate maximum value of LTM function
+ * [0..4194303], accuracy: 1/64. In case of 0, LTM function is OFF
+ * @tnp_mag: Intensity adjustment of LTM function [0..16383], accuracy: 1/64
+ * @tnp_fil: Smoothing filter coefficient [0..255].
+ * [0]: coef0, [1]: coef1, [2]: coef2, [3]: coef3, [4]: coef4
+ * EINVAL needs to be returned in the below condition.
+ * "(coef1 + coef2 + coef3 + coef4) * 2 + coef0 != 1024"
+ */
+struct viif_l1_hdrc_ltm_config {
+ __u32 tnp_max;
+ __u32 tnp_mag;
+ __u8 tnp_fil[5];
+};
+
+/**
+ * struct viif_l1_gamma - L1ISP gamma correction parameters
+ * for &struct viif_l1_gamma_config
+ * @gam_p: Luminance value after gamma correction [0..8191]
+ * @blkadj: Black level adjustment value after gamma correction [0..65535]
+ */
+struct viif_l1_gamma {
+ __u16 gam_p[44];
+ __u16 blkadj;
+};
+
+/**
+ * struct viif_l1_gamma_config - L1ISP gamma correction parameters
+ * @param_addr: Address to a &struct viif_l1_gamma instance.
+ * Set 0 to disable gamma correction at l1 ISP.
+ */
+struct viif_l1_gamma_config {
+ __u64 param_addr;
+};
+
+/**
+ * struct viif_l1_nonlinear_contrast - L1ISP non-linear contrast parameters
+ * for &struct viif_l1_img_quality_adjustment_config
+ * @blk_knee: Black side peak luminance value [0..0xFFFF]
+ * @wht_knee: White side peak luminance value[0..0xFFFF]
+ * @blk_cont: Black side slope [0..255], accuracy: 1/256
+ * [0]:the value at AG minimum, [1]:the value at AG less than 128,
+ * [2]:the value at AG equal to or more than 128
+ * @wht_cont: White side slope [0..255], accuracy: 1/256
+ * [0]:the value at AG minimum, [1]:the value at AG less than 128,
+ * [2]:the value at AG equal to or more than 128
+ */
+struct viif_l1_nonlinear_contrast {
+ __u16 blk_knee;
+ __u16 wht_knee;
+ __u8 blk_cont[3];
+ __u8 wht_cont[3];
+};
+
+/**
+ * struct viif_l1_lum_noise_reduction - L1ISP luminance noise reduction
+ * parameters for &struct viif_l1_img_quality_adjustment_config
+ * @gain_min: Minimum value of extracted noise gain [0..0xFFFF], accuracy: 1/256
+ * @gain_max: Maximum value of extracted noise gain [0..0xFFFF], accuracy: 1/256
+ * @lim_min: Minimum value of extracted noise limit [0..0xFFFF]
+ * @lim_max: Maximum value of extracted noise limit [0..0xFFFF]
+ *
+ * Parameter error needs to be returned in the below conditions.
+ * "gain_min > gain_max" or "lim_min > lim_max"
+ */
+struct viif_l1_lum_noise_reduction {
+ __u16 gain_min;
+ __u16 gain_max;
+ __u16 lim_min;
+ __u16 lim_max;
+};
+
+/**
+ * struct viif_l1_edge_enhancement - L1ISP edge enhancement parameters
+ * for &struct viif_l1_img_quality_adjustment_config
+ * @gain_min: Extracted edge gain minimum value [0..0xFFFF], accuracy: 1/256
+ * @gain_max: Extracted edge gain maximum value [0..0xFFFF], accuracy: 1/256
+ * @lim_min: Extracted edge limit minimum value [0..0xFFFF]
+ * @lim_max: Extracted edge limit maximum value [0..0xFFFF]
+ * @coring_min: Extracted edge coring threshold minimum value [0..0xFFFF]
+ * @coring_max: Extracted edge coring threshold maximum value [0..0xFFFF]
+ *
+ * Parameter error needs to be returned in the below conditions.
+ * "gain_min > gain_max" or "lim_min > lim_max" or "coring_min > coring_max"
+ */
+struct viif_l1_edge_enhancement {
+ __u16 gain_min;
+ __u16 gain_max;
+ __u16 lim_min;
+ __u16 lim_max;
+ __u16 coring_min;
+ __u16 coring_max;
+};
+
+/**
+ * struct viif_l1_uv_suppression - L1ISP UV suppression parameters
+ * for &struct viif_l1_img_quality_adjustment_config
+ * @bk_mp: Black side slope [0..0x3FFF], accuracy: 1/16384
+ * @black: Minimum black side gain [0..0x3FFF], accuracy: 1/16384
+ * @wh_mp: White side slope [0..0x3FFF], accuracy: 1/16384
+ * @white: Minimum white side gain [0..0x3FFF], accuracy: 1/16384
+ * @bk_slv: Black side intercept [0..0xFFFF]
+ * @wh_slv: White side intercept [0..0xFFFF]
+ *
+ * parameter error needs to be returned in "bk_slv >= wh_slv" condition.
+ */
+struct viif_l1_uv_suppression {
+ __u32 bk_mp;
+ __u32 black;
+ __u32 wh_mp;
+ __u32 white;
+ __u16 bk_slv;
+ __u16 wh_slv;
+};
+
+/**
+ * struct viif_l1_coring_suppression - L1ISP coring suppression parameters
+ * for &struct viif_l1_img_quality_adjustment_config
+ * @lv_min: Minimum coring threshold [0..0xFFFF]
+ * @lv_max: Maximum coring threshold [0..0xFFFF]
+ * @gain_min: Minimum gain [0..0xFFFF], accuracy: 1/65536
+ * @gain_max: Maximum gain [0..0xFFFF], accuracy: 1/65536
+ *
+ * Parameter error needs to be returned in the below condition.
+ * "lv_min > lv_max" or "gain_min > gain_max"
+ */
+struct viif_l1_coring_suppression {
+ __u16 lv_min;
+ __u16 lv_max;
+ __u16 gain_min;
+ __u16 gain_max;
+};
+
+/**
+ * struct viif_l1_edge_suppression - L1ISP edge suppression parameters
+ * for &struct viif_l1_img_quality_adjustment_config
+ * @gain: Gain of edge color suppression [0..0xFFFF], accuracy: 1/256
+ * @lim: Limiter threshold of edge color suppression [0..15]
+ */
+struct viif_l1_edge_suppression {
+ __u16 gain;
+ __u32 lim;
+};
+
+/**
+ * struct viif_l1_color_level - L1ISP color level parameters
+ * for &struct viif_l1_img_quality_adjustment_config
+ * @cb_gain: U component gain [0..0xFFF], accuracy: 1/2048
+ * @cr_gain: V component gain [0..0xFFF], accuracy: 1/2048
+ * @cbr_mgain_min: UV component gain [0..0xFFF], accuracy: 1/2048
+ * @cbp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
+ * @cbm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
+ * @crp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
+ * @crm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
+ */
+struct viif_l1_color_level {
+ __u32 cb_gain;
+ __u32 cr_gain;
+ __u32 cbr_mgain_min;
+ __u32 cbp_gain_max;
+ __u32 cbm_gain_max;
+ __u32 crp_gain_max;
+ __u32 crm_gain_max;
+};
+
+/**
+ * struct viif_l1_img_quality_adjustment_config - L1ISP image quality
+ * adjustment parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT`
+ * @coef_cb: Cb coefficient used in RGB to YUV conversion
+ * [0..0xFFFF], accuracy: 1/65536
+ * @coef_cr: Cr coefficient used in RGB to YUV conversion
+ * [0..0xFFFF], accuracy: 1/65536
+ * @brightness: Brightness value [-32768..32767] (0 means off)
+ * @linear_contrast: Linear contrast adjustment value
+ * [0..0xFF], accuracy: 1/128 (128 means off)
+ * @nonlinear_contrast_addr: Address to a &struct viif_l1_nonlinear_contrast instance.
+ * Set 0 to disable nonlinear contrast adjustment.
+ * @lum_noise_reduction_addr: Address to a &struct viif_l1_lum_noise_reduction instance.
+ * Set 0 to disable luminance noise reduction.
+ * @edge_enhancement_addr: Address to a &struct viif_l1_edge_enhancement instance.
+ * Set 0 to disable edge enhancement,
+ * @uv_suppression_addr: Address to a &struct viif_l1_uv_suppression instance.
+ * Set 0 to disable chroma suppression.
+ * @coring_suppression_addr: Address to a &struct viif_l1_coring_suppression instance.
+ * Set 0 to disable coring suppression.
+ * @edge_suppression_addr: Address to a &struct viif_l1_edge_suppression instance.
+ * Set 0 to disable chroma edge suppression.
+ * @color_level_addr: Address to a &struct viif_l1_color_level instance.
+ * Set 0 to disable color level adjustment.
+ * @color_noise_reduction_enable: 1:Enable/0:disable setting of
+ * color component noise reduction processing
+ */
+struct viif_l1_img_quality_adjustment_config {
+ __u16 coef_cb;
+ __u16 coef_cr;
+ __s16 brightness;
+ __u8 linear_contrast;
+ __u64 nonlinear_contrast_addr;
+ __u64 lum_noise_reduction_addr;
+ __u64 edge_enhancement_addr;
+ __u64 uv_suppression_addr;
+ __u64 coring_suppression_addr;
+ __u64 edge_suppression_addr;
+ __u64 color_level_addr;
+ __u32 color_noise_reduction_enable;
+};
+
+/**
+ * struct viif_l1_avg_lum_generation_config - L1ISP average luminance generation configuration
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION`
+ * @aexp_start_x: horizontal position of block[0] [0.."width of input image - 1"] [pixel]
+ * @aexp_start_y: vertical position of block[0] [0.."height of input image - 1"] [line]
+ * @aexp_block_width: width of one block(needs to be multiple of 64)
+ * [64.."width of input image"] [pixel]
+ * @aexp_block_height: height of one block(needs to be multiple of 64)
+ * [64.."height of input image"] [line]
+ * @aexp_weight: weight of each block [0..3] [y][x]:
+ * y means vertical position and x means horizontal position
+ * @aexp_satur_ratio: threshold to judge whether saturated block or not [0..256]
+ * @aexp_black_ratio: threshold to judge whether black block or not [0..256]
+ * @aexp_satur_level: threshold to judge whether saturated pixel or not [0x0..0xffffff]
+ * @aexp_ave4linesy: vertical position of the initial line
+ * for 4-lines average luminance [0.."height of input image - 4"] [line]
+ */
+struct viif_l1_avg_lum_generation_config {
+ __u32 aexp_start_x;
+ __u32 aexp_start_y;
+ __u32 aexp_block_width;
+ __u32 aexp_block_height;
+ __u32 aexp_weight[8][8];
+ __u32 aexp_satur_ratio;
+ __u32 aexp_black_ratio;
+ __u32 aexp_satur_level;
+ __u32 aexp_ave4linesy[4];
+};
+
+/**
+ * enum viif_l2_undist_mode - L2ISP undistortion mode
+ * @VIIF_L2_UNDIST_POLY: polynomial mode
+ * @VIIF_L2_UNDIST_GRID: grid table mode
+ * @VIIF_L2_UNDIST_POLY_TO_GRID: polynomial, then grid table mode
+ * @VIIF_L2_UNDIST_GRID_TO_POLY: grid table, then polynomial mode
+ */
+enum viif_l2_undist_mode {
+ VIIF_L2_UNDIST_POLY = 0,
+ VIIF_L2_UNDIST_GRID = 1,
+ VIIF_L2_UNDIST_POLY_TO_GRID = 2,
+ VIIF_L2_UNDIST_GRID_TO_POLY = 3,
+};
+
+/**
+ * struct viif_l2_undist - L2ISP UNDIST parameters
+ * for &struct viif_l2_undist_config
+ * @through_mode: 1:enable or 0:disable through mode of undistortion
+ * @roi_mode: &enum viif_l2_undist_mode value. Sets L2ISP undistortion mode.
+ * @sensor_crop_ofs_h: Horizontal start position of sensor crop area[pixel]
+ * [-4296..4296], accuracy: 1/2
+ * @sensor_crop_ofs_v: Vertical start position of sensor crop area[line]
+ * [-2360..2360], accuracy: 1/2
+ * @norm_scale: Normalization coefficient for distance from center
+ * [0..1677721], accuracy: 1/33554432
+ * @valid_r_norm2_poly: Setting target area for polynomial correction
+ * [0..0x3FFFFFF], accuracy: 1/33554432
+ * @valid_r_norm2_grid: Setting target area for grid table correction
+ * [0..0x3FFFFFF], accuracy: 1/33554432
+ * @roi_write_area_delta: Error adjustment value of forward function and
+ * inverse function for pixel position calculation
+ * [0..0x7FF], accuracy: 1/1024
+ * @poly_write_g_coef: 10th-order polynomial coefficient for G write pixel position calculation
+ * [-2147352576..2147352576], accuracy: 1/131072
+ * @poly_read_b_coef: 10th-order polynomial coefficient for B read pixel position calculation
+ * [-2147352576..2147352576], accuracy: 1/131072
+ * @poly_read_g_coef: 10th-order polynomial coefficient for G read pixel position calculation
+ * [-2147352576..2147352576], accuracy: 1/131072
+ * @poly_read_r_coef: 10th-order polynomial coefficient for R read pixel position calculation
+ * [-2147352576..2147352576], accuracy: 1/131072
+ * @grid_node_num_h: Number of horizontal grids [16..64]
+ * @grid_node_num_v: Number of vertical grids [16..64]
+ * @grid_patch_hsize_inv: Inverse pixel size between horizontal grids
+ * [0..0x7FFFFF], accuracy: 1/8388608
+ * @grid_patch_vsize_inv: Inverse pixel size between vertical grids
+ * [0..0x7FFFFF], accuracy: 1/8388608
+ */
+struct viif_l2_undist {
+ __u32 through_mode;
+ __u32 roi_mode[2];
+ __s32 sensor_crop_ofs_h;
+ __s32 sensor_crop_ofs_v;
+ __u32 norm_scale;
+ __u32 valid_r_norm2_poly;
+ __u32 valid_r_norm2_grid;
+ __u32 roi_write_area_delta[2];
+ __s32 poly_write_g_coef[11];
+ __s32 poly_read_b_coef[11];
+ __s32 poly_read_g_coef[11];
+ __s32 poly_read_r_coef[11];
+ __u32 grid_node_num_h;
+ __u32 grid_node_num_v;
+ __u32 grid_patch_hsize_inv;
+ __u32 grid_patch_vsize_inv;
+};
+
+/**
+ * struct viif_l2_undist_config - L2ISP UNDIST parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST`
+ * @param: &struct viif_l2_undist
+ * @write_g_addr: Address to write-G grid table.
+ * Table size is specified by member size.
+ * Set 0 to disable this table.
+ * @read_b_addr: Address to read-B grid table.
+ * Table size is specified by member size.
+ * Set 0 to disable this table.
+ * @read_g_addr: Address to read-G grid table.
+ * Table size is specified by member size.
+ * Set 0 to disable this table.
+ * @read_r_addr: Address to read-R grid table.
+ * Table size is specified by member size.
+ * Set 0 to disable this table.
+ * @size: Table size [byte]. Range: [1024..8192] or 0.
+ * The value should be "grid_node_num_h * grid_node_num_v * 4".
+ * See also &struct viif_l2_undist.
+ * Set 0 if NULL is set for all tables.
+ * Set valid size value if at least one table is valid.
+ *
+ * Application should make sure that the table data is based on HW specification
+ * since this driver does not check the contents of specified grid table.
+ */
+struct viif_l2_undist_config {
+ struct viif_l2_undist param;
+ __u64 write_g_addr;
+ __u64 read_b_addr;
+ __u64 read_g_addr;
+ __u64 read_r_addr;
+ __u32 size;
+};
+
+/**
+ * struct viif_l2_roi_config - L2ISP ROI parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI`
+ * @roi_num:
+ * 1 when only capture path0 is activated,
+ * 2 when both capture path 0 and path 1 are activated.
+ * @roi_scale: Scale value for each ROI [32768..131072], accuracy: 1/65536
+ * @roi_scale_inv: Inverse scale value for each ROI [32768..131072], accuracy: 1/65536
+ * @corrected_wo_scale_hsize: Corrected image width for each ROI [pixel] [128..8190]
+ * @corrected_wo_scale_vsize: Corrected image height for each ROI [line] [128..4094]
+ * @corrected_hsize: Corrected and scaled image width for each ROI [pixel] [128..8190]
+ * @corrected_vsize: Corrected and scaled image height for each ROI [line] [128..4094]
+ */
+struct viif_l2_roi_config {
+ __u32 roi_num;
+ __u32 roi_scale[2];
+ __u32 roi_scale_inv[2];
+ __u32 corrected_wo_scale_hsize[2];
+ __u32 corrected_wo_scale_vsize[2];
+ __u32 corrected_hsize[2];
+ __u32 corrected_vsize[2];
+};
+
+/** enum viif_gamma_mode - Gamma correction mode
+ *
+ * @VIIF_GAMMA_COMPRESSED: compressed table mode
+ * @VIIF_GAMMA_LINEAR: linear table mode
+ */
+enum viif_gamma_mode {
+ VIIF_GAMMA_COMPRESSED = 0,
+ VIIF_GAMMA_LINEAR = 1,
+};
+
+/**
+ * struct viif_l2_gamma_config - L2ISP gamma correction parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA`
+ * @pathid: 0 for Capture Path 0, 1 for Capture Path 1.
+ * @enable: 1:Enable, 0:Disable settings of L2ISP gamma correction control
+ * @vsplit: Line switching position of first table and second table [line] [0..4094].
+ * Should set 0 in case 0 is set to @enable
+ * @mode: &enum viif_gamma_mode value.
+ * Should set VIIF_GAMMA_COMPRESSED when 0 is set to @enable
+ * @table_addr: Address to gamma table for L2ISP gamma.
+ * The table has 6 channels;
+ * [0]: G/Y(1st table), [1]: G/Y(2nd table), [2]: B/U(1st table)
+ * [3]: B/U(2nd table), [4]: R/V(1st table), [5]: R/V(2nd table)
+ * Each channel of the table is __u16 typed and 512 bytes.
+ */
+struct viif_l2_gamma_config {
+ __u32 pathid;
+ __u32 enable;
+ __u32 vsplit;
+ __u32 mode;
+ __u64 table_addr[6];
+};
+
+/**
+ * enum viif_csi2_cal_status - CSI2RX calibration status
+ *
+ * @VIIF_CSI2_CAL_NOT_DONE: Calibration not complete
+ * @VIIF_CSI2_CAL_SUCCESS: Calibration success
+ * @VIIF_CSI2_CAL_FAIL: Calibration failed
+ */
+enum viif_csi2_cal_status {
+ VIIF_CSI2_CAL_NOT_DONE = 0,
+ VIIF_CSI2_CAL_SUCCESS = 1,
+ VIIF_CSI2_CAL_FAIL = 2,
+};
+
+/**
+ * struct viif_csi2rx_dphy_calibration_status - CSI2-RX D-PHY Calibration
+ * information for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS`
+ * @term_cal_with_rext: Result of termination calibration with rext
+ * @clock_lane_offset_cal: Result of offset calibration of clock lane
+ * @data_lane0_offset_cal: Result of offset calibration of data lane0
+ * @data_lane1_offset_cal: Result of offset calibration of data lane1
+ * @data_lane2_offset_cal: Result of offset calibration of data lane2
+ * @data_lane3_offset_cal: Result of offset calibration of data lane3
+ * @data_lane0_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane0
+ * @data_lane1_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane1
+ * @data_lane2_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane2
+ * @data_lane3_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane3
+ *
+ * Values for each member is typed &enum viif_csi2_cal_status.
+ */
+struct viif_csi2rx_dphy_calibration_status {
+ __u32 term_cal_with_rext;
+ __u32 clock_lane_offset_cal;
+ __u32 data_lane0_offset_cal;
+ __u32 data_lane1_offset_cal;
+ __u32 data_lane2_offset_cal;
+ __u32 data_lane3_offset_cal;
+ __u32 data_lane0_ddl_tuning_cal;
+ __u32 data_lane1_ddl_tuning_cal;
+ __u32 data_lane2_ddl_tuning_cal;
+ __u32 data_lane3_ddl_tuning_cal;
+};
+
+/**
+ * struct viif_csi2rx_err_status - CSI2RX Error status parameters
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS`
+ * @err_phy_fatal: D-PHY FATAL error.
+ *
+ * * bit[3]: Start of transmission error on DATA Lane3.
+ * * bit[2]: Start of transmission error on DATA Lane2.
+ * * bit[1]: Start of transmission error on DATA Lane1.
+ * * bit[0]: Start of transmission error on DATA Lane0.
+ * @err_pkt_fatal: Packet FATAL error.
+ *
+ * * bit[16]: Header ECC contains 2 errors, unrecoverable.
+ * * bit[3]: Checksum error detected on virtual channel 3.
+ * * bit[2]: Checksum error detected on virtual channel 2.
+ * * bit[1]: Checksum error detected on virtual channel 1.
+ * * bit[0]: Checksum error detected on virtual channel 0.
+ * @err_frame_fatal: Frame FATAL error.
+ *
+ * * bit[19]: Last received Frame, in virtual channel 3, has at least one CRC error.
+ * * bit[18]: Last received Frame, in virtual channel 2, has at least one CRC error.
+ * * bit[17]: Last received Frame, in virtual channel 1, has at least one CRC error.
+ * * bit[16]: Last received Frame, in virtual channel 0, has at least one CRC error.
+ * * bit[11]: Incorrect Frame Sequence detected in virtual channel 3.
+ * * bit[10]: Incorrect Frame Sequence detected in virtual channel 2.
+ * * bit[9]: Incorrect Frame Sequence detected in virtual channel 1.
+ * * bit[8]: Incorrect Frame Sequence detected in virtual channel 0.
+ * * bit[3]: Error matching Frame Start with Frame End for virtual channel 3.
+ * * bit[2]: Error matching Frame Start with Frame End for virtual channel 2.
+ * * bit[1]: Error matching Frame Start with Frame End for virtual channel 1.
+ * * bit[0]: Error matching Frame Start with Frame End for virtual channel 0.
+ * @err_phy: D-PHY error.
+ *
+ * * bit[19]: Escape Entry Error on Data Lane 3.
+ * * bit[18]: Escape Entry Error on Data Lane 2.
+ * * bit[17]: Escape Entry Error on Data Lane 1.
+ * * bit[16]: Escape Entry Error on Data Lane 0.
+ * * bit[3]: Start of Transmission Error on Data Lane 3 (synchronization can still be achieved).
+ * * bit[2]: Start of Transmission Error on Data Lane 2 (synchronization can still be achieved).
+ * * bit[1]: Start of Transmission Error on Data Lane 1 (synchronization can still be achieved).
+ * * bit[0]: Start of Transmission Error on Data Lane 0 (synchronization can still be achieved).
+ * @err_pkt: Packet error.
+ *
+ * * bit[19]: Header Error detected and corrected on virtual channel 3.
+ * * bit[18]: Header Error detected and corrected on virtual channel 2.
+ * * bit[17]: Header Error detected and corrected on virtual channel 1.
+ * * bit[16]: Header Error detected and corrected on virtual channel 0.
+ * * bit[3]: Unrecognized or unimplemented data type detected in virtual channel 3.
+ * * bit[2]: Unrecognized or unimplemented data type detected in virtual channel 2.
+ * * bit[1]: Unrecognized or unimplemented data type detected in virtual channel 1.
+ * * bit[0]: Unrecognized or unimplemented data type detected in virtual channel 0.
+ * @err_line: Line error.
+ *
+ * * bit[23]: Error in the sequence of lines for vc7 and dt7.
+ * * bit[22]: Error in the sequence of lines for vc6 and dt6.
+ * * bit[21]: Error in the sequence of lines for vc5 and dt5.
+ * * bit[20]: Error in the sequence of lines for vc4 and dt4.
+ * * bit[19]: Error in the sequence of lines for vc3 and dt3.
+ * * bit[18]: Error in the sequence of lines for vc2 and dt2.
+ * * bit[17]: Error in the sequence of lines for vc1 and dt1.
+ * * bit[16]: Error in the sequence of lines for vc0 and dt0.
+ * * bit[7]: Error matching Line Start with Line End for vc7 and dt7.
+ * * bit[6]: Error matching Line Start with Line End for vc6 and dt6.
+ * * bit[5]: Error matching Line Start with Line End for vc5 and dt5.
+ * * bit[4]: Error matching Line Start with Line End for vc4 and dt4.
+ * * bit[3]: Error matching Line Start with Line End for vc3 and dt3.
+ * * bit[2]: Error matching Line Start with Line End for vc2 and dt2.
+ * * bit[1]: Error matching Line Start with Line End for vc1 and dt1.
+ * * bit[0]: Error matching Line Start with Line End for vc0 and dt0.
+ */
+struct viif_csi2rx_err_status {
+ __u32 err_phy_fatal;
+ __u32 err_pkt_fatal;
+ __u32 err_frame_fatal;
+ __u32 err_phy;
+ __u32 err_pkt;
+ __u32 err_line;
+};
+
+/**
+ * struct viif_l1_info - L1ISP AWB information
+ * for &struct viif_isp_capture_status
+ * @avg_lum_weight: weighted average luminance value at average luminance generation
+ * @avg_lum_block: average luminance of each block [y][x]:
+ * y means vertical position and x means horizontal position
+ * @avg_lum_four_line_lum: 4-lines average luminance.
+ * avg_lum_four_line_lum[n] corresponds to aexp_ave4linesy[n]
+ * @avg_satur_pixnum: the number of saturated pixel at average luminance generation
+ * @avg_black_pixnum: the number of black pixel at average luminance generation
+ * @awb_ave_u: U average value of AWB adjustment [pixel]
+ * @awb_ave_v: V average value of AWB adjustment [pixel]
+ * @awb_accumulated_pixel: Accumulated pixel count of AWB adjustment
+ * @awb_gain_r: R gain used in the next frame of AWB adjustment
+ * @awb_gain_g: G gain used in the next frame of AWB adjustment
+ * @awb_gain_b: B gain used in the next frame of AWB adjustment
+ * @awb_status_u: boolean value of U convergence state of AWB adjustment
+ * (0: not-converged, 1: converged)
+ * @awb_status_v: boolean value of V convergence state of AWB adjustment
+ * (0: not-converged, 1: converged)
+ */
+struct viif_l1_info {
+ __u32 avg_lum_weight;
+ __u32 avg_lum_block[8][8];
+ __u32 avg_lum_four_line_lum[4];
+ __u32 avg_satur_pixnum;
+ __u32 avg_black_pixnum;
+ __u32 awb_ave_u;
+ __u32 awb_ave_v;
+ __u32 awb_accumulated_pixel;
+ __u32 awb_gain_r;
+ __u32 awb_gain_g;
+ __u32 awb_gain_b;
+ __u8 awb_status_u;
+ __u8 awb_status_v;
+};
+
+/**
+ * struct viif_isp_capture_status - L1ISP capture information
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS`
+ * @l1_info: L1ISP AWB information. Refer to &struct viif_l1_info
+ */
+struct viif_isp_capture_status {
+ struct viif_l1_info l1_info;
+};
+
+/**
+ * struct viif_reported_errors - Errors since last call
+ * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS`
+ * @main: error flag value for capture device 0 and 1
+ * @sub: error flag value for capture device 2
+ * @csi2rx: error flag value for CSI2 receiver
+ */
+struct viif_reported_errors {
+ __u32 main;
+ __u32 sub;
+ __u32 csi2rx;
+};
+
+#endif /* __UAPI_VISCONTI_VIIF_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
@ 2023-01-11 15:30 ` kernel test robot
2023-01-11 22:55 ` kernel test robot
` (3 subsequent siblings)
4 siblings, 0 replies; 42+ messages in thread
From: kernel test robot @ 2023-01-11 15:30 UTC (permalink / raw)
To: Yuji Ishikawa, Hans Verkuil, Laurent Pinchart,
Mauro Carvalho Chehab, Nobuhiro Iwamatsu, Rob Herring,
Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown
Cc: llvm, oe-kbuild-all, linux-media, linux-arm-kernel, linux-kernel,
devicetree, yuji2.ishikawa
[-- Attachment #1: Type: text/plain, Size: 2513 bytes --]
Hi Yuji,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on media-tree/master]
[also build test ERROR on linus/master v6.2-rc3 next-20230111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yuji-Ishikawa/dt-bindings-media-platform-visconti-Add-Toshiba-Visconti-Video-Input-Interface-bindings/20230111-103311
base: git://linuxtv.org/media_tree.git master
patch link: https://lore.kernel.org/r/20230111022433.25950-3-yuji2.ishikawa%40toshiba.co.jp
patch subject: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
config: i386-randconfig-a013
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/3c3aa5193e57992c40b61f5cc1cdc072c2b14fae
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Yuji-Ishikawa/dt-bindings-media-platform-visconti-Add-Toshiba-Visconti-Video-Input-Interface-bindings/20230111-103311
git checkout 3c3aa5193e57992c40b61f5cc1cdc072c2b14fae
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from <built-in>:1:
In file included from ./usr/include/linux/visconti_viif.h:12:
>> usr/include/linux/videodev2.h:2442:20: error: field has incomplete type 'struct timespec'
struct timespec timestamp;
^
usr/include/linux/videodev2.h:2442:9: note: forward declaration of 'struct timespec'
struct timespec timestamp;
^
1 error generated.
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
[-- Attachment #2: config --]
[-- Type: text/plain, Size: 157130 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# Linux/i386 6.2.0-rc1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="clang version 14.0.6 (git://gitmirror/llvm_project f28c006a5895fc0e329fe15fead81e37457cb1d1)"
CONFIG_GCC_VERSION=0
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=140006
CONFIG_AS_IS_LLVM=y
CONFIG_AS_VERSION=140006
CONFIG_LD_VERSION=0
CONFIG_LD_IS_LLD=y
CONFIG_LLD_VERSION=140006
CONFIG_RUST_IS_AVAILABLE=y
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=123
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_UAPI_HEADER_TEST=y
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_ZSTD=y
# CONFIG_KERNEL_GZIP is not set
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_KERNEL_LZ4=y
# CONFIG_KERNEL_ZSTD is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_WATCH_QUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
# CONFIG_USELIB is not set
# CONFIG_AUDIT is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_PENDING_IRQ=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=125
# end of Timers subsystem
CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
# CONFIG_BPF_JIT is not set
CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
CONFIG_USERMODE_DRIVER=y
# CONFIG_BPF_PRELOAD is not set
# end of BPF subsystem
CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_DYNAMIC is not set
# CONFIG_SCHED_CORE is not set
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting
# CONFIG_CPU_ISOLATION is not set
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_FORCE_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_FORCE_TASKS_RUDE_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_FORCE_TASKS_TRACE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_FANOUT=32
CONFIG_RCU_FANOUT_LEAF=16
# CONFIG_RCU_NOCB_CPU is not set
# CONFIG_TASKS_TRACE_RCU_READ_MB is not set
# end of RCU Subsystem
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_IKHEADERS=m
CONFIG_LOG_BUF_SHIFT=20
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
# CONFIG_MEMCG is not set
# CONFIG_BLK_CGROUP is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
# CONFIG_CGROUP_RDMA is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_HUGETLB is not set
# CONFIG_CPUSETS is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_BPF is not set
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
# CONFIG_USER_NS is not set
CONFIG_PID_NS=y
# CONFIG_NET_NS is not set
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
# CONFIG_PCSPKR_PLATFORM is not set
# CONFIG_BASE_FULL is not set
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
# CONFIG_EVENTFD is not set
CONFIG_SHMEM=y
CONFIG_AIO=y
# CONFIG_IO_URING is not set
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PC104=y
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
CONFIG_DEBUG_PERF_USE_VMALLOC=y
# end of Kernel Performance Events And Counters
# CONFIG_PROFILING is not set
CONFIG_TRACEPOINTS=y
# end of General setup
CONFIG_X86_32=y
CONFIG_FORCE_DYNAMIC_FTRACE=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf32-i386"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_X86_32_SMP=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=2
#
# Processor type and features
#
CONFIG_SMP=y
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_MPPARSE=y
CONFIG_GOLDFISH=y
# CONFIG_X86_CPU_RESCTRL is not set
# CONFIG_X86_BIGSMP is not set
# CONFIG_X86_EXTENDED_PLATFORM is not set
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_X86_32_IRIS=m
# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_DEBUG is not set
# CONFIG_PARAVIRT_SPINLOCKS is not set
CONFIG_X86_HV_CALLBACK_VECTOR=y
CONFIG_KVM_GUEST=y
CONFIG_ARCH_CPUIDLE_HALTPOLL=y
# CONFIG_PVH is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_PARAVIRT_CLOCK=y
# CONFIG_M486SX is not set
# CONFIG_M486 is not set
CONFIG_M586=y
# CONFIG_M586TSC is not set
# CONFIG_M586MMX is not set
# CONFIG_M686 is not set
# CONFIG_MPENTIUMII is not set
# CONFIG_MPENTIUMIII is not set
# CONFIG_MPENTIUMM is not set
# CONFIG_MPENTIUM4 is not set
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MEFFICEON is not set
# CONFIG_MWINCHIPC6 is not set
# CONFIG_MWINCHIP3D is not set
# CONFIG_MELAN is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
# CONFIG_MCYRIXIII is not set
# CONFIG_MVIAC3_2 is not set
# CONFIG_MVIAC7 is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_X86_GENERIC=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_F00F_BUG=y
CONFIG_X86_ALIGNMENT_16=y
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_MINIMUM_CPU_FAMILY=4
CONFIG_IA32_FEAT_CTL=y
CONFIG_X86_VMX_FEATURE_NAMES=y
CONFIG_PROCESSOR_SELECT=y
CONFIG_CPU_SUP_INTEL=y
# CONFIG_CPU_SUP_CYRIX_32 is not set
# CONFIG_CPU_SUP_AMD is not set
# CONFIG_CPU_SUP_HYGON is not set
# CONFIG_CPU_SUP_CENTAUR is not set
CONFIG_CPU_SUP_TRANSMETA_32=y
CONFIG_CPU_SUP_UMC_32=y
# CONFIG_CPU_SUP_ZHAOXIN is not set
CONFIG_CPU_SUP_VORTEX_32=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_DMI=y
CONFIG_BOOT_VESA_SUPPORT=y
CONFIG_NR_CPUS_RANGE_BEGIN=2
CONFIG_NR_CPUS_RANGE_END=8
CONFIG_NR_CPUS_DEFAULT=8
CONFIG_NR_CPUS=8
CONFIG_SCHED_CLUSTER=y
CONFIG_SCHED_SMT=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_MC_PRIO is not set
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
# CONFIG_X86_MCE is not set
#
# Performance monitoring
#
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
# CONFIG_PERF_EVENTS_INTEL_RAPL is not set
# CONFIG_PERF_EVENTS_INTEL_CSTATE is not set
# end of Performance monitoring
# CONFIG_X86_LEGACY_VM86 is not set
# CONFIG_X86_16BIT is not set
CONFIG_X86_IOPL_IOPERM=y
# CONFIG_TOSHIBA is not set
CONFIG_X86_REBOOTFIXUPS=y
CONFIG_MICROCODE=y
CONFIG_MICROCODE_INTEL=y
# CONFIG_MICROCODE_LATE_LOADING is not set
CONFIG_X86_MSR=m
CONFIG_X86_CPUID=m
# CONFIG_NOHIGHMEM is not set
CONFIG_HIGHMEM4G=y
# CONFIG_VMSPLIT_3G is not set
# CONFIG_VMSPLIT_3G_OPT is not set
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_2G_OPT is not set
CONFIG_VMSPLIT_1G=y
CONFIG_PAGE_OFFSET=0x40000000
CONFIG_HIGHMEM=y
CONFIG_X86_CPA_STATISTICS=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ILLEGAL_POINTER_VALUE=0
# CONFIG_HIGHPTE is not set
# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
# CONFIG_MTRR is not set
CONFIG_X86_UMIP=y
CONFIG_CC_HAS_IBT=y
# CONFIG_X86_INTEL_TSX_MODE_OFF is not set
# CONFIG_X86_INTEL_TSX_MODE_ON is not set
CONFIG_X86_INTEL_TSX_MODE_AUTO=y
# CONFIG_EFI is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
CONFIG_HZ_1000=y
CONFIG_HZ=1000
CONFIG_SCHED_HRTICK=y
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
CONFIG_PHYSICAL_START=0x1000000
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_X86_NEED_RELOCS=y
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_HOTPLUG_CPU=y
CONFIG_BOOTPARAM_HOTPLUG_CPU0=y
# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
# CONFIG_COMPAT_VDSO is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_MODIFY_LDT_SYSCALL=y
CONFIG_STRICT_SIGALTSTACK_SIZE=y
# end of Processor type and features
CONFIG_CC_HAS_ENTRY_PADDING=y
CONFIG_FUNCTION_PADDING_CFI=11
CONFIG_FUNCTION_PADDING_BYTES=16
CONFIG_SPECULATION_MITIGATIONS=y
CONFIG_RETPOLINE=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
#
# Power management and ACPI options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
# CONFIG_ENERGY_MODEL is not set
CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
CONFIG_ACPI_TABLE_LIB=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SLEEP=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_TAD is not set
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_PROCESSOR=y
# CONFIG_ACPI_IPMI is not set
CONFIG_ACPI_HOTPLUG_CPU=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
# CONFIG_ACPI_APEI is not set
# CONFIG_ACPI_DPTF is not set
# CONFIG_ACPI_CONFIGFS is not set
# CONFIG_ACPI_FFH is not set
# CONFIG_PMIC_OPREGION is not set
CONFIG_ACPI_VIOT=y
CONFIG_X86_PM_TIMER=y
# CONFIG_APM is not set
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_X86_INTEL_PSTATE is not set
# CONFIG_X86_PCC_CPUFREQ is not set
# CONFIG_X86_AMD_PSTATE is not set
# CONFIG_X86_AMD_PSTATE_UT is not set
# CONFIG_X86_ACPI_CPUFREQ is not set
CONFIG_X86_POWERNOW_K6=m
CONFIG_X86_POWERNOW_K7=m
CONFIG_X86_POWERNOW_K7_ACPI=y
CONFIG_X86_GX_SUSPMOD=y
CONFIG_X86_SPEEDSTEP_CENTRINO=m
CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE=y
CONFIG_X86_SPEEDSTEP_ICH=m
# CONFIG_X86_SPEEDSTEP_SMI is not set
CONFIG_X86_P4_CLOCKMOD=y
CONFIG_X86_CPUFREQ_NFORCE2=m
CONFIG_X86_LONGRUN=y
# CONFIG_X86_LONGHAUL is not set
# CONFIG_X86_E_POWERSAVER is not set
#
# shared options
#
CONFIG_X86_SPEEDSTEP_LIB=y
# CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK is not set
# end of CPU Frequency scaling
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
CONFIG_HALTPOLL_CPUIDLE=y
# end of CPU Idle
# CONFIG_INTEL_IDLE is not set
# end of Power management and ACPI options
#
# Bus options (PCI etc.)
#
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GOMMCONFIG is not set
CONFIG_PCI_GODIRECT=y
# CONFIG_PCI_GOANY is not set
CONFIG_PCI_DIRECT=y
CONFIG_PCI_CNB20LE_QUIRK=y
CONFIG_ISA_BUS=y
CONFIG_ISA_DMA_API=y
CONFIG_ISA=y
CONFIG_SCx200=y
CONFIG_SCx200HR_TIMER=m
# CONFIG_OLPC is not set
# CONFIG_ALIX is not set
# CONFIG_NET5501 is not set
# CONFIG_GEOS is not set
# end of Bus options (PCI etc.)
#
# Binary Emulations
#
CONFIG_COMPAT_32=y
# end of Binary Emulations
CONFIG_HAVE_ATOMIC_IOMAP=y
CONFIG_HAVE_KVM=y
# CONFIG_VIRTUALIZATION is not set
CONFIG_AS_AVX512=y
CONFIG_AS_SHA1_NI=y
CONFIG_AS_SHA256_NI=y
CONFIG_AS_TPAUSE=y
#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_HOTPLUG_SMT=y
CONFIG_GENERIC_ENTRY=y
CONFIG_KPROBES=y
# CONFIG_JUMP_LABEL is not set
# CONFIG_STATIC_CALL_SELFTEST is not set
CONFIG_OPTPROBES=y
CONFIG_KPROBES_ON_FTRACE=y
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_KRETPROBE_ON_RETHOOK=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_GATHER_MERGE_VMAS=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
# CONFIG_SECCOMP is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ISA_BUS_API=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
CONFIG_HAVE_STATIC_CALL=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPLIT_ARG64=y
CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
CONFIG_DYNAMIC_SIGFRAME=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT_16B=y
CONFIG_FUNCTION_ALIGNMENT=16
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=1
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_WBT is not set
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
CONFIG_ACORN_PARTITION=y
# CONFIG_ACORN_PARTITION_CUMANA is not set
# CONFIG_ACORN_PARTITION_EESOX is not set
# CONFIG_ACORN_PARTITION_ICS is not set
# CONFIG_ACORN_PARTITION_ADFS is not set
# CONFIG_ACORN_PARTITION_POWERTEC is not set
# CONFIG_ACORN_PARTITION_RISCIX is not set
CONFIG_AIX_PARTITION=y
CONFIG_OSF_PARTITION=y
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
CONFIG_ULTRIX_PARTITION=y
# CONFIG_SUN_PARTITION is not set
CONFIG_KARMA_PARTITION=y
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
# end of Partition Types
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_MQ_RDMA=y
CONFIG_BLK_PM=y
#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=m
CONFIG_MQ_IOSCHED_KYBER=y
# CONFIG_IOSCHED_BFQ is not set
# end of IO Schedulers
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ELFCORE=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats
#
# Memory Management options
#
CONFIG_SWAP=y
# CONFIG_ZSWAP is not set
#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB_DEPRECATED is not set
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# end of SLAB allocator options
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
# CONFIG_PAGE_REPORTING is not set
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_BOUNCE=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_READ_ONLY_THP_FOR_FS=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_CMA=y
CONFIG_CMA_DEBUG=y
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
# CONFIG_ZONE_DMA is not set
CONFIG_VMAP_PFN=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MAPPING_DIRTY_HELPERS=y
CONFIG_KMAP_LOCAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
# CONFIG_LRU_GEN is not set
#
# Data Access Monitoring
#
CONFIG_DAMON=y
# CONFIG_DAMON_VADDR is not set
# CONFIG_DAMON_PADDR is not set
# CONFIG_DAMON_SYSFS is not set
# end of Data Access Monitoring
# end of Memory Management options
CONFIG_NET=y
CONFIG_SKB_EXTENSIONS=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=m
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_SMC=m
CONFIG_SMC_DIAG=m
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
CONFIG_IP_PNP_RARP=y
# CONFIG_NET_IPIP is not set
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
# CONFIG_IP_MROUTE is not set
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=m
# CONFIG_INET_RAW_DIAG is not set
CONFIG_INET_DIAG_DESTROY=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
CONFIG_IPV6_ILA=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
# CONFIG_IPV6_SIT is not set
CONFIG_IPV6_TUNNEL=m
# CONFIG_IPV6_GRE is not set
CONFIG_IPV6_FOU=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
# CONFIG_MPTCP is not set
CONFIG_NETWORK_SECMARK=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_INGRESS is not set
# CONFIG_NETFILTER_EGRESS is not set
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_PROCFS=y
# CONFIG_NF_CONNTRACK_LABELS is not set
# CONFIG_NF_CONNTRACK_FTP is not set
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_TABLES=m
# CONFIG_NF_TABLES_INET is not set
# CONFIG_NF_TABLES_NETDEV is not set
# CONFIG_NFT_NUMGEN is not set
# CONFIG_NFT_CT is not set
CONFIG_NFT_LOG=m
# CONFIG_NFT_LIMIT is not set
# CONFIG_NFT_MASQ is not set
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
# CONFIG_NFT_QUOTA is not set
CONFIG_NFT_REJECT=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
# CONFIG_NFT_XFRM is not set
CONFIG_NFT_SOCKET=m
# CONFIG_NFT_TPROXY is not set
CONFIG_NETFILTER_XTABLES=y
#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set
# CONFIG_NETFILTER_XT_TARGET_LOG is not set
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
# CONFIG_NETFILTER_XT_TARGET_MASQUERADE is not set
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
# end of Core Netfilter Configuration
CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
# CONFIG_IP_SET_BITMAP_IP is not set
CONFIG_IP_SET_BITMAP_IPMAC=m
# CONFIG_IP_SET_BITMAP_PORT is not set
# CONFIG_IP_SET_HASH_IP is not set
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
# CONFIG_IP_SET_HASH_IPPORTNET is not set
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
# CONFIG_IP_SET_HASH_NETPORTNET is not set
CONFIG_IP_SET_HASH_NET=m
# CONFIG_IP_SET_HASH_NETNET is not set
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
# CONFIG_IP_VS_IPV6 is not set
CONFIG_IP_VS_DEBUG=y
CONFIG_IP_VS_TAB_BITS=12
#
# IPVS transport protocol load balancing support
#
# CONFIG_IP_VS_PROTO_TCP is not set
# CONFIG_IP_VS_PROTO_UDP is not set
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
# CONFIG_IP_VS_PROTO_SCTP is not set
#
# IPVS scheduler
#
# CONFIG_IP_VS_RR is not set
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
# CONFIG_IP_VS_OVF is not set
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
# CONFIG_IP_VS_NQ is not set
# CONFIG_IP_VS_TWOS is not set
#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8
#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12
#
# IPVS application helper
#
CONFIG_IP_VS_NFCT=y
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_TPROXY_IPV4=m
# CONFIG_NF_TABLES_IPV4 is not set
# CONFIG_NF_TABLES_ARP is not set
# CONFIG_NF_DUP_IPV4 is not set
CONFIG_NF_LOG_ARP=y
# CONFIG_NF_LOG_IPV4 is not set
CONFIG_NF_REJECT_IPV4=y
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_FILTER is not set
# CONFIG_IP_NF_NAT is not set
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_RAW=m
# end of IP: Netfilter Configuration
#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
# CONFIG_NFT_DUP_IPV6 is not set
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
# CONFIG_NF_LOG_IPV6 is not set
# CONFIG_IP6_NF_IPTABLES is not set
# end of IPv6: Netfilter Configuration
CONFIG_NF_DEFRAG_IPV6=m
CONFIG_NF_TABLES_BRIDGE=m
# CONFIG_NFT_BRIDGE_META is not set
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
# CONFIG_BRIDGE_EBT_802_3 is not set
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
# CONFIG_BRIDGE_EBT_LIMIT is not set
# CONFIG_BRIDGE_EBT_MARK is not set
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
# CONFIG_BRIDGE_EBT_REDIRECT is not set
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=y
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m
#
# DCCP CCIDs Configuration
#
CONFIG_IP_DCCP_CCID2_DEBUG=y
# CONFIG_IP_DCCP_CCID3 is not set
# end of DCCP CCIDs Configuration
#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_CLIP_NO_ICMP=y
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=y
# CONFIG_L2TP_ETH is not set
CONFIG_STP=y
CONFIG_GARP=y
CONFIG_MRP=y
CONFIG_BRIDGE=m
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_NONE=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
# CONFIG_NET_DSA_TAG_GSWIP is not set
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=y
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
# CONFIG_COPS is not set
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_X25=y
CONFIG_LAPB=m
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
CONFIG_IEEE802154=y
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=y
CONFIG_MAC802154=y
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
# CONFIG_DNS_RESOLVER is not set
CONFIG_BATMAN_ADV=m
# CONFIG_BATMAN_ADV_BATMAN_V is not set
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
CONFIG_BATMAN_ADV_DEBUG=y
CONFIG_BATMAN_ADV_TRACING=y
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=m
CONFIG_MPLS=y
# CONFIG_NET_MPLS_GSO is not set
# CONFIG_MPLS_ROUTING is not set
CONFIG_NET_NSH=y
CONFIG_HSR=m
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
# CONFIG_QRTR is not set
CONFIG_NET_NCSI=y
CONFIG_NCSI_OEM_CMD_GET_MAC=y
CONFIG_NCSI_OEM_CMD_KEEP_PHY=y
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_NET_FLOW_LIMIT=y
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NET_DROP_MONITOR=y
# end of Network testing
# end of Networking options
CONFIG_HAMRADIO=y
#
# Packet Radio protocols
#
# CONFIG_AX25 is not set
# CONFIG_CAN is not set
CONFIG_BT=y
# CONFIG_BT_BREDR is not set
# CONFIG_BT_LE is not set
# CONFIG_BT_LEDS is not set
CONFIG_BT_MSFTEXT=y
CONFIG_BT_AOSPEXT=y
CONFIG_BT_DEBUGFS=y
# CONFIG_BT_SELFTEST is not set
# CONFIG_BT_FEATURE_DEBUG is not set
#
# Bluetooth device drivers
#
CONFIG_BT_MTK=y
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM4377 is not set
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=y
CONFIG_BT_MTKUART=y
# CONFIG_BT_VIRTIO is not set
# end of Bluetooth device drivers
CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
CONFIG_AF_RXRPC_DEBUG=y
# CONFIG_RXKAD is not set
# CONFIG_RXPERF is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
CONFIG_MCTP=y
CONFIG_FIB_RULES=y
# CONFIG_WIRELESS is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
# CONFIG_RFKILL_INPUT is not set
CONFIG_RFKILL_GPIO=y
CONFIG_NET_9P=y
CONFIG_NET_9P_FD=y
CONFIG_NET_9P_VIRTIO=y
# CONFIG_NET_9P_RDMA is not set
# CONFIG_NET_9P_DEBUG is not set
CONFIG_CAIF=y
CONFIG_CAIF_DEBUG=y
# CONFIG_CAIF_NETDEV is not set
CONFIG_CAIF_USB=m
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
# CONFIG_FAILOVER is not set
CONFIG_ETHTOOL_NETLINK=y
#
# Device Drivers
#
CONFIG_HAVE_EISA=y
# CONFIG_EISA is not set
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCIEPORTBUS is not set
# CONFIG_PCIEASPM is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
CONFIG_PCI_STUB=y
CONFIG_PCI_ATS=y
CONFIG_PCI_DOE=y
CONFIG_PCI_LOCKLESS_CONFIG=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
# CONFIG_PCIE_BUS_DEFAULT is not set
CONFIG_PCIE_BUS_SAFE=y
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_VGA_ARB is not set
# CONFIG_HOTPLUG_PCI is not set
#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
CONFIG_PCIE_XILINX=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
# CONFIG_PCIE_DW_PLAT_EP is not set
CONFIG_PCIE_INTEL_GW=y
CONFIG_PCI_MESON=m
# end of DesignWare PCI Core Support
#
# Mobiveil PCIe Core Support
#
# end of Mobiveil PCIe Core Support
#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# CONFIG_PCI_J721E_HOST is not set
# CONFIG_PCI_J721E_EP is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers
#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
# CONFIG_PCI_EPF_NTB is not set
# end of PCI Endpoint
#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=y
# end of PCI switch controller drivers
CONFIG_CXL_BUS=y
CONFIG_CXL_PCI=y
CONFIG_CXL_MEM_RAW_COMMANDS=y
CONFIG_CXL_ACPI=y
CONFIG_CXL_MEM=m
CONFIG_CXL_PORT=y
CONFIG_CXL_SUSPEND=y
# CONFIG_PCCARD is not set
CONFIG_RAPIDIO=y
CONFIG_RAPIDIO_DISC_TIMEOUT=30
CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
CONFIG_RAPIDIO_DEBUG=y
CONFIG_RAPIDIO_ENUM_BASIC=m
CONFIG_RAPIDIO_CHMAN=m
CONFIG_RAPIDIO_MPORT_CDEV=m
#
# RapidIO Switch drivers
#
CONFIG_RAPIDIO_CPS_XX=y
CONFIG_RAPIDIO_CPS_GEN2=y
CONFIG_RAPIDIO_RXS_GEN3=m
# end of RapidIO Switch drivers
#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader
CONFIG_WANT_DEV_COREDUMP=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_W1=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_FENCE_TRACE=y
# end of Generic Driver Options
#
# Bus devices
#
CONFIG_MOXTET=m
CONFIG_MHI_BUS=y
CONFIG_MHI_BUS_DEBUG=y
CONFIG_MHI_BUS_PCI_GENERIC=m
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices
CONFIG_CONNECTOR=m
#
# Firmware Drivers
#
#
# ARM System Control and Management Interface Protocol
#
# end of ARM System Control and Management Interface Protocol
# CONFIG_EDD is not set
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
# CONFIG_DMI_SYSFS is not set
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
# CONFIG_ISCSI_IBFT is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_GOOGLE_FIRMWARE is not set
#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers
CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
# CONFIG_GNSS_MTK_SERIAL is not set
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
# CONFIG_MTD is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=m
# CONFIG_PARPORT_SERIAL is not set
CONFIG_PARPORT_PC_FIFO=y
CONFIG_PARPORT_PC_SUPERIO=y
CONFIG_PARPORT_AX88796=y
# CONFIG_PARPORT_1284 is not set
CONFIG_PARPORT_NOT_PC=y
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y
#
# Protocols
#
# CONFIG_ISAPNP is not set
# CONFIG_PNPBIOS is not set
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_FD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_ZRAM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_VIRTIO_BLK is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set
# CONFIG_BLK_DEV_RNBD_CLIENT is not set
# CONFIG_BLK_DEV_RNBD_SERVER is not set
#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_VERBOSE_ERRORS is not set
# CONFIG_NVME_HWMON is not set
CONFIG_NVME_FABRICS=y
CONFIG_NVME_RDMA=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=y
# CONFIG_NVME_AUTH is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support
#
# Misc devices
#
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
CONFIG_AD525X_DPOT_SPI=m
# CONFIG_DUMMY_IRQ is not set
# CONFIG_IBM_ASM is not set
CONFIG_PHANTOM=y
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
CONFIG_ENCLOSURE_SERVICES=y
CONFIG_CS5535_MFGPT=y
CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
CONFIG_CS5535_CLOCK_EVENT_SRC=m
CONFIG_HI6421V600_IRQ=m
# CONFIG_HP_ILO is not set
CONFIG_APDS9802ALS=y
CONFIG_ISL29003=y
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
CONFIG_SENSORS_BH1770=y
# CONFIG_SENSORS_APDS990X is not set
CONFIG_HMC6352=y
CONFIG_DS1682=y
CONFIG_PCH_PHUB=y
CONFIG_LATTICE_ECP3_CONFIG=m
CONFIG_SRAM=y
CONFIG_DW_XDATA_PCIE=m
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_XILINX_SDFEC=y
CONFIG_MISC_RTSX=m
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=m
CONFIG_EEPROM_LEGACY=y
CONFIG_EEPROM_MAX6875=y
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
CONFIG_EEPROM_IDT_89HPESX=m
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support
CONFIG_CB710_CORE=m
CONFIG_CB710_DEBUG=y
CONFIG_CB710_DEBUG_ASSUMPTIONS=y
#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
CONFIG_INTEL_MEI=m
CONFIG_INTEL_MEI_ME=m
# CONFIG_INTEL_MEI_TXE is not set
# CONFIG_INTEL_MEI_GSC is not set
CONFIG_INTEL_MEI_HDCP=m
# CONFIG_INTEL_MEI_PXP is not set
# CONFIG_VMWARE_VMCI is not set
CONFIG_ECHO=y
CONFIG_BCM_VK=m
# CONFIG_BCM_VK_TTY is not set
# CONFIG_MISC_ALCOR_PCI is not set
CONFIG_MISC_RTSX_PCI=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=y
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
# CONFIG_BLK_DEV_SD is not set
# CONFIG_CHR_DEV_ST is not set
# CONFIG_BLK_DEV_SR is not set
CONFIG_CHR_DEV_SG=y
CONFIG_BLK_DEV_BSG=y
CONFIG_CHR_DEV_SCH=m
# CONFIG_SCSI_ENCLOSURE is not set
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SRP_ATTRS=y
# end of SCSI Transports
CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=y
CONFIG_ISCSI_BOOT_SYSFS=y
CONFIG_SCSI_CXGB3_ISCSI=m
# CONFIG_SCSI_CXGB4_ISCSI is not set
CONFIG_SCSI_BNX2_ISCSI=m
CONFIG_BE2ISCSI=y
CONFIG_BLK_DEV_3W_XXXX_RAID=m
CONFIG_SCSI_HPSA=m
# CONFIG_SCSI_3W_9XXX is not set
CONFIG_SCSI_3W_SAS=y
CONFIG_SCSI_ACARD=m
# CONFIG_SCSI_AHA152X is not set
CONFIG_SCSI_AHA1542=m
CONFIG_SCSI_AACRAID=m
CONFIG_SCSI_AIC7XXX=m
CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
CONFIG_AIC7XXX_RESET_DELAY_MS=5000
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
CONFIG_AIC7XXX_DEBUG_MASK=0
CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
CONFIG_SCSI_AIC79XX=m
CONFIG_AIC79XX_CMDS_PER_DEVICE=32
CONFIG_AIC79XX_RESET_DELAY_MS=5000
# CONFIG_AIC79XX_DEBUG_ENABLE is not set
CONFIG_AIC79XX_DEBUG_MASK=0
# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
CONFIG_SCSI_AIC94XX=m
CONFIG_AIC94XX_DEBUG=y
CONFIG_SCSI_MVSAS=m
CONFIG_SCSI_MVSAS_DEBUG=y
# CONFIG_SCSI_MVSAS_TASKLET is not set
CONFIG_SCSI_MVUMI=y
CONFIG_SCSI_ADVANSYS=y
CONFIG_SCSI_ARCMSR=y
CONFIG_SCSI_ESAS2R=y
# CONFIG_MEGARAID_NEWGEN is not set
CONFIG_MEGARAID_LEGACY=m
# CONFIG_MEGARAID_SAS is not set
CONFIG_SCSI_MPT3SAS=m
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
CONFIG_SCSI_MPT3SAS_MAX_SGE=128
CONFIG_SCSI_MPT2SAS=m
CONFIG_SCSI_MPI3MR=y
CONFIG_SCSI_SMARTPQI=y
CONFIG_SCSI_HPTIOP=m
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
CONFIG_SCSI_MYRS=y
CONFIG_VMWARE_PVSCSI=y
CONFIG_SCSI_SNIC=y
# CONFIG_SCSI_SNIC_DEBUG_FS is not set
# CONFIG_SCSI_DMX3191D is not set
CONFIG_SCSI_FDOMAIN=m
CONFIG_SCSI_FDOMAIN_PCI=m
# CONFIG_SCSI_FDOMAIN_ISA is not set
CONFIG_SCSI_ISCI=y
CONFIG_SCSI_GENERIC_NCR5380=y
CONFIG_SCSI_IPS=m
CONFIG_SCSI_INITIO=y
CONFIG_SCSI_INIA100=m
CONFIG_SCSI_PPA=m
# CONFIG_SCSI_IMM is not set
# CONFIG_SCSI_IZIP_EPP16 is not set
CONFIG_SCSI_IZIP_SLOW_CTR=y
# CONFIG_SCSI_STEX is not set
CONFIG_SCSI_SYM53C8XX_2=m
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
# CONFIG_SCSI_SYM53C8XX_MMIO is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
CONFIG_SCSI_DC395x=y
CONFIG_SCSI_AM53C974=y
# CONFIG_SCSI_NSP32 is not set
CONFIG_SCSI_WD719X=m
# CONFIG_SCSI_DEBUG is not set
CONFIG_SCSI_PMCRAID=m
CONFIG_SCSI_PM8001=m
# CONFIG_SCSI_VIRTIO is not set
CONFIG_SCSI_DH=y
# CONFIG_SCSI_DH_RDAC is not set
CONFIG_SCSI_DH_HP_SW=y
# CONFIG_SCSI_DH_EMC is not set
# CONFIG_SCSI_DH_ALUA is not set
# end of SCSI device support
CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
# CONFIG_ATA_FORCE is not set
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y
#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=m
# CONFIG_AHCI_DWC is not set
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_QORIQ=m
# CONFIG_SATA_INIC162X is not set
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=y
# CONFIG_ATA_SFF is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=y
CONFIG_FIREWIRE_OHCI=m
# CONFIG_FIREWIRE_SBP2 is not set
CONFIG_FIREWIRE_NET=y
CONFIG_FIREWIRE_NOSY=y
# end of IEEE 1394 (FireWire) support
CONFIG_MACINTOSH_DRIVERS=y
# CONFIG_MAC_EMUMOUSEBTN is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
# CONFIG_NET_CORE is not set
# CONFIG_ARCNET is not set
CONFIG_ATM_DRIVERS=y
CONFIG_ATM_DUMMY=m
# CONFIG_ATM_TCP is not set
CONFIG_ATM_LANAI=m
# CONFIG_ATM_ENI is not set
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_NICSTAR_USE_SUNI=y
CONFIG_ATM_NICSTAR_USE_IDT77105=y
CONFIG_ATM_IDT77252=m
CONFIG_ATM_IDT77252_DEBUG=y
CONFIG_ATM_IDT77252_RCV_ALL=y
CONFIG_ATM_IDT77252_USE_SUNI=y
# CONFIG_ATM_IA is not set
CONFIG_ATM_FORE200E=m
CONFIG_ATM_FORE200E_USE_TASKLET=y
CONFIG_ATM_FORE200E_TX_RETRY=16
CONFIG_ATM_FORE200E_DEBUG=0
# CONFIG_ATM_HE is not set
CONFIG_ATM_SOLOS=m
CONFIG_CAIF_DRIVERS=y
# CONFIG_CAIF_TTY is not set
CONFIG_CAIF_VIRTIO=y
#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
# CONFIG_B53_MDIO_DRIVER is not set
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
# CONFIG_NET_DSA_MT7530 is not set
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
CONFIG_NET_DSA_MV88E6XXX=m
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
# CONFIG_NET_DSA_REALTEK is not set
CONFIG_NET_DSA_SMSC_LAN9303=m
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers
CONFIG_ETHERNET=y
CONFIG_MDIO=y
CONFIG_NET_VENDOR_3COM=y
CONFIG_EL3=m
CONFIG_3C515=y
CONFIG_VORTEX=y
CONFIG_TYPHOON=y
# CONFIG_NET_VENDOR_ADAPTEC is not set
CONFIG_NET_VENDOR_AGERE=y
CONFIG_ET131X=m
CONFIG_NET_VENDOR_ALACRITECH=y
CONFIG_SLICOSS=m
# CONFIG_NET_VENDOR_ALTEON is not set
CONFIG_ALTERA_TSE=m
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_AQTION=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ASIX is not set
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=y
# CONFIG_ATL1 is not set
CONFIG_ATL1E=m
# CONFIG_ATL1C is not set
# CONFIG_ALX is not set
# CONFIG_CX_ECAT is not set
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_BCMGENET is not set
CONFIG_BNX2=y
CONFIG_CNIC=m
CONFIG_TIGON3=m
CONFIG_TIGON3_HWMON=y
# CONFIG_BNX2X is not set
# CONFIG_SYSTEMPORT is not set
CONFIG_BNXT=m
CONFIG_BNXT_FLOWER_OFFLOAD=y
# CONFIG_BNXT_HWMON is not set
CONFIG_NET_VENDOR_CADENCE=y
# CONFIG_MACB is not set
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NET_VENDOR_CHELSIO=y
CONFIG_CHELSIO_T1=y
CONFIG_CHELSIO_T1_1G=y
CONFIG_CHELSIO_T3=y
# CONFIG_CHELSIO_T4 is not set
CONFIG_CHELSIO_T4VF=y
CONFIG_CHELSIO_LIB=m
# CONFIG_NET_VENDOR_CIRRUS is not set
CONFIG_NET_VENDOR_CISCO=y
CONFIG_ENIC=m
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
CONFIG_DNET=y
# CONFIG_NET_VENDOR_DEC is not set
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=y
# CONFIG_SUNDANCE is not set
CONFIG_NET_VENDOR_EMULEX=y
CONFIG_BE2NET=y
# CONFIG_BE2NET_HWMON is not set
# CONFIG_BE2NET_BE2 is not set
# CONFIG_BE2NET_BE3 is not set
CONFIG_BE2NET_LANCER=y
CONFIG_BE2NET_SKYHAWK=y
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_HINIC is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_E1000E_HWTS=y
CONFIG_IGB=m
# CONFIG_IGB_HWMON is not set
CONFIG_IGBVF=y
CONFIG_IXGB=m
CONFIG_IXGBE=y
# CONFIG_IXGBE_HWMON is not set
# CONFIG_IXGBE_IPSEC is not set
CONFIG_IXGBEVF=m
CONFIG_IXGBEVF_IPSEC=y
CONFIG_I40E=y
# CONFIG_I40EVF is not set
CONFIG_ICE=m
# CONFIG_ICE_SWITCHDEV is not set
CONFIG_ICE_HWTS=y
CONFIG_FM10K=y
CONFIG_IGC=m
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_JME is not set
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=y
CONFIG_MLX4_CORE=y
# CONFIG_MLX4_DEBUG is not set
# CONFIG_MLX4_CORE_GEN2 is not set
# CONFIG_MLX5_CORE is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
CONFIG_KSZ884X_PCI=m
CONFIG_NET_VENDOR_MICROCHIP=y
CONFIG_ENC28J60=y
CONFIG_ENC28J60_WRITEVERIFY=y
CONFIG_ENCX24J600=y
# CONFIG_LAN743X is not set
# CONFIG_LAN966X_SWITCH is not set
# CONFIG_VCAP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
# CONFIG_MSCC_OCELOT_SWITCH is not set
CONFIG_NET_VENDOR_MICROSOFT=y
# CONFIG_NET_VENDOR_MYRI is not set
CONFIG_NET_VENDOR_NI=y
CONFIG_NI_XGE_MANAGEMENT_ENET=y
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=m
# CONFIG_NS83820 is not set
CONFIG_NET_VENDOR_NETERION=y
CONFIG_S2IO=y
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_8390 is not set
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=m
CONFIG_NET_VENDOR_OKI=y
CONFIG_ETHOC=y
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
CONFIG_NET_VENDOR_PENSANDO=y
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
CONFIG_QCA7000=y
CONFIG_QCA7000_SPI=y
CONFIG_QCA7000_UART=m
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_ATP=m
CONFIG_8139CP=m
# CONFIG_8139TOO is not set
# CONFIG_R8169 is not set
# CONFIG_NET_VENDOR_RENESAS is not set
CONFIG_NET_VENDOR_ROCKER=y
# CONFIG_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=m
# CONFIG_NET_VENDOR_SIS is not set
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
CONFIG_SFC_FALCON=m
CONFIG_NET_VENDOR_SMSC=y
CONFIG_SMC9194=m
CONFIG_EPIC100=m
# CONFIG_SMSC911X is not set
CONFIG_SMSC9420=y
# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
CONFIG_TEHUTI=y
CONFIG_NET_VENDOR_TI=y
CONFIG_TI_CPSW_PHY_SEL=y
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
CONFIG_NET_VENDOR_VIA=y
# CONFIG_VIA_RHINE is not set
CONFIG_VIA_VELOCITY=y
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_FDDI=m
# CONFIG_DEFXX is not set
CONFIG_SKFP=m
CONFIG_HIPPI=y
CONFIG_ROADRUNNER=m
# CONFIG_ROADRUNNER_LARGE_RINGS is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=m
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set
#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
CONFIG_ADIN_PHY=m
# CONFIG_ADIN1100_PHY is not set
CONFIG_AQUANTIA_PHY=y
# CONFIG_AX88796B_PHY is not set
CONFIG_BROADCOM_PHY=y
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
CONFIG_BCM84881_PHY=y
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=y
# CONFIG_CICADA_PHY is not set
CONFIG_CORTINA_PHY=m
CONFIG_DAVICOM_PHY=y
# CONFIG_ICPLUS_PHY is not set
CONFIG_LXT_PHY=m
CONFIG_INTEL_XWAY_PHY=y
# CONFIG_LSI_ET1011C_PHY is not set
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=y
CONFIG_MARVELL_88X2222_PHY=y
# CONFIG_MAXLINEAR_GPHY is not set
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MICREL_PHY=y
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROCHIP_T1_PHY is not set
CONFIG_MICROSEMI_PHY=m
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
CONFIG_NXP_C45_TJA11XX_PHY=y
CONFIG_NXP_TJA11XX_PHY=y
# CONFIG_AT803X_PHY is not set
CONFIG_QSEMI_PHY=y
CONFIG_REALTEK_PHY=m
CONFIG_RENESAS_PHY=y
# CONFIG_ROCKCHIP_PHY is not set
CONFIG_SMSC_PHY=y
# CONFIG_STE10XP is not set
CONFIG_TERANETICS_PHY=y
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
CONFIG_DP83867_PHY=m
CONFIG_DP83869_PHY=y
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=y
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
#
# MCTP Device Drivers
#
# CONFIG_MCTP_SERIAL is not set
# CONFIG_MCTP_TRANSPORT_I2C is not set
# end of MCTP Device Drivers
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BCM_UNIMAC=y
# CONFIG_MDIO_GPIO is not set
CONFIG_MDIO_HISI_FEMAC=m
CONFIG_MDIO_MSCC_MIIM=m
# CONFIG_MDIO_IPQ4019 is not set
CONFIG_MDIO_IPQ8064=y
#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m
CONFIG_MDIO_BUS_MUX_MMIOREG=y
#
# PCS device drivers
#
CONFIG_PCS_XPCS=m
CONFIG_PCS_ALTERA_TSE=m
# end of PCS device drivers
CONFIG_PLIP=y
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=y
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
# CONFIG_PPP_ASYNC is not set
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=y
#
# Host-side USB support is needed for USB Network Adapter support
#
# CONFIG_WLAN is not set
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
# CONFIG_IEEE802154_AT86RF230 is not set
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m
#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN
CONFIG_VMXNET3=y
# CONFIG_FUJITSU_ES is not set
# CONFIG_NETDEVSIM is not set
# CONFIG_NET_FAILOVER is not set
CONFIG_NETDEV_LEGACY_INIT=y
CONFIG_ISDN=y
CONFIG_ISDN_CAPI=y
CONFIG_MISDN=y
CONFIG_MISDN_DSP=y
CONFIG_MISDN_L1OIP=y
#
# mISDN hardware drivers
#
CONFIG_MISDN_HFCPCI=y
CONFIG_MISDN_HFCMULTI=m
# CONFIG_MISDN_AVMFRITZ is not set
CONFIG_MISDN_SPEEDFAX=m
CONFIG_MISDN_INFINEON=m
# CONFIG_MISDN_W6692 is not set
# CONFIG_MISDN_NETJET is not set
CONFIG_MISDN_IPAC=m
CONFIG_MISDN_ISAR=m
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set
CONFIG_INPUT_VIVALDIFMAP=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5520 is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_IQS62X is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CROS_EC is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_MTK_PMIC is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
# CONFIG_MOUSE_PS2_VMMOUSE is not set
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_INPORT is not set
# CONFIG_MOUSE_LOGIBM is not set
# CONFIG_MOUSE_PC110PAD is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_RMI4_CORE is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PARKBD is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=m
CONFIG_SERIO_ALTERA_PS2=m
CONFIG_SERIO_PS2MULT=m
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_GPIO_PS2=m
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
CONFIG_GAMEPORT_NS558=m
# CONFIG_GAMEPORT_L4 is not set
CONFIG_GAMEPORT_EMU10K1=m
CONFIG_GAMEPORT_FM801=m
# end of Hardware I/O ports
# end of Input device support
#
# Character devices
#
CONFIG_TTY=y
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
# CONFIG_SERIAL_8250_MEN_MCB is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
CONFIG_SERIAL_8250_DWLIB=y
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_LPSS=y
CONFIG_SERIAL_8250_MID=y
CONFIG_SERIAL_8250_PERICOM=y
# CONFIG_SERIAL_OF_PLATFORM is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_LANTIQ is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_PCH_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_MEN_Z135 is not set
# CONFIG_SERIAL_SPRD is not set
# CONFIG_SERIAL_LITEUART is not set
# end of Serial drivers
CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_GOLDFISH_TTY is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_PRINTER=m
CONFIG_LP_CONSOLE=y
# CONFIG_PPDEV is not set
# CONFIG_VIRTIO_CONSOLE is not set
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_DMI_DECODE=y
CONFIG_IPMI_PLAT_DATA=y
# CONFIG_IPMI_PANIC_EVENT is not set
# CONFIG_IPMI_DEVICE_INTERFACE is not set
CONFIG_IPMI_SI=m
# CONFIG_IPMI_SSIF is not set
CONFIG_IPMI_IPMB=m
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
# CONFIG_HW_RANDOM_INTEL is not set
# CONFIG_HW_RANDOM_AMD is not set
CONFIG_HW_RANDOM_BA431=m
CONFIG_HW_RANDOM_GEODE=m
CONFIG_HW_RANDOM_VIA=y
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_CCTRNG=m
CONFIG_HW_RANDOM_XIPHERA=y
CONFIG_DTLK=m
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
# CONFIG_MWAVE is not set
CONFIG_SCx200_GPIO=m
# CONFIG_PC8736x_GPIO is not set
CONFIG_NSC_GPIO=m
CONFIG_DEVMEM=y
CONFIG_NVRAM=m
CONFIG_DEVPORT=y
# CONFIG_HPET is not set
CONFIG_HANGCHECK_TIMER=y
CONFIG_TCG_TPM=y
# CONFIG_HW_RANDOM_TPM is not set
CONFIG_TCG_TIS_CORE=y
CONFIG_TCG_TIS=y
CONFIG_TCG_TIS_SPI=m
# CONFIG_TCG_TIS_SPI_CR50 is not set
# CONFIG_TCG_TIS_I2C is not set
CONFIG_TCG_TIS_I2C_CR50=y
# CONFIG_TCG_TIS_I2C_ATMEL is not set
# CONFIG_TCG_TIS_I2C_INFINEON is not set
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
CONFIG_TCG_NSC=y
CONFIG_TCG_ATMEL=y
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
CONFIG_TCG_VTPM_PROXY=m
CONFIG_TCG_TIS_ST33ZP24=y
CONFIG_TCG_TIS_ST33ZP24_I2C=y
# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
CONFIG_TELCLOCK=y
# CONFIG_XILLYBUS is not set
# end of Character devices
#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
# CONFIG_I2C_MUX_GPIO is not set
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
CONFIG_I2C_DEMUX_PINCTRL=y
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_SMBUS=y
#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=y
# end of I2C Algorithms
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=y
CONFIG_I2C_ALI1535=m
# CONFIG_I2C_ALI1563 is not set
CONFIG_I2C_ALI15X3=y
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
CONFIG_I2C_I801=y
# CONFIG_I2C_ISCH is not set
CONFIG_I2C_ISMT=y
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
CONFIG_I2C_NVIDIA_GPU=y
CONFIG_I2C_SIS5595=y
# CONFIG_I2C_SIS630 is not set
CONFIG_I2C_SIS96X=m
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CBUS_GPIO=y
CONFIG_I2C_DESIGNWARE_CORE=m
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=m
# CONFIG_I2C_DESIGNWARE_AMDPSP is not set
# CONFIG_I2C_DESIGNWARE_BAYTRAIL is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
CONFIG_I2C_EG20T=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
CONFIG_I2C_OCORES=m
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_PXA=y
CONFIG_I2C_PXA_PCI=y
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
CONFIG_I2C_XILINX=m
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_PCA_ISA=y
CONFIG_I2C_CROS_EC_TUNNEL=m
# CONFIG_SCx200_ACB is not set
CONFIG_I2C_VIRTIO=y
# end of I2C Hardware Bus support
# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
# CONFIG_I2C_SLAVE_EEPROM is not set
# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support
CONFIG_I3C=m
# CONFIG_CDNS_I3C_MASTER is not set
CONFIG_DW_I3C_MASTER=m
CONFIG_SVC_I3C_MASTER=m
# CONFIG_MIPI_I3C_HCI is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
# CONFIG_SPI_MEM is not set
#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_BUTTERFLY is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
CONFIG_SPI_DESIGNWARE=m
# CONFIG_SPI_DW_DMA is not set
# CONFIG_SPI_DW_PCI is not set
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_NXP_FLEXSPI is not set
CONFIG_SPI_GPIO=y
CONFIG_SPI_LM70_LLP=y
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
CONFIG_SPI_LANTIQ_SSC=y
CONFIG_SPI_OC_TINY=y
# CONFIG_SPI_PCI1XXXX is not set
# CONFIG_SPI_PXA2XX is not set
CONFIG_SPI_ROCKCHIP=m
CONFIG_SPI_SC18IS602=y
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_TOPCLIFF_PCH is not set
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=y
# CONFIG_SPI_AMD is not set
#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m
#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_TLE62X0=m
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=y
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=m
CONFIG_SPMI_HISI3670=m
CONFIG_HSI=y
CONFIG_HSI_BOARDINFO=y
#
# HSI controllers
#
#
# HSI clients
#
CONFIG_HSI_CHAR=m
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
CONFIG_NTP_PPS=y
#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
CONFIG_PPS_CLIENT_PARPORT=m
CONFIG_PPS_CLIENT_GPIO=m
#
# PPS generators support
#
#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# end of PTP clock support
CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
CONFIG_DEBUG_PINCTRL=y
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_DA9062=m
CONFIG_PINCTRL_EQUILIBRIUM=y
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
CONFIG_PINCTRL_MICROCHIP_SGPIO=y
# CONFIG_PINCTRL_OCELOT is not set
# CONFIG_PINCTRL_PALMAS is not set
# CONFIG_PINCTRL_RK805 is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=m
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_MADERA=y
CONFIG_PINCTRL_CS47L35=y
#
# Intel pinctrl drivers
#
# CONFIG_PINCTRL_BAYTRAIL is not set
# CONFIG_PINCTRL_CHERRYVIEW is not set
# CONFIG_PINCTRL_LYNXPOINT is not set
# CONFIG_PINCTRL_ALDERLAKE is not set
# CONFIG_PINCTRL_BROXTON is not set
# CONFIG_PINCTRL_CANNONLAKE is not set
# CONFIG_PINCTRL_CEDARFORK is not set
# CONFIG_PINCTRL_DENVERTON is not set
# CONFIG_PINCTRL_ELKHARTLAKE is not set
# CONFIG_PINCTRL_EMMITSBURG is not set
# CONFIG_PINCTRL_GEMINILAKE is not set
# CONFIG_PINCTRL_ICELAKE is not set
# CONFIG_PINCTRL_JASPERLAKE is not set
# CONFIG_PINCTRL_LAKEFIELD is not set
# CONFIG_PINCTRL_LEWISBURG is not set
# CONFIG_PINCTRL_METEORLAKE is not set
# CONFIG_PINCTRL_SUNRISEPOINT is not set
# CONFIG_PINCTRL_TIGERLAKE is not set
# end of Intel pinctrl drivers
#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
CONFIG_GPIO_CDEV=y
# CONFIG_GPIO_CDEV_V1 is not set
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m
CONFIG_GPIO_IDIO_16=y
#
# Memory mapped GPIO drivers
#
CONFIG_GPIO_74XX_MMIO=m
CONFIG_GPIO_ALTERA=m
# CONFIG_GPIO_AMDPT is not set
CONFIG_GPIO_CADENCE=y
CONFIG_GPIO_DWAPB=m
# CONFIG_GPIO_EXAR is not set
CONFIG_GPIO_FTGPIO010=y
# CONFIG_GPIO_GENERIC_PLATFORM is not set
CONFIG_GPIO_GRGPIO=y
CONFIG_GPIO_HLWD=y
CONFIG_GPIO_LOGICVC=y
CONFIG_GPIO_MB86S7X=m
# CONFIG_GPIO_MENZ127 is not set
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SIOX is not set
# CONFIG_GPIO_SYSCON is not set
CONFIG_GPIO_VX855=m
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers
#
# Port-mapped I/O GPIO drivers
#
CONFIG_GPIO_I8255=y
CONFIG_GPIO_104_DIO_48E=y
# CONFIG_GPIO_104_IDIO_16 is not set
CONFIG_GPIO_104_IDI_48=y
# CONFIG_GPIO_F7188X is not set
# CONFIG_GPIO_GPIO_MM is not set
CONFIG_GPIO_IT87=m
# CONFIG_GPIO_SCH311X is not set
CONFIG_GPIO_WINBOND=m
# CONFIG_GPIO_WS16C48 is not set
# end of Port-mapped I/O GPIO drivers
#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=y
CONFIG_GPIO_GW_PLD=m
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_MAX732X_IRQ=y
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCA9570 is not set
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TPIC2810=y
# end of I2C GPIO expanders
#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=m
# CONFIG_GPIO_ARIZONA is not set
CONFIG_GPIO_CS5535=y
# CONFIG_GPIO_DA9052 is not set
CONFIG_GPIO_MADERA=y
# CONFIG_GPIO_PALMAS is not set
CONFIG_GPIO_RC5T583=y
CONFIG_GPIO_TPS65218=m
CONFIG_GPIO_TPS65910=y
# CONFIG_GPIO_TPS65912 is not set
CONFIG_GPIO_TQMX86=y
# CONFIG_GPIO_WM831X is not set
CONFIG_GPIO_WM8350=m
# CONFIG_GPIO_WM8994 is not set
# end of MFD GPIO expanders
#
# PCI GPIO expanders
#
# CONFIG_GPIO_AMD8111 is not set
CONFIG_GPIO_BT8XX=m
# CONFIG_GPIO_ML_IOH is not set
# CONFIG_GPIO_PCH is not set
CONFIG_GPIO_PCI_IDIO_16=y
CONFIG_GPIO_PCIE_IDIO_24=m
CONFIG_GPIO_RDC321X=y
# CONFIG_GPIO_SODAVILLE is not set
# end of PCI GPIO expanders
#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
CONFIG_GPIO_MAX3191X=y
CONFIG_GPIO_MAX7301=m
# CONFIG_GPIO_MC33880 is not set
CONFIG_GPIO_PISOSR=y
CONFIG_GPIO_XRA1403=m
CONFIG_GPIO_MOXTET=m
# end of SPI GPIO expanders
#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
# CONFIG_GPIO_LATCH is not set
CONFIG_GPIO_MOCKUP=y
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers
CONFIG_W1=y
CONFIG_W1_CON=y
#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2482=y
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters
#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
# CONFIG_W1_SLAVE_SMEM is not set
CONFIG_W1_SLAVE_DS2405=y
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
# CONFIG_W1_SLAVE_DS2406 is not set
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=y
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=y
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=y
CONFIG_W1_SLAVE_DS250X=y
CONFIG_W1_SLAVE_DS2780=y
CONFIG_W1_SLAVE_DS2781=y
CONFIG_W1_SLAVE_DS28E04=m
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_POWER_SUPPLY_HWMON is not set
CONFIG_PDA_POWER=m
# CONFIG_IP5XXX_POWER is not set
# CONFIG_MAX8925_POWER is not set
CONFIG_WM831X_BACKUP=y
# CONFIG_WM831X_POWER is not set
CONFIG_WM8350_POWER=m
# CONFIG_TEST_POWER is not set
CONFIG_CHARGER_ADP5061=m
CONFIG_BATTERY_CW2015=y
CONFIG_BATTERY_DS2760=m
CONFIG_BATTERY_DS2780=m
CONFIG_BATTERY_DS2781=m
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
CONFIG_BATTERY_SBS=y
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
CONFIG_BATTERY_DA9030=m
# CONFIG_BATTERY_DA9052 is not set
# CONFIG_BATTERY_DA9150 is not set
CONFIG_BATTERY_MAX17040=m
# CONFIG_BATTERY_MAX17042 is not set
CONFIG_BATTERY_MAX1721X=m
CONFIG_CHARGER_PCF50633=m
CONFIG_CHARGER_MAX8903=y
CONFIG_CHARGER_LP8727=y
# CONFIG_CHARGER_GPIO is not set
CONFIG_CHARGER_MANAGER=y
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=m
CONFIG_CHARGER_MAX14577=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77693 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
CONFIG_CHARGER_BQ24190=y
# CONFIG_CHARGER_BQ24257 is not set
CONFIG_CHARGER_BQ24735=m
# CONFIG_CHARGER_BQ2515X is not set
CONFIG_CHARGER_BQ25890=m
CONFIG_CHARGER_BQ25980=m
CONFIG_CHARGER_BQ256XX=m
# CONFIG_CHARGER_RK817 is not set
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65217=m
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_BATTERY_GOLDFISH=y
CONFIG_BATTERY_RT5033=m
CONFIG_CHARGER_RT9455=m
CONFIG_CHARGER_CROS_PCHG=m
CONFIG_CHARGER_UCS1002=y
CONFIG_CHARGER_BD99954=y
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
CONFIG_SENSORS_ABITUGURU=m
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7314 is not set
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=y
# CONFIG_SENSORS_ADM1025 is not set
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
CONFIG_SENSORS_ADM9240=y
CONFIG_SENSORS_ADT7X10=y
CONFIG_SENSORS_ADT7310=m
CONFIG_SENSORS_ADT7410=y
CONFIG_SENSORS_ADT7411=y
CONFIG_SENSORS_ADT7462=y
# CONFIG_SENSORS_ADT7470 is not set
CONFIG_SENSORS_ADT7475=m
CONFIG_SENSORS_AHT10=y
CONFIG_SENSORS_AS370=m
CONFIG_SENSORS_ASC7621=m
CONFIG_SENSORS_AXI_FAN_CONTROL=y
CONFIG_SENSORS_K8TEMP=m
# CONFIG_SENSORS_APPLESMC is not set
CONFIG_SENSORS_ASB100=y
CONFIG_SENSORS_ATXP1=y
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
# CONFIG_SENSORS_DS1621 is not set
CONFIG_SENSORS_DELL_SMM=m
# CONFIG_I8K is not set
CONFIG_SENSORS_DA9052_ADC=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71805F=y
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=y
# CONFIG_SENSORS_GSC is not set
CONFIG_SENSORS_MC13783_ADC=m
CONFIG_SENSORS_FSCHMD=y
# CONFIG_SENSORS_GL518SM is not set
CONFIG_SENSORS_GL520SM=m
# CONFIG_SENSORS_G760A is not set
CONFIG_SENSORS_G762=y
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
CONFIG_SENSORS_I5500=m
CONFIG_SENSORS_CORETEMP=m
CONFIG_SENSORS_IT87=y
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=y
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2947=y
CONFIG_SENSORS_LTC2947_I2C=y
CONFIG_SENSORS_LTC2947_SPI=m
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC2992=y
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=y
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=y
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
CONFIG_SENSORS_MAX127=y
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=y
# CONFIG_SENSORS_MAX1668 is not set
CONFIG_SENSORS_MAX197=y
CONFIG_SENSORS_MAX31722=y
CONFIG_SENSORS_MAX31730=y
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
CONFIG_SENSORS_MAX6639=y
# CONFIG_SENSORS_MAX6650 is not set
CONFIG_SENSORS_MAX6697=y
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=y
CONFIG_SENSORS_TC654=y
CONFIG_SENSORS_TPS23861=y
# CONFIG_SENSORS_MENF21BMC_HWMON is not set
# CONFIG_SENSORS_MR75203 is not set
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
# CONFIG_SENSORS_LM70 is not set
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
CONFIG_SENSORS_LM83=y
CONFIG_SENSORS_LM85=y
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=y
# CONFIG_SENSORS_LM92 is not set
CONFIG_SENSORS_LM93=y
CONFIG_SENSORS_LM95234=m
# CONFIG_SENSORS_LM95241 is not set
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
# CONFIG_SENSORS_PC87427 is not set
CONFIG_SENSORS_NCT6683=m
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
CONFIG_SENSORS_NCT7802=y
CONFIG_SENSORS_NPCM7XX=m
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_OXP is not set
# CONFIG_SENSORS_PCF8591 is not set
CONFIG_PMBUS=y
# CONFIG_SENSORS_PMBUS is not set
CONFIG_SENSORS_ADM1266=y
CONFIG_SENSORS_ADM1275=m
CONFIG_SENSORS_BEL_PFE=y
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
CONFIG_SENSORS_FSP_3Y=m
CONFIG_SENSORS_IBM_CFFPS=y
CONFIG_SENSORS_DPS920AB=m
# CONFIG_SENSORS_INSPUR_IPSPS is not set
CONFIG_SENSORS_IR35221=y
# CONFIG_SENSORS_IR36021 is not set
CONFIG_SENSORS_IR38064=y
# CONFIG_SENSORS_IR38064_REGULATOR is not set
CONFIG_SENSORS_IRPS5401=y
CONFIG_SENSORS_ISL68137=y
# CONFIG_SENSORS_LM25066 is not set
# CONFIG_SENSORS_LT7182S is not set
# CONFIG_SENSORS_LTC2978 is not set
CONFIG_SENSORS_LTC3815=m
CONFIG_SENSORS_MAX15301=y
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX16601 is not set
CONFIG_SENSORS_MAX20730=y
# CONFIG_SENSORS_MAX20751 is not set
CONFIG_SENSORS_MAX31785=m
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
CONFIG_SENSORS_MP2888=m
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_MP5023 is not set
CONFIG_SENSORS_PIM4328=m
# CONFIG_SENSORS_PLI1209BC is not set
# CONFIG_SENSORS_PM6764TR is not set
CONFIG_SENSORS_PXE1610=m
CONFIG_SENSORS_Q54SJ108A2=m
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS546D24 is not set
CONFIG_SENSORS_UCD9000=m
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_XDPE152 is not set
CONFIG_SENSORS_XDPE122=m
# CONFIG_SENSORS_XDPE122_REGULATOR is not set
CONFIG_SENSORS_ZL6100=y
CONFIG_SENSORS_PWM_FAN=y
# CONFIG_SENSORS_SBTSI is not set
CONFIG_SENSORS_SBRMI=m
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
# CONFIG_SENSORS_SHT3x is not set
CONFIG_SENSORS_SHT4x=m
# CONFIG_SENSORS_SHTC1 is not set
CONFIG_SENSORS_SIS5595=y
CONFIG_SENSORS_DME1737=m
CONFIG_SENSORS_EMC1403=m
CONFIG_SENSORS_EMC2103=y
# CONFIG_SENSORS_EMC2305 is not set
CONFIG_SENSORS_EMC6W201=y
CONFIG_SENSORS_SMSC47M1=y
CONFIG_SENSORS_SMSC47M192=y
CONFIG_SENSORS_SMSC47B397=y
# CONFIG_SENSORS_STTS751 is not set
CONFIG_SENSORS_SMM665=m
CONFIG_SENSORS_ADC128D818=y
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA209=y
CONFIG_SENSORS_INA2XX=m
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
CONFIG_SENSORS_THMC50=y
CONFIG_SENSORS_TMP102=m
CONFIG_SENSORS_TMP103=m
CONFIG_SENSORS_TMP108=y
CONFIG_SENSORS_TMP401=y
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
CONFIG_SENSORS_TMP513=m
# CONFIG_SENSORS_VIA_CPUTEMP is not set
CONFIG_SENSORS_VIA686A=m
CONFIG_SENSORS_VT1211=y
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
CONFIG_SENSORS_W83781D=y
CONFIG_SENSORS_W83791D=m
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
CONFIG_SENSORS_W83L785TS=y
CONFIG_SENSORS_W83L786NG=y
CONFIG_SENSORS_W83627HF=y
CONFIG_SENSORS_W83627EHF=y
CONFIG_SENSORS_WM831X=m
# CONFIG_SENSORS_WM8350 is not set
#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
# CONFIG_SENSORS_ASUS_WMI is not set
# CONFIG_SENSORS_ASUS_EC is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
# CONFIG_CPU_THERMAL is not set
# CONFIG_DEVFREQ_THERMAL is not set
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
# CONFIG_DA9062_THERMAL is not set
#
# Intel thermal drivers
#
# CONFIG_INTEL_POWERCLAMP is not set
CONFIG_X86_THERMAL_VECTOR=y
CONFIG_X86_PKG_TEMP_THERMAL=m
# CONFIG_INTEL_SOC_DTS_THERMAL is not set
#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers
# CONFIG_INTEL_PCH_THERMAL is not set
# CONFIG_INTEL_TCC_COOLING is not set
# CONFIG_INTEL_MENLOW is not set
# CONFIG_INTEL_HFI_THERMAL is not set
# end of Intel thermal drivers
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_PCIHOST_POSSIBLE=y
# CONFIG_SSB_PCIHOST is not set
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
# CONFIG_BCMA_HOST_PCI is not set
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set
#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_CS5535=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
CONFIG_PMIC_ADP5520=y
CONFIG_MFD_AAT2870_CORE=y
CONFIG_MFD_ATMEL_FLEXCOM=m
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
CONFIG_MFD_CROS_EC_DEV=m
CONFIG_MFD_MADERA=y
CONFIG_MFD_MADERA_I2C=y
CONFIG_MFD_MADERA_SPI=m
# CONFIG_MFD_CS47L15 is not set
CONFIG_MFD_CS47L35=y
# CONFIG_MFD_CS47L85 is not set
# CONFIG_MFD_CS47L90 is not set
# CONFIG_MFD_CS47L92 is not set
CONFIG_PMIC_DA903X=y
CONFIG_PMIC_DA9052=y
# CONFIG_MFD_DA9052_SPI is not set
CONFIG_MFD_DA9052_I2C=y
# CONFIG_MFD_DA9055 is not set
CONFIG_MFD_DA9062=m
CONFIG_MFD_DA9063=y
CONFIG_MFD_DA9150=y
CONFIG_MFD_GATEWORKS_GSC=m
CONFIG_MFD_MC13XXX=m
CONFIG_MFD_MC13XXX_SPI=m
# CONFIG_MFD_MC13XXX_I2C is not set
CONFIG_MFD_MP2629=m
# CONFIG_MFD_HI6421_PMIC is not set
CONFIG_MFD_HI6421_SPMI=m
CONFIG_HTC_PASIC3=y
CONFIG_MFD_INTEL_QUARK_I2C_GPIO=y
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_INTEL_SOC_PMIC_MRFLD is not set
CONFIG_MFD_INTEL_LPSS=m
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
CONFIG_MFD_INTEL_LPSS_PCI=m
# CONFIG_MFD_INTEL_PMC_BXT is not set
CONFIG_MFD_IQS62X=y
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
CONFIG_MFD_88PM805=y
# CONFIG_MFD_88PM860X is not set
CONFIG_MFD_MAX14577=m
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
CONFIG_MFD_MAX77693=m
# CONFIG_MFD_MAX77714 is not set
CONFIG_MFD_MAX77843=y
CONFIG_MFD_MAX8907=m
CONFIG_MFD_MAX8925=y
CONFIG_MFD_MAX8997=y
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
CONFIG_MFD_MT6397=m
CONFIG_MFD_MENF21BMC=m
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
CONFIG_MFD_CPCAP=y
CONFIG_MFD_NTXEC=y
CONFIG_MFD_RETU=m
CONFIG_MFD_PCF50633=m
# CONFIG_PCF50633_ADC is not set
CONFIG_PCF50633_GPIO=m
# CONFIG_MFD_SY7636A is not set
CONFIG_MFD_RDC321X=y
CONFIG_MFD_RT4831=m
CONFIG_MFD_RT5033=m
# CONFIG_MFD_RT5120 is not set
CONFIG_MFD_RC5T583=y
CONFIG_MFD_RK808=y
CONFIG_MFD_RN5T618=y
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SI476X_CORE=y
CONFIG_MFD_SM501=y
# CONFIG_MFD_SM501_GPIO is not set
CONFIG_MFD_SKY81452=m
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=y
# CONFIG_MFD_LP3943 is not set
CONFIG_MFD_LP8788=y
# CONFIG_MFD_TI_LMU is not set
CONFIG_MFD_PALMAS=y
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
CONFIG_TPS6507X=y
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
CONFIG_MFD_TPS65217=m
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
CONFIG_MFD_TPS65218=m
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TPS65912=y
CONFIG_MFD_TPS65912_I2C=m
CONFIG_MFD_TPS65912_SPI=y
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
CONFIG_MFD_LM3533=m
# CONFIG_MFD_TIMBERDALE is not set
# CONFIG_MFD_TC3589X is not set
CONFIG_MFD_TQMX86=y
CONFIG_MFD_VX855=m
# CONFIG_MFD_LOCHNAGAR is not set
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=m
CONFIG_MFD_ARIZONA_SPI=y
# CONFIG_MFD_CS47L24 is not set
CONFIG_MFD_WM5102=y
# CONFIG_MFD_WM5110 is not set
CONFIG_MFD_WM8997=y
CONFIG_MFD_WM8998=y
CONFIG_MFD_WM8400=y
CONFIG_MFD_WM831X=y
CONFIG_MFD_WM831X_I2C=y
# CONFIG_MFD_WM831X_SPI is not set
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=m
CONFIG_MFD_ROHM_BD718XX=m
# CONFIG_MFD_ROHM_BD71828 is not set
CONFIG_MFD_ROHM_BD957XMUF=m
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
CONFIG_MFD_RSMU_SPI=m
# end of Multifunction device drivers
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
CONFIG_REGULATOR_88PG86X=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_REGULATOR_AD5398=m
# CONFIG_REGULATOR_AAT2870 is not set
# CONFIG_REGULATOR_BD718XX is not set
# CONFIG_REGULATOR_BD957XMUF is not set
# CONFIG_REGULATOR_CPCAP is not set
# CONFIG_REGULATOR_CROS_EC is not set
# CONFIG_REGULATOR_DA9052 is not set
# CONFIG_REGULATOR_DA9062 is not set
CONFIG_REGULATOR_DA9063=m
# CONFIG_REGULATOR_DA9121 is not set
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_DA9211=m
CONFIG_REGULATOR_FAN53555=m
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_HI6421V600=m
CONFIG_REGULATOR_ISL9305=y
CONFIG_REGULATOR_ISL6271A=m
CONFIG_REGULATOR_LP3971=y
# CONFIG_REGULATOR_LP3972 is not set
CONFIG_REGULATOR_LP872X=y
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LP8788=m
# CONFIG_REGULATOR_LTC3589 is not set
CONFIG_REGULATOR_LTC3676=y
CONFIG_REGULATOR_MAX14577=m
CONFIG_REGULATOR_MAX1586=y
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
CONFIG_REGULATOR_MAX8893=y
CONFIG_REGULATOR_MAX8907=m
# CONFIG_REGULATOR_MAX8925 is not set
CONFIG_REGULATOR_MAX8952=y
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX8997 is not set
# CONFIG_REGULATOR_MAX20086 is not set
CONFIG_REGULATOR_MAX77693=y
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MC13XXX_CORE=m
CONFIG_REGULATOR_MC13783=m
# CONFIG_REGULATOR_MC13892 is not set
CONFIG_REGULATOR_MCP16502=y
CONFIG_REGULATOR_MP5416=y
CONFIG_REGULATOR_MP8859=y
CONFIG_REGULATOR_MP886X=y
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
CONFIG_REGULATOR_MT6315=m
# CONFIG_REGULATOR_MT6323 is not set
# CONFIG_REGULATOR_MT6331 is not set
# CONFIG_REGULATOR_MT6332 is not set
# CONFIG_REGULATOR_MT6357 is not set
# CONFIG_REGULATOR_MT6358 is not set
# CONFIG_REGULATOR_MT6359 is not set
# CONFIG_REGULATOR_MT6397 is not set
CONFIG_REGULATOR_PALMAS=m
CONFIG_REGULATOR_PCA9450=y
CONFIG_REGULATOR_PCF50633=m
# CONFIG_REGULATOR_PF8X00 is not set
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_REGULATOR_PV88060 is not set
CONFIG_REGULATOR_PV88080=m
CONFIG_REGULATOR_PV88090=m
CONFIG_REGULATOR_PWM=m
CONFIG_REGULATOR_QCOM_SPMI=m
CONFIG_REGULATOR_QCOM_USB_VBUS=m
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y
# CONFIG_REGULATOR_RC5T583 is not set
# CONFIG_REGULATOR_RK808 is not set
CONFIG_REGULATOR_RN5T618=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4831 is not set
CONFIG_REGULATOR_RT5033=m
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5759 is not set
CONFIG_REGULATOR_RT6160=m
# CONFIG_REGULATOR_RT6190 is not set
CONFIG_REGULATOR_RT6245=y
CONFIG_REGULATOR_RTQ2134=m
CONFIG_REGULATOR_RTMV20=y
CONFIG_REGULATOR_RTQ6752=y
CONFIG_REGULATOR_S2MPA01=m
# CONFIG_REGULATOR_S2MPS11 is not set
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_SKY81452=m
# CONFIG_REGULATOR_SLG51000 is not set
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=y
# CONFIG_REGULATOR_SY8827N is not set
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS62360=m
# CONFIG_REGULATOR_TPS6286X is not set
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65132=y
# CONFIG_REGULATOR_TPS65217 is not set
CONFIG_REGULATOR_TPS65218=m
CONFIG_REGULATOR_TPS6524X=y
CONFIG_REGULATOR_TPS65910=m
CONFIG_REGULATOR_TPS65912=m
CONFIG_REGULATOR_VCTRL=m
CONFIG_REGULATOR_WM831X=m
CONFIG_REGULATOR_WM8350=y
# CONFIG_REGULATOR_WM8400 is not set
CONFIG_REGULATOR_WM8994=m
CONFIG_REGULATOR_QCOM_LABIBB=m
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
#
# CEC support
#
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_CROS_EC=m
# CONFIG_CEC_SECO is not set
# CONFIG_USB_PULSE8_CEC is not set
# CONFIG_USB_RAINSHADOW_CEC is not set
# end of CEC support
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_RADIO_SUPPORT=y
# CONFIG_MEDIA_SDR_SUPPORT is not set
# CONFIG_MEDIA_PLATFORM_SUPPORT is not set
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types
CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
# end of Video4Linux options
#
# Media controller options
#
# end of Media controller options
#
# Media drivers
#
#
# Drivers filtered as selected at 'Filter media drivers'
#
#
# Media drivers
#
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_RADIO_ADAPTERS=y
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SAA7706H=m
# CONFIG_RADIO_SI4713 is not set
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_TEA5764=y
# CONFIG_RADIO_TEA5764_XTAL is not set
# CONFIG_RADIO_TEF6862 is not set
CONFIG_RADIO_WL1273=m
CONFIG_RADIO_SI470X=m
CONFIG_I2C_SI470X=m
# CONFIG_V4L_RADIO_ISA_DRIVERS is not set
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_VMALLOC=y
# end of Media drivers
#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y
#
# Camera sensor devices
#
# CONFIG_VIDEO_AR0521 is not set
CONFIG_VIDEO_HI556=y
CONFIG_VIDEO_HI846=y
# CONFIG_VIDEO_HI847 is not set
CONFIG_VIDEO_IMX208=y
# CONFIG_VIDEO_IMX214 is not set
# CONFIG_VIDEO_IMX219 is not set
CONFIG_VIDEO_IMX258=y
CONFIG_VIDEO_IMX274=m
# CONFIG_VIDEO_IMX290 is not set
CONFIG_VIDEO_IMX319=y
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=y
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX412=y
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=y
# CONFIG_VIDEO_MT9M032 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
# CONFIG_VIDEO_MT9V011 is not set
CONFIG_VIDEO_MT9V032=m
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_NOON010PC30 is not set
# CONFIG_VIDEO_OG01A1B is not set
CONFIG_VIDEO_OV02A10=m
# CONFIG_VIDEO_OV08D10 is not set
# CONFIG_VIDEO_OV08X40 is not set
# CONFIG_VIDEO_OV13858 is not set
CONFIG_VIDEO_OV13B10=y
# CONFIG_VIDEO_OV2640 is not set
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=y
# CONFIG_VIDEO_OV2685 is not set
CONFIG_VIDEO_OV2740=m
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=y
CONFIG_VIDEO_OV5647=m
# CONFIG_VIDEO_OV5648 is not set
CONFIG_VIDEO_OV5670=y
CONFIG_VIDEO_OV5675=y
# CONFIG_VIDEO_OV5693 is not set
# CONFIG_VIDEO_OV5695 is not set
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=y
CONFIG_VIDEO_OV7640=m
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV772X is not set
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
CONFIG_VIDEO_OV9640=m
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV9734 is not set
CONFIG_VIDEO_RDACM20=m
# CONFIG_VIDEO_RDACM21 is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# CONFIG_VIDEO_S5K5BAF is not set
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K6AA=y
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_VIDEO_ST_VGXY61 is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set
# CONFIG_VIDEO_M5MOLS is not set
# end of Camera sensor devices
#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
# CONFIG_VIDEO_AK7375 is not set
CONFIG_VIDEO_DW9714=y
# CONFIG_VIDEO_DW9768 is not set
CONFIG_VIDEO_DW9807_VCM=y
# end of Lens drivers
#
# Flash devices
#
CONFIG_VIDEO_ADP1653=y
CONFIG_VIDEO_LM3560=y
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices
#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_CS3308 is not set
CONFIG_VIDEO_CS5345=m
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_MSP3400 is not set
CONFIG_VIDEO_SONY_BTF_MPX=y
CONFIG_VIDEO_TDA7432=m
# CONFIG_VIDEO_TDA9840 is not set
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=y
# CONFIG_VIDEO_TVAUDIO is not set
CONFIG_VIDEO_UDA1342=y
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=y
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers
#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders
#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
CONFIG_VIDEO_ADV7183=y
CONFIG_VIDEO_ADV748X=y
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
# CONFIG_VIDEO_BT819 is not set
CONFIG_VIDEO_BT856=y
CONFIG_VIDEO_BT866=m
# CONFIG_VIDEO_ISL7998X is not set
CONFIG_VIDEO_KS0127=y
CONFIG_VIDEO_MAX9286=y
CONFIG_VIDEO_ML86V7667=y
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TC358746 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
CONFIG_VIDEO_TVP7002=m
# CONFIG_VIDEO_TW2804 is not set
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=y
# CONFIG_VIDEO_TW9910 is not set
CONFIG_VIDEO_VPX3220=m
#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=y
# CONFIG_VIDEO_CX25840 is not set
# end of Video decoders
#
# Video encoders
#
CONFIG_VIDEO_AD9389B=y
CONFIG_VIDEO_ADV7170=m
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
CONFIG_VIDEO_ADV7393=m
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
CONFIG_VIDEO_THS8200=y
# end of Video encoders
#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips
#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips
#
# SDR tuner chips
#
# end of SDR tuner chips
#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=y
CONFIG_VIDEO_M52790=y
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips
#
# Media SPI Adapters
#
# CONFIG_VIDEO_GS1662 is not set
# end of Media SPI Adapters
CONFIG_MEDIA_TUNER=y
#
# Customize TV tuners
#
# CONFIG_MEDIA_TUNER_E4000 is not set
CONFIG_MEDIA_TUNER_FC0011=y
# CONFIG_MEDIA_TUNER_FC0012 is not set
CONFIG_MEDIA_TUNER_FC0013=y
CONFIG_MEDIA_TUNER_FC2580=m
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
CONFIG_MEDIA_TUNER_MAX2165=y
CONFIG_MEDIA_TUNER_MC44S803=y
# CONFIG_MEDIA_TUNER_MSI001 is not set
CONFIG_MEDIA_TUNER_MT2060=m
# CONFIG_MEDIA_TUNER_MT2063 is not set
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MXL301RF=y
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
CONFIG_MEDIA_TUNER_QM1D1B0004=m
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_TDA18218=m
# CONFIG_MEDIA_TUNER_TDA18250 is not set
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
# CONFIG_MEDIA_TUNER_TUA9001 is not set
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_XC5000=y
# end of Customize TV tuners
# end of Media ancillary drivers
#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_VIDEO_NOMODESET=y
CONFIG_AGP=y
CONFIG_AGP_ALI=y
# CONFIG_AGP_ATI is not set
# CONFIG_AGP_AMD is not set
# CONFIG_AGP_INTEL is not set
CONFIG_AGP_NVIDIA=m
CONFIG_AGP_SIS=m
CONFIG_AGP_SWORKS=m
CONFIG_AGP_VIA=m
CONFIG_AGP_EFFICEON=m
CONFIG_INTEL_GTT=y
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM=y
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_DP_AUX_BUS=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DP_AUX_CHARDEV=y
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_TTM=y
CONFIG_DRM_BUDDY=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=y
#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=y
CONFIG_DRM_I2C_SIL164=y
CONFIG_DRM_I2C_NXP_TDA998X=y
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips
#
# ARM devices
#
CONFIG_DRM_KOMEDA=m
# end of ARM devices
# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_FORCE_PROBE=""
# CONFIG_DRM_I915_CAPTURE_ERROR is not set
# CONFIG_DRM_I915_USERPTR is not set
#
# drm/i915 Debugging
#
# CONFIG_DRM_I915_WERROR is not set
# CONFIG_DRM_I915_DEBUG is not set
CONFIG_DRM_I915_DEBUG_MMIO=y
CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS=y
CONFIG_DRM_I915_SW_FENCE_CHECK_DAG=y
# CONFIG_DRM_I915_DEBUG_GUC is not set
# CONFIG_DRM_I915_SELFTEST is not set
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
CONFIG_DRM_I915_DEBUG_VBLANK_EVADE=y
CONFIG_DRM_I915_DEBUG_RUNTIME_PM=y
# end of drm/i915 Debugging
#
# drm/i915 Profile Guided Optimisation
#
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_STOP_TIMEOUT=100
CONFIG_DRM_I915_TIMESLICE_DURATION=1
# end of drm/i915 Profile Guided Optimisation
CONFIG_DRM_VGEM=m
CONFIG_DRM_VKMS=y
CONFIG_DRM_VMWGFX=m
# CONFIG_DRM_VMWGFX_MKSSTATS is not set
CONFIG_DRM_GMA500=m
CONFIG_DRM_AST=y
CONFIG_DRM_MGAG200=m
CONFIG_DRM_RCAR_DW_HDMI=m
# CONFIG_DRM_RCAR_USE_LVDS is not set
# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
CONFIG_DRM_QXL=m
CONFIG_DRM_PANEL=y
#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=y
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y
CONFIG_DRM_PANEL_DSI_CM=y
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_EDP is not set
# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
CONFIG_DRM_PANEL_ILITEK_ILI9341=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
CONFIG_DRM_PANEL_JDI_LT070ME05000=y
# CONFIG_DRM_PANEL_JDI_R63452 is not set
CONFIG_DRM_PANEL_KHADAS_TS050=y
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=y
CONFIG_DRM_PANEL_LG_LG4573=y
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
CONFIG_DRM_PANEL_NOVATEK_NT36672A=y
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=y
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=y
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=y
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=y
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
CONFIG_DRM_PANEL_TDO_TL070WSH30=y
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
CONFIG_DRM_PANEL_TPO_TD043MTEA1=y
CONFIG_DRM_PANEL_TPO_TPG110=y
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y
CONFIG_DRM_PANEL_VISIONOX_RM69299=y
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
CONFIG_DRM_CHIPONE_ICN6211=m
CONFIG_DRM_CHRONTEL_CH7033=y
CONFIG_DRM_CROS_EC_ANX7688=m
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
CONFIG_DRM_ITE_IT66121=m
CONFIG_DRM_LVDS_CODEC=y
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_NWL_MIPI_DSI=y
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
CONFIG_DRM_PARADE_PS8640=y
CONFIG_DRM_SIL_SII8620=y
CONFIG_DRM_SII902X=m
CONFIG_DRM_SII9234=y
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
CONFIG_DRM_TOSHIBA_TC358764=m
CONFIG_DRM_TOSHIBA_TC358767=m
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
CONFIG_DRM_TI_SN65DSI83=m
CONFIG_DRM_TI_SN65DSI86=y
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_CEC=y
CONFIG_DRM_CDNS_MHDP8546=m
CONFIG_DRM_DW_HDMI=m
# CONFIG_DRM_DW_HDMI_CEC is not set
# end of Display Interface Bridges
CONFIG_DRM_ETNAVIV=y
# CONFIG_DRM_ETNAVIV_THERMAL is not set
# CONFIG_DRM_LOGICVC is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_IMX_LCDIF is not set
CONFIG_DRM_ARCPGU=y
CONFIG_DRM_BOCHS=m
CONFIG_DRM_CIRRUS_QEMU=m
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
CONFIG_TINYDRM_ILI9486=y
CONFIG_TINYDRM_MI0283QT=m
# CONFIG_TINYDRM_REPAPER is not set
CONFIG_TINYDRM_ST7586=m
CONFIG_TINYDRM_ST7735R=y
CONFIG_DRM_VBOXVIDEO=y
# CONFIG_DRM_SSD130X is not set
CONFIG_DRM_LEGACY=y
CONFIG_DRM_TDFX=y
CONFIG_DRM_R128=y
# CONFIG_DRM_MGA is not set
# CONFIG_DRM_SIS is not set
# CONFIG_DRM_VIA is not set
CONFIG_DRM_SAVAGE=m
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DDC=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_SVGALIB=y
CONFIG_FB_BACKLIGHT=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_CYBER2000=y
CONFIG_FB_CYBER2000_DDC=y
# CONFIG_FB_ARC is not set
CONFIG_FB_ASILIANT=y
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_VESA=y
# CONFIG_FB_N411 is not set
CONFIG_FB_HGA=y
CONFIG_FB_OPENCORES=y
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_NVIDIA=m
# CONFIG_FB_NVIDIA_I2C is not set
# CONFIG_FB_NVIDIA_DEBUG is not set
CONFIG_FB_NVIDIA_BACKLIGHT=y
# CONFIG_FB_RIVA is not set
CONFIG_FB_I740=m
# CONFIG_FB_LE80578 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
CONFIG_FB_ATY128=m
CONFIG_FB_ATY128_BACKLIGHT=y
CONFIG_FB_ATY=y
CONFIG_FB_ATY_CT=y
# CONFIG_FB_ATY_GENERIC_LCD is not set
# CONFIG_FB_ATY_GX is not set
CONFIG_FB_ATY_BACKLIGHT=y
CONFIG_FB_S3=y
CONFIG_FB_S3_DDC=y
CONFIG_FB_SAVAGE=m
CONFIG_FB_SAVAGE_I2C=y
CONFIG_FB_SAVAGE_ACCEL=y
CONFIG_FB_SIS=m
# CONFIG_FB_SIS_300 is not set
CONFIG_FB_SIS_315=y
# CONFIG_FB_VIA is not set
CONFIG_FB_NEOMAGIC=y
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
CONFIG_FB_VOODOO1=y
CONFIG_FB_VT8623=y
CONFIG_FB_TRIDENT=y
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
CONFIG_FB_CARMINE=m
CONFIG_FB_CARMINE_DRAM_EVAL=y
# CONFIG_CARMINE_DRAM_CUSTOM is not set
# CONFIG_FB_GEODE is not set
# CONFIG_FB_SM501 is not set
CONFIG_FB_IBM_GXT4500=m
CONFIG_FB_GOLDFISH=y
# CONFIG_FB_VIRTUAL is not set
CONFIG_FB_METRONOME=y
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
CONFIG_FB_SM712=y
# end of Frame buffer Devices
#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=y
# CONFIG_LCD_L4F00242T03 is not set
CONFIG_LCD_LMS283GF05=y
CONFIG_LCD_LTV350QV=y
CONFIG_LCD_ILI922X=y
CONFIG_LCD_ILI9320=y
CONFIG_LCD_TDO24M=m
# CONFIG_LCD_VGG2432A4 is not set
CONFIG_LCD_PLATFORM=m
CONFIG_LCD_AMS369FG06=m
CONFIG_LCD_LMS501KF03=y
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_LM3533 is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_DA903X is not set
CONFIG_BACKLIGHT_DA9052=y
CONFIG_BACKLIGHT_MAX8925=m
# CONFIG_BACKLIGHT_APPLE is not set
CONFIG_BACKLIGHT_QCOM_WLED=m
CONFIG_BACKLIGHT_RT4831=m
CONFIG_BACKLIGHT_SAHARA=y
# CONFIG_BACKLIGHT_WM831X is not set
# CONFIG_BACKLIGHT_ADP5520 is not set
CONFIG_BACKLIGHT_ADP8860=y
# CONFIG_BACKLIGHT_ADP8870 is not set
CONFIG_BACKLIGHT_PCF50633=m
CONFIG_BACKLIGHT_AAT2870=y
CONFIG_BACKLIGHT_LM3630A=m
CONFIG_BACKLIGHT_LM3639=y
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_LP8788=y
# CONFIG_BACKLIGHT_SKY81452 is not set
CONFIG_BACKLIGHT_TPS65217=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=y
# CONFIG_BACKLIGHT_ARCXCNN is not set
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support
CONFIG_VGASTATE=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# end of Graphics support
# CONFIG_DRM_ACCEL is not set
CONFIG_SOUND=y
# CONFIG_SND is not set
#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_VRC2 is not set
# CONFIG_HID_XIAOMI is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NINTENDO is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PLAYSTATION is not set
# CONFIG_HID_PXRC is not set
# CONFIG_HID_RAZER is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SEMITEK is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TOPRE is not set
# CONFIG_HID_THINGM is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
# end of Special HID drivers
#
# I2C HID support
#
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_ELAN is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
# end of I2C HID support
# end of HID support
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB is not set
CONFIG_USB_PCI=y
#
# USB dual-mode controller drivers
#
#
# USB port drivers
#
#
# USB Physical Layer drivers
#
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_TAHVO_USB is not set
# end of USB Physical Layer drivers
# CONFIG_USB_GADGET is not set
# CONFIG_TYPEC is not set
# CONFIG_USB_ROLE_SWITCH is not set
# CONFIG_MMC is not set
CONFIG_SCSI_UFSHCD=m
# CONFIG_SCSI_UFS_BSG is not set
# CONFIG_SCSI_UFS_CRYPTO is not set
# CONFIG_SCSI_UFS_HPB is not set
# CONFIG_SCSI_UFS_FAULT_INJECTION is not set
# CONFIG_SCSI_UFS_HWMON is not set
CONFIG_SCSI_UFSHCD_PCI=m
CONFIG_SCSI_UFS_DWC_TC_PCI=m
CONFIG_SCSI_UFSHCD_PLATFORM=m
CONFIG_SCSI_UFS_CDNS_PLATFORM=m
CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
CONFIG_MEMSTICK=m
CONFIG_MEMSTICK_DEBUG=y
#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
CONFIG_MSPRO_BLOCK=m
CONFIG_MS_BLOCK=m
#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=m
# CONFIG_MEMSTICK_JMICRON_38X is not set
CONFIG_MEMSTICK_R592=m
# CONFIG_MEMSTICK_REALTEK_PCI is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
CONFIG_LEDS_APU=y
CONFIG_LEDS_AW2013=y
CONFIG_LEDS_BCM6328=m
# CONFIG_LEDS_BCM6358 is not set
CONFIG_LEDS_CPCAP=y
# CONFIG_LEDS_CR0014114 is not set
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=y
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3533=m
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_MT6323 is not set
CONFIG_LEDS_NET48XX=m
CONFIG_LEDS_WRAP=m
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=y
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=y
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
# CONFIG_LEDS_LP8501 is not set
CONFIG_LEDS_LP8788=y
CONFIG_LEDS_LP8860=y
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=y
CONFIG_LEDS_WM831X_STATUS=y
CONFIG_LEDS_WM8350=m
CONFIG_LEDS_DA903X=m
CONFIG_LEDS_DA9052=y
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
# CONFIG_LEDS_BD2802 is not set
CONFIG_LEDS_INTEL_SS4200=y
CONFIG_LEDS_LT3593=y
CONFIG_LEDS_ADP5520=m
# CONFIG_LEDS_MC13783 is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_MAX8997 is not set
CONFIG_LEDS_LM355x=y
# CONFIG_LEDS_OT200 is not set
CONFIG_LEDS_MENF21BMC=m
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
# CONFIG_LEDS_SYSCON is not set
CONFIG_LEDS_MLXCPLD=y
CONFIG_LEDS_MLXREG=m
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_NIC78BX is not set
# CONFIG_LEDS_SPI_BYTE is not set
CONFIG_LEDS_TI_LMU_COMMON=y
CONFIG_LEDS_LM3697=y
CONFIG_LEDS_LGM=m
#
# Flash and Torch LED drivers
#
#
# RGB LED drivers
#
# CONFIG_LEDS_PWM_MULTICOLOR is not set
# CONFIG_LEDS_QCOM_LPG is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_GPIO is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=m
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_LEDS_TRIGGER_PANIC is not set
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=y
# CONFIG_LEDS_TRIGGER_TTY is not set
#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
#
# Speakup console speech
#
# end of Speakup console speech
CONFIG_INFINIBAND=m
CONFIG_INFINIBAND_USER_MAD=m
# CONFIG_INFINIBAND_USER_ACCESS is not set
CONFIG_INFINIBAND_ADDR_TRANS=y
CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
CONFIG_INFINIBAND_IRDMA=m
CONFIG_MLX4_INFINIBAND=m
# CONFIG_INFINIBAND_MTHCA is not set
CONFIG_INFINIBAND_OCRDMA=m
CONFIG_INFINIBAND_VMWARE_PVRDMA=m
# CONFIG_INFINIBAND_IPOIB is not set
# CONFIG_INFINIBAND_SRP is not set
# CONFIG_INFINIBAND_ISER is not set
CONFIG_INFINIBAND_RTRS=m
CONFIG_INFINIBAND_RTRS_CLIENT=m
CONFIG_INFINIBAND_RTRS_SERVER=m
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
# CONFIG_EDAC_LEGACY_SYSFS is not set
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_AMD76X is not set
CONFIG_EDAC_E7XXX=y
CONFIG_EDAC_E752X=m
CONFIG_EDAC_I82875P=y
CONFIG_EDAC_I82975X=y
CONFIG_EDAC_I3000=m
# CONFIG_EDAC_I3200 is not set
CONFIG_EDAC_IE31200=m
CONFIG_EDAC_X38=m
# CONFIG_EDAC_I5400 is not set
CONFIG_EDAC_I82860=y
# CONFIG_EDAC_R82600 is not set
CONFIG_EDAC_I5100=y
CONFIG_EDAC_I7300=m
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
CONFIG_RTC_DEBUG=y
# CONFIG_RTC_NVMEM is not set
#
# RTC interfaces
#
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_PROC is not set
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=y
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=y
# CONFIG_RTC_DRV_DS1307_CENTURY is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_LP8788=y
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_MAX8907 is not set
CONFIG_RTC_DRV_MAX8925=m
CONFIG_RTC_DRV_MAX8997=y
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RS5C372 is not set
CONFIG_RTC_DRV_ISL1208=y
# CONFIG_RTC_DRV_ISL12022 is not set
CONFIG_RTC_DRV_ISL12026=y
# CONFIG_RTC_DRV_X1205 is not set
CONFIG_RTC_DRV_PCF8523=m
# CONFIG_RTC_DRV_PCF85063 is not set
CONFIG_RTC_DRV_PCF85363=m
# CONFIG_RTC_DRV_PCF8563 is not set
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=y
# CONFIG_RTC_DRV_M41T80_WDT is not set
# CONFIG_RTC_DRV_BQ32K is not set
CONFIG_RTC_DRV_PALMAS=m
CONFIG_RTC_DRV_TPS65910=y
CONFIG_RTC_DRV_RC5T583=m
# CONFIG_RTC_DRV_RC5T619 is not set
# CONFIG_RTC_DRV_S35390A is not set
CONFIG_RTC_DRV_FM3130=m
# CONFIG_RTC_DRV_RX8010 is not set
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV3028 is not set
CONFIG_RTC_DRV_RV3032=m
# CONFIG_RTC_DRV_RV8803 is not set
CONFIG_RTC_DRV_S5M=m
CONFIG_RTC_DRV_SD3078=y
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
CONFIG_RTC_DRV_M41T94=m
CONFIG_RTC_DRV_DS1302=m
CONFIG_RTC_DRV_DS1305=y
# CONFIG_RTC_DRV_DS1343 is not set
CONFIG_RTC_DRV_DS1347=m
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
CONFIG_RTC_DRV_RX4581=m
CONFIG_RTC_DRV_RS5C348=y
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
CONFIG_RTC_DRV_MCP795=y
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=y
# CONFIG_RTC_DRV_RV3029_HWMON is not set
CONFIG_RTC_DRV_RX6110=m
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=m
CONFIG_RTC_DRV_DS1286=y
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=y
CONFIG_RTC_DRV_DS1685_FAMILY=m
# CONFIG_RTC_DRV_DS1685 is not set
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
CONFIG_RTC_DRV_DS17485=y
# CONFIG_RTC_DRV_DS17885 is not set
# CONFIG_RTC_DRV_DS1742 is not set
CONFIG_RTC_DRV_DS2404=m
# CONFIG_RTC_DRV_DA9052 is not set
CONFIG_RTC_DRV_DA9063=y
CONFIG_RTC_DRV_STK17TA8=y
CONFIG_RTC_DRV_M48T86=y
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
# CONFIG_RTC_DRV_MSM6242 is not set
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_WM831X is not set
# CONFIG_RTC_DRV_WM8350 is not set
CONFIG_RTC_DRV_PCF50633=m
CONFIG_RTC_DRV_ZYNQMP=y
CONFIG_RTC_DRV_CROS_EC=m
CONFIG_RTC_DRV_NTXEC=y
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_CADENCE=m
# CONFIG_RTC_DRV_FTRTC010 is not set
CONFIG_RTC_DRV_MC13XXX=m
# CONFIG_RTC_DRV_MT6397 is not set
# CONFIG_RTC_DRV_R7301 is not set
# CONFIG_RTC_DRV_CPCAP is not set
#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_GOLDFISH=y
# CONFIG_DMADEVICES is not set
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
CONFIG_UDMABUF=y
CONFIG_DMABUF_MOVE_NOTIFY=y
CONFIG_DMABUF_DEBUG=y
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# end of DMABUF options
CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_KS0108=m
CONFIG_KS0108_PORT=0x378
CONFIG_KS0108_DELAY=2
CONFIG_CFAG12864B=m
CONFIG_CFAG12864B_RATE=20
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_HT16K33 is not set
CONFIG_LCD2S=y
CONFIG_PARPORT_PANEL=m
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
CONFIG_PANEL_CHANGE_MESSAGE=y
CONFIG_PANEL_BOOT_MESSAGE=""
# CONFIG_CHARLCD_BL_OFF is not set
CONFIG_CHARLCD_BL_ON=y
# CONFIG_CHARLCD_BL_FLASH is not set
CONFIG_PANEL=m
CONFIG_UIO=y
CONFIG_UIO_CIF=y
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_UIO_AEC=y
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
CONFIG_UIO_NETX=y
# CONFIG_UIO_PRUSS is not set
CONFIG_UIO_MF624=y
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=y
CONFIG_VHOST_RING=y
# CONFIG_VHOST_MENU is not set
#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support
CONFIG_GREYBUS=m
# CONFIG_COMEDI is not set
# CONFIG_STAGING is not set
# CONFIG_GOLDFISH_PIPE is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CHROMEOS_ACPI is not set
CONFIG_CHROMEOS_LAPTOP=m
# CONFIG_CHROMEOS_PSTORE is not set
# CONFIG_CHROMEOS_TBMC is not set
CONFIG_CROS_EC=m
CONFIG_CROS_EC_I2C=m
CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=m
# CONFIG_CROS_EC_LPC is not set
CONFIG_CROS_EC_PROTO=y
# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
# CONFIG_CROS_EC_CHARDEV is not set
CONFIG_CROS_EC_LIGHTBAR=m
# CONFIG_CROS_EC_VBC is not set
CONFIG_CROS_EC_DEBUGFS=m
CONFIG_CROS_EC_SENSORHUB=m
CONFIG_CROS_EC_SYSFS=m
# CONFIG_CROS_HPS_I2C is not set
# CONFIG_CROS_USBPD_NOTIFY is not set
# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE3_WMI is not set
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_X86_PLATFORM_DEVICES=y
CONFIG_ACPI_WMI=y
CONFIG_WMI_BMOF=y
# CONFIG_HUAWEI_WMI is not set
# CONFIG_MXM_WMI is not set
# CONFIG_PEAQ_WMI is not set
# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
# CONFIG_XIAOMI_WMI is not set
# CONFIG_GIGABYTE_WMI is not set
# CONFIG_YOGABOOK_WMI is not set
# CONFIG_ACERHDF is not set
# CONFIG_ACER_WIRELESS is not set
# CONFIG_ACER_WMI is not set
# CONFIG_AMD_PMF is not set
# CONFIG_AMD_PMC is not set
# CONFIG_ADV_SWBUTTON is not set
# CONFIG_APPLE_GMUX is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_ASUS_WIRELESS is not set
# CONFIG_ASUS_TF103C_DOCK is not set
# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
CONFIG_AMILO_RFKILL=m
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set
# CONFIG_GPD_POCKET_FAN is not set
# CONFIG_X86_PLATFORM_DRIVERS_HP is not set
# CONFIG_WIRELESS_HOTKEY is not set
CONFIG_IBM_RTL=y
# CONFIG_IDEAPAD_LAPTOP is not set
# CONFIG_SENSORS_HDAPS is not set
# CONFIG_THINKPAD_ACPI is not set
# CONFIG_THINKPAD_LMI is not set
CONFIG_INTEL_ATOMISP2_PDX86=y
CONFIG_INTEL_ATOMISP2_LED=y
CONFIG_INTEL_ATOMISP2_PM=m
# CONFIG_INTEL_SAR_INT1092 is not set
# CONFIG_INTEL_SKL_INT3472 is not set
# CONFIG_INTEL_PMC_CORE is not set
# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
# CONFIG_INTEL_WMI_THUNDERBOLT is not set
# CONFIG_INTEL_HID_EVENT is not set
# CONFIG_INTEL_VBTN is not set
# CONFIG_INTEL_INT0002_VGPIO is not set
# CONFIG_INTEL_OAKTRAIL is not set
CONFIG_INTEL_PUNIT_IPC=m
# CONFIG_INTEL_RST is not set
# CONFIG_INTEL_SMARTCONNECT is not set
# CONFIG_INTEL_VSEC is not set
# CONFIG_MSI_LAPTOP is not set
# CONFIG_MSI_WMI is not set
# CONFIG_PCENGINES_APU2 is not set
CONFIG_BARCO_P50_GPIO=m
CONFIG_SAMSUNG_LAPTOP=y
# CONFIG_SAMSUNG_Q10 is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_HAPS is not set
# CONFIG_TOSHIBA_WMI is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_COMPAL_LAPTOP is not set
# CONFIG_LG_LAPTOP is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_SONY_LAPTOP is not set
# CONFIG_SYSTEM76_ACPI is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
CONFIG_MLX_PLATFORM=y
# CONFIG_INTEL_IPS is not set
CONFIG_INTEL_SCU_IPC=y
CONFIG_INTEL_SCU=y
CONFIG_INTEL_SCU_PCI=y
# CONFIG_INTEL_SCU_PLATFORM is not set
CONFIG_INTEL_SCU_IPC_UTIL=y
# CONFIG_SIEMENS_SIMATIC_IPC is not set
# CONFIG_WINMATE_FM07_KEYS is not set
CONFIG_P2SB=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_WM831X=y
# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=m
# CONFIG_COMMON_CLK_SI5341 is not set
CONFIG_COMMON_CLK_SI5351=m
CONFIG_COMMON_CLK_SI514=y
CONFIG_COMMON_CLK_SI544=y
CONFIG_COMMON_CLK_SI570=y
CONFIG_COMMON_CLK_CDCE706=m
CONFIG_COMMON_CLK_CDCE925=m
# CONFIG_COMMON_CLK_CS2000_CP is not set
CONFIG_COMMON_CLK_S2MPS11=m
CONFIG_COMMON_CLK_AXI_CLKGEN=y
CONFIG_COMMON_CLK_PALMAS=y
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
CONFIG_COMMON_CLK_VC5=y
# CONFIG_COMMON_CLK_VC7 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
# CONFIG_CLK_LGM_CGU is not set
CONFIG_XILINX_VCU=y
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_CLKBLD_I8253=y
CONFIG_MICROCHIP_PIT64B=y
# end of Clock Source drivers
CONFIG_MAILBOX=y
CONFIG_PLATFORM_MHU=y
# CONFIG_PCC is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
# end of Generic IOMMU Pagetable Support
CONFIG_IOMMU_DEBUGFS=y
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
CONFIG_IOMMU_DEFAULT_DMA_LAZY=y
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
# CONFIG_INTEL_IOMMU is not set
# CONFIG_IOMMUFD is not set
CONFIG_VIRTIO_IOMMU=m
#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers
#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=y
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_VIRTIO=y
# end of Rpmsg drivers
CONFIG_SOUNDWIRE=y
#
# SoundWire Devices
#
#
# SOC (System On Chip) specific Drivers
#
#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers
#
# Broadcom SoC drivers
#
# end of Broadcom SoC drivers
#
# NXP/Freescale QorIQ SoC drivers
#
# end of NXP/Freescale QorIQ SoC drivers
#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers
#
# i.MX SoC drivers
#
# end of i.MX SoC drivers
#
# Enable LiteX SoC Builder specific drivers
#
CONFIG_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=m
# end of Enable LiteX SoC Builder specific drivers
#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers
CONFIG_SOC_TI=y
#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers
CONFIG_PM_DEVFREQ=y
#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
#
# DEVFREQ Drivers
#
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_INTEL_INT3496 is not set
# CONFIG_EXTCON_MAX14577 is not set
CONFIG_EXTCON_MAX3355=m
# CONFIG_EXTCON_MAX77693 is not set
# CONFIG_EXTCON_MAX77843 is not set
# CONFIG_EXTCON_MAX8997 is not set
# CONFIG_EXTCON_PALMAS is not set
CONFIG_EXTCON_PTN5150=y
CONFIG_EXTCON_RT8973A=m
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=m
CONFIG_MEMORY=y
# CONFIG_IIO is not set
# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_DEBUG=y
CONFIG_PWM_ATMEL_TCB=m
# CONFIG_PWM_CLK is not set
# CONFIG_PWM_CROS_EC is not set
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_INTEL_LGM=y
CONFIG_PWM_IQS620A=m
# CONFIG_PWM_LPSS_PCI is not set
# CONFIG_PWM_LPSS_PLATFORM is not set
CONFIG_PWM_NTXEC=m
# CONFIG_PWM_PCA9685 is not set
# CONFIG_PWM_XILINX is not set
#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_AL_FIC=y
CONFIG_MADERA_IRQ=y
# CONFIG_XILINX_INTC is not set
# end of IRQ chip support
CONFIG_IPACK_BUS=m
# CONFIG_BOARD_TPCI200 is not set
# CONFIG_SERIAL_IPOCTAL is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_INTEL_GW is not set
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set
#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_USB_LGM_PHY is not set
CONFIG_PHY_CAN_TRANSCEIVER=m
#
# PHY drivers for Broadcom platforms
#
CONFIG_BCM_KONA_USB2_PHY=y
# end of PHY drivers for Broadcom platforms
CONFIG_PHY_CADENCE_TORRENT=m
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
CONFIG_PHY_CADENCE_SIERRA=m
CONFIG_PHY_CADENCE_SALVO=y
CONFIG_PHY_PXA_28NM_HSIC=m
CONFIG_PHY_PXA_28NM_USB2=m
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
CONFIG_PHY_INTEL_LGM_COMBO=y
CONFIG_PHY_INTEL_LGM_EMMC=y
# end of PHY Subsystem
CONFIG_POWERCAP=y
CONFIG_INTEL_RAPL_CORE=m
CONFIG_INTEL_RAPL=m
# CONFIG_IDLE_INJECT is not set
CONFIG_DTPM=y
CONFIG_MCB=y
CONFIG_MCB_PCI=y
# CONFIG_MCB_LPC is not set
#
# Performance monitor support
#
# end of Performance monitor support
CONFIG_RAS=y
# CONFIG_USB4 is not set
#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android
CONFIG_DAX=y
# CONFIG_DEV_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_RMEM=m
CONFIG_NVMEM_SPMI_SDAM=m
#
# HW tracing support
#
CONFIG_STM=y
CONFIG_STM_PROTO_BASIC=m
# CONFIG_STM_PROTO_SYS_T is not set
CONFIG_STM_DUMMY=y
CONFIG_STM_SOURCE_CONSOLE=y
CONFIG_STM_SOURCE_HEARTBEAT=y
CONFIG_STM_SOURCE_FTRACE=m
# CONFIG_INTEL_TH is not set
# end of HW tracing support
# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_MULTIPLEXER=y
#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=y
CONFIG_MUX_ADGS1408=m
# CONFIG_MUX_GPIO is not set
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers
CONFIG_PM_OPP=y
CONFIG_SIOX=y
CONFIG_SIOX_BUS_GPIO=y
# CONFIG_SLIMBUS is not set
CONFIG_INTERCONNECT=y
CONFIG_COUNTER=y
CONFIG_104_QUAD_8=y
# CONFIG_INTERRUPT_CNT is not set
CONFIG_FTM_QUADDEC=y
CONFIG_MICROCHIP_TCB_CAPTURE=m
CONFIG_INTEL_QEP=y
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# end of Device Drivers
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
# CONFIG_EXT2_FS_SECURITY is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
# CONFIG_EXT4_FS_POSIX_ACL is not set
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_DEBUG=y
CONFIG_JBD2=y
CONFIG_JBD2_DEBUG=y
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
CONFIG_OCFS2_FS=y
# CONFIG_OCFS2_FS_O2CB is not set
CONFIG_OCFS2_FS_STATS=y
# CONFIG_OCFS2_DEBUG_MASKLOG is not set
CONFIG_OCFS2_DEBUG_FS=y
# CONFIG_BTRFS_FS is not set
CONFIG_NILFS2_FS=y
CONFIG_F2FS_FS=m
# CONFIG_F2FS_STAT_FS is not set
CONFIG_F2FS_FS_XATTR=y
# CONFIG_F2FS_FS_POSIX_ACL is not set
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_CHECK_FS=y
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
# CONFIG_F2FS_FS_LZORLE is not set
# CONFIG_F2FS_FS_LZ4 is not set
# CONFIG_F2FS_FS_ZSTD is not set
CONFIG_F2FS_IOSTAT=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
CONFIG_QUOTA_DEBUG=y
CONFIG_QUOTA_TREE=y
CONFIG_QFMT_V1=m
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_AUTOFS_FS=y
# CONFIG_FUSE_FS is not set
# CONFIG_OVERLAY_FS is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
# end of Caches
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems
#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
# CONFIG_VFAT_FS is not set
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_EXFAT_FS=m
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
# CONFIG_PROC_PAGE_MONITOR is not set
# CONFIG_PROC_CHILDREN is not set
CONFIG_PROC_PID_ARCH_STATUS=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
CONFIG_ADFS_FS=m
CONFIG_ADFS_FS_RW=y
CONFIG_AFFS_FS=y
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_CRAMFS=m
# CONFIG_CRAMFS_BLOCKDEV is not set
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
# CONFIG_SQUASHFS_XATTR is not set
CONFIG_SQUASHFS_ZLIB=y
# CONFIG_SQUASHFS_LZ4 is not set
CONFIG_SQUASHFS_LZO=y
# CONFIG_SQUASHFS_XZ is not set
CONFIG_SQUASHFS_ZSTD=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_VXFS_FS=m
CONFIG_MINIX_FS=m
CONFIG_OMFS_FS=y
CONFIG_HPFS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=m
CONFIG_PSTORE_LZO_COMPRESS=m
CONFIG_PSTORE_LZ4_COMPRESS=m
# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
# CONFIG_PSTORE_842_COMPRESS is not set
# CONFIG_PSTORE_ZSTD_COMPRESS is not set
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="lz4"
# CONFIG_PSTORE_CONSOLE is not set
CONFIG_PSTORE_PMSG=y
# CONFIG_PSTORE_FTRACE is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_PSTORE_BLK is not set
CONFIG_SYSV_FS=y
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
CONFIG_EROFS_FS_DEBUG=y
# CONFIG_EROFS_FS_XATTR is not set
# CONFIG_EROFS_FS_ZIP is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=y
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=m
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
CONFIG_NLS_CODEPAGE_866=m
# CONFIG_NLS_CODEPAGE_869 is not set
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
CONFIG_NLS_CODEPAGE_949=y
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
CONFIG_NLS_ISO8859_3=m
# CONFIG_NLS_ISO8859_4 is not set
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=y
CONFIG_NLS_MAC_CELTIC=y
CONFIG_NLS_MAC_CENTEURO=m
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
CONFIG_NLS_MAC_GAELIC=y
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
# end of File systems
#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
CONFIG_PERSISTENT_KEYRINGS=y
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_INFINIBAND is not set
# CONFIG_SECURITY_PATH is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper"
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
#
# Kernel hardening options
#
#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_ENABLER=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
# CONFIG_INIT_STACK_NONE is not set
CONFIG_INIT_STACK_ALL_PATTERN=y
# CONFIG_INIT_STACK_ALL_ZERO is not set
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
CONFIG_RANDSTRUCT_NONE=y
# end of Kernel hardening options
# end of Security options
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=m
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_SIMD=y
# end of Crypto core or helper
#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECDSA=m
CONFIG_CRYPTO_ECRDSA=y
# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography
#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
CONFIG_CRYPTO_SERPENT=y
# CONFIG_CRYPTO_SM4_GENERIC is not set
# CONFIG_CRYPTO_TWOFISH is not set
CONFIG_CRYPTO_TWOFISH_COMMON=m
# end of Block ciphers
#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_LRW is not set
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=m
CONFIG_CRYPTO_NHPOLY1305=m
# end of Length-preserving ciphers and modes
#
# AEAD (authenticated encryption with associated data) ciphers
#
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers
#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_RMD160 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
# CONFIG_CRYPTO_SM3_GENERIC is not set
CONFIG_CRYPTO_STREEBOG=y
# CONFIG_CRYPTO_VMAC is not set
CONFIG_CRYPTO_WP512=m
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_XXHASH is not set
# end of Hashes, digests, and MACs
#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=m
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_LZO=m
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=m
# end of Compression
#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation
#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
# CONFIG_CRYPTO_STATS is not set
# end of Userspace interface
CONFIG_CRYPTO_HASH_INFO=y
#
# Accelerated Cryptographic Algorithms for CPU (x86)
#
# CONFIG_CRYPTO_AES_NI_INTEL is not set
CONFIG_CRYPTO_SERPENT_SSE2_586=y
CONFIG_CRYPTO_TWOFISH_586=m
# CONFIG_CRYPTO_CRC32C_INTEL is not set
CONFIG_CRYPTO_CRC32_PCLMUL=y
# end of Accelerated Cryptographic Algorithms for CPU (x86)
# CONFIG_CRYPTO_HW is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
#
# Certificates for signature checking
#
# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking
CONFIG_BINARY_PRINTF=y
#
# Library routines
#
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
# CONFIG_CORDIC is not set
CONFIG_PRIME_NUMBERS=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
# CONFIG_CRYPTO_LIB_CURVE25519 is not set
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
# CONFIG_CRC32_SLICEBY8 is not set
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_BIT=y
CONFIG_CRC64=y
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=m
CONFIG_CRC8=y
CONFIG_XXHASH=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=m
CONFIG_ZSTD_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_PERCENTAGE=0
# CONFIG_CMA_SIZE_SEL_MBYTES is not set
CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
CONFIG_DMA_MAP_BENCHMARK=y
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# end of Library routines
CONFIG_PLDMFW=y
#
# Kernel hacking
#
#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DYNAMIC_DEBUG_CORE is not set
# CONFIG_SYMBOLIC_ERRNAME is not set
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y
#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_LEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_BTF_TAG=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=8192
CONFIG_STRIP_ASM_SYMS=y
CONFIG_HEADERS_INSTALL=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
CONFIG_VMLINUX_MAP=y
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
# end of Compile-time checks and compiler options
#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_FS_ALLOW_ALL is not set
CONFIG_DEBUG_FS_DISALLOW_MOUNT=y
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
CONFIG_UBSAN=y
# CONFIG_UBSAN_TRAP is not set
CONFIG_CC_HAS_UBSAN_BOUNDS=y
CONFIG_CC_HAS_UBSAN_ARRAY_BOUNDS=y
CONFIG_UBSAN_BOUNDS=y
CONFIG_UBSAN_ARRAY_BOUNDS=y
CONFIG_UBSAN_SHIFT=y
CONFIG_UBSAN_UNREACHABLE=y
# CONFIG_UBSAN_BOOL is not set
# CONFIG_UBSAN_ENUM is not set
# CONFIG_UBSAN_ALIGNMENT is not set
CONFIG_UBSAN_SANITIZE_ALL=y
# CONFIG_TEST_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments
#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging
#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
CONFIG_PAGE_OWNER=y
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
CONFIG_PTDUMP_CORE=y
CONFIG_PTDUMP_DEBUGFS=y
CONFIG_DEBUG_OBJECTS=y
# CONFIG_DEBUG_OBJECTS_SELFTEST is not set
# CONFIG_DEBUG_OBJECTS_FREE is not set
# CONFIG_DEBUG_OBJECTS_TIMERS is not set
CONFIG_DEBUG_OBJECTS_WORK=y
# CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set
# CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_STACK_USAGE=y
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_DEBUG_KMAP_LOCAL=y
CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
# CONFIG_DEBUG_HIGHMEM is not set
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
CONFIG_HAVE_KMSAN_COMPILER=y
# end of Memory Debugging
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Oops, Lockups and Hangs
#
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=480
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_WQ_WATCHDOG=y
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs
#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging
CONFIG_DEBUG_TIMEKEEPING=y
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
# CONFIG_PROVE_RAW_LOCK_NESTING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_LOCK_TORTURE_TEST=m
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)
CONFIG_TRACE_IRQFLAGS=y
CONFIG_TRACE_IRQFLAGS_NMI=y
# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
CONFIG_DEBUG_SG=y
# CONFIG_DEBUG_NOTIFIERS is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures
# CONFIG_DEBUG_CREDENTIALS is not set
#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_LIST is not set
CONFIG_TORTURE_TEST=m
CONFIG_RCU_SCALE_TEST=m
CONFIG_RCU_TORTURE_TEST=m
CONFIG_RCU_REF_SCALE_TEST=m
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
CONFIG_RCU_TRACE=y
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging
CONFIG_DEBUG_WQ_FORCE_RR_CPU=y
CONFIG_CPU_HOTPLUG_STATE_CONTROL=y
CONFIG_LATENCYTOP=y
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_RETHOOK=y
CONFIG_RETHOOK=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_FENTRY=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
CONFIG_BUILDTIME_MCOUNT_SORT=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
CONFIG_DYNAMIC_FTRACE=y
CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
# CONFIG_FPROBE is not set
# CONFIG_FUNCTION_PROFILER is not set
CONFIG_STACK_TRACER=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_HWLAT_TRACER=y
CONFIG_OSNOISE_TRACER=y
# CONFIG_TIMERLAT_TRACER is not set
CONFIG_MMIOTRACE=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_TRACER_SNAPSHOT=y
CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_KPROBE_EVENTS_ON_NOTRACE=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_BPF_KPROBE_OVERRIDE=y
CONFIG_FTRACE_MCOUNT_RECORD=y
CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y
CONFIG_TRACING_MAP=y
CONFIG_SYNTH_EVENTS=y
CONFIG_HIST_TRIGGERS=y
CONFIG_TRACE_EVENT_INJECT=y
CONFIG_TRACEPOINT_BENCHMARK=y
CONFIG_RING_BUFFER_BENCHMARK=m
# CONFIG_TRACE_EVAL_MAP_FILE is not set
CONFIG_FTRACE_RECORD_RECURSION=y
CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
# CONFIG_RING_BUFFER_RECORD_RECURSION is not set
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y
# CONFIG_MMIOTRACE_TEST is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_SYNTH_EVENT_GEN_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
CONFIG_HIST_TRIGGERS_DEBUG=y
# CONFIG_RV is not set
# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
CONFIG_SAMPLES=y
# CONFIG_SAMPLE_AUXDISPLAY is not set
CONFIG_SAMPLE_TRACE_EVENTS=m
# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set
# CONFIG_SAMPLE_TRACE_PRINTK is not set
# CONFIG_SAMPLE_TRACE_ARRAY is not set
# CONFIG_SAMPLE_KOBJECT is not set
CONFIG_SAMPLE_KPROBES=m
# CONFIG_SAMPLE_KRETPROBES is not set
# CONFIG_SAMPLE_HW_BREAKPOINT is not set
# CONFIG_SAMPLE_KFIFO is not set
CONFIG_SAMPLE_RPMSG_CLIENT=m
CONFIG_SAMPLE_CONFIGFS=m
CONFIG_SAMPLE_CONNECTOR=m
CONFIG_SAMPLE_FANOTIFY_ERROR=y
CONFIG_SAMPLE_HIDRAW=y
# CONFIG_SAMPLE_LANDLOCK is not set
# CONFIG_SAMPLE_PIDFD is not set
CONFIG_SAMPLE_TIMER=y
CONFIG_SAMPLE_UHID=y
CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB=m
# CONFIG_SAMPLE_ANDROID_BINDERFS is not set
CONFIG_SAMPLE_VFS=y
# CONFIG_SAMPLE_INTEL_MEI is not set
CONFIG_SAMPLE_WATCHDOG=y
CONFIG_SAMPLE_WATCH_QUEUE=y
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set
#
# x86 Debugging
#
CONFIG_EARLY_PRINTK_USB=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_DBGP=y
CONFIG_EARLY_PRINTK_USB_XDBC=y
CONFIG_DEBUG_TLBFLUSH=y
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
# CONFIG_X86_DECODER_SELFTEST is not set
CONFIG_IO_DELAY_0X80=y
# CONFIG_IO_DELAY_0XED is not set
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
# CONFIG_DEBUG_BOOT_PARAMS is not set
# CONFIG_CPA_DEBUG is not set
# CONFIG_DEBUG_ENTRY is not set
# CONFIG_DEBUG_NMI_SELFTEST is not set
# CONFIG_X86_DEBUG_FPU is not set
CONFIG_PUNIT_ATOM_DEBUG=m
CONFIG_UNWINDER_FRAME_POINTER=y
# end of x86 Debugging
#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
CONFIG_NOTIFIER_ERROR_INJECTION=m
CONFIG_PM_NOTIFIER_ERROR_INJECT=m
CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=m
CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m
CONFIG_FUNCTION_ERROR_INJECTION=y
CONFIG_FAULT_INJECTION=y
# CONFIG_FAILSLAB is not set
# CONFIG_FAIL_PAGE_ALLOC is not set
CONFIG_FAULT_INJECTION_USERCOPY=y
# CONFIG_FAIL_MAKE_REQUEST is not set
CONFIG_FAIL_IO_TIMEOUT=y
CONFIG_FAIL_FUTEX=y
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAIL_FUNCTION=y
# CONFIG_FAULT_INJECTION_STACKTRACE_FILTER is not set
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage
#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
2023-01-11 15:30 ` kernel test robot
@ 2023-01-11 22:55 ` kernel test robot
2023-01-17 10:01 ` Hans Verkuil
` (2 subsequent siblings)
4 siblings, 0 replies; 42+ messages in thread
From: kernel test robot @ 2023-01-11 22:55 UTC (permalink / raw)
To: Yuji Ishikawa, Hans Verkuil, Laurent Pinchart,
Mauro Carvalho Chehab, Nobuhiro Iwamatsu, Rob Herring,
Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown
Cc: oe-kbuild-all, linux-media, linux-arm-kernel, linux-kernel,
devicetree, yuji2.ishikawa
[-- Attachment #1: Type: text/plain, Size: 2029 bytes --]
Hi Yuji,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on media-tree/master]
[also build test ERROR on linus/master v6.2-rc3 next-20230111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yuji-Ishikawa/dt-bindings-media-platform-visconti-Add-Toshiba-Visconti-Video-Input-Interface-bindings/20230111-103311
base: git://linuxtv.org/media_tree.git master
patch link: https://lore.kernel.org/r/20230111022433.25950-3-yuji2.ishikawa%40toshiba.co.jp
patch subject: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
config: i386-allyesconfig
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/3c3aa5193e57992c40b61f5cc1cdc072c2b14fae
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Yuji-Ishikawa/dt-bindings-media-platform-visconti-Add-Toshiba-Visconti-Video-Input-Interface-bindings/20230111-103311
git checkout 3c3aa5193e57992c40b61f5cc1cdc072c2b14fae
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 olddefconfig
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from ./usr/include/linux/visconti_viif.h:12,
from <command-line>:
>> usr/include/linux/videodev2.h:2442:41: error: field 'timestamp' has incomplete type
2442 | struct timespec timestamp;
| ^~~~~~~~~
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
[-- Attachment #2: config --]
[-- Type: text/plain, Size: 289986 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# Linux/i386 6.2.0-rc1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="gcc-11 (Debian 11.3.0-8) 11.3.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=110300
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=23990
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=23990
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=123
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_UAPI_HEADER_TEST=y
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_ZSTD=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
# CONFIG_KERNEL_ZSTD is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_WATCH_QUEUE=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_USELIB=y
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_PENDING_IRQ=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_TIME_KUNIT_TEST=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=125
# end of Timers subsystem
CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_JIT_ALWAYS_ON=y
CONFIG_BPF_JIT_DEFAULT_ON=y
CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
CONFIG_USERMODE_DRIVER=y
# CONFIG_BPF_PRELOAD is not set
CONFIG_BPF_LSM=y
# end of BPF subsystem
CONFIG_PREEMPT_BUILD=y
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_DYNAMIC=y
CONFIG_SCHED_CORE=y
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_SCHED_AVG_IRQ=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
CONFIG_PSI_DEFAULT_DISABLED=y
# end of CPU/Task time and stats accounting
CONFIG_CPU_ISOLATION=y
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_FORCE_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_FORCE_TASKS_RUDE_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_FORCE_TASKS_TRACE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_FANOUT=32
CONFIG_RCU_FANOUT_LEAF=16
CONFIG_RCU_BOOST=y
CONFIG_RCU_BOOST_DELAY=500
CONFIG_RCU_EXP_KTHREAD=y
CONFIG_RCU_NOCB_CPU=y
CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
CONFIG_RCU_NOCB_CPU_CB_BOOST=y
CONFIG_TASKS_TRACE_RCU_READ_MB=y
CONFIG_RCU_LAZY=y
# end of RCU Subsystem
CONFIG_BUILD_BIN2C=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_IKHEADERS=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_PRINTK_INDEX=y
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
#
# Scheduler features
#
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_BUCKETS_COUNT=5
# end of Scheduler features
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_CGROUP_FAVOR_DYNMODS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
CONFIG_CGROUP_DEBUG=y
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
CONFIG_BOOT_CONFIG_EMBED=y
CONFIG_BOOT_CONFIG_EMBED_FILE=""
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_SELFTEST=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
CONFIG_DEBUG_RSEQ=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PC104=y
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
CONFIG_DEBUG_PERF_USE_VMALLOC=y
# end of Kernel Performance Events And Counters
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup
CONFIG_X86_32=y
CONFIG_FORCE_DYNAMIC_FTRACE=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf32-i386"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_HAVE_INTEL_TXT=y
CONFIG_X86_32_SMP=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
#
# Processor type and features
#
CONFIG_SMP=y
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_MPPARSE=y
CONFIG_GOLDFISH=y
CONFIG_X86_CPU_RESCTRL=y
CONFIG_X86_BIGSMP=y
CONFIG_X86_EXTENDED_PLATFORM=y
CONFIG_X86_GOLDFISH=y
CONFIG_X86_INTEL_MID=y
CONFIG_X86_INTEL_QUARK=y
CONFIG_X86_INTEL_LPSS=y
CONFIG_X86_AMD_PLATFORM_DEVICE=y
CONFIG_IOSF_MBI=y
CONFIG_IOSF_MBI_DEBUG=y
CONFIG_X86_RDC321X=y
CONFIG_X86_32_NON_STANDARD=y
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
CONFIG_STA2X11=y
CONFIG_X86_32_IRIS=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_DEBUG=y
CONFIG_PARAVIRT_SPINLOCKS=y
CONFIG_X86_HV_CALLBACK_VECTOR=y
CONFIG_KVM_GUEST=y
CONFIG_ARCH_CPUIDLE_HALTPOLL=y
CONFIG_PVH=y
CONFIG_PARAVIRT_TIME_ACCOUNTING=y
CONFIG_PARAVIRT_CLOCK=y
# CONFIG_M486SX is not set
# CONFIG_M486 is not set
# CONFIG_M586 is not set
# CONFIG_M586TSC is not set
# CONFIG_M586MMX is not set
CONFIG_M686=y
# CONFIG_MPENTIUMII is not set
# CONFIG_MPENTIUMIII is not set
# CONFIG_MPENTIUMM is not set
# CONFIG_MPENTIUM4 is not set
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MEFFICEON is not set
# CONFIG_MWINCHIPC6 is not set
# CONFIG_MWINCHIP3D is not set
# CONFIG_MELAN is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
# CONFIG_MCYRIXIII is not set
# CONFIG_MVIAC3_2 is not set
# CONFIG_MVIAC7 is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_X86_GENERIC=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_USE_PPRO_CHECKSUM=y
CONFIG_X86_TSC=y
CONFIG_X86_CMPXCHG64=y
CONFIG_X86_CMOV=y
CONFIG_X86_MINIMUM_CPU_FAMILY=6
CONFIG_X86_DEBUGCTLMSR=y
CONFIG_IA32_FEAT_CTL=y
CONFIG_X86_VMX_FEATURE_NAMES=y
CONFIG_PROCESSOR_SELECT=y
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_CYRIX_32=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_HYGON=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_CPU_SUP_TRANSMETA_32=y
CONFIG_CPU_SUP_UMC_32=y
CONFIG_CPU_SUP_ZHAOXIN=y
CONFIG_CPU_SUP_VORTEX_32=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_DMI=y
CONFIG_BOOT_VESA_SUPPORT=y
CONFIG_NR_CPUS_RANGE_BEGIN=2
CONFIG_NR_CPUS_RANGE_END=64
CONFIG_NR_CPUS_DEFAULT=32
CONFIG_NR_CPUS=32
CONFIG_SCHED_CLUSTER=y
CONFIG_SCHED_SMT=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_MC_PRIO=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
CONFIG_X86_MCE=y
CONFIG_X86_MCELOG_LEGACY=y
CONFIG_X86_MCE_INTEL=y
CONFIG_X86_MCE_AMD=y
CONFIG_X86_ANCIENT_MCE=y
CONFIG_X86_MCE_THRESHOLD=y
CONFIG_X86_MCE_INJECT=y
#
# Performance monitoring
#
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
CONFIG_PERF_EVENTS_INTEL_RAPL=y
CONFIG_PERF_EVENTS_INTEL_CSTATE=y
CONFIG_PERF_EVENTS_AMD_POWER=y
CONFIG_PERF_EVENTS_AMD_UNCORE=y
CONFIG_PERF_EVENTS_AMD_BRS=y
# end of Performance monitoring
CONFIG_X86_LEGACY_VM86=y
CONFIG_VM86=y
CONFIG_X86_16BIT=y
CONFIG_X86_ESPFIX32=y
CONFIG_X86_IOPL_IOPERM=y
CONFIG_TOSHIBA=y
CONFIG_X86_REBOOTFIXUPS=y
CONFIG_MICROCODE=y
CONFIG_MICROCODE_INTEL=y
CONFIG_MICROCODE_AMD=y
CONFIG_MICROCODE_LATE_LOADING=y
CONFIG_X86_MSR=y
CONFIG_X86_CPUID=y
# CONFIG_NOHIGHMEM is not set
CONFIG_HIGHMEM4G=y
# CONFIG_HIGHMEM64G is not set
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_3G_OPT is not set
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_2G_OPT is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_HIGHMEM=y
CONFIG_X86_CPA_STATISTICS=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_HIGHPTE=y
CONFIG_X86_CHECK_BIOS_CORRUPTION=y
CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
CONFIG_MTRR=y
CONFIG_MTRR_SANITIZER=y
CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
CONFIG_X86_PAT=y
CONFIG_ARCH_USES_PG_UNCACHED=y
CONFIG_X86_UMIP=y
CONFIG_CC_HAS_IBT=y
CONFIG_X86_INTEL_TSX_MODE_OFF=y
# CONFIG_X86_INTEL_TSX_MODE_ON is not set
# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
CONFIG_EFI=y
CONFIG_EFI_STUB=y
CONFIG_EFI_HANDOVER_PROTOCOL=y
CONFIG_EFI_FAKE_MEMMAP=y
CONFIG_EFI_MAX_FAKE_MEM=8
CONFIG_EFI_RUNTIME_MAP=y
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_KEXEC_JUMP=y
CONFIG_PHYSICAL_START=0x1000000
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_X86_NEED_RELOCS=y
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_HOTPLUG_CPU=y
CONFIG_BOOTPARAM_HOTPLUG_CPU0=y
CONFIG_DEBUG_HOTPLUG_CPU0=y
CONFIG_COMPAT_VDSO=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE=""
CONFIG_MODIFY_LDT_SYSCALL=y
CONFIG_STRICT_SIGALTSTACK_SIZE=y
# end of Processor type and features
CONFIG_CC_HAS_SLS=y
CONFIG_CC_HAS_RETURN_THUNK=y
CONFIG_CC_HAS_ENTRY_PADDING=y
CONFIG_FUNCTION_PADDING_CFI=0
CONFIG_FUNCTION_PADDING_BYTES=4
CONFIG_SPECULATION_MITIGATIONS=y
CONFIG_RETPOLINE=y
CONFIG_RETHUNK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
#
# Power management and ACPI options
#
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SUSPEND_SKIP_SYNC=y
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_HIBERNATION_SNAPSHOT_DEV=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_USERSPACE_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=100
CONFIG_PM_WAKELOCKS_GC=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_DPM_WATCHDOG=y
CONFIG_DPM_WATCHDOG_TIMEOUT=120
CONFIG_PM_TRACE=y
CONFIG_PM_TRACE_RTC=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
CONFIG_ACPI_TABLE_LIB=y
CONFIG_ACPI_DEBUGGER=y
CONFIG_ACPI_DEBUGGER_USER=y
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_SLEEP=y
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
CONFIG_ACPI_EC_DEBUGFS=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
CONFIG_ACPI_TAD=y
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_IPMI=y
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_PROCESSOR_AGGREGATOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_PLATFORM_PROFILE=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_DEBUG=y
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
CONFIG_ACPI_SBS=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=y
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_PCIEAER=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=y
CONFIG_ACPI_APEI_ERST_DEBUG=y
CONFIG_ACPI_DPTF=y
CONFIG_DPTF_POWER=y
CONFIG_DPTF_PCH_FIVR=y
CONFIG_ACPI_WATCHDOG=y
CONFIG_ACPI_EXTLOG=y
CONFIG_ACPI_CONFIGFS=y
CONFIG_ACPI_PCC=y
CONFIG_ACPI_FFH=y
CONFIG_PMIC_OPREGION=y
CONFIG_BYTCRC_PMIC_OPREGION=y
CONFIG_CHTCRC_PMIC_OPREGION=y
CONFIG_XPOWER_PMIC_OPREGION=y
CONFIG_BXT_WC_PMIC_OPREGION=y
CONFIG_CHT_WC_PMIC_OPREGION=y
CONFIG_CHT_DC_TI_PMIC_OPREGION=y
CONFIG_TPS68470_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_X86_PM_TIMER=y
CONFIG_X86_APM_BOOT=y
CONFIG_APM=y
CONFIG_APM_IGNORE_USER_SUSPEND=y
CONFIG_APM_DO_ENABLE=y
CONFIG_APM_CPU_IDLE=y
CONFIG_APM_DISPLAY_BLANK=y
CONFIG_APM_ALLOW_INTS=y
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_X86_INTEL_PSTATE=y
CONFIG_X86_PCC_CPUFREQ=y
CONFIG_X86_AMD_PSTATE=y
CONFIG_X86_AMD_PSTATE_UT=y
CONFIG_X86_ACPI_CPUFREQ=y
CONFIG_X86_ACPI_CPUFREQ_CPB=y
CONFIG_X86_POWERNOW_K6=y
CONFIG_X86_POWERNOW_K7=y
CONFIG_X86_POWERNOW_K7_ACPI=y
CONFIG_X86_POWERNOW_K8=y
CONFIG_X86_AMD_FREQ_SENSITIVITY=y
CONFIG_X86_GX_SUSPMOD=y
CONFIG_X86_SPEEDSTEP_CENTRINO=y
CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE=y
CONFIG_X86_SPEEDSTEP_ICH=y
CONFIG_X86_SPEEDSTEP_SMI=y
CONFIG_X86_P4_CLOCKMOD=y
CONFIG_X86_CPUFREQ_NFORCE2=y
CONFIG_X86_LONGRUN=y
CONFIG_X86_LONGHAUL=y
CONFIG_X86_E_POWERSAVER=y
#
# shared options
#
CONFIG_X86_SPEEDSTEP_LIB=y
CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK=y
# end of CPU Frequency scaling
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_GOV_TEO=y
CONFIG_CPU_IDLE_GOV_HALTPOLL=y
CONFIG_HALTPOLL_CPUIDLE=y
# end of CPU Idle
CONFIG_INTEL_IDLE=y
# end of Power management and ACPI options
#
# Bus options (PCI etc.)
#
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GOMMCONFIG is not set
# CONFIG_PCI_GODIRECT is not set
# CONFIG_PCI_GOOLPC is not set
CONFIG_PCI_GOANY=y
CONFIG_PCI_BIOS=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCI_OLPC=y
CONFIG_PCI_CNB20LE_QUIRK=y
CONFIG_ISA_BUS=y
CONFIG_ISA_DMA_API=y
CONFIG_ISA=y
CONFIG_SCx200=y
CONFIG_SCx200HR_TIMER=y
CONFIG_OLPC=y
CONFIG_OLPC_XO1_PM=y
CONFIG_OLPC_XO1_RTC=y
CONFIG_OLPC_XO1_SCI=y
CONFIG_OLPC_XO15_SCI=y
CONFIG_ALIX=y
CONFIG_NET5501=y
CONFIG_GEOS=y
CONFIG_AMD_NB=y
# end of Bus options (PCI etc.)
#
# Binary Emulations
#
CONFIG_COMPAT_32=y
# end of Binary Emulations
CONFIG_HAVE_ATOMIC_IOMAP=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_PFNCACHE=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_TSO=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_ASYNC_PF=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_NO_POLL=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_HAVE_KVM_PM_NOTIFIER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_KVM_WERROR is not set
CONFIG_KVM_INTEL=y
CONFIG_KVM_AMD=y
CONFIG_KVM_SMM=y
CONFIG_KVM_XEN=y
CONFIG_AS_AVX512=y
CONFIG_AS_SHA1_NI=y
CONFIG_AS_SHA256_NI=y
CONFIG_AS_TPAUSE=y
#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_HOTPLUG_SMT=y
CONFIG_GENERIC_ENTRY=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
CONFIG_STATIC_KEYS_SELFTEST=y
CONFIG_STATIC_CALL_SELFTEST=y
CONFIG_OPTPROBES=y
CONFIG_KPROBES_ON_FTRACE=y
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_KRETPROBE_ON_RETHOOK=y
CONFIG_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_GATHER_MERGE_VMAS=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_SECCOMP_CACHE_DEBUG=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ISA_BUS_API=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
CONFIG_LOCK_EVENT_COUNTS=y
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
CONFIG_HAVE_STATIC_CALL=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPLIT_ARG64=y
CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
CONFIG_DYNAMIC_SIGFRAME=y
#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# CONFIG_GCOV_PROFILE_ALL is not set
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULE_SIG_FORMAT=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y
CONFIG_MODVERSIONS=y
CONFIG_ASM_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_MODULE_SIG=y
CONFIG_MODULE_SIG_FORCE=y
CONFIG_MODULE_SIG_ALL=y
CONFIG_MODULE_SIG_SHA1=y
# CONFIG_MODULE_SIG_SHA224 is not set
# CONFIG_MODULE_SIG_SHA256 is not set
# CONFIG_MODULE_SIG_SHA384 is not set
# CONFIG_MODULE_SIG_SHA512 is not set
CONFIG_MODULE_SIG_HASH="sha1"
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
CONFIG_BLK_DEV_THROTTLING_LOW=y
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_FC_APPID=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
CONFIG_ACORN_PARTITION=y
CONFIG_ACORN_PARTITION_CUMANA=y
CONFIG_ACORN_PARTITION_EESOX=y
CONFIG_ACORN_PARTITION_ICS=y
CONFIG_ACORN_PARTITION_ADFS=y
CONFIG_ACORN_PARTITION_POWERTEC=y
CONFIG_ACORN_PARTITION_RISCIX=y
CONFIG_AIX_PARTITION=y
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
CONFIG_LDM_DEBUG=y
CONFIG_SGI_PARTITION=y
CONFIG_ULTRIX_PARTITION=y
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_SYSV68_PARTITION=y
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_MQ_RDMA=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y
#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
CONFIG_BFQ_CGROUP_DEBUG=y
# end of IO Schedulers
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_ELF_KUNIT_TEST=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats
#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
CONFIG_ZSWAP_DEFAULT_ON=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
CONFIG_ZSMALLOC_STAT=y
#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB_DEPRECATED is not set
CONFIG_SLUB_TINY=y
CONFIG_SLAB_MERGE_DEFAULT=y
# end of SLAB allocator options
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
CONFIG_COMPAT_BRK=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_BOUNCE=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
CONFIG_HWPOISON_INJECT=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_READ_ONLY_THP_FOR_FS=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
CONFIG_CMA_DEBUG=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_HMM_MIRROR=y
CONFIG_VMAP_PFN=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PERCPU_STATS=y
CONFIG_GUP_TEST=y
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MAPPING_DIRTY_HELPERS=y
CONFIG_KMAP_LOCAL=y
CONFIG_SECRETMEM=y
CONFIG_ANON_VMA_NAME=y
CONFIG_USERFAULTFD=y
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
CONFIG_LRU_GEN_STATS=y
#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_KUNIT_TEST=y
CONFIG_DAMON_VADDR=y
CONFIG_DAMON_PADDR=y
CONFIG_DAMON_VADDR_KUNIT_TEST=y
CONFIG_DAMON_SYSFS=y
CONFIG_DAMON_DBGFS=y
CONFIG_DAMON_DBGFS_KUNIT_TEST=y
CONFIG_DAMON_RECLAIM=y
CONFIG_DAMON_LRU_SORT=y
# end of Data Access Monitoring
# end of Memory Management options
CONFIG_NET=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=y
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_XFRM_ESPINTCP=y
CONFIG_SMC=y
CONFIG_SMC_DIAG=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_FIB_TRIE_STATS=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=y
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=y
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=y
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=y
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=y
CONFIG_TCP_CONG_HTCP=y
CONFIG_TCP_CONG_HSTCP=y
CONFIG_TCP_CONG_HYBLA=y
CONFIG_TCP_CONG_VEGAS=y
CONFIG_TCP_CONG_NV=y
CONFIG_TCP_CONG_SCALABLE=y
CONFIG_TCP_CONG_LP=y
CONFIG_TCP_CONG_VENO=y
CONFIG_TCP_CONG_YEAH=y
CONFIG_TCP_CONG_ILLINOIS=y
CONFIG_TCP_CONG_DCTCP=y
CONFIG_TCP_CONG_CDG=y
CONFIG_TCP_CONG_BBR=y
# CONFIG_DEFAULT_BIC is not set
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_HTCP is not set
# CONFIG_DEFAULT_HYBLA is not set
# CONFIG_DEFAULT_VEGAS is not set
# CONFIG_DEFAULT_VENO is not set
# CONFIG_DEFAULT_WESTWOOD is not set
# CONFIG_DEFAULT_DCTCP is not set
# CONFIG_DEFAULT_CDG is not set
# CONFIG_DEFAULT_BBR is not set
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=y
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_ILA=y
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=y
CONFIG_IPV6_SIT=y
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=y
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
CONFIG_IPV6_IOAM6_LWTUNNEL=y
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_MPTCP_KUNIT_TEST=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=y
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_NETLINK_HOOK=y
CONFIG_NETFILTER_NETLINK_ACCT=y
CONFIG_NETFILTER_NETLINK_QUEUE=y
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_NETFILTER_NETLINK_OSF=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=y
CONFIG_NETFILTER_CONNCOUNT=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_BROADCAST=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_SNMP=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SIP=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NF_CT_NETLINK_TIMEOUT=y
CONFIG_NF_CT_NETLINK_HELPER=y
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=y
CONFIG_NF_NAT_AMANDA=y
CONFIG_NF_NAT_FTP=y
CONFIG_NF_NAT_IRC=y
CONFIG_NF_NAT_SIP=y
CONFIG_NF_NAT_TFTP=y
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=y
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=y
CONFIG_NFT_CT=y
CONFIG_NFT_FLOW_OFFLOAD=y
CONFIG_NFT_CONNLIMIT=y
CONFIG_NFT_LOG=y
CONFIG_NFT_LIMIT=y
CONFIG_NFT_MASQ=y
CONFIG_NFT_REDIR=y
CONFIG_NFT_NAT=y
CONFIG_NFT_TUNNEL=y
CONFIG_NFT_QUEUE=y
CONFIG_NFT_QUOTA=y
CONFIG_NFT_REJECT=y
CONFIG_NFT_REJECT_INET=y
CONFIG_NFT_COMPAT=y
CONFIG_NFT_HASH=y
CONFIG_NFT_FIB=y
CONFIG_NFT_FIB_INET=y
CONFIG_NFT_XFRM=y
CONFIG_NFT_SOCKET=y
CONFIG_NFT_OSF=y
CONFIG_NFT_TPROXY=y
CONFIG_NFT_SYNPROXY=y
CONFIG_NF_DUP_NETDEV=y
CONFIG_NFT_DUP_NETDEV=y
CONFIG_NFT_FWD_NETDEV=y
CONFIG_NFT_FIB_NETDEV=y
CONFIG_NFT_REJECT_NETDEV=y
CONFIG_NF_FLOW_TABLE_INET=y
CONFIG_NF_FLOW_TABLE=y
CONFIG_NF_FLOW_TABLE_PROCFS=y
CONFIG_NETFILTER_XTABLES=y
#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y
CONFIG_NETFILTER_XT_SET=y
#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=y
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_CT=y
CONFIG_NETFILTER_XT_TARGET_DSCP=y
CONFIG_NETFILTER_XT_TARGET_HL=y
CONFIG_NETFILTER_XT_TARGET_HMARK=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_LED=y
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_NAT=y
CONFIG_NETFILTER_XT_TARGET_NETMAP=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
CONFIG_NETFILTER_XT_TARGET_TEE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
CONFIG_NETFILTER_XT_MATCH_BPF=y
CONFIG_NETFILTER_XT_MATCH_CGROUP=y
CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_CPU=y
CONFIG_NETFILTER_XT_MATCH_DCCP=y
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
CONFIG_NETFILTER_XT_MATCH_DSCP=y
CONFIG_NETFILTER_XT_MATCH_ECN=y
CONFIG_NETFILTER_XT_MATCH_ESP=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_HL=y
CONFIG_NETFILTER_XT_MATCH_IPCOMP=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_IPVS=y
CONFIG_NETFILTER_XT_MATCH_L2TP=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
CONFIG_NETFILTER_XT_MATCH_NFACCT=y
CONFIG_NETFILTER_XT_MATCH_OSF=y
CONFIG_NETFILTER_XT_MATCH_OWNER=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_RATEEST=y
CONFIG_NETFILTER_XT_MATCH_REALM=y
CONFIG_NETFILTER_XT_MATCH_RECENT=y
CONFIG_NETFILTER_XT_MATCH_SCTP=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
# end of Core Netfilter Configuration
CONFIG_IP_SET=y
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=y
CONFIG_IP_SET_BITMAP_IPMAC=y
CONFIG_IP_SET_BITMAP_PORT=y
CONFIG_IP_SET_HASH_IP=y
CONFIG_IP_SET_HASH_IPMARK=y
CONFIG_IP_SET_HASH_IPPORT=y
CONFIG_IP_SET_HASH_IPPORTIP=y
CONFIG_IP_SET_HASH_IPPORTNET=y
CONFIG_IP_SET_HASH_IPMAC=y
CONFIG_IP_SET_HASH_MAC=y
CONFIG_IP_SET_HASH_NETPORTNET=y
CONFIG_IP_SET_HASH_NET=y
CONFIG_IP_SET_HASH_NETNET=y
CONFIG_IP_SET_HASH_NETPORT=y
CONFIG_IP_SET_HASH_NETIFACE=y
CONFIG_IP_SET_LIST_SET=y
CONFIG_IP_VS=y
CONFIG_IP_VS_IPV6=y
CONFIG_IP_VS_DEBUG=y
CONFIG_IP_VS_TAB_BITS=12
#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y
#
# IPVS scheduler
#
CONFIG_IP_VS_RR=y
CONFIG_IP_VS_WRR=y
CONFIG_IP_VS_LC=y
CONFIG_IP_VS_WLC=y
CONFIG_IP_VS_FO=y
CONFIG_IP_VS_OVF=y
CONFIG_IP_VS_LBLC=y
CONFIG_IP_VS_LBLCR=y
CONFIG_IP_VS_DH=y
CONFIG_IP_VS_SH=y
CONFIG_IP_VS_MH=y
CONFIG_IP_VS_SED=y
CONFIG_IP_VS_NQ=y
CONFIG_IP_VS_TWOS=y
#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8
#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12
#
# IPVS application helper
#
CONFIG_IP_VS_FTP=y
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=y
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_TPROXY_IPV4=y
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=y
CONFIG_NFT_DUP_IPV4=y
CONFIG_NFT_FIB_IPV4=y
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=y
CONFIG_NF_LOG_ARP=y
CONFIG_NF_LOG_IPV4=y
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_SNMP_BASIC=y
CONFIG_NF_NAT_PPTP=y
CONFIG_NF_NAT_H323=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_RPFILTER=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_TARGET_SYNPROXY=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_TARGET_CLUSTERIP=y
CONFIG_IP_NF_TARGET_ECN=y
CONFIG_IP_NF_TARGET_TTL=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_SECURITY=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
# end of IP: Netfilter Configuration
#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=y
CONFIG_NF_TPROXY_IPV6=y
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=y
CONFIG_NFT_DUP_IPV6=y
CONFIG_NFT_FIB_IPV6=y
CONFIG_NF_DUP_IPV6=y
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_AH=y
CONFIG_IP6_NF_MATCH_EUI64=y
CONFIG_IP6_NF_MATCH_FRAG=y
CONFIG_IP6_NF_MATCH_OPTS=y
CONFIG_IP6_NF_MATCH_HL=y
CONFIG_IP6_NF_MATCH_IPV6HEADER=y
CONFIG_IP6_NF_MATCH_MH=y
CONFIG_IP6_NF_MATCH_RPFILTER=y
CONFIG_IP6_NF_MATCH_RT=y
CONFIG_IP6_NF_MATCH_SRH=y
CONFIG_IP6_NF_TARGET_HL=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_TARGET_SYNPROXY=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_SECURITY=y
CONFIG_IP6_NF_NAT=y
CONFIG_IP6_NF_TARGET_MASQUERADE=y
CONFIG_IP6_NF_TARGET_NPT=y
# end of IPv6: Netfilter Configuration
CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=y
CONFIG_NFT_BRIDGE_META=y
CONFIG_NFT_BRIDGE_REJECT=y
CONFIG_NF_CONNTRACK_BRIDGE=y
CONFIG_BRIDGE_NF_EBTABLES=y
CONFIG_BRIDGE_EBT_BROUTE=y
CONFIG_BRIDGE_EBT_T_FILTER=y
CONFIG_BRIDGE_EBT_T_NAT=y
CONFIG_BRIDGE_EBT_802_3=y
CONFIG_BRIDGE_EBT_AMONG=y
CONFIG_BRIDGE_EBT_ARP=y
CONFIG_BRIDGE_EBT_IP=y
CONFIG_BRIDGE_EBT_IP6=y
CONFIG_BRIDGE_EBT_LIMIT=y
CONFIG_BRIDGE_EBT_MARK=y
CONFIG_BRIDGE_EBT_PKTTYPE=y
CONFIG_BRIDGE_EBT_STP=y
CONFIG_BRIDGE_EBT_VLAN=y
CONFIG_BRIDGE_EBT_ARPREPLY=y
CONFIG_BRIDGE_EBT_DNAT=y
CONFIG_BRIDGE_EBT_MARK_T=y
CONFIG_BRIDGE_EBT_REDIRECT=y
CONFIG_BRIDGE_EBT_SNAT=y
CONFIG_BRIDGE_EBT_LOG=y
CONFIG_BRIDGE_EBT_NFLOG=y
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=y
CONFIG_IP_DCCP=y
CONFIG_INET_DCCP_DIAG=y
#
# DCCP CCIDs Configuration
#
CONFIG_IP_DCCP_CCID2_DEBUG=y
CONFIG_IP_DCCP_CCID3=y
CONFIG_IP_DCCP_CCID3_DEBUG=y
CONFIG_IP_DCCP_TFRC_LIB=y
CONFIG_IP_DCCP_TFRC_DEBUG=y
# end of DCCP CCIDs Configuration
#
# DCCP Kernel Hacking
#
CONFIG_IP_DCCP_DEBUG=y
# end of DCCP Kernel Hacking
CONFIG_IP_SCTP=y
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=y
CONFIG_RDS=y
CONFIG_RDS_RDMA=y
CONFIG_RDS_TCP=y
CONFIG_RDS_DEBUG=y
CONFIG_TIPC=y
CONFIG_TIPC_MEDIA_IB=y
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=y
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
CONFIG_ATM_CLIP_NO_ICMP=y
CONFIG_ATM_LANE=y
CONFIG_ATM_MPOA=y
CONFIG_ATM_BR2684=y
CONFIG_ATM_BR2684_IPFILTER=y
CONFIG_L2TP=y
CONFIG_L2TP_DEBUGFS=y
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=y
CONFIG_L2TP_ETH=y
CONFIG_STP=y
CONFIG_GARP=y
CONFIG_MRP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_TAG_NONE=y
CONFIG_NET_DSA_TAG_AR9331=y
CONFIG_NET_DSA_TAG_BRCM_COMMON=y
CONFIG_NET_DSA_TAG_BRCM=y
CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
CONFIG_NET_DSA_TAG_HELLCREEK=y
CONFIG_NET_DSA_TAG_GSWIP=y
CONFIG_NET_DSA_TAG_DSA_COMMON=y
CONFIG_NET_DSA_TAG_DSA=y
CONFIG_NET_DSA_TAG_EDSA=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_DSA_TAG_KSZ=y
CONFIG_NET_DSA_TAG_OCELOT=y
CONFIG_NET_DSA_TAG_OCELOT_8021Q=y
CONFIG_NET_DSA_TAG_QCA=y
CONFIG_NET_DSA_TAG_RTL4_A=y
CONFIG_NET_DSA_TAG_RTL8_4=y
CONFIG_NET_DSA_TAG_RZN1_A5PSW=y
CONFIG_NET_DSA_TAG_LAN9303=y
CONFIG_NET_DSA_TAG_SJA1105=y
CONFIG_NET_DSA_TAG_TRAILER=y
CONFIG_NET_DSA_TAG_XRS700X=y
CONFIG_VLAN_8021Q=y
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=y
CONFIG_ATALK=y
CONFIG_DEV_APPLETALK=y
CONFIG_COPS=y
CONFIG_COPS_DAYNA=y
CONFIG_COPS_TANGENT=y
CONFIG_IPDDP=y
CONFIG_IPDDP_ENCAP=y
CONFIG_X25=y
CONFIG_LAPB=y
CONFIG_PHONET=y
CONFIG_6LOWPAN=y
CONFIG_6LOWPAN_DEBUGFS=y
CONFIG_6LOWPAN_NHC=y
CONFIG_6LOWPAN_NHC_DEST=y
CONFIG_6LOWPAN_NHC_FRAGMENT=y
CONFIG_6LOWPAN_NHC_HOP=y
CONFIG_6LOWPAN_NHC_IPV6=y
CONFIG_6LOWPAN_NHC_MOBILITY=y
CONFIG_6LOWPAN_NHC_ROUTING=y
CONFIG_6LOWPAN_NHC_UDP=y
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=y
CONFIG_6LOWPAN_GHC_UDP=y
CONFIG_6LOWPAN_GHC_ICMPV6=y
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=y
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=y
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=y
CONFIG_IEEE802154=y
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=y
CONFIG_IEEE802154_6LOWPAN=y
CONFIG_MAC802154=y
CONFIG_NET_SCHED=y
#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_HFSC=y
CONFIG_NET_SCH_ATM=y
CONFIG_NET_SCH_PRIO=y
CONFIG_NET_SCH_MULTIQ=y
CONFIG_NET_SCH_RED=y
CONFIG_NET_SCH_SFB=y
CONFIG_NET_SCH_SFQ=y
CONFIG_NET_SCH_TEQL=y
CONFIG_NET_SCH_TBF=y
CONFIG_NET_SCH_CBS=y
CONFIG_NET_SCH_ETF=y
CONFIG_NET_SCH_TAPRIO=y
CONFIG_NET_SCH_GRED=y
CONFIG_NET_SCH_DSMARK=y
CONFIG_NET_SCH_NETEM=y
CONFIG_NET_SCH_DRR=y
CONFIG_NET_SCH_MQPRIO=y
CONFIG_NET_SCH_SKBPRIO=y
CONFIG_NET_SCH_CHOKE=y
CONFIG_NET_SCH_QFQ=y
CONFIG_NET_SCH_CODEL=y
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=y
CONFIG_NET_SCH_FQ=y
CONFIG_NET_SCH_HHF=y
CONFIG_NET_SCH_PIE=y
CONFIG_NET_SCH_FQ_PIE=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_SCH_PLUG=y
CONFIG_NET_SCH_ETS=y
CONFIG_NET_SCH_DEFAULT=y
# CONFIG_DEFAULT_FQ is not set
# CONFIG_DEFAULT_CODEL is not set
# CONFIG_DEFAULT_FQ_CODEL is not set
# CONFIG_DEFAULT_FQ_PIE is not set
# CONFIG_DEFAULT_SFQ is not set
CONFIG_DEFAULT_PFIFO_FAST=y
CONFIG_DEFAULT_NET_SCH="pfifo_fast"
#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=y
CONFIG_NET_CLS_TCINDEX=y
CONFIG_NET_CLS_ROUTE4=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=y
CONFIG_NET_CLS_RSVP6=y
CONFIG_NET_CLS_FLOW=y
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_CLS_FLOWER=y
CONFIG_NET_CLS_MATCHALL=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=y
CONFIG_NET_EMATCH_NBYTE=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_EMATCH_META=y
CONFIG_NET_EMATCH_TEXT=y
CONFIG_NET_EMATCH_CANID=y
CONFIG_NET_EMATCH_IPSET=y
CONFIG_NET_EMATCH_IPT=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=y
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=y
CONFIG_NET_ACT_SAMPLE=y
CONFIG_NET_ACT_IPT=y
CONFIG_NET_ACT_NAT=y
CONFIG_NET_ACT_PEDIT=y
CONFIG_NET_ACT_SIMP=y
CONFIG_NET_ACT_SKBEDIT=y
CONFIG_NET_ACT_CSUM=y
CONFIG_NET_ACT_MPLS=y
CONFIG_NET_ACT_VLAN=y
CONFIG_NET_ACT_BPF=y
CONFIG_NET_ACT_CONNMARK=y
CONFIG_NET_ACT_CTINFO=y
CONFIG_NET_ACT_SKBMOD=y
CONFIG_NET_ACT_IFE=y
CONFIG_NET_ACT_TUNNEL_KEY=y
CONFIG_NET_ACT_CT=y
CONFIG_NET_ACT_GATE=y
CONFIG_NET_IFE_SKBMARK=y
CONFIG_NET_IFE_SKBPRIO=y
CONFIG_NET_IFE_SKBTCINDEX=y
CONFIG_NET_TC_SKB_EXT=y
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=y
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
CONFIG_BATMAN_ADV_DEBUG=y
CONFIG_BATMAN_ADV_TRACING=y
CONFIG_OPENVSWITCH=y
CONFIG_OPENVSWITCH_GRE=y
CONFIG_OPENVSWITCH_VXLAN=y
CONFIG_OPENVSWITCH_GENEVE=y
CONFIG_VSOCKETS=y
CONFIG_VSOCKETS_DIAG=y
CONFIG_VSOCKETS_LOOPBACK=y
CONFIG_VMWARE_VMCI_VSOCKETS=y
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_VIRTIO_VSOCKETS_COMMON=y
CONFIG_HYPERV_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=y
CONFIG_MPLS_ROUTING=y
CONFIG_MPLS_IPTUNNEL=y
CONFIG_NET_NSH=y
CONFIG_HSR=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=y
CONFIG_QRTR_SMD=y
CONFIG_QRTR_TUN=y
CONFIG_QRTR_MHI=y
CONFIG_NET_NCSI=y
CONFIG_NCSI_OEM_CMD_GET_MAC=y
CONFIG_NCSI_OEM_CMD_KEEP_PHY=y
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y
#
# Network testing
#
CONFIG_NET_PKTGEN=y
CONFIG_NET_DROP_MONITOR=y
# end of Network testing
# end of Networking options
CONFIG_HAMRADIO=y
#
# Packet Radio protocols
#
CONFIG_AX25=y
CONFIG_AX25_DAMA_SLAVE=y
CONFIG_NETROM=y
CONFIG_ROSE=y
#
# AX.25 network device drivers
#
CONFIG_MKISS=y
CONFIG_6PACK=y
CONFIG_BPQETHER=y
CONFIG_SCC=y
CONFIG_SCC_DELAY=y
CONFIG_SCC_TRXECHO=y
CONFIG_BAYCOM_SER_FDX=y
CONFIG_BAYCOM_SER_HDX=y
CONFIG_BAYCOM_PAR=y
CONFIG_BAYCOM_EPP=y
CONFIG_YAM=y
# end of AX.25 network device drivers
CONFIG_CAN=y
CONFIG_CAN_RAW=y
CONFIG_CAN_BCM=y
CONFIG_CAN_GW=y
CONFIG_CAN_J1939=y
CONFIG_CAN_ISOTP=y
CONFIG_BT=y
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_CMTP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=y
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
CONFIG_BT_AOSPEXT=y
CONFIG_BT_DEBUGFS=y
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y
#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=y
CONFIG_BT_BCM=y
CONFIG_BT_RTL=y
CONFIG_BT_QCA=y
CONFIG_BT_MTK=y
CONFIG_BT_HCIBTUSB=y
CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=y
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=y
CONFIG_BT_HCIBCM4377=y
CONFIG_BT_HCIBPA10X=y
CONFIG_BT_HCIBFUSB=y
CONFIG_BT_HCIDTL1=y
CONFIG_BT_HCIBT3C=y
CONFIG_BT_HCIBLUECARD=y
CONFIG_BT_HCIVHCI=y
CONFIG_BT_MRVL=y
CONFIG_BT_MRVL_SDIO=y
CONFIG_BT_ATH3K=y
CONFIG_BT_MTKSDIO=y
CONFIG_BT_MTKUART=y
CONFIG_BT_HCIRSI=y
CONFIG_BT_VIRTIO=y
# end of Bluetooth device drivers
CONFIG_AF_RXRPC=y
CONFIG_AF_RXRPC_IPV6=y
CONFIG_AF_RXRPC_INJECT_LOSS=y
CONFIG_AF_RXRPC_DEBUG=y
CONFIG_RXKAD=y
CONFIG_RXPERF=y
CONFIG_AF_KCM=y
CONFIG_STREAM_PARSER=y
CONFIG_MCTP=y
CONFIG_MCTP_TEST=y
CONFIG_MCTP_FLOWS=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=y
CONFIG_NL80211_TESTMODE=y
CONFIG_CFG80211_DEVELOPER_WARNINGS=y
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=y
CONFIG_LIB80211_CRYPT_WEP=y
CONFIG_LIB80211_CRYPT_CCMP=y
CONFIG_LIB80211_CRYPT_TKIP=y
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=y
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
CONFIG_MAC80211_MESSAGE_TRACING=y
CONFIG_MAC80211_DEBUG_MENU=y
CONFIG_MAC80211_NOINLINE=y
CONFIG_MAC80211_VERBOSE_DEBUG=y
CONFIG_MAC80211_MLME_DEBUG=y
CONFIG_MAC80211_STA_DEBUG=y
CONFIG_MAC80211_HT_DEBUG=y
CONFIG_MAC80211_OCB_DEBUG=y
CONFIG_MAC80211_IBSS_DEBUG=y
CONFIG_MAC80211_PS_DEBUG=y
CONFIG_MAC80211_MPL_DEBUG=y
CONFIG_MAC80211_MPATH_DEBUG=y
CONFIG_MAC80211_MHWMP_DEBUG=y
CONFIG_MAC80211_MESH_SYNC_DEBUG=y
CONFIG_MAC80211_MESH_CSA_DEBUG=y
CONFIG_MAC80211_MESH_PS_DEBUG=y
CONFIG_MAC80211_TDLS_DEBUG=y
CONFIG_MAC80211_DEBUG_COUNTERS=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
CONFIG_NET_9P=y
CONFIG_NET_9P_FD=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_NET_9P_RDMA=y
CONFIG_NET_9P_DEBUG=y
CONFIG_CAIF=y
CONFIG_CAIF_DEBUG=y
CONFIG_CAIF_NETDEV=y
CONFIG_CAIF_USB=y
CONFIG_CEPH_LIB=y
CONFIG_CEPH_LIB_PRETTYDEBUG=y
CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
CONFIG_NFC=y
CONFIG_NFC_DIGITAL=y
CONFIG_NFC_NCI=y
CONFIG_NFC_NCI_SPI=y
CONFIG_NFC_NCI_UART=y
CONFIG_NFC_HCI=y
CONFIG_NFC_SHDLC=y
#
# Near Field Communication (NFC) devices
#
CONFIG_NFC_TRF7970A=y
CONFIG_NFC_MEI_PHY=y
CONFIG_NFC_SIM=y
CONFIG_NFC_PORT100=y
CONFIG_NFC_VIRTUAL_NCI=y
CONFIG_NFC_FDP=y
CONFIG_NFC_FDP_I2C=y
CONFIG_NFC_PN544=y
CONFIG_NFC_PN544_I2C=y
CONFIG_NFC_PN544_MEI=y
CONFIG_NFC_PN533=y
CONFIG_NFC_PN533_USB=y
CONFIG_NFC_PN533_I2C=y
CONFIG_NFC_PN532_UART=y
CONFIG_NFC_MICROREAD=y
CONFIG_NFC_MICROREAD_I2C=y
CONFIG_NFC_MICROREAD_MEI=y
CONFIG_NFC_MRVL=y
CONFIG_NFC_MRVL_USB=y
CONFIG_NFC_MRVL_UART=y
CONFIG_NFC_MRVL_I2C=y
CONFIG_NFC_MRVL_SPI=y
CONFIG_NFC_ST21NFCA=y
CONFIG_NFC_ST21NFCA_I2C=y
CONFIG_NFC_ST_NCI=y
CONFIG_NFC_ST_NCI_I2C=y
CONFIG_NFC_ST_NCI_SPI=y
CONFIG_NFC_NXP_NCI=y
CONFIG_NFC_NXP_NCI_I2C=y
CONFIG_NFC_S3FWRN5=y
CONFIG_NFC_S3FWRN5_I2C=y
CONFIG_NFC_S3FWRN82_UART=y
CONFIG_NFC_ST95HF=y
# end of Near Field Communication (NFC) devices
CONFIG_PSAMPLE=y
CONFIG_NET_IFE=y
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=y
CONFIG_ETHTOOL_NETLINK=y
CONFIG_NETDEV_ADDR_LIST_TEST=y
#
# Device Drivers
#
CONFIG_HAVE_EISA=y
CONFIG_EISA=y
CONFIG_EISA_VLB_PRIMING=y
CONFIG_EISA_PCI_EISA=y
CONFIG_EISA_VIRTUAL_ROOT=y
CONFIG_EISA_NAMES=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_DPC=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_EDR=y
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
CONFIG_PCI_STUB=y
CONFIG_PCI_PF_STUB=y
CONFIG_PCI_ATS=y
CONFIG_PCI_DOE=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_LOCKLESS_CONFIG=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_COMPAQ=y
CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM=y
CONFIG_HOTPLUG_PCI_IBM=y
CONFIG_HOTPLUG_PCI_ACPI=y
CONFIG_HOTPLUG_PCI_ACPI_IBM=y
CONFIG_HOTPLUG_PCI_CPCI=y
CONFIG_HOTPLUG_PCI_CPCI_ZT5550=y
CONFIG_HOTPLUG_PCI_CPCI_GENERIC=y
CONFIG_HOTPLUG_PCI_SHPC=y
#
# PCI controller drivers
#
CONFIG_PCI_FTPCI100=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCIE_XILINX=y
CONFIG_PCIE_MICROCHIP_HOST=y
#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_INTEL_GW=y
CONFIG_PCI_MESON=y
# end of DesignWare PCI Core Support
#
# Mobiveil PCIe Core Support
#
# end of Mobiveil PCIe Core Support
#
# Cadence PCIe controllers support
#
CONFIG_PCIE_CADENCE=y
CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_CADENCE_EP=y
CONFIG_PCIE_CADENCE_PLAT=y
CONFIG_PCIE_CADENCE_PLAT_HOST=y
CONFIG_PCIE_CADENCE_PLAT_EP=y
CONFIG_PCI_J721E=y
CONFIG_PCI_J721E_HOST=y
CONFIG_PCI_J721E_EP=y
# end of Cadence PCIe controllers support
# end of PCI controller drivers
#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=y
CONFIG_PCI_EPF_NTB=y
CONFIG_PCI_EPF_VNTB=y
# end of PCI Endpoint
#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=y
# end of PCI switch controller drivers
CONFIG_CXL_BUS=y
CONFIG_CXL_PCI=y
CONFIG_CXL_MEM_RAW_COMMANDS=y
CONFIG_CXL_ACPI=y
CONFIG_CXL_MEM=y
CONFIG_CXL_PORT=y
CONFIG_CXL_SUSPEND=y
CONFIG_PCCARD=y
CONFIG_PCMCIA=y
CONFIG_PCMCIA_LOAD_CIS=y
CONFIG_CARDBUS=y
#
# PC-card bridges
#
CONFIG_YENTA=y
CONFIG_YENTA_O2=y
CONFIG_YENTA_RICOH=y
CONFIG_YENTA_TI=y
CONFIG_YENTA_ENE_TUNE=y
CONFIG_YENTA_TOSHIBA=y
CONFIG_PD6729=y
CONFIG_I82092=y
CONFIG_I82365=y
CONFIG_TCIC=y
CONFIG_PCMCIA_PROBE=y
CONFIG_PCCARD_NONSTATIC=y
CONFIG_RAPIDIO=y
CONFIG_RAPIDIO_TSI721=y
CONFIG_RAPIDIO_DISC_TIMEOUT=30
CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
CONFIG_RAPIDIO_DMA_ENGINE=y
CONFIG_RAPIDIO_DEBUG=y
CONFIG_RAPIDIO_ENUM_BASIC=y
CONFIG_RAPIDIO_CHMAN=y
CONFIG_RAPIDIO_MPORT_CDEV=y
#
# RapidIO Switch drivers
#
CONFIG_RAPIDIO_CPS_XX=y
CONFIG_RAPIDIO_CPS_GEN2=y
CONFIG_RAPIDIO_RXS_GEN3=y
# end of RapidIO Switch drivers
#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DEVTMPFS_SAFE=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
CONFIG_FW_CACHE=y
CONFIG_FW_UPLOAD=y
# end of Firmware loader
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
CONFIG_DEBUG_DRIVER=y
CONFIG_DEBUG_DEVRES=y
CONFIG_DEBUG_TEST_DRIVER_REMOVE=y
CONFIG_PM_QOS_KUNIT_TEST=y
CONFIG_TEST_ASYNC_DRIVER_PROBE=m
CONFIG_DRIVER_PE_KUNIT_TEST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SLIMBUS=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_W1=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SOUNDWIRE=y
CONFIG_REGMAP_SOUNDWIRE_MBQ=y
CONFIG_REGMAP_SCCB=y
CONFIG_REGMAP_I3C=y
CONFIG_REGMAP_SPI_AVMM=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_FENCE_TRACE=y
# end of Generic Driver Options
#
# Bus devices
#
CONFIG_MOXTET=y
CONFIG_MHI_BUS=y
CONFIG_MHI_BUS_DEBUG=y
CONFIG_MHI_BUS_PCI_GENERIC=y
CONFIG_MHI_BUS_EP=y
# end of Bus devices
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
#
# Firmware Drivers
#
#
# ARM System Control and Management Interface Protocol
#
# end of ARM System Control and Management Interface Protocol
CONFIG_EDD=y
CONFIG_EDD_OFF=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
CONFIG_ISCSI_IBFT_FIND=y
CONFIG_ISCSI_IBFT=y
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_SYSFB=y
CONFIG_SYSFB_SIMPLEFB=y
CONFIG_FW_CS_DSP=y
CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_SMI=y
CONFIG_GOOGLE_CBMEM=y
CONFIG_GOOGLE_COREBOOT_TABLE=y
CONFIG_GOOGLE_MEMCONSOLE=y
CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=y
CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y
CONFIG_GOOGLE_VPD=y
#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_BOOTLOADER_CONTROL=y
CONFIG_EFI_CAPSULE_LOADER=y
CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
CONFIG_EFI_TEST=y
CONFIG_EFI_DEV_PATH_PARSER=y
CONFIG_APPLE_PROPERTIES=y
CONFIG_RESET_ATTACK_MITIGATION=y
CONFIG_EFI_RCI2_TABLE=y
CONFIG_EFI_DISABLE_PCI_DMA=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
CONFIG_EFI_DISABLE_RUNTIME=y
CONFIG_EFI_COCO_SECRET=y
CONFIG_EFI_EMBEDDED_FIRMWARE=y
# end of EFI (Extensible Firmware Interface) Support
CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_X86=y
#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers
CONFIG_GNSS=y
CONFIG_GNSS_SERIAL=y
CONFIG_GNSS_MTK_SERIAL=y
CONFIG_GNSS_SIRF_SERIAL=y
CONFIG_GNSS_UBX_SERIAL=y
CONFIG_GNSS_USB=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
#
# Partition parsers
#
CONFIG_MTD_AR7_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
# end of Partition parsers
#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
CONFIG_FTL=y
CONFIG_NFTL=y
CONFIG_NFTL_RW=y
CONFIG_INFTL=y
CONFIG_RFD_FTL=y
CONFIG_SSFDC=y
CONFIG_SM_FTL=y
CONFIG_MTD_OOPS=y
CONFIG_MTD_PSTORE=y
CONFIG_MTD_SWAP=y
CONFIG_MTD_PARTITIONED_MASTER=y
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_MAP_BANK_WIDTH_8=y
CONFIG_MTD_MAP_BANK_WIDTH_16=y
CONFIG_MTD_MAP_BANK_WIDTH_32=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_I8=y
CONFIG_MTD_OTP=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_ABSENT=y
# end of RAM/ROM/Flash chip drivers
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_COMPAT=y
CONFIG_MTD_PHYSMAP_START=0x8000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_PHYSMAP_VERSATILE=y
CONFIG_MTD_PHYSMAP_GEMINI=y
CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
CONFIG_MTD_SBC_GXX=y
CONFIG_MTD_SCx200_DOCFLASH=y
CONFIG_MTD_AMD76XROM=y
CONFIG_MTD_ICHXROM=y
CONFIG_MTD_ESB2ROM=y
CONFIG_MTD_CK804XROM=y
CONFIG_MTD_SCB2_FLASH=y
CONFIG_MTD_NETtel=y
CONFIG_MTD_L440GX=y
CONFIG_MTD_PCI=y
CONFIG_MTD_PCMCIA=y
CONFIG_MTD_PCMCIA_ANONYMOUS=y
CONFIG_MTD_INTEL_VR_NOR=y
CONFIG_MTD_PLATRAM=y
# end of Mapping drivers for chip access
#
# Self-contained MTD device drivers
#
CONFIG_MTD_PMC551=y
CONFIG_MTD_PMC551_BUGFIX=y
CONFIG_MTD_PMC551_DEBUG=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
CONFIG_MTD_DATAFLASH_OTP=y
CONFIG_MTD_MCHP23K256=y
CONFIG_MTD_MCHP48L640=y
CONFIG_MTD_SST25L=y
CONFIG_MTD_SLRAM=y
CONFIG_MTD_PHRAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128
CONFIG_MTD_BLOCK2MTD=y
#
# Disk-On-Chip Device Drivers
#
CONFIG_MTD_DOCG3=y
CONFIG_BCH_CONST_M=14
CONFIG_BCH_CONST_T=4
# end of Self-contained MTD device drivers
#
# NAND
#
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y
CONFIG_MTD_ONENAND_OTP=y
CONFIG_MTD_ONENAND_2X_PROGRAM=y
CONFIG_MTD_RAW_NAND=y
#
# Raw/parallel NAND flash controllers
#
CONFIG_MTD_NAND_DENALI=y
CONFIG_MTD_NAND_DENALI_PCI=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_CAFE=y
CONFIG_MTD_NAND_CS553X=y
CONFIG_MTD_NAND_MXIC=y
CONFIG_MTD_NAND_GPIO=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_CADENCE=y
CONFIG_MTD_NAND_ARASAN=y
CONFIG_MTD_NAND_INTEL_LGM=y
#
# Misc
#
CONFIG_MTD_SM_COMMON=y
CONFIG_MTD_NAND_NANDSIM=y
CONFIG_MTD_NAND_RICOH=y
CONFIG_MTD_NAND_DISKONCHIP=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
CONFIG_MTD_SPI_NAND=y
#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_MXIC=y
# end of ECC engine support
# end of NAND
#
# LPDDR & LPDDR2 PCM memory drivers
#
CONFIG_MTD_LPDDR=y
CONFIG_MTD_QINFO_PROBE=y
# end of LPDDR & LPDDR2 PCM memory drivers
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_HYPERBUS=y
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_OF_UNITTEST=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_PROMTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y
CONFIG_PARPORT_SERIAL=y
CONFIG_PARPORT_PC_FIFO=y
CONFIG_PARPORT_PC_SUPERIO=y
CONFIG_PARPORT_PC_PCMCIA=y
CONFIG_PARPORT_AX88796=y
CONFIG_PARPORT_1284=y
CONFIG_PARPORT_NOT_PC=y
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y
#
# Protocols
#
CONFIG_ISAPNP=y
CONFIG_PNPBIOS=y
CONFIG_PNPBIOS_PROC_FS=y
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=y
CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y
CONFIG_BLK_DEV_FD=y
CONFIG_BLK_DEV_FD_RAWCMD=y
CONFIG_CDROM=y
CONFIG_PARIDE=y
#
# Parallel IDE high-level drivers
#
CONFIG_PARIDE_PD=y
CONFIG_PARIDE_PCD=y
CONFIG_PARIDE_PF=y
CONFIG_PARIDE_PT=y
CONFIG_PARIDE_PG=y
#
# Parallel IDE protocol modules
#
CONFIG_PARIDE_ATEN=y
CONFIG_PARIDE_BPCK=y
CONFIG_PARIDE_BPCK6=y
CONFIG_PARIDE_COMM=y
CONFIG_PARIDE_DSTR=y
CONFIG_PARIDE_FIT2=y
CONFIG_PARIDE_FIT3=y
CONFIG_PARIDE_EPAT=y
CONFIG_PARIDE_EPATC8=y
CONFIG_PARIDE_EPIA=y
CONFIG_PARIDE_FRIQ=y
CONFIG_PARIDE_FRPW=y
CONFIG_PARIDE_KBIC=y
CONFIG_PARIDE_KTTI=y
CONFIG_PARIDE_ON20=y
CONFIG_PARIDE_ON26=y
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
CONFIG_ZRAM=y
CONFIG_ZRAM_DEF_COMP_LZORLE=y
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="lzo-rle"
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
CONFIG_ZRAM_MULTI_COMP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_DRBD=y
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_ATA_OVER_ETH=y
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_RBD=y
CONFIG_BLK_DEV_UBLK=y
CONFIG_BLK_DEV_RNBD=y
CONFIG_BLK_DEV_RNBD_CLIENT=y
CONFIG_BLK_DEV_RNBD_SERVER=y
#
# NVME Support
#
CONFIG_NVME_COMMON=y
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
CONFIG_NVME_MULTIPATH=y
CONFIG_NVME_VERBOSE_ERRORS=y
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=y
CONFIG_NVME_RDMA=y
CONFIG_NVME_FC=y
CONFIG_NVME_TCP=y
CONFIG_NVME_AUTH=y
CONFIG_NVME_TARGET=y
CONFIG_NVME_TARGET_PASSTHRU=y
CONFIG_NVME_TARGET_LOOP=y
CONFIG_NVME_TARGET_RDMA=y
CONFIG_NVME_TARGET_FC=y
CONFIG_NVME_TARGET_FCLOOP=y
CONFIG_NVME_TARGET_TCP=y
CONFIG_NVME_TARGET_AUTH=y
# end of NVME Support
#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=y
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
CONFIG_AD525X_DPOT_SPI=y
CONFIG_DUMMY_IRQ=y
CONFIG_IBM_ASM=y
CONFIG_PHANTOM=y
CONFIG_TIFM_CORE=y
CONFIG_TIFM_7XX1=y
CONFIG_ICS932S401=y
CONFIG_ENCLOSURE_SERVICES=y
CONFIG_SMPRO_ERRMON=y
CONFIG_SMPRO_MISC=y
CONFIG_CS5535_MFGPT=y
CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
CONFIG_CS5535_CLOCK_EVENT_SRC=y
CONFIG_HI6421V600_IRQ=y
CONFIG_HP_ILO=y
CONFIG_APDS9802ALS=y
CONFIG_ISL29003=y
CONFIG_ISL29020=y
CONFIG_SENSORS_TSL2550=y
CONFIG_SENSORS_BH1770=y
CONFIG_SENSORS_APDS990X=y
CONFIG_HMC6352=y
CONFIG_DS1682=y
CONFIG_VMWARE_BALLOON=y
CONFIG_PCH_PHUB=y
CONFIG_LATTICE_ECP3_CONFIG=y
CONFIG_SRAM=y
CONFIG_DW_XDATA_PCIE=y
CONFIG_PCI_ENDPOINT_TEST=y
CONFIG_XILINX_SDFEC=y
CONFIG_MISC_RTSX=y
CONFIG_HISI_HIKEY_USB=y
CONFIG_OPEN_DICE=y
CONFIG_VCPU_STALL_DETECTOR=y
CONFIG_C2PORT=y
CONFIG_C2PORT_DURAMAR_2150=y
#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_EEPROM_LEGACY=y
CONFIG_EEPROM_MAX6875=y
CONFIG_EEPROM_93CX6=y
CONFIG_EEPROM_93XX46=y
CONFIG_EEPROM_IDT_89HPESX=y
CONFIG_EEPROM_EE1004=y
# end of EEPROM support
CONFIG_CB710_CORE=y
CONFIG_CB710_DEBUG=y
CONFIG_CB710_DEBUG_ASSUMPTIONS=y
#
# Texas Instruments shared transport line discipline
#
CONFIG_TI_ST=y
# end of Texas Instruments shared transport line discipline
CONFIG_SENSORS_LIS3_I2C=y
CONFIG_ALTERA_STAPL=y
CONFIG_INTEL_MEI=y
CONFIG_INTEL_MEI_ME=y
CONFIG_INTEL_MEI_TXE=y
CONFIG_INTEL_MEI_GSC=y
CONFIG_INTEL_MEI_HDCP=y
CONFIG_INTEL_MEI_PXP=y
CONFIG_VMWARE_VMCI=y
CONFIG_ECHO=y
CONFIG_BCM_VK=y
CONFIG_BCM_VK_TTY=y
CONFIG_MISC_ALCOR_PCI=y
CONFIG_MISC_RTSX_PCI=y
CONFIG_MISC_RTSX_USB=y
# CONFIG_HABANA_AI is not set
CONFIG_UACCE=y
CONFIG_PVPANIC=y
CONFIG_PVPANIC_MMIO=y
CONFIG_PVPANIC_PCI=y
CONFIG_GP_PCI1XXXX=y
# end of Misc devices
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=y
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_NETLINK=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_BLK_DEV_BSG=y
CONFIG_CHR_DEV_SCH=y
CONFIG_SCSI_ENCLOSURE=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
CONFIG_SCSI_FC_ATTRS=y
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SRP_ATTRS=y
# end of SCSI Transports
CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=y
CONFIG_ISCSI_BOOT_SYSFS=y
CONFIG_SCSI_CXGB3_ISCSI=y
CONFIG_SCSI_CXGB4_ISCSI=y
CONFIG_SCSI_BNX2_ISCSI=y
CONFIG_SCSI_BNX2X_FCOE=y
CONFIG_BE2ISCSI=y
CONFIG_BLK_DEV_3W_XXXX_RAID=y
CONFIG_SCSI_HPSA=y
CONFIG_SCSI_3W_9XXX=y
CONFIG_SCSI_3W_SAS=y
CONFIG_SCSI_ACARD=y
CONFIG_SCSI_AHA152X=y
CONFIG_SCSI_AHA1542=y
CONFIG_SCSI_AHA1740=y
CONFIG_SCSI_AACRAID=y
CONFIG_SCSI_AIC7XXX=y
CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
CONFIG_AIC7XXX_RESET_DELAY_MS=5000
CONFIG_AIC7XXX_DEBUG_ENABLE=y
CONFIG_AIC7XXX_DEBUG_MASK=0
CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
CONFIG_SCSI_AIC79XX=y
CONFIG_AIC79XX_CMDS_PER_DEVICE=32
CONFIG_AIC79XX_RESET_DELAY_MS=5000
CONFIG_AIC79XX_DEBUG_ENABLE=y
CONFIG_AIC79XX_DEBUG_MASK=0
CONFIG_AIC79XX_REG_PRETTY_PRINT=y
CONFIG_SCSI_AIC94XX=y
CONFIG_AIC94XX_DEBUG=y
CONFIG_SCSI_MVSAS=y
CONFIG_SCSI_MVSAS_DEBUG=y
CONFIG_SCSI_MVSAS_TASKLET=y
CONFIG_SCSI_MVUMI=y
CONFIG_SCSI_ADVANSYS=y
CONFIG_SCSI_ARCMSR=y
CONFIG_SCSI_ESAS2R=y
CONFIG_MEGARAID_NEWGEN=y
CONFIG_MEGARAID_MM=y
CONFIG_MEGARAID_MAILBOX=y
CONFIG_MEGARAID_LEGACY=y
CONFIG_MEGARAID_SAS=y
CONFIG_SCSI_MPT3SAS=y
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
CONFIG_SCSI_MPT3SAS_MAX_SGE=128
CONFIG_SCSI_MPT2SAS=y
CONFIG_SCSI_MPI3MR=y
CONFIG_SCSI_SMARTPQI=y
CONFIG_SCSI_HPTIOP=y
CONFIG_SCSI_BUSLOGIC=y
CONFIG_SCSI_FLASHPOINT=y
CONFIG_SCSI_MYRB=y
CONFIG_SCSI_MYRS=y
CONFIG_VMWARE_PVSCSI=y
CONFIG_HYPERV_STORAGE=y
CONFIG_LIBFC=y
CONFIG_LIBFCOE=y
CONFIG_FCOE=y
CONFIG_FCOE_FNIC=y
CONFIG_SCSI_SNIC=y
CONFIG_SCSI_SNIC_DEBUG_FS=y
CONFIG_SCSI_DMX3191D=y
CONFIG_SCSI_FDOMAIN=y
CONFIG_SCSI_FDOMAIN_PCI=y
CONFIG_SCSI_FDOMAIN_ISA=y
CONFIG_SCSI_ISCI=y
CONFIG_SCSI_GENERIC_NCR5380=y
CONFIG_SCSI_IPS=y
CONFIG_SCSI_INITIO=y
CONFIG_SCSI_INIA100=y
CONFIG_SCSI_PPA=y
CONFIG_SCSI_IMM=y
CONFIG_SCSI_IZIP_EPP16=y
CONFIG_SCSI_IZIP_SLOW_CTR=y
CONFIG_SCSI_STEX=y
CONFIG_SCSI_SYM53C8XX_2=y
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
CONFIG_SCSI_SYM53C8XX_MMIO=y
CONFIG_SCSI_IPR=y
CONFIG_SCSI_IPR_TRACE=y
CONFIG_SCSI_IPR_DUMP=y
CONFIG_SCSI_QLOGIC_FAS=y
CONFIG_SCSI_QLOGIC_1280=y
CONFIG_SCSI_QLA_FC=y
CONFIG_TCM_QLA2XXX=y
CONFIG_TCM_QLA2XXX_DEBUG=y
CONFIG_SCSI_QLA_ISCSI=y
CONFIG_QEDI=y
CONFIG_QEDF=y
CONFIG_SCSI_LPFC=y
CONFIG_SCSI_LPFC_DEBUG_FS=y
CONFIG_SCSI_EFCT=y
CONFIG_SCSI_SIM710=y
CONFIG_SCSI_DC395x=y
CONFIG_SCSI_AM53C974=y
CONFIG_SCSI_NSP32=y
CONFIG_SCSI_WD719X=y
CONFIG_SCSI_DEBUG=y
CONFIG_SCSI_PMCRAID=y
CONFIG_SCSI_PM8001=y
CONFIG_SCSI_BFA_FC=y
CONFIG_SCSI_VIRTIO=y
CONFIG_SCSI_CHELSIO_FCOE=y
CONFIG_SCSI_LOWLEVEL_PCMCIA=y
CONFIG_PCMCIA_AHA152X=m
CONFIG_PCMCIA_FDOMAIN=m
CONFIG_PCMCIA_NINJA_SCSI=m
CONFIG_PCMCIA_QLOGIC=m
CONFIG_PCMCIA_SYM53C500=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=y
CONFIG_SCSI_DH_HP_SW=y
CONFIG_SCSI_DH_EMC=y
CONFIG_SCSI_DH_ALUA=y
# end of SCSI device support
CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
CONFIG_SATA_ZPODD=y
CONFIG_SATA_PMP=y
#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=y
CONFIG_AHCI_QORIQ=y
CONFIG_SATA_INIC162X=y
CONFIG_SATA_ACARD_AHCI=y
CONFIG_SATA_SIL24=y
CONFIG_ATA_SFF=y
#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=y
CONFIG_SATA_QSTOR=y
CONFIG_SATA_SX4=y
CONFIG_ATA_BMDMA=y
#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
CONFIG_SATA_DWC=y
CONFIG_SATA_DWC_OLD_DMA=y
CONFIG_SATA_MV=y
CONFIG_SATA_NV=y
CONFIG_SATA_PROMISE=y
CONFIG_SATA_SIL=y
CONFIG_SATA_SIS=y
CONFIG_SATA_SVW=y
CONFIG_SATA_ULI=y
CONFIG_SATA_VIA=y
CONFIG_SATA_VITESSE=y
#
# PATA SFF controllers with BMDMA
#
CONFIG_PATA_ALI=y
CONFIG_PATA_AMD=y
CONFIG_PATA_ARTOP=y
CONFIG_PATA_ATIIXP=y
CONFIG_PATA_ATP867X=y
CONFIG_PATA_CMD64X=y
CONFIG_PATA_CS5520=y
CONFIG_PATA_CS5530=y
CONFIG_PATA_CS5535=y
CONFIG_PATA_CS5536=y
CONFIG_PATA_CYPRESS=y
CONFIG_PATA_EFAR=y
CONFIG_PATA_HPT366=y
CONFIG_PATA_HPT37X=y
CONFIG_PATA_HPT3X2N=y
CONFIG_PATA_HPT3X3=y
CONFIG_PATA_HPT3X3_DMA=y
CONFIG_PATA_IT8213=y
CONFIG_PATA_IT821X=y
CONFIG_PATA_JMICRON=y
CONFIG_PATA_MARVELL=y
CONFIG_PATA_NETCELL=y
CONFIG_PATA_NINJA32=y
CONFIG_PATA_NS87415=y
CONFIG_PATA_OLDPIIX=y
CONFIG_PATA_OPTIDMA=y
CONFIG_PATA_PDC2027X=y
CONFIG_PATA_PDC_OLD=y
CONFIG_PATA_RADISYS=y
CONFIG_PATA_RDC=y
CONFIG_PATA_SC1200=y
CONFIG_PATA_SCH=y
CONFIG_PATA_SERVERWORKS=y
CONFIG_PATA_SIL680=y
CONFIG_PATA_SIS=y
CONFIG_PATA_TOSHIBA=y
CONFIG_PATA_TRIFLEX=y
CONFIG_PATA_VIA=y
CONFIG_PATA_WINBOND=y
#
# PIO-only SFF controllers
#
CONFIG_PATA_CMD640_PCI=y
CONFIG_PATA_ISAPNP=y
CONFIG_PATA_MPIIX=y
CONFIG_PATA_NS87410=y
CONFIG_PATA_OPTI=y
CONFIG_PATA_PCMCIA=y
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_OF_PLATFORM=y
CONFIG_PATA_QDI=y
CONFIG_PATA_RZ1000=y
CONFIG_PATA_WINBOND_VLB=y
#
# Generic fallback / legacy drivers
#
CONFIG_PATA_ACPI=y
CONFIG_ATA_GENERIC=y
CONFIG_PATA_LEGACY=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_AUTODETECT=y
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=y
CONFIG_MD_RAID456=y
CONFIG_MD_MULTIPATH=y
CONFIG_MD_FAULTY=y
CONFIG_MD_CLUSTER=y
CONFIG_BCACHE=y
CONFIG_BCACHE_DEBUG=y
CONFIG_BCACHE_CLOSURES_DEBUG=y
CONFIG_BCACHE_ASYNC_REGISTRATION=y
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_DEBUG=y
CONFIG_DM_BUFIO=y
CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y
CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y
CONFIG_DM_BIO_PRISON=y
CONFIG_DM_PERSISTENT_DATA=y
CONFIG_DM_UNSTRIPED=y
CONFIG_DM_CRYPT=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_THIN_PROVISIONING=y
CONFIG_DM_CACHE=y
CONFIG_DM_CACHE_SMQ=y
CONFIG_DM_WRITECACHE=y
CONFIG_DM_ERA=y
CONFIG_DM_CLONE=y
CONFIG_DM_MIRROR=y
CONFIG_DM_LOG_USERSPACE=y
CONFIG_DM_RAID=y
CONFIG_DM_ZERO=y
CONFIG_DM_MULTIPATH=y
CONFIG_DM_MULTIPATH_QL=y
CONFIG_DM_MULTIPATH_ST=y
CONFIG_DM_MULTIPATH_HST=y
CONFIG_DM_MULTIPATH_IOA=y
CONFIG_DM_DELAY=y
CONFIG_DM_DUST=y
CONFIG_DM_INIT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_FLAKEY=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_SWITCH=y
CONFIG_DM_LOG_WRITES=y
CONFIG_DM_INTEGRITY=y
CONFIG_DM_ZONED=y
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=y
CONFIG_TCM_IBLOCK=y
CONFIG_TCM_FILEIO=y
CONFIG_TCM_PSCSI=y
CONFIG_TCM_USER2=y
CONFIG_LOOPBACK_TARGET=y
CONFIG_TCM_FC=y
CONFIG_ISCSI_TARGET=y
CONFIG_ISCSI_TARGET_CXGB4=y
CONFIG_SBP_TARGET=y
CONFIG_FUSION=y
CONFIG_FUSION_SPI=y
CONFIG_FUSION_FC=y
CONFIG_FUSION_SAS=y
CONFIG_FUSION_MAX_SGE=128
CONFIG_FUSION_CTL=y
CONFIG_FUSION_LAN=y
CONFIG_FUSION_LOGGING=y
#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=y
CONFIG_FIREWIRE_OHCI=y
CONFIG_FIREWIRE_SBP2=y
CONFIG_FIREWIRE_NET=y
CONFIG_FIREWIRE_NOSY=y
# end of IEEE 1394 (FireWire) support
CONFIG_MACINTOSH_DRIVERS=y
CONFIG_MAC_EMUMOUSEBTN=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=y
CONFIG_DUMMY=y
CONFIG_WIREGUARD=y
CONFIG_WIREGUARD_DEBUG=y
CONFIG_EQUALIZER=y
CONFIG_NET_FC=y
CONFIG_IFB=y
CONFIG_NET_TEAM=y
CONFIG_NET_TEAM_MODE_BROADCAST=y
CONFIG_NET_TEAM_MODE_ROUNDROBIN=y
CONFIG_NET_TEAM_MODE_RANDOM=y
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=y
CONFIG_NET_TEAM_MODE_LOADBALANCE=y
CONFIG_MACVLAN=y
CONFIG_MACVTAP=y
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=y
CONFIG_IPVTAP=y
CONFIG_VXLAN=y
CONFIG_GENEVE=y
CONFIG_BAREUDP=y
CONFIG_GTP=y
CONFIG_AMT=y
CONFIG_MACSEC=y
CONFIG_NETCONSOLE=y
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_NTB_NETDEV=y
CONFIG_RIONET=y
CONFIG_RIONET_TX_SIZE=128
CONFIG_RIONET_RX_SIZE=128
CONFIG_TUN=y
CONFIG_TAP=y
CONFIG_TUN_VNET_CROSS_LE=y
CONFIG_VETH=y
CONFIG_VIRTIO_NET=y
CONFIG_NLMON=y
CONFIG_NET_VRF=y
CONFIG_VSOCKMON=y
CONFIG_MHI_NET=y
CONFIG_SUNGEM_PHY=y
CONFIG_ARCNET=y
CONFIG_ARCNET_1201=y
CONFIG_ARCNET_1051=y
CONFIG_ARCNET_RAW=y
CONFIG_ARCNET_CAP=y
CONFIG_ARCNET_COM90xx=y
CONFIG_ARCNET_COM90xxIO=y
CONFIG_ARCNET_RIM_I=y
CONFIG_ARCNET_COM20020=y
CONFIG_ARCNET_COM20020_ISA=y
CONFIG_ARCNET_COM20020_PCI=y
CONFIG_ARCNET_COM20020_CS=y
CONFIG_ATM_DRIVERS=y
CONFIG_ATM_DUMMY=y
CONFIG_ATM_TCP=y
CONFIG_ATM_LANAI=y
CONFIG_ATM_ENI=y
CONFIG_ATM_ENI_DEBUG=y
CONFIG_ATM_ENI_TUNE_BURST=y
CONFIG_ATM_ENI_BURST_TX_16W=y
CONFIG_ATM_ENI_BURST_TX_8W=y
CONFIG_ATM_ENI_BURST_TX_4W=y
CONFIG_ATM_ENI_BURST_TX_2W=y
CONFIG_ATM_ENI_BURST_RX_16W=y
CONFIG_ATM_ENI_BURST_RX_8W=y
CONFIG_ATM_ENI_BURST_RX_4W=y
CONFIG_ATM_ENI_BURST_RX_2W=y
CONFIG_ATM_NICSTAR=y
CONFIG_ATM_NICSTAR_USE_SUNI=y
CONFIG_ATM_NICSTAR_USE_IDT77105=y
CONFIG_ATM_IDT77252=y
CONFIG_ATM_IDT77252_DEBUG=y
CONFIG_ATM_IDT77252_RCV_ALL=y
CONFIG_ATM_IDT77252_USE_SUNI=y
CONFIG_ATM_IA=y
CONFIG_ATM_IA_DEBUG=y
CONFIG_ATM_FORE200E=y
CONFIG_ATM_FORE200E_USE_TASKLET=y
CONFIG_ATM_FORE200E_TX_RETRY=16
CONFIG_ATM_FORE200E_DEBUG=0
CONFIG_ATM_HE=y
CONFIG_ATM_HE_USE_SUNI=y
CONFIG_ATM_SOLOS=y
CONFIG_CAIF_DRIVERS=y
CONFIG_CAIF_TTY=y
CONFIG_CAIF_VIRTIO=y
#
# Distributed Switch Architecture drivers
#
CONFIG_B53=y
CONFIG_B53_SPI_DRIVER=y
CONFIG_B53_MDIO_DRIVER=y
CONFIG_B53_MMAP_DRIVER=y
CONFIG_B53_SRAB_DRIVER=y
CONFIG_B53_SERDES=y
CONFIG_NET_DSA_BCM_SF2=y
CONFIG_NET_DSA_LOOP=y
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=y
CONFIG_NET_DSA_LANTIQ_GSWIP=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MV88E6060=y
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=y
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=y
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=y
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=y
CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_MSCC_SEVILLE=y
CONFIG_NET_DSA_AR9331=y
CONFIG_NET_DSA_QCA8K=y
CONFIG_NET_DSA_SJA1105=y
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=y
CONFIG_NET_DSA_XRS700X_I2C=y
CONFIG_NET_DSA_XRS700X_MDIO=y
CONFIG_NET_DSA_REALTEK=y
CONFIG_NET_DSA_REALTEK_MDIO=y
CONFIG_NET_DSA_REALTEK_SMI=y
CONFIG_NET_DSA_REALTEK_RTL8365MB=y
CONFIG_NET_DSA_REALTEK_RTL8366RB=y
CONFIG_NET_DSA_SMSC_LAN9303=y
CONFIG_NET_DSA_SMSC_LAN9303_I2C=y
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=y
CONFIG_NET_DSA_VITESSE_VSC73XX=y
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=y
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=y
# end of Distributed Switch Architecture drivers
CONFIG_ETHERNET=y
CONFIG_MDIO=y
CONFIG_NET_VENDOR_3COM=y
CONFIG_EL3=y
CONFIG_3C515=y
CONFIG_PCMCIA_3C574=y
CONFIG_PCMCIA_3C589=y
CONFIG_VORTEX=y
CONFIG_TYPHOON=y
CONFIG_NET_VENDOR_ADAPTEC=y
CONFIG_ADAPTEC_STARFIRE=y
CONFIG_NET_VENDOR_AGERE=y
CONFIG_ET131X=y
CONFIG_NET_VENDOR_ALACRITECH=y
CONFIG_SLICOSS=y
CONFIG_NET_VENDOR_ALTEON=y
CONFIG_ACENIC=y
CONFIG_ACENIC_OMIT_TIGON_I=y
CONFIG_ALTERA_TSE=y
CONFIG_NET_VENDOR_AMAZON=y
CONFIG_ENA_ETHERNET=y
CONFIG_NET_VENDOR_AMD=y
CONFIG_AMD8111_ETH=y
CONFIG_LANCE=y
CONFIG_PCNET32=y
CONFIG_PCMCIA_NMCLAN=y
CONFIG_AMD_XGBE=y
CONFIG_AMD_XGBE_DCB=y
CONFIG_AMD_XGBE_HAVE_ECC=y
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_AQTION=y
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ASIX=y
CONFIG_SPI_AX88796C=y
CONFIG_SPI_AX88796C_COMPRESSION=y
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=y
CONFIG_ATL1=y
CONFIG_ATL1E=y
CONFIG_ATL1C=y
CONFIG_ALX=y
CONFIG_CX_ECAT=y
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=y
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
CONFIG_BCMGENET=y
CONFIG_BNX2=y
CONFIG_CNIC=y
CONFIG_TIGON3=y
CONFIG_TIGON3_HWMON=y
CONFIG_BNX2X=y
CONFIG_BNX2X_SRIOV=y
CONFIG_SYSTEMPORT=y
CONFIG_BNXT=y
CONFIG_BNXT_SRIOV=y
CONFIG_BNXT_FLOWER_OFFLOAD=y
CONFIG_BNXT_DCB=y
CONFIG_BNXT_HWMON=y
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=y
CONFIG_MACB_USE_HWSTAMP=y
CONFIG_MACB_PCI=y
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NET_VENDOR_CHELSIO=y
CONFIG_CHELSIO_T1=y
CONFIG_CHELSIO_T1_1G=y
CONFIG_CHELSIO_T3=y
CONFIG_CHELSIO_T4=y
CONFIG_CHELSIO_T4_DCB=y
CONFIG_CHELSIO_T4_FCOE=y
CONFIG_CHELSIO_T4VF=y
CONFIG_CHELSIO_LIB=y
CONFIG_CHELSIO_INLINE_CRYPTO=y
CONFIG_CRYPTO_DEV_CHELSIO_TLS=y
CONFIG_CHELSIO_IPSEC_INLINE=y
CONFIG_CHELSIO_TLS_DEVICE=y
CONFIG_NET_VENDOR_CIRRUS=y
# CONFIG_CS89x0_ISA is not set
CONFIG_NET_VENDOR_CISCO=y
CONFIG_ENIC=y
CONFIG_NET_VENDOR_CORTINA=y
CONFIG_GEMINI_ETHERNET=y
CONFIG_NET_VENDOR_DAVICOM=y
CONFIG_DM9051=y
CONFIG_DNET=y
CONFIG_NET_VENDOR_DEC=y
CONFIG_NET_TULIP=y
CONFIG_DE2104X=y
CONFIG_DE2104X_DSL=0
CONFIG_TULIP=y
CONFIG_TULIP_MWI=y
CONFIG_TULIP_MMIO=y
CONFIG_TULIP_NAPI=y
CONFIG_TULIP_NAPI_HW_MITIGATION=y
CONFIG_WINBOND_840=y
CONFIG_DM9102=y
CONFIG_ULI526X=y
CONFIG_PCMCIA_XIRCOM=y
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=y
CONFIG_SUNDANCE=y
CONFIG_SUNDANCE_MMIO=y
CONFIG_NET_VENDOR_EMULEX=y
CONFIG_BE2NET=y
CONFIG_BE2NET_HWMON=y
CONFIG_BE2NET_BE2=y
CONFIG_BE2NET_BE3=y
CONFIG_BE2NET_LANCER=y
CONFIG_BE2NET_SKYHAWK=y
CONFIG_NET_VENDOR_ENGLEDER=y
CONFIG_TSNEP=y
CONFIG_TSNEP_SELFTESTS=y
CONFIG_NET_VENDOR_EZCHIP=y
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y
CONFIG_NET_VENDOR_FUJITSU=y
CONFIG_PCMCIA_FMVJ18X=y
CONFIG_NET_VENDOR_FUNGIBLE=y
CONFIG_FUN_CORE=y
CONFIG_FUN_ETH=y
CONFIG_NET_VENDOR_GOOGLE=y
CONFIG_GVE=y
CONFIG_NET_VENDOR_HUAWEI=y
CONFIG_HINIC=y
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_E1000E_HWTS=y
CONFIG_IGB=y
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=y
CONFIG_IXGB=y
CONFIG_IXGBE=y
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_DCB=y
CONFIG_IXGBE_IPSEC=y
CONFIG_IXGBEVF=y
CONFIG_IXGBEVF_IPSEC=y
CONFIG_I40E=y
CONFIG_I40E_DCB=y
CONFIG_IAVF=y
CONFIG_I40EVF=y
CONFIG_ICE=y
CONFIG_ICE_SWITCHDEV=y
CONFIG_ICE_HWTS=y
CONFIG_FM10K=y
CONFIG_IGC=y
CONFIG_NET_VENDOR_WANGXUN=y
CONFIG_LIBWX=y
CONFIG_NGBE=y
CONFIG_TXGBE=y
CONFIG_JME=y
CONFIG_NET_VENDOR_ADI=y
CONFIG_ADIN1110=y
CONFIG_NET_VENDOR_LITEX=y
CONFIG_LITEX_LITEETH=y
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_MVMDIO=y
CONFIG_SKGE=y
CONFIG_SKGE_DEBUG=y
CONFIG_SKGE_GENESIS=y
CONFIG_SKY2=y
CONFIG_SKY2_DEBUG=y
CONFIG_PRESTERA=y
CONFIG_PRESTERA_PCI=y
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=y
CONFIG_MLX4_EN_DCB=y
CONFIG_MLX4_CORE=y
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=y
CONFIG_MLX5_FPGA=y
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
CONFIG_MLX5_ESWITCH=y
CONFIG_MLX5_BRIDGE=y
CONFIG_MLX5_CLS_ACT=y
CONFIG_MLX5_TC_CT=y
CONFIG_MLX5_TC_SAMPLE=y
CONFIG_MLX5_CORE_EN_DCB=y
CONFIG_MLX5_CORE_IPOIB=y
CONFIG_MLX5_EN_MACSEC=y
CONFIG_MLX5_EN_IPSEC=y
CONFIG_MLX5_EN_TLS=y
CONFIG_MLX5_SW_STEERING=y
CONFIG_MLX5_SF=y
CONFIG_MLX5_SF_MANAGER=y
CONFIG_MLXSW_CORE=y
CONFIG_MLXSW_CORE_HWMON=y
CONFIG_MLXSW_CORE_THERMAL=y
CONFIG_MLXSW_PCI=y
CONFIG_MLXSW_I2C=y
CONFIG_MLXSW_SPECTRUM=y
CONFIG_MLXSW_SPECTRUM_DCB=y
CONFIG_MLXSW_MINIMAL=y
CONFIG_MLXFW=y
CONFIG_NET_VENDOR_MICREL=y
CONFIG_KS8842=y
CONFIG_KS8851=y
CONFIG_KS8851_MLL=y
CONFIG_KSZ884X_PCI=y
CONFIG_NET_VENDOR_MICROCHIP=y
CONFIG_ENC28J60=y
CONFIG_ENC28J60_WRITEVERIFY=y
CONFIG_ENCX24J600=y
CONFIG_LAN743X=y
CONFIG_LAN966X_SWITCH=y
CONFIG_VCAP=y
CONFIG_VCAP_KUNIT_TEST=y
CONFIG_NET_VENDOR_MICROSEMI=y
CONFIG_MSCC_OCELOT_SWITCH_LIB=y
CONFIG_MSCC_OCELOT_SWITCH=y
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
CONFIG_MYRI10GE=y
CONFIG_NET_VENDOR_NI=y
CONFIG_NI_XGE_MANAGEMENT_ENET=y
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=y
CONFIG_NS83820=y
CONFIG_NET_VENDOR_NETERION=y
CONFIG_S2IO=y
CONFIG_NET_VENDOR_NETRONOME=y
CONFIG_NFP=y
CONFIG_NFP_APP_FLOWER=y
CONFIG_NFP_APP_ABM_NIC=y
CONFIG_NFP_NET_IPSEC=y
CONFIG_NFP_DEBUG=y
CONFIG_NET_VENDOR_8390=y
CONFIG_PCMCIA_AXNET=y
CONFIG_NE2000=y
CONFIG_NE2K_PCI=y
CONFIG_PCMCIA_PCNET=y
CONFIG_ULTRA=y
CONFIG_WD80x3=y
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=y
CONFIG_NET_VENDOR_OKI=y
CONFIG_PCH_GBE=y
CONFIG_ETHOC=y
CONFIG_NET_VENDOR_PACKET_ENGINES=y
CONFIG_HAMACHI=y
CONFIG_YELLOWFIN=y
CONFIG_NET_VENDOR_PENSANDO=y
CONFIG_NET_VENDOR_QLOGIC=y
CONFIG_QLA3XXX=y
CONFIG_QLCNIC=y
CONFIG_QLCNIC_SRIOV=y
CONFIG_QLCNIC_DCB=y
CONFIG_QLCNIC_HWMON=y
CONFIG_NETXEN_NIC=y
CONFIG_QED=y
CONFIG_QED_LL2=y
CONFIG_QED_SRIOV=y
CONFIG_QEDE=y
CONFIG_QED_ISCSI=y
CONFIG_QED_FCOE=y
CONFIG_QED_OOO=y
CONFIG_NET_VENDOR_BROCADE=y
CONFIG_BNA=y
CONFIG_NET_VENDOR_QUALCOMM=y
CONFIG_QCA7000=y
CONFIG_QCA7000_SPI=y
CONFIG_QCA7000_UART=y
CONFIG_QCOM_EMAC=y
CONFIG_RMNET=y
CONFIG_NET_VENDOR_RDC=y
CONFIG_R6040=y
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_ATP=y
CONFIG_8139CP=y
CONFIG_8139TOO=y
CONFIG_8139TOO_PIO=y
CONFIG_8139TOO_TUNE_TWISTER=y
CONFIG_8139TOO_8129=y
CONFIG_8139_OLD_RX_RESET=y
CONFIG_R8169=y
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_ROCKER=y
CONFIG_NET_VENDOR_SAMSUNG=y
CONFIG_SXGBE_ETH=y
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=y
CONFIG_NET_VENDOR_SIS=y
CONFIG_SIS900=y
CONFIG_SIS190=y
CONFIG_NET_VENDOR_SOLARFLARE=y
CONFIG_SFC=y
CONFIG_SFC_MTD=y
CONFIG_SFC_MCDI_MON=y
CONFIG_SFC_SRIOV=y
CONFIG_SFC_MCDI_LOGGING=y
CONFIG_SFC_FALCON=y
CONFIG_SFC_FALCON_MTD=y
CONFIG_SFC_SIENA=y
CONFIG_SFC_SIENA_MTD=y
CONFIG_SFC_SIENA_MCDI_MON=y
CONFIG_SFC_SIENA_SRIOV=y
CONFIG_SFC_SIENA_MCDI_LOGGING=y
CONFIG_NET_VENDOR_SMSC=y
CONFIG_SMC9194=y
CONFIG_PCMCIA_SMC91C92=y
CONFIG_EPIC100=y
CONFIG_SMSC911X=y
CONFIG_SMSC9420=y
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_INTEL_PLAT=y
CONFIG_DWMAC_INTEL=y
CONFIG_DWMAC_LOONGSON=y
CONFIG_STMMAC_PCI=y
CONFIG_NET_VENDOR_SUN=y
CONFIG_HAPPYMEAL=y
CONFIG_SUNGEM=y
CONFIG_CASSINI=y
CONFIG_NIU=y
CONFIG_NET_VENDOR_SYNOPSYS=y
CONFIG_DWC_XLGMAC=y
CONFIG_DWC_XLGMAC_PCI=y
CONFIG_NET_VENDOR_TEHUTI=y
CONFIG_TEHUTI=y
CONFIG_NET_VENDOR_TI=y
CONFIG_TI_CPSW_PHY_SEL=y
CONFIG_TLAN=y
CONFIG_NET_VENDOR_VERTEXCOM=y
CONFIG_MSE102X=y
CONFIG_NET_VENDOR_VIA=y
CONFIG_VIA_RHINE=y
CONFIG_VIA_RHINE_MMIO=y
CONFIG_VIA_VELOCITY=y
CONFIG_NET_VENDOR_WIZNET=y
CONFIG_WIZNET_W5100=y
CONFIG_WIZNET_W5300=y
# CONFIG_WIZNET_BUS_DIRECT is not set
# CONFIG_WIZNET_BUS_INDIRECT is not set
CONFIG_WIZNET_BUS_ANY=y
CONFIG_WIZNET_W5100_SPI=y
CONFIG_NET_VENDOR_XILINX=y
CONFIG_XILINX_EMACLITE=y
CONFIG_XILINX_AXI_EMAC=y
CONFIG_XILINX_LL_TEMAC=y
CONFIG_NET_VENDOR_XIRCOM=y
CONFIG_PCMCIA_XIRC2PS=y
CONFIG_FDDI=y
CONFIG_DEFXX=y
CONFIG_SKFP=y
CONFIG_HIPPI=y
CONFIG_ROADRUNNER=y
CONFIG_ROADRUNNER_LARGE_RINGS=y
CONFIG_NET_SB1000=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_SFP=y
#
# MII PHY device drivers
#
CONFIG_AMD_PHY=y
CONFIG_ADIN_PHY=y
CONFIG_ADIN1100_PHY=y
CONFIG_AQUANTIA_PHY=y
CONFIG_AX88796B_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_BCM54140_PHY=y
CONFIG_BCM7XXX_PHY=y
CONFIG_BCM84881_PHY=y
CONFIG_BCM87XX_PHY=y
CONFIG_BCM_NET_PHYLIB=y
CONFIG_BCM_NET_PHYPTP=y
CONFIG_CICADA_PHY=y
CONFIG_CORTINA_PHY=y
CONFIG_DAVICOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_LXT_PHY=y
CONFIG_INTEL_XWAY_PHY=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_MARVELL_10G_PHY=y
CONFIG_MARVELL_88X2222_PHY=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_MICROCHIP_PHY=y
CONFIG_MICROCHIP_T1_PHY=y
CONFIG_MICROSEMI_PHY=y
CONFIG_MOTORCOMM_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_NXP_C45_TJA11XX_PHY=y
CONFIG_NXP_TJA11XX_PHY=y
CONFIG_AT803X_PHY=y
CONFIG_QSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_RENESAS_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_STE10XP=y
CONFIG_TERANETICS_PHY=y
CONFIG_DP83822_PHY=y
CONFIG_DP83TC811_PHY=y
CONFIG_DP83848_PHY=y
CONFIG_DP83867_PHY=y
CONFIG_DP83869_PHY=y
CONFIG_DP83TD510_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_XILINX_GMII2RGMII=y
CONFIG_MICREL_KS8995MA=y
CONFIG_PSE_CONTROLLER=y
CONFIG_PSE_REGULATOR=y
CONFIG_CAN_DEV=y
CONFIG_CAN_VCAN=y
CONFIG_CAN_VXCAN=y
CONFIG_CAN_NETLINK=y
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_RX_OFFLOAD=y
CONFIG_CAN_CAN327=y
CONFIG_CAN_FLEXCAN=y
CONFIG_CAN_GRCAN=y
CONFIG_CAN_JANZ_ICAN3=y
CONFIG_CAN_KVASER_PCIEFD=y
CONFIG_CAN_SLCAN=y
CONFIG_CAN_C_CAN=y
CONFIG_CAN_C_CAN_PLATFORM=y
CONFIG_CAN_C_CAN_PCI=y
CONFIG_CAN_CC770=y
CONFIG_CAN_CC770_ISA=y
CONFIG_CAN_CC770_PLATFORM=y
CONFIG_CAN_CTUCANFD=y
CONFIG_CAN_CTUCANFD_PCI=y
CONFIG_CAN_CTUCANFD_PLATFORM=y
CONFIG_CAN_IFI_CANFD=y
CONFIG_CAN_M_CAN=y
CONFIG_CAN_M_CAN_PCI=y
CONFIG_CAN_M_CAN_PLATFORM=y
CONFIG_CAN_M_CAN_TCAN4X5X=y
CONFIG_CAN_PEAK_PCIEFD=y
CONFIG_CAN_SJA1000=y
CONFIG_CAN_EMS_PCI=y
CONFIG_CAN_EMS_PCMCIA=y
CONFIG_CAN_F81601=y
CONFIG_CAN_KVASER_PCI=y
CONFIG_CAN_PEAK_PCI=y
CONFIG_CAN_PEAK_PCIEC=y
CONFIG_CAN_PEAK_PCMCIA=y
CONFIG_CAN_PLX_PCI=y
CONFIG_CAN_SJA1000_ISA=y
CONFIG_CAN_SJA1000_PLATFORM=y
CONFIG_CAN_TSCAN1=y
CONFIG_CAN_SOFTING=y
CONFIG_CAN_SOFTING_CS=y
#
# CAN SPI interfaces
#
CONFIG_CAN_HI311X=y
CONFIG_CAN_MCP251X=y
CONFIG_CAN_MCP251XFD=y
CONFIG_CAN_MCP251XFD_SANITY=y
# end of CAN SPI interfaces
#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=y
CONFIG_CAN_EMS_USB=y
CONFIG_CAN_ESD_USB=y
CONFIG_CAN_ETAS_ES58X=y
CONFIG_CAN_GS_USB=y
CONFIG_CAN_KVASER_USB=y
CONFIG_CAN_MCBA_USB=y
CONFIG_CAN_PEAK_USB=y
CONFIG_CAN_UCAN=y
# end of CAN USB interfaces
CONFIG_CAN_DEBUG_DEVICES=y
#
# MCTP Device Drivers
#
CONFIG_MCTP_SERIAL=y
CONFIG_MCTP_TRANSPORT_I2C=y
# end of MCTP Device Drivers
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BCM_UNIMAC=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_HISI_FEMAC=y
CONFIG_MDIO_I2C=y
CONFIG_MDIO_MVUSB=y
CONFIG_MDIO_MSCC_MIIM=y
CONFIG_MDIO_IPQ4019=y
CONFIG_MDIO_IPQ8064=y
#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
CONFIG_PCS_LYNX=y
CONFIG_PCS_ALTERA_TSE=y
# end of PCS device drivers
CONFIG_PLIP=y
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=y
CONFIG_PPPOE=y
CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_SLIP=y
CONFIG_SLHC=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=y
CONFIG_USB_KAWETH=y
CONFIG_USB_PEGASUS=y
CONFIG_USB_RTL8150=y
CONFIG_USB_RTL8152=y
CONFIG_USB_LAN78XX=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_AX88179_178A=y
CONFIG_USB_NET_CDCETHER=y
CONFIG_USB_NET_CDC_EEM=y
CONFIG_USB_NET_CDC_NCM=y
CONFIG_USB_NET_HUAWEI_CDC_NCM=y
CONFIG_USB_NET_CDC_MBIM=y
CONFIG_USB_NET_DM9601=y
CONFIG_USB_NET_SR9700=y
CONFIG_USB_NET_SR9800=y
CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y
CONFIG_USB_NET_GL620A=y
CONFIG_USB_NET_NET1080=y
CONFIG_USB_NET_PLUSB=y
CONFIG_USB_NET_MCS7830=y
CONFIG_USB_NET_RNDIS_HOST=y
CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
CONFIG_USB_NET_CDC_SUBSET=y
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=y
CONFIG_USB_NET_CX82310_ETH=y
CONFIG_USB_NET_KALMIA=y
CONFIG_USB_NET_QMI_WWAN=y
CONFIG_USB_HSO=y
CONFIG_USB_NET_INT51X1=y
CONFIG_USB_CDC_PHONET=y
CONFIG_USB_IPHETH=y
CONFIG_USB_SIERRA_NET=y
CONFIG_USB_VL600=y
CONFIG_USB_NET_CH9200=y
CONFIG_USB_NET_AQC111=y
CONFIG_USB_RTL8153_ECM=y
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=y
CONFIG_ATH_COMMON=y
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_DEBUG=y
CONFIG_ATH_TRACEPOINTS=y
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y
CONFIG_ATH5K=y
CONFIG_ATH5K_DEBUG=y
CONFIG_ATH5K_TRACER=y
CONFIG_ATH5K_PCI=y
CONFIG_ATH5K_TEST_CHANNELS=y
CONFIG_ATH9K_HW=y
CONFIG_ATH9K_COMMON=y
CONFIG_ATH9K_COMMON_DEBUG=y
CONFIG_ATH9K_DFS_DEBUGFS=y
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=y
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
CONFIG_ATH9K_DEBUGFS=y
CONFIG_ATH9K_STATION_STATISTICS=y
CONFIG_ATH9K_TX99=y
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
CONFIG_ATH9K_WOW=y
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
CONFIG_ATH9K_PCOEM=y
CONFIG_ATH9K_PCI_NO_EEPROM=y
CONFIG_ATH9K_HTC=y
CONFIG_ATH9K_HTC_DEBUGFS=y
CONFIG_ATH9K_HWRNG=y
CONFIG_ATH9K_COMMON_SPECTRAL=y
CONFIG_CARL9170=y
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_DEBUGFS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=y
CONFIG_ATH6KL_SDIO=y
CONFIG_ATH6KL_USB=y
CONFIG_ATH6KL_DEBUG=y
CONFIG_ATH6KL_TRACING=y
CONFIG_ATH6KL_REGDOMAIN=y
CONFIG_AR5523=y
CONFIG_WIL6210=y
CONFIG_WIL6210_ISR_COR=y
CONFIG_WIL6210_TRACING=y
CONFIG_WIL6210_DEBUGFS=y
CONFIG_ATH10K=y
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=y
CONFIG_ATH10K_AHB=y
CONFIG_ATH10K_SDIO=y
CONFIG_ATH10K_USB=y
CONFIG_ATH10K_DEBUG=y
CONFIG_ATH10K_DEBUGFS=y
CONFIG_ATH10K_SPECTRAL=y
CONFIG_ATH10K_TRACING=y
CONFIG_ATH10K_DFS_CERTIFIED=y
CONFIG_WCN36XX=y
CONFIG_WCN36XX_DEBUGFS=y
CONFIG_ATH11K=y
CONFIG_ATH11K_AHB=y
CONFIG_ATH11K_PCI=y
CONFIG_ATH11K_DEBUG=y
CONFIG_ATH11K_DEBUGFS=y
CONFIG_ATH11K_TRACING=y
CONFIG_ATH11K_SPECTRAL=y
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_ATMEL=y
CONFIG_PCI_ATMEL=y
CONFIG_PCMCIA_ATMEL=y
CONFIG_AT76C50X_USB=y
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=y
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
CONFIG_B43_SDIO=y
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
CONFIG_B43_DEBUG=y
CONFIG_B43LEGACY=y
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=y
CONFIG_BRCMSMAC=y
CONFIG_BRCMSMAC_LEDS=y
CONFIG_BRCMFMAC=y
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
CONFIG_WLAN_VENDOR_CISCO=y
CONFIG_AIRO=y
CONFIG_AIRO_CS=y
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=y
CONFIG_IPW2100_MONITOR=y
CONFIG_IPW2100_DEBUG=y
CONFIG_IPW2200=y
CONFIG_IPW2200_MONITOR=y
CONFIG_IPW2200_RADIOTAP=y
CONFIG_IPW2200_PROMISCUOUS=y
CONFIG_IPW2200_QOS=y
CONFIG_IPW2200_DEBUG=y
CONFIG_LIBIPW=y
CONFIG_LIBIPW_DEBUG=y
CONFIG_IWLEGACY=y
CONFIG_IWL4965=y
CONFIG_IWL3945=y
#
# iwl3945 / iwl4965 Debugging Options
#
CONFIG_IWLEGACY_DEBUG=y
CONFIG_IWLEGACY_DEBUGFS=y
# end of iwl3945 / iwl4965 Debugging Options
CONFIG_IWLWIFI=y
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=y
CONFIG_IWLMVM=y
#
# Debugging Options
#
CONFIG_IWLWIFI_DEBUG=y
CONFIG_IWLWIFI_DEBUGFS=y
CONFIG_IWLWIFI_DEVICE_TRACING=y
# end of Debugging Options
CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=y
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
CONFIG_HOSTAP_PLX=y
CONFIG_HOSTAP_PCI=y
CONFIG_HOSTAP_CS=y
CONFIG_HERMES=y
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=y
CONFIG_TMD_HERMES=y
CONFIG_NORTEL_HERMES=y
CONFIG_PCI_HERMES=y
CONFIG_PCMCIA_HERMES=y
CONFIG_PCMCIA_SPECTRUM=y
CONFIG_ORINOCO_USB=y
CONFIG_P54_COMMON=y
CONFIG_P54_USB=y
CONFIG_P54_PCI=y
CONFIG_P54_SPI=y
CONFIG_P54_SPI_DEFAULT_EEPROM=y
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=y
CONFIG_LIBERTAS_USB=y
CONFIG_LIBERTAS_CS=y
CONFIG_LIBERTAS_SDIO=y
CONFIG_LIBERTAS_SPI=y
CONFIG_LIBERTAS_DEBUG=y
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=y
CONFIG_LIBERTAS_THINFIRM_DEBUG=y
CONFIG_LIBERTAS_THINFIRM_USB=y
CONFIG_MWIFIEX=y
CONFIG_MWIFIEX_SDIO=y
CONFIG_MWIFIEX_PCIE=y
CONFIG_MWIFIEX_USB=y
CONFIG_MWL8K=y
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=y
CONFIG_MT76_CORE=y
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=y
CONFIG_MT76_SDIO=y
CONFIG_MT76x02_LIB=y
CONFIG_MT76x02_USB=y
CONFIG_MT76_CONNAC_LIB=y
CONFIG_MT76x0_COMMON=y
CONFIG_MT76x0U=y
CONFIG_MT76x0E=y
CONFIG_MT76x2_COMMON=y
CONFIG_MT76x2E=y
CONFIG_MT76x2U=y
CONFIG_MT7603E=y
CONFIG_MT7615_COMMON=y
CONFIG_MT7615E=y
CONFIG_MT7663_USB_SDIO_COMMON=y
CONFIG_MT7663U=y
CONFIG_MT7663S=y
CONFIG_MT7915E=y
CONFIG_MT7921_COMMON=y
CONFIG_MT7921E=y
CONFIG_MT7921S=y
CONFIG_MT7921U=y
CONFIG_MT7996E=y
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=y
CONFIG_WILC1000_SDIO=y
CONFIG_WILC1000_SPI=y
CONFIG_WILC1000_HW_OOB_INTR=y
CONFIG_WLAN_VENDOR_PURELIFI=y
CONFIG_PLFXLC=y
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=y
CONFIG_RT2400PCI=y
CONFIG_RT2500PCI=y
CONFIG_RT61PCI=y
CONFIG_RT2800PCI=y
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=y
CONFIG_RT73USB=y
CONFIG_RT2800USB=y
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=y
CONFIG_RT2800_LIB_MMIO=y
CONFIG_RT2X00_LIB_MMIO=y
CONFIG_RT2X00_LIB_PCI=y
CONFIG_RT2X00_LIB_USB=y
CONFIG_RT2X00_LIB=y
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
CONFIG_RT2X00_LIB_DEBUGFS=y
CONFIG_RT2X00_DEBUG=y
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=y
CONFIG_RTL8187=y
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=y
CONFIG_RTL8192CE=y
CONFIG_RTL8192SE=y
CONFIG_RTL8192DE=y
CONFIG_RTL8723AE=y
CONFIG_RTL8723BE=y
CONFIG_RTL8188EE=y
CONFIG_RTL8192EE=y
CONFIG_RTL8821AE=y
CONFIG_RTL8192CU=y
CONFIG_RTLWIFI=y
CONFIG_RTLWIFI_PCI=y
CONFIG_RTLWIFI_USB=y
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=y
CONFIG_RTL8723_COMMON=y
CONFIG_RTLBTCOEXIST=y
CONFIG_RTL8XXXU=y
CONFIG_RTL8XXXU_UNTESTED=y
CONFIG_RTW88=y
CONFIG_RTW88_CORE=y
CONFIG_RTW88_PCI=y
CONFIG_RTW88_USB=y
CONFIG_RTW88_8822B=y
CONFIG_RTW88_8822C=y
CONFIG_RTW88_8723D=y
CONFIG_RTW88_8821C=y
CONFIG_RTW88_8822BE=y
CONFIG_RTW88_8822BU=y
CONFIG_RTW88_8822CE=y
CONFIG_RTW88_8822CU=y
CONFIG_RTW88_8723DE=y
CONFIG_RTW88_8723DU=y
CONFIG_RTW88_8821CE=y
CONFIG_RTW88_8821CU=y
CONFIG_RTW88_DEBUG=y
CONFIG_RTW88_DEBUGFS=y
CONFIG_RTW89=y
CONFIG_RTW89_CORE=y
CONFIG_RTW89_PCI=y
CONFIG_RTW89_8852A=y
CONFIG_RTW89_8852B=y
CONFIG_RTW89_8852C=y
CONFIG_RTW89_8852AE=y
CONFIG_RTW89_8852BE=y
CONFIG_RTW89_8852CE=y
CONFIG_RTW89_DEBUG=y
CONFIG_RTW89_DEBUGMSG=y
CONFIG_RTW89_DEBUGFS=y
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=y
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=y
CONFIG_RSI_USB=y
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_SILABS=y
CONFIG_WFX=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=y
CONFIG_CW1200_WLAN_SDIO=y
CONFIG_CW1200_WLAN_SPI=y
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=y
CONFIG_WL1251_SPI=y
CONFIG_WL1251_SDIO=y
CONFIG_WL12XX=y
CONFIG_WL18XX=y
CONFIG_WLCORE=y
CONFIG_WLCORE_SPI=y
CONFIG_WLCORE_SDIO=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=y
CONFIG_ZD1211RW=y
CONFIG_ZD1211RW_DEBUG=y
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=y
CONFIG_QTNFMAC_PCIE=y
CONFIG_PCMCIA_RAYCS=y
CONFIG_PCMCIA_WL3501=y
CONFIG_MAC80211_HWSIM=y
CONFIG_USB_NET_RNDIS_WLAN=y
CONFIG_VIRT_WIFI=y
CONFIG_WAN=y
CONFIG_HDLC=y
CONFIG_HDLC_RAW=y
CONFIG_HDLC_RAW_ETH=y
CONFIG_HDLC_CISCO=y
CONFIG_HDLC_FR=y
CONFIG_HDLC_PPP=y
CONFIG_HDLC_X25=y
CONFIG_PCI200SYN=y
CONFIG_WANXL=y
CONFIG_PC300TOO=y
CONFIG_N2=y
CONFIG_C101=y
CONFIG_FARSYNC=y
CONFIG_LAPBETHER=y
CONFIG_IEEE802154_DRIVERS=y
CONFIG_IEEE802154_FAKELB=y
CONFIG_IEEE802154_AT86RF230=y
CONFIG_IEEE802154_MRF24J40=y
CONFIG_IEEE802154_CC2520=y
CONFIG_IEEE802154_ATUSB=y
CONFIG_IEEE802154_ADF7242=y
CONFIG_IEEE802154_CA8210=y
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=y
CONFIG_IEEE802154_HWSIM=y
#
# Wireless WAN
#
CONFIG_WWAN=y
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=y
CONFIG_MHI_WWAN_CTRL=y
CONFIG_MHI_WWAN_MBIM=y
CONFIG_RPMSG_WWAN_CTRL=y
CONFIG_IOSM=y
CONFIG_MTK_T7XX=y
# end of Wireless WAN
CONFIG_VMXNET3=y
CONFIG_FUJITSU_ES=y
CONFIG_USB4_NET=y
CONFIG_HYPERV_NET=y
CONFIG_NETDEVSIM=y
CONFIG_NET_FAILOVER=y
CONFIG_NETDEV_LEGACY_INIT=y
CONFIG_ISDN=y
CONFIG_ISDN_CAPI=y
CONFIG_CAPI_TRACE=y
CONFIG_ISDN_CAPI_MIDDLEWARE=y
CONFIG_MISDN=y
CONFIG_MISDN_DSP=y
CONFIG_MISDN_L1OIP=y
#
# mISDN hardware drivers
#
CONFIG_MISDN_HFCPCI=y
CONFIG_MISDN_HFCMULTI=y
CONFIG_MISDN_HFCUSB=y
CONFIG_MISDN_AVMFRITZ=y
CONFIG_MISDN_SPEEDFAX=y
CONFIG_MISDN_INFINEON=y
CONFIG_MISDN_W6692=y
CONFIG_MISDN_NETJET=y
CONFIG_MISDN_HDLC=y
CONFIG_MISDN_IPAC=y
CONFIG_MISDN_ISAR=y
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=y
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=y
CONFIG_KEYBOARD_ADP5520=y
CONFIG_KEYBOARD_ADP5588=y
CONFIG_KEYBOARD_ADP5589=y
CONFIG_KEYBOARD_APPLESPI=y
CONFIG_KEYBOARD_ATKBD=y
CONFIG_KEYBOARD_QT1050=y
CONFIG_KEYBOARD_QT1070=y
CONFIG_KEYBOARD_QT2160=y
CONFIG_KEYBOARD_DLINK_DIR685=y
CONFIG_KEYBOARD_LKKBD=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_KEYBOARD_TCA6416=y
CONFIG_KEYBOARD_TCA8418=y
CONFIG_KEYBOARD_MATRIX=y
CONFIG_KEYBOARD_LM8323=y
CONFIG_KEYBOARD_LM8333=y
CONFIG_KEYBOARD_MAX7359=y
CONFIG_KEYBOARD_MCS=y
CONFIG_KEYBOARD_MPR121=y
CONFIG_KEYBOARD_NEWTON=y
CONFIG_KEYBOARD_OPENCORES=y
CONFIG_KEYBOARD_PINEPHONE=y
CONFIG_KEYBOARD_SAMSUNG=y
CONFIG_KEYBOARD_GOLDFISH_EVENTS=y
CONFIG_KEYBOARD_STOWAWAY=y
CONFIG_KEYBOARD_SUNKBD=y
CONFIG_KEYBOARD_STMPE=y
CONFIG_KEYBOARD_IQS62X=y
CONFIG_KEYBOARD_OMAP4=y
CONFIG_KEYBOARD_TC3589X=y
CONFIG_KEYBOARD_TM2_TOUCHKEY=y
CONFIG_KEYBOARD_TWL4030=y
CONFIG_KEYBOARD_XTKBD=y
CONFIG_KEYBOARD_CROS_EC=y
CONFIG_KEYBOARD_CAP11XX=y
CONFIG_KEYBOARD_BCM=y
CONFIG_KEYBOARD_MTK_PMIC=y
CONFIG_KEYBOARD_CYPRESS_SF=y
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_PS2_OLPC=y
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_VMMOUSE=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=y
CONFIG_MOUSE_APPLETOUCH=y
CONFIG_MOUSE_BCM5974=y
CONFIG_MOUSE_CYAPA=y
CONFIG_MOUSE_ELAN_I2C=y
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_INPORT=y
CONFIG_MOUSE_ATIXL=y
CONFIG_MOUSE_LOGIBM=y
CONFIG_MOUSE_PC110PAD=y
CONFIG_MOUSE_VSXXXAA=y
CONFIG_MOUSE_GPIO=y
CONFIG_MOUSE_SYNAPTICS_I2C=y
CONFIG_MOUSE_SYNAPTICS_USB=y
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=y
CONFIG_JOYSTICK_A3D=y
CONFIG_JOYSTICK_ADC=y
CONFIG_JOYSTICK_ADI=y
CONFIG_JOYSTICK_COBRA=y
CONFIG_JOYSTICK_GF2K=y
CONFIG_JOYSTICK_GRIP=y
CONFIG_JOYSTICK_GRIP_MP=y
CONFIG_JOYSTICK_GUILLEMOT=y
CONFIG_JOYSTICK_INTERACT=y
CONFIG_JOYSTICK_SIDEWINDER=y
CONFIG_JOYSTICK_TMDC=y
CONFIG_JOYSTICK_IFORCE=y
CONFIG_JOYSTICK_IFORCE_USB=y
CONFIG_JOYSTICK_IFORCE_232=y
CONFIG_JOYSTICK_WARRIOR=y
CONFIG_JOYSTICK_MAGELLAN=y
CONFIG_JOYSTICK_SPACEORB=y
CONFIG_JOYSTICK_SPACEBALL=y
CONFIG_JOYSTICK_STINGER=y
CONFIG_JOYSTICK_TWIDJOY=y
CONFIG_JOYSTICK_ZHENHUA=y
CONFIG_JOYSTICK_DB9=y
CONFIG_JOYSTICK_GAMECON=y
CONFIG_JOYSTICK_TURBOGRAFX=y
CONFIG_JOYSTICK_AS5011=y
CONFIG_JOYSTICK_JOYDUMP=y
CONFIG_JOYSTICK_XPAD=y
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_WALKERA0701=y
CONFIG_JOYSTICK_PSXPAD_SPI=y
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=y
CONFIG_JOYSTICK_QWIIC=y
CONFIG_JOYSTICK_FSIA6B=y
CONFIG_JOYSTICK_SENSEHAT=y
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=y
CONFIG_TABLET_USB_AIPTEK=y
CONFIG_TABLET_USB_HANWANG=y
CONFIG_TABLET_USB_KBTAB=y
CONFIG_TABLET_USB_PEGASUS=y
CONFIG_TABLET_SERIAL_WACOM4=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_88PM860X=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_AD7877=y
CONFIG_TOUCHSCREEN_AD7879=y
CONFIG_TOUCHSCREEN_AD7879_I2C=y
CONFIG_TOUCHSCREEN_AD7879_SPI=y
CONFIG_TOUCHSCREEN_ADC=y
CONFIG_TOUCHSCREEN_AR1021_I2C=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=y
CONFIG_TOUCHSCREEN_BU21013=y
CONFIG_TOUCHSCREEN_BU21029=y
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=y
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=y
CONFIG_TOUCHSCREEN_CY8CTMA140=y
CONFIG_TOUCHSCREEN_CY8CTMG110=y
CONFIG_TOUCHSCREEN_CYTTSP_CORE=y
CONFIG_TOUCHSCREEN_CYTTSP_I2C=y
CONFIG_TOUCHSCREEN_CYTTSP_SPI=y
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=y
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=y
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=y
CONFIG_TOUCHSCREEN_CYTTSP5=y
CONFIG_TOUCHSCREEN_DA9034=y
CONFIG_TOUCHSCREEN_DA9052=y
CONFIG_TOUCHSCREEN_DYNAPRO=y
CONFIG_TOUCHSCREEN_HAMPSHIRE=y
CONFIG_TOUCHSCREEN_EETI=y
CONFIG_TOUCHSCREEN_EGALAX=y
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=y
CONFIG_TOUCHSCREEN_EXC3000=y
CONFIG_TOUCHSCREEN_FUJITSU=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_TOUCHSCREEN_HIDEEP=y
CONFIG_TOUCHSCREEN_HYCON_HY46XX=y
CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=y
CONFIG_TOUCHSCREEN_ILI210X=y
CONFIG_TOUCHSCREEN_ILITEK=y
CONFIG_TOUCHSCREEN_S6SY761=y
CONFIG_TOUCHSCREEN_GUNZE=y
CONFIG_TOUCHSCREEN_EKTF2127=y
CONFIG_TOUCHSCREEN_ELAN=y
CONFIG_TOUCHSCREEN_ELO=y
CONFIG_TOUCHSCREEN_WACOM_W8001=y
CONFIG_TOUCHSCREEN_WACOM_I2C=y
CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_MCS5000=y
CONFIG_TOUCHSCREEN_MMS114=y
CONFIG_TOUCHSCREEN_MELFAS_MIP4=y
CONFIG_TOUCHSCREEN_MSG2638=y
CONFIG_TOUCHSCREEN_MTOUCH=y
CONFIG_TOUCHSCREEN_IMAGIS=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_INEXIO=y
CONFIG_TOUCHSCREEN_MK712=y
CONFIG_TOUCHSCREEN_HTCPEN=y
CONFIG_TOUCHSCREEN_PENMOUNT=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TOUCHSCREEN_TOUCHRIGHT=y
CONFIG_TOUCHSCREEN_TOUCHWIN=y
CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y
CONFIG_TOUCHSCREEN_UCB1400=y
CONFIG_TOUCHSCREEN_PIXCIR=y
CONFIG_TOUCHSCREEN_WDT87XX_I2C=y
CONFIG_TOUCHSCREEN_WM831X=y
CONFIG_TOUCHSCREEN_WM97XX=y
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=y
CONFIG_TOUCHSCREEN_TSC_SERIO=y
CONFIG_TOUCHSCREEN_TSC200X_CORE=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2005=y
CONFIG_TOUCHSCREEN_TSC2007=y
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_PCAP=y
CONFIG_TOUCHSCREEN_RM_TS=y
CONFIG_TOUCHSCREEN_SILEAD=y
CONFIG_TOUCHSCREEN_SIS_I2C=y
CONFIG_TOUCHSCREEN_ST1232=y
CONFIG_TOUCHSCREEN_STMFTS=y
CONFIG_TOUCHSCREEN_STMPE=y
CONFIG_TOUCHSCREEN_SUR40=y
CONFIG_TOUCHSCREEN_SURFACE3_SPI=y
CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_TPS6507X=y
CONFIG_TOUCHSCREEN_ZET6223=y
CONFIG_TOUCHSCREEN_ZFORCE=y
CONFIG_TOUCHSCREEN_COLIBRI_VF50=y
CONFIG_TOUCHSCREEN_ROHM_BU21023=y
CONFIG_TOUCHSCREEN_IQS5XX=y
CONFIG_TOUCHSCREEN_ZINITIX=y
CONFIG_TOUCHSCREEN_HIMAX_HX83112B=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_88PM860X_ONKEY=y
CONFIG_INPUT_88PM80X_ONKEY=y
CONFIG_INPUT_AD714X=y
CONFIG_INPUT_AD714X_I2C=y
CONFIG_INPUT_AD714X_SPI=y
CONFIG_INPUT_ARIZONA_HAPTICS=y
CONFIG_INPUT_ATC260X_ONKEY=y
CONFIG_INPUT_ATMEL_CAPTOUCH=y
CONFIG_INPUT_BMA150=y
CONFIG_INPUT_E3X0_BUTTON=y
CONFIG_INPUT_PCSPKR=y
CONFIG_INPUT_MAX77650_ONKEY=y
CONFIG_INPUT_MAX77693_HAPTIC=y
CONFIG_INPUT_MAX8925_ONKEY=y
CONFIG_INPUT_MAX8997_HAPTIC=y
CONFIG_INPUT_MC13783_PWRBUTTON=y
CONFIG_INPUT_MMA8450=y
CONFIG_INPUT_APANEL=y
CONFIG_INPUT_GPIO_BEEPER=y
CONFIG_INPUT_GPIO_DECODER=y
CONFIG_INPUT_GPIO_VIBRA=y
CONFIG_INPUT_CPCAP_PWRBUTTON=y
CONFIG_INPUT_WISTRON_BTNS=y
CONFIG_INPUT_ATLAS_BTNS=y
CONFIG_INPUT_ATI_REMOTE2=y
CONFIG_INPUT_KEYSPAN_REMOTE=y
CONFIG_INPUT_KXTJ9=y
CONFIG_INPUT_POWERMATE=y
CONFIG_INPUT_YEALINK=y
CONFIG_INPUT_CM109=y
CONFIG_INPUT_REGULATOR_HAPTIC=y
CONFIG_INPUT_RETU_PWRBUTTON=y
CONFIG_INPUT_TPS65218_PWRBUTTON=y
CONFIG_INPUT_TPS65219_PWRBUTTON=y
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_TWL4030_PWRBUTTON=y
CONFIG_INPUT_TWL4030_VIBRA=y
CONFIG_INPUT_TWL6040_VIBRA=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_PALMAS_PWRBUTTON=y
CONFIG_INPUT_PCF50633_PMU=y
CONFIG_INPUT_PCF8574=y
CONFIG_INPUT_PWM_BEEPER=y
CONFIG_INPUT_PWM_VIBRA=y
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
CONFIG_INPUT_DA7280_HAPTICS=y
CONFIG_INPUT_DA9052_ONKEY=y
CONFIG_INPUT_DA9055_ONKEY=y
CONFIG_INPUT_DA9063_ONKEY=y
CONFIG_INPUT_WM831X_ON=y
CONFIG_INPUT_PCAP=y
CONFIG_INPUT_ADXL34X=y
CONFIG_INPUT_ADXL34X_I2C=y
CONFIG_INPUT_ADXL34X_SPI=y
CONFIG_INPUT_IBM_PANEL=y
CONFIG_INPUT_IMS_PCU=y
CONFIG_INPUT_IQS269A=y
CONFIG_INPUT_IQS626A=y
CONFIG_INPUT_IQS7222=y
CONFIG_INPUT_CMA3000=y
CONFIG_INPUT_CMA3000_I2C=y
CONFIG_INPUT_IDEAPAD_SLIDEBAR=y
CONFIG_INPUT_SOC_BUTTON_ARRAY=y
CONFIG_INPUT_DRV260X_HAPTICS=y
CONFIG_INPUT_DRV2665_HAPTICS=y
CONFIG_INPUT_DRV2667_HAPTICS=y
CONFIG_INPUT_RAVE_SP_PWRBUTTON=y
CONFIG_INPUT_RT5120_PWRKEY=y
CONFIG_INPUT_STPMIC1_ONKEY=y
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_CT82C710=y
CONFIG_SERIO_PARKBD=y
CONFIG_SERIO_PCIPS2=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=y
CONFIG_SERIO_ALTERA_PS2=y
CONFIG_SERIO_PS2MULT=y
CONFIG_SERIO_ARC_PS2=y
CONFIG_SERIO_APBPS2=y
CONFIG_HYPERV_KEYBOARD=y
CONFIG_SERIO_GPIO_PS2=y
CONFIG_USERIO=y
CONFIG_GAMEPORT=y
CONFIG_GAMEPORT_NS558=y
CONFIG_GAMEPORT_L4=y
CONFIG_GAMEPORT_EMU10K1=y
CONFIG_GAMEPORT_FM801=y
# end of Hardware I/O ports
# end of Input device support
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
CONFIG_SERIAL_8250_FINTEK=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_CS=y
CONFIG_SERIAL_8250_MEN_MCB=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_FOURPORT=y
CONFIG_SERIAL_8250_ACCENT=y
CONFIG_SERIAL_8250_BOCA=y
CONFIG_SERIAL_8250_EXAR_ST16C554=y
CONFIG_SERIAL_8250_HUB6=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_RT288X=y
CONFIG_SERIAL_8250_LPSS=y
CONFIG_SERIAL_8250_MID=y
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y
#
# Non-8250 serial port support
#
CONFIG_SERIAL_KGDB_NMI=y
CONFIG_SERIAL_MAX3100=y
CONFIG_SERIAL_MAX310X=y
CONFIG_SERIAL_UARTLITE=y
CONFIG_SERIAL_UARTLITE_CONSOLE=y
CONFIG_SERIAL_UARTLITE_NR_UARTS=1
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_JSM=y
CONFIG_SERIAL_SIFIVE=y
CONFIG_SERIAL_SIFIVE_CONSOLE=y
CONFIG_SERIAL_LANTIQ=y
CONFIG_SERIAL_LANTIQ_CONSOLE=y
CONFIG_SERIAL_SCCNXP=y
CONFIG_SERIAL_SCCNXP_CONSOLE=y
CONFIG_SERIAL_SC16IS7XX_CORE=y
CONFIG_SERIAL_SC16IS7XX=y
CONFIG_SERIAL_SC16IS7XX_I2C=y
CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_SERIAL_TIMBERDALE=y
CONFIG_SERIAL_ALTERA_JTAGUART=y
CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE=y
CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS=y
CONFIG_SERIAL_ALTERA_UART=y
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
CONFIG_SERIAL_ALTERA_UART_CONSOLE=y
CONFIG_SERIAL_PCH_UART=y
CONFIG_SERIAL_PCH_UART_CONSOLE=y
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_SERIAL_ARC=y
CONFIG_SERIAL_ARC_CONSOLE=y
CONFIG_SERIAL_ARC_NR_PORTS=1
CONFIG_SERIAL_RP2=y
CONFIG_SERIAL_RP2_NR_UARTS=32
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
CONFIG_SERIAL_MEN_Z135=y
CONFIG_SERIAL_SPRD=y
CONFIG_SERIAL_SPRD_CONSOLE=y
CONFIG_SERIAL_LITEUART=y
CONFIG_SERIAL_LITEUART_MAX_PORTS=1
CONFIG_SERIAL_LITEUART_CONSOLE=y
# end of Serial drivers
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_MOXA_INTELLIO=y
CONFIG_MOXA_SMARTIO=y
CONFIG_SYNCLINK_GT=y
CONFIG_N_HDLC=y
CONFIG_GOLDFISH_TTY=y
CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y
CONFIG_N_GSM=y
CONFIG_NOZOMI=y
CONFIG_NULL_TTY=y
CONFIG_HVC_DRIVER=y
CONFIG_RPMSG_TTY=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_TTY_PRINTK=y
CONFIG_TTY_PRINTK_LEVEL=6
CONFIG_PRINTER=y
CONFIG_LP_CONSOLE=y
CONFIG_PPDEV=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_DMI_DECODE=y
CONFIG_IPMI_PLAT_DATA=y
CONFIG_IPMI_PANIC_EVENT=y
CONFIG_IPMI_PANIC_STRING=y
CONFIG_IPMI_DEVICE_INTERFACE=y
CONFIG_IPMI_SI=y
CONFIG_IPMI_SSIF=y
CONFIG_IPMI_IPMB=y
CONFIG_IPMI_WATCHDOG=y
CONFIG_IPMI_POWEROFF=y
CONFIG_SSIF_IPMI_BMC=y
CONFIG_IPMB_DEVICE_INTERFACE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
CONFIG_HW_RANDOM_INTEL=y
CONFIG_HW_RANDOM_AMD=y
CONFIG_HW_RANDOM_BA431=y
CONFIG_HW_RANDOM_GEODE=y
CONFIG_HW_RANDOM_VIA=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_HW_RANDOM_CCTRNG=y
CONFIG_HW_RANDOM_XIPHERA=y
CONFIG_DTLK=y
CONFIG_APPLICOM=y
CONFIG_SONYPI=y
#
# PCMCIA character devices
#
CONFIG_SYNCLINK_CS=y
CONFIG_CARDMAN_4000=y
CONFIG_CARDMAN_4040=y
CONFIG_SCR24X=y
CONFIG_IPWIRELESS=y
# end of PCMCIA character devices
CONFIG_MWAVE=y
CONFIG_SCx200_GPIO=y
CONFIG_PC8736x_GPIO=y
CONFIG_NSC_GPIO=y
CONFIG_DEVMEM=y
CONFIG_NVRAM=y
CONFIG_DEVPORT=y
CONFIG_HPET=y
CONFIG_HPET_MMAP=y
CONFIG_HPET_MMAP_DEFAULT=y
CONFIG_HANGCHECK_TIMER=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
CONFIG_TCG_TIS_CORE=y
CONFIG_TCG_TIS=y
CONFIG_TCG_TIS_SPI=y
CONFIG_TCG_TIS_SPI_CR50=y
CONFIG_TCG_TIS_I2C=y
CONFIG_TCG_TIS_I2C_CR50=y
CONFIG_TCG_TIS_I2C_ATMEL=y
CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_TCG_TIS_I2C_NUVOTON=y
CONFIG_TCG_NSC=y
CONFIG_TCG_ATMEL=y
CONFIG_TCG_INFINEON=y
CONFIG_TCG_CRB=y
CONFIG_TCG_VTPM_PROXY=y
CONFIG_TCG_TIS_ST33ZP24=y
CONFIG_TCG_TIS_ST33ZP24_I2C=y
CONFIG_TCG_TIS_ST33ZP24_SPI=y
CONFIG_TELCLOCK=y
CONFIG_XILLYBUS_CLASS=y
CONFIG_XILLYBUS=y
CONFIG_XILLYBUS_PCIE=y
CONFIG_XILLYBUS_OF=y
CONFIG_XILLYUSB=y
# end of Character devices
#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=y
# end of Multiplexer I2C Chip support
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCA=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=y
CONFIG_I2C_ALI1535=y
CONFIG_I2C_ALI1563=y
CONFIG_I2C_ALI15X3=y
CONFIG_I2C_AMD756=y
CONFIG_I2C_AMD756_S4882=y
CONFIG_I2C_AMD8111=y
CONFIG_I2C_AMD_MP2=y
CONFIG_I2C_I801=y
CONFIG_I2C_ISCH=y
CONFIG_I2C_ISMT=y
CONFIG_I2C_PIIX4=y
CONFIG_I2C_CHT_WC=y
CONFIG_I2C_NFORCE2=y
CONFIG_I2C_NFORCE2_S4985=y
CONFIG_I2C_NVIDIA_GPU=y
CONFIG_I2C_SIS5595=y
CONFIG_I2C_SIS630=y
CONFIG_I2C_SIS96X=y
CONFIG_I2C_VIA=y
CONFIG_I2C_VIAPRO=y
#
# ACPI drivers
#
CONFIG_I2C_SCMI=y
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CBUS_GPIO=y
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_AMDPSP=y
CONFIG_I2C_DESIGNWARE_BAYTRAIL=y
CONFIG_I2C_DESIGNWARE_PCI=y
CONFIG_I2C_EG20T=y
CONFIG_I2C_EMEV2=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
CONFIG_I2C_KEMPLD=y
CONFIG_I2C_OCORES=y
CONFIG_I2C_PCA_PLATFORM=y
CONFIG_I2C_PXA=y
CONFIG_I2C_PXA_PCI=y
CONFIG_I2C_RK3X=y
CONFIG_I2C_SIMTEC=y
CONFIG_I2C_XILINX=y
#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=y
CONFIG_I2C_DLN2=y
CONFIG_I2C_CP2615=y
CONFIG_I2C_PARPORT=y
CONFIG_I2C_PCI1XXXX=y
CONFIG_I2C_ROBOTFUZZ_OSIF=y
CONFIG_I2C_TAOS_EVM=y
CONFIG_I2C_TINY_USB=y
CONFIG_I2C_VIPERBOARD=y
#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_PCA_ISA=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SCx200_ACB=y
CONFIG_I2C_FSI=y
CONFIG_I2C_VIRTIO=y
# end of I2C Hardware Bus support
CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=y
CONFIG_I2C_SLAVE_TESTUNIT=y
CONFIG_I2C_DEBUG_CORE=y
CONFIG_I2C_DEBUG_ALGO=y
CONFIG_I2C_DEBUG_BUS=y
# end of I2C support
CONFIG_I3C=y
CONFIG_CDNS_I3C_MASTER=y
CONFIG_DW_I3C_MASTER=y
CONFIG_SVC_I3C_MASTER=y
CONFIG_MIPI_I3C_HCI=y
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=y
CONFIG_SPI_ALTERA_CORE=y
CONFIG_SPI_ALTERA_DFL=y
CONFIG_SPI_AXI_SPI_ENGINE=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_BUTTERFLY=y
CONFIG_SPI_CADENCE=y
CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_SPI_CADENCE_XSPI=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_PCI=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_DLN2=y
CONFIG_SPI_FSI=y
CONFIG_SPI_NXP_FLEXSPI=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_INTEL=y
CONFIG_SPI_INTEL_PCI=y
CONFIG_SPI_INTEL_PLATFORM=y
CONFIG_SPI_LM70_LLP=y
CONFIG_SPI_FSL_LIB=y
CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_MICROCHIP_CORE=y
CONFIG_SPI_MICROCHIP_CORE_QSPI=y
CONFIG_SPI_LANTIQ_SSC=y
CONFIG_SPI_OC_TINY=y
CONFIG_SPI_PCI1XXXX=y
CONFIG_SPI_PXA2XX=y
CONFIG_SPI_PXA2XX_PCI=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_SC18IS602=y
CONFIG_SPI_SIFIVE=y
CONFIG_SPI_SN_F_OSPI=y
CONFIG_SPI_MXIC=y
CONFIG_SPI_TOPCLIFF_PCH=y
CONFIG_SPI_XCOMM=y
CONFIG_SPI_XILINX=y
CONFIG_SPI_ZYNQMP_GQSPI=y
CONFIG_SPI_AMD=y
#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=y
#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=y
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=y
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
CONFIG_SPMI_HISI3670=y
CONFIG_HSI=y
CONFIG_HSI_BOARDINFO=y
#
# HSI controllers
#
#
# HSI clients
#
CONFIG_HSI_CHAR=y
CONFIG_PPS=y
CONFIG_PPS_DEBUG=y
#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=y
CONFIG_PPS_CLIENT_LDISC=y
CONFIG_PPS_CLIENT_PARPORT=y
CONFIG_PPS_CLIENT_GPIO=y
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_DP83640_PHY=y
CONFIG_PTP_1588_CLOCK_INES=y
CONFIG_PTP_1588_CLOCK_PCH=y
CONFIG_PTP_1588_CLOCK_KVM=y
CONFIG_PTP_1588_CLOCK_IDT82P33=y
CONFIG_PTP_1588_CLOCK_IDTCM=y
CONFIG_PTP_1588_CLOCK_VMW=y
CONFIG_PTP_1588_CLOCK_OCP=y
# end of PTP clock support
CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_AS3722=y
CONFIG_PINCTRL_AXP209=y
CONFIG_PINCTRL_CY8C95X0=y
CONFIG_PINCTRL_DA9062=y
CONFIG_PINCTRL_EQUILIBRIUM=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_MCP23S08_I2C=y
CONFIG_PINCTRL_MCP23S08_SPI=y
CONFIG_PINCTRL_MCP23S08=y
CONFIG_PINCTRL_MICROCHIP_SGPIO=y
CONFIG_PINCTRL_OCELOT=y
CONFIG_PINCTRL_PALMAS=y
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=y
CONFIG_PINCTRL_SX150X=y
CONFIG_PINCTRL_LOCHNAGAR=y
CONFIG_PINCTRL_MADERA=y
CONFIG_PINCTRL_CS47L15=y
CONFIG_PINCTRL_CS47L35=y
CONFIG_PINCTRL_CS47L85=y
CONFIG_PINCTRL_CS47L90=y
CONFIG_PINCTRL_CS47L92=y
#
# Intel pinctrl drivers
#
CONFIG_PINCTRL_BAYTRAIL=y
CONFIG_PINCTRL_CHERRYVIEW=y
CONFIG_PINCTRL_LYNXPOINT=y
CONFIG_PINCTRL_MERRIFIELD=y
CONFIG_PINCTRL_MOOREFIELD=y
CONFIG_PINCTRL_INTEL=y
CONFIG_PINCTRL_ALDERLAKE=y
CONFIG_PINCTRL_BROXTON=y
CONFIG_PINCTRL_CANNONLAKE=y
CONFIG_PINCTRL_CEDARFORK=y
CONFIG_PINCTRL_DENVERTON=y
CONFIG_PINCTRL_ELKHARTLAKE=y
CONFIG_PINCTRL_EMMITSBURG=y
CONFIG_PINCTRL_GEMINILAKE=y
CONFIG_PINCTRL_ICELAKE=y
CONFIG_PINCTRL_JASPERLAKE=y
CONFIG_PINCTRL_LAKEFIELD=y
CONFIG_PINCTRL_LEWISBURG=y
CONFIG_PINCTRL_METEORLAKE=y
CONFIG_PINCTRL_SUNRISEPOINT=y
CONFIG_PINCTRL_TIGERLAKE=y
# end of Intel pinctrl drivers
#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=y
CONFIG_GPIO_IDIO_16=y
#
# Memory mapped GPIO drivers
#
CONFIG_GPIO_74XX_MMIO=y
CONFIG_GPIO_ALTERA=y
CONFIG_GPIO_AMDPT=y
CONFIG_GPIO_CADENCE=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_EXAR=y
CONFIG_GPIO_FTGPIO010=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_GRGPIO=y
CONFIG_GPIO_HLWD=y
CONFIG_GPIO_ICH=y
CONFIG_GPIO_LOGICVC=y
CONFIG_GPIO_MB86S7X=y
CONFIG_GPIO_MENZ127=y
CONFIG_GPIO_SIFIVE=y
CONFIG_GPIO_SIOX=y
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_VX855=y
CONFIG_GPIO_WCD934X=y
CONFIG_GPIO_XILINX=y
CONFIG_GPIO_AMD_FCH=y
# end of Memory mapped GPIO drivers
#
# Port-mapped I/O GPIO drivers
#
CONFIG_GPIO_I8255=y
CONFIG_GPIO_104_DIO_48E=y
CONFIG_GPIO_104_IDIO_16=y
CONFIG_GPIO_104_IDI_48=y
CONFIG_GPIO_F7188X=y
CONFIG_GPIO_GPIO_MM=y
CONFIG_GPIO_IT87=y
CONFIG_GPIO_SCH=y
CONFIG_GPIO_SCH311X=y
CONFIG_GPIO_WINBOND=y
CONFIG_GPIO_WS16C48=y
# end of Port-mapped I/O GPIO drivers
#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=y
CONFIG_GPIO_GW_PLD=y
CONFIG_GPIO_MAX7300=y
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_MAX732X_IRQ=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCA9570=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TPIC2810=y
# end of I2C GPIO expanders
#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=y
CONFIG_GPIO_ARIZONA=y
CONFIG_GPIO_BD71815=y
CONFIG_GPIO_BD71828=y
CONFIG_GPIO_BD9571MWV=y
CONFIG_GPIO_CRYSTAL_COVE=y
CONFIG_GPIO_CS5535=y
CONFIG_GPIO_DA9052=y
CONFIG_GPIO_DA9055=y
CONFIG_GPIO_DLN2=y
CONFIG_GPIO_JANZ_TTL=y
CONFIG_GPIO_KEMPLD=y
CONFIG_GPIO_LP3943=y
CONFIG_GPIO_LP873X=y
CONFIG_GPIO_LP87565=y
CONFIG_GPIO_MADERA=y
CONFIG_GPIO_MAX77620=y
CONFIG_GPIO_MAX77650=y
CONFIG_GPIO_PALMAS=y
CONFIG_GPIO_RC5T583=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TC3589X=y
CONFIG_GPIO_TIMBERDALE=y
CONFIG_GPIO_TPS65086=y
CONFIG_GPIO_TPS65218=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_GPIO_TPS65912=y
CONFIG_GPIO_TPS68470=y
CONFIG_GPIO_TQMX86=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_TWL6040=y
CONFIG_GPIO_UCB1400=y
CONFIG_GPIO_WHISKEY_COVE=y
CONFIG_GPIO_WM831X=y
CONFIG_GPIO_WM8350=y
CONFIG_GPIO_WM8994=y
# end of MFD GPIO expanders
#
# PCI GPIO expanders
#
CONFIG_GPIO_AMD8111=y
CONFIG_GPIO_MERRIFIELD=y
CONFIG_GPIO_ML_IOH=y
CONFIG_GPIO_PCH=y
CONFIG_GPIO_PCI_IDIO_16=y
CONFIG_GPIO_PCIE_IDIO_24=y
CONFIG_GPIO_RDC321X=y
CONFIG_GPIO_SODAVILLE=y
# end of PCI GPIO expanders
#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=y
CONFIG_GPIO_MAX3191X=y
CONFIG_GPIO_MAX7301=y
CONFIG_GPIO_MC33880=y
CONFIG_GPIO_PISOSR=y
CONFIG_GPIO_XRA1403=y
CONFIG_GPIO_MOXTET=y
# end of SPI GPIO expanders
#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=y
# end of USB GPIO expanders
#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=y
CONFIG_GPIO_LATCH=y
CONFIG_GPIO_MOCKUP=y
CONFIG_GPIO_VIRTIO=y
CONFIG_GPIO_SIM=y
# end of Virtual GPIO drivers
CONFIG_W1=y
CONFIG_W1_CON=y
#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=y
CONFIG_W1_MASTER_DS2490=y
CONFIG_W1_MASTER_DS2482=y
CONFIG_W1_MASTER_DS1WM=y
CONFIG_W1_MASTER_GPIO=y
CONFIG_W1_MASTER_SGI=y
# end of 1-wire Bus Masters
#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=y
CONFIG_W1_SLAVE_SMEM=y
CONFIG_W1_SLAVE_DS2405=y
CONFIG_W1_SLAVE_DS2408=y
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=y
CONFIG_W1_SLAVE_DS2406=y
CONFIG_W1_SLAVE_DS2423=y
CONFIG_W1_SLAVE_DS2805=y
CONFIG_W1_SLAVE_DS2430=y
CONFIG_W1_SLAVE_DS2431=y
CONFIG_W1_SLAVE_DS2433=y
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=y
CONFIG_W1_SLAVE_DS250X=y
CONFIG_W1_SLAVE_DS2780=y
CONFIG_W1_SLAVE_DS2781=y
CONFIG_W1_SLAVE_DS28E04=y
CONFIG_W1_SLAVE_DS28E17=y
# end of 1-wire Slaves
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_ATC260X=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_LTC2952=y
CONFIG_POWER_RESET_MT6323=y
CONFIG_POWER_RESET_REGULATOR=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_TPS65086=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PDA_POWER=y
CONFIG_GENERIC_ADC_BATTERY=y
CONFIG_IP5XXX_POWER=y
CONFIG_MAX8925_POWER=y
CONFIG_WM831X_BACKUP=y
CONFIG_WM831X_POWER=y
CONFIG_WM8350_POWER=y
CONFIG_TEST_POWER=y
CONFIG_BATTERY_88PM860X=y
CONFIG_CHARGER_ADP5061=y
CONFIG_BATTERY_ACT8945A=y
CONFIG_BATTERY_CPCAP=y
CONFIG_BATTERY_CW2015=y
CONFIG_BATTERY_DS2760=y
CONFIG_BATTERY_DS2780=y
CONFIG_BATTERY_DS2781=y
CONFIG_BATTERY_DS2782=y
CONFIG_BATTERY_OLPC=y
CONFIG_BATTERY_SAMSUNG_SDI=y
CONFIG_BATTERY_WM97XX=y
CONFIG_BATTERY_SBS=y
CONFIG_CHARGER_SBS=y
CONFIG_MANAGER_SBS=y
CONFIG_BATTERY_BQ27XXX=y
CONFIG_BATTERY_BQ27XXX_I2C=y
CONFIG_BATTERY_BQ27XXX_HDQ=y
CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
CONFIG_BATTERY_DA9030=y
CONFIG_BATTERY_DA9052=y
CONFIG_CHARGER_DA9150=y
CONFIG_BATTERY_DA9150=y
CONFIG_CHARGER_AXP20X=y
CONFIG_BATTERY_AXP20X=y
CONFIG_AXP20X_POWER=y
CONFIG_AXP288_CHARGER=y
CONFIG_AXP288_FUEL_GAUGE=y
CONFIG_BATTERY_MAX17040=y
CONFIG_BATTERY_MAX17042=y
CONFIG_BATTERY_MAX1721X=y
CONFIG_BATTERY_TWL4030_MADC=y
CONFIG_CHARGER_88PM860X=y
CONFIG_CHARGER_PCF50633=y
CONFIG_BATTERY_RX51=y
CONFIG_CHARGER_ISP1704=y
CONFIG_CHARGER_MAX8903=y
CONFIG_CHARGER_TWL4030=y
CONFIG_CHARGER_LP8727=y
CONFIG_CHARGER_LP8788=y
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_MANAGER=y
CONFIG_CHARGER_LT3651=y
CONFIG_CHARGER_LTC4162L=y
CONFIG_CHARGER_MAX14577=y
CONFIG_CHARGER_DETECTOR_MAX14656=y
CONFIG_CHARGER_MAX77650=y
CONFIG_CHARGER_MAX77693=y
CONFIG_CHARGER_MAX77976=y
CONFIG_CHARGER_MAX8997=y
CONFIG_CHARGER_MAX8998=y
CONFIG_CHARGER_MP2629=y
CONFIG_CHARGER_MT6360=y
CONFIG_CHARGER_MT6370=y
CONFIG_CHARGER_BQ2415X=y
CONFIG_CHARGER_BQ24190=y
CONFIG_CHARGER_BQ24257=y
CONFIG_CHARGER_BQ24735=y
CONFIG_CHARGER_BQ2515X=y
CONFIG_CHARGER_BQ25890=y
CONFIG_CHARGER_BQ25980=y
CONFIG_CHARGER_BQ256XX=y
CONFIG_CHARGER_RK817=y
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65090=y
CONFIG_CHARGER_TPS65217=y
CONFIG_BATTERY_GAUGE_LTC2941=y
CONFIG_BATTERY_GOLDFISH=y
CONFIG_BATTERY_RT5033=y
CONFIG_CHARGER_RT9455=y
CONFIG_CHARGER_CROS_USBPD=y
CONFIG_CHARGER_CROS_PCHG=y
CONFIG_CHARGER_UCS1002=y
CONFIG_CHARGER_BD99954=y
CONFIG_CHARGER_WILCO=y
CONFIG_RN5T618_POWER=y
CONFIG_BATTERY_SURFACE=y
CONFIG_CHARGER_SURFACE=y
CONFIG_BATTERY_UG3105=y
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
CONFIG_HWMON_DEBUG_CHIP=y
#
# Native drivers
#
CONFIG_SENSORS_ABITUGURU=y
CONFIG_SENSORS_ABITUGURU3=y
CONFIG_SENSORS_SMPRO=y
CONFIG_SENSORS_AD7314=y
CONFIG_SENSORS_AD7414=y
CONFIG_SENSORS_AD7418=y
CONFIG_SENSORS_ADM1025=y
CONFIG_SENSORS_ADM1026=y
CONFIG_SENSORS_ADM1029=y
CONFIG_SENSORS_ADM1031=y
CONFIG_SENSORS_ADM1177=y
CONFIG_SENSORS_ADM9240=y
CONFIG_SENSORS_ADT7X10=y
CONFIG_SENSORS_ADT7310=y
CONFIG_SENSORS_ADT7410=y
CONFIG_SENSORS_ADT7411=y
CONFIG_SENSORS_ADT7462=y
CONFIG_SENSORS_ADT7470=y
CONFIG_SENSORS_ADT7475=y
CONFIG_SENSORS_AHT10=y
CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=y
CONFIG_SENSORS_AS370=y
CONFIG_SENSORS_ASC7621=y
CONFIG_SENSORS_AXI_FAN_CONTROL=y
CONFIG_SENSORS_K8TEMP=y
CONFIG_SENSORS_K10TEMP=y
CONFIG_SENSORS_FAM15H_POWER=y
CONFIG_SENSORS_APPLESMC=y
CONFIG_SENSORS_ASB100=y
CONFIG_SENSORS_ATXP1=y
CONFIG_SENSORS_CORSAIR_CPRO=y
CONFIG_SENSORS_CORSAIR_PSU=y
CONFIG_SENSORS_DRIVETEMP=y
CONFIG_SENSORS_DS620=y
CONFIG_SENSORS_DS1621=y
CONFIG_SENSORS_DELL_SMM=y
CONFIG_I8K=y
CONFIG_SENSORS_DA9052_ADC=y
CONFIG_SENSORS_DA9055=y
CONFIG_SENSORS_I5K_AMB=y
CONFIG_SENSORS_F71805F=y
CONFIG_SENSORS_F71882FG=y
CONFIG_SENSORS_F75375S=y
CONFIG_SENSORS_GSC=y
CONFIG_SENSORS_MC13783_ADC=y
CONFIG_SENSORS_FSCHMD=y
CONFIG_SENSORS_FTSTEUTATES=y
CONFIG_SENSORS_GL518SM=y
CONFIG_SENSORS_GL520SM=y
CONFIG_SENSORS_G760A=y
CONFIG_SENSORS_G762=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_HIH6130=y
CONFIG_SENSORS_IBMAEM=y
CONFIG_SENSORS_IBMPEX=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_SENSORS_I5500=y
CONFIG_SENSORS_CORETEMP=y
CONFIG_SENSORS_IT87=y
CONFIG_SENSORS_JC42=y
CONFIG_SENSORS_POWR1220=y
CONFIG_SENSORS_LINEAGE=y
CONFIG_SENSORS_LOCHNAGAR=y
CONFIG_SENSORS_LTC2945=y
CONFIG_SENSORS_LTC2947=y
CONFIG_SENSORS_LTC2947_I2C=y
CONFIG_SENSORS_LTC2947_SPI=y
CONFIG_SENSORS_LTC2990=y
CONFIG_SENSORS_LTC2992=y
CONFIG_SENSORS_LTC4151=y
CONFIG_SENSORS_LTC4215=y
CONFIG_SENSORS_LTC4222=y
CONFIG_SENSORS_LTC4245=y
CONFIG_SENSORS_LTC4260=y
CONFIG_SENSORS_LTC4261=y
CONFIG_SENSORS_MAX1111=y
CONFIG_SENSORS_MAX127=y
CONFIG_SENSORS_MAX16065=y
CONFIG_SENSORS_MAX1619=y
CONFIG_SENSORS_MAX1668=y
CONFIG_SENSORS_MAX197=y
CONFIG_SENSORS_MAX31722=y
CONFIG_SENSORS_MAX31730=y
CONFIG_SENSORS_MAX31760=y
CONFIG_SENSORS_MAX6620=y
CONFIG_SENSORS_MAX6621=y
CONFIG_SENSORS_MAX6639=y
CONFIG_SENSORS_MAX6650=y
CONFIG_SENSORS_MAX6697=y
CONFIG_SENSORS_MAX31790=y
CONFIG_SENSORS_MCP3021=y
CONFIG_SENSORS_MLXREG_FAN=y
CONFIG_SENSORS_TC654=y
CONFIG_SENSORS_TPS23861=y
CONFIG_SENSORS_MENF21BMC_HWMON=y
CONFIG_SENSORS_MR75203=y
CONFIG_SENSORS_ADCXX=y
CONFIG_SENSORS_LM63=y
CONFIG_SENSORS_LM70=y
CONFIG_SENSORS_LM73=y
CONFIG_SENSORS_LM75=y
CONFIG_SENSORS_LM77=y
CONFIG_SENSORS_LM78=y
CONFIG_SENSORS_LM80=y
CONFIG_SENSORS_LM83=y
CONFIG_SENSORS_LM85=y
CONFIG_SENSORS_LM87=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_SENSORS_LM93=y
CONFIG_SENSORS_LM95234=y
CONFIG_SENSORS_LM95241=y
CONFIG_SENSORS_LM95245=y
CONFIG_SENSORS_PC87360=y
CONFIG_SENSORS_PC87427=y
CONFIG_SENSORS_NTC_THERMISTOR=y
CONFIG_SENSORS_NCT6683=y
CONFIG_SENSORS_NCT6775_CORE=y
CONFIG_SENSORS_NCT6775=y
CONFIG_SENSORS_NCT6775_I2C=y
CONFIG_SENSORS_NCT7802=y
CONFIG_SENSORS_NCT7904=y
CONFIG_SENSORS_NPCM7XX=y
CONFIG_SENSORS_NZXT_KRAKEN2=y
CONFIG_SENSORS_NZXT_SMART2=y
CONFIG_SENSORS_OCC_P8_I2C=y
CONFIG_SENSORS_OCC_P9_SBE=y
CONFIG_SENSORS_OCC=y
CONFIG_SENSORS_OXP=y
CONFIG_SENSORS_PCF8591=y
CONFIG_SENSORS_PECI_CPUTEMP=y
CONFIG_SENSORS_PECI_DIMMTEMP=y
CONFIG_SENSORS_PECI=y
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
CONFIG_SENSORS_ADM1266=y
CONFIG_SENSORS_ADM1275=y
CONFIG_SENSORS_BEL_PFE=y
CONFIG_SENSORS_BPA_RS600=y
CONFIG_SENSORS_DELTA_AHE50DC_FAN=y
CONFIG_SENSORS_FSP_3Y=y
CONFIG_SENSORS_IBM_CFFPS=y
CONFIG_SENSORS_DPS920AB=y
CONFIG_SENSORS_INSPUR_IPSPS=y
CONFIG_SENSORS_IR35221=y
CONFIG_SENSORS_IR36021=y
CONFIG_SENSORS_IR38064=y
CONFIG_SENSORS_IR38064_REGULATOR=y
CONFIG_SENSORS_IRPS5401=y
CONFIG_SENSORS_ISL68137=y
CONFIG_SENSORS_LM25066=y
CONFIG_SENSORS_LM25066_REGULATOR=y
CONFIG_SENSORS_LT7182S=y
CONFIG_SENSORS_LTC2978=y
CONFIG_SENSORS_LTC2978_REGULATOR=y
CONFIG_SENSORS_LTC3815=y
CONFIG_SENSORS_MAX15301=y
CONFIG_SENSORS_MAX16064=y
CONFIG_SENSORS_MAX16601=y
CONFIG_SENSORS_MAX20730=y
CONFIG_SENSORS_MAX20751=y
CONFIG_SENSORS_MAX31785=y
CONFIG_SENSORS_MAX34440=y
CONFIG_SENSORS_MAX8688=y
CONFIG_SENSORS_MP2888=y
CONFIG_SENSORS_MP2975=y
CONFIG_SENSORS_MP5023=y
CONFIG_SENSORS_PIM4328=y
CONFIG_SENSORS_PLI1209BC=y
CONFIG_SENSORS_PLI1209BC_REGULATOR=y
CONFIG_SENSORS_PM6764TR=y
CONFIG_SENSORS_PXE1610=y
CONFIG_SENSORS_Q54SJ108A2=y
CONFIG_SENSORS_STPDDC60=y
CONFIG_SENSORS_TPS40422=y
CONFIG_SENSORS_TPS53679=y
CONFIG_SENSORS_TPS546D24=y
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=y
CONFIG_SENSORS_XDPE152=y
CONFIG_SENSORS_XDPE122=y
CONFIG_SENSORS_XDPE122_REGULATOR=y
CONFIG_SENSORS_ZL6100=y
CONFIG_SENSORS_PWM_FAN=y
CONFIG_SENSORS_SBTSI=y
CONFIG_SENSORS_SBRMI=y
CONFIG_SENSORS_SHT15=y
CONFIG_SENSORS_SHT21=y
CONFIG_SENSORS_SHT3x=y
CONFIG_SENSORS_SHT4x=y
CONFIG_SENSORS_SHTC1=y
CONFIG_SENSORS_SIS5595=y
CONFIG_SENSORS_SY7636A=y
CONFIG_SENSORS_DME1737=y
CONFIG_SENSORS_EMC1403=y
CONFIG_SENSORS_EMC2103=y
CONFIG_SENSORS_EMC2305=y
CONFIG_SENSORS_EMC6W201=y
CONFIG_SENSORS_SMSC47M1=y
CONFIG_SENSORS_SMSC47M192=y
CONFIG_SENSORS_SMSC47B397=y
CONFIG_SENSORS_SCH56XX_COMMON=y
CONFIG_SENSORS_SCH5627=y
CONFIG_SENSORS_SCH5636=y
CONFIG_SENSORS_STTS751=y
CONFIG_SENSORS_SMM665=y
CONFIG_SENSORS_ADC128D818=y
CONFIG_SENSORS_ADS7828=y
CONFIG_SENSORS_ADS7871=y
CONFIG_SENSORS_AMC6821=y
CONFIG_SENSORS_INA209=y
CONFIG_SENSORS_INA2XX=y
CONFIG_SENSORS_INA238=y
CONFIG_SENSORS_INA3221=y
CONFIG_SENSORS_TC74=y
CONFIG_SENSORS_THMC50=y
CONFIG_SENSORS_TMP102=y
CONFIG_SENSORS_TMP103=y
CONFIG_SENSORS_TMP108=y
CONFIG_SENSORS_TMP401=y
CONFIG_SENSORS_TMP421=y
CONFIG_SENSORS_TMP464=y
CONFIG_SENSORS_TMP513=y
CONFIG_SENSORS_VIA_CPUTEMP=y
CONFIG_SENSORS_VIA686A=y
CONFIG_SENSORS_VT1211=y
CONFIG_SENSORS_VT8231=y
CONFIG_SENSORS_W83773G=y
CONFIG_SENSORS_W83781D=y
CONFIG_SENSORS_W83791D=y
CONFIG_SENSORS_W83792D=y
CONFIG_SENSORS_W83793=y
CONFIG_SENSORS_W83795=y
CONFIG_SENSORS_W83795_FANCTRL=y
CONFIG_SENSORS_W83L785TS=y
CONFIG_SENSORS_W83L786NG=y
CONFIG_SENSORS_W83627HF=y
CONFIG_SENSORS_W83627EHF=y
CONFIG_SENSORS_WM831X=y
CONFIG_SENSORS_WM8350=y
CONFIG_SENSORS_XGENE=y
CONFIG_SENSORS_INTEL_M10_BMC_HWMON=y
#
# ACPI drivers
#
CONFIG_SENSORS_ACPI_POWER=y
CONFIG_SENSORS_ATK0110=y
CONFIG_SENSORS_ASUS_WMI=y
CONFIG_SENSORS_ASUS_EC=y
CONFIG_THERMAL=y
CONFIG_THERMAL_NETLINK=y
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_CPU_IDLE_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_MMIO=y
CONFIG_MAX77620_THERMAL=y
CONFIG_DA9062_THERMAL=y
#
# Intel thermal drivers
#
CONFIG_INTEL_POWERCLAMP=y
CONFIG_X86_THERMAL_VECTOR=y
CONFIG_X86_PKG_TEMP_THERMAL=y
CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
CONFIG_INTEL_SOC_DTS_THERMAL=y
CONFIG_INTEL_QUARK_DTS_THERMAL=y
#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers
CONFIG_INTEL_BXT_PMIC_THERMAL=y
CONFIG_INTEL_PCH_THERMAL=y
CONFIG_INTEL_TCC_COOLING=y
CONFIG_INTEL_MENLOW=y
CONFIG_INTEL_HFI_THERMAL=y
# end of Intel thermal drivers
# CONFIG_TI_SOC_THERMAL is not set
CONFIG_GENERIC_ADC_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
CONFIG_WATCHDOG_SYSFS=y
CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y
#
# Watchdog Pretimeout Governors
#
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=y
CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y
CONFIG_BD957XMUF_WATCHDOG=y
CONFIG_DA9052_WATCHDOG=y
CONFIG_DA9055_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=y
CONFIG_DA9062_WATCHDOG=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_MENF21BMC_WATCHDOG=y
CONFIG_MENZ069_WATCHDOG=y
CONFIG_WDAT_WDT=y
CONFIG_WM831X_WATCHDOG=y
CONFIG_WM8350_WATCHDOG=y
CONFIG_XILINX_WATCHDOG=y
CONFIG_ZIIRAVE_WATCHDOG=y
CONFIG_RAVE_SP_WATCHDOG=y
CONFIG_MLX_WDT=y
CONFIG_CADENCE_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_RN5T618_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
CONFIG_MAX63XX_WATCHDOG=y
CONFIG_MAX77620_WATCHDOG=y
CONFIG_RETU_WATCHDOG=y
CONFIG_STPMIC1_WATCHDOG=y
CONFIG_ACQUIRE_WDT=y
CONFIG_ADVANTECH_WDT=y
CONFIG_ADVANTECH_EC_WDT=y
CONFIG_ALIM1535_WDT=y
CONFIG_ALIM7101_WDT=y
CONFIG_EBC_C384_WDT=y
CONFIG_EXAR_WDT=y
CONFIG_F71808E_WDT=y
CONFIG_SP5100_TCO=y
CONFIG_GEODE_WDT=y
CONFIG_SBC_FITPC2_WATCHDOG=y
CONFIG_EUROTECH_WDT=y
CONFIG_IB700_WDT=y
CONFIG_IBMASR=y
CONFIG_WAFER_WDT=y
CONFIG_I6300ESB_WDT=y
CONFIG_IE6XX_WDT=y
CONFIG_INTEL_MID_WATCHDOG=y
CONFIG_ITCO_WDT=y
CONFIG_ITCO_VENDOR_SUPPORT=y
CONFIG_IT8712F_WDT=y
CONFIG_IT87_WDT=y
CONFIG_HP_WATCHDOG=y
CONFIG_HPWDT_NMI_DECODING=y
CONFIG_KEMPLD_WDT=y
CONFIG_SC1200_WDT=y
CONFIG_SCx200_WDT=y
CONFIG_PC87413_WDT=y
CONFIG_NV_TCO=y
CONFIG_RDC321X_WDT=y
CONFIG_60XX_WDT=y
CONFIG_SBC8360_WDT=y
CONFIG_SBC7240_WDT=y
CONFIG_CPU5_WDT=y
CONFIG_SMSC_SCH311X_WDT=y
CONFIG_SMSC37B787_WDT=y
CONFIG_TQMX86_WDT=y
CONFIG_VIA_WDT=y
CONFIG_W83627HF_WDT=y
CONFIG_W83877F_WDT=y
CONFIG_W83977F_WDT=y
CONFIG_MACHZ_WDT=y
CONFIG_SBC_EPX_C3_WATCHDOG=y
CONFIG_INTEL_MEI_WDT=y
CONFIG_NI903X_WDT=y
CONFIG_NIC7018_WDT=y
CONFIG_SIEMENS_SIMATIC_IPC_WDT=y
CONFIG_MEN_A21_WDT=y
#
# ISA-based Watchdog Cards
#
CONFIG_PCWATCHDOG=y
CONFIG_MIXCOMWD=y
CONFIG_WDT=y
#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=y
CONFIG_WDTPCI=y
#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=y
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=y
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
CONFIG_SSB_PCMCIAHOST=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=y
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y
#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_CS5535=y
CONFIG_MFD_ACT8945A=y
CONFIG_MFD_AS3711=y
CONFIG_MFD_SMPRO=y
CONFIG_MFD_AS3722=y
CONFIG_PMIC_ADP5520=y
CONFIG_MFD_AAT2870_CORE=y
CONFIG_MFD_ATMEL_FLEXCOM=y
CONFIG_MFD_ATMEL_HLCDC=y
CONFIG_MFD_BCM590XX=y
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_CROS_EC_DEV=y
CONFIG_MFD_MADERA=y
CONFIG_MFD_MADERA_I2C=y
CONFIG_MFD_MADERA_SPI=y
CONFIG_MFD_CS47L15=y
CONFIG_MFD_CS47L35=y
CONFIG_MFD_CS47L85=y
CONFIG_MFD_CS47L90=y
CONFIG_MFD_CS47L92=y
CONFIG_PMIC_DA903X=y
CONFIG_PMIC_DA9052=y
CONFIG_MFD_DA9052_SPI=y
CONFIG_MFD_DA9052_I2C=y
CONFIG_MFD_DA9055=y
CONFIG_MFD_DA9062=y
CONFIG_MFD_DA9063=y
CONFIG_MFD_DA9150=y
CONFIG_MFD_DLN2=y
CONFIG_MFD_GATEWORKS_GSC=y
CONFIG_MFD_MC13XXX=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_MFD_MP2629=y
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_HI6421_SPMI=y
CONFIG_HTC_PASIC3=y
CONFIG_MFD_INTEL_QUARK_I2C_GPIO=y
CONFIG_LPC_ICH=y
CONFIG_LPC_SCH=y
CONFIG_INTEL_SOC_PMIC=y
CONFIG_INTEL_SOC_PMIC_BXTWC=y
CONFIG_INTEL_SOC_PMIC_CHTWC=y
CONFIG_INTEL_SOC_PMIC_CHTDC_TI=y
CONFIG_INTEL_SOC_PMIC_MRFLD=y
CONFIG_MFD_INTEL_LPSS=y
CONFIG_MFD_INTEL_LPSS_ACPI=y
CONFIG_MFD_INTEL_LPSS_PCI=y
CONFIG_MFD_INTEL_PMC_BXT=y
CONFIG_MFD_IQS62X=y
CONFIG_MFD_JANZ_CMODIO=y
CONFIG_MFD_KEMPLD=y
CONFIG_MFD_88PM800=y
CONFIG_MFD_88PM805=y
CONFIG_MFD_88PM860X=y
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77620=y
CONFIG_MFD_MAX77650=y
CONFIG_MFD_MAX77686=y
CONFIG_MFD_MAX77693=y
CONFIG_MFD_MAX77714=y
CONFIG_MFD_MAX77843=y
CONFIG_MFD_MAX8907=y
CONFIG_MFD_MAX8925=y
CONFIG_MFD_MAX8997=y
CONFIG_MFD_MAX8998=y
CONFIG_MFD_MT6360=y
CONFIG_MFD_MT6370=y
CONFIG_MFD_MT6397=y
CONFIG_MFD_MENF21BMC=y
CONFIG_MFD_OCELOT=y
CONFIG_EZX_PCAP=y
CONFIG_MFD_CPCAP=y
CONFIG_MFD_VIPERBOARD=y
CONFIG_MFD_NTXEC=y
CONFIG_MFD_RETU=y
CONFIG_MFD_PCF50633=y
CONFIG_PCF50633_ADC=y
CONFIG_PCF50633_GPIO=y
CONFIG_UCB1400_CORE=y
CONFIG_MFD_SY7636A=y
CONFIG_MFD_RDC321X=y
CONFIG_MFD_RT4831=y
CONFIG_MFD_RT5033=y
CONFIG_MFD_RT5120=y
CONFIG_MFD_RC5T583=y
CONFIG_MFD_RK808=y
CONFIG_MFD_RN5T618=y
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SI476X_CORE=y
CONFIG_MFD_SIMPLE_MFD_I2C=y
CONFIG_MFD_SM501=y
CONFIG_MFD_SM501_GPIO=y
CONFIG_MFD_SKY81452=y
CONFIG_MFD_STMPE=y
#
# STMicroelectronics STMPE Interface Drivers
#
CONFIG_STMPE_I2C=y
CONFIG_STMPE_SPI=y
# end of STMicroelectronics STMPE Interface Drivers
CONFIG_MFD_STA2X11=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=y
CONFIG_MFD_LP3943=y
CONFIG_MFD_LP8788=y
CONFIG_MFD_TI_LMU=y
CONFIG_MFD_PALMAS=y
CONFIG_TPS6105X=y
CONFIG_TPS65010=y
CONFIG_TPS6507X=y
CONFIG_MFD_TPS65086=y
CONFIG_MFD_TPS65090=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TI_LP873X=y
CONFIG_MFD_TI_LP87565=y
CONFIG_MFD_TPS65218=y
CONFIG_MFD_TPS65219=y
CONFIG_MFD_TPS6586X=y
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TPS65912=y
CONFIG_MFD_TPS65912_I2C=y
CONFIG_MFD_TPS65912_SPI=y
CONFIG_TWL4030_CORE=y
CONFIG_MFD_TWL4030_AUDIO=y
CONFIG_TWL6040_CORE=y
CONFIG_MFD_WL1273_CORE=y
CONFIG_MFD_LM3533=y
CONFIG_MFD_TIMBERDALE=y
CONFIG_MFD_TC3589X=y
CONFIG_MFD_TQMX86=y
CONFIG_MFD_VX855=y
CONFIG_MFD_LOCHNAGAR=y
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=y
CONFIG_MFD_ARIZONA_SPI=y
CONFIG_MFD_CS47L24=y
CONFIG_MFD_WM5102=y
CONFIG_MFD_WM5110=y
CONFIG_MFD_WM8997=y
CONFIG_MFD_WM8998=y
CONFIG_MFD_WM8400=y
CONFIG_MFD_WM831X=y
CONFIG_MFD_WM831X_I2C=y
CONFIG_MFD_WM831X_SPI=y
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=y
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_ROHM_BD71828=y
CONFIG_MFD_ROHM_BD957XMUF=y
CONFIG_MFD_STPMIC1=y
CONFIG_MFD_STMFX=y
CONFIG_MFD_WCD934X=y
CONFIG_MFD_ATC260X=y
CONFIG_MFD_ATC260X_I2C=y
CONFIG_MFD_QCOM_PM8008=y
CONFIG_RAVE_SP_CORE=y
CONFIG_MFD_INTEL_M10_BMC=y
CONFIG_MFD_RSMU_I2C=y
CONFIG_MFD_RSMU_SPI=y
# end of Multifunction device drivers
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
CONFIG_REGULATOR_88PG86X=y
CONFIG_REGULATOR_88PM800=y
CONFIG_REGULATOR_88PM8607=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_REGULATOR_ACT8945A=y
CONFIG_REGULATOR_AD5398=y
CONFIG_REGULATOR_AAT2870=y
CONFIG_REGULATOR_ARIZONA_LDO1=y
CONFIG_REGULATOR_ARIZONA_MICSUPP=y
CONFIG_REGULATOR_AS3711=y
CONFIG_REGULATOR_AS3722=y
CONFIG_REGULATOR_ATC260X=y
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BCM590XX=y
CONFIG_REGULATOR_BD71815=y
CONFIG_REGULATOR_BD71828=y
CONFIG_REGULATOR_BD718XX=y
CONFIG_REGULATOR_BD9571MWV=y
CONFIG_REGULATOR_BD957XMUF=y
CONFIG_REGULATOR_CPCAP=y
CONFIG_REGULATOR_CROS_EC=y
CONFIG_REGULATOR_DA903X=y
CONFIG_REGULATOR_DA9052=y
CONFIG_REGULATOR_DA9055=y
CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_DA9063=y
CONFIG_REGULATOR_DA9121=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_DA9211=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_HI6421=y
CONFIG_REGULATOR_HI6421V530=y
CONFIG_REGULATOR_HI6421V600=y
CONFIG_REGULATOR_ISL9305=y
CONFIG_REGULATOR_ISL6271A=y
CONFIG_REGULATOR_LM363X=y
CONFIG_REGULATOR_LOCHNAGAR=y
CONFIG_REGULATOR_LP3971=y
CONFIG_REGULATOR_LP3972=y
CONFIG_REGULATOR_LP872X=y
CONFIG_REGULATOR_LP873X=y
CONFIG_REGULATOR_LP8755=y
CONFIG_REGULATOR_LP87565=y
CONFIG_REGULATOR_LP8788=y
CONFIG_REGULATOR_LTC3589=y
CONFIG_REGULATOR_LTC3676=y
CONFIG_REGULATOR_MAX14577=y
CONFIG_REGULATOR_MAX1586=y
CONFIG_REGULATOR_MAX77620=y
CONFIG_REGULATOR_MAX77650=y
CONFIG_REGULATOR_MAX8649=y
CONFIG_REGULATOR_MAX8660=y
CONFIG_REGULATOR_MAX8893=y
CONFIG_REGULATOR_MAX8907=y
CONFIG_REGULATOR_MAX8925=y
CONFIG_REGULATOR_MAX8952=y
CONFIG_REGULATOR_MAX8973=y
CONFIG_REGULATOR_MAX8997=y
CONFIG_REGULATOR_MAX8998=y
CONFIG_REGULATOR_MAX20086=y
CONFIG_REGULATOR_MAX77686=y
CONFIG_REGULATOR_MAX77693=y
CONFIG_REGULATOR_MAX77802=y
CONFIG_REGULATOR_MAX77826=y
CONFIG_REGULATOR_MC13XXX_CORE=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_MCP16502=y
CONFIG_REGULATOR_MP5416=y
CONFIG_REGULATOR_MP8859=y
CONFIG_REGULATOR_MP886X=y
CONFIG_REGULATOR_MPQ7920=y
CONFIG_REGULATOR_MT6311=y
CONFIG_REGULATOR_MT6315=y
CONFIG_REGULATOR_MT6323=y
CONFIG_REGULATOR_MT6331=y
CONFIG_REGULATOR_MT6332=y
CONFIG_REGULATOR_MT6357=y
CONFIG_REGULATOR_MT6358=y
CONFIG_REGULATOR_MT6359=y
CONFIG_REGULATOR_MT6360=y
CONFIG_REGULATOR_MT6370=y
CONFIG_REGULATOR_MT6397=y
CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_PCA9450=y
CONFIG_REGULATOR_PCAP=y
CONFIG_REGULATOR_PCF50633=y
CONFIG_REGULATOR_PF8X00=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_REGULATOR_PV88060=y
CONFIG_REGULATOR_PV88080=y
CONFIG_REGULATOR_PV88090=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_SPMI=y
CONFIG_REGULATOR_QCOM_USB_VBUS=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y
CONFIG_REGULATOR_RC5T583=y
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RN5T618=y
CONFIG_REGULATOR_ROHM=y
CONFIG_REGULATOR_RT4801=y
CONFIG_REGULATOR_RT4831=y
CONFIG_REGULATOR_RT5033=y
CONFIG_REGULATOR_RT5120=y
CONFIG_REGULATOR_RT5190A=y
CONFIG_REGULATOR_RT5759=y
CONFIG_REGULATOR_RT6160=y
CONFIG_REGULATOR_RT6190=y
CONFIG_REGULATOR_RT6245=y
CONFIG_REGULATOR_RTQ2134=y
CONFIG_REGULATOR_RTMV20=y
CONFIG_REGULATOR_RTQ6752=y
CONFIG_REGULATOR_S2MPA01=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_SKY81452=y
CONFIG_REGULATOR_SLG51000=y
CONFIG_REGULATOR_STPMIC1=y
CONFIG_REGULATOR_SY7636A=y
CONFIG_REGULATOR_SY8106A=y
CONFIG_REGULATOR_SY8824X=y
CONFIG_REGULATOR_SY8827N=y
CONFIG_REGULATOR_TPS51632=y
CONFIG_REGULATOR_TPS6105X=y
CONFIG_REGULATOR_TPS62360=y
CONFIG_REGULATOR_TPS6286X=y
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65086=y
CONFIG_REGULATOR_TPS65090=y
CONFIG_REGULATOR_TPS65132=y
CONFIG_REGULATOR_TPS65217=y
CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS65219=y
CONFIG_REGULATOR_TPS6524X=y
CONFIG_REGULATOR_TPS6586X=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_TPS65912=y
CONFIG_REGULATOR_TPS68470=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_WM831X=y
CONFIG_REGULATOR_WM8350=y
CONFIG_REGULATOR_WM8400=y
CONFIG_REGULATOR_WM8994=y
CONFIG_REGULATOR_QCOM_LABIBB=y
CONFIG_RC_CORE=y
CONFIG_BPF_LIRC_MODE2=y
CONFIG_LIRC=y
CONFIG_RC_MAP=y
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=y
CONFIG_IR_JVC_DECODER=y
CONFIG_IR_MCE_KBD_DECODER=y
CONFIG_IR_NEC_DECODER=y
CONFIG_IR_RC5_DECODER=y
CONFIG_IR_RC6_DECODER=y
CONFIG_IR_RCMM_DECODER=y
CONFIG_IR_SANYO_DECODER=y
CONFIG_IR_SHARP_DECODER=y
CONFIG_IR_SONY_DECODER=y
CONFIG_IR_XMP_DECODER=y
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=y
CONFIG_IR_FINTEK=y
CONFIG_IR_GPIO_CIR=y
CONFIG_IR_GPIO_TX=y
CONFIG_IR_HIX5HD2=y
CONFIG_IR_IGORPLUGUSB=y
CONFIG_IR_IGUANA=y
CONFIG_IR_IMON=y
CONFIG_IR_IMON_RAW=y
CONFIG_IR_ITE_CIR=y
CONFIG_IR_MCEUSB=y
CONFIG_IR_NUVOTON=y
CONFIG_IR_PWM_TX=y
CONFIG_IR_REDRAT3=y
CONFIG_IR_SERIAL=y
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=y
CONFIG_IR_STREAMZAP=y
CONFIG_IR_TOY=y
CONFIG_IR_TTUSBIR=y
CONFIG_IR_WINBOND_CIR=y
CONFIG_RC_ATI_REMOTE=y
CONFIG_RC_LOOPBACK=y
CONFIG_RC_XBOX_DVD=y
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
CONFIG_CEC_PIN=y
#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_CEC_PIN_ERROR_INJ=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=y
CONFIG_CEC_CROS_EC=y
CONFIG_CEC_GPIO=y
CONFIG_CEC_SECO=y
CONFIG_CEC_SECO_RC=y
CONFIG_USB_PULSE8_CEC=y
CONFIG_USB_RAINSHADOW_CEC=y
# end of CEC support
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types
CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y
#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=y
CONFIG_V4L2_MEM2MEM_DEV=y
CONFIG_V4L2_FLASH_LED_CLASS=y
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
CONFIG_VIDEOBUF_GEN=y
CONFIG_VIDEOBUF_DMA_SG=y
CONFIG_VIDEOBUF_VMALLOC=y
# end of Video4Linux options
#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options
#
# Digital TV options
#
CONFIG_DVB_MMAP=y
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=16
CONFIG_DVB_DYNAMIC_MINORS=y
CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y
CONFIG_DVB_ULE_DEBUG=y
# end of Digital TV options
#
# Media drivers
#
#
# Drivers filtered as selected at 'Filter media drivers'
#
#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y
#
# Webcam devices
#
CONFIG_USB_GSPCA=y
CONFIG_USB_GSPCA_BENQ=y
CONFIG_USB_GSPCA_CONEX=y
CONFIG_USB_GSPCA_CPIA1=y
CONFIG_USB_GSPCA_DTCS033=y
CONFIG_USB_GSPCA_ETOMS=y
CONFIG_USB_GSPCA_FINEPIX=y
CONFIG_USB_GSPCA_JEILINJ=y
CONFIG_USB_GSPCA_JL2005BCD=y
CONFIG_USB_GSPCA_KINECT=y
CONFIG_USB_GSPCA_KONICA=y
CONFIG_USB_GSPCA_MARS=y
CONFIG_USB_GSPCA_MR97310A=y
CONFIG_USB_GSPCA_NW80X=y
CONFIG_USB_GSPCA_OV519=y
CONFIG_USB_GSPCA_OV534=y
CONFIG_USB_GSPCA_OV534_9=y
CONFIG_USB_GSPCA_PAC207=y
CONFIG_USB_GSPCA_PAC7302=y
CONFIG_USB_GSPCA_PAC7311=y
CONFIG_USB_GSPCA_SE401=y
CONFIG_USB_GSPCA_SN9C2028=y
CONFIG_USB_GSPCA_SN9C20X=y
CONFIG_USB_GSPCA_SONIXB=y
CONFIG_USB_GSPCA_SONIXJ=y
CONFIG_USB_GSPCA_SPCA1528=y
CONFIG_USB_GSPCA_SPCA500=y
CONFIG_USB_GSPCA_SPCA501=y
CONFIG_USB_GSPCA_SPCA505=y
CONFIG_USB_GSPCA_SPCA506=y
CONFIG_USB_GSPCA_SPCA508=y
CONFIG_USB_GSPCA_SPCA561=y
CONFIG_USB_GSPCA_SQ905=y
CONFIG_USB_GSPCA_SQ905C=y
CONFIG_USB_GSPCA_SQ930X=y
CONFIG_USB_GSPCA_STK014=y
CONFIG_USB_GSPCA_STK1135=y
CONFIG_USB_GSPCA_STV0680=y
CONFIG_USB_GSPCA_SUNPLUS=y
CONFIG_USB_GSPCA_T613=y
CONFIG_USB_GSPCA_TOPRO=y
CONFIG_USB_GSPCA_TOUPTEK=y
CONFIG_USB_GSPCA_TV8532=y
CONFIG_USB_GSPCA_VC032X=y
CONFIG_USB_GSPCA_VICAM=y
CONFIG_USB_GSPCA_XIRLINK_CIT=y
CONFIG_USB_GSPCA_ZC3XX=y
CONFIG_USB_GL860=y
CONFIG_USB_M5602=y
CONFIG_USB_STV06XX=y
CONFIG_USB_PWC=y
CONFIG_USB_PWC_DEBUG=y
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=y
CONFIG_VIDEO_USBTV=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
#
# Analog TV USB devices
#
CONFIG_VIDEO_GO7007=y
CONFIG_VIDEO_GO7007_USB=y
CONFIG_VIDEO_GO7007_LOADER=y
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=y
CONFIG_VIDEO_HDPVR=y
CONFIG_VIDEO_PVRUSB2=y
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
CONFIG_VIDEO_PVRUSB2_DEBUGIFC=y
CONFIG_VIDEO_STK1160_COMMON=y
CONFIG_VIDEO_STK1160=y
#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=y
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=y
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=y
CONFIG_VIDEO_CX231XX_DVB=y
#
# Digital TV USB devices
#
CONFIG_DVB_AS102=y
CONFIG_DVB_B2C2_FLEXCOP_USB=y
CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG=y
CONFIG_DVB_USB_V2=y
CONFIG_DVB_USB_AF9015=y
CONFIG_DVB_USB_AF9035=y
CONFIG_DVB_USB_ANYSEE=y
CONFIG_DVB_USB_AU6610=y
CONFIG_DVB_USB_AZ6007=y
CONFIG_DVB_USB_CE6230=y
CONFIG_DVB_USB_DVBSKY=y
CONFIG_DVB_USB_EC168=y
CONFIG_DVB_USB_GL861=y
CONFIG_DVB_USB_LME2510=y
CONFIG_DVB_USB_MXL111SF=y
CONFIG_DVB_USB_RTL28XXU=y
CONFIG_DVB_USB_ZD1301=y
CONFIG_DVB_USB=y
CONFIG_DVB_USB_DEBUG=y
CONFIG_DVB_USB_A800=y
CONFIG_DVB_USB_AF9005=y
CONFIG_DVB_USB_AF9005_REMOTE=y
CONFIG_DVB_USB_AZ6027=y
CONFIG_DVB_USB_CINERGY_T2=y
CONFIG_DVB_USB_CXUSB=y
CONFIG_DVB_USB_CXUSB_ANALOG=y
CONFIG_DVB_USB_DIB0700=y
CONFIG_DVB_USB_DIB3000MC=y
CONFIG_DVB_USB_DIBUSB_MB=y
CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
CONFIG_DVB_USB_DIBUSB_MC=y
CONFIG_DVB_USB_DIGITV=y
CONFIG_DVB_USB_DTT200U=y
CONFIG_DVB_USB_DTV5100=y
CONFIG_DVB_USB_DW2102=y
CONFIG_DVB_USB_GP8PSK=y
CONFIG_DVB_USB_M920X=y
CONFIG_DVB_USB_NOVA_T_USB2=y
CONFIG_DVB_USB_OPERA1=y
CONFIG_DVB_USB_PCTV452E=y
CONFIG_DVB_USB_TECHNISAT_USB2=y
CONFIG_DVB_USB_TTUSB2=y
CONFIG_DVB_USB_UMT_010=y
CONFIG_DVB_USB_VP702X=y
CONFIG_DVB_USB_VP7045=y
CONFIG_SMS_USB_DRV=y
CONFIG_DVB_TTUSB_BUDGET=y
CONFIG_DVB_TTUSB_DEC=y
#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=y
CONFIG_VIDEO_EM28XX_V4L2=y
CONFIG_VIDEO_EM28XX_ALSA=y
CONFIG_VIDEO_EM28XX_DVB=y
CONFIG_VIDEO_EM28XX_RC=y
#
# Software defined radio USB devices
#
CONFIG_USB_AIRSPY=y
CONFIG_USB_HACKRF=y
CONFIG_USB_MSI2500=y
CONFIG_MEDIA_PCI_SUPPORT=y
#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=y
CONFIG_STA2X11_VIP=y
CONFIG_VIDEO_TW5864=y
CONFIG_VIDEO_TW68=y
CONFIG_VIDEO_TW686X=y
CONFIG_VIDEO_ZORAN=y
CONFIG_VIDEO_ZORAN_DC30=y
CONFIG_VIDEO_ZORAN_ZR36060=y
CONFIG_VIDEO_ZORAN_BUZ=y
CONFIG_VIDEO_ZORAN_DC10=y
CONFIG_VIDEO_ZORAN_LML33=y
CONFIG_VIDEO_ZORAN_LML33R10=y
CONFIG_VIDEO_ZORAN_AVS6EYES=y
#
# Media capture/analog TV support
#
CONFIG_VIDEO_DT3155=y
CONFIG_VIDEO_IVTV=y
CONFIG_VIDEO_IVTV_ALSA=y
CONFIG_VIDEO_FB_IVTV=y
CONFIG_VIDEO_FB_IVTV_FORCE_PAT=y
#
# Media capture/analog/hybrid TV support
#
CONFIG_VIDEO_BT848=y
CONFIG_DVB_BT8XX=y
CONFIG_VIDEO_CX18=y
CONFIG_VIDEO_CX18_ALSA=y
CONFIG_VIDEO_CX23885=y
CONFIG_MEDIA_ALTERA_CI=y
CONFIG_VIDEO_CX25821=y
CONFIG_VIDEO_CX25821_ALSA=y
CONFIG_VIDEO_CX88=y
CONFIG_VIDEO_CX88_ALSA=y
CONFIG_VIDEO_CX88_BLACKBIRD=y
CONFIG_VIDEO_CX88_DVB=y
CONFIG_VIDEO_CX88_ENABLE_VP3054=y
CONFIG_VIDEO_CX88_VP3054=y
CONFIG_VIDEO_CX88_MPEG=y
CONFIG_VIDEO_SAA7134=y
CONFIG_VIDEO_SAA7134_ALSA=y
CONFIG_VIDEO_SAA7134_RC=y
CONFIG_VIDEO_SAA7134_DVB=y
CONFIG_VIDEO_SAA7134_GO7007=y
CONFIG_VIDEO_SAA7164=y
#
# Media digital TV PCI Adapters
#
CONFIG_DVB_B2C2_FLEXCOP_PCI=y
CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG=y
CONFIG_DVB_DDBRIDGE=y
CONFIG_DVB_DDBRIDGE_MSIENABLE=y
CONFIG_DVB_DM1105=y
CONFIG_MANTIS_CORE=y
CONFIG_DVB_MANTIS=y
CONFIG_DVB_HOPPER=y
CONFIG_DVB_NETUP_UNIDVB=y
CONFIG_DVB_NGENE=y
CONFIG_DVB_PLUTO2=y
CONFIG_DVB_PT1=y
CONFIG_DVB_PT3=y
CONFIG_DVB_SMIPCIE=y
CONFIG_VIDEO_PCI_SKELETON=y
CONFIG_VIDEO_IPU3_CIO2=y
CONFIG_CIO2_BRIDGE=y
CONFIG_RADIO_ADAPTERS=y
CONFIG_RADIO_MAXIRADIO=y
CONFIG_RADIO_SAA7706H=y
CONFIG_RADIO_SHARK=y
CONFIG_RADIO_SHARK2=y
CONFIG_RADIO_SI4713=y
CONFIG_RADIO_SI476X=y
CONFIG_RADIO_TEA575X=y
CONFIG_RADIO_TEA5764=y
CONFIG_RADIO_TEA5764_XTAL=y
CONFIG_RADIO_TEF6862=y
CONFIG_RADIO_TIMBERDALE=y
CONFIG_RADIO_WL1273=y
CONFIG_USB_DSBR=y
CONFIG_USB_KEENE=y
CONFIG_USB_MA901=y
CONFIG_USB_MR800=y
CONFIG_USB_RAREMONO=y
CONFIG_RADIO_SI470X=y
CONFIG_USB_SI470X=y
CONFIG_I2C_SI470X=y
CONFIG_USB_SI4713=y
CONFIG_PLATFORM_SI4713=y
CONFIG_I2C_SI4713=y
CONFIG_RADIO_WL128X=y
CONFIG_V4L_RADIO_ISA_DRIVERS=y
CONFIG_RADIO_AZTECH=y
CONFIG_RADIO_AZTECH_PORT=350
CONFIG_RADIO_CADET=y
CONFIG_RADIO_GEMTEK=y
CONFIG_RADIO_GEMTEK_PORT=34c
CONFIG_RADIO_GEMTEK_PROBE=y
CONFIG_RADIO_ISA=y
CONFIG_RADIO_MIROPCM20=y
CONFIG_RADIO_RTRACK=y
CONFIG_RADIO_RTRACK2=y
CONFIG_RADIO_RTRACK2_PORT=30c
CONFIG_RADIO_RTRACK_PORT=30f
CONFIG_RADIO_SF16FMI=y
CONFIG_RADIO_SF16FMR2=y
CONFIG_RADIO_TERRATEC=y
CONFIG_RADIO_TRUST=y
CONFIG_RADIO_TRUST_PORT=350
CONFIG_RADIO_TYPHOON=y
CONFIG_RADIO_TYPHOON_MUTEFREQ=87500
CONFIG_RADIO_TYPHOON_PORT=316
CONFIG_RADIO_ZOLTRIX=y
CONFIG_RADIO_ZOLTRIX_PORT=20c
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_DVB_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_MUX=y
#
# Allegro DVT media platform drivers
#
#
# Amlogic media platform drivers
#
#
# Amphion drivers
#
#
# Aspeed media platform drivers
#
#
# Atmel media platform drivers
#
#
# Cadence media platform drivers
#
CONFIG_VIDEO_CADENCE_CSI2RX=y
CONFIG_VIDEO_CADENCE_CSI2TX=y
#
# Chips&Media media platform drivers
#
#
# Intel media platform drivers
#
#
# Marvell media platform drivers
#
CONFIG_VIDEO_CAFE_CCIC=y
#
# Mediatek media platform drivers
#
#
# Microchip Technology, Inc. media platform drivers
#
#
# NVidia media platform drivers
#
#
# NXP media platform drivers
#
#
# Qualcomm media platform drivers
#
#
# Renesas media platform drivers
#
#
# Rockchip media platform drivers
#
#
# Samsung media platform drivers
#
#
# STMicroelectronics media platform drivers
#
#
# Sunxi media platform drivers
#
#
# Texas Instruments drivers
#
#
# Verisilicon media platform drivers
#
#
# VIA media platform drivers
#
CONFIG_VIDEO_VIA_CAMERA=y
#
# Xilinx media platform drivers
#
CONFIG_VIDEO_XILINX=y
CONFIG_VIDEO_XILINX_CSI2RXSS=y
CONFIG_VIDEO_XILINX_TPG=y
CONFIG_VIDEO_XILINX_VTC=y
#
# MMC/SDIO DVB adapters
#
CONFIG_SMS_SDIO_DRV=y
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIM2M=y
CONFIG_VIDEO_VICODEC=y
CONFIG_VIDEO_VIMC=y
CONFIG_VIDEO_VIVID=y
CONFIG_VIDEO_VIVID_CEC=y
CONFIG_VIDEO_VIVID_MAX_DEVS=64
CONFIG_VIDEO_VISL=y
CONFIG_VISL_DEBUGFS=y
CONFIG_DVB_TEST_DRIVERS=y
CONFIG_DVB_VIDTV=y
#
# FireWire (IEEE 1394) Adapters
#
CONFIG_DVB_FIREDTV=y
CONFIG_DVB_FIREDTV_INPUT=y
CONFIG_MEDIA_COMMON_OPTIONS=y
#
# common driver options
#
CONFIG_CYPRESS_FIRMWARE=y
CONFIG_TTPCI_EEPROM=y
CONFIG_VIDEO_CX2341X=y
CONFIG_VIDEO_TVEEPROM=y
CONFIG_DVB_B2C2_FLEXCOP=y
CONFIG_DVB_B2C2_FLEXCOP_DEBUG=y
CONFIG_SMS_SIANO_MDTV=y
CONFIG_SMS_SIANO_RC=y
CONFIG_SMS_SIANO_DEBUGFS=y
CONFIG_VIDEO_V4L2_TPG=y
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=y
CONFIG_VIDEOBUF2_DVB=y
# end of Media drivers
#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y
#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=y
#
# Camera sensor devices
#
CONFIG_VIDEO_APTINA_PLL=y
CONFIG_VIDEO_CCS_PLL=y
CONFIG_VIDEO_AR0521=y
CONFIG_VIDEO_HI556=y
CONFIG_VIDEO_HI846=y
CONFIG_VIDEO_HI847=y
CONFIG_VIDEO_IMX208=y
CONFIG_VIDEO_IMX214=y
CONFIG_VIDEO_IMX219=y
CONFIG_VIDEO_IMX258=y
CONFIG_VIDEO_IMX274=y
CONFIG_VIDEO_IMX290=y
CONFIG_VIDEO_IMX319=y
CONFIG_VIDEO_IMX334=y
CONFIG_VIDEO_IMX335=y
CONFIG_VIDEO_IMX355=y
CONFIG_VIDEO_IMX412=y
CONFIG_VIDEO_MAX9271_LIB=y
CONFIG_VIDEO_MT9M001=y
CONFIG_VIDEO_MT9M032=y
CONFIG_VIDEO_MT9M111=y
CONFIG_VIDEO_MT9P031=y
CONFIG_VIDEO_MT9T001=y
CONFIG_VIDEO_MT9T112=y
CONFIG_VIDEO_MT9V011=y
CONFIG_VIDEO_MT9V032=y
CONFIG_VIDEO_MT9V111=y
CONFIG_VIDEO_NOON010PC30=y
CONFIG_VIDEO_OG01A1B=y
CONFIG_VIDEO_OV02A10=y
CONFIG_VIDEO_OV08D10=y
CONFIG_VIDEO_OV08X40=y
CONFIG_VIDEO_OV13858=y
CONFIG_VIDEO_OV13B10=y
CONFIG_VIDEO_OV2640=y
CONFIG_VIDEO_OV2659=y
CONFIG_VIDEO_OV2680=y
CONFIG_VIDEO_OV2685=y
CONFIG_VIDEO_OV2740=y
CONFIG_VIDEO_OV4689=y
CONFIG_VIDEO_OV5640=y
CONFIG_VIDEO_OV5645=y
CONFIG_VIDEO_OV5647=y
CONFIG_VIDEO_OV5648=y
CONFIG_VIDEO_OV5670=y
CONFIG_VIDEO_OV5675=y
CONFIG_VIDEO_OV5693=y
CONFIG_VIDEO_OV5695=y
CONFIG_VIDEO_OV6650=y
CONFIG_VIDEO_OV7251=y
CONFIG_VIDEO_OV7640=y
CONFIG_VIDEO_OV7670=y
CONFIG_VIDEO_OV772X=y
CONFIG_VIDEO_OV7740=y
CONFIG_VIDEO_OV8856=y
CONFIG_VIDEO_OV8865=y
CONFIG_VIDEO_OV9282=y
CONFIG_VIDEO_OV9640=y
CONFIG_VIDEO_OV9650=y
CONFIG_VIDEO_OV9734=y
CONFIG_VIDEO_RDACM20=y
CONFIG_VIDEO_RDACM21=y
CONFIG_VIDEO_RJ54N1=y
CONFIG_VIDEO_S5C73M3=y
CONFIG_VIDEO_S5K5BAF=y
CONFIG_VIDEO_S5K6A3=y
CONFIG_VIDEO_S5K6AA=y
CONFIG_VIDEO_SR030PC30=y
CONFIG_VIDEO_ST_VGXY61=y
CONFIG_VIDEO_VS6624=y
CONFIG_VIDEO_CCS=y
CONFIG_VIDEO_ET8EK8=y
CONFIG_VIDEO_M5MOLS=y
# end of Camera sensor devices
#
# Lens drivers
#
CONFIG_VIDEO_AD5820=y
CONFIG_VIDEO_AK7375=y
CONFIG_VIDEO_DW9714=y
CONFIG_VIDEO_DW9768=y
CONFIG_VIDEO_DW9807_VCM=y
# end of Lens drivers
#
# Flash devices
#
CONFIG_VIDEO_ADP1653=y
CONFIG_VIDEO_LM3560=y
CONFIG_VIDEO_LM3646=y
# end of Flash devices
#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=y
CONFIG_VIDEO_CS5345=y
CONFIG_VIDEO_CS53L32A=y
CONFIG_VIDEO_MSP3400=y
CONFIG_VIDEO_SONY_BTF_MPX=y
CONFIG_VIDEO_TDA1997X=y
CONFIG_VIDEO_TDA7432=y
CONFIG_VIDEO_TDA9840=y
CONFIG_VIDEO_TEA6415C=y
CONFIG_VIDEO_TEA6420=y
CONFIG_VIDEO_TLV320AIC23B=y
CONFIG_VIDEO_TVAUDIO=y
CONFIG_VIDEO_UDA1342=y
CONFIG_VIDEO_VP27SMPX=y
CONFIG_VIDEO_WM8739=y
CONFIG_VIDEO_WM8775=y
# end of Audio decoders, processors and mixers
#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=y
# end of RDS decoders
#
# Video decoders
#
CONFIG_VIDEO_ADV7180=y
CONFIG_VIDEO_ADV7183=y
CONFIG_VIDEO_ADV748X=y
CONFIG_VIDEO_ADV7604=y
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=y
CONFIG_VIDEO_ADV7842_CEC=y
CONFIG_VIDEO_BT819=y
CONFIG_VIDEO_BT856=y
CONFIG_VIDEO_BT866=y
CONFIG_VIDEO_ISL7998X=y
CONFIG_VIDEO_KS0127=y
CONFIG_VIDEO_MAX9286=y
CONFIG_VIDEO_ML86V7667=y
CONFIG_VIDEO_SAA7110=y
CONFIG_VIDEO_SAA711X=y
CONFIG_VIDEO_TC358743=y
CONFIG_VIDEO_TC358743_CEC=y
CONFIG_VIDEO_TC358746=y
CONFIG_VIDEO_TVP514X=y
CONFIG_VIDEO_TVP5150=y
CONFIG_VIDEO_TVP7002=y
CONFIG_VIDEO_TW2804=y
CONFIG_VIDEO_TW9903=y
CONFIG_VIDEO_TW9906=y
CONFIG_VIDEO_TW9910=y
CONFIG_VIDEO_VPX3220=y
#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=y
CONFIG_VIDEO_CX25840=y
# end of Video decoders
#
# Video encoders
#
CONFIG_VIDEO_AD9389B=y
CONFIG_VIDEO_ADV7170=y
CONFIG_VIDEO_ADV7175=y
CONFIG_VIDEO_ADV7343=y
CONFIG_VIDEO_ADV7393=y
CONFIG_VIDEO_AK881X=y
CONFIG_VIDEO_SAA7127=y
CONFIG_VIDEO_SAA7185=y
CONFIG_VIDEO_THS8200=y
# end of Video encoders
#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=y
CONFIG_VIDEO_UPD64083=y
# end of Video improvement chips
#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=y
# end of Audio/Video compression chips
#
# SDR tuner chips
#
CONFIG_SDR_MAX2175=y
# end of SDR tuner chips
#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=y
CONFIG_VIDEO_M52790=y
CONFIG_VIDEO_ST_MIPID02=y
CONFIG_VIDEO_THS7303=y
# end of Miscellaneous helper chips
#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=y
CONFIG_VIDEO_GS1662=y
# end of Media SPI Adapters
CONFIG_MEDIA_TUNER=y
#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_E4000=y
CONFIG_MEDIA_TUNER_FC0011=y
CONFIG_MEDIA_TUNER_FC0012=y
CONFIG_MEDIA_TUNER_FC0013=y
CONFIG_MEDIA_TUNER_FC2580=y
CONFIG_MEDIA_TUNER_IT913X=y
CONFIG_MEDIA_TUNER_M88RS6000T=y
CONFIG_MEDIA_TUNER_MAX2165=y
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_MEDIA_TUNER_MSI001=y
CONFIG_MEDIA_TUNER_MT2060=y
CONFIG_MEDIA_TUNER_MT2063=y
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2131=y
CONFIG_MEDIA_TUNER_MT2266=y
CONFIG_MEDIA_TUNER_MXL301RF=y
CONFIG_MEDIA_TUNER_MXL5005S=y
CONFIG_MEDIA_TUNER_MXL5007T=y
CONFIG_MEDIA_TUNER_QM1D1B0004=y
CONFIG_MEDIA_TUNER_QM1D1C0042=y
CONFIG_MEDIA_TUNER_QT1010=y
CONFIG_MEDIA_TUNER_R820T=y
CONFIG_MEDIA_TUNER_SI2157=y
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18212=y
CONFIG_MEDIA_TUNER_TDA18218=y
CONFIG_MEDIA_TUNER_TDA18250=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_TUA9001=y
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_XC5000=y
# end of Customize TV tuners
#
# Customise DVB Frontends
#
#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=y
CONFIG_DVB_MXL5XX=y
CONFIG_DVB_STB0899=y
CONFIG_DVB_STB6100=y
CONFIG_DVB_STV090x=y
CONFIG_DVB_STV0910=y
CONFIG_DVB_STV6110x=y
CONFIG_DVB_STV6111=y
#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=y
CONFIG_DVB_MN88472=y
CONFIG_DVB_MN88473=y
CONFIG_DVB_SI2165=y
CONFIG_DVB_TDA18271C2DD=y
#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=y
CONFIG_DVB_CX24116=y
CONFIG_DVB_CX24117=y
CONFIG_DVB_CX24120=y
CONFIG_DVB_CX24123=y
CONFIG_DVB_DS3000=y
CONFIG_DVB_MB86A16=y
CONFIG_DVB_MT312=y
CONFIG_DVB_S5H1420=y
CONFIG_DVB_SI21XX=y
CONFIG_DVB_STB6000=y
CONFIG_DVB_STV0288=y
CONFIG_DVB_STV0299=y
CONFIG_DVB_STV0900=y
CONFIG_DVB_STV6110=y
CONFIG_DVB_TDA10071=y
CONFIG_DVB_TDA10086=y
CONFIG_DVB_TDA8083=y
CONFIG_DVB_TDA8261=y
CONFIG_DVB_TDA826X=y
CONFIG_DVB_TS2020=y
CONFIG_DVB_TUA6100=y
CONFIG_DVB_TUNER_CX24113=y
CONFIG_DVB_TUNER_ITD1000=y
CONFIG_DVB_VES1X93=y
CONFIG_DVB_ZL10036=y
CONFIG_DVB_ZL10039=y
#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=y
CONFIG_DVB_AS102_FE=y
CONFIG_DVB_CX22700=y
CONFIG_DVB_CX22702=y
CONFIG_DVB_CXD2820R=y
CONFIG_DVB_CXD2841ER=y
CONFIG_DVB_DIB3000MB=y
CONFIG_DVB_DIB3000MC=y
CONFIG_DVB_DIB7000M=y
CONFIG_DVB_DIB7000P=y
CONFIG_DVB_DIB9000=y
CONFIG_DVB_DRXD=y
CONFIG_DVB_EC100=y
CONFIG_DVB_GP8PSK_FE=y
CONFIG_DVB_L64781=y
CONFIG_DVB_MT352=y
CONFIG_DVB_NXT6000=y
CONFIG_DVB_RTL2830=y
CONFIG_DVB_RTL2832=y
CONFIG_DVB_RTL2832_SDR=y
CONFIG_DVB_S5H1432=y
CONFIG_DVB_SI2168=y
CONFIG_DVB_SP887X=y
CONFIG_DVB_STV0367=y
CONFIG_DVB_TDA10048=y
CONFIG_DVB_TDA1004X=y
CONFIG_DVB_ZD1301_DEMOD=y
CONFIG_DVB_ZL10353=y
CONFIG_DVB_CXD2880=y
#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=y
CONFIG_DVB_TDA10021=y
CONFIG_DVB_TDA10023=y
CONFIG_DVB_VES1820=y
#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=y
CONFIG_DVB_AU8522_DTV=y
CONFIG_DVB_AU8522_V4L=y
CONFIG_DVB_BCM3510=y
CONFIG_DVB_LG2160=y
CONFIG_DVB_LGDT3305=y
CONFIG_DVB_LGDT3306A=y
CONFIG_DVB_LGDT330X=y
CONFIG_DVB_MXL692=y
CONFIG_DVB_NXT200X=y
CONFIG_DVB_OR51132=y
CONFIG_DVB_OR51211=y
CONFIG_DVB_S5H1409=y
CONFIG_DVB_S5H1411=y
#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=y
CONFIG_DVB_MB86A20S=y
CONFIG_DVB_S921=y
#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_MN88443X=y
CONFIG_DVB_TC90522=y
#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=y
CONFIG_DVB_TUNER_DIB0070=y
CONFIG_DVB_TUNER_DIB0090=y
#
# SEC control devices for DVB-S
#
CONFIG_DVB_A8293=y
CONFIG_DVB_AF9033=y
CONFIG_DVB_ASCOT2E=y
CONFIG_DVB_ATBM8830=y
CONFIG_DVB_HELENE=y
CONFIG_DVB_HORUS3A=y
CONFIG_DVB_ISL6405=y
CONFIG_DVB_ISL6421=y
CONFIG_DVB_ISL6423=y
CONFIG_DVB_IX2505V=y
CONFIG_DVB_LGS8GL5=y
CONFIG_DVB_LGS8GXX=y
CONFIG_DVB_LNBH25=y
CONFIG_DVB_LNBH29=y
CONFIG_DVB_LNBP21=y
CONFIG_DVB_LNBP22=y
CONFIG_DVB_M88RS2000=y
CONFIG_DVB_TDA665x=y
CONFIG_DVB_DRX39XYJ=y
#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=y
CONFIG_DVB_SP2=y
# end of Customise DVB Frontends
#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=y
# end of Media ancillary drivers
#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_VIDEO_NOMODESET=y
CONFIG_AGP=y
CONFIG_AGP_ALI=y
CONFIG_AGP_ATI=y
CONFIG_AGP_AMD=y
CONFIG_AGP_AMD64=y
CONFIG_AGP_INTEL=y
CONFIG_AGP_NVIDIA=y
CONFIG_AGP_SIS=y
CONFIG_AGP_SWORKS=y
CONFIG_AGP_VIA=y
CONFIG_AGP_EFFICEON=y
CONFIG_INTEL_GTT=y
CONFIG_VGA_SWITCHEROO=y
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_DEBUG_MM=y
CONFIG_DRM_USE_DYNAMIC_DEBUG=y
CONFIG_DRM_KUNIT_TEST=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y
CONFIG_DRM_DEBUG_MODESET_LOCK=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM=y
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP_AUX_BUS=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DP_AUX_CHARDEV=y
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_TTM=y
CONFIG_DRM_BUDDY=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=y
#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=y
CONFIG_DRM_I2C_SIL164=y
CONFIG_DRM_I2C_NXP_TDA998X=y
CONFIG_DRM_I2C_NXP_TDA9950=y
# end of I2C encoder or helper chips
#
# ARM devices
#
CONFIG_DRM_KOMEDA=y
# end of ARM devices
CONFIG_DRM_RADEON=y
CONFIG_DRM_RADEON_USERPTR=y
CONFIG_DRM_AMDGPU=y
CONFIG_DRM_AMDGPU_SI=y
CONFIG_DRM_AMDGPU_CIK=y
CONFIG_DRM_AMDGPU_USERPTR=y
#
# ACP (Audio CoProcessor) Configuration
#
CONFIG_DRM_AMD_ACP=y
# end of ACP (Audio CoProcessor) Configuration
#
# Display Engine Configuration
#
CONFIG_DRM_AMD_DC=y
CONFIG_DRM_AMD_DC_DCN=y
CONFIG_DRM_AMD_DC_HDCP=y
CONFIG_DRM_AMD_DC_SI=y
CONFIG_DEBUG_KERNEL_DC=y
CONFIG_DRM_AMD_SECURE_DISPLAY=y
# end of Display Engine Configuration
CONFIG_DRM_NOUVEAU=y
CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
CONFIG_NOUVEAU_DEBUG=5
CONFIG_NOUVEAU_DEBUG_DEFAULT=3
CONFIG_NOUVEAU_DEBUG_MMU=y
CONFIG_NOUVEAU_DEBUG_PUSH=y
CONFIG_DRM_NOUVEAU_BACKLIGHT=y
CONFIG_DRM_I915=y
CONFIG_DRM_I915_FORCE_PROBE=""
CONFIG_DRM_I915_CAPTURE_ERROR=y
CONFIG_DRM_I915_COMPRESS_ERROR=y
CONFIG_DRM_I915_USERPTR=y
CONFIG_DRM_I915_PXP=y
#
# drm/i915 Debugging
#
CONFIG_DRM_I915_WERROR=y
# CONFIG_DRM_I915_DEBUG is not set
CONFIG_DRM_I915_DEBUG_MMIO=y
# CONFIG_DRM_I915_DEBUG_GEM is not set
CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS=y
CONFIG_DRM_I915_SW_FENCE_CHECK_DAG=y
CONFIG_DRM_I915_DEBUG_GUC=y
CONFIG_DRM_I915_SELFTEST=y
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS=y
CONFIG_DRM_I915_DEBUG_VBLANK_EVADE=y
CONFIG_DRM_I915_DEBUG_RUNTIME_PM=y
# end of drm/i915 Debugging
#
# drm/i915 Profile Guided Optimisation
#
CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
CONFIG_DRM_I915_FENCE_TIMEOUT=10000
CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500
CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
CONFIG_DRM_I915_STOP_TIMEOUT=100
CONFIG_DRM_I915_TIMESLICE_DURATION=1
# end of drm/i915 Profile Guided Optimisation
CONFIG_DRM_VGEM=y
CONFIG_DRM_VKMS=y
CONFIG_DRM_VMWGFX=y
CONFIG_DRM_VMWGFX_MKSSTATS=y
CONFIG_DRM_GMA500=y
CONFIG_DRM_UDL=y
CONFIG_DRM_AST=y
CONFIG_DRM_MGAG200=y
CONFIG_DRM_RCAR_DW_HDMI=y
CONFIG_DRM_RCAR_USE_LVDS=y
CONFIG_DRM_RCAR_USE_MIPI_DSI=y
CONFIG_DRM_QXL=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_PANEL=y
#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=y
CONFIG_DRM_PANEL_ARM_VERSATILE=y
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=y
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=y
CONFIG_DRM_PANEL_BOE_HIMAX8279D=y
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y
CONFIG_DRM_PANEL_DSI_CM=y
CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_DRM_PANEL_EBBG_FT8719=y
CONFIG_DRM_PANEL_ELIDA_KD35T133=y
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=y
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y
CONFIG_DRM_PANEL_ILITEK_IL9322=y
CONFIG_DRM_PANEL_ILITEK_ILI9341=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=y
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=y
CONFIG_DRM_PANEL_JDI_LT070ME05000=y
CONFIG_DRM_PANEL_JDI_R63452=y
CONFIG_DRM_PANEL_KHADAS_TS050=y
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=y
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y
CONFIG_DRM_PANEL_SAMSUNG_LD9040=y
CONFIG_DRM_PANEL_LG_LB035Q02=y
CONFIG_DRM_PANEL_LG_LG4573=y
CONFIG_DRM_PANEL_NEC_NL8048HL11=y
CONFIG_DRM_PANEL_NEWVISION_NV3051D=y
CONFIG_DRM_PANEL_NEWVISION_NV3052C=y
CONFIG_DRM_PANEL_NOVATEK_NT35510=y
CONFIG_DRM_PANEL_NOVATEK_NT35560=y
CONFIG_DRM_PANEL_NOVATEK_NT35950=y
CONFIG_DRM_PANEL_NOVATEK_NT36672A=y
CONFIG_DRM_PANEL_NOVATEK_NT39016=y
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=y
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=y
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
CONFIG_DRM_PANEL_RAYDIUM_RM68200=y
CONFIG_DRM_PANEL_RONBO_RB070D30=y
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=y
CONFIG_DRM_PANEL_SAMSUNG_DB7430=y
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=y
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=y
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=y
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=y
CONFIG_DRM_PANEL_SITRONIX_ST7701=y
CONFIG_DRM_PANEL_SITRONIX_ST7703=y
CONFIG_DRM_PANEL_SITRONIX_ST7789V=y
CONFIG_DRM_PANEL_SONY_ACX565AKM=y
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=y
CONFIG_DRM_PANEL_TDO_TL070WSH30=y
CONFIG_DRM_PANEL_TPO_TD028TTEC1=y
CONFIG_DRM_PANEL_TPO_TD043MTEA1=y
CONFIG_DRM_PANEL_TPO_TPG110=y
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y
CONFIG_DRM_PANEL_VISIONOX_RM69299=y
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=y
CONFIG_DRM_PANEL_XINPENG_XPP055C272=y
# end of Display Panels
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
CONFIG_DRM_CDNS_DSI=y
CONFIG_DRM_CHIPONE_ICN6211=y
CONFIG_DRM_CHRONTEL_CH7033=y
CONFIG_DRM_CROS_EC_ANX7688=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_ITE_IT6505=y
CONFIG_DRM_LONTIUM_LT8912B=y
CONFIG_DRM_LONTIUM_LT9211=y
CONFIG_DRM_LONTIUM_LT9611=y
CONFIG_DRM_LONTIUM_LT9611UXC=y
CONFIG_DRM_ITE_IT66121=y
CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y
CONFIG_DRM_NWL_MIPI_DSI=y
CONFIG_DRM_NXP_PTN3460=y
CONFIG_DRM_PARADE_PS8622=y
CONFIG_DRM_PARADE_PS8640=y
CONFIG_DRM_SIL_SII8620=y
CONFIG_DRM_SII902X=y
CONFIG_DRM_SII9234=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_THINE_THC63LVD1024=y
CONFIG_DRM_TOSHIBA_TC358762=y
CONFIG_DRM_TOSHIBA_TC358764=y
CONFIG_DRM_TOSHIBA_TC358767=y
CONFIG_DRM_TOSHIBA_TC358768=y
CONFIG_DRM_TOSHIBA_TC358775=y
CONFIG_DRM_TI_DLPC3433=y
CONFIG_DRM_TI_TFP410=y
CONFIG_DRM_TI_SN65DSI83=y
CONFIG_DRM_TI_SN65DSI86=y
CONFIG_DRM_TI_TPD12S015=y
CONFIG_DRM_ANALOGIX_ANX6345=y
CONFIG_DRM_ANALOGIX_ANX78XX=y
CONFIG_DRM_ANALOGIX_DP=y
CONFIG_DRM_ANALOGIX_ANX7625=y
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
CONFIG_DRM_CDNS_MHDP8546=y
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_GP_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=y
# end of Display Interface Bridges
CONFIG_DRM_ETNAVIV=y
CONFIG_DRM_ETNAVIV_THERMAL=y
CONFIG_DRM_LOGICVC=y
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_IMX_LCDIF is not set
CONFIG_DRM_ARCPGU=y
CONFIG_DRM_BOCHS=y
CONFIG_DRM_CIRRUS_QEMU=y
CONFIG_DRM_GM12U320=y
CONFIG_DRM_PANEL_MIPI_DBI=y
CONFIG_DRM_SIMPLEDRM=y
CONFIG_TINYDRM_HX8357D=y
CONFIG_TINYDRM_ILI9163=y
CONFIG_TINYDRM_ILI9225=y
CONFIG_TINYDRM_ILI9341=y
CONFIG_TINYDRM_ILI9486=y
CONFIG_TINYDRM_MI0283QT=y
CONFIG_TINYDRM_REPAPER=y
CONFIG_TINYDRM_ST7586=y
CONFIG_TINYDRM_ST7735R=y
CONFIG_DRM_VBOXVIDEO=y
CONFIG_DRM_GUD=y
CONFIG_DRM_SSD130X=y
CONFIG_DRM_SSD130X_I2C=y
CONFIG_DRM_SSD130X_SPI=y
CONFIG_DRM_HYPERV=y
CONFIG_DRM_LEGACY=y
CONFIG_DRM_TDFX=y
CONFIG_DRM_R128=y
CONFIG_DRM_MGA=y
CONFIG_DRM_SIS=y
CONFIG_DRM_VIA=y
CONFIG_DRM_SAVAGE=y
CONFIG_DRM_EXPORT_FOR_TESTS=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_LIB_RANDOM=y
CONFIG_DRM_PRIVACY_SCREEN=y
#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DDC=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FB_FOREIGN_ENDIAN=y
CONFIG_FB_BOTH_ENDIAN=y
# CONFIG_FB_BIG_ENDIAN is not set
# CONFIG_FB_LITTLE_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_HECUBA=y
CONFIG_FB_SVGALIB=y
CONFIG_FB_BACKLIGHT=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
#
# Frame buffer hardware drivers
#
CONFIG_FB_CIRRUS=y
CONFIG_FB_PM2=y
CONFIG_FB_PM2_FIFO_DISCONNECT=y
CONFIG_FB_CYBER2000=y
CONFIG_FB_CYBER2000_DDC=y
CONFIG_FB_ARC=y
CONFIG_FB_ASILIANT=y
CONFIG_FB_IMSTT=y
CONFIG_FB_VGA16=y
CONFIG_FB_UVESA=y
CONFIG_FB_VESA=y
CONFIG_FB_EFI=y
CONFIG_FB_N411=y
CONFIG_FB_HGA=y
CONFIG_FB_OPENCORES=y
CONFIG_FB_S1D13XXX=y
CONFIG_FB_NVIDIA=y
CONFIG_FB_NVIDIA_I2C=y
CONFIG_FB_NVIDIA_DEBUG=y
CONFIG_FB_NVIDIA_BACKLIGHT=y
CONFIG_FB_RIVA=y
CONFIG_FB_RIVA_I2C=y
CONFIG_FB_RIVA_DEBUG=y
CONFIG_FB_RIVA_BACKLIGHT=y
CONFIG_FB_I740=y
CONFIG_FB_I810=y
CONFIG_FB_I810_GTF=y
CONFIG_FB_I810_I2C=y
CONFIG_FB_LE80578=y
CONFIG_FB_CARILLO_RANCH=y
CONFIG_FB_MATROX=y
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
CONFIG_FB_MATROX_G=y
CONFIG_FB_MATROX_I2C=y
CONFIG_FB_MATROX_MAVEN=y
CONFIG_FB_RADEON=y
CONFIG_FB_RADEON_I2C=y
CONFIG_FB_RADEON_BACKLIGHT=y
CONFIG_FB_RADEON_DEBUG=y
CONFIG_FB_ATY128=y
CONFIG_FB_ATY128_BACKLIGHT=y
CONFIG_FB_ATY=y
CONFIG_FB_ATY_CT=y
CONFIG_FB_ATY_GENERIC_LCD=y
CONFIG_FB_ATY_GX=y
CONFIG_FB_ATY_BACKLIGHT=y
CONFIG_FB_S3=y
CONFIG_FB_S3_DDC=y
CONFIG_FB_SAVAGE=y
CONFIG_FB_SAVAGE_I2C=y
CONFIG_FB_SAVAGE_ACCEL=y
CONFIG_FB_SIS=y
CONFIG_FB_SIS_300=y
CONFIG_FB_SIS_315=y
CONFIG_FB_VIA=y
CONFIG_FB_VIA_DIRECT_PROCFS=y
CONFIG_FB_VIA_X_COMPATIBILITY=y
CONFIG_FB_NEOMAGIC=y
CONFIG_FB_KYRO=y
CONFIG_FB_3DFX=y
CONFIG_FB_3DFX_ACCEL=y
CONFIG_FB_3DFX_I2C=y
CONFIG_FB_VOODOO1=y
CONFIG_FB_VT8623=y
CONFIG_FB_TRIDENT=y
CONFIG_FB_ARK=y
CONFIG_FB_PM3=y
CONFIG_FB_CARMINE=y
CONFIG_FB_CARMINE_DRAM_EVAL=y
# CONFIG_CARMINE_DRAM_CUSTOM is not set
CONFIG_FB_GEODE=y
CONFIG_FB_GEODE_LX=y
CONFIG_FB_GEODE_GX=y
CONFIG_FB_GEODE_GX1=y
CONFIG_FB_SM501=y
CONFIG_FB_SMSCUFX=y
CONFIG_FB_UDL=y
CONFIG_FB_IBM_GXT4500=y
CONFIG_FB_GOLDFISH=y
CONFIG_FB_VIRTUAL=y
CONFIG_FB_METRONOME=y
CONFIG_FB_MB862XX=y
CONFIG_FB_MB862XX_PCI_GDC=y
CONFIG_FB_MB862XX_I2C=y
CONFIG_FB_HYPERV=y
CONFIG_FB_SSD1307=y
CONFIG_FB_SM712=y
# end of Frame buffer Devices
#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y
CONFIG_LCD_LMS283GF05=y
CONFIG_LCD_LTV350QV=y
CONFIG_LCD_ILI922X=y
CONFIG_LCD_ILI9320=y
CONFIG_LCD_TDO24M=y
CONFIG_LCD_VGG2432A4=y
CONFIG_LCD_PLATFORM=y
CONFIG_LCD_AMS369FG06=y
CONFIG_LCD_LMS501KF03=y
CONFIG_LCD_HX8357=y
CONFIG_LCD_OTM3225A=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=y
CONFIG_BACKLIGHT_LM3533=y
CONFIG_BACKLIGHT_CARILLO_RANCH=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_DA903X=y
CONFIG_BACKLIGHT_DA9052=y
CONFIG_BACKLIGHT_MAX8925=y
CONFIG_BACKLIGHT_MT6370=y
CONFIG_BACKLIGHT_APPLE=y
CONFIG_BACKLIGHT_QCOM_WLED=y
CONFIG_BACKLIGHT_RT4831=y
CONFIG_BACKLIGHT_SAHARA=y
CONFIG_BACKLIGHT_WM831X=y
CONFIG_BACKLIGHT_ADP5520=y
CONFIG_BACKLIGHT_ADP8860=y
CONFIG_BACKLIGHT_ADP8870=y
CONFIG_BACKLIGHT_88PM860X=y
CONFIG_BACKLIGHT_PCF50633=y
CONFIG_BACKLIGHT_AAT2870=y
CONFIG_BACKLIGHT_LM3630A=y
CONFIG_BACKLIGHT_LM3639=y
CONFIG_BACKLIGHT_LP855X=y
CONFIG_BACKLIGHT_LP8788=y
CONFIG_BACKLIGHT_PANDORA=y
CONFIG_BACKLIGHT_SKY81452=y
CONFIG_BACKLIGHT_TPS65217=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=y
CONFIG_BACKLIGHT_BD6107=y
CONFIG_BACKLIGHT_ARCXCNN=y
CONFIG_BACKLIGHT_RAVE_SP=y
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support
CONFIG_VGASTATE=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
CONFIG_MDA_CONSOLE=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
# end of Console display driver support
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support
CONFIG_DRM_ACCEL=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_CTL_FAST_LOOKUP=y
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
CONFIG_SND_PCM_XRUN_DEBUG=y
CONFIG_SND_CTL_INPUT_VALIDATION=y
CONFIG_SND_CTL_DEBUG=y
CONFIG_SND_JACK_INJECTION_DEBUG=y
CONFIG_SND_VMASTER=y
CONFIG_SND_DMA_SGBUF=y
CONFIG_SND_CTL_LED=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=y
CONFIG_SND_SEQ_MIDI=y
CONFIG_SND_SEQ_MIDI_EMUL=y
CONFIG_SND_SEQ_VIRMIDI=y
CONFIG_SND_MPU401_UART=y
CONFIG_SND_OPL3_LIB=y
CONFIG_SND_OPL4_LIB=y
CONFIG_SND_OPL3_LIB_SEQ=y
CONFIG_SND_OPL4_LIB_SEQ=y
CONFIG_SND_VX_LIB=y
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_PCSP=y
CONFIG_SND_DUMMY=y
CONFIG_SND_ALOOP=y
CONFIG_SND_VIRMIDI=y
CONFIG_SND_MTPAV=y
CONFIG_SND_MTS64=y
CONFIG_SND_SERIAL_U16550=y
CONFIG_SND_SERIAL_GENERIC=y
CONFIG_SND_MPU401=y
CONFIG_SND_PORTMAN2X4=y
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
CONFIG_SND_WSS_LIB=y
CONFIG_SND_SB_COMMON=y
CONFIG_SND_SB8_DSP=y
CONFIG_SND_SB16_DSP=y
CONFIG_SND_ISA=y
CONFIG_SND_ADLIB=y
CONFIG_SND_AD1816A=y
CONFIG_SND_AD1848=y
CONFIG_SND_ALS100=y
CONFIG_SND_AZT1605=y
CONFIG_SND_AZT2316=y
CONFIG_SND_AZT2320=y
CONFIG_SND_CMI8328=y
CONFIG_SND_CMI8330=y
CONFIG_SND_CS4231=y
CONFIG_SND_CS4236=y
CONFIG_SND_ES1688=y
CONFIG_SND_ES18XX=y
CONFIG_SND_SC6000=y
CONFIG_SND_GUSCLASSIC=y
CONFIG_SND_GUSEXTREME=y
CONFIG_SND_GUSMAX=y
CONFIG_SND_INTERWAVE=y
CONFIG_SND_INTERWAVE_STB=y
CONFIG_SND_JAZZ16=y
CONFIG_SND_OPL3SA2=y
CONFIG_SND_OPTI92X_AD1848=y
CONFIG_SND_OPTI92X_CS4231=y
CONFIG_SND_OPTI93X=y
CONFIG_SND_MIRO=y
CONFIG_SND_SB8=y
CONFIG_SND_SB16=y
CONFIG_SND_SBAWE=y
CONFIG_SND_SBAWE_SEQ=y
CONFIG_SND_SB16_CSP=y
CONFIG_SND_SSCAPE=y
CONFIG_SND_WAVEFRONT=y
CONFIG_SND_MSND_PINNACLE=y
CONFIG_SND_MSND_CLASSIC=y
CONFIG_SND_PCI=y
CONFIG_SND_AD1889=y
CONFIG_SND_ALS300=y
CONFIG_SND_ALS4000=y
CONFIG_SND_ALI5451=y
CONFIG_SND_ASIHPI=y
CONFIG_SND_ATIIXP=y
CONFIG_SND_ATIIXP_MODEM=y
CONFIG_SND_AU8810=y
CONFIG_SND_AU8820=y
CONFIG_SND_AU8830=y
CONFIG_SND_AW2=y
CONFIG_SND_AZT3328=y
CONFIG_SND_BT87X=y
CONFIG_SND_BT87X_OVERCLOCK=y
CONFIG_SND_CA0106=y
CONFIG_SND_CMIPCI=y
CONFIG_SND_OXYGEN_LIB=y
CONFIG_SND_OXYGEN=y
CONFIG_SND_CS4281=y
CONFIG_SND_CS46XX=y
CONFIG_SND_CS46XX_NEW_DSP=y
CONFIG_SND_CS5530=y
CONFIG_SND_CS5535AUDIO=y
CONFIG_SND_CTXFI=y
CONFIG_SND_DARLA20=y
CONFIG_SND_GINA20=y
CONFIG_SND_LAYLA20=y
CONFIG_SND_DARLA24=y
CONFIG_SND_GINA24=y
CONFIG_SND_LAYLA24=y
CONFIG_SND_MONA=y
CONFIG_SND_MIA=y
CONFIG_SND_ECHO3G=y
CONFIG_SND_INDIGO=y
CONFIG_SND_INDIGOIO=y
CONFIG_SND_INDIGODJ=y
CONFIG_SND_INDIGOIOX=y
CONFIG_SND_INDIGODJX=y
CONFIG_SND_EMU10K1=y
CONFIG_SND_EMU10K1_SEQ=y
CONFIG_SND_EMU10K1X=y
CONFIG_SND_ENS1370=y
CONFIG_SND_ENS1371=y
CONFIG_SND_ES1938=y
CONFIG_SND_ES1968=y
CONFIG_SND_ES1968_INPUT=y
CONFIG_SND_ES1968_RADIO=y
CONFIG_SND_FM801=y
CONFIG_SND_FM801_TEA575X_BOOL=y
CONFIG_SND_HDSP=y
#
# Don't forget to add built-in firmwares for HDSP driver
#
CONFIG_SND_HDSPM=y
CONFIG_SND_ICE1712=y
CONFIG_SND_ICE1724=y
CONFIG_SND_INTEL8X0=y
CONFIG_SND_INTEL8X0M=y
CONFIG_SND_KORG1212=y
CONFIG_SND_LOLA=y
CONFIG_SND_LX6464ES=y
CONFIG_SND_MAESTRO3=y
CONFIG_SND_MAESTRO3_INPUT=y
CONFIG_SND_MIXART=y
CONFIG_SND_NM256=y
CONFIG_SND_PCXHR=y
CONFIG_SND_RIPTIDE=y
CONFIG_SND_RME32=y
CONFIG_SND_RME96=y
CONFIG_SND_RME9652=y
CONFIG_SND_SIS7019=y
CONFIG_SND_SONICVIBES=y
CONFIG_SND_TRIDENT=y
CONFIG_SND_VIA82XX=y
CONFIG_SND_VIA82XX_MODEM=y
CONFIG_SND_VIRTUOSO=y
CONFIG_SND_VX222=y
CONFIG_SND_YMFPCI=y
#
# HD-Audio
#
CONFIG_SND_HDA=y
CONFIG_SND_HDA_GENERIC_LEDS=y
CONFIG_SND_HDA_INTEL=y
CONFIG_SND_HDA_HWDEP=y
CONFIG_SND_HDA_RECONFIG=y
CONFIG_SND_HDA_INPUT_BEEP=y
CONFIG_SND_HDA_INPUT_BEEP_MODE=1
CONFIG_SND_HDA_PATCH_LOADER=y
CONFIG_SND_HDA_SCODEC_CS35L41=y
CONFIG_SND_HDA_CS_DSP_CONTROLS=y
CONFIG_SND_HDA_SCODEC_CS35L41_I2C=y
CONFIG_SND_HDA_SCODEC_CS35L41_SPI=y
CONFIG_SND_HDA_CODEC_REALTEK=y
CONFIG_SND_HDA_CODEC_ANALOG=y
CONFIG_SND_HDA_CODEC_SIGMATEL=y
CONFIG_SND_HDA_CODEC_VIA=y
CONFIG_SND_HDA_CODEC_HDMI=y
CONFIG_SND_HDA_CODEC_CIRRUS=y
CONFIG_SND_HDA_CODEC_CS8409=y
CONFIG_SND_HDA_CODEC_CONEXANT=y
CONFIG_SND_HDA_CODEC_CA0110=y
CONFIG_SND_HDA_CODEC_CA0132=y
CONFIG_SND_HDA_CODEC_CA0132_DSP=y
CONFIG_SND_HDA_CODEC_CMEDIA=y
CONFIG_SND_HDA_CODEC_SI3054=y
CONFIG_SND_HDA_GENERIC=y
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y
# end of HD-Audio
CONFIG_SND_HDA_CORE=y
CONFIG_SND_HDA_DSP_LOADER=y
CONFIG_SND_HDA_COMPONENT=y
CONFIG_SND_HDA_I915=y
CONFIG_SND_HDA_EXT_CORE=y
CONFIG_SND_HDA_PREALLOC_SIZE=0
CONFIG_SND_INTEL_NHLT=y
CONFIG_SND_INTEL_DSP_CONFIG=y
CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
CONFIG_SND_INTEL_BYT_PREFER_SOF=y
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=y
CONFIG_SND_USB_USX2Y=y
CONFIG_SND_USB_CAIAQ=y
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_US122L=y
CONFIG_SND_USB_6FIRE=y
CONFIG_SND_USB_HIFACE=y
CONFIG_SND_BCD2000=y
CONFIG_SND_USB_LINE6=y
CONFIG_SND_USB_POD=y
CONFIG_SND_USB_PODHD=y
CONFIG_SND_USB_TONEPORT=y
CONFIG_SND_USB_VARIAX=y
CONFIG_SND_FIREWIRE=y
CONFIG_SND_FIREWIRE_LIB=y
CONFIG_SND_DICE=y
CONFIG_SND_OXFW=y
CONFIG_SND_ISIGHT=y
CONFIG_SND_FIREWORKS=y
CONFIG_SND_BEBOB=y
CONFIG_SND_FIREWIRE_DIGI00X=y
CONFIG_SND_FIREWIRE_TASCAM=y
CONFIG_SND_FIREWIRE_MOTU=y
CONFIG_SND_FIREFACE=y
CONFIG_SND_PCMCIA=y
CONFIG_SND_VXPOCKET=y
CONFIG_SND_PDAUDIOCF=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
CONFIG_SND_SOC_TOPOLOGY=y
CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=y
CONFIG_SND_SOC_UTILS_KUNIT_TEST=y
CONFIG_SND_SOC_ACPI=y
CONFIG_SND_SOC_ADI=y
CONFIG_SND_SOC_ADI_AXI_I2S=y
CONFIG_SND_SOC_ADI_AXI_SPDIF=y
CONFIG_SND_SOC_AMD_ACP=y
CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=y
CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=y
CONFIG_SND_SOC_AMD_ST_ES8336_MACH=y
CONFIG_SND_SOC_AMD_ACP3x=y
CONFIG_SND_SOC_AMD_RV_RT5682_MACH=y
CONFIG_SND_SOC_AMD_RENOIR=y
CONFIG_SND_SOC_AMD_RENOIR_MACH=y
CONFIG_SND_SOC_AMD_ACP5x=y
CONFIG_SND_SOC_AMD_VANGOGH_MACH=y
CONFIG_SND_SOC_AMD_ACP6x=y
CONFIG_SND_SOC_AMD_YC_MACH=y
CONFIG_SND_AMD_ACP_CONFIG=y
CONFIG_SND_SOC_AMD_ACP_COMMON=y
CONFIG_SND_SOC_AMD_ACP_PDM=y
CONFIG_SND_SOC_AMD_ACP_I2S=y
CONFIG_SND_SOC_AMD_ACP_PCM=y
CONFIG_SND_SOC_AMD_ACP_PCI=y
CONFIG_SND_AMD_ASOC_RENOIR=y
CONFIG_SND_AMD_ASOC_REMBRANDT=y
CONFIG_SND_SOC_AMD_MACH_COMMON=y
CONFIG_SND_SOC_AMD_LEGACY_MACH=y
CONFIG_SND_SOC_AMD_SOF_MACH=y
CONFIG_SND_SOC_AMD_RPL_ACP6x=y
CONFIG_SND_SOC_AMD_PS=y
CONFIG_SND_SOC_AMD_PS_MACH=y
CONFIG_SND_ATMEL_SOC=y
CONFIG_SND_SOC_MIKROE_PROTO=y
CONFIG_SND_BCM63XX_I2S_WHISTLER=y
CONFIG_SND_DESIGNWARE_I2S=y
CONFIG_SND_DESIGNWARE_PCM=y
#
# SoC Audio for Freescale CPUs
#
#
# Common SoC Audio options for Freescale CPUs:
#
CONFIG_SND_SOC_FSL_ASRC=y
CONFIG_SND_SOC_FSL_SAI=y
CONFIG_SND_SOC_FSL_MQS=y
CONFIG_SND_SOC_FSL_AUDMIX=y
CONFIG_SND_SOC_FSL_SSI=y
CONFIG_SND_SOC_FSL_SPDIF=y
CONFIG_SND_SOC_FSL_ESAI=y
CONFIG_SND_SOC_FSL_MICFIL=y
CONFIG_SND_SOC_FSL_EASRC=y
CONFIG_SND_SOC_FSL_XCVR=y
CONFIG_SND_SOC_FSL_UTILS=y
CONFIG_SND_SOC_FSL_RPMSG=y
CONFIG_SND_SOC_IMX_AUDMUX=y
# end of SoC Audio for Freescale CPUs
CONFIG_SND_I2S_HI6210_I2S=y
CONFIG_SND_SOC_IMG=y
CONFIG_SND_SOC_IMG_I2S_IN=y
CONFIG_SND_SOC_IMG_I2S_OUT=y
CONFIG_SND_SOC_IMG_PARALLEL_OUT=y
CONFIG_SND_SOC_IMG_SPDIF_IN=y
CONFIG_SND_SOC_IMG_SPDIF_OUT=y
CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=y
CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
CONFIG_SND_SOC_INTEL_SST=y
CONFIG_SND_SOC_INTEL_CATPT=y
CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=y
CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=y
CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=y
CONFIG_SND_SOC_INTEL_SKYLAKE=y
CONFIG_SND_SOC_INTEL_SKL=y
CONFIG_SND_SOC_INTEL_APL=y
CONFIG_SND_SOC_INTEL_KBL=y
CONFIG_SND_SOC_INTEL_GLK=y
CONFIG_SND_SOC_INTEL_CNL=y
CONFIG_SND_SOC_INTEL_CFL=y
CONFIG_SND_SOC_INTEL_CML_H=y
CONFIG_SND_SOC_INTEL_CML_LP=y
CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=y
CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=y
CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y
CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=y
CONFIG_SND_SOC_ACPI_INTEL_MATCH=y
CONFIG_SND_SOC_INTEL_AVS=y
#
# Intel AVS Machine drivers
#
#
# Available DSP configurations
#
CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=y
CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=y
CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=y
CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=y
CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=y
CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=y
CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=y
CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=y
CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=y
CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=y
CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=y
CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=y
CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=y
CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=y
# end of Intel AVS Machine drivers
CONFIG_SND_SOC_INTEL_MACH=y
CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y
CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=y
CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=y
CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=y
CONFIG_SND_SOC_INTEL_HASWELL_MACH=y
CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=y
CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=y
CONFIG_SND_SOC_INTEL_BROADWELL_MACH=y
CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=y
CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=y
CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=y
CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=y
CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=y
CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=y
CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=y
CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=y
CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=y
CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=y
CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=y
CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=y
CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=y
CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=y
CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=y
CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=y
CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=y
CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=y
CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=y
CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=y
CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=y
CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=y
CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=y
CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=y
CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=y
CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=y
CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=y
CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=y
CONFIG_SND_SOC_MTK_BTCVSD=y
CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_PCI_DEV=y
CONFIG_SND_SOC_SOF_PCI=y
CONFIG_SND_SOC_SOF_ACPI=y
CONFIG_SND_SOC_SOF_ACPI_DEV=y
CONFIG_SND_SOC_SOF_OF=y
CONFIG_SND_SOC_SOF_DEBUG_PROBES=y
CONFIG_SND_SOC_SOF_CLIENT=y
CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT=y
CONFIG_SND_SOC_SOF_FORCE_PROBE_WORKQUEUE=y
CONFIG_SND_SOC_SOF_NOCODEC=y
CONFIG_SND_SOC_SOF_NOCODEC_SUPPORT=y
CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS=y
CONFIG_SND_SOC_SOF_DEBUG=y
CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE=y
CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP=y
CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC=y
CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION=y
CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE=y
CONFIG_SND_SOC_SOF_DEBUG_ENABLE_FIRMWARE_TRACE=y
CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST=y
CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM=2
CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR=y
CONFIG_SND_SOC_SOF_DEBUG_RETAIN_DSP_CONTEXT=y
CONFIG_SND_SOC_SOF=y
CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
CONFIG_SND_SOC_SOF_IPC3=y
CONFIG_SND_SOC_SOF_INTEL_IPC4=y
CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=y
CONFIG_SND_SOC_SOF_AMD_COMMON=y
CONFIG_SND_SOC_SOF_AMD_RENOIR=y
CONFIG_SND_SOC_SOF_AMD_REMBRANDT=y
CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=y
CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=y
CONFIG_SND_SOC_SOF_INTEL_COMMON=y
CONFIG_SND_SOC_SOF_BAYTRAIL=y
CONFIG_SND_SOC_SOF_BROADWELL=y
CONFIG_SND_SOC_SOF_MERRIFIELD=y
CONFIG_SND_SOC_SOF_INTEL_SKL=y
CONFIG_SND_SOC_SOF_SKYLAKE=y
CONFIG_SND_SOC_SOF_KABYLAKE=y
CONFIG_SND_SOC_SOF_INTEL_APL=y
CONFIG_SND_SOC_SOF_APOLLOLAKE=y
CONFIG_SND_SOC_SOF_GEMINILAKE=y
CONFIG_SND_SOC_SOF_INTEL_CNL=y
CONFIG_SND_SOC_SOF_CANNONLAKE=y
CONFIG_SND_SOC_SOF_COFFEELAKE=y
CONFIG_SND_SOC_SOF_COMETLAKE=y
CONFIG_SND_SOC_SOF_INTEL_ICL=y
CONFIG_SND_SOC_SOF_ICELAKE=y
CONFIG_SND_SOC_SOF_JASPERLAKE=y
CONFIG_SND_SOC_SOF_INTEL_TGL=y
CONFIG_SND_SOC_SOF_TIGERLAKE=y
CONFIG_SND_SOC_SOF_ELKHARTLAKE=y
CONFIG_SND_SOC_SOF_ALDERLAKE=y
CONFIG_SND_SOC_SOF_INTEL_MTL=y
CONFIG_SND_SOC_SOF_METEORLAKE=y
CONFIG_SND_SOC_SOF_HDA_COMMON=y
CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=y
CONFIG_SND_SOC_SOF_HDA_PROBES=y
CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=y
CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=y
CONFIG_SND_SOC_SOF_XTENSA=y
#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support
CONFIG_SND_SOC_XILINX_I2S=y
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y
CONFIG_SND_SOC_XILINX_SPDIF=y
CONFIG_SND_SOC_XTFPGA_I2S=y
CONFIG_SND_SOC_I2C_AND_SPI=y
#
# CODEC drivers
#
CONFIG_SND_SOC_ARIZONA=y
CONFIG_SND_SOC_WM_ADSP=y
CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_ADAU_UTILS=y
CONFIG_SND_SOC_ADAU1372=y
CONFIG_SND_SOC_ADAU1372_I2C=y
CONFIG_SND_SOC_ADAU1372_SPI=y
CONFIG_SND_SOC_ADAU1701=y
CONFIG_SND_SOC_ADAU17X1=y
CONFIG_SND_SOC_ADAU1761=y
CONFIG_SND_SOC_ADAU1761_I2C=y
CONFIG_SND_SOC_ADAU1761_SPI=y
CONFIG_SND_SOC_ADAU7002=y
CONFIG_SND_SOC_ADAU7118=y
CONFIG_SND_SOC_ADAU7118_HW=y
CONFIG_SND_SOC_ADAU7118_I2C=y
CONFIG_SND_SOC_AK4104=y
CONFIG_SND_SOC_AK4118=y
CONFIG_SND_SOC_AK4375=y
CONFIG_SND_SOC_AK4458=y
CONFIG_SND_SOC_AK4554=y
CONFIG_SND_SOC_AK4613=y
CONFIG_SND_SOC_AK4642=y
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_AK5558=y
CONFIG_SND_SOC_ALC5623=y
CONFIG_SND_SOC_AW8738=y
CONFIG_SND_SOC_BD28623=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_CPCAP=y
CONFIG_SND_SOC_CROS_EC_CODEC=y
CONFIG_SND_SOC_CS35L32=y
CONFIG_SND_SOC_CS35L33=y
CONFIG_SND_SOC_CS35L34=y
CONFIG_SND_SOC_CS35L35=y
CONFIG_SND_SOC_CS35L36=y
CONFIG_SND_SOC_CS35L41_LIB=y
CONFIG_SND_SOC_CS35L41=y
CONFIG_SND_SOC_CS35L41_SPI=y
CONFIG_SND_SOC_CS35L41_I2C=y
CONFIG_SND_SOC_CS35L45_TABLES=y
CONFIG_SND_SOC_CS35L45=y
CONFIG_SND_SOC_CS35L45_SPI=y
CONFIG_SND_SOC_CS35L45_I2C=y
CONFIG_SND_SOC_CS42L42_CORE=y
CONFIG_SND_SOC_CS42L42=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L51_I2C=y
CONFIG_SND_SOC_CS42L52=y
CONFIG_SND_SOC_CS42L56=y
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS42L83=y
CONFIG_SND_SOC_CS4234=y
CONFIG_SND_SOC_CS4265=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CS4271_I2C=y
CONFIG_SND_SOC_CS4271_SPI=y
CONFIG_SND_SOC_CS42XX8=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_CS43130=y
CONFIG_SND_SOC_CS4341=y
CONFIG_SND_SOC_CS4349=y
CONFIG_SND_SOC_CS53L30=y
CONFIG_SND_SOC_CX2072X=y
CONFIG_SND_SOC_DA7213=y
CONFIG_SND_SOC_DA7219=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=y
CONFIG_SND_SOC_ES7241=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8326=y
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_GTM601=y
CONFIG_SND_SOC_HDAC_HDMI=y
CONFIG_SND_SOC_HDAC_HDA=y
CONFIG_SND_SOC_HDA=y
CONFIG_SND_SOC_ICS43432=y
CONFIG_SND_SOC_INNO_RK3036=y
CONFIG_SND_SOC_LOCHNAGAR_SC=y
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=y
CONFIG_SND_SOC_MAX9867=y
CONFIG_SND_SOC_MAX98927=y
CONFIG_SND_SOC_MAX98520=y
CONFIG_SND_SOC_MAX98373=y
CONFIG_SND_SOC_MAX98373_I2C=y
CONFIG_SND_SOC_MAX98373_SDW=y
CONFIG_SND_SOC_MAX98390=y
CONFIG_SND_SOC_MAX98396=y
CONFIG_SND_SOC_MAX9860=y
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1789=y
CONFIG_SND_SOC_PCM1789_I2C=y
CONFIG_SND_SOC_PCM179X=y
CONFIG_SND_SOC_PCM179X_I2C=y
CONFIG_SND_SOC_PCM179X_SPI=y
CONFIG_SND_SOC_PCM186X=y
CONFIG_SND_SOC_PCM186X_I2C=y
CONFIG_SND_SOC_PCM186X_SPI=y
CONFIG_SND_SOC_PCM3060=y
CONFIG_SND_SOC_PCM3060_I2C=y
CONFIG_SND_SOC_PCM3060_SPI=y
CONFIG_SND_SOC_PCM3168A=y
CONFIG_SND_SOC_PCM3168A_I2C=y
CONFIG_SND_SOC_PCM3168A_SPI=y
CONFIG_SND_SOC_PCM5102A=y
CONFIG_SND_SOC_PCM512x=y
CONFIG_SND_SOC_PCM512x_I2C=y
CONFIG_SND_SOC_PCM512x_SPI=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_RL6347A=y
CONFIG_SND_SOC_RT274=y
CONFIG_SND_SOC_RT286=y
CONFIG_SND_SOC_RT298=y
CONFIG_SND_SOC_RT1011=y
CONFIG_SND_SOC_RT1015=y
CONFIG_SND_SOC_RT1015P=y
CONFIG_SND_SOC_RT1019=y
CONFIG_SND_SOC_RT1308=y
CONFIG_SND_SOC_RT1308_SDW=y
CONFIG_SND_SOC_RT1316_SDW=y
CONFIG_SND_SOC_RT1318_SDW=y
CONFIG_SND_SOC_RT5514=y
CONFIG_SND_SOC_RT5514_SPI=y
CONFIG_SND_SOC_RT5616=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5645=y
CONFIG_SND_SOC_RT5651=y
CONFIG_SND_SOC_RT5659=y
CONFIG_SND_SOC_RT5660=y
CONFIG_SND_SOC_RT5663=y
CONFIG_SND_SOC_RT5670=y
CONFIG_SND_SOC_RT5677=y
CONFIG_SND_SOC_RT5677_SPI=y
CONFIG_SND_SOC_RT5682=y
CONFIG_SND_SOC_RT5682_I2C=y
CONFIG_SND_SOC_RT5682_SDW=y
CONFIG_SND_SOC_RT5682S=y
CONFIG_SND_SOC_RT700=y
CONFIG_SND_SOC_RT700_SDW=y
CONFIG_SND_SOC_RT711=y
CONFIG_SND_SOC_RT711_SDW=y
CONFIG_SND_SOC_RT711_SDCA_SDW=y
CONFIG_SND_SOC_RT715=y
CONFIG_SND_SOC_RT715_SDW=y
CONFIG_SND_SOC_RT715_SDCA_SDW=y
CONFIG_SND_SOC_RT9120=y
CONFIG_SND_SOC_SDW_MOCKUP=y
CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_SI476X=y
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SIGMADSP_I2C=y
CONFIG_SND_SOC_SIGMADSP_REGMAP=y
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIMPLE_MUX=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SRC4XXX_I2C=y
CONFIG_SND_SOC_SRC4XXX=y
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM4567=y
CONFIG_SND_SOC_STA32X=y
CONFIG_SND_SOC_STA350=y
CONFIG_SND_SOC_STI_SAS=y
CONFIG_SND_SOC_TAS2552=y
CONFIG_SND_SOC_TAS2562=y
CONFIG_SND_SOC_TAS2764=y
CONFIG_SND_SOC_TAS2770=y
CONFIG_SND_SOC_TAS2780=y
CONFIG_SND_SOC_TAS5086=y
CONFIG_SND_SOC_TAS571X=y
CONFIG_SND_SOC_TAS5720=y
CONFIG_SND_SOC_TAS5805M=y
CONFIG_SND_SOC_TAS6424=y
CONFIG_SND_SOC_TDA7419=y
CONFIG_SND_SOC_TFA9879=y
CONFIG_SND_SOC_TFA989X=y
CONFIG_SND_SOC_TLV320ADC3XXX=y
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC23_I2C=y
CONFIG_SND_SOC_TLV320AIC23_SPI=y
CONFIG_SND_SOC_TLV320AIC31XX=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC32X4_I2C=y
CONFIG_SND_SOC_TLV320AIC32X4_SPI=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320AIC3X_I2C=y
CONFIG_SND_SOC_TLV320AIC3X_SPI=y
CONFIG_SND_SOC_TLV320ADCX140=y
CONFIG_SND_SOC_TS3A227E=y
CONFIG_SND_SOC_TSCS42XX=y
CONFIG_SND_SOC_TSCS454=y
CONFIG_SND_SOC_UDA1334=y
CONFIG_SND_SOC_WCD9335=y
CONFIG_SND_SOC_WCD_MBHC=y
CONFIG_SND_SOC_WCD934X=y
CONFIG_SND_SOC_WCD938X=y
CONFIG_SND_SOC_WCD938X_SDW=y
CONFIG_SND_SOC_WM5102=y
CONFIG_SND_SOC_WM8510=y
CONFIG_SND_SOC_WM8523=y
CONFIG_SND_SOC_WM8524=y
CONFIG_SND_SOC_WM8580=y
CONFIG_SND_SOC_WM8711=y
CONFIG_SND_SOC_WM8728=y
CONFIG_SND_SOC_WM8731=y
CONFIG_SND_SOC_WM8731_I2C=y
CONFIG_SND_SOC_WM8731_SPI=y
CONFIG_SND_SOC_WM8737=y
CONFIG_SND_SOC_WM8741=y
CONFIG_SND_SOC_WM8750=y
CONFIG_SND_SOC_WM8753=y
CONFIG_SND_SOC_WM8770=y
CONFIG_SND_SOC_WM8776=y
CONFIG_SND_SOC_WM8782=y
CONFIG_SND_SOC_WM8804=y
CONFIG_SND_SOC_WM8804_I2C=y
CONFIG_SND_SOC_WM8804_SPI=y
CONFIG_SND_SOC_WM8903=y
CONFIG_SND_SOC_WM8904=y
CONFIG_SND_SOC_WM8940=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SOC_WM8961=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SOC_WM8974=y
CONFIG_SND_SOC_WM8978=y
CONFIG_SND_SOC_WM8985=y
CONFIG_SND_SOC_WSA881X=y
CONFIG_SND_SOC_WSA883X=y
CONFIG_SND_SOC_ZL38060=y
CONFIG_SND_SOC_MAX9759=y
CONFIG_SND_SOC_MT6351=y
CONFIG_SND_SOC_MT6358=y
CONFIG_SND_SOC_MT6660=y
CONFIG_SND_SOC_NAU8315=y
CONFIG_SND_SOC_NAU8540=y
CONFIG_SND_SOC_NAU8810=y
CONFIG_SND_SOC_NAU8821=y
CONFIG_SND_SOC_NAU8822=y
CONFIG_SND_SOC_NAU8824=y
CONFIG_SND_SOC_NAU8825=y
CONFIG_SND_SOC_TPA6130A2=y
CONFIG_SND_SOC_LPASS_MACRO_COMMON=y
CONFIG_SND_SOC_LPASS_WSA_MACRO=y
CONFIG_SND_SOC_LPASS_VA_MACRO=y
CONFIG_SND_SOC_LPASS_RX_MACRO=y
CONFIG_SND_SOC_LPASS_TX_MACRO=y
# end of CODEC drivers
CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD2=y
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=y
CONFIG_SND_TEST_COMPONENT=y
CONFIG_SND_X86=y
CONFIG_HDMI_LPE_AUDIO=y
CONFIG_SND_SYNTH_EMUX=y
CONFIG_SND_VIRTIO=y
CONFIG_AC97_BUS=y
#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
CONFIG_HID_ACCUTOUCH=y
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
CONFIG_HID_APPLEIR=y
CONFIG_HID_ASUS=y
CONFIG_HID_AUREAL=y
CONFIG_HID_BELKIN=y
CONFIG_HID_BETOP_FF=y
CONFIG_HID_BIGBEN_FF=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CORSAIR=y
CONFIG_HID_COUGAR=y
CONFIG_HID_MACALLY=y
CONFIG_HID_PRODIKEYS=y
CONFIG_HID_CMEDIA=y
CONFIG_HID_CP2112=y
CONFIG_HID_CREATIVE_SB0540=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=y
CONFIG_HID_ELAN=y
CONFIG_HID_ELECOM=y
CONFIG_HID_ELO=y
CONFIG_HID_EZKEY=y
CONFIG_HID_FT260=y
CONFIG_HID_GEMBIRD=y
CONFIG_HID_GFRM=y
CONFIG_HID_GLORIOUS=y
CONFIG_HID_HOLTEK=y
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=y
CONFIG_HID_GOOGLE_HAMMER=y
CONFIG_HID_VIVALDI=y
CONFIG_HID_GT683R=y
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
CONFIG_HID_VIEWSONIC=y
CONFIG_HID_VRC2=y
CONFIG_HID_XIAOMI=y
CONFIG_HID_GYRATION=y
CONFIG_HID_ICADE=y
CONFIG_HID_ITE=y
CONFIG_HID_JABRA=y
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=y
CONFIG_HID_LENOVO=y
CONFIG_HID_LETSKETCH=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_LOGITECH_DJ=y
CONFIG_HID_LOGITECH_HIDPP=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MALTRON=y
CONFIG_HID_MAYFLASH=y
CONFIG_HID_MEGAWORLD_FF=y
CONFIG_HID_REDRAGON=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NINTENDO=y
CONFIG_NINTENDO_FF=y
CONFIG_HID_NTI=y
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=y
CONFIG_HID_PLAYSTATION=y
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=y
CONFIG_HID_RAZER=y
CONFIG_HID_PRIMAX=y
CONFIG_HID_RETRODE=y
CONFIG_HID_ROCCAT=y
CONFIG_HID_SAITEK=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SEMITEK=y
CONFIG_HID_SIGMAMICRO=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=y
CONFIG_HID_STEAM=y
CONFIG_HID_STEELSERIES=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_RMI=y
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_HYPERV_MOUSE=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_TOPRE=y
CONFIG_HID_THINGM=y
CONFIG_HID_THRUSTMASTER=y
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=y
CONFIG_HID_U2FZERO=y
CONFIG_HID_WACOM=y
CONFIG_HID_WIIMOTE=y
CONFIG_HID_XINMO=y
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=y
CONFIG_HID_SENSOR_HUB=y
CONFIG_HID_SENSOR_CUSTOM_SENSOR=y
CONFIG_HID_ALPS=y
CONFIG_HID_MCP2221=y
CONFIG_HID_KUNIT_TEST=y
# end of Special HID drivers
#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support
#
# I2C HID support
#
CONFIG_I2C_HID_ACPI=y
CONFIG_I2C_HID_OF=y
CONFIG_I2C_HID_OF_ELAN=y
CONFIG_I2C_HID_OF_GOODIX=y
# end of I2C HID support
CONFIG_I2C_HID_CORE=y
#
# Surface System Aggregator Module HID support
#
CONFIG_SURFACE_HID=y
CONFIG_SURFACE_KBD=y
# end of Surface System Aggregator Module HID support
CONFIG_SURFACE_HID_CORE=y
# end of HID support
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
CONFIG_USB_FEW_INIT_RETRIES=y
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_PRODUCTLIST=y
CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y
CONFIG_USB_OTG_FSM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y
#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DBGCAP=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PCI_RENESAS=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=y
CONFIG_USB_ISP116X_HCD=y
CONFIG_USB_MAX3421_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
CONFIG_USB_OHCI_HCD_SSB=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_U132_HCD=y
CONFIG_USB_SL811_HCD=y
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_SL811_CS=y
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_HCD_BCMA=y
CONFIG_USB_HCD_SSB=y
CONFIG_USB_HCD_TEST_MODE=y
#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=y
CONFIG_USB_WDM=y
CONFIG_USB_TMC=y
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_STORAGE_REALTEK=y
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_USB_STORAGE_ALAUDA=y
CONFIG_USB_STORAGE_ONETOUCH=y
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_UAS=y
#
# USB Imaging devices
#
CONFIG_USB_MDC800=y
CONFIG_USB_MICROTEK=y
CONFIG_USBIP_CORE=y
CONFIG_USBIP_VHCI_HCD=y
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=y
CONFIG_USBIP_VUDC=y
CONFIG_USBIP_DEBUG=y
#
# USB dual-mode controller drivers
#
CONFIG_USB_CDNS_SUPPORT=y
CONFIG_USB_CDNS_HOST=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_CDNS3_PCI_WRAP=y
CONFIG_USB_CDNSP_PCI=y
CONFIG_USB_CDNSP_GADGET=y
CONFIG_USB_CDNSP_HOST=y
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y
#
# Platform Glue Layer
#
#
# MUSB DMA mode
#
CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y
#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set
#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=y
CONFIG_USB_DWC2_DEBUG=y
CONFIG_USB_DWC2_VERBOSE=y
CONFIG_USB_DWC2_TRACK_MISSED_SOFS=y
CONFIG_USB_DWC2_DEBUG_PERIODIC=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=y
CONFIG_USB_CHIPIDEA_MSM=y
CONFIG_USB_CHIPIDEA_IMX=y
CONFIG_USB_CHIPIDEA_GENERIC=y
CONFIG_USB_CHIPIDEA_TEGRA=y
CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y
#
# USB port drivers
#
CONFIG_USB_USS720=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
CONFIG_USB_SERIAL_AIRCABLE=y
CONFIG_USB_SERIAL_ARK3116=y
CONFIG_USB_SERIAL_BELKIN=y
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_WHITEHEAT=y
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=y
CONFIG_USB_SERIAL_EMPEG=y
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=y
CONFIG_USB_SERIAL_IPAQ=y
CONFIG_USB_SERIAL_IR=y
CONFIG_USB_SERIAL_EDGEPORT=y
CONFIG_USB_SERIAL_EDGEPORT_TI=y
CONFIG_USB_SERIAL_F81232=y
CONFIG_USB_SERIAL_F8153X=y
CONFIG_USB_SERIAL_GARMIN=y
CONFIG_USB_SERIAL_IPW=y
CONFIG_USB_SERIAL_IUU=y
CONFIG_USB_SERIAL_KEYSPAN_PDA=y
CONFIG_USB_SERIAL_KEYSPAN=y
CONFIG_USB_SERIAL_KLSI=y
CONFIG_USB_SERIAL_KOBIL_SCT=y
CONFIG_USB_SERIAL_MCT_U232=y
CONFIG_USB_SERIAL_METRO=y
CONFIG_USB_SERIAL_MOS7720=y
CONFIG_USB_SERIAL_MOS7715_PARPORT=y
CONFIG_USB_SERIAL_MOS7840=y
CONFIG_USB_SERIAL_MXUPORT=y
CONFIG_USB_SERIAL_NAVMAN=y
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=y
CONFIG_USB_SERIAL_QCAUX=y
CONFIG_USB_SERIAL_QUALCOMM=y
CONFIG_USB_SERIAL_SPCP8X5=y
CONFIG_USB_SERIAL_SAFE=y
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
CONFIG_USB_SERIAL_SYMBOL=y
CONFIG_USB_SERIAL_TI=y
CONFIG_USB_SERIAL_CYBERJACK=y
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_SERIAL_OMNINET=y
CONFIG_USB_SERIAL_OPTICON=y
CONFIG_USB_SERIAL_XSENS_MT=y
CONFIG_USB_SERIAL_WISHBONE=y
CONFIG_USB_SERIAL_SSU100=y
CONFIG_USB_SERIAL_QT2=y
CONFIG_USB_SERIAL_UPD78F0730=y
CONFIG_USB_SERIAL_XR=y
CONFIG_USB_SERIAL_DEBUG=y
#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=y
CONFIG_USB_EMI26=y
CONFIG_USB_ADUTUX=y
CONFIG_USB_SEVSEG=y
CONFIG_USB_LEGOTOWER=y
CONFIG_USB_LCD=y
CONFIG_USB_CYPRESS_CY7C63=y
CONFIG_USB_CYTHERM=y
CONFIG_USB_IDMOUSE=y
CONFIG_USB_FTDI_ELAN=y
CONFIG_USB_APPLEDISPLAY=y
CONFIG_APPLE_MFI_FASTCHARGE=y
CONFIG_USB_SISUSBVGA=y
CONFIG_USB_LD=y
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_IOWARRIOR=y
CONFIG_USB_TEST=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_ISIGHTFW=y
CONFIG_USB_YUREX=y
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_HSIC_USB4604=y
CONFIG_USB_LINK_LAYER_TEST=y
CONFIG_USB_CHAOSKEY=y
CONFIG_USB_ONBOARD_HUB=y
CONFIG_USB_ATM=y
CONFIG_USB_SPEEDTOUCH=y
CONFIG_USB_CXACRU=y
CONFIG_USB_UEAGLEATM=y
CONFIG_USB_XUSBATM=y
#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_TAHVO_USB=y
CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
CONFIG_USB_ISP1301=y
# end of USB Physical Layer drivers
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG=y
CONFIG_USB_GADGET_VERBOSE=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_U_SERIAL_CONSOLE=y
#
# USB Peripheral Controller
#
CONFIG_USB_FUSB300=y
CONFIG_USB_GR_UDC=y
CONFIG_USB_R8A66597=y
CONFIG_USB_PXA27X=y
CONFIG_USB_MV_UDC=y
CONFIG_USB_MV_U3D=y
CONFIG_USB_SNP_CORE=y
CONFIG_USB_SNP_UDC_PLAT=y
CONFIG_USB_M66592=y
CONFIG_USB_BDC_UDC=y
CONFIG_USB_AMD5536UDC=y
CONFIG_USB_NET2272=y
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=y
CONFIG_USB_GOKU=y
CONFIG_USB_EG20T=y
CONFIG_USB_GADGET_XILINX=y
CONFIG_USB_MAX3420_UDC=y
CONFIG_USB_DUMMY_HCD=y
# end of USB Peripheral Controller
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_SS_LB=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_OBEX=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_PHONET=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC1_LEGACY=y
CONFIG_USB_F_UAC2=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MIDI=y
CONFIG_USB_F_HID=y
CONFIG_USB_F_PRINTER=y
CONFIG_USB_F_TCM=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_PHONET=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y
#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=y
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=y
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=y
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=y
CONFIG_USB_GADGETFS=y
CONFIG_USB_FUNCTIONFS=y
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=y
CONFIG_USB_GADGET_TARGET=y
CONFIG_USB_G_SERIAL=y
CONFIG_USB_MIDI_GADGET=y
CONFIG_USB_G_PRINTER=y
CONFIG_USB_CDC_COMPOSITE=y
CONFIG_USB_G_NOKIA=y
CONFIG_USB_G_ACM_MS=y
CONFIG_USB_G_MULTI=y
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=y
CONFIG_USB_G_DBGP=y
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=y
CONFIG_USB_RAW_GADGET=y
# end of USB Gadget precomposed configurations
CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_MT6360=y
CONFIG_TYPEC_TCPCI_MT6370=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_WCOVE=y
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_CCG=y
CONFIG_UCSI_ACPI=y
CONFIG_UCSI_STM32G0=y
CONFIG_TYPEC_TPS6598X=y
CONFIG_TYPEC_ANX7411=y
CONFIG_TYPEC_RT1719=y
CONFIG_TYPEC_HD3SS3220=y
CONFIG_TYPEC_STUSB160X=y
CONFIG_TYPEC_WUSB3801=y
#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=y
CONFIG_TYPEC_MUX_PI3USB30532=y
CONFIG_TYPEC_MUX_INTEL_PMC=y
# end of USB Type-C Multiplexer/DeMultiplexer Switch support
#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=y
CONFIG_TYPEC_NVIDIA_ALTMODE=y
# end of USB Type-C Alternate Mode drivers
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_ROLES_INTEL_XHCI=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SD8787=y
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_SDIO_UART=y
CONFIG_MMC_TEST=y
CONFIG_MMC_CRYPTO=y
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_DEBUG=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=y
CONFIG_MMC_SDHCI_MILBEAUT=y
CONFIG_MMC_WBSD=y
CONFIG_MMC_ALCOR=y
CONFIG_MMC_TIFM_SD=y
CONFIG_MMC_SPI=y
CONFIG_MMC_SDRICOH_CS=y
CONFIG_MMC_CB710=y
CONFIG_MMC_VIA_SDMMC=y
CONFIG_MMC_VUB300=y
CONFIG_MMC_USHC=y
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_REALTEK_PCI=y
CONFIG_MMC_REALTEK_USB=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MMC_SDHCI_OMAP=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
CONFIG_MMC_LITEX=y
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFS_BSG=y
CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_SCSI_UFS_HPB=y
CONFIG_SCSI_UFS_FAULT_INJECTION=y
CONFIG_SCSI_UFS_HWMON=y
CONFIG_SCSI_UFSHCD_PCI=y
CONFIG_SCSI_UFS_DWC_TC_PCI=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_CDNS_PLATFORM=y
CONFIG_SCSI_UFS_DWC_TC_PLATFORM=y
CONFIG_MEMSTICK=y
CONFIG_MEMSTICK_DEBUG=y
#
# MemoryStick drivers
#
CONFIG_MEMSTICK_UNSAFE_RESUME=y
CONFIG_MSPRO_BLOCK=y
CONFIG_MS_BLOCK=y
#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=y
CONFIG_MEMSTICK_JMICRON_38X=y
CONFIG_MEMSTICK_R592=y
CONFIG_MEMSTICK_REALTEK_PCI=y
CONFIG_MEMSTICK_REALTEK_USB=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
#
# LED drivers
#
CONFIG_LEDS_88PM860X=y
CONFIG_LEDS_AN30259A=y
CONFIG_LEDS_APU=y
CONFIG_LEDS_AW2013=y
CONFIG_LEDS_BCM6328=y
CONFIG_LEDS_BCM6358=y
CONFIG_LEDS_CPCAP=y
CONFIG_LEDS_CR0014114=y
CONFIG_LEDS_EL15203000=y
CONFIG_LEDS_LM3530=y
CONFIG_LEDS_LM3532=y
CONFIG_LEDS_LM3533=y
CONFIG_LEDS_LM3642=y
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_MT6323=y
CONFIG_LEDS_NET48XX=y
CONFIG_LEDS_WRAP=y
CONFIG_LEDS_PCA9532=y
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=y
CONFIG_LEDS_LP3952=y
CONFIG_LEDS_LP50XX=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=y
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP8501=y
CONFIG_LEDS_LP8788=y
CONFIG_LEDS_LP8860=y
CONFIG_LEDS_PCA955X=y
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=y
CONFIG_LEDS_WM831X_STATUS=y
CONFIG_LEDS_WM8350=y
CONFIG_LEDS_DA903X=y
CONFIG_LEDS_DA9052=y
CONFIG_LEDS_DAC124S085=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=y
CONFIG_LEDS_INTEL_SS4200=y
CONFIG_LEDS_LT3593=y
CONFIG_LEDS_ADP5520=y
CONFIG_LEDS_MC13783=y
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LEDS_MAX77650=y
CONFIG_LEDS_MAX8997=y
CONFIG_LEDS_LM355x=y
CONFIG_LEDS_OT200=y
CONFIG_LEDS_MENF21BMC=y
CONFIG_LEDS_IS31FL319X=y
CONFIG_LEDS_IS31FL32XX=y
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=y
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXCPLD=y
CONFIG_LEDS_MLXREG=y
CONFIG_LEDS_USER=y
CONFIG_LEDS_NIC78BX=y
CONFIG_LEDS_SPI_BYTE=y
CONFIG_LEDS_TI_LMU_COMMON=y
CONFIG_LEDS_LM3697=y
CONFIG_LEDS_LM36274=y
CONFIG_LEDS_TPS6105X=y
CONFIG_LEDS_LGM=y
#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=y
CONFIG_LEDS_AS3645A=y
CONFIG_LEDS_KTD2692=y
CONFIG_LEDS_LM3601X=y
CONFIG_LEDS_MAX77693=y
CONFIG_LEDS_MT6360=y
CONFIG_LEDS_RT4505=y
CONFIG_LEDS_RT8515=y
CONFIG_LEDS_SGM3140=y
#
# RGB LED drivers
#
CONFIG_LEDS_PWM_MULTICOLOR=y
CONFIG_LEDS_QCOM_LPG=y
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_LEDS_TRIGGER_TTY=y
#
# Simple LED drivers
#
CONFIG_LEDS_SIEMENS_SIMATIC_IPC=y
CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y
#
# Speakup console speech
#
CONFIG_SPEAKUP=y
CONFIG_SPEAKUP_SERIALIO=y
CONFIG_SPEAKUP_SYNTH_ACNTSA=y
CONFIG_SPEAKUP_SYNTH_ACNTPC=y
CONFIG_SPEAKUP_SYNTH_APOLLO=y
CONFIG_SPEAKUP_SYNTH_AUDPTR=y
CONFIG_SPEAKUP_SYNTH_BNS=y
CONFIG_SPEAKUP_SYNTH_DECTLK=y
CONFIG_SPEAKUP_SYNTH_DECEXT=y
CONFIG_SPEAKUP_SYNTH_DECPC=m
CONFIG_SPEAKUP_SYNTH_DTLK=y
CONFIG_SPEAKUP_SYNTH_KEYPC=y
CONFIG_SPEAKUP_SYNTH_LTLK=y
CONFIG_SPEAKUP_SYNTH_SOFT=y
CONFIG_SPEAKUP_SYNTH_SPKOUT=y
CONFIG_SPEAKUP_SYNTH_TXPRT=y
CONFIG_SPEAKUP_SYNTH_DUMMY=y
# end of Speakup console speech
CONFIG_INFINIBAND=y
CONFIG_INFINIBAND_USER_MAD=y
CONFIG_INFINIBAND_USER_ACCESS=y
CONFIG_INFINIBAND_USER_MEM=y
CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
CONFIG_INFINIBAND_ADDR_TRANS=y
CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
CONFIG_INFINIBAND_CXGB4=y
CONFIG_INFINIBAND_IRDMA=y
CONFIG_MLX4_INFINIBAND=y
CONFIG_MLX5_INFINIBAND=y
CONFIG_INFINIBAND_MTHCA=y
CONFIG_INFINIBAND_MTHCA_DEBUG=y
CONFIG_INFINIBAND_OCRDMA=y
CONFIG_INFINIBAND_USNIC=y
CONFIG_INFINIBAND_VMWARE_PVRDMA=y
CONFIG_INFINIBAND_IPOIB=y
CONFIG_INFINIBAND_IPOIB_CM=y
CONFIG_INFINIBAND_IPOIB_DEBUG=y
CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
CONFIG_INFINIBAND_SRP=y
CONFIG_INFINIBAND_SRPT=y
CONFIG_INFINIBAND_ISER=y
CONFIG_INFINIBAND_ISERT=y
CONFIG_INFINIBAND_RTRS=y
CONFIG_INFINIBAND_RTRS_CLIENT=y
CONFIG_INFINIBAND_RTRS_SERVER=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_DEBUG=y
CONFIG_EDAC_DECODE_MCE=y
CONFIG_EDAC_GHES=y
CONFIG_EDAC_AMD64=y
CONFIG_EDAC_AMD76X=y
CONFIG_EDAC_E7XXX=y
CONFIG_EDAC_E752X=y
CONFIG_EDAC_I82875P=y
CONFIG_EDAC_I82975X=y
CONFIG_EDAC_I3000=y
CONFIG_EDAC_I3200=y
CONFIG_EDAC_IE31200=y
CONFIG_EDAC_X38=y
CONFIG_EDAC_I5400=y
CONFIG_EDAC_I7CORE=y
CONFIG_EDAC_I82860=y
CONFIG_EDAC_R82600=y
CONFIG_EDAC_I5100=y
CONFIG_EDAC_I7300=y
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
CONFIG_RTC_DEBUG=y
CONFIG_RTC_LIB_KUNIT_TEST=y
CONFIG_RTC_NVMEM=y
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_TEST=y
#
# I2C RTC drivers
#
CONFIG_RTC_DRV_88PM860X=y
CONFIG_RTC_DRV_88PM80X=y
CONFIG_RTC_DRV_ABB5ZES3=y
CONFIG_RTC_DRV_ABEOZ9=y
CONFIG_RTC_DRV_ABX80X=y
CONFIG_RTC_DRV_AS3722=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=y
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_LP8788=y
CONFIG_RTC_DRV_MAX6900=y
CONFIG_RTC_DRV_MAX8907=y
CONFIG_RTC_DRV_MAX8925=y
CONFIG_RTC_DRV_MAX8998=y
CONFIG_RTC_DRV_MAX8997=y
CONFIG_RTC_DRV_MAX77686=y
CONFIG_RTC_DRV_NCT3018Y=y
CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_DRV_RS5C372=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_ISL12022=y
CONFIG_RTC_DRV_ISL12026=y
CONFIG_RTC_DRV_X1205=y
CONFIG_RTC_DRV_PCF8523=y
CONFIG_RTC_DRV_PCF85063=y
CONFIG_RTC_DRV_PCF85363=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=y
CONFIG_RTC_DRV_M41T80=y
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BD70528=y
CONFIG_RTC_DRV_BQ32K=y
CONFIG_RTC_DRV_TWL4030=y
CONFIG_RTC_DRV_PALMAS=y
CONFIG_RTC_DRV_TPS6586X=y
CONFIG_RTC_DRV_TPS65910=y
CONFIG_RTC_DRV_RC5T583=y
CONFIG_RTC_DRV_RC5T619=y
CONFIG_RTC_DRV_S35390A=y
CONFIG_RTC_DRV_FM3130=y
CONFIG_RTC_DRV_RX8010=y
CONFIG_RTC_DRV_RX8581=y
CONFIG_RTC_DRV_RX8025=y
CONFIG_RTC_DRV_EM3027=y
CONFIG_RTC_DRV_RV3028=y
CONFIG_RTC_DRV_RV3032=y
CONFIG_RTC_DRV_RV8803=y
CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_SD3078=y
#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=y
CONFIG_RTC_DRV_M41T94=y
CONFIG_RTC_DRV_DS1302=y
CONFIG_RTC_DRV_DS1305=y
CONFIG_RTC_DRV_DS1343=y
CONFIG_RTC_DRV_DS1347=y
CONFIG_RTC_DRV_DS1390=y
CONFIG_RTC_DRV_MAX6916=y
CONFIG_RTC_DRV_R9701=y
CONFIG_RTC_DRV_RX4581=y
CONFIG_RTC_DRV_RS5C348=y
CONFIG_RTC_DRV_MAX6902=y
CONFIG_RTC_DRV_PCF2123=y
CONFIG_RTC_DRV_MCP795=y
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=y
CONFIG_RTC_DRV_RV3029C2=y
CONFIG_RTC_DRV_RV3029_HWMON=y
CONFIG_RTC_DRV_RX6110=y
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_DS1286=y
CONFIG_RTC_DRV_DS1511=y
CONFIG_RTC_DRV_DS1553=y
CONFIG_RTC_DRV_DS1685_FAMILY=y
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=y
CONFIG_RTC_DRV_DS2404=y
CONFIG_RTC_DRV_DA9052=y
CONFIG_RTC_DRV_DA9055=y
CONFIG_RTC_DRV_DA9063=y
CONFIG_RTC_DRV_STK17TA8=y
CONFIG_RTC_DRV_M48T86=y
CONFIG_RTC_DRV_M48T35=y
CONFIG_RTC_DRV_M48T59=y
CONFIG_RTC_DRV_MSM6242=y
CONFIG_RTC_DRV_BQ4802=y
CONFIG_RTC_DRV_RP5C01=y
CONFIG_RTC_DRV_V3020=y
CONFIG_RTC_DRV_WM831X=y
CONFIG_RTC_DRV_WM8350=y
CONFIG_RTC_DRV_PCF50633=y
CONFIG_RTC_DRV_ZYNQMP=y
CONFIG_RTC_DRV_CROS_EC=y
CONFIG_RTC_DRV_NTXEC=y
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_CADENCE=y
CONFIG_RTC_DRV_FTRTC010=y
CONFIG_RTC_DRV_PCAP=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MT6397=y
CONFIG_RTC_DRV_R7301=y
CONFIG_RTC_DRV_CPCAP=y
#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=y
CONFIG_RTC_DRV_GOLDFISH=y
CONFIG_RTC_DRV_WILCO_EC=y
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES_DEBUG=y
CONFIG_DMADEVICES_VDEBUG=y
#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
CONFIG_ALTERA_MSGDMA=y
CONFIG_DW_AXI_DMAC=y
CONFIG_FSL_EDMA=y
CONFIG_INTEL_IDMA64=y
CONFIG_PCH_DMA=y
CONFIG_PLX_DMA=y
CONFIG_TIMB_DMA=y
CONFIG_XILINX_ZYNQMP_DPDMA=y
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_DW_DMAC_PCI=y
CONFIG_DW_EDMA=y
CONFIG_DW_EDMA_PCIE=y
CONFIG_HSU_DMA=y
CONFIG_HSU_DMA_PCI=y
CONFIG_SF_PDMA=y
CONFIG_INTEL_LDMA=y
#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
CONFIG_DMATEST=y
CONFIG_DMA_ENGINE_RAID=y
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_MOVE_NOTIFY=y
CONFIG_DMABUF_DEBUG=y
CONFIG_DMABUF_SELFTESTS=y
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# end of DMABUF options
CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_LINEDISP=y
CONFIG_HD44780_COMMON=y
CONFIG_HD44780=y
CONFIG_KS0108=y
CONFIG_KS0108_PORT=0x378
CONFIG_KS0108_DELAY=2
CONFIG_CFAG12864B=y
CONFIG_CFAG12864B_RATE=20
CONFIG_IMG_ASCII_LCD=y
CONFIG_HT16K33=y
CONFIG_LCD2S=y
CONFIG_PARPORT_PANEL=y
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
CONFIG_PANEL_CHANGE_MESSAGE=y
CONFIG_PANEL_BOOT_MESSAGE=""
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_PANEL=y
CONFIG_UIO=y
CONFIG_UIO_CIF=y
CONFIG_UIO_PDRV_GENIRQ=y
CONFIG_UIO_DMEM_GENIRQ=y
CONFIG_UIO_AEC=y
CONFIG_UIO_SERCOS3=y
CONFIG_UIO_PCI_GENERIC=y
CONFIG_UIO_NETX=y
CONFIG_UIO_PRUSS=y
CONFIG_UIO_MF624=y
CONFIG_UIO_HV_GENERIC=y
CONFIG_UIO_DFL=y
CONFIG_VFIO=y
CONFIG_VFIO_CONTAINER=y
CONFIG_VFIO_IOMMU_TYPE1=y
CONFIG_VFIO_NOIOMMU=y
CONFIG_VFIO_VIRQFD=y
CONFIG_VFIO_PCI_CORE=y
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=y
CONFIG_VFIO_PCI_VGA=y
CONFIG_VFIO_PCI_IGD=y
CONFIG_MLX5_VFIO_PCI=y
CONFIG_VFIO_MDEV=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
CONFIG_VBOXGUEST=y
CONFIG_NITRO_ENCLAVES=y
CONFIG_NITRO_ENCLAVES_MISC_DEV_TEST=y
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_VDPA=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
CONFIG_VDPA=y
CONFIG_VDPA_SIM=y
CONFIG_VDPA_SIM_NET=y
CONFIG_VDPA_SIM_BLOCK=y
CONFIG_VDPA_USER=y
CONFIG_IFCVF=y
CONFIG_MLX5_VDPA=y
CONFIG_MLX5_VDPA_NET=y
CONFIG_VP_VDPA=y
CONFIG_ALIBABA_ENI_VDPA=y
CONFIG_VHOST_IOTLB=y
CONFIG_VHOST_RING=y
CONFIG_VHOST=y
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_SCSI=y
CONFIG_VHOST_VSOCK=y
CONFIG_VHOST_VDPA=y
CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y
#
# Microsoft Hyper-V guest support
#
CONFIG_HYPERV=y
CONFIG_HYPERV_TIMER=y
CONFIG_HYPERV_UTILS=y
CONFIG_HYPERV_BALLOON=y
# end of Microsoft Hyper-V guest support
CONFIG_GREYBUS=y
CONFIG_GREYBUS_ES2=y
CONFIG_COMEDI=y
CONFIG_COMEDI_DEBUG=y
CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
CONFIG_COMEDI_MISC_DRIVERS=y
CONFIG_COMEDI_BOND=y
CONFIG_COMEDI_TEST=y
CONFIG_COMEDI_PARPORT=y
CONFIG_COMEDI_SSV_DNP=y
CONFIG_COMEDI_ISA_DRIVERS=y
CONFIG_COMEDI_PCL711=y
CONFIG_COMEDI_PCL724=y
CONFIG_COMEDI_PCL726=y
CONFIG_COMEDI_PCL730=y
CONFIG_COMEDI_PCL812=y
CONFIG_COMEDI_PCL816=y
CONFIG_COMEDI_PCL818=y
CONFIG_COMEDI_PCM3724=y
CONFIG_COMEDI_AMPLC_DIO200_ISA=y
CONFIG_COMEDI_AMPLC_PC236_ISA=y
CONFIG_COMEDI_AMPLC_PC263_ISA=y
CONFIG_COMEDI_RTI800=y
CONFIG_COMEDI_RTI802=y
CONFIG_COMEDI_DAC02=y
CONFIG_COMEDI_DAS16M1=y
CONFIG_COMEDI_DAS08_ISA=y
CONFIG_COMEDI_DAS16=y
CONFIG_COMEDI_DAS800=y
CONFIG_COMEDI_DAS1800=y
CONFIG_COMEDI_DAS6402=y
CONFIG_COMEDI_DT2801=y
CONFIG_COMEDI_DT2811=y
CONFIG_COMEDI_DT2814=y
CONFIG_COMEDI_DT2815=y
CONFIG_COMEDI_DT2817=y
CONFIG_COMEDI_DT282X=y
CONFIG_COMEDI_DMM32AT=y
CONFIG_COMEDI_FL512=y
CONFIG_COMEDI_AIO_AIO12_8=y
CONFIG_COMEDI_AIO_IIRO_16=y
CONFIG_COMEDI_II_PCI20KC=y
CONFIG_COMEDI_C6XDIGIO=y
CONFIG_COMEDI_MPC624=y
CONFIG_COMEDI_ADQ12B=y
CONFIG_COMEDI_NI_AT_A2150=y
CONFIG_COMEDI_NI_AT_AO=y
CONFIG_COMEDI_NI_ATMIO=y
CONFIG_COMEDI_NI_ATMIO16D=y
CONFIG_COMEDI_NI_LABPC_ISA=y
CONFIG_COMEDI_PCMAD=y
CONFIG_COMEDI_PCMDA12=y
CONFIG_COMEDI_PCMMIO=y
CONFIG_COMEDI_PCMUIO=y
CONFIG_COMEDI_MULTIQ3=y
CONFIG_COMEDI_S526=y
CONFIG_COMEDI_PCI_DRIVERS=y
CONFIG_COMEDI_8255_PCI=y
CONFIG_COMEDI_ADDI_WATCHDOG=y
CONFIG_COMEDI_ADDI_APCI_1032=y
CONFIG_COMEDI_ADDI_APCI_1500=y
CONFIG_COMEDI_ADDI_APCI_1516=y
CONFIG_COMEDI_ADDI_APCI_1564=y
CONFIG_COMEDI_ADDI_APCI_16XX=y
CONFIG_COMEDI_ADDI_APCI_2032=y
CONFIG_COMEDI_ADDI_APCI_2200=y
CONFIG_COMEDI_ADDI_APCI_3120=y
CONFIG_COMEDI_ADDI_APCI_3501=y
CONFIG_COMEDI_ADDI_APCI_3XXX=y
CONFIG_COMEDI_ADL_PCI6208=y
CONFIG_COMEDI_ADL_PCI7X3X=y
CONFIG_COMEDI_ADL_PCI8164=y
CONFIG_COMEDI_ADL_PCI9111=y
CONFIG_COMEDI_ADL_PCI9118=y
CONFIG_COMEDI_ADV_PCI1710=y
CONFIG_COMEDI_ADV_PCI1720=y
CONFIG_COMEDI_ADV_PCI1723=y
CONFIG_COMEDI_ADV_PCI1724=y
CONFIG_COMEDI_ADV_PCI1760=y
CONFIG_COMEDI_ADV_PCI_DIO=y
CONFIG_COMEDI_AMPLC_DIO200_PCI=y
CONFIG_COMEDI_AMPLC_PC236_PCI=y
CONFIG_COMEDI_AMPLC_PC263_PCI=y
CONFIG_COMEDI_AMPLC_PCI224=y
CONFIG_COMEDI_AMPLC_PCI230=y
CONFIG_COMEDI_CONTEC_PCI_DIO=y
CONFIG_COMEDI_DAS08_PCI=y
CONFIG_COMEDI_DT3000=y
CONFIG_COMEDI_DYNA_PCI10XX=y
CONFIG_COMEDI_GSC_HPDI=y
CONFIG_COMEDI_MF6X4=y
CONFIG_COMEDI_ICP_MULTI=y
CONFIG_COMEDI_DAQBOARD2000=y
CONFIG_COMEDI_JR3_PCI=y
CONFIG_COMEDI_KE_COUNTER=y
CONFIG_COMEDI_CB_PCIDAS64=y
CONFIG_COMEDI_CB_PCIDAS=y
CONFIG_COMEDI_CB_PCIDDA=y
CONFIG_COMEDI_CB_PCIMDAS=y
CONFIG_COMEDI_CB_PCIMDDA=y
CONFIG_COMEDI_ME4000=y
CONFIG_COMEDI_ME_DAQ=y
CONFIG_COMEDI_NI_6527=y
CONFIG_COMEDI_NI_65XX=y
CONFIG_COMEDI_NI_660X=y
CONFIG_COMEDI_NI_670X=y
CONFIG_COMEDI_NI_LABPC_PCI=y
CONFIG_COMEDI_NI_PCIDIO=y
CONFIG_COMEDI_NI_PCIMIO=y
CONFIG_COMEDI_RTD520=y
CONFIG_COMEDI_S626=y
CONFIG_COMEDI_MITE=y
CONFIG_COMEDI_NI_TIOCMD=y
CONFIG_COMEDI_PCMCIA_DRIVERS=y
CONFIG_COMEDI_CB_DAS16_CS=y
CONFIG_COMEDI_DAS08_CS=y
CONFIG_COMEDI_NI_DAQ_700_CS=y
CONFIG_COMEDI_NI_DAQ_DIO24_CS=y
CONFIG_COMEDI_NI_LABPC_CS=y
CONFIG_COMEDI_NI_MIO_CS=y
CONFIG_COMEDI_QUATECH_DAQP_CS=y
CONFIG_COMEDI_USB_DRIVERS=y
CONFIG_COMEDI_DT9812=y
CONFIG_COMEDI_NI_USB6501=y
CONFIG_COMEDI_USBDUX=y
CONFIG_COMEDI_USBDUXFAST=y
CONFIG_COMEDI_USBDUXSIGMA=y
CONFIG_COMEDI_VMK80XX=y
CONFIG_COMEDI_8254=y
CONFIG_COMEDI_8255=y
CONFIG_COMEDI_8255_SA=y
CONFIG_COMEDI_KCOMEDILIB=y
CONFIG_COMEDI_AMPLC_DIO200=y
CONFIG_COMEDI_AMPLC_PC236=y
CONFIG_COMEDI_DAS08=y
CONFIG_COMEDI_ISADMA=y
CONFIG_COMEDI_NI_LABPC=y
CONFIG_COMEDI_NI_LABPC_ISADMA=y
CONFIG_COMEDI_NI_TIO=y
CONFIG_COMEDI_NI_ROUTING=y
CONFIG_COMEDI_TESTS=y
CONFIG_COMEDI_TESTS_EXAMPLE=y
CONFIG_COMEDI_TESTS_NI_ROUTES=y
CONFIG_STAGING=y
CONFIG_PRISM2_USB=y
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_RTL8723BS=m
CONFIG_R8712U=y
CONFIG_R8188EU=m
CONFIG_RTS5208=y
CONFIG_VT6655=m
CONFIG_VT6656=m
#
# IIO staging drivers
#
#
# Accelerometers
#
CONFIG_ADIS16203=y
CONFIG_ADIS16240=y
# end of Accelerometers
#
# Analog to digital converters
#
CONFIG_AD7816=y
# end of Analog to digital converters
#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=y
CONFIG_ADT7316_SPI=y
CONFIG_ADT7316_I2C=y
# end of Analog digital bi-direction converters
#
# Direct Digital Synthesis
#
CONFIG_AD9832=y
CONFIG_AD9834=y
# end of Direct Digital Synthesis
#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=y
# end of Network Analyzer, Impedance Converters
#
# Active energy metering IC
#
CONFIG_ADE7854=y
CONFIG_ADE7854_I2C=y
CONFIG_ADE7854_SPI=y
# end of Active energy metering IC
#
# Resolver to digital converters
#
CONFIG_AD2S1210=y
# end of Resolver to digital converters
# end of IIO staging drivers
CONFIG_FB_SM750=y
CONFIG_STAGING_MEDIA=y
CONFIG_INTEL_ATOMISP=y
CONFIG_VIDEO_ATOMISP=y
CONFIG_VIDEO_ATOMISP_ISP2401=y
CONFIG_VIDEO_ATOMISP_OV2722=y
CONFIG_VIDEO_ATOMISP_GC2235=y
CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=y
CONFIG_VIDEO_ATOMISP_MT9M114=y
CONFIG_VIDEO_ATOMISP_GC0310=y
CONFIG_VIDEO_ATOMISP_OV2680=y
CONFIG_VIDEO_ATOMISP_OV5693=y
CONFIG_VIDEO_ATOMISP_LM3554=y
CONFIG_VIDEO_IPU3_IMGU=y
CONFIG_VIDEO_MAX96712=y
CONFIG_STAGING_MEDIA_DEPRECATED=y
#
# Atmel media platform drivers
#
CONFIG_VIDEO_CPIA2=y
CONFIG_VIDEO_MEYE=y
CONFIG_VIDEO_SAA7146=y
CONFIG_VIDEO_SAA7146_VV=y
CONFIG_DVB_AV7110_IR=y
CONFIG_DVB_AV7110=y
CONFIG_DVB_AV7110_OSD=y
CONFIG_DVB_BUDGET_PATCH=y
CONFIG_DVB_SP8870=y
CONFIG_VIDEO_HEXIUM_GEMINI=y
CONFIG_VIDEO_HEXIUM_ORION=y
CONFIG_VIDEO_MXB=y
CONFIG_DVB_BUDGET_CORE=y
CONFIG_DVB_BUDGET=y
CONFIG_DVB_BUDGET_CI=y
CONFIG_DVB_BUDGET_AV=y
CONFIG_VIDEO_STKWEBCAM=y
CONFIG_VIDEO_TM6000=y
CONFIG_VIDEO_TM6000_ALSA=y
CONFIG_VIDEO_TM6000_DVB=y
CONFIG_USB_ZR364XX=y
CONFIG_STAGING_BOARD=y
CONFIG_LTE_GDM724X=m
CONFIG_FB_TFT=y
CONFIG_FB_TFT_AGM1264K_FL=y
CONFIG_FB_TFT_BD663474=y
CONFIG_FB_TFT_HX8340BN=y
CONFIG_FB_TFT_HX8347D=y
CONFIG_FB_TFT_HX8353D=y
CONFIG_FB_TFT_HX8357D=y
CONFIG_FB_TFT_ILI9163=y
CONFIG_FB_TFT_ILI9320=y
CONFIG_FB_TFT_ILI9325=y
CONFIG_FB_TFT_ILI9340=y
CONFIG_FB_TFT_ILI9341=y
CONFIG_FB_TFT_ILI9481=y
CONFIG_FB_TFT_ILI9486=y
CONFIG_FB_TFT_PCD8544=y
CONFIG_FB_TFT_RA8875=y
CONFIG_FB_TFT_S6D02A1=y
CONFIG_FB_TFT_S6D1121=y
CONFIG_FB_TFT_SEPS525=y
CONFIG_FB_TFT_SH1106=y
CONFIG_FB_TFT_SSD1289=y
CONFIG_FB_TFT_SSD1305=y
CONFIG_FB_TFT_SSD1306=y
CONFIG_FB_TFT_SSD1331=y
CONFIG_FB_TFT_SSD1351=y
CONFIG_FB_TFT_ST7735R=y
CONFIG_FB_TFT_ST7789V=y
CONFIG_FB_TFT_TINYLCD=y
CONFIG_FB_TFT_TLS8204=y
CONFIG_FB_TFT_UC1611=y
CONFIG_FB_TFT_UC1701=y
CONFIG_FB_TFT_UPD161704=y
CONFIG_MOST_COMPONENTS=y
CONFIG_MOST_NET=y
CONFIG_MOST_VIDEO=y
CONFIG_MOST_DIM2=y
CONFIG_MOST_I2C=y
CONFIG_KS7010=y
CONFIG_GREYBUS_AUDIO=y
CONFIG_GREYBUS_AUDIO_APB_CODEC=y
CONFIG_GREYBUS_BOOTROM=y
CONFIG_GREYBUS_FIRMWARE=y
CONFIG_GREYBUS_HID=y
CONFIG_GREYBUS_LIGHT=y
CONFIG_GREYBUS_LOG=y
CONFIG_GREYBUS_LOOPBACK=y
CONFIG_GREYBUS_POWER=y
CONFIG_GREYBUS_RAW=y
CONFIG_GREYBUS_VIBRATOR=y
CONFIG_GREYBUS_BRIDGED_PHY=y
CONFIG_GREYBUS_GPIO=y
CONFIG_GREYBUS_I2C=y
CONFIG_GREYBUS_PWM=y
CONFIG_GREYBUS_SDIO=y
CONFIG_GREYBUS_SPI=y
CONFIG_GREYBUS_UART=y
CONFIG_GREYBUS_USB=y
CONFIG_PI433=y
CONFIG_XIL_AXIS_FIFO=y
CONFIG_FIELDBUS_DEV=y
CONFIG_HMS_ANYBUSS_BUS=y
CONFIG_ARCX_ANYBUS_CONTROLLER=y
CONFIG_HMS_PROFINET=y
CONFIG_QLGE=y
CONFIG_VME_BUS=y
#
# VME Bridge Drivers
#
CONFIG_VME_TSI148=y
CONFIG_VME_FAKE=y
#
# VME Device Drivers
#
CONFIG_VME_USER=y
CONFIG_GOLDFISH_PIPE=y
CONFIG_CHROME_PLATFORMS=y
CONFIG_CHROMEOS_ACPI=y
CONFIG_CHROMEOS_LAPTOP=y
CONFIG_CHROMEOS_PSTORE=y
CONFIG_CHROMEOS_TBMC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_RPMSG=y
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=y
CONFIG_CROS_EC_CHARDEV=y
CONFIG_CROS_EC_LIGHTBAR=y
CONFIG_CROS_EC_VBC=y
CONFIG_CROS_EC_DEBUGFS=y
CONFIG_CROS_EC_SENSORHUB=y
CONFIG_CROS_EC_SYSFS=y
CONFIG_CROS_EC_TYPEC=y
CONFIG_CROS_HPS_I2C=y
CONFIG_CROS_USBPD_LOGGER=y
CONFIG_CROS_USBPD_NOTIFY=y
CONFIG_CHROMEOS_PRIVACY_SCREEN=y
CONFIG_CROS_TYPEC_SWITCH=y
CONFIG_WILCO_EC=y
CONFIG_WILCO_EC_DEBUGFS=y
CONFIG_WILCO_EC_EVENTS=y
CONFIG_WILCO_EC_TELEMETRY=y
CONFIG_CROS_KUNIT=y
CONFIG_MELLANOX_PLATFORM=y
CONFIG_MLXREG_HOTPLUG=y
CONFIG_MLXREG_IO=y
CONFIG_MLXREG_LC=y
CONFIG_NVSW_SN2201=y
CONFIG_OLPC_EC=y
CONFIG_SURFACE_PLATFORMS=y
CONFIG_SURFACE3_WMI=y
CONFIG_SURFACE_3_POWER_OPREGION=y
CONFIG_SURFACE_ACPI_NOTIFY=y
CONFIG_SURFACE_AGGREGATOR_CDEV=y
CONFIG_SURFACE_AGGREGATOR_HUB=y
CONFIG_SURFACE_AGGREGATOR_REGISTRY=y
CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=y
CONFIG_SURFACE_DTX=y
CONFIG_SURFACE_GPE=y
CONFIG_SURFACE_HOTPLUG=y
CONFIG_SURFACE_PLATFORM_PROFILE=y
CONFIG_SURFACE_PRO3_BUTTON=y
CONFIG_SURFACE_AGGREGATOR=y
CONFIG_SURFACE_AGGREGATOR_BUS=y
CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION=y
CONFIG_X86_PLATFORM_DEVICES=y
CONFIG_ACPI_WMI=y
CONFIG_WMI_BMOF=y
CONFIG_HUAWEI_WMI=y
CONFIG_MXM_WMI=y
CONFIG_PEAQ_WMI=y
CONFIG_NVIDIA_WMI_EC_BACKLIGHT=y
CONFIG_XIAOMI_WMI=y
CONFIG_GIGABYTE_WMI=y
CONFIG_YOGABOOK_WMI=y
CONFIG_ACERHDF=y
CONFIG_ACER_WIRELESS=y
CONFIG_ACER_WMI=y
CONFIG_AMD_PMF=y
CONFIG_AMD_PMC=y
CONFIG_ADV_SWBUTTON=y
CONFIG_APPLE_GMUX=y
CONFIG_ASUS_LAPTOP=y
CONFIG_ASUS_WIRELESS=y
CONFIG_ASUS_WMI=y
CONFIG_ASUS_NB_WMI=y
CONFIG_ASUS_TF103C_DOCK=y
CONFIG_MERAKI_MX100=y
CONFIG_EEEPC_LAPTOP=y
CONFIG_EEEPC_WMI=y
CONFIG_X86_PLATFORM_DRIVERS_DELL=y
CONFIG_ALIENWARE_WMI=y
CONFIG_DCDBAS=y
CONFIG_DELL_LAPTOP=y
CONFIG_DELL_RBU=y
CONFIG_DELL_RBTN=y
CONFIG_DELL_SMBIOS=y
CONFIG_DELL_SMBIOS_WMI=y
CONFIG_DELL_SMBIOS_SMM=y
CONFIG_DELL_SMO8800=y
CONFIG_DELL_WMI=y
CONFIG_DELL_WMI_PRIVACY=y
CONFIG_DELL_WMI_AIO=y
CONFIG_DELL_WMI_DESCRIPTOR=y
CONFIG_DELL_WMI_DDV=y
CONFIG_DELL_WMI_LED=y
CONFIG_DELL_WMI_SYSMAN=y
CONFIG_AMILO_RFKILL=y
CONFIG_FUJITSU_LAPTOP=y
CONFIG_FUJITSU_TABLET=y
CONFIG_GPD_POCKET_FAN=y
CONFIG_X86_PLATFORM_DRIVERS_HP=y
CONFIG_HP_ACCEL=y
CONFIG_HP_WMI=y
CONFIG_TC1100_WMI=y
CONFIG_WIRELESS_HOTKEY=y
CONFIG_IBM_RTL=y
CONFIG_IDEAPAD_LAPTOP=y
CONFIG_SENSORS_HDAPS=y
CONFIG_THINKPAD_ACPI=y
CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y
CONFIG_THINKPAD_ACPI_DEBUG=y
CONFIG_THINKPAD_ACPI_UNSAFE_LEDS=y
CONFIG_THINKPAD_ACPI_VIDEO=y
CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
CONFIG_THINKPAD_LMI=y
CONFIG_INTEL_ATOMISP2_PDX86=y
CONFIG_INTEL_ATOMISP2_LED=y
CONFIG_INTEL_SAR_INT1092=y
CONFIG_INTEL_SKL_INT3472=y
CONFIG_INTEL_PMC_CORE=y
CONFIG_INTEL_PMT_CLASS=y
CONFIG_INTEL_PMT_TELEMETRY=y
CONFIG_INTEL_PMT_CRASHLOG=y
CONFIG_INTEL_WMI=y
CONFIG_INTEL_WMI_SBL_FW_UPDATE=y
CONFIG_INTEL_WMI_THUNDERBOLT=y
CONFIG_INTEL_HID_EVENT=y
CONFIG_INTEL_VBTN=y
CONFIG_INTEL_INT0002_VGPIO=y
CONFIG_INTEL_OAKTRAIL=y
CONFIG_INTEL_BXTWC_PMIC_TMU=y
CONFIG_INTEL_CHTDC_TI_PWRBTN=y
CONFIG_INTEL_CHTWC_INT33FE=y
CONFIG_INTEL_MRFLD_PWRBTN=y
CONFIG_INTEL_PUNIT_IPC=y
CONFIG_INTEL_RST=y
CONFIG_INTEL_SMARTCONNECT=y
CONFIG_INTEL_VSEC=y
CONFIG_MSI_LAPTOP=y
CONFIG_MSI_WMI=y
CONFIG_XO15_EBOOK=y
CONFIG_XO1_RFKILL=y
CONFIG_PCENGINES_APU2=y
CONFIG_BARCO_P50_GPIO=y
CONFIG_SAMSUNG_LAPTOP=y
CONFIG_SAMSUNG_Q10=y
CONFIG_ACPI_TOSHIBA=y
CONFIG_TOSHIBA_BT_RFKILL=y
CONFIG_TOSHIBA_HAPS=y
CONFIG_TOSHIBA_WMI=y
CONFIG_ACPI_CMPC=y
CONFIG_COMPAL_LAPTOP=y
CONFIG_LG_LAPTOP=y
CONFIG_PANASONIC_LAPTOP=y
CONFIG_SONY_LAPTOP=y
CONFIG_SONYPI_COMPAT=y
CONFIG_SYSTEM76_ACPI=y
CONFIG_TOPSTAR_LAPTOP=y
CONFIG_SERIAL_MULTI_INSTANTIATE=y
CONFIG_MLX_PLATFORM=y
CONFIG_TOUCHSCREEN_DMI=y
CONFIG_X86_ANDROID_TABLETS=y
CONFIG_FW_ATTR_CLASS=y
CONFIG_INTEL_IMR=y
CONFIG_INTEL_IPS=y
CONFIG_INTEL_SCU_IPC=y
CONFIG_INTEL_SCU=y
CONFIG_INTEL_SCU_PCI=y
CONFIG_INTEL_SCU_PLATFORM=y
CONFIG_INTEL_SCU_WDT=y
CONFIG_INTEL_SCU_IPC_UTIL=y
CONFIG_SIEMENS_SIMATIC_IPC=y
CONFIG_WINMATE_FM07_KEYS=y
CONFIG_P2SB=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_WM831X=y
CONFIG_LMK04832=y
CONFIG_COMMON_CLK_MAX77686=y
CONFIG_COMMON_CLK_MAX9485=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SI5341=y
CONFIG_COMMON_CLK_SI5351=y
CONFIG_COMMON_CLK_SI514=y
CONFIG_COMMON_CLK_SI544=y
CONFIG_COMMON_CLK_SI570=y
CONFIG_COMMON_CLK_CDCE706=y
CONFIG_COMMON_CLK_TPS68470=y
CONFIG_COMMON_CLK_CDCE925=y
CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_CLK_TWL6040=y
CONFIG_COMMON_CLK_AXI_CLKGEN=y
CONFIG_COMMON_CLK_LOCHNAGAR=y
CONFIG_COMMON_CLK_PALMAS=y
CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_RS9_PCIE=y
CONFIG_COMMON_CLK_VC5=y
CONFIG_COMMON_CLK_VC7=y
CONFIG_COMMON_CLK_BD718XX=y
CONFIG_COMMON_CLK_FIXED_MMIO=y
CONFIG_CLK_LGM_CGU=y
CONFIG_XILINX_VCU=y
CONFIG_COMMON_CLK_XLNX_CLKWZRD=y
CONFIG_CLK_KUNIT_TEST=y
CONFIG_CLK_GATE_KUNIT_TEST=y
CONFIG_HWSPINLOCK=y
#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_I8253=y
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
CONFIG_DW_APB_TIMER=y
CONFIG_MICROCHIP_PIT64B=y
# end of Clock Source drivers
CONFIG_MAILBOX=y
CONFIG_PLATFORM_MHU=y
CONFIG_PCC=y
CONFIG_ALTERA_MBOX=y
CONFIG_MAILBOX_TEST=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOASID=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
# end of Generic IOMMU Pagetable Support
CONFIG_IOMMU_DEBUGFS=y
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
CONFIG_IOMMU_DEFAULT_DMA_LAZY=y
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_DMAR_TABLE=y
CONFIG_DMAR_PERF=y
CONFIG_DMAR_DEBUG=y
CONFIG_INTEL_IOMMU=y
CONFIG_INTEL_IOMMU_DEBUGFS=y
CONFIG_INTEL_IOMMU_DEFAULT_ON=y
CONFIG_INTEL_IOMMU_FLOPPY_WA=y
CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON=y
CONFIG_IOMMUFD=y
CONFIG_IOMMUFD_TEST=y
CONFIG_HYPERV_IOMMU=y
CONFIG_VIRTIO_IOMMU=y
#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# end of Remoteproc drivers
#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_NS=y
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_VIRTIO=y
# end of Rpmsg drivers
CONFIG_SOUNDWIRE=y
#
# SoundWire Devices
#
CONFIG_SOUNDWIRE_CADENCE=y
CONFIG_SOUNDWIRE_INTEL=y
CONFIG_SOUNDWIRE_QCOM=y
CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=y
#
# SOC (System On Chip) specific Drivers
#
#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers
#
# Broadcom SoC drivers
#
# end of Broadcom SoC drivers
#
# NXP/Freescale QorIQ SoC drivers
#
# end of NXP/Freescale QorIQ SoC drivers
#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers
#
# i.MX SoC drivers
#
# end of i.MX SoC drivers
#
# Enable LiteX SoC Builder specific drivers
#
CONFIG_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=y
# end of Enable LiteX SoC Builder specific drivers
#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=y
# end of Qualcomm SoC drivers
CONFIG_SOC_TI=y
#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers
CONFIG_PM_DEVFREQ=y
#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
#
# DEVFREQ Drivers
#
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=y
CONFIG_EXTCON_AXP288=y
CONFIG_EXTCON_FSA9480=y
CONFIG_EXTCON_GPIO=y
CONFIG_EXTCON_INTEL_INT3496=y
CONFIG_EXTCON_INTEL_CHT_WC=y
CONFIG_EXTCON_INTEL_MRFLD=y
CONFIG_EXTCON_MAX14577=y
CONFIG_EXTCON_MAX3355=y
CONFIG_EXTCON_MAX77693=y
CONFIG_EXTCON_MAX77843=y
CONFIG_EXTCON_MAX8997=y
CONFIG_EXTCON_PALMAS=y
CONFIG_EXTCON_PTN5150=y
CONFIG_EXTCON_RT8973A=y
CONFIG_EXTCON_SM5502=y
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_EXTCON_USBC_TUSB320=y
CONFIG_MEMORY=y
CONFIG_FPGA_DFL_EMIF=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=y
CONFIG_IIO_BUFFER_DMAENGINE=y
CONFIG_IIO_BUFFER_HW_CONSUMER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=y
CONFIG_IIO_SW_TRIGGER=y
CONFIG_IIO_TRIGGERED_EVENT=y
#
# Accelerometers
#
CONFIG_ADIS16201=y
CONFIG_ADIS16209=y
CONFIG_ADXL313=y
CONFIG_ADXL313_I2C=y
CONFIG_ADXL313_SPI=y
CONFIG_ADXL355=y
CONFIG_ADXL355_I2C=y
CONFIG_ADXL355_SPI=y
CONFIG_ADXL367=y
CONFIG_ADXL367_SPI=y
CONFIG_ADXL367_I2C=y
CONFIG_ADXL372=y
CONFIG_ADXL372_SPI=y
CONFIG_ADXL372_I2C=y
CONFIG_BMA220=y
CONFIG_BMA400=y
CONFIG_BMA400_I2C=y
CONFIG_BMA400_SPI=y
CONFIG_BMC150_ACCEL=y
CONFIG_BMC150_ACCEL_I2C=y
CONFIG_BMC150_ACCEL_SPI=y
CONFIG_BMI088_ACCEL=y
CONFIG_BMI088_ACCEL_SPI=y
CONFIG_DA280=y
CONFIG_DA311=y
CONFIG_DMARD06=y
CONFIG_DMARD09=y
CONFIG_DMARD10=y
CONFIG_FXLS8962AF=y
CONFIG_FXLS8962AF_I2C=y
CONFIG_FXLS8962AF_SPI=y
CONFIG_HID_SENSOR_ACCEL_3D=y
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=y
CONFIG_IIO_KX022A=y
CONFIG_IIO_KX022A_SPI=y
CONFIG_IIO_KX022A_I2C=y
CONFIG_KXSD9=y
CONFIG_KXSD9_SPI=y
CONFIG_KXSD9_I2C=y
CONFIG_KXCJK1013=y
CONFIG_MC3230=y
CONFIG_MMA7455=y
CONFIG_MMA7455_I2C=y
CONFIG_MMA7455_SPI=y
CONFIG_MMA7660=y
CONFIG_MMA8452=y
CONFIG_MMA9551_CORE=y
CONFIG_MMA9551=y
CONFIG_MMA9553=y
CONFIG_MSA311=y
CONFIG_MXC4005=y
CONFIG_MXC6255=y
CONFIG_SCA3000=y
CONFIG_SCA3300=y
CONFIG_STK8312=y
CONFIG_STK8BA50=y
# end of Accelerometers
#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=y
CONFIG_AD4130=y
CONFIG_AD7091R5=y
CONFIG_AD7124=y
CONFIG_AD7192=y
CONFIG_AD7266=y
CONFIG_AD7280=y
CONFIG_AD7291=y
CONFIG_AD7292=y
CONFIG_AD7298=y
CONFIG_AD7476=y
CONFIG_AD7606=y
CONFIG_AD7606_IFACE_PARALLEL=y
CONFIG_AD7606_IFACE_SPI=y
CONFIG_AD7766=y
CONFIG_AD7768_1=y
CONFIG_AD7780=y
CONFIG_AD7791=y
CONFIG_AD7793=y
CONFIG_AD7887=y
CONFIG_AD7923=y
CONFIG_AD7949=y
CONFIG_AD799X=y
CONFIG_AD9467=y
CONFIG_ADI_AXI_ADC=y
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
CONFIG_CC10001_ADC=y
CONFIG_CPCAP_ADC=y
CONFIG_DA9150_GPADC=y
CONFIG_DLN2_ADC=y
CONFIG_ENVELOPE_DETECTOR=y
CONFIG_HI8435=y
CONFIG_HX711=y
CONFIG_INTEL_MRFLD_ADC=y
CONFIG_LP8788_ADC=y
CONFIG_LTC2471=y
CONFIG_LTC2485=y
CONFIG_LTC2496=y
CONFIG_LTC2497=y
CONFIG_MAX1027=y
CONFIG_MAX11100=y
CONFIG_MAX1118=y
CONFIG_MAX11205=y
CONFIG_MAX11410=y
CONFIG_MAX1241=y
CONFIG_MAX1363=y
CONFIG_MAX9611=y
CONFIG_MCP320X=y
CONFIG_MCP3422=y
CONFIG_MCP3911=y
CONFIG_MEDIATEK_MT6360_ADC=y
CONFIG_MEDIATEK_MT6370_ADC=y
CONFIG_MEN_Z188_ADC=y
CONFIG_MP2629_ADC=y
CONFIG_NAU7802=y
CONFIG_PALMAS_GPADC=y
CONFIG_QCOM_VADC_COMMON=y
CONFIG_QCOM_SPMI_IADC=y
CONFIG_QCOM_SPMI_VADC=y
CONFIG_QCOM_SPMI_ADC5=y
CONFIG_RN5T618_ADC=y
CONFIG_RICHTEK_RTQ6056=y
CONFIG_SD_ADC_MODULATOR=y
CONFIG_STMPE_ADC=y
CONFIG_TI_ADC081C=y
CONFIG_TI_ADC0832=y
CONFIG_TI_ADC084S021=y
CONFIG_TI_ADC12138=y
CONFIG_TI_ADC108S102=y
CONFIG_TI_ADC128S052=y
CONFIG_TI_ADC161S626=y
CONFIG_TI_ADS1015=y
CONFIG_TI_ADS7950=y
CONFIG_TI_ADS8344=y
CONFIG_TI_ADS8688=y
CONFIG_TI_ADS124S08=y
CONFIG_TI_ADS131E08=y
CONFIG_TI_AM335X_ADC=y
CONFIG_TI_TLC4541=y
CONFIG_TI_TSC2046=y
CONFIG_TWL4030_MADC=y
CONFIG_TWL6030_GPADC=y
CONFIG_VF610_ADC=y
CONFIG_VIPERBOARD_ADC=y
CONFIG_XILINX_XADC=y
# end of Analog to digital converters
#
# Analog to digital and digital to analog converters
#
CONFIG_AD74115=y
CONFIG_AD74413R=y
CONFIG_STX104=y
# end of Analog to digital and digital to analog converters
#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=y
# end of Analog Front Ends
#
# Amplifiers
#
CONFIG_AD8366=y
CONFIG_ADA4250=y
CONFIG_HMC425=y
# end of Amplifiers
#
# Capacitance to digital converters
#
CONFIG_AD7150=y
CONFIG_AD7746=y
# end of Capacitance to digital converters
#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=y
CONFIG_ATLAS_EZO_SENSOR=y
CONFIG_BME680=y
CONFIG_BME680_I2C=y
CONFIG_BME680_SPI=y
CONFIG_CCS811=y
CONFIG_IAQCORE=y
CONFIG_PMS7003=y
CONFIG_SCD30_CORE=y
CONFIG_SCD30_I2C=y
CONFIG_SCD30_SERIAL=y
CONFIG_SCD4X=y
CONFIG_SENSIRION_SGP30=y
CONFIG_SENSIRION_SGP40=y
CONFIG_SPS30=y
CONFIG_SPS30_I2C=y
CONFIG_SPS30_SERIAL=y
CONFIG_SENSEAIR_SUNRISE_CO2=y
CONFIG_VZ89X=y
# end of Chemical Sensors
CONFIG_IIO_CROS_EC_SENSORS_CORE=y
CONFIG_IIO_CROS_EC_SENSORS=y
CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=y
#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=y
CONFIG_HID_SENSOR_IIO_TRIGGER=y
# end of Hid Sensor IIO Common
CONFIG_IIO_MS_SENSORS_I2C=y
#
# IIO SCMI Sensors
#
# end of IIO SCMI Sensors
#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=y
CONFIG_IIO_SSP_SENSORHUB=y
# end of SSP Sensor Common
CONFIG_IIO_ST_SENSORS_I2C=y
CONFIG_IIO_ST_SENSORS_SPI=y
CONFIG_IIO_ST_SENSORS_CORE=y
#
# Digital to analog converters
#
CONFIG_AD3552R=y
CONFIG_AD5064=y
CONFIG_AD5360=y
CONFIG_AD5380=y
CONFIG_AD5421=y
CONFIG_AD5446=y
CONFIG_AD5449=y
CONFIG_AD5592R_BASE=y
CONFIG_AD5592R=y
CONFIG_AD5593R=y
CONFIG_AD5504=y
CONFIG_AD5624R_SPI=y
CONFIG_LTC2688=y
CONFIG_AD5686=y
CONFIG_AD5686_SPI=y
CONFIG_AD5696_I2C=y
CONFIG_AD5755=y
CONFIG_AD5758=y
CONFIG_AD5761=y
CONFIG_AD5764=y
CONFIG_AD5766=y
CONFIG_AD5770R=y
CONFIG_AD5791=y
CONFIG_AD7293=y
CONFIG_AD7303=y
CONFIG_AD8801=y
CONFIG_CIO_DAC=y
CONFIG_DPOT_DAC=y
CONFIG_DS4424=y
CONFIG_LTC1660=y
CONFIG_LTC2632=y
CONFIG_M62332=y
CONFIG_MAX517=y
CONFIG_MAX5821=y
CONFIG_MCP4725=y
CONFIG_MCP4922=y
CONFIG_TI_DAC082S085=y
CONFIG_TI_DAC5571=y
CONFIG_TI_DAC7311=y
CONFIG_TI_DAC7612=y
CONFIG_VF610_DAC=y
# end of Digital to analog converters
#
# IIO dummy driver
#
CONFIG_IIO_DUMMY_EVGEN=y
CONFIG_IIO_SIMPLE_DUMMY=y
CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
# end of IIO dummy driver
#
# Filters
#
# end of Filters
#
# Frequency Synthesizers DDS/PLL
#
#
# Clock Generator/Distribution
#
CONFIG_AD9523=y
# end of Clock Generator/Distribution
#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=y
CONFIG_ADF4371=y
CONFIG_ADF4377=y
CONFIG_ADMV1013=y
CONFIG_ADMV4420=y
CONFIG_ADRF6780=y
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL
#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=y
CONFIG_ADIS16130=y
CONFIG_ADIS16136=y
CONFIG_ADIS16260=y
CONFIG_ADXRS290=y
CONFIG_ADXRS450=y
CONFIG_BMG160=y
CONFIG_BMG160_I2C=y
CONFIG_BMG160_SPI=y
CONFIG_FXAS21002C=y
CONFIG_FXAS21002C_I2C=y
CONFIG_FXAS21002C_SPI=y
CONFIG_HID_SENSOR_GYRO_3D=y
CONFIG_MPU3050=y
CONFIG_MPU3050_I2C=y
CONFIG_IIO_ST_GYRO_3AXIS=y
CONFIG_IIO_ST_GYRO_I2C_3AXIS=y
CONFIG_IIO_ST_GYRO_SPI_3AXIS=y
CONFIG_ITG3200=y
# end of Digital gyroscope sensors
#
# Health Sensors
#
#
# Heart Rate Monitors
#
CONFIG_AFE4403=y
CONFIG_AFE4404=y
CONFIG_MAX30100=y
CONFIG_MAX30102=y
# end of Heart Rate Monitors
# end of Health Sensors
#
# Humidity sensors
#
CONFIG_AM2315=y
CONFIG_DHT11=y
CONFIG_HDC100X=y
CONFIG_HDC2010=y
CONFIG_HID_SENSOR_HUMIDITY=y
CONFIG_HTS221=y
CONFIG_HTS221_I2C=y
CONFIG_HTS221_SPI=y
CONFIG_HTU21=y
CONFIG_SI7005=y
CONFIG_SI7020=y
# end of Humidity sensors
#
# Inertial measurement units
#
CONFIG_ADIS16400=y
CONFIG_ADIS16460=y
CONFIG_ADIS16475=y
CONFIG_ADIS16480=y
CONFIG_BMI160=y
CONFIG_BMI160_I2C=y
CONFIG_BMI160_SPI=y
CONFIG_BOSCH_BNO055=y
CONFIG_BOSCH_BNO055_SERIAL=y
CONFIG_BOSCH_BNO055_I2C=y
CONFIG_FXOS8700=y
CONFIG_FXOS8700_I2C=y
CONFIG_FXOS8700_SPI=y
CONFIG_KMX61=y
CONFIG_INV_ICM42600=y
CONFIG_INV_ICM42600_I2C=y
CONFIG_INV_ICM42600_SPI=y
CONFIG_INV_MPU6050_IIO=y
CONFIG_INV_MPU6050_I2C=y
CONFIG_INV_MPU6050_SPI=y
CONFIG_IIO_ST_LSM6DSX=y
CONFIG_IIO_ST_LSM6DSX_I2C=y
CONFIG_IIO_ST_LSM6DSX_SPI=y
CONFIG_IIO_ST_LSM6DSX_I3C=y
# end of Inertial measurement units
CONFIG_IIO_ADIS_LIB=y
CONFIG_IIO_ADIS_LIB_BUFFER=y
#
# Light sensors
#
CONFIG_ACPI_ALS=y
CONFIG_ADJD_S311=y
CONFIG_ADUX1020=y
CONFIG_AL3010=y
CONFIG_AL3320A=y
CONFIG_APDS9300=y
CONFIG_APDS9960=y
CONFIG_AS73211=y
CONFIG_BH1750=y
CONFIG_BH1780=y
CONFIG_CM32181=y
CONFIG_CM3232=y
CONFIG_CM3323=y
CONFIG_CM3605=y
CONFIG_CM36651=y
CONFIG_IIO_CROS_EC_LIGHT_PROX=y
CONFIG_GP2AP002=y
CONFIG_GP2AP020A00F=y
CONFIG_IQS621_ALS=y
CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_ISL29028=y
CONFIG_ISL29125=y
CONFIG_HID_SENSOR_ALS=y
CONFIG_HID_SENSOR_PROX=y
CONFIG_JSA1212=y
CONFIG_RPR0521=y
CONFIG_SENSORS_LM3533=y
CONFIG_LTR501=y
CONFIG_LTRF216A=y
CONFIG_LV0104CS=y
CONFIG_MAX44000=y
CONFIG_MAX44009=y
CONFIG_NOA1305=y
CONFIG_OPT3001=y
CONFIG_PA12203001=y
CONFIG_SI1133=y
CONFIG_SI1145=y
CONFIG_STK3310=y
CONFIG_ST_UVIS25=y
CONFIG_ST_UVIS25_I2C=y
CONFIG_ST_UVIS25_SPI=y
CONFIG_TCS3414=y
CONFIG_TCS3472=y
CONFIG_SENSORS_TSL2563=y
CONFIG_TSL2583=y
CONFIG_TSL2591=y
CONFIG_TSL2772=y
CONFIG_TSL4531=y
CONFIG_US5182D=y
CONFIG_VCNL4000=y
CONFIG_VCNL4035=y
CONFIG_VEML6030=y
CONFIG_VEML6070=y
CONFIG_VL6180=y
CONFIG_ZOPT2201=y
# end of Light sensors
#
# Magnetometer sensors
#
CONFIG_AK8974=y
CONFIG_AK8975=y
CONFIG_AK09911=y
CONFIG_BMC150_MAGN=y
CONFIG_BMC150_MAGN_I2C=y
CONFIG_BMC150_MAGN_SPI=y
CONFIG_MAG3110=y
CONFIG_HID_SENSOR_MAGNETOMETER_3D=y
CONFIG_MMC35240=y
CONFIG_IIO_ST_MAGN_3AXIS=y
CONFIG_IIO_ST_MAGN_I2C_3AXIS=y
CONFIG_IIO_ST_MAGN_SPI_3AXIS=y
CONFIG_SENSORS_HMC5843=y
CONFIG_SENSORS_HMC5843_I2C=y
CONFIG_SENSORS_HMC5843_SPI=y
CONFIG_SENSORS_RM3100=y
CONFIG_SENSORS_RM3100_I2C=y
CONFIG_SENSORS_RM3100_SPI=y
CONFIG_YAMAHA_YAS530=y
# end of Magnetometer sensors
#
# Multiplexers
#
CONFIG_IIO_MUX=y
# end of Multiplexers
#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=y
CONFIG_HID_SENSOR_DEVICE_ROTATION=y
# end of Inclinometer sensors
CONFIG_IIO_RESCALE_KUNIT_TEST=y
CONFIG_IIO_FORMAT_KUNIT_TEST=y
#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=y
CONFIG_IIO_INTERRUPT_TRIGGER=y
CONFIG_IIO_TIGHTLOOP_TRIGGER=y
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone
#
# Linear and angular position sensors
#
CONFIG_IQS624_POS=y
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=y
# end of Linear and angular position sensors
#
# Digital potentiometers
#
CONFIG_AD5110=y
CONFIG_AD5272=y
CONFIG_DS1803=y
CONFIG_MAX5432=y
CONFIG_MAX5481=y
CONFIG_MAX5487=y
CONFIG_MCP4018=y
CONFIG_MCP4131=y
CONFIG_MCP4531=y
CONFIG_MCP41010=y
CONFIG_TPL0102=y
# end of Digital potentiometers
#
# Digital potentiostats
#
CONFIG_LMP91000=y
# end of Digital potentiostats
#
# Pressure sensors
#
CONFIG_ABP060MG=y
CONFIG_BMP280=y
CONFIG_BMP280_I2C=y
CONFIG_BMP280_SPI=y
CONFIG_IIO_CROS_EC_BARO=y
CONFIG_DLHL60D=y
CONFIG_DPS310=y
CONFIG_HID_SENSOR_PRESS=y
CONFIG_HP03=y
CONFIG_ICP10100=y
CONFIG_MPL115=y
CONFIG_MPL115_I2C=y
CONFIG_MPL115_SPI=y
CONFIG_MPL3115=y
CONFIG_MS5611=y
CONFIG_MS5611_I2C=y
CONFIG_MS5611_SPI=y
CONFIG_MS5637=y
CONFIG_IIO_ST_PRESS=y
CONFIG_IIO_ST_PRESS_I2C=y
CONFIG_IIO_ST_PRESS_SPI=y
CONFIG_T5403=y
CONFIG_HP206C=y
CONFIG_ZPA2326=y
CONFIG_ZPA2326_I2C=y
CONFIG_ZPA2326_SPI=y
# end of Pressure sensors
#
# Lightning sensors
#
CONFIG_AS3935=y
# end of Lightning sensors
#
# Proximity and distance sensors
#
CONFIG_CROS_EC_MKBP_PROXIMITY=y
CONFIG_ISL29501=y
CONFIG_LIDAR_LITE_V2=y
CONFIG_MB1232=y
CONFIG_PING=y
CONFIG_RFD77402=y
CONFIG_SRF04=y
CONFIG_SX_COMMON=y
CONFIG_SX9310=y
CONFIG_SX9324=y
CONFIG_SX9360=y
CONFIG_SX9500=y
CONFIG_SRF08=y
CONFIG_VCNL3020=y
CONFIG_VL53L0X_I2C=y
# end of Proximity and distance sensors
#
# Resolver to digital converters
#
CONFIG_AD2S90=y
CONFIG_AD2S1200=y
# end of Resolver to digital converters
#
# Temperature sensors
#
CONFIG_IQS620AT_TEMP=y
CONFIG_LTC2983=y
CONFIG_MAXIM_THERMOCOUPLE=y
CONFIG_HID_SENSOR_TEMP=y
CONFIG_MLX90614=y
CONFIG_MLX90632=y
CONFIG_TMP006=y
CONFIG_TMP007=y
CONFIG_TMP117=y
CONFIG_TSYS01=y
CONFIG_TSYS02D=y
CONFIG_MAX30208=y
CONFIG_MAX31856=y
CONFIG_MAX31865=y
# end of Temperature sensors
CONFIG_NTB=y
CONFIG_NTB_MSI=y
CONFIG_NTB_IDT=y
CONFIG_NTB_EPF=m
CONFIG_NTB_SWITCHTEC=y
CONFIG_NTB_PINGPONG=y
CONFIG_NTB_TOOL=y
CONFIG_NTB_PERF=y
CONFIG_NTB_MSI_TEST=y
CONFIG_NTB_TRANSPORT=y
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_DEBUG=y
CONFIG_PWM_ATMEL_HLCDC_PWM=y
CONFIG_PWM_ATMEL_TCB=y
CONFIG_PWM_CLK=y
CONFIG_PWM_CRC=y
CONFIG_PWM_CROS_EC=y
CONFIG_PWM_DWC=y
CONFIG_PWM_FSL_FTM=y
CONFIG_PWM_INTEL_LGM=y
CONFIG_PWM_IQS620A=y
CONFIG_PWM_LP3943=y
CONFIG_PWM_LPSS=y
CONFIG_PWM_LPSS_PCI=y
CONFIG_PWM_LPSS_PLATFORM=y
CONFIG_PWM_NTXEC=y
CONFIG_PWM_PCA9685=y
CONFIG_PWM_STMPE=y
CONFIG_PWM_TWL=y
CONFIG_PWM_TWL_LED=y
CONFIG_PWM_XILINX=y
#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_AL_FIC=y
CONFIG_MADERA_IRQ=y
CONFIG_XILINX_INTC=y
# end of IRQ chip support
CONFIG_IPACK_BUS=y
CONFIG_BOARD_TPCI200=y
CONFIG_SERIAL_IPOCTAL=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_INTEL_GW=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_TI_SYSCON=y
CONFIG_RESET_TI_TPS380X=y
#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
CONFIG_USB_LGM_PHY=y
CONFIG_PHY_CAN_TRANSCEIVER=y
#
# PHY drivers for Broadcom platforms
#
CONFIG_BCM_KONA_USB2_PHY=y
# end of PHY drivers for Broadcom platforms
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_CADENCE_DPHY=y
CONFIG_PHY_CADENCE_DPHY_RX=y
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_CADENCE_SALVO=y
CONFIG_PHY_PXA_28NM_HSIC=y
CONFIG_PHY_PXA_28NM_USB2=y
CONFIG_PHY_LAN966X_SERDES=y
CONFIG_PHY_CPCAP_USB=y
CONFIG_PHY_MAPPHONE_MDM6600=y
CONFIG_PHY_OCELOT_SERDES=y
CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_QCOM_USB_HSIC=y
CONFIG_PHY_SAMSUNG_USB2=y
CONFIG_PHY_TUSB1210=y
CONFIG_PHY_INTEL_LGM_COMBO=y
CONFIG_PHY_INTEL_LGM_EMMC=y
# end of PHY Subsystem
CONFIG_POWERCAP=y
CONFIG_INTEL_RAPL_CORE=y
CONFIG_INTEL_RAPL=y
CONFIG_IDLE_INJECT=y
CONFIG_DTPM=y
CONFIG_DTPM_CPU=y
CONFIG_DTPM_DEVFREQ=y
CONFIG_MCB=y
CONFIG_MCB_PCI=y
CONFIG_MCB_LPC=y
#
# Performance monitor support
#
# end of Performance monitor support
CONFIG_RAS=y
CONFIG_RAS_CEC=y
CONFIG_RAS_CEC_DEBUG=y
CONFIG_USB4=y
CONFIG_USB4_DEBUGFS_WRITE=y
CONFIG_USB4_DEBUGFS_MARGINING=y
CONFIG_USB4_KUNIT_TEST=y
CONFIG_USB4_DMA_TEST=y
#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
CONFIG_ANDROID_BINDER_IPC_SELFTEST=y
# end of Android
CONFIG_DAX=y
CONFIG_DEV_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_RAVE_SP_EEPROM=y
CONFIG_NVMEM_RMEM=y
CONFIG_NVMEM_SPMI_SDAM=y
CONFIG_NVMEM_U_BOOT_ENV=y
#
# HW tracing support
#
CONFIG_STM=y
CONFIG_STM_PROTO_BASIC=y
CONFIG_STM_PROTO_SYS_T=y
CONFIG_STM_DUMMY=y
CONFIG_STM_SOURCE_CONSOLE=y
CONFIG_STM_SOURCE_HEARTBEAT=y
CONFIG_STM_SOURCE_FTRACE=y
CONFIG_INTEL_TH=y
CONFIG_INTEL_TH_PCI=y
CONFIG_INTEL_TH_ACPI=y
CONFIG_INTEL_TH_GTH=y
CONFIG_INTEL_TH_STH=y
CONFIG_INTEL_TH_MSU=y
CONFIG_INTEL_TH_PTI=y
CONFIG_INTEL_TH_DEBUG=y
# end of HW tracing support
CONFIG_FPGA=y
CONFIG_ALTERA_PR_IP_CORE=y
CONFIG_ALTERA_PR_IP_CORE_PLAT=y
CONFIG_FPGA_MGR_ALTERA_PS_SPI=y
CONFIG_FPGA_MGR_ALTERA_CVP=y
CONFIG_FPGA_MGR_XILINX_SPI=y
CONFIG_FPGA_MGR_ICE40_SPI=y
CONFIG_FPGA_MGR_MACHXO2_SPI=y
CONFIG_FPGA_BRIDGE=y
CONFIG_ALTERA_FREEZE_BRIDGE=y
CONFIG_XILINX_PR_DECOUPLER=y
CONFIG_FPGA_REGION=y
CONFIG_OF_FPGA_REGION=y
CONFIG_FPGA_DFL=y
CONFIG_FPGA_DFL_FME=y
CONFIG_FPGA_DFL_FME_MGR=y
CONFIG_FPGA_DFL_FME_BRIDGE=y
CONFIG_FPGA_DFL_FME_REGION=y
CONFIG_FPGA_DFL_AFU=y
CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=y
CONFIG_FPGA_DFL_PCI=y
CONFIG_FPGA_M10_BMC_SEC_UPDATE=y
CONFIG_FPGA_MGR_MICROCHIP_SPI=y
CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=y
CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=y
CONFIG_FSI=y
CONFIG_FSI_NEW_DEV_NODE=y
CONFIG_FSI_MASTER_GPIO=y
CONFIG_FSI_MASTER_HUB=y
CONFIG_FSI_MASTER_ASPEED=y
CONFIG_FSI_SCOM=y
CONFIG_FSI_SBEFIFO=y
CONFIG_FSI_OCC=y
CONFIG_TEE=y
CONFIG_MULTIPLEXER=y
#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=y
CONFIG_MUX_ADGS1408=y
CONFIG_MUX_GPIO=y
CONFIG_MUX_MMIO=y
# end of Multiplexer drivers
CONFIG_PM_OPP=y
CONFIG_SIOX=y
CONFIG_SIOX_BUS_GPIO=y
CONFIG_SLIMBUS=y
CONFIG_SLIM_QCOM_CTRL=y
CONFIG_INTERCONNECT=y
CONFIG_COUNTER=y
CONFIG_104_QUAD_8=y
CONFIG_INTERRUPT_CNT=y
CONFIG_FTM_QUADDEC=y
CONFIG_MICROCHIP_TCB_CAPTURE=y
CONFIG_INTEL_QEP=y
CONFIG_MOST=y
CONFIG_MOST_USB_HDM=y
CONFIG_MOST_CDEV=y
CONFIG_MOST_SND=y
CONFIG_PECI=y
CONFIG_PECI_CPU=y
CONFIG_HTE=y
# end of Device Drivers
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_DEBUG=y
CONFIG_EXT4_KUNIT_TESTS=y
CONFIG_JBD2=y
CONFIG_JBD2_DEBUG=y
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=y
CONFIG_REISERFS_CHECK=y
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=y
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
CONFIG_JFS_DEBUG=y
CONFIG_JFS_STATISTICS=y
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_XFS_RT=y
CONFIG_XFS_ONLINE_SCRUB=y
CONFIG_XFS_ONLINE_REPAIR=y
CONFIG_XFS_DEBUG=y
CONFIG_XFS_ASSERT_FATAL=y
CONFIG_GFS2_FS=y
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=y
CONFIG_OCFS2_FS_O2CB=y
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=y
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
CONFIG_OCFS2_DEBUG_FS=y
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_BTRFS_FS_CHECK_INTEGRITY=y
CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y
CONFIG_BTRFS_DEBUG=y
CONFIG_BTRFS_ASSERT=y
CONFIG_BTRFS_FS_REF_VERIFY=y
CONFIG_NILFS2_FS=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
CONFIG_F2FS_CHECK_FS=y
CONFIG_F2FS_FAULT_INJECTION=y
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
CONFIG_F2FS_UNFAIR_RWSEM=y
CONFIG_ZONEFS_FS=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_FS_VERITY=y
CONFIG_FS_VERITY_DEBUG=y
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
CONFIG_QUOTA_DEBUG=y
CONFIG_QUOTA_TREE=y
CONFIG_QFMT_V1=y
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=y
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
CONFIG_OVERLAY_FS_INDEX=y
CONFIG_OVERLAY_FS_METACOPY=y
#
# Caches
#
CONFIG_NETFS_SUPPORT=y
CONFIG_NETFS_STATS=y
CONFIG_FSCACHE=y
CONFIG_FSCACHE_STATS=y
CONFIG_FSCACHE_DEBUG=y
CONFIG_CACHEFILES=y
CONFIG_CACHEFILES_DEBUG=y
CONFIG_CACHEFILES_ERROR_INJECTION=y
CONFIG_CACHEFILES_ONDEMAND=y
# end of Caches
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
# end of CD-ROM/DVD Filesystems
#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_FAT_KUNIT_TEST=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_NTFS_FS=y
CONFIG_NTFS_DEBUG=y
CONFIG_NTFS_RW=y
CONFIG_NTFS3_FS=y
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_VMCORE_DEVICE_DUMP=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_PROC_PID_ARCH_STATUS=y
CONFIG_PROC_CPU_RESCTRL=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems
CONFIG_MISC_FILESYSTEMS=y
CONFIG_ORANGEFS_FS=y
CONFIG_ADFS_FS=y
CONFIG_ADFS_FS_RW=y
CONFIG_AFFS_FS=y
CONFIG_ECRYPT_FS=y
CONFIG_ECRYPT_FS_MESSAGING=y
CONFIG_HFS_FS=y
CONFIG_HFSPLUS_FS=y
CONFIG_BEFS_FS=y
CONFIG_BEFS_DEBUG=y
CONFIG_BFS_FS=y
CONFIG_EFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_FS_POSIX_ACL=y
CONFIG_JFFS2_FS_SECURITY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
CONFIG_UBIFS_ATIME_SUPPORT=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
CONFIG_UBIFS_FS_AUTHENTICATION=y
CONFIG_CRAMFS=y
CONFIG_CRAMFS_BLOCKDEV=y
CONFIG_CRAMFS_MTD=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
CONFIG_SQUASHFS_DECOMP_MULTI=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_VXFS_FS=y
CONFIG_MINIX_FS=y
CONFIG_OMFS_FS=y
CONFIG_HPFS_FS=y
CONFIG_QNX4FS_FS=y
CONFIG_QNX6FS_FS=y
CONFIG_QNX6FS_DEBUG=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_FTRACE=y
CONFIG_PSTORE_RAM=y
CONFIG_PSTORE_ZONE=y
CONFIG_PSTORE_BLK=y
CONFIG_PSTORE_BLK_BLKDEV=""
CONFIG_PSTORE_BLK_KMSG_SIZE=64
CONFIG_PSTORE_BLK_MAX_REASON=2
CONFIG_PSTORE_BLK_PMSG_SIZE=64
CONFIG_PSTORE_BLK_CONSOLE_SIZE=64
CONFIG_PSTORE_BLK_FTRACE_SIZE=64
CONFIG_SYSV_FS=y
CONFIG_UFS_FS=y
CONFIG_UFS_FS_WRITE=y
CONFIG_UFS_DEBUG=y
CONFIG_EROFS_FS=y
CONFIG_EROFS_FS_DEBUG=y
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_ZIP_LZMA=y
CONFIG_EROFS_FS_ONDEMAND=y
CONFIG_VBOXSF_FS=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_BLOCK=y
CONFIG_PNFS_FLEXFILE_LAYOUT=y
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
CONFIG_NFS_V4_1_MIGRATION=y
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_ROOT_NFS=y
CONFIG_NFS_FSCACHE=y
CONFIG_NFS_USE_LEGACY_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=y
CONFIG_NFSD_V2=y
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_SUNRPC_XPRT_RDMA=y
CONFIG_CEPH_FS=y
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
CONFIG_CEPH_FS_SECURITY_LABEL=y
CONFIG_CIFS=y
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
CONFIG_CIFS_DEBUG2=y
CONFIG_CIFS_DEBUG_DUMP_KEYS=y
CONFIG_CIFS_DFS_UPCALL=y
CONFIG_CIFS_SWN_UPCALL=y
CONFIG_CIFS_SMB_DIRECT=y
CONFIG_CIFS_FSCACHE=y
CONFIG_CIFS_ROOT=y
CONFIG_SMB_SERVER=y
CONFIG_SMB_SERVER_SMBDIRECT=y
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS_COMMON=y
CONFIG_CODA_FS=y
CONFIG_AFS_FS=y
CONFIG_AFS_DEBUG=y
CONFIG_AFS_FSCACHE=y
CONFIG_AFS_DEBUG_CURSOR=y
CONFIG_9P_FS=y
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_MAC_ROMAN=y
CONFIG_NLS_MAC_CELTIC=y
CONFIG_NLS_MAC_CENTEURO=y
CONFIG_NLS_MAC_CROATIAN=y
CONFIG_NLS_MAC_CYRILLIC=y
CONFIG_NLS_MAC_GAELIC=y
CONFIG_NLS_MAC_GREEK=y
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
CONFIG_NLS_MAC_ROMANIAN=y
CONFIG_NLS_MAC_TURKISH=y
CONFIG_NLS_UTF8=y
CONFIG_DLM=y
CONFIG_DLM_DEPRECATED_API=y
CONFIG_DLM_DEBUG=y
CONFIG_UNICODE=y
CONFIG_UNICODE_NORMALIZATION_SELFTEST=y
CONFIG_IO_WQ=y
# end of File systems
#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_REQUEST_CACHE=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_BIG_KEYS=y
CONFIG_TRUSTED_KEYS=y
CONFIG_TRUSTED_KEYS_TPM=y
CONFIG_TRUSTED_KEYS_TEE=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_USER_DECRYPTED_DATA=y
CONFIG_KEY_DH_OPERATIONS=y
CONFIG_KEY_NOTIFICATIONS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITY=y
CONFIG_SECURITY_WRITABLE_HOOKS=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_INFINIBAND=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_PATH=y
CONFIG_INTEL_TXT=y
CONFIG_LSM_MMAP_MIN_ADDR=65536
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper"
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
CONFIG_SECURITY_SMACK=y
CONFIG_SECURITY_SMACK_BRINGUP=y
CONFIG_SECURITY_SMACK_NETFILTER=y
CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y
CONFIG_SECURITY_TOMOYO=y
CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048
CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024
CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER=y
CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING=y
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_DEBUG=y
CONFIG_SECURITY_APPARMOR_DEBUG_ASSERTS=y
CONFIG_SECURITY_APPARMOR_DEBUG_MESSAGES=y
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
CONFIG_SECURITY_APPARMOR_KUNIT_TEST=y
CONFIG_SECURITY_LOADPIN=y
CONFIG_SECURITY_LOADPIN_ENFORCE=y
CONFIG_SECURITY_LOADPIN_VERITY=y
CONFIG_SECURITY_YAMA=y
CONFIG_SECURITY_SAFESETID=y
CONFIG_SECURITY_LOCKDOWN_LSM=y
CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y
# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set
# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set
CONFIG_SECURITY_LANDLOCK=y
CONFIG_INTEGRITY=y
CONFIG_INTEGRITY_SIGNATURE=y
CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
CONFIG_INTEGRITY_TRUSTED_KEYRING=y
CONFIG_INTEGRITY_PLATFORM_KEYRING=y
CONFIG_LOAD_UEFI_KEYS=y
CONFIG_INTEGRITY_AUDIT=y
CONFIG_IMA=y
CONFIG_IMA_MEASURE_PCR_IDX=10
CONFIG_IMA_LSM_RULES=y
CONFIG_IMA_NG_TEMPLATE=y
# CONFIG_IMA_SIG_TEMPLATE is not set
CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng"
CONFIG_IMA_DEFAULT_HASH_SHA1=y
# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set
# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set
# CONFIG_IMA_DEFAULT_HASH_WP512 is not set
# CONFIG_IMA_DEFAULT_HASH_SM3 is not set
CONFIG_IMA_DEFAULT_HASH="sha1"
CONFIG_IMA_WRITE_POLICY=y
CONFIG_IMA_READ_POLICY=y
CONFIG_IMA_APPRAISE=y
CONFIG_IMA_ARCH_POLICY=y
CONFIG_IMA_APPRAISE_BUILD_POLICY=y
CONFIG_IMA_APPRAISE_REQUIRE_FIRMWARE_SIGS=y
CONFIG_IMA_APPRAISE_REQUIRE_KEXEC_SIGS=y
CONFIG_IMA_APPRAISE_REQUIRE_MODULE_SIGS=y
CONFIG_IMA_APPRAISE_REQUIRE_POLICY_SIGS=y
CONFIG_IMA_APPRAISE_BOOTPARAM=y
CONFIG_IMA_APPRAISE_MODSIG=y
CONFIG_IMA_TRUSTED_KEYRING=y
CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y
CONFIG_IMA_BLACKLIST_KEYRING=y
CONFIG_IMA_LOAD_X509=y
CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der"
CONFIG_IMA_APPRAISE_SIGNED_INIT=y
CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y
CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y
CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT=y
CONFIG_IMA_DISABLE_HTABLE=y
CONFIG_EVM=y
CONFIG_EVM_ATTR_FSUUID=y
CONFIG_EVM_EXTRA_SMACK_XATTRS=y
CONFIG_EVM_ADD_XATTRS=y
CONFIG_EVM_LOAD_X509=y
CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der"
CONFIG_DEFAULT_SECURITY_SELINUX=y
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
# CONFIG_DEFAULT_SECURITY_DAC is not set
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf"
#
# Kernel hardening options
#
CONFIG_GCC_PLUGIN_STRUCTLEAK=y
#
# Memory initialization
#
# CONFIG_INIT_STACK_NONE is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_VERBOSE is not set
CONFIG_GCC_PLUGIN_STACKLEAK=y
# CONFIG_GCC_PLUGIN_STACKLEAK_VERBOSE is not set
CONFIG_STACKLEAK_TRACK_MIN_SIZE=100
CONFIG_STACKLEAK_METRICS=y
CONFIG_STACKLEAK_RUNTIME_DISABLE=y
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
CONFIG_INIT_ON_FREE_DEFAULT_ON=y
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
CONFIG_ZERO_CALL_USED_REGS=y
# end of Memory initialization
# CONFIG_RANDSTRUCT_NONE is not set
CONFIG_RANDSTRUCT_FULL=y
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
CONFIG_RANDSTRUCT=y
CONFIG_GCC_PLUGIN_RANDSTRUCT=y
# end of Kernel hardening options
# end of Security options
CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=y
CONFIG_ASYNC_MEMCPY=y
CONFIG_ASYNC_XOR=y
CONFIG_ASYNC_PQ=y
CONFIG_ASYNC_RAID6_RECOV=y
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper
#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECDSA=y
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography
#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARIA=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers
#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=y
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XCTR=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes
#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers
#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_VMAC=y
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs
#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression
#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_KDF800108_CTR=y
# end of Random number generation
#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_RNG_CAVP=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_STATS=y
# end of Userspace interface
CONFIG_CRYPTO_HASH_INFO=y
#
# Accelerated Cryptographic Algorithms for CPU (x86)
#
CONFIG_CRYPTO_AES_NI_INTEL=y
CONFIG_CRYPTO_SERPENT_SSE2_586=y
CONFIG_CRYPTO_TWOFISH_586=y
CONFIG_CRYPTO_CRC32C_INTEL=y
CONFIG_CRYPTO_CRC32_PCLMUL=y
# end of Accelerated Cryptographic Algorithms for CPU (x86)
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_PADLOCK=y
CONFIG_CRYPTO_DEV_PADLOCK_AES=y
CONFIG_CRYPTO_DEV_PADLOCK_SHA=y
CONFIG_CRYPTO_DEV_GEODE=y
CONFIG_CRYPTO_DEV_HIFN_795X=y
CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
CONFIG_CRYPTO_DEV_ATMEL_I2C=y
CONFIG_CRYPTO_DEV_ATMEL_ECC=y
CONFIG_CRYPTO_DEV_ATMEL_SHA204A=y
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=y
CONFIG_CRYPTO_DEV_SP_CCP=y
CONFIG_CRYPTO_DEV_CCP_CRYPTO=y
CONFIG_CRYPTO_DEV_CCP_DEBUGFS=y
CONFIG_CRYPTO_DEV_QAT=y
CONFIG_CRYPTO_DEV_QAT_DH895xCC=y
CONFIG_CRYPTO_DEV_QAT_C3XXX=y
CONFIG_CRYPTO_DEV_QAT_C62X=y
CONFIG_CRYPTO_DEV_QAT_4XXX=y
CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=y
CONFIG_CRYPTO_DEV_QAT_C3XXXVF=y
CONFIG_CRYPTO_DEV_QAT_C62XVF=y
CONFIG_CRYPTO_DEV_CHELSIO=y
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRYPTO_DEV_SAFEXCEL=y
CONFIG_CRYPTO_DEV_CCREE=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=y
CONFIG_SIGNED_PE_FILE_VERIFICATION=y
CONFIG_FIPS_SIGNATURE_SELFTEST=y
#
# Certificates for signature checking
#
CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
CONFIG_SECONDARY_TRUSTED_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
CONFIG_SYSTEM_REVOCATION_LIST=y
CONFIG_SYSTEM_REVOCATION_KEYS=""
CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
# end of Certificates for signature checking
CONFIG_BINARY_PRINTF=y
#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=y
CONFIG_PRIME_NUMBERS=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
CONFIG_CRC32_SELFTEST=y
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_TEST=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC16=y
CONFIG_REED_SOLOMON_DEC16=y
CONFIG_BCH=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=y
CONFIG_TEXTSEARCH_BM=y
CONFIG_TEXTSEARCH_FSM=y
CONFIG_BTREE=y
CONFIG_INTERVAL_TREE=y
CONFIG_INTERVAL_TREE_SPAN_ITER=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=0
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
CONFIG_DMA_API_DEBUG=y
CONFIG_DMA_API_DEBUG_SG=y
CONFIG_DMA_MAP_BENCHMARK=y
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
CONFIG_CPUMASK_OFFSTACK=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
CONFIG_GLOB_SELFTEST=y
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=y
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_SIGNATURE=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_FONT_6x11=y
CONFIG_FONT_7x14=y
CONFIG_FONT_PEARL_8x8=y
CONFIG_FONT_ACORN_8x8=y
CONFIG_FONT_MINI_4x6=y
CONFIG_FONT_6x10=y
CONFIG_FONT_10x18=y
CONFIG_FONT_SUN8x16=y
CONFIG_FONT_SUN12x22=y
CONFIG_FONT_TER16x32=y
CONFIG_FONT_6x8=y
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_REF_TRACKER=y
CONFIG_SBITMAP=y
CONFIG_PARMAN=y
CONFIG_OBJAGG=y
# end of Library routines
CONFIG_PLDMFW=y
CONFIG_ASN1_ENCODER=y
CONFIG_POLYNOMIAL=y
#
# Kernel hacking
#
#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y
#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
CONFIG_READABLE_ASM=y
CONFIG_HEADERS_INSTALL=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
CONFIG_VMLINUX_MAP=y
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
# end of Compile-time checks and compiler options
#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
CONFIG_KGDB_HONOUR_BLOCKLIST=y
CONFIG_KGDB_SERIAL_CONSOLE=y
CONFIG_KGDB_TESTS=y
CONFIG_KGDB_TESTS_ON_BOOT=y
CONFIG_KGDB_TESTS_BOOT_STRING="V1F100"
CONFIG_KGDB_LOW_LEVEL_TRAP=y
CONFIG_KGDB_KDB=y
CONFIG_KDB_DEFAULT_ENABLE=0x1
CONFIG_KDB_KEYBOARD=y
CONFIG_KDB_CONTINUE_CATASTROPHIC=0
CONFIG_ARCH_HAS_EARLY_DEBUG=y
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
CONFIG_UBSAN=y
# CONFIG_UBSAN_TRAP is not set
CONFIG_CC_HAS_UBSAN_BOUNDS=y
CONFIG_UBSAN_BOUNDS=y
CONFIG_UBSAN_ONLY_BOUNDS=y
CONFIG_UBSAN_SHIFT=y
CONFIG_UBSAN_DIV_ZERO=y
CONFIG_UBSAN_UNREACHABLE=y
CONFIG_UBSAN_BOOL=y
CONFIG_UBSAN_ENUM=y
# CONFIG_UBSAN_ALIGNMENT is not set
CONFIG_UBSAN_SANITIZE_ALL=y
CONFIG_TEST_UBSAN=m
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments
#
# Networking Debugging
#
CONFIG_NET_DEV_REFCNT_TRACKER=y
CONFIG_NET_NS_REFCNT_TRACKER=y
CONFIG_DEBUG_NET=y
# end of Networking Debugging
#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
CONFIG_DEBUG_PAGEALLOC=y
CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y
CONFIG_PAGE_OWNER=y
CONFIG_PAGE_POISONING=y
CONFIG_DEBUG_PAGE_REF=y
CONFIG_DEBUG_RODATA_TEST=y
CONFIG_ARCH_HAS_DEBUG_WX=y
CONFIG_DEBUG_WX=y
CONFIG_GENERIC_PTDUMP=y
CONFIG_PTDUMP_CORE=y
CONFIG_PTDUMP_DEBUGFS=y
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_OBJECTS_SELFTEST=y
CONFIG_DEBUG_OBJECTS_FREE=y
CONFIG_DEBUG_OBJECTS_TIMERS=y
CONFIG_DEBUG_OBJECTS_WORK=y
CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
CONFIG_SHRINKER_DEBUG=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000
CONFIG_DEBUG_KMEMLEAK_TEST=m
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_VM_MAPLE_TREE=y
CONFIG_DEBUG_VM_RB=y
CONFIG_DEBUG_VM_PGFLAGS=y
CONFIG_DEBUG_VM_PGTABLE=y
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_DEBUG_VIRTUAL=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_PER_CPU_MAPS=y
CONFIG_DEBUG_KMAP_LOCAL=y
CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP=y
CONFIG_DEBUG_HIGHMEM=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
CONFIG_HAVE_ARCH_KFENCE=y
CONFIG_KFENCE=y
CONFIG_KFENCE_SAMPLE_INTERVAL=100
CONFIG_KFENCE_NUM_OBJECTS=255
CONFIG_KFENCE_DEFERRABLE=y
CONFIG_KFENCE_STATIC_KEYS=y
CONFIG_KFENCE_STRESS_TEST_FAULTS=0
CONFIG_KFENCE_KUNIT_TEST=y
# end of Memory Debugging
CONFIG_DEBUG_SHIRQ=y
#
# Debug Oops, Lockups and Hangs
#
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_WQ_WATCHDOG=y
CONFIG_TEST_LOCKUP=m
# end of Debug Oops, Lockups and Hangs
#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging
CONFIG_DEBUG_TIMEKEEPING=y
CONFIG_DEBUG_PREEMPT=y
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
CONFIG_PROVE_RAW_LOCK_NESTING=y
CONFIG_LOCK_STAT=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
CONFIG_DEBUG_LOCKDEP=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LOCKING_API_SELFTESTS=y
CONFIG_LOCK_TORTURE_TEST=y
CONFIG_WW_MUTEX_SELFTEST=y
CONFIG_SCF_TORTURE_TEST=y
# end of Lock Debugging (spinlocks, mutexes, etc...)
CONFIG_TRACE_IRQFLAGS=y
CONFIG_TRACE_IRQFLAGS_NMI=y
CONFIG_DEBUG_IRQFLAGS=y
CONFIG_STACKTRACE=y
CONFIG_WARN_ALL_UNSEEDED_RANDOM=y
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_KOBJECT_RELEASE=y
#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
CONFIG_DEBUG_PLIST=y
CONFIG_DEBUG_SG=y
CONFIG_DEBUG_NOTIFIERS=y
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_DEBUG_MAPLE_TREE=y
# end of Debug kernel data structures
CONFIG_DEBUG_CREDENTIALS=y
#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
CONFIG_PROVE_RCU_LIST=y
CONFIG_TORTURE_TEST=y
CONFIG_RCU_SCALE_TEST=y
CONFIG_RCU_TORTURE_TEST=y
CONFIG_RCU_REF_SCALE_TEST=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
CONFIG_RCU_TRACE=y
CONFIG_RCU_EQS_DEBUG=y
# end of RCU Debugging
CONFIG_DEBUG_WQ_FORCE_RR_CPU=y
CONFIG_CPU_HOTPLUG_STATE_CONTROL=y
CONFIG_LATENCYTOP=y
CONFIG_DEBUG_CGROUP_REF=y
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_RETHOOK=y
CONFIG_RETHOOK=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_FENTRY=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
CONFIG_BUILDTIME_MCOUNT_SORT=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_BOOTTIME_TRACING=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
CONFIG_DYNAMIC_FTRACE=y
CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
CONFIG_FPROBE=y
CONFIG_FUNCTION_PROFILER=y
CONFIG_STACK_TRACER=y
CONFIG_TRACE_PREEMPT_TOGGLE=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_PREEMPT_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_HWLAT_TRACER=y
CONFIG_OSNOISE_TRACER=y
CONFIG_TIMERLAT_TRACER=y
CONFIG_MMIOTRACE=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_TRACER_SNAPSHOT=y
CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_KPROBE_EVENTS=y
CONFIG_KPROBE_EVENTS_ON_NOTRACE=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_BPF_KPROBE_OVERRIDE=y
CONFIG_FTRACE_MCOUNT_RECORD=y
CONFIG_FTRACE_MCOUNT_USE_CC=y
CONFIG_TRACING_MAP=y
CONFIG_SYNTH_EVENTS=y
CONFIG_HIST_TRIGGERS=y
CONFIG_TRACE_EVENT_INJECT=y
CONFIG_TRACEPOINT_BENCHMARK=y
CONFIG_RING_BUFFER_BENCHMARK=y
CONFIG_TRACE_EVAL_MAP_FILE=y
CONFIG_FTRACE_RECORD_RECURSION=y
CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
CONFIG_RING_BUFFER_RECORD_RECURSION=y
CONFIG_GCOV_PROFILE_FTRACE=y
CONFIG_FTRACE_SELFTEST=y
CONFIG_FTRACE_STARTUP_TEST=y
CONFIG_EVENT_TRACE_STARTUP_TEST=y
CONFIG_EVENT_TRACE_TEST_SYSCALLS=y
CONFIG_FTRACE_SORT_STARTUP_TEST=y
CONFIG_RING_BUFFER_STARTUP_TEST=y
CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y
CONFIG_MMIOTRACE_TEST=m
CONFIG_PREEMPTIRQ_DELAY_TEST=m
CONFIG_SYNTH_EVENT_GEN_TEST=y
CONFIG_KPROBE_EVENT_GEN_TEST=y
CONFIG_HIST_TRIGGERS_DEBUG=y
CONFIG_DA_MON_EVENTS=y
CONFIG_DA_MON_EVENTS_IMPLICIT=y
CONFIG_DA_MON_EVENTS_ID=y
CONFIG_RV=y
CONFIG_RV_MON_WIP=y
CONFIG_RV_MON_WWNR=y
CONFIG_RV_REACTORS=y
CONFIG_RV_REACT_PRINTK=y
CONFIG_RV_REACT_PANIC=y
CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
CONFIG_SAMPLES=y
CONFIG_SAMPLE_AUXDISPLAY=y
CONFIG_SAMPLE_TRACE_EVENTS=m
CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS=m
CONFIG_SAMPLE_TRACE_PRINTK=m
CONFIG_SAMPLE_TRACE_ARRAY=m
CONFIG_SAMPLE_KOBJECT=y
CONFIG_SAMPLE_KPROBES=m
CONFIG_SAMPLE_KRETPROBES=m
CONFIG_SAMPLE_HW_BREAKPOINT=m
CONFIG_SAMPLE_FPROBE=m
CONFIG_SAMPLE_KFIFO=m
CONFIG_SAMPLE_KDB=m
CONFIG_SAMPLE_RPMSG_CLIENT=m
CONFIG_SAMPLE_CONFIGFS=m
CONFIG_SAMPLE_CONNECTOR=m
CONFIG_SAMPLE_FANOTIFY_ERROR=y
CONFIG_SAMPLE_HIDRAW=y
CONFIG_SAMPLE_LANDLOCK=y
CONFIG_SAMPLE_PIDFD=y
CONFIG_SAMPLE_SECCOMP=y
CONFIG_SAMPLE_TIMER=y
CONFIG_SAMPLE_UHID=y
CONFIG_SAMPLE_VFIO_MDEV_MTTY=m
CONFIG_SAMPLE_VFIO_MDEV_MDPY=m
CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB=m
CONFIG_SAMPLE_VFIO_MDEV_MBOCHS=m
CONFIG_SAMPLE_ANDROID_BINDERFS=y
CONFIG_SAMPLE_VFS=y
CONFIG_SAMPLE_INTEL_MEI=y
CONFIG_SAMPLE_WATCHDOG=y
CONFIG_SAMPLE_WATCH_QUEUE=y
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
CONFIG_STRICT_DEVMEM=y
CONFIG_IO_STRICT_DEVMEM=y
#
# x86 Debugging
#
CONFIG_EARLY_PRINTK_USB=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_DBGP=y
CONFIG_EARLY_PRINTK_USB_XDBC=y
CONFIG_EFI_PGT_DUMP=y
CONFIG_DEBUG_TLBFLUSH=y
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
# CONFIG_X86_DECODER_SELFTEST is not set
CONFIG_IO_DELAY_0X80=y
# CONFIG_IO_DELAY_0XED is not set
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
CONFIG_DEBUG_BOOT_PARAMS=y
CONFIG_CPA_DEBUG=y
CONFIG_DEBUG_ENTRY=y
CONFIG_DEBUG_NMI_SELFTEST=y
CONFIG_DEBUG_IMR_SELFTEST=y
CONFIG_X86_DEBUG_FPU=y
CONFIG_PUNIT_ATOM_DEBUG=y
CONFIG_UNWINDER_FRAME_POINTER=y
# end of x86 Debugging
#
# Kernel Testing and Coverage
#
CONFIG_KUNIT=y
CONFIG_KUNIT_DEBUGFS=y
CONFIG_KUNIT_TEST=y
CONFIG_KUNIT_EXAMPLE_TEST=y
CONFIG_KUNIT_ALL_TESTS=y
CONFIG_KUNIT_DEFAULT_ENABLED=y
CONFIG_NOTIFIER_ERROR_INJECTION=y
CONFIG_PM_NOTIFIER_ERROR_INJECT=y
CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=y
CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=y
CONFIG_FUNCTION_ERROR_INJECTION=y
CONFIG_FAULT_INJECTION=y
CONFIG_FAILSLAB=y
CONFIG_FAIL_PAGE_ALLOC=y
CONFIG_FAULT_INJECTION_USERCOPY=y
CONFIG_FAIL_MAKE_REQUEST=y
CONFIG_FAIL_IO_TIMEOUT=y
CONFIG_FAIL_FUTEX=y
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAIL_FUNCTION=y
CONFIG_FAIL_MMC_REQUEST=y
CONFIG_FAIL_SUNRPC=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
CONFIG_RUNTIME_TESTING_MENU=y
CONFIG_LKDTM=y
CONFIG_CPUMASK_KUNIT_TEST=y
CONFIG_TEST_LIST_SORT=y
CONFIG_TEST_MIN_HEAP=y
CONFIG_TEST_SORT=y
CONFIG_TEST_DIV64=y
CONFIG_KPROBES_SANITY_TEST=y
CONFIG_FPROBE_SANITY_TEST=y
CONFIG_BACKTRACE_SELF_TEST=y
CONFIG_TEST_REF_TRACKER=y
CONFIG_RBTREE_TEST=y
CONFIG_REED_SOLOMON_TEST=y
CONFIG_INTERVAL_TREE_TEST=y
CONFIG_PERCPU_TEST=m
CONFIG_ATOMIC64_SELFTEST=y
CONFIG_ASYNC_RAID6_TEST=y
CONFIG_TEST_HEXDUMP=y
CONFIG_STRING_SELFTEST=y
CONFIG_TEST_STRING_HELPERS=y
CONFIG_TEST_KSTRTOX=y
CONFIG_TEST_PRINTF=y
CONFIG_TEST_SCANF=y
CONFIG_TEST_BITMAP=y
CONFIG_TEST_UUID=y
CONFIG_TEST_XARRAY=y
CONFIG_TEST_MAPLE_TREE=y
CONFIG_TEST_RHASHTABLE=y
CONFIG_TEST_IDA=y
CONFIG_TEST_PARMAN=y
CONFIG_TEST_LKM=m
CONFIG_TEST_BITOPS=m
CONFIG_TEST_VMALLOC=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
CONFIG_TEST_BLACKHOLE_DEV=m
CONFIG_FIND_BIT_BENCHMARK=y
CONFIG_TEST_FIRMWARE=y
CONFIG_TEST_SYSCTL=y
CONFIG_BITFIELD_KUNIT=y
CONFIG_HASH_KUNIT_TEST=y
CONFIG_RESOURCE_KUNIT_TEST=y
CONFIG_SYSCTL_KUNIT_TEST=y
CONFIG_LIST_KUNIT_TEST=y
CONFIG_LINEAR_RANGES_TEST=y
CONFIG_CMDLINE_KUNIT_TEST=y
CONFIG_BITS_TEST=y
CONFIG_RATIONAL_KUNIT_TEST=y
CONFIG_MEMCPY_KUNIT_TEST=y
CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=y
CONFIG_OVERFLOW_KUNIT_TEST=y
CONFIG_STACKINIT_KUNIT_TEST=y
CONFIG_FORTIFY_KUNIT_TEST=y
CONFIG_HW_BREAKPOINT_KUNIT_TEST=y
CONFIG_STRSCPY_KUNIT_TEST=y
CONFIG_SIPHASH_KUNIT_TEST=y
CONFIG_TEST_UDELAY=y
CONFIG_TEST_STATIC_KEYS=m
CONFIG_TEST_DYNAMIC_DEBUG=y
CONFIG_TEST_KMOD=m
CONFIG_TEST_DEBUG_VIRTUAL=y
CONFIG_TEST_MEMCAT_P=y
CONFIG_TEST_OBJAGG=y
CONFIG_TEST_MEMINIT=y
CONFIG_TEST_FREE_PAGES=y
CONFIG_TEST_FPU=y
CONFIG_TEST_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
CONFIG_HYPERV_TESTING=y
# end of Kernel Testing and Coverage
#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
2023-01-11 15:30 ` kernel test robot
2023-01-11 22:55 ` kernel test robot
@ 2023-01-17 10:01 ` Hans Verkuil
2023-01-25 12:12 ` yuji2.ishikawa
2023-01-17 22:39 ` Sakari Ailus
2023-01-18 0:52 ` Laurent Pinchart
4 siblings, 1 reply; 42+ messages in thread
From: Hans Verkuil @ 2023-01-17 10:01 UTC (permalink / raw)
To: Yuji Ishikawa, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
Hi Yuji,
Some review comments below:
On 11/01/2023 03:24, Yuji Ishikawa wrote:
> Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> The interface device includes CSI2 Receiver,
> frame grabber, video DMAC and image signal processor.
> This patch provides operations to handle registers of HW listed above.
>
> The Video DMACs have 32bit address space
> and currently corresponding IOMMU driver is not provided.
> Therefore, memory-block address for captured image is 32bit IOVA
> which is equal to 32bit-truncated phisical address.
> When the Visconti IOMMU driver (currently under development) is accepted,
> the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> ---
> Changelog v2:
> - Resend v1 because a patch exceeds size limit.
>
> Changelog v3:
> - Adapted to media control framework
> - Introduced ISP subdevice, capture device
> - Remove private IOCTLs and add vendor specific V4L2 controls
> - Change function name avoiding camelcase and uppercase letters
>
> Changelog v4:
> - Split patches because the v3 patch exceeds size limit
> - Stop using ID number to identify driver instance:
> - Use dynamically allocated structure to hold driver's context,
> instead of static one indexed by ID number.
> - Functions accept driver's context structure instead of ID number.
>
> Changelog v5:
> - no change
> ---
> drivers/media/platform/Kconfig | 1 +
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/visconti/Kconfig | 9 +
> drivers/media/platform/visconti/Makefile | 8 +
> drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
> drivers/media/platform/visconti/hwd_viif.h | 710 +++++
> .../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
> .../platform/visconti/hwd_viif_internal.h | 340 ++
> .../media/platform/visconti/hwd_viif_reg.h | 2802 +++++++++++++++++
> include/uapi/linux/visconti_viif.h | 1724 ++++++++++
> 10 files changed, 7895 insertions(+)
> create mode 100644 drivers/media/platform/visconti/Kconfig
> create mode 100644 drivers/media/platform/visconti/Makefile
> create mode 100644 drivers/media/platform/visconti/hwd_viif.c
> create mode 100644 drivers/media/platform/visconti/hwd_viif.h
> create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
> create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
> create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
> create mode 100644 include/uapi/linux/visconti_viif.h
>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index a9334263fa9..0908158036d 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -83,6 +83,7 @@ source "drivers/media/platform/sunxi/Kconfig"
> source "drivers/media/platform/ti/Kconfig"
> source "drivers/media/platform/verisilicon/Kconfig"
> source "drivers/media/platform/via/Kconfig"
> +source "drivers/media/platform/visconti/Kconfig"
We're moving towards a "drivers/media/platform/<vendor>/<model>/" directory
structure, so it is better to move this driver to .../platform/toshiba/visconti/.
> source "drivers/media/platform/xilinx/Kconfig"
>
> endif # MEDIA_PLATFORM_DRIVERS
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index a91f4202427..1c67cb56244 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -26,6 +26,7 @@ obj-y += sunxi/
> obj-y += ti/
> obj-y += verisilicon/
> obj-y += via/
> +obj-y += visconti/
> obj-y += xilinx/
>
> # Please place here only ancillary drivers that aren't SoC-specific
> diff --git a/drivers/media/platform/visconti/Kconfig b/drivers/media/platform/visconti/Kconfig
> new file mode 100644
> index 00000000000..031e4610809
> --- /dev/null
> +++ b/drivers/media/platform/visconti/Kconfig
> @@ -0,0 +1,9 @@
> +config VIDEO_VISCONTI_VIIF
> + tristate "Visconti Camera Interface driver"
> + depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER && VIDEO_DEV
> + depends on ARCH_VISCONTI
This should be: depends on ARCH_VISCONTI || COMPILE_TEST
We want to be able to compile this driver for other platforms as well.
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_FWNODE
> + help
> + This is V4L2 driver for Toshiba Visconti Camera Interface driver
> +
> diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
> new file mode 100644
> index 00000000000..e14b904df75
> --- /dev/null
> +++ b/drivers/media/platform/visconti/Makefile
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for the Visconti video input device driver
> +#
> +
> +visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> +
> +obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> diff --git a/drivers/media/platform/visconti/hwd_viif.c b/drivers/media/platform/visconti/hwd_viif.c
> new file mode 100644
> index 00000000000..260293fa4d0
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif.c
> @@ -0,0 +1,1690 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
It's odd to see two copyrights from what looks like the same company.
Just checking: is this correct?
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +#include "hwd_viif.h"
> +#include "hwd_viif_internal.h"
> +
> +/* MIPI CSI2 DataType definition */
> +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
> +
> +struct hwd_viif_res *allocate_viif_res(struct device *dev, void *csi2host_vaddr,
> + void *capture_vaddr)
> +{
> + struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res), GFP_KERNEL);
> +
> + res->csi2host_reg = csi2host_vaddr;
> + res->capture_reg = capture_vaddr;
> + res->run_flag_main = (bool)false;
> + return res;
> +}
> +
> +/* Convert the unit of time-period (from sysclk, to num lines in the image) */
> +static u32 sysclk_to_numlines(u64 time_in_sysclk, const struct hwd_viif_input_img *img)
> +{
> + u64 v1 = time_in_sysclk * (u64)img->pixel_clock;
> + u64 v2 = (u64)img->htotal_size * HWD_VIIF_SYS_CLK;
> +
> + return (u32)(v1 / v2);
Use div64_u64 instead so it will compile on platforms without native 64 bit division support.
> +}
> +
> +static u32 lineperiod_in_sysclk(u64 hsize, u64 pixel_clock)
> +{
> + return (u32)(hsize * HWD_VIIF_SYS_CLK / pixel_clock);
Ditto.
> +}
<snip>
> diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h b/drivers/media/platform/visconti/hwd_viif_internal.h
> new file mode 100644
> index 00000000000..c954e804946
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_internal.h
> @@ -0,0 +1,340 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_INTERNAL_H
> +#define HWD_VIIF_INTERNAL_H
> +
> +#include "hwd_viif_reg.h"
> +
> +#define HWD_VIIF_CSI2_MAX_VC (3U)
> +#define HWD_VIIF_CSI2_MIN_DT (0x10U)
> +#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
> +#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
> +#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
> +#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
> +#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
> +#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
> +#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
> +
> +/* maximum horizontal/vertical position/dimension of CROP with ISP */
> +#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
> +#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
> +#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
> +#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
> +
> +/* maximum horizontal/vertical position/dimension of CROP without ISP */
> +#define HWD_VIIF_CROP_MAX_X (1920U)
> +#define HWD_VIIF_CROP_MAX_Y (1408U)
> +#define HWD_VIIF_CROP_MIN_W (128U)
> +#define HWD_VIIF_CROP_MAX_W (2048U)
> +#define HWD_VIIF_CROP_MIN_H (128U)
> +#define HWD_VIIF_CROP_MAX_H (1536U)
> +
> +/* pixel clock: [kHz] */
> +#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
> +#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
> +
> +/* picture size: [pixel], [ns] */
> +#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
> +#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
> +#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
> +#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
> +
> +/* horizontal back porch size: [system clock] */
> +#define HWD_VIIF_HBP_SYSCLK (10U)
> +
> +/* active picture size: [pixel] */
> +#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
> +#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
> +#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
> +#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
> +
> +/* picture vertical size: [line], [packet] */
> +#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
> +#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
> +#define HWD_VIIF_MIN_VBP_LINE (5U)
> +#define HWD_VIIF_MAX_VBP_LINE (4095U)
> +#define HWD_VIIF_MIN_VBP_PACKET (5U)
> +#define HWD_VIIF_MAX_VBP_PACKET (4095U)
> +#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
> +#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
> +#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
> +#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
> +
> +/* image source select */
> +#define HWD_VIIF_INPUT_CSI2 (0U)
> +
> +#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
> +#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
> +#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
> +#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
> +#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
> +#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
> +#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
> +#define HWD_VIIF_MAX_PITCH_ISP (32704U)
> +#define HWD_VIIF_MAX_PITCH (65536U)
> +
> +/* size of minimum/maximum input image */
> +#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
> +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
> +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
> +#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
> +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
> +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
> +#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
> +
> +/* size of minimum/maximum output image */
> +#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> +
> +#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> +
> +#define HWD_VIIF_NO_EVENT (0x0U)
> +
> +/* System clock: [kHz] */
> +#define HWD_VIIF_SYS_CLK (500000UL)
> +
> +/*
> + * wait time for force abort to complete(max 1line time = 1228.8[us]
> + * when width = 4096, RAW24, 80Mbps
> + */
> +#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
> +
> +/*
> + * complete time of register buffer transfer.
> + * actual time is about 30us in case of L1ISP
> + */
> +#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
> +
> +/* internal operation latencies: [system clock]*/
> +#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
> +#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
> +
> +/* offset of Vsync delay: [line] */
> +#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
> +#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
> +
> +/* data width is 32bit */
> +#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
> +
> +/* vsync mode is pulse */
> +#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
> +
> +/* Vlatch mask bit for L1ISP and L2ISP */
> +#define HWD_VIIF_ISP_VLATCH_MASK (2U)
> +
> +/* Register buffer */
> +#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
> +#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
> +#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
> +#define HWD_VIIF_ISP_REGBUF_READ (1U)
> +
> +/* constants for L1 ISP*/
> +#define HWD_VIIF_L1_INPUT_MODE_NUM (5U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_MIN (8U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_MAX (24U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_SDR_MAX (12U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX (14U)
> +#define HWD_VIIF_L1_RAW_MODE_NUM (4U)
> +#define HWD_VIIF_L1_INPUT_NUM_MIN (1U)
> +#define HWD_VIIF_L1_INPUT_NUM_MAX (3U)
> +#define HWD_VIIF_L1_AG_ID_NUM (4U)
> +#define HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM (3U)
> +#define HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL (0x3fffU)
> +#define HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL (0xffffffU)
> +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO (0x400000U)
> +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL (0xffffffU)
> +#define HWD_VIIF_L1_OBCC_MAX_AG_VAL (511U)
> +#define HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL (0xffffffU)
> +#define HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL (1023U)
> +#define HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL (1U)
> +#define HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL (31U)
> +#define HWD_VIIF_L1_VDM_ALIGN (0x8U) /* port interface width is 64bit */
> +#define HWD_VIIF_L1_VDM_CFG_PARAM (0x00000310U) /* data width is 64bit */
> +#define HWD_VIIF_L1_VDM_SRAM_BASE (0x00000600U)
> +#define HWD_VIIF_L1_VDM_SRAM_SIZE (0x00000020U)
> +#define HWD_VIIF_L1_VDM_DPC_TABLE_SIZE (0x2000U)
> +#define HWD_VIIF_L1_VDM_LSC_TABLE_SIZE (0x600U)
> +#define HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL (4095U)
> +#define HWD_VIIF_L1_PWHB_MAX_GAIN_VAL (0x80000U)
> +#define HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL (63U)
> +#define HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL (31U)
> +#define HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL (3U)
> +#define HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL (256U)
> +#define HWD_VIIF_L1_RCNR_MAX_BLEND_VAL (16U)
> +#define HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL (64U)
> +#define HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL (4U)
> +#define HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL (16U)
> +#define HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL (32U)
> +#define HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL (2U)
> +#define HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO (15U)
> +#define HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO (0x400U)
> +#define HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO (0x400000U)
> +#define HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL (0x400000U)
> +#define HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL (0xffffffU)
> +#define HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL (4095U)
> +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL (0xffffffU)
> +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL (0x100000U)
> +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL (0xffffffU)
> +#define HWD_VIIF_LSC_MIN_GAIN (-4096)
> +#define HWD_VIIF_LSC_MAX_GAIN (4096)
> +#define HWD_VIIF_LSC_GRID_MIN_COORDINATE (1U)
> +#define HWD_VIIF_LSC_PWB_MAX_COEF_VAL (0x800U)
> +#define HWD_VIIF_DAMP_MAX_LSBSEL (15U)
> +#define HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL (0xffffffU)
> +#define HWD_VIIF_AWB_MIN_GAIN (64U)
> +#define HWD_VIIF_AWB_MAX_GAIN (1024U)
> +#define HWD_VIIF_AWB_GATE_LOWER (-127)
> +#define HWD_VIIF_AWB_GATE_UPPER (127)
> +#define HWD_VIIF_AWB_UNSIGNED_GATE_UPPER (127U)
> +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED (15U)
> +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL (31U)
> +#define HWD_VIIF_AWB_INTEGRATION_STOP_TH (1023U)
> +#define HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL (8U)
> +#define HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH (10U)
> +#define HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH (24U)
> +#define HWD_VIIF_L1_HDRC_MAX_PT_SLOPE (13U)
> +#define HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO (256U)
> +#define HWD_VIIF_L1_HDRC_MAX_FLARE_VAL (0xffffffU)
> +#define HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA (16U)
> +#define HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO (0x400000U)
> +#define HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION (0x4000U)
> +#define HWD_VIIF_L1_HDRC_RATIO_OFFSET (10U)
> +#define HWD_VIIF_L1_GAMMA_MAX_VAL (8191U)
> +#define HWD_VIIF_L1_SUPPRESSION_MAX_VAL (0x4000U)
> +#define HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT (15U)
> +#define HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN (0x1000U)
> +#define HWD_VIIF_L1_AEXP_MAX_WEIGHT (3U)
> +#define HWD_VIIF_L1_AEXP_MAX_BLOCK_TH (256U)
> +#define HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH (0xffffffU)
> +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH (64U)
> +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT (64U)
> +#define HWD_VIIF_L1_HIST_COLOR_RGBY (2U)
> +#define HWD_VIIF_L1_HIST_MAX_BLOCK_NUM (8U)
> +#define HWD_VIIF_L1_HIST_MAX_STEP (15U)
> +#define HWD_VIIF_L1_HIST_MAX_BIN_SHIFT (31U)
> +#define HWD_VIIF_L1_HIST_MAX_COEF (65536U)
> +#define HWD_VIIF_L1_HIST_MIN_ADD_B_COEF (-65536)
> +#define HWD_VIIF_L1_HIST_MIN_ADD_A_COEF (-16777216)
> +#define HWD_VIIF_L1_HIST_MAX_ADD_A_COEF (16777216)
> +#define HWD_VIIF_L1_HIST_VDM_SIZE (4096U)
> +#define HWD_VIIF_L1_HIST_VDM_SRAM_BASE (0x00000400U)
> +#define HWD_VIIF_L1_HIST_VDM_SRAM_SIZE (0x00000040U)
> +#define HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT (0x0200U)
> +#define HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT (0x10BFU)
> +#define HWD_VIIF_L1_COEF_MIN (256U)
> +#define HWD_VIIF_L1_COEF_MAX (65024U)
> +
> +/* constants for L2 ISP */
> +#define HWD_VIIF_L2_VDM_ALIGN (0x4U)
> +#define HWD_VIIF_L2_VDM_GRID_SRAM_BASE (0x00000620U)
> +#define HWD_VIIF_L2_VDM_GRID_SRAM_SIZE (0x00000020U)
> +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE (0x00000640U)
> +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE (0x00000020U)
> +#define HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE (0x00000200U)
> +#define HWD_VIIF_L2_UNDIST_POLY_NUM (11U)
> +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H (-4296)
> +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H (4296)
> +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V (-2360)
> +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V (2360)
> +#define HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE (1677721U)
> +#define HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2 (0x4000000U)
> +#define HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA (0x800U)
> +#define HWD_VIIF_L2_UNDIST_MIN_POLY_COEF (-2147352576)
> +#define HWD_VIIF_L2_UNDIST_MAX_POLY_COEF (2147352576)
> +#define HWD_VIIF_L2_UNDIST_MIN_GRID_NUM (16U)
> +#define HWD_VIIF_L2_UNDIST_MAX_GRID_NUM (64U)
> +#define HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM (2048U)
> +#define HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV (0x800000U)
> +#define HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE (0x400U)
> +#define HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE (0x2000U)
> +#define HWD_VIIF_L2_ROI_MIN_NUM (1U)
> +#define HWD_VIIF_L2_ROI_MAX_NUM (2U)
> +#define HWD_VIIF_L2_ROI_MIN_SCALE (32768U)
> +#define HWD_VIIF_L2_ROI_MAX_SCALE (131072U)
> +#define HWD_VIIF_L2_ROI_MIN_SCALE_INV (32768U)
> +#define HWD_VIIF_L2_ROI_MAX_SCALE_INV (131072U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE (8190U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE (4094U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE (8190U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE (4094U)
> +#define HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT (0x1CU)
> +#define HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT (0x1FU)
> +#define HWD_VIIF_L2_ROI_NONE (3U)
> +#define HWD_VIIF_MAX_POST_NUM (2U)
> +#define HWD_VIIF_L2_INPUT_OTHER_CH (0x50U)
> +
> +/**
> + * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
> + *
> + * @roi_num: the number of ROIs which are used.
> + * @post_enable_flag: flag to show which of POST is enabled.
> + * @post_crop_x: CROP x of each L2ISP POST
> + * @post_crop_y: CROP y of each L2ISP POST
> + * @post_crop_w: CROP w of each L2ISP POST
> + * @post_crop_h: CROP h of each L2ISP POST
> + */
> +struct hwd_viif_l2_roi_path_info {
> + u32 roi_num;
> + bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_res - driver internal resource structure
> + *
> + * @clock_id: clock ID of each unit
> + * @csi2_clock_id: clock ID of CSI-2 RX
> + * @csi2_reset_id: reset ID of CSI-2 RX
> + * @pixel_clock: pixel clock
> + * @htotal_size: horizontal total size
> + * @dt_image_main_w_isp: Data type of image data for ISP path
> + * @csi2host_reg: pointer to register access structure of CSI-2 RX host controller
> + * @capture_reg: pointer to register access structure of capture unit
> + * @l2_roi_path_info: ROI path information of L2ISP
> + * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
> + */
> +struct hwd_viif_res {
> + //u32 clock_id;
> + //u32 csi2_clock_id;
> + //u32 csi2_reset_id;
These are commented out, but they are still present in the kerneldoc above.
Any reason why these three fields aren't just removed?
> + u32 pixel_clock;
> + u32 htotal_size;
> + u32 dt_image_main_w_isp;
> + struct hwd_viif_csi2host_reg *csi2host_reg;
> + struct hwd_viif_capture_reg *capture_reg;
> + struct hwd_viif_l2_roi_path_info l2_roi_path_info;
> + bool run_flag_main;
> +};
> +
> +/**
> + * struct hwd_viif_dphy_hs_info - dphy hs information
> + *
> + * @rate: Data rate [Mbps]
> + * @hsfreqrange: IP operating frequency(hsfreqrange)
> + * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
> + */
> +struct hwd_viif_dphy_hs_info {
> + u32 rate;
> + u32 hsfreqrange;
> + u32 osc_freq_target;
> +};
> +
> +#endif /* HWD_VIIF_INTERNAL_H */
<snip>
> diff --git a/include/uapi/linux/visconti_viif.h b/include/uapi/linux/visconti_viif.h
> new file mode 100644
> index 00000000000..f92278425b7
> --- /dev/null
> +++ b/include/uapi/linux/visconti_viif.h
> @@ -0,0 +1,1724 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef __UAPI_VISCONTI_VIIF_H_
> +#define __UAPI_VISCONTI_VIIF_H_
> +
> +#include <linux/types.h>
> +#include <linux/videodev2.h>
> +
> +/* Visconti specific compound controls */
> +#define V4L2_CID_VISCONTI_VIIF_BASE (V4L2_CID_USER_BASE + 0x1000)
You need to reserve a range for Visconti controls in the v4l2-controls.h header.
See e.g. V4L2_CID_USER_DW100_BASE. That ensures that these controls have unique
IDs, not used by other drivers.
> +#define V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 1)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 2)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF (V4L2_CID_VISCONTI_VIIF_BASE + 3)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 4)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG (V4L2_CID_VISCONTI_VIIF_BASE + 5)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE (V4L2_CID_VISCONTI_VIIF_BASE + 6)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION (V4L2_CID_VISCONTI_VIIF_BASE + 7)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC (V4L2_CID_VISCONTI_VIIF_BASE + 8)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE (V4L2_CID_VISCONTI_VIIF_BASE + 9)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION \
> + (V4L2_CID_VISCONTI_VIIF_BASE + 10)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS (V4L2_CID_VISCONTI_VIIF_BASE + 11)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION (V4L2_CID_VISCONTI_VIIF_BASE + 12)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC (V4L2_CID_VISCONTI_VIIF_BASE + 13)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS (V4L2_CID_VISCONTI_VIIF_BASE + 14)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB (V4L2_CID_VISCONTI_VIIF_BASE + 15)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN (V4L2_CID_VISCONTI_VIIF_BASE + 16)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC (V4L2_CID_VISCONTI_VIIF_BASE + 17)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM (V4L2_CID_VISCONTI_VIIF_BASE + 18)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 19)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT (V4L2_CID_VISCONTI_VIIF_BASE + 20)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION (V4L2_CID_VISCONTI_VIIF_BASE + 21)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST (V4L2_CID_VISCONTI_VIIF_BASE + 22)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI (V4L2_CID_VISCONTI_VIIF_BASE + 23)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 24)
> +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 25)
> +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 26)
> +#define V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 27)
> +#define V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS (V4L2_CID_VISCONTI_VIIF_BASE + 28)
These controls need to be documented: what do they do, what arguments do they have.
Take a look at v4l2-controls.h, for example the V4L2_CID_STATELESS_VP9_COMPRESSED_HDR
define. The data structure it takes is just above the CID define, so it is already
much easier to see what the control takes as value.
But in this case it needs a bit more since these controls are not documented in the
V4L2 spec, so you will have to do that here as well. I.e., describe what the control does.
Does the driver configure these controls to sensible default values when it is
first loaded?
Also, if there is public documentation available, then add a URL to it at the top of
this header.
> +
> +/* Enable/Disable flag */
> +#define VIIF_DISABLE (0U)
> +#define VIIF_ENABLE (1U)
> +
> +/**
> + * enum viif_rawpack_mode - RAW pack mode for ioctl(VIDIOC_VIIF_MAIN_SET_RAWPACK_MODE)
> + *
> + * @VIIF_RAWPACK_DISABLE: RAW pack disable
> + * @VIIF_RAWPACK_MSBFIRST: RAW pack enable (MSB First)
> + * @VIIF_RAWPACK_LSBFIRST: RAW pack enable (LSB First)
> + */
> +enum viif_rawpack_mode {
> + VIIF_RAWPACK_DISABLE = 0,
> + VIIF_RAWPACK_MSBFIRST = 2,
> + VIIF_RAWPACK_LSBFIRST = 3,
> +};
> +
> +/**
> + * enum viif_l1_input - L1ISP preprocessing mode
> + *
> + * @VIIF_L1_INPUT_HDR: bypass(HDR input)
> + * @VIIF_L1_INPUT_PWL: HDRE(PWL input)
> + * @VIIF_L1_INPUT_HDR_IMG_CORRECT: SLIC-ABPC-PWHB-RCNR-HDRS
> + * @VIIF_L1_INPUT_PWL_IMG_CORRECT: HDRE-SLIC-ABPC-PWHB-RCNR-HDRS
> + */
> +enum viif_l1_input {
> + VIIF_L1_INPUT_HDR = 0,
> + VIIF_L1_INPUT_PWL = 1,
> + VIIF_L1_INPUT_HDR_IMG_CORRECT = 3,
> + VIIF_L1_INPUT_PWL_IMG_CORRECT = 4,
> +};
> +
> +/**
> + * enum viif_l1_raw - L1ISP RAW color filter mode
> + *
> + * @VIIF_L1_RAW_GR_R_B_GB: Gr-R-B-Gb
> + * @VIIF_L1_RAW_R_GR_GB_B: R-Gr-Gb-B
> + * @VIIF_L1_RAW_B_GB_GR_R: B-Gb-Gr-R
> + * @VIIF_L1_RAW_GB_B_R_GR: Gb-B-R-Gr
> + */
> +enum viif_l1_raw {
> + VIIF_L1_RAW_GR_R_B_GB = 0,
> + VIIF_L1_RAW_R_GR_GB_B = 1,
> + VIIF_L1_RAW_B_GB_GR_R = 2,
> + VIIF_L1_RAW_GB_B_R_GR = 3,
> +};
> +
> +/**
> + * struct viif_l1_input_mode_config - L1ISP INPUT MODE parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE`
> + * @mode: &enum viif_l1_input value.
> + * @depth: Color depth (even only). Range for each L1ISP pre-processing mode is:
> + *
> + * * VIIF_L1_INPUT_HDR/HDR_IMG_CORRECT: Range: [8..24].
> + * * VIIF_L1_INPUT_PWL/PWL_IMG_CORRECT: Range: [8..14].
> + * @raw_color_filter: &enum viif_l1_raw value.
> + */
> +struct viif_l1_input_mode_config {
> + __u32 mode;
> + __u32 depth;
> + __u32 raw_color_filter;
> +};
> +
> +/**
> + * struct viif_l1_rgb_to_y_coef_config - L1ISP coefficient for calculating
> + * Y from RGB parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF`
> + * @coef_r: R co-efficient [256..65024] accuracy: 1/65536
> + * @coef_g: R co-efficient [256..65024] accuracy: 1/65536
> + * @coef_b: R co-efficient [256..65024] accuracy: 1/65536
> + */
> +struct viif_l1_rgb_to_y_coef_config {
> + __u16 coef_r;
> + __u16 coef_g;
> + __u16 coef_b;
> +};
> +
> +/**
> + * enum viif_l1_img_sensitivity_mode - L1ISP image sensitivity
> + *
> + * @VIIF_L1_IMG_SENSITIVITY_HIGH: high sensitivity
> + * @VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED: middle sensitivity or led
> + * @VIIF_L1_IMG_SENSITIVITY_LOW: low sensitivity
> + */
> +enum viif_l1_img_sensitivity_mode {
> + VIIF_L1_IMG_SENSITIVITY_HIGH = 0,
> + VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED = 1,
> + VIIF_L1_IMG_SENSITIVITY_LOW = 2,
> +};
> +
> +/**
> + * struct viif_l1_ag_mode_config - L1ISP AG mode parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE`
> + * @sysm_ag_grad: Analog gain slope [0..255] (element is id)
> + * @sysm_ag_ofst: Analog gain offset [0..65535] (element is id)
> + * @sysm_ag_cont_hobc_en_high: 1:enable/0:disable to control analog gain
> + * for high sensitivity image of OBCC
> + * @sysm_ag_psel_hobc_high: Analog gain id for high sensitivity image of OBCC [0..3]
> + * @sysm_ag_cont_hobc_en_middle_led: 1:enable/0:disable to control analog gain
> + * for middle sensitivity or LED image of OBCC
> + * @sysm_ag_psel_hobc_middle_led: Analog gain id for middle sensitivity
> + * or LED image of OBCC [0..3]
> + * @sysm_ag_cont_hobc_en_low: 1:enable/0:disable to control analog gain
> + * for low sensitivity image of OBCC
> + * @sysm_ag_psel_hobc_low: Analog gain id for low sensitivity image of OBCC [0..3]
> + * @sysm_ag_cont_abpc_en_high: 1:enable/0:disable to control analog gain
> + * for high sensitivity image of ABPC
> + * @sysm_ag_psel_abpc_high: Analog gain id for high sensitivity image of ABPC [0..3]
> + * @sysm_ag_cont_abpc_en_middle_led: 1:enable/0:disable to control analog gain
> + * for middle sensitivity or LED image of ABPC
> + * @sysm_ag_psel_abpc_middle_led: Analog gain id for middle sensitivity
> + * or LED image of ABPC [0..3]
> + * @sysm_ag_cont_abpc_en_low: 1:enable/0:disable to control analog gain
> + * for low sensitivity image of ABPC
> + * @sysm_ag_psel_abpc_low: Analog gain id for low sensitivity image of ABPC [0..3]
> + * @sysm_ag_cont_rcnr_en_high: 1:enable/0:disable to control analog gain
> + * for high sensitivity image of RCNR
> + * @sysm_ag_psel_rcnr_high: Analog gain id for high sensitivity image of RCNR [0..3]
> + * @sysm_ag_cont_rcnr_en_middle_led: 1:enable/0:disable to control analog gain
> + * for middle sensitivity or LED image of RCNR
> + * @sysm_ag_psel_rcnr_middle_led: Analog gain id for middle sensitivity
> + * or LED image of RCNR [0..3]
> + * @sysm_ag_cont_rcnr_en_low: 1:enable/0:disable to control analog gain
> + * for low sensitivity image of RCNR
> + * @sysm_ag_psel_rcnr_low: Analog gain id for low sensitivity image of RCNR [0..3]
> + * @sysm_ag_cont_lssc_en: 1:enable/0:disable to control analog gain for LSC
> + * @sysm_ag_ssel_lssc: &enum viif_l1_img_sensitivity_mode value. Sensitive image used for LSC.
> + * @sysm_ag_psel_lssc: Analog gain id for LSC [0..3]
> + * @sysm_ag_cont_mpro_en: 1:enable/0:disable to control analog gain for color matrix
> + * @sysm_ag_ssel_mpro: &enum viif_l1_img_sensitivity_mode value.
> + * Sensitive image used for color matrix.
> + * @sysm_ag_psel_mpro:Aanalog gain id for color matrix [0..3]
> + * @sysm_ag_cont_vpro_en: 1:enable/0:disable to control analog gain for image adjustment
> + * @sysm_ag_ssel_vpro: &enum viif_l1_img_sensitivity_mode value.
> + * Sensitive image used for image adjustment.
> + * @sysm_ag_psel_vpro: Analog gain id for image adjustment [0..3]
> + * @sysm_ag_cont_hobc_test_high: Manual analog gain for high sensitivity image
> + * of OBCC [0..255]
> + * @sysm_ag_cont_hobc_test_middle_led: Manual analog gain for middle sensitivity
> + * or led image of OBCC [0..255]
> + * @sysm_ag_cont_hobc_test_low: Manual analog gain for low sensitivity image
> + * of OBCC [0..255]
> + * @sysm_ag_cont_abpc_test_high: Manual analog gain for high sensitivity image
> + * of ABPC [0..255]
> + * @sysm_ag_cont_abpc_test_middle_led: Manual analog gain for middle sensitivity
> + * or led image of ABPC [0..255]
> + * @sysm_ag_cont_abpc_test_low: Manual analog gain for low sensitivity image
> + * of ABPC [0..255]
> + * @sysm_ag_cont_rcnr_test_high: Manual analog gain for high sensitivity image
> + * of RCNR [0..255]
> + * @sysm_ag_cont_rcnr_test_middle_led: Manual analog gain for middle sensitivity
> + * or led image of RCNR [0..255]
> + * @sysm_ag_cont_rcnr_test_low: Manual analog gain for low sensitivity image
> + * of RCNR [0..255]
> + * @sysm_ag_cont_lssc_test: Manual analog gain for LSSC [0..255]
> + * @sysm_ag_cont_mpro_test: Manual analog gain for color matrix [0..255]
> + * @sysm_ag_cont_vpro_test: Manual analog gain for image adjustment [0..255]
> + *
> + * Operation setting of L1ISP analog gain function.
> + * Analog gain control is disabled if following settings are done.
> + * "sysm_ag_cont_*_en = DRV_VIIF_DISABLE" and "sysm_ag_cont_*_test = 0"
> + * In case "VIIF_L1_INPUT_HDR" or "VIIF_L1_INPUT_PWL" is set to "mode" which is
> + * an &struct viif_l1_input_mode_config, analog gain control needs to be disabled.
> + * Even if this condition is not satisfied, this driver doesn't return error.
> + *
> + * The value set in sysm_ag_psel_xxx indicates analog gain system to be used and
> + * corresponds to the element number of sysm_ag_grad and sysm_ag_ofst.
> + * For example, if sysm_ag_psel_hobc_high is set to 2, then values set in
> + * sysm_ag_grad[2] and sysm_ag_ofst[2] are used for high sensitivity images
> + * in OBCC processing.
> + */
> +struct viif_l1_ag_mode_config {
> + __u8 sysm_ag_grad[4];
> + __u16 sysm_ag_ofst[4];
> + __u32 sysm_ag_cont_hobc_en_high;
> + __u32 sysm_ag_psel_hobc_high;
> + __u32 sysm_ag_cont_hobc_en_middle_led;
> + __u32 sysm_ag_psel_hobc_middle_led;
> + __u32 sysm_ag_cont_hobc_en_low;
> + __u32 sysm_ag_psel_hobc_low;
> + __u32 sysm_ag_cont_abpc_en_high;
> + __u32 sysm_ag_psel_abpc_high;
> + __u32 sysm_ag_cont_abpc_en_middle_led;
> + __u32 sysm_ag_psel_abpc_middle_led;
> + __u32 sysm_ag_cont_abpc_en_low;
> + __u32 sysm_ag_psel_abpc_low;
> + __u32 sysm_ag_cont_rcnr_en_high;
> + __u32 sysm_ag_psel_rcnr_high;
> + __u32 sysm_ag_cont_rcnr_en_middle_led;
> + __u32 sysm_ag_psel_rcnr_middle_led;
> + __u32 sysm_ag_cont_rcnr_en_low;
> + __u32 sysm_ag_psel_rcnr_low;
> + __u32 sysm_ag_cont_lssc_en;
> + __u32 sysm_ag_ssel_lssc;
> + __u32 sysm_ag_psel_lssc;
> + __u32 sysm_ag_cont_mpro_en;
> + __u32 sysm_ag_ssel_mpro;
> + __u32 sysm_ag_psel_mpro;
> + __u32 sysm_ag_cont_vpro_en;
> + __u32 sysm_ag_ssel_vpro;
> + __u32 sysm_ag_psel_vpro;
> + __u8 sysm_ag_cont_hobc_test_high;
> + __u8 sysm_ag_cont_hobc_test_middle_led;
> + __u8 sysm_ag_cont_hobc_test_low;
> + __u8 sysm_ag_cont_abpc_test_high;
> + __u8 sysm_ag_cont_abpc_test_middle_led;
> + __u8 sysm_ag_cont_abpc_test_low;
> + __u8 sysm_ag_cont_rcnr_test_high;
> + __u8 sysm_ag_cont_rcnr_test_middle_led;
> + __u8 sysm_ag_cont_rcnr_test_low;
> + __u8 sysm_ag_cont_lssc_test;
> + __u8 sysm_ag_cont_mpro_test;
> + __u8 sysm_ag_cont_vpro_test;
> +};
> +
> +/**
> + * struct viif_l1_ag_config - L1ISP AG parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG`
> + * @gain_h: Analog gain for high sensitive image [0..65535]
> + * @gain_m: Analog gain for middle sensitive image or LED image [0..65535]
> + * @gain_l: Analog gain for low sensitive image [0..65535]
> + */
> +struct viif_l1_ag_config {
> + __u16 gain_h;
> + __u16 gain_m;
> + __u16 gain_l;
> +};
> +
> +/**
> + * struct viif_l1_hdre_config - L1ISP HDRE parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE`
> + * @hdre_src_point: Knee point N value of PWL compressed signal [0..0x3FFF]
> + * @hdre_dst_base: Offset value of HDR signal in Knee area M [0..0xFFFFFF]
> + * @hdre_ratio: Slope of output pixel value in Knee area M
> + * [0..0x3FFFFF], accuracy: 1/64
> + * @hdre_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
> + */
> +struct viif_l1_hdre_config {
> + __u32 hdre_src_point[16];
> + __u32 hdre_dst_base[17];
> + __u32 hdre_ratio[17];
> + __u32 hdre_dst_max_val;
> +};
> +
> +/**
> + * struct viif_l1_img_extraction_config - L1ISP image extraction parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION`
> + * @input_black_gr: Black level of input pixel (Gr) [0..0xFFFFFF]
> + * @input_black_r: Black level of input pixel (R) [0..0xFFFFFF]
> + * @input_black_b: Black level of input pixel (B) [0..0xFFFFFF]
> + * @input_black_gb: Black level of input pixel (Gb) [0..0xFFFFFF]
> + */
> +struct viif_l1_img_extraction_config {
> + __u32 input_black_gr;
> + __u32 input_black_r;
> + __u32 input_black_b;
> + __u32 input_black_gb;
> +};
> +
> +/**
> + * enum viif_l1_dpc_mode - L1ISP defect pixel correction mode
> + * @VIIF_L1_DPC_1PIXEL: 1 pixel correction mode
> + * @VIIF_L1_DPC_2PIXEL: 2 pixel correction mode
> + */
> +enum viif_l1_dpc_mode {
> + VIIF_L1_DPC_1PIXEL = 0,
> + VIIF_L1_DPC_2PIXEL = 1,
> +};
> +
> +/**
> + * struct viif_l1_dpc - L1ISP defect pixel correction parameters
> + * for &struct viif_l1_dpc_config
> + * @abpc_sta_en: 1:enable/0:disable setting of Static DPC
> + * @abpc_dyn_en: 1:enable/0:disable setting of Dynamic DPC
> + * @abpc_dyn_mode: &enume viif_l1_dpc_mode value. Sets dynamic DPC mode.
> + * @abpc_ratio_limit: Variation adjustment of dynamic DPC [0..1023]
> + * @abpc_dark_limit: White defect judgment limit of dark area [0..1023]
> + * @abpc_sn_coef_w_ag_min: Luminance difference adjustment of white DPC
> + * (undere lower threshold) [1..31]
> + * @abpc_sn_coef_w_ag_mid: Luminance difference adjustment of white DPC
> + * (between lower and upper threshold) [1..31]
> + * @abpc_sn_coef_w_ag_max: Luminance difference adjustment of white DPC
> + * (over upper threshold) [1..31]
> + * @abpc_sn_coef_b_ag_min: Luminance difference adjustment of black DPC
> + * (undere lower threshold) [1..31]
> + * @abpc_sn_coef_b_ag_mid: Luminance difference adjustment of black DPC
> + * (between lower and upper threshold) [1..31]
> + * @abpc_sn_coef_b_ag_max: Luminance difference adjustment of black DPC
> + * (over upper threshold) [1..31]
> + * @abpc_sn_coef_w_th_min: Luminance difference adjustment of white DPC
> + * analog gain lower threshold [0..255]
> + * @abpc_sn_coef_w_th_max: Luminance difference adjustment of white DPC
> + * analog gain upper threshold [0..255]
> + * @abpc_sn_coef_b_th_min: Luminance difference adjustment of black DPC
> + * analog gain lower threshold [0..255]
> + * @abpc_sn_coef_b_th_max: Luminance difference adjustment of black DPC
> + * analog gain upper threshold [0..255]
> + *
> + * Parameters should meet the following conditions.
> + * "abpc_sn_coef_w_th_min < abpc_sn_coef_w_th_max" and
> + * "abpc_sn_coef_b_th_min < abpc_sn_coef_b_th_max"
> + */
> +struct viif_l1_dpc {
> + __u32 abpc_sta_en;
> + __u32 abpc_dyn_en;
> + __u32 abpc_dyn_mode;
> + __u32 abpc_ratio_limit;
> + __u32 abpc_dark_limit;
> + __u32 abpc_sn_coef_w_ag_min;
> + __u32 abpc_sn_coef_w_ag_mid;
> + __u32 abpc_sn_coef_w_ag_max;
> + __u32 abpc_sn_coef_b_ag_min;
> + __u32 abpc_sn_coef_b_ag_mid;
> + __u32 abpc_sn_coef_b_ag_max;
> + __u8 abpc_sn_coef_w_th_min;
> + __u8 abpc_sn_coef_w_th_max;
> + __u8 abpc_sn_coef_b_th_min;
> + __u8 abpc_sn_coef_b_th_max;
> +};
> +
> +/**
> + * struct viif_l1_dpc_config - L1ISP defect pixel correction parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC`
> + * @param_h: DPC parameter for high sensitive image. Refer to &struct viif_l1_dpc
> + * @param_m: DPC parameter for middle sensitive image. Refer to &struct viif_l1_dpc
> + * @param_l: DPC parameter for low sensitive image. Refer to &struct viif_l1_dpc
> + * @table_h_addr: DPC table address for high sensitive image.
> + * The table size is sizeof(u32) * 2048.
> + * Set zero to disable this table.
Addresses in a control struct? Sounds iffy, but I'll comment more on it when I review
the control code.
> + * @table_m_addr: DPC table address for middle sensitive image or LED image.
> + * The table size is sizeof(u32) * 2048.
> + * Set zero to disable this table.
> + * @table_l_addr: DPC table address for low sensitive image.
> + * The table size is sizeof(u32) * 2048.
> + * Set zero to disable this table.
> + *
> + * The size of each table is fixed at 8192 Byte.
> + * Application should make sure that the table data is based on HW specification
> + * since this driver does not check the DPC table.
> + */
> +struct viif_l1_dpc_config {
> + struct viif_l1_dpc param_h;
> + struct viif_l1_dpc param_m;
> + struct viif_l1_dpc param_l;
> + __u64 table_h_addr;
> + __u64 table_m_addr;
> + __u64 table_l_addr;
> +};
> +
> +/**
> + * struct viif_l1_preset_wb - L1ISP preset white balance parameters
> + * for &struct viif_l1_preset_white_balance_config
> + * @gain_gr: Gr gain [0..524287], accuracy 1/16384
> + * @gain_r: R gain [0..524287], accuracy 1/16384
> + * @gain_b: B gain [0..524287], accuracy 1/16384
> + * @gain_gb: Gb gain [0..524287], accuracy 1/16384
> + */
> +struct viif_l1_preset_wb {
> + __u32 gain_gr;
> + __u32 gain_r;
> + __u32 gain_b;
> + __u32 gain_gb;
> +};
> +
> +/**
> + * struct viif_l1_preset_white_balance_config - L1ISP preset white balance
> + * parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE`
> + * @dstmaxval: Maximum value of output pixel [pixel] [0..4095]
> + * @param_h: Preset white balance parameter for high sensitive image.
> + * Refer to &struct viif_l1_preset_wb
> + * @param_m: Preset white balance parameters for middle sensitive image or LED image.
> + * Refer to &struct viif_l1_preset_wb
> + * @param_l: Preset white balance parameters for low sensitive image.
> + * Refer to &struct viif_l1_preset_wb
> + */
> +struct viif_l1_preset_white_balance_config {
> + __u32 dstmaxval;
> + struct viif_l1_preset_wb param_h;
> + struct viif_l1_preset_wb param_m;
> + struct viif_l1_preset_wb param_l;
> +};
> +
> +/**
> + * enum viif_l1_rcnr_type - L1ISP high resolution luminance filter type
> + *
> + * @VIIF_L1_RCNR_LOW_RESOLUTION: low resolution
> + * @VIIF_L1_RCNR_MIDDLE_RESOLUTION: middle resolution
> + * @VIIF_L1_RCNR_HIGH_RESOLUTION: high resolution
> + * @VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION: ultra high resolution
> + */
> +enum viif_l1_rcnr_type {
> + VIIF_L1_RCNR_LOW_RESOLUTION = 0,
> + VIIF_L1_RCNR_MIDDLE_RESOLUTION = 1,
> + VIIF_L1_RCNR_HIGH_RESOLUTION = 2,
> + VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION = 3,
> +};
> +
> +/**
> + * enum viif_l1_msf_blend_ratio - L1ISP MSF blend ratio
> + *
> + * @VIIF_L1_MSF_BLEND_RATIO_0_DIV_64: 0/64
> + * @VIIF_L1_MSF_BLEND_RATIO_1_DIV_64: 1/64
> + * @VIIF_L1_MSF_BLEND_RATIO_2_DIV_64: 2/64
> + */
> +enum viif_l1_msf_blend_ratio {
> + VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 = 0,
> + VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 = 1,
> + VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 = 2,
> +};
> +
> +/**
> + * struct viif_l1_raw_color_noise_reduction - L1ISP RCNR parameters
> + * for &struct viif_l1_raw_color_noise_reduction_config
> + * @rcnr_sw: 1:Enable/0:Disable setting of RAW color noise reduction
> + * @rcnr_cnf_dark_ag0: Maximum value of LSF dark noise adjustment[0..63]
> + * @rcnr_cnf_dark_ag1: Middle value of LSF dark noise adjustment [0..63]
> + * @rcnr_cnf_dark_ag2: Minimum value of LSF dark noise adjustment [0..63]
> + * @rcnr_cnf_ratio_ag0: Maximum value of LSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_cnf_ratio_ag1: Middle value of LSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_cnf_ratio_ag2: Minimum value of LSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_cnf_clip_gain_r: LSF color correction limit adjustment gain R [0..3]
> + * @rcnr_cnf_clip_gain_g: LSF color correction limit adjustment gain G [0..3]
> + * @rcnr_cnf_clip_gain_b: LSF color correction limit adjustment gain B [0..3]
> + * @rcnr_a1l_dark_ag0: Maximum value of MSF dark noise adjustment [0..63]
> + * @rcnr_a1l_dark_ag1: Middle value of MSF dark noise adjustment [0..63]
> + * @rcnr_a1l_dark_ag2: Minimum value of MSF dark noise adjustment [0..63]
> + * @rcnr_a1l_ratio_ag0: Maximum value of MSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_a1l_ratio_ag1: Middle value of MSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_a1l_ratio_ag2: Minimum value of MSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_inf_zero_clip: Input stage zero clip setting [0..256]
> + * @rcnr_merge_d2blend_ag0: Maximum value of filter results and input blend ratio [0..16]
> + * @rcnr_merge_d2blend_ag1: Middle value of filter results and input blend ratio [0..16]
> + * @rcnr_merge_d2blend_ag2: Minimum value of filter results and input blend ratio [0..16]
> + * @rcnr_merge_black: Black level minimum value [0..64]
> + * @rcnr_merge_mindiv: 0 div guard value of inverse arithmetic unit [4..16]
> + * @rcnr_hry_type: &enum viif_l1_rcnr_type value. Filter type for HSF filter process.
> + * @rcnr_anf_blend_ag0: &enum viif_l1_msf_blend_ratio value.
> + * Maximum value of MSF result blend ratio in write back data to line memory.
> + * @rcnr_anf_blend_ag1: &enum viif_l1_msf_blend_ratio value.
> + * Middle value of MSF result blend ratio in write back data to line memory.
> + * @rcnr_anf_blend_ag2: &enum viif_l1_msf_blend_ratio value.
> + * Minimum value of MSF result blend ratio in write back data to line memory.
> + * @rcnr_lpf_threshold: Multiplier value for calculating dark noise / luminance
> + * interlock noise of MSF [0..31], accuracy: 1/8
> + * @rcnr_merge_hlblend_ag0: Maximum value of luminance signal generation blend [0..2]
> + * @rcnr_merge_hlblend_ag1: Middle value of luminance signal generation blend [0..2]
> + * @rcnr_merge_hlblend_ag2: Minimum value of luminance signal generation blend [0..2]
> + * @rcnr_gnr_sw: 1:Enable/0:Disable setting of Gr/Gb sensitivity ratio
> + * correction function switching
> + * @rcnr_gnr_ratio: Upper limit of Gr/Gb sensitivity ratio correction factor [0..15]
> + * @rcnr_gnr_wide_en: 1:Enable/0:Disable setting of the function to double
> + * correction upper limit ratio of rcnr_gnr_ratio
> + */
> +struct viif_l1_raw_color_noise_reduction {
> + __u32 rcnr_sw;
> + __u32 rcnr_cnf_dark_ag0;
> + __u32 rcnr_cnf_dark_ag1;
> + __u32 rcnr_cnf_dark_ag2;
> + __u32 rcnr_cnf_ratio_ag0;
> + __u32 rcnr_cnf_ratio_ag1;
> + __u32 rcnr_cnf_ratio_ag2;
> + __u32 rcnr_cnf_clip_gain_r;
> + __u32 rcnr_cnf_clip_gain_g;
> + __u32 rcnr_cnf_clip_gain_b;
> + __u32 rcnr_a1l_dark_ag0;
> + __u32 rcnr_a1l_dark_ag1;
> + __u32 rcnr_a1l_dark_ag2;
> + __u32 rcnr_a1l_ratio_ag0;
> + __u32 rcnr_a1l_ratio_ag1;
> + __u32 rcnr_a1l_ratio_ag2;
> + __u32 rcnr_inf_zero_clip;
> + __u32 rcnr_merge_d2blend_ag0;
> + __u32 rcnr_merge_d2blend_ag1;
> + __u32 rcnr_merge_d2blend_ag2;
> + __u32 rcnr_merge_black;
> + __u32 rcnr_merge_mindiv;
> + __u32 rcnr_hry_type;
> + __u32 rcnr_anf_blend_ag0;
> + __u32 rcnr_anf_blend_ag1;
> + __u32 rcnr_anf_blend_ag2;
> + __u32 rcnr_lpf_threshold;
> + __u32 rcnr_merge_hlblend_ag0;
> + __u32 rcnr_merge_hlblend_ag1;
> + __u32 rcnr_merge_hlblend_ag2;
> + __u32 rcnr_gnr_sw;
> + __u32 rcnr_gnr_ratio;
> + __u32 rcnr_gnr_wide_en;
> +};
> +
> +/**
> + * struct viif_l1_raw_color_noise_reduction_config - L1ISP RCNR parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION`
> + * @param_h: RAW color noise reduction parameter for high sensitive image.
> + * Refer to &struct viif_l1_raw_color_noise_reduction
> + * @param_m: RAW color noise reduction parameter for middle sensitive image or LED image.
> + * Refer to &struct viif_l1_raw_color_noise_reduction
> + * @param_l: RAW color noise reduction parameter for low sensitive image.
> + * Refer to &struct viif_l1_raw_color_noise_reduction
> + */
> +struct viif_l1_raw_color_noise_reduction_config {
> + struct viif_l1_raw_color_noise_reduction param_h;
> + struct viif_l1_raw_color_noise_reduction param_m;
> + struct viif_l1_raw_color_noise_reduction param_l;
> +};
> +
> +/**
> + * enum viif_l1_hdrs_middle_img_mode - L1ISP HDR setting
> + *
> + * @VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE: not use middle image
> + * @VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE: use middle image
> + */
> +enum viif_l1_hdrs_middle_img_mode {
> + VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE = 0,
> + VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE = 1,
> +};
> +
> +/**
> + * struct viif_l1_hdrs_config - L1ISP HDRS parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS`
> + * @hdrs_hdr_mode: &enum viif_l1_hdrs_middle_img_mode value.
> + * Use/No use settings of middle sensitivity image in HDRS.
> + * @hdrs_hdr_ratio_m: Magnification ratio of middle sensitivity image for high
> + * sensitivity image [0x400..0x400000] accuracy: 1/1024
> + * @hdrs_hdr_ratio_l: Magnification ratio of low sensitivity image for high
> + * sensitivity image [0x400..0x400000], accuracy: 1/1024
> + * @hdrs_hdr_ratio_e: Magnification ratio of LED image for high sensitivity image
> + * [0x400..0x400000], accuracy: 1/1024
> + * @hdrs_dg_h: High sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_dg_m: Middle sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_dg_l: Low sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_dg_e: LED image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_blendend_h: Maximum luminance used for blend high sensitivity image [0..4095]
> + * @hdrs_blendend_m: Maximum luminance used for blend middle sensitivity image [0..4095]
> + * @hdrs_blendend_e: Maximum luminance used for blend LED image [0..4095]
> + * @hdrs_blendbeg_h: Minimum luminance used for blend high sensitivity image [0..4095]
> + * @hdrs_blendbeg_m: Minimum luminance used for blend middle sensitivity image [0..4095]
> + * @hdrs_blendbeg_e: Minimum luminance used for blend LED image [0..4095]
> + * @hdrs_led_mode_on: 1:Enable/0:Disable settings of LED mode
> + * @hdrs_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
> + *
> + * parameter error needs to be returned in the below condition.
> + * (hdrs_hdr_mode == VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) && (hdrs_led_mode_on == 1)
> + */
> +struct viif_l1_hdrs_config {
> + __u32 hdrs_hdr_mode;
> + __u32 hdrs_hdr_ratio_m;
> + __u32 hdrs_hdr_ratio_l;
> + __u32 hdrs_hdr_ratio_e;
> + __u32 hdrs_dg_h;
> + __u32 hdrs_dg_m;
> + __u32 hdrs_dg_l;
> + __u32 hdrs_dg_e;
> + __u32 hdrs_blendend_h;
> + __u32 hdrs_blendend_m;
> + __u32 hdrs_blendend_e;
> + __u32 hdrs_blendbeg_h;
> + __u32 hdrs_blendbeg_m;
> + __u32 hdrs_blendbeg_e;
> + __u32 hdrs_led_mode_on;
> + __u32 hdrs_dst_max_val;
> +};
> +
> +/**
> + * struct viif_l1_black_level_correction_config - L1ISP image level conversion
> + * parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION`
> + * @srcblacklevel_gr: Black level of Gr input pixel [pixel] [0..0xFFFFFF]
> + * @srcblacklevel_r: Black level of R input pixel [pixel] [0..0xFFFFFF]
> + * @srcblacklevel_b: Black level of B input pixel [pixel] [0..0xFFFFFF]
> + * @srcblacklevel_gb: Black level of Gb input pixel [pixel] [0..0xFFFFFF]
> + * @mulval_gr: Gr gain [0..0xFFFFF], accuracy: 1/256
> + * @mulval_r: R gain [0..0xFFFFF], accuracy: 1/256
> + * @mulval_b: B gain [0..0xFFFFF], accuracy: 1/256
> + * @mulval_gb: Gb gain [0..0xFFFFF], accuracy: 1/256
> + * @dstmaxval: Maximum value of output pixel [pixel] [0..0xFFFFFF]
> + */
> +struct viif_l1_black_level_correction_config {
> + __u32 srcblacklevel_gr;
> + __u32 srcblacklevel_r;
> + __u32 srcblacklevel_b;
> + __u32 srcblacklevel_gb;
> + __u32 mulval_gr;
> + __u32 mulval_r;
> + __u32 mulval_b;
> + __u32 mulval_gb;
> + __u32 dstmaxval;
> +};
> +
> +/**
> + * enum viif_l1_para_coef_gain - L1ISP parabola shading correction coefficient ratio
> + *
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH: 1/8
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH: 1/4
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_SECOND: 1/2
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_FIRST: 1/1
> + */
> +enum viif_l1_para_coef_gain {
> + VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH = 0, /* 1/8 */
> + VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH = 1, /* 1/4 */
> + VIIF_L1_PARA_COEF_GAIN_ONE_SECOND = 2, /* 1/2 */
> + VIIF_L1_PARA_COEF_GAIN_ONE_FIRST = 3, /* 1/1 */
> +};
> +
> +/**
> + * enum viif_l1_grid_coef_gain - L1ISP grid shading correction coefficient ratio
> + *
> + * @VIIF_L1_GRID_COEF_GAIN_X1: x1
> + * @VIIF_L1_GRID_COEF_GAIN_X2: x2
> + */
> +enum viif_l1_grid_coef_gain {
> + VIIF_L1_GRID_COEF_GAIN_X1 = 0,
> + VIIF_L1_GRID_COEF_GAIN_X2 = 1,
> +};
> +
> +/**
> + * struct viif_l1_lsc_parabola_ag_param - L2ISP parabola shading parameters
> + * for &struct viif_l1_lsc_parabola_param
> + * @lssc_paracoef_h_l_max: Parabola coefficient left maximum gain value
> + * @lssc_paracoef_h_l_min: Parabola coefficient left minimum gain value
> + * @lssc_paracoef_h_r_max: Parabola coefficient right maximum gain value
> + * @lssc_paracoef_h_r_min: Parabola coefficient right minimum gain value
> + * @lssc_paracoef_v_u_max: Parabola coefficient upper maximum gain value
> + * @lssc_paracoef_v_u_min: Parabola coefficient upper minimum gain value
> + * @lssc_paracoef_v_d_max: Parabola coefficient lower maximum gain value
> + * @lssc_paracoef_v_d_min: Parabola coefficient lower minimum gain value
> + * @lssc_paracoef_hv_lu_max: Parabola coefficient upper left gain maximum value
> + * @lssc_paracoef_hv_lu_min: Parabola coefficient upper left gain minimum value
> + * @lssc_paracoef_hv_ru_max: Parabola coefficient upper right gain maximum value
> + * @lssc_paracoef_hv_ru_min: Parabola coefficient upper right minimum gain value
> + * @lssc_paracoef_hv_ld_max: Parabola coefficient lower left gain maximum value
> + * @lssc_paracoef_hv_ld_min: Parabola coefficient lower left gain minimum value
> + * @lssc_paracoef_hv_rd_max: Parabola coefficient lower right gain maximum value
> + * @lssc_paracoef_hv_rd_min: Parabola coefficient lower right minimum gain value
> + *
> + * The range and accuracy of each coefficient are as
> + * "range: [-4096..4095], accuracy: 1/256 "
> + *
> + * Each coefficient should meet the following conditions.
> + * "lssc_paracoef_xx_xx_min <= lssc_paracoef_xx_xx_max"
> + */
> +struct viif_l1_lsc_parabola_ag_param {
> + __s16 lssc_paracoef_h_l_max;
> + __s16 lssc_paracoef_h_l_min;
> + __s16 lssc_paracoef_h_r_max;
> + __s16 lssc_paracoef_h_r_min;
> + __s16 lssc_paracoef_v_u_max;
> + __s16 lssc_paracoef_v_u_min;
> + __s16 lssc_paracoef_v_d_max;
> + __s16 lssc_paracoef_v_d_min;
> + __s16 lssc_paracoef_hv_lu_max;
> + __s16 lssc_paracoef_hv_lu_min;
> + __s16 lssc_paracoef_hv_ru_max;
> + __s16 lssc_paracoef_hv_ru_min;
> + __s16 lssc_paracoef_hv_ld_max;
> + __s16 lssc_paracoef_hv_ld_min;
> + __s16 lssc_paracoef_hv_rd_max;
> + __s16 lssc_paracoef_hv_rd_min;
> +};
> +
> +/**
> + * struct viif_l1_lsc_parabola_param - L2ISP parabola shading parameters
> + * for &struct viif_l1_lsc
> + * @lssc_para_h_center: Horizontal coordinate of central optical axis [pixel]
> + * [0..(Input image width - 1)]
> + * @lssc_para_v_center: Vertical coordinate of central optical axis [line]
> + * [0..(Input image height - 1)]
> + * @lssc_para_h_gain: Horizontal distance gain with the optical axis
> + * [0..4095], accuracy: 1/256
> + * @lssc_para_v_gain: Vertical distance gain with the optical axis
> + * [0..4095], accuracy: 1/256
> + * @lssc_para_mgsel2: &enum viif_l1_para_coef_gain value.
> + * Parabola 2D correction coefficient gain magnification ratio.
> + * @lssc_para_mgsel4: &enum viif_l1_para_coef_gain value.
> + * Parabola 4D correction coefficient gain magnification ratio.
> + * @r_2d: 2D parabola coefficient for R.
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @r_4d: 4D parabola coefficient for R.
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gr_2d: 2D parabola coefficient for Gr
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gr_4d: 4D parabola coefficient for Gr
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gb_2d: 2D parabola coefficient for Gb
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gb_4d: 4D parabola coefficient for Gb
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @b_2d: 2D parabola coefficient for B
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @b_4d: 4D parabola coefficient for B
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + */
> +struct viif_l1_lsc_parabola_param {
> + __u32 lssc_para_h_center;
> + __u32 lssc_para_v_center;
> + __u32 lssc_para_h_gain;
> + __u32 lssc_para_v_gain;
> + __u32 lssc_para_mgsel2;
> + __u32 lssc_para_mgsel4;
> + struct viif_l1_lsc_parabola_ag_param r_2d;
> + struct viif_l1_lsc_parabola_ag_param r_4d;
> + struct viif_l1_lsc_parabola_ag_param gr_2d;
> + struct viif_l1_lsc_parabola_ag_param gr_4d;
> + struct viif_l1_lsc_parabola_ag_param gb_2d;
> + struct viif_l1_lsc_parabola_ag_param gb_4d;
> + struct viif_l1_lsc_parabola_ag_param b_2d;
> + struct viif_l1_lsc_parabola_ag_param b_4d;
> +};
> +
> +/**
> + * struct viif_l1_lsc_grid_param - L2ISP grid shading parameters
> + * for &struct viif_l1_lsc
> + * @lssc_grid_h_size: Grid horizontal direction pixel count [32, 64, 128, 256, 512]
> + * @lssc_grid_v_size: Grid vertical direction pixel count [32, 64, 128, 256, 512]
> + * @lssc_grid_h_center: Horizontal coordinates of grid (1, 1) [pixel] [1..lssc_grid_h_size]
> + * Should meet the following condition.
> + * "Input image width <= lssc_grid_h_center + lssc_grid_h_size * 31"
> + * @lssc_grid_v_center: Vertical coordinates of grid (1, 1) [line] [1..lssc_grid_v_size]
> + * Should meet the following condition.
> + * "Input image height <= lssc_grid_v_center + lssc_grid_v_size * 23"
> + * @lssc_grid_mgsel: &enum viif_l1_grid_coef_gain value.
> + * Grid correction coefficient gain value magnification ratio.
> + */
> +struct viif_l1_lsc_grid_param {
> + __u32 lssc_grid_h_size;
> + __u32 lssc_grid_v_size;
> + __u32 lssc_grid_h_center;
> + __u32 lssc_grid_v_center;
> + __u32 lssc_grid_mgsel;
> +};
> +
> +/**
> + * struct viif_l1_lsc - L2ISP LSC parameters for &struct viif_l1_lsc_config
> + * @lssc_parabola_param_addr: Address of a &struct viif_l1_lsc_parabola_param instance.
> + * Set 0 to disable parabola shading correction.
> + * @lssc_grid_param_addr: Address of a &struct viif_l1_lsc_grid_param instance,
> + * Set 0 to disable grid shading correction.
> + * @lssc_pwhb_r_gain_max: PWB R correction processing coefficient maximum value
> + * @lssc_pwhb_r_gain_min: PWB R correction processing coefficient minimum value
> + * @lssc_pwhb_gr_gain_max: PWB Gr correction processing coefficient maximum value
> + * @lssc_pwhb_gr_gain_min: PWB Gr correction processing coefficient minimum value
> + * @lssc_pwhb_gb_gain_max: PWB Gb correction processing coefficient maximum value
> + * @lssc_pwhb_gb_gain_min: PWB Gb correction processing coefficient minimum value
> + * @lssc_pwhb_b_gain_max: PWB B correction processing coefficient maximum value
> + * @lssc_pwhb_b_gain_min: PWB B correction processing coefficient minimum value
> + *
> + * The range and accuracy of preset white balance (PWB) correction process
> + * coefficient (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) are as below.
> + * "range: [0..2047], accuracy: 1/256"
> + *
> + * PWB correction process coefficient
> + * (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) should meet the following conditions.
> + * "lssc_pwhb_{r/gr/gb/b}_gain_min <= lssc_pwhb_{r/gr/gb/b}_gain_max"
> + */
> +struct viif_l1_lsc {
> + __u64 lssc_parabola_param_addr;
> + __u64 lssc_grid_param_addr;
> + __u32 lssc_pwhb_r_gain_max;
> + __u32 lssc_pwhb_r_gain_min;
> + __u32 lssc_pwhb_gr_gain_max;
> + __u32 lssc_pwhb_gr_gain_min;
> + __u32 lssc_pwhb_gb_gain_max;
> + __u32 lssc_pwhb_gb_gain_min;
> + __u32 lssc_pwhb_b_gain_max;
> + __u32 lssc_pwhb_b_gain_min;
> +};
> +
> +/**
> + * struct viif_l1_lsc_config - L2ISP LSC parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC`
> + * @param_addr: Address of a &struct viif_l1_lsc instance.
> + * Set 0 to disable LSC operation.
> + * @table_gr_addr: Address of the grid table for LSC of Gr component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + * @table_r_addr: Address of the grid table for LSC of R component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + * @table_b_addr: Address of the grid table for LSC of B component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + * @table_gb_addr: Address of the grid table for LSC of Gb component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + *
> + * The size of each table is fixed to 1,536 Bytes.
> + * Application should make sure that the table data is based on HW specification
> + * since this driver does not check the grid table.
> + */
> +struct viif_l1_lsc_config {
> + __u64 param_addr;
> + __u64 table_gr_addr;
> + __u64 table_r_addr;
> + __u64 table_b_addr;
> + __u64 table_gb_addr;
> +};
> +
> +/**
> + * enum viif_l1_demosaic_mode - L1ISP demosaic modeenum viif_l1_demosaic_mode
> + *
> + * @VIIF_L1_DEMOSAIC_ACPI: Toshiba ACPI algorithm
> + * @VIIF_L1_DEMOSAIC_DMG: DMG algorithm
> + */
> +enum viif_l1_demosaic_mode {
> + VIIF_L1_DEMOSAIC_ACPI = 0,
> + VIIF_L1_DEMOSAIC_DMG = 1,
> +};
> +
> +/**
> + * struct viif_l1_color_matrix_correction - L1ISP color matrix correction
> + * parameters for &struct viif_l1_main_process_config
> + * @coef_rmg_min: (R-G) Minimum coefficient
> + * @coef_rmg_max: (R-G) Maximum coefficient
> + * @coef_rmb_min: (R-B) Minimum coefficient
> + * @coef_rmb_max: (R-B) Maximum coefficient
> + * @coef_gmr_min: (G-R) Minimum coefficient
> + * @coef_gmr_max: (G-R) Maximum coefficient
> + * @coef_gmb_min: (G-B) Minimum coefficient
> + * @coef_gmb_max: (G-B) Maximum coefficient
> + * @coef_bmr_min: (B-R) Minimum coefficient
> + * @coef_bmr_max: (B-R) Maximum coefficient
> + * @coef_bmg_min: (B-G) Minimum coefficient
> + * @coef_bmg_max: (B-G) Maximum coefficient
> + * @dst_minval: Minimum value of output pixel [0..0xFFFF] [pixel]
> + *
> + * The range and accuracy of each coefficient are as
> + * "range: [-32768..32767], accuracy: 1/ 4096"
> + *
> + * Also, each coefficient should meet "coef_xxx_min <= coef_xxx_max" condition
> + */
> +struct viif_l1_color_matrix_correction {
> + __s16 coef_rmg_min;
> + __s16 coef_rmg_max;
> + __s16 coef_rmb_min;
> + __s16 coef_rmb_max;
> + __s16 coef_gmr_min;
> + __s16 coef_gmr_max;
> + __s16 coef_gmb_min;
> + __s16 coef_gmb_max;
> + __s16 coef_bmr_min;
> + __s16 coef_bmr_max;
> + __s16 coef_bmg_min;
> + __s16 coef_bmg_max;
> + __u16 dst_minval;
> +};
> +
> +/**
> + * struct viif_l1_main_process_config - L1ISP Main process operating parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS`
> + * @demosaic_mode: &enum viif_l1_demosaic_mode value. Sets demosaic mode.
> + * @damp_lsbsel: Clipping range of output pixel value to AWB adjustment function [0..15]
> + * @param_addr: Address to a &struct viif_l1_color_matrix_correction instance.
> + * Set 0 to disable color matrix correction.
> + * @dst_maxval: Maximum value of output pixel [0..0xFFFFFF].
> + * Applicable to output of each process (digital amplifier,
> + * demosaicing and color matrix correction) in L1ISP Main process.
> + */
> +struct viif_l1_main_process_config {
> + __u32 demosaic_mode;
> + __u32 damp_lsbsel;
> + __u64 param_addr;
> + __u32 dst_maxval;
> +};
> +
> +/**
> + * enum viif_l1_awb_mag - L1ISP signal magnification before AWB adjustment
> + *
> + * @VIIF_L1_AWB_ONE_SECOND: x 1/2
> + * @VIIF_L1_AWB_X1: 1 times
> + * @VIIF_L1_AWB_X2: 2 times
> + * @VIIF_L1_AWB_X4: 4 times
> + */
> +enum viif_l1_awb_mag {
> + VIIF_L1_AWB_ONE_SECOND = 0,
> + VIIF_L1_AWB_X1 = 1,
> + VIIF_L1_AWB_X2 = 2,
> + VIIF_L1_AWB_X4 = 3,
> +};
> +
> +/**
> + * enum viif_l1_awb_area_mode - L1ISP AWB detection target area
> + *
> + * @VIIF_L1_AWB_AREA_MODE0: only center area
> + * @VIIF_L1_AWB_AREA_MODE1: center area when uv is in square gate
> + * @VIIF_L1_AWB_AREA_MODE2: all area except center area
> + * @VIIF_L1_AWB_AREA_MODE3: all area
> + */
> +enum viif_l1_awb_area_mode {
> + VIIF_L1_AWB_AREA_MODE0 = 0,
> + VIIF_L1_AWB_AREA_MODE1 = 1,
> + VIIF_L1_AWB_AREA_MODE2 = 2,
> + VIIF_L1_AWB_AREA_MODE3 = 3,
> +};
> +
> +/**
> + * enum viif_l1_awb_restart_cond - L1ISP AWB adjustment restart conditions
> + *
> + * @VIIF_L1_AWB_RESTART_NO: no restart
> + * @VIIF_L1_AWB_RESTART_128FRAME: restart after 128 frame
> + * @VIIF_L1_AWB_RESTART_64FRAME: restart after 64 frame
> + * @VIIF_L1_AWB_RESTART_32FRAME: restart after 32 frame
> + * @VIIF_L1_AWB_RESTART_16FRAME: restart after 16 frame
> + * @VIIF_L1_AWB_RESTART_8FRAME: restart after 8 frame
> + * @VIIF_L1_AWB_RESTART_4FRAME: restart after 4 frame
> + * @VIIF_L1_AWB_RESTART_2FRAME: restart after 2 frame
> + */
> +enum viif_l1_awb_restart_cond {
> + VIIF_L1_AWB_RESTART_NO = 0,
> + VIIF_L1_AWB_RESTART_128FRAME = 1,
> + VIIF_L1_AWB_RESTART_64FRAME = 2,
> + VIIF_L1_AWB_RESTART_32FRAME = 3,
> + VIIF_L1_AWB_RESTART_16FRAME = 4,
> + VIIF_L1_AWB_RESTART_8FRAME = 5,
> + VIIF_L1_AWB_RESTART_4FRAME = 6,
> + VIIF_L1_AWB_RESTART_2FRAME = 7,
> +};
> +
> +/**
> + * struct viif_l1_awb - L1ISP AWB adjustment parameters
> + * for &struct viif_l1_awb_config
> + * @awhb_ygate_sel: 1:Enable/0:Disable to fix Y value at YUV conversion
> + * @awhb_ygate_data: Y value in case Y value is fixed [64, 128, 256, 512]
> + * @awhb_cgrange: &enum viif_l1_awb_mag value.
> + * Signal output magnification ratio before AWB adjustment.
> + * @awhb_ygatesw: 1:Enable/0:Disable settings of luminance gate
> + * @awhb_hexsw: 1:Enable/0:Disable settings of hexa-gate
> + * @awhb_areamode: &enum viif_l1_awb_area_mode value.
> + * Final selection of accumulation area for detection target area.
> + * @awhb_area_hsize: Horizontal size per block in central area [pixel]
> + * [1..(Input image width -8)/8]
> + * @awhb_area_vsize: Vertical size per block in central area [line]
> + * [1..(Input image height -4)/8]
> + * @awhb_area_hofs: Horizontal offset of block [0] in central area [pixel]
> + * [0..(Input image width -9)]
> + * @awhb_area_vofs: Vertical offset of block [0] in central area [line]
> + * [0..(Input image height -5)]
> + * @awhb_area_maskh: Setting 1:Enable/0:Disable( of accumulated selection.
> + * Each bit implies the following.
> + * [31:0] = {
> + * (7, 3),(6, 3),(5, 3),(4, 3),(3, 3),(2, 3),(1, 3),(0, 3),
> + * (7, 2),(6, 2),(5, 2),(4, 2),(3, 2),(2, 2),(1, 2),(0, 2),
> + * (7, 1),(6, 1),(5, 1),(4, 1),(3, 1),(2, 1),(1, 1),(0, 1),
> + * (7, 0),(6, 0),(5, 0),(4, 0),(3, 0),(2, 0),(1, 0),(0, 0)}
> + * @awhb_area_maskl: Setting 1:Enable/0:Disable of accumulated selection.
> + * Each bit implies the following.
> + * [31:0] = {
> + * (7, 7),(6, 7),(5, 7),(4, 7),(3, 7),(2, 7),(1, 7),(0, 7),
> + * (7, 6),(6, 6),(5, 6),(4, 6),(3, 6),(2, 6),(1, 6),(0, 6),
> + * (7, 5),(6, 5),(5, 5),(4, 5),(3, 5),(2, 5),(1, 5),(0, 5),
> + * (7, 4),(6, 4),(5, 4),(4, 4),(3, 4),(2, 4),(1, 4),(0, 4)}
> + * @awhb_sq_sw: 1:Enable/0:Disable each square gate
> + * @awhb_sq_pol: 1:Enable/0:Disable to add accumulated gate for each square gate
> + * @awhb_bycut0p: U upper end value [pixel] [0..127]
> + * @awhb_bycut0n: U lower end value [pixel] [0..127]
> + * @awhb_rycut0p: V upper end value [pixel] [0..127]
> + * @awhb_rycut0n: V lower end value [pixel] [0..127]
> + * @awhb_rbcut0h: V-axis intercept upper end [pixel] [-127..127]
> + * @awhb_rbcut0l: V-axis intercept lower end [pixel] [-127..127]
> + * @awhb_bycut_h: U direction center value of each square gate [-127..127]
> + * @awhb_bycut_l: U direction width of each square gate [0..127]
> + * @awhb_rycut_h: V direction center value of each square gate [-127..127]
> + * @awhb_rycut_l: V direction width of each square gate [0..127]
> + * @awhb_awbsftu: U gain offset [-127..127]
> + * @awhb_awbsftv: V gain offset [-127..127]
> + * @awhb_awbhuecor: 1:Enable/0:Disable setting of color correlation retention function
> + * @awhb_awbspd: UV convergence speed [0..15] [times] (0 means "stop")
> + * @awhb_awbulv: U convergence point level [0..31]
> + * @awhb_awbvlv: V convergence point level [0..31]
> + * @awhb_awbondot: Accumulation operation stop pixel count threshold [pixel] [0..1023]
> + * @awhb_awbfztim: &enum viif_l1_awb_restart_cond value. Condition to restart AWB process.
> + * @awhb_wbgrmax: B gain adjustment range (Width from center to upper limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_wbgbmax: R gain adjustment range (Width from center to upper limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_wbgrmin: B gain adjustment range (Width from center to lower limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_wbgbmin: R gain adjustment range (Width from center to lower limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_ygateh: Luminance gate maximum value [pixel] [0..255]
> + * @awhb_ygatel: Luminance gate minimum value [pixel] [0..255]
> + * @awhb_awbwait: Number of restart frames after UV convergence freeze [0..255]
> + */
> +struct viif_l1_awb {
> + __u32 awhb_ygate_sel;
> + __u32 awhb_ygate_data;
> + __u32 awhb_cgrange;
> + __u32 awhb_ygatesw;
> + __u32 awhb_hexsw;
> + __u32 awhb_areamode;
> + __u32 awhb_area_hsize;
> + __u32 awhb_area_vsize;
> + __u32 awhb_area_hofs;
> + __u32 awhb_area_vofs;
> + __u32 awhb_area_maskh;
> + __u32 awhb_area_maskl;
> + __u32 awhb_sq_sw[3];
> + __u32 awhb_sq_pol[3];
> + __u32 awhb_bycut0p;
> + __u32 awhb_bycut0n;
> + __u32 awhb_rycut0p;
> + __u32 awhb_rycut0n;
> + __s32 awhb_rbcut0h;
> + __s32 awhb_rbcut0l;
> + __s32 awhb_bycut_h[3];
> + __u32 awhb_bycut_l[3];
> + __s32 awhb_rycut_h[3];
> + __u32 awhb_rycut_l[3];
> + __s32 awhb_awbsftu;
> + __s32 awhb_awbsftv;
> + __u32 awhb_awbhuecor;
> + __u32 awhb_awbspd;
> + __u32 awhb_awbulv;
> + __u32 awhb_awbvlv;
> + __u32 awhb_awbondot;
> + __u32 awhb_awbfztim;
> + __u8 awhb_wbgrmax;
> + __u8 awhb_wbgbmax;
> + __u8 awhb_wbgrmin;
> + __u8 awhb_wbgbmin;
> + __u8 awhb_ygateh;
> + __u8 awhb_ygatel;
> + __u8 awhb_awbwait;
> +};
> +
> +/**
> + * struct viif_l1_awb_config - L1ISP AWB parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB`
> + * @param_addr: Address to a &struct viif_l1_awb instance.
> + * Set 0 to disable AWB adjustment.
> + * @awhb_wbmrg: White balance adjustment R gain [64..1023], accuracy: 1/256
> + * @awhb_wbmgg: White balance adjustment G gain [64..1023], accuracy: 1/256
> + * @awhb_wbmbg: White balance adjustment B gain [64..1023], accuracy: 1/256
> + */
> +struct viif_l1_awb_config {
> + __u64 param_addr;
> + __u32 awhb_wbmrg;
> + __u32 awhb_wbmgg;
> + __u32 awhb_wbmbg;
> +};
> +
> +/**
> + * enum viif_l1_hdrc_tone_type - L1ISP HDRC tone type
> + *
> + * @VIIF_L1_HDRC_TONE_USER: User Tone
> + * @VIIF_L1_HDRC_TONE_PRESET: Preset Tone
> + */
> +enum viif_l1_hdrc_tone_type {
> + VIIF_L1_HDRC_TONE_USER = 0,
> + VIIF_L1_HDRC_TONE_PRESET = 1,
> +};
> +
> +/**
> + * struct viif_l1_hdrc - L1ISP HDRC parameters for &struct viif_l1_hdrc_config
> + * @hdrc_ratio: Data width of input image [bit] [10..24]
> + * @hdrc_pt_ratio: Preset Tone curve slope [0..13]
> + * @hdrc_pt_blend: Preset Tone0 curve blend ratio [0..256], accuracy: 1/256
> + * @hdrc_pt_blend2: Preset Tone2 curve blend ratio [0..256], accuracy: 1/256
> + * @hdrc_tn_type: &enum viif_l1_hdrc_tone_type value. L1ISP HDRC tone type.
> + * @hdrc_utn_tbl: HDRC value of User Tone curve [0..0xFFFF]
> + * @hdrc_flr_val: Constant flare value [0..0xFFFFFF]
> + * @hdrc_flr_adp: 1:Enable/0:Disable setting of dynamic flare measurement
> + * @hdrc_ybr_off: 1:Enable(function OFF) / 0:Disable(function ON) settings
> + * of bilateral luminance filter function OFF
> + * @hdrc_orgy_blend: Blend settings of luminance correction data after HDRC
> + * and data before luminance correction [0..16].
> + * (0:Luminance correction 100%, 8:Luminance correction 50%,
> + * 16:Luminance correction 0%)
> + * @hdrc_pt_sat: Preset Tone saturation value [0..0xFFFF]
> + *
> + * Parameter error needs to be returned in
> + * "hdrc_pt_blend + hdrc_pt_blend2 > 256" condition.
> + *
> + * In case application enables dynamic flare control, input image height should
> + * satisfy the following condition. Even if this condition is not satisfied,
> + * this driver doesn't return error in case other conditions for each parameter
> + * are satisfied. "Input image height % 64 != 18, 20, 22, 24, 26"
> + *
> + * hdrc_utn_tbl should satisfy the following condition. Even if this condition
> + * is not satisfied, this driver doesn't return error in case other conditions
> + * for each parameter are satisfied. "hdrc_utn_tbl[N] <= hdrc_utn_tbl[N+1]"
> + */
> +struct viif_l1_hdrc {
> + __u32 hdrc_ratio;
> + __u32 hdrc_pt_ratio;
> + __u32 hdrc_pt_blend;
> + __u32 hdrc_pt_blend2;
> + __u32 hdrc_tn_type;
> + __u16 hdrc_utn_tbl[20];
> + __u32 hdrc_flr_val;
> + __u32 hdrc_flr_adp;
> + __u32 hdrc_ybr_off;
> + __u32 hdrc_orgy_blend;
> + __u16 hdrc_pt_sat;
> +};
> +
> +/**
> + * struct viif_l1_hdrc_config - L1ISP HDRC parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC`
> + * @param_addr: Address to a &struct viif_l1_hdrc instance.
> + * Set 0 to disable HDR compression.
> + * @hdrc_thr_sft_amt: Amount of right shift in through mode (HDRC disabled) [0..8].
> + * Should set 0 if HDRC is enabled
> + */
> +struct viif_l1_hdrc_config {
> + __u64 param_addr;
> + __u32 hdrc_thr_sft_amt;
> +};
> +
> +/**
> + * struct viif_l1_hdrc_ltm_config - L1ISP HDRC LTM parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM`
> + * @tnp_max: Tone blend rate maximum value of LTM function
> + * [0..4194303], accuracy: 1/64. In case of 0, LTM function is OFF
> + * @tnp_mag: Intensity adjustment of LTM function [0..16383], accuracy: 1/64
> + * @tnp_fil: Smoothing filter coefficient [0..255].
> + * [0]: coef0, [1]: coef1, [2]: coef2, [3]: coef3, [4]: coef4
> + * EINVAL needs to be returned in the below condition.
> + * "(coef1 + coef2 + coef3 + coef4) * 2 + coef0 != 1024"
> + */
> +struct viif_l1_hdrc_ltm_config {
> + __u32 tnp_max;
> + __u32 tnp_mag;
> + __u8 tnp_fil[5];
> +};
> +
> +/**
> + * struct viif_l1_gamma - L1ISP gamma correction parameters
> + * for &struct viif_l1_gamma_config
> + * @gam_p: Luminance value after gamma correction [0..8191]
> + * @blkadj: Black level adjustment value after gamma correction [0..65535]
> + */
> +struct viif_l1_gamma {
> + __u16 gam_p[44];
> + __u16 blkadj;
> +};
> +
> +/**
> + * struct viif_l1_gamma_config - L1ISP gamma correction parameters
> + * @param_addr: Address to a &struct viif_l1_gamma instance.
> + * Set 0 to disable gamma correction at l1 ISP.
> + */
> +struct viif_l1_gamma_config {
> + __u64 param_addr;
> +};
> +
> +/**
> + * struct viif_l1_nonlinear_contrast - L1ISP non-linear contrast parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @blk_knee: Black side peak luminance value [0..0xFFFF]
> + * @wht_knee: White side peak luminance value[0..0xFFFF]
> + * @blk_cont: Black side slope [0..255], accuracy: 1/256
> + * [0]:the value at AG minimum, [1]:the value at AG less than 128,
> + * [2]:the value at AG equal to or more than 128
> + * @wht_cont: White side slope [0..255], accuracy: 1/256
> + * [0]:the value at AG minimum, [1]:the value at AG less than 128,
> + * [2]:the value at AG equal to or more than 128
> + */
> +struct viif_l1_nonlinear_contrast {
> + __u16 blk_knee;
> + __u16 wht_knee;
> + __u8 blk_cont[3];
> + __u8 wht_cont[3];
> +};
> +
> +/**
> + * struct viif_l1_lum_noise_reduction - L1ISP luminance noise reduction
> + * parameters for &struct viif_l1_img_quality_adjustment_config
> + * @gain_min: Minimum value of extracted noise gain [0..0xFFFF], accuracy: 1/256
> + * @gain_max: Maximum value of extracted noise gain [0..0xFFFF], accuracy: 1/256
> + * @lim_min: Minimum value of extracted noise limit [0..0xFFFF]
> + * @lim_max: Maximum value of extracted noise limit [0..0xFFFF]
> + *
> + * Parameter error needs to be returned in the below conditions.
> + * "gain_min > gain_max" or "lim_min > lim_max"
> + */
> +struct viif_l1_lum_noise_reduction {
> + __u16 gain_min;
> + __u16 gain_max;
> + __u16 lim_min;
> + __u16 lim_max;
> +};
> +
> +/**
> + * struct viif_l1_edge_enhancement - L1ISP edge enhancement parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @gain_min: Extracted edge gain minimum value [0..0xFFFF], accuracy: 1/256
> + * @gain_max: Extracted edge gain maximum value [0..0xFFFF], accuracy: 1/256
> + * @lim_min: Extracted edge limit minimum value [0..0xFFFF]
> + * @lim_max: Extracted edge limit maximum value [0..0xFFFF]
> + * @coring_min: Extracted edge coring threshold minimum value [0..0xFFFF]
> + * @coring_max: Extracted edge coring threshold maximum value [0..0xFFFF]
> + *
> + * Parameter error needs to be returned in the below conditions.
> + * "gain_min > gain_max" or "lim_min > lim_max" or "coring_min > coring_max"
> + */
> +struct viif_l1_edge_enhancement {
> + __u16 gain_min;
> + __u16 gain_max;
> + __u16 lim_min;
> + __u16 lim_max;
> + __u16 coring_min;
> + __u16 coring_max;
> +};
> +
> +/**
> + * struct viif_l1_uv_suppression - L1ISP UV suppression parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @bk_mp: Black side slope [0..0x3FFF], accuracy: 1/16384
> + * @black: Minimum black side gain [0..0x3FFF], accuracy: 1/16384
> + * @wh_mp: White side slope [0..0x3FFF], accuracy: 1/16384
> + * @white: Minimum white side gain [0..0x3FFF], accuracy: 1/16384
> + * @bk_slv: Black side intercept [0..0xFFFF]
> + * @wh_slv: White side intercept [0..0xFFFF]
> + *
> + * parameter error needs to be returned in "bk_slv >= wh_slv" condition.
> + */
> +struct viif_l1_uv_suppression {
> + __u32 bk_mp;
> + __u32 black;
> + __u32 wh_mp;
> + __u32 white;
> + __u16 bk_slv;
> + __u16 wh_slv;
> +};
> +
> +/**
> + * struct viif_l1_coring_suppression - L1ISP coring suppression parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @lv_min: Minimum coring threshold [0..0xFFFF]
> + * @lv_max: Maximum coring threshold [0..0xFFFF]
> + * @gain_min: Minimum gain [0..0xFFFF], accuracy: 1/65536
> + * @gain_max: Maximum gain [0..0xFFFF], accuracy: 1/65536
> + *
> + * Parameter error needs to be returned in the below condition.
> + * "lv_min > lv_max" or "gain_min > gain_max"
> + */
> +struct viif_l1_coring_suppression {
> + __u16 lv_min;
> + __u16 lv_max;
> + __u16 gain_min;
> + __u16 gain_max;
> +};
> +
> +/**
> + * struct viif_l1_edge_suppression - L1ISP edge suppression parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @gain: Gain of edge color suppression [0..0xFFFF], accuracy: 1/256
> + * @lim: Limiter threshold of edge color suppression [0..15]
> + */
> +struct viif_l1_edge_suppression {
> + __u16 gain;
> + __u32 lim;
> +};
> +
> +/**
> + * struct viif_l1_color_level - L1ISP color level parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @cb_gain: U component gain [0..0xFFF], accuracy: 1/2048
> + * @cr_gain: V component gain [0..0xFFF], accuracy: 1/2048
> + * @cbr_mgain_min: UV component gain [0..0xFFF], accuracy: 1/2048
> + * @cbp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
> + * @cbm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
> + * @crp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
> + * @crm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
> + */
> +struct viif_l1_color_level {
> + __u32 cb_gain;
> + __u32 cr_gain;
> + __u32 cbr_mgain_min;
> + __u32 cbp_gain_max;
> + __u32 cbm_gain_max;
> + __u32 crp_gain_max;
> + __u32 crm_gain_max;
> +};
> +
> +/**
> + * struct viif_l1_img_quality_adjustment_config - L1ISP image quality
> + * adjustment parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT`
> + * @coef_cb: Cb coefficient used in RGB to YUV conversion
> + * [0..0xFFFF], accuracy: 1/65536
> + * @coef_cr: Cr coefficient used in RGB to YUV conversion
> + * [0..0xFFFF], accuracy: 1/65536
> + * @brightness: Brightness value [-32768..32767] (0 means off)
> + * @linear_contrast: Linear contrast adjustment value
> + * [0..0xFF], accuracy: 1/128 (128 means off)
> + * @nonlinear_contrast_addr: Address to a &struct viif_l1_nonlinear_contrast instance.
> + * Set 0 to disable nonlinear contrast adjustment.
> + * @lum_noise_reduction_addr: Address to a &struct viif_l1_lum_noise_reduction instance.
> + * Set 0 to disable luminance noise reduction.
> + * @edge_enhancement_addr: Address to a &struct viif_l1_edge_enhancement instance.
> + * Set 0 to disable edge enhancement,
> + * @uv_suppression_addr: Address to a &struct viif_l1_uv_suppression instance.
> + * Set 0 to disable chroma suppression.
> + * @coring_suppression_addr: Address to a &struct viif_l1_coring_suppression instance.
> + * Set 0 to disable coring suppression.
> + * @edge_suppression_addr: Address to a &struct viif_l1_edge_suppression instance.
> + * Set 0 to disable chroma edge suppression.
> + * @color_level_addr: Address to a &struct viif_l1_color_level instance.
> + * Set 0 to disable color level adjustment.
> + * @color_noise_reduction_enable: 1:Enable/0:disable setting of
> + * color component noise reduction processing
> + */
> +struct viif_l1_img_quality_adjustment_config {
> + __u16 coef_cb;
> + __u16 coef_cr;
> + __s16 brightness;
> + __u8 linear_contrast;
> + __u64 nonlinear_contrast_addr;
> + __u64 lum_noise_reduction_addr;
> + __u64 edge_enhancement_addr;
> + __u64 uv_suppression_addr;
> + __u64 coring_suppression_addr;
> + __u64 edge_suppression_addr;
> + __u64 color_level_addr;
> + __u32 color_noise_reduction_enable;
> +};
> +
> +/**
> + * struct viif_l1_avg_lum_generation_config - L1ISP average luminance generation configuration
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION`
> + * @aexp_start_x: horizontal position of block[0] [0.."width of input image - 1"] [pixel]
> + * @aexp_start_y: vertical position of block[0] [0.."height of input image - 1"] [line]
> + * @aexp_block_width: width of one block(needs to be multiple of 64)
> + * [64.."width of input image"] [pixel]
> + * @aexp_block_height: height of one block(needs to be multiple of 64)
> + * [64.."height of input image"] [line]
> + * @aexp_weight: weight of each block [0..3] [y][x]:
> + * y means vertical position and x means horizontal position
> + * @aexp_satur_ratio: threshold to judge whether saturated block or not [0..256]
> + * @aexp_black_ratio: threshold to judge whether black block or not [0..256]
> + * @aexp_satur_level: threshold to judge whether saturated pixel or not [0x0..0xffffff]
> + * @aexp_ave4linesy: vertical position of the initial line
> + * for 4-lines average luminance [0.."height of input image - 4"] [line]
> + */
> +struct viif_l1_avg_lum_generation_config {
> + __u32 aexp_start_x;
> + __u32 aexp_start_y;
> + __u32 aexp_block_width;
> + __u32 aexp_block_height;
> + __u32 aexp_weight[8][8];
> + __u32 aexp_satur_ratio;
> + __u32 aexp_black_ratio;
> + __u32 aexp_satur_level;
> + __u32 aexp_ave4linesy[4];
> +};
> +
> +/**
> + * enum viif_l2_undist_mode - L2ISP undistortion mode
> + * @VIIF_L2_UNDIST_POLY: polynomial mode
> + * @VIIF_L2_UNDIST_GRID: grid table mode
> + * @VIIF_L2_UNDIST_POLY_TO_GRID: polynomial, then grid table mode
> + * @VIIF_L2_UNDIST_GRID_TO_POLY: grid table, then polynomial mode
> + */
> +enum viif_l2_undist_mode {
> + VIIF_L2_UNDIST_POLY = 0,
> + VIIF_L2_UNDIST_GRID = 1,
> + VIIF_L2_UNDIST_POLY_TO_GRID = 2,
> + VIIF_L2_UNDIST_GRID_TO_POLY = 3,
> +};
> +
> +/**
> + * struct viif_l2_undist - L2ISP UNDIST parameters
> + * for &struct viif_l2_undist_config
> + * @through_mode: 1:enable or 0:disable through mode of undistortion
> + * @roi_mode: &enum viif_l2_undist_mode value. Sets L2ISP undistortion mode.
> + * @sensor_crop_ofs_h: Horizontal start position of sensor crop area[pixel]
> + * [-4296..4296], accuracy: 1/2
> + * @sensor_crop_ofs_v: Vertical start position of sensor crop area[line]
> + * [-2360..2360], accuracy: 1/2
> + * @norm_scale: Normalization coefficient for distance from center
> + * [0..1677721], accuracy: 1/33554432
> + * @valid_r_norm2_poly: Setting target area for polynomial correction
> + * [0..0x3FFFFFF], accuracy: 1/33554432
> + * @valid_r_norm2_grid: Setting target area for grid table correction
> + * [0..0x3FFFFFF], accuracy: 1/33554432
> + * @roi_write_area_delta: Error adjustment value of forward function and
> + * inverse function for pixel position calculation
> + * [0..0x7FF], accuracy: 1/1024
> + * @poly_write_g_coef: 10th-order polynomial coefficient for G write pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @poly_read_b_coef: 10th-order polynomial coefficient for B read pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @poly_read_g_coef: 10th-order polynomial coefficient for G read pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @poly_read_r_coef: 10th-order polynomial coefficient for R read pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @grid_node_num_h: Number of horizontal grids [16..64]
> + * @grid_node_num_v: Number of vertical grids [16..64]
> + * @grid_patch_hsize_inv: Inverse pixel size between horizontal grids
> + * [0..0x7FFFFF], accuracy: 1/8388608
> + * @grid_patch_vsize_inv: Inverse pixel size between vertical grids
> + * [0..0x7FFFFF], accuracy: 1/8388608
> + */
> +struct viif_l2_undist {
> + __u32 through_mode;
> + __u32 roi_mode[2];
> + __s32 sensor_crop_ofs_h;
> + __s32 sensor_crop_ofs_v;
> + __u32 norm_scale;
> + __u32 valid_r_norm2_poly;
> + __u32 valid_r_norm2_grid;
> + __u32 roi_write_area_delta[2];
> + __s32 poly_write_g_coef[11];
> + __s32 poly_read_b_coef[11];
> + __s32 poly_read_g_coef[11];
> + __s32 poly_read_r_coef[11];
> + __u32 grid_node_num_h;
> + __u32 grid_node_num_v;
> + __u32 grid_patch_hsize_inv;
> + __u32 grid_patch_vsize_inv;
> +};
> +
> +/**
> + * struct viif_l2_undist_config - L2ISP UNDIST parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST`
> + * @param: &struct viif_l2_undist
> + * @write_g_addr: Address to write-G grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @read_b_addr: Address to read-B grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @read_g_addr: Address to read-G grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @read_r_addr: Address to read-R grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @size: Table size [byte]. Range: [1024..8192] or 0.
> + * The value should be "grid_node_num_h * grid_node_num_v * 4".
> + * See also &struct viif_l2_undist.
> + * Set 0 if NULL is set for all tables.
> + * Set valid size value if at least one table is valid.
> + *
> + * Application should make sure that the table data is based on HW specification
> + * since this driver does not check the contents of specified grid table.
> + */
> +struct viif_l2_undist_config {
> + struct viif_l2_undist param;
> + __u64 write_g_addr;
> + __u64 read_b_addr;
> + __u64 read_g_addr;
> + __u64 read_r_addr;
> + __u32 size;
> +};
> +
> +/**
> + * struct viif_l2_roi_config - L2ISP ROI parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI`
> + * @roi_num:
> + * 1 when only capture path0 is activated,
> + * 2 when both capture path 0 and path 1 are activated.
> + * @roi_scale: Scale value for each ROI [32768..131072], accuracy: 1/65536
> + * @roi_scale_inv: Inverse scale value for each ROI [32768..131072], accuracy: 1/65536
> + * @corrected_wo_scale_hsize: Corrected image width for each ROI [pixel] [128..8190]
> + * @corrected_wo_scale_vsize: Corrected image height for each ROI [line] [128..4094]
> + * @corrected_hsize: Corrected and scaled image width for each ROI [pixel] [128..8190]
> + * @corrected_vsize: Corrected and scaled image height for each ROI [line] [128..4094]
> + */
> +struct viif_l2_roi_config {
> + __u32 roi_num;
> + __u32 roi_scale[2];
> + __u32 roi_scale_inv[2];
> + __u32 corrected_wo_scale_hsize[2];
> + __u32 corrected_wo_scale_vsize[2];
> + __u32 corrected_hsize[2];
> + __u32 corrected_vsize[2];
> +};
> +
> +/** enum viif_gamma_mode - Gamma correction mode
> + *
> + * @VIIF_GAMMA_COMPRESSED: compressed table mode
> + * @VIIF_GAMMA_LINEAR: linear table mode
> + */
> +enum viif_gamma_mode {
> + VIIF_GAMMA_COMPRESSED = 0,
> + VIIF_GAMMA_LINEAR = 1,
> +};
> +
> +/**
> + * struct viif_l2_gamma_config - L2ISP gamma correction parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA`
> + * @pathid: 0 for Capture Path 0, 1 for Capture Path 1.
> + * @enable: 1:Enable, 0:Disable settings of L2ISP gamma correction control
> + * @vsplit: Line switching position of first table and second table [line] [0..4094].
> + * Should set 0 in case 0 is set to @enable
> + * @mode: &enum viif_gamma_mode value.
> + * Should set VIIF_GAMMA_COMPRESSED when 0 is set to @enable
> + * @table_addr: Address to gamma table for L2ISP gamma.
> + * The table has 6 channels;
> + * [0]: G/Y(1st table), [1]: G/Y(2nd table), [2]: B/U(1st table)
> + * [3]: B/U(2nd table), [4]: R/V(1st table), [5]: R/V(2nd table)
> + * Each channel of the table is __u16 typed and 512 bytes.
> + */
> +struct viif_l2_gamma_config {
> + __u32 pathid;
> + __u32 enable;
> + __u32 vsplit;
> + __u32 mode;
> + __u64 table_addr[6];
> +};
> +
> +/**
> + * enum viif_csi2_cal_status - CSI2RX calibration status
> + *
> + * @VIIF_CSI2_CAL_NOT_DONE: Calibration not complete
> + * @VIIF_CSI2_CAL_SUCCESS: Calibration success
> + * @VIIF_CSI2_CAL_FAIL: Calibration failed
> + */
> +enum viif_csi2_cal_status {
> + VIIF_CSI2_CAL_NOT_DONE = 0,
> + VIIF_CSI2_CAL_SUCCESS = 1,
> + VIIF_CSI2_CAL_FAIL = 2,
> +};
> +
> +/**
> + * struct viif_csi2rx_dphy_calibration_status - CSI2-RX D-PHY Calibration
> + * information for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS`
> + * @term_cal_with_rext: Result of termination calibration with rext
> + * @clock_lane_offset_cal: Result of offset calibration of clock lane
> + * @data_lane0_offset_cal: Result of offset calibration of data lane0
> + * @data_lane1_offset_cal: Result of offset calibration of data lane1
> + * @data_lane2_offset_cal: Result of offset calibration of data lane2
> + * @data_lane3_offset_cal: Result of offset calibration of data lane3
> + * @data_lane0_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane0
> + * @data_lane1_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane1
> + * @data_lane2_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane2
> + * @data_lane3_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane3
> + *
> + * Values for each member is typed &enum viif_csi2_cal_status.
> + */
> +struct viif_csi2rx_dphy_calibration_status {
> + __u32 term_cal_with_rext;
> + __u32 clock_lane_offset_cal;
> + __u32 data_lane0_offset_cal;
> + __u32 data_lane1_offset_cal;
> + __u32 data_lane2_offset_cal;
> + __u32 data_lane3_offset_cal;
> + __u32 data_lane0_ddl_tuning_cal;
> + __u32 data_lane1_ddl_tuning_cal;
> + __u32 data_lane2_ddl_tuning_cal;
> + __u32 data_lane3_ddl_tuning_cal;
> +};
> +
> +/**
> + * struct viif_csi2rx_err_status - CSI2RX Error status parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS`
> + * @err_phy_fatal: D-PHY FATAL error.
> + *
> + * * bit[3]: Start of transmission error on DATA Lane3.
> + * * bit[2]: Start of transmission error on DATA Lane2.
> + * * bit[1]: Start of transmission error on DATA Lane1.
> + * * bit[0]: Start of transmission error on DATA Lane0.
> + * @err_pkt_fatal: Packet FATAL error.
> + *
> + * * bit[16]: Header ECC contains 2 errors, unrecoverable.
> + * * bit[3]: Checksum error detected on virtual channel 3.
> + * * bit[2]: Checksum error detected on virtual channel 2.
> + * * bit[1]: Checksum error detected on virtual channel 1.
> + * * bit[0]: Checksum error detected on virtual channel 0.
> + * @err_frame_fatal: Frame FATAL error.
> + *
> + * * bit[19]: Last received Frame, in virtual channel 3, has at least one CRC error.
> + * * bit[18]: Last received Frame, in virtual channel 2, has at least one CRC error.
> + * * bit[17]: Last received Frame, in virtual channel 1, has at least one CRC error.
> + * * bit[16]: Last received Frame, in virtual channel 0, has at least one CRC error.
> + * * bit[11]: Incorrect Frame Sequence detected in virtual channel 3.
> + * * bit[10]: Incorrect Frame Sequence detected in virtual channel 2.
> + * * bit[9]: Incorrect Frame Sequence detected in virtual channel 1.
> + * * bit[8]: Incorrect Frame Sequence detected in virtual channel 0.
> + * * bit[3]: Error matching Frame Start with Frame End for virtual channel 3.
> + * * bit[2]: Error matching Frame Start with Frame End for virtual channel 2.
> + * * bit[1]: Error matching Frame Start with Frame End for virtual channel 1.
> + * * bit[0]: Error matching Frame Start with Frame End for virtual channel 0.
> + * @err_phy: D-PHY error.
> + *
> + * * bit[19]: Escape Entry Error on Data Lane 3.
> + * * bit[18]: Escape Entry Error on Data Lane 2.
> + * * bit[17]: Escape Entry Error on Data Lane 1.
> + * * bit[16]: Escape Entry Error on Data Lane 0.
> + * * bit[3]: Start of Transmission Error on Data Lane 3 (synchronization can still be achieved).
> + * * bit[2]: Start of Transmission Error on Data Lane 2 (synchronization can still be achieved).
> + * * bit[1]: Start of Transmission Error on Data Lane 1 (synchronization can still be achieved).
> + * * bit[0]: Start of Transmission Error on Data Lane 0 (synchronization can still be achieved).
> + * @err_pkt: Packet error.
> + *
> + * * bit[19]: Header Error detected and corrected on virtual channel 3.
> + * * bit[18]: Header Error detected and corrected on virtual channel 2.
> + * * bit[17]: Header Error detected and corrected on virtual channel 1.
> + * * bit[16]: Header Error detected and corrected on virtual channel 0.
> + * * bit[3]: Unrecognized or unimplemented data type detected in virtual channel 3.
> + * * bit[2]: Unrecognized or unimplemented data type detected in virtual channel 2.
> + * * bit[1]: Unrecognized or unimplemented data type detected in virtual channel 1.
> + * * bit[0]: Unrecognized or unimplemented data type detected in virtual channel 0.
> + * @err_line: Line error.
> + *
> + * * bit[23]: Error in the sequence of lines for vc7 and dt7.
> + * * bit[22]: Error in the sequence of lines for vc6 and dt6.
> + * * bit[21]: Error in the sequence of lines for vc5 and dt5.
> + * * bit[20]: Error in the sequence of lines for vc4 and dt4.
> + * * bit[19]: Error in the sequence of lines for vc3 and dt3.
> + * * bit[18]: Error in the sequence of lines for vc2 and dt2.
> + * * bit[17]: Error in the sequence of lines for vc1 and dt1.
> + * * bit[16]: Error in the sequence of lines for vc0 and dt0.
> + * * bit[7]: Error matching Line Start with Line End for vc7 and dt7.
> + * * bit[6]: Error matching Line Start with Line End for vc6 and dt6.
> + * * bit[5]: Error matching Line Start with Line End for vc5 and dt5.
> + * * bit[4]: Error matching Line Start with Line End for vc4 and dt4.
> + * * bit[3]: Error matching Line Start with Line End for vc3 and dt3.
> + * * bit[2]: Error matching Line Start with Line End for vc2 and dt2.
> + * * bit[1]: Error matching Line Start with Line End for vc1 and dt1.
> + * * bit[0]: Error matching Line Start with Line End for vc0 and dt0.
> + */
> +struct viif_csi2rx_err_status {
> + __u32 err_phy_fatal;
> + __u32 err_pkt_fatal;
> + __u32 err_frame_fatal;
> + __u32 err_phy;
> + __u32 err_pkt;
> + __u32 err_line;
> +};
> +
> +/**
> + * struct viif_l1_info - L1ISP AWB information
> + * for &struct viif_isp_capture_status
> + * @avg_lum_weight: weighted average luminance value at average luminance generation
> + * @avg_lum_block: average luminance of each block [y][x]:
> + * y means vertical position and x means horizontal position
> + * @avg_lum_four_line_lum: 4-lines average luminance.
> + * avg_lum_four_line_lum[n] corresponds to aexp_ave4linesy[n]
> + * @avg_satur_pixnum: the number of saturated pixel at average luminance generation
> + * @avg_black_pixnum: the number of black pixel at average luminance generation
> + * @awb_ave_u: U average value of AWB adjustment [pixel]
> + * @awb_ave_v: V average value of AWB adjustment [pixel]
> + * @awb_accumulated_pixel: Accumulated pixel count of AWB adjustment
> + * @awb_gain_r: R gain used in the next frame of AWB adjustment
> + * @awb_gain_g: G gain used in the next frame of AWB adjustment
> + * @awb_gain_b: B gain used in the next frame of AWB adjustment
> + * @awb_status_u: boolean value of U convergence state of AWB adjustment
> + * (0: not-converged, 1: converged)
> + * @awb_status_v: boolean value of V convergence state of AWB adjustment
> + * (0: not-converged, 1: converged)
> + */
> +struct viif_l1_info {
> + __u32 avg_lum_weight;
> + __u32 avg_lum_block[8][8];
> + __u32 avg_lum_four_line_lum[4];
> + __u32 avg_satur_pixnum;
> + __u32 avg_black_pixnum;
> + __u32 awb_ave_u;
> + __u32 awb_ave_v;
> + __u32 awb_accumulated_pixel;
> + __u32 awb_gain_r;
> + __u32 awb_gain_g;
> + __u32 awb_gain_b;
> + __u8 awb_status_u;
> + __u8 awb_status_v;
> +};
> +
> +/**
> + * struct viif_isp_capture_status - L1ISP capture information
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS`
> + * @l1_info: L1ISP AWB information. Refer to &struct viif_l1_info
> + */
> +struct viif_isp_capture_status {
> + struct viif_l1_info l1_info;
> +};
> +
> +/**
> + * struct viif_reported_errors - Errors since last call
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS`
> + * @main: error flag value for capture device 0 and 1
> + * @sub: error flag value for capture device 2
> + * @csi2rx: error flag value for CSI2 receiver
> + */
> +struct viif_reported_errors {
> + __u32 main;
> + __u32 sub;
> + __u32 csi2rx;
> +};
> +
> +#endif /* __UAPI_VISCONTI_VIIF_H_ */
Regards,
Hans
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-17 10:01 ` Hans Verkuil
@ 2023-01-25 12:12 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-25 12:12 UTC (permalink / raw)
To: hverkuil, laurent.pinchart, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
Hello Hans,
Thank you for your comments.
> -----Original Message-----
> From: Hans Verkuil <hverkuil@xs4all.nl>
> Sent: Tuesday, January 17, 2023 7:01 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>; Mauro Carvalho Chehab
> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>
> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver
>
> Hi Yuji,
>
> Some review comments below:
>
> On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > The interface device includes CSI2 Receiver,
> > frame grabber, video DMAC and image signal processor.
> > This patch provides operations to handle registers of HW listed above.
> >
> > The Video DMACs have 32bit address space
> > and currently corresponding IOMMU driver is not provided.
> > Therefore, memory-block address for captured image is 32bit IOVA
> > which is equal to 32bit-truncated phisical address.
> > When the Visconti IOMMU driver (currently under development) is accepted,
> > the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
> >
> > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > ---
> > Changelog v2:
> > - Resend v1 because a patch exceeds size limit.
> >
> > Changelog v3:
> > - Adapted to media control framework
> > - Introduced ISP subdevice, capture device
> > - Remove private IOCTLs and add vendor specific V4L2 controls
> > - Change function name avoiding camelcase and uppercase letters
> >
> > Changelog v4:
> > - Split patches because the v3 patch exceeds size limit
> > - Stop using ID number to identify driver instance:
> > - Use dynamically allocated structure to hold driver's context,
> > instead of static one indexed by ID number.
> > - Functions accept driver's context structure instead of ID number.
> >
> > Changelog v5:
> > - no change
> > ---
> > drivers/media/platform/Kconfig | 1 +
> > drivers/media/platform/Makefile | 1 +
> > drivers/media/platform/visconti/Kconfig | 9 +
> > drivers/media/platform/visconti/Makefile | 8 +
> > drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
> > drivers/media/platform/visconti/hwd_viif.h | 710 +++++
> > .../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
> > .../platform/visconti/hwd_viif_internal.h | 340 ++
> > .../media/platform/visconti/hwd_viif_reg.h | 2802
> +++++++++++++++++
> > include/uapi/linux/visconti_viif.h | 1724 ++++++++++
> > 10 files changed, 7895 insertions(+)
> > create mode 100644 drivers/media/platform/visconti/Kconfig
> > create mode 100644 drivers/media/platform/visconti/Makefile
> > create mode 100644 drivers/media/platform/visconti/hwd_viif.c
> > create mode 100644 drivers/media/platform/visconti/hwd_viif.h
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
> > create mode 100644 include/uapi/linux/visconti_viif.h
> >
> > diff --git a/drivers/media/platform/Kconfig
> b/drivers/media/platform/Kconfig
> > index a9334263fa9..0908158036d 100644
> > --- a/drivers/media/platform/Kconfig
> > +++ b/drivers/media/platform/Kconfig
> > @@ -83,6 +83,7 @@ source "drivers/media/platform/sunxi/Kconfig"
> > source "drivers/media/platform/ti/Kconfig"
> > source "drivers/media/platform/verisilicon/Kconfig"
> > source "drivers/media/platform/via/Kconfig"
> > +source "drivers/media/platform/visconti/Kconfig"
>
> We're moving towards a "drivers/media/platform/<vendor>/<model>/"
> directory
> structure, so it is better to move this driver to .../platform/toshiba/visconti/.
I'll move files to media/platform/toshiba/visconti/
> > source "drivers/media/platform/xilinx/Kconfig"
> >
> > endif # MEDIA_PLATFORM_DRIVERS
> > diff --git a/drivers/media/platform/Makefile
> b/drivers/media/platform/Makefile
> > index a91f4202427..1c67cb56244 100644
> > --- a/drivers/media/platform/Makefile
> > +++ b/drivers/media/platform/Makefile
> > @@ -26,6 +26,7 @@ obj-y += sunxi/
> > obj-y += ti/
> > obj-y += verisilicon/
> > obj-y += via/
> > +obj-y += visconti/
> > obj-y += xilinx/
> >
> > # Please place here only ancillary drivers that aren't SoC-specific
> > diff --git a/drivers/media/platform/visconti/Kconfig
> b/drivers/media/platform/visconti/Kconfig
> > new file mode 100644
> > index 00000000000..031e4610809
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/Kconfig
> > @@ -0,0 +1,9 @@
> > +config VIDEO_VISCONTI_VIIF
> > + tristate "Visconti Camera Interface driver"
> > + depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER &&
> VIDEO_DEV
> > + depends on ARCH_VISCONTI
>
> This should be: depends on ARCH_VISCONTI || COMPILE_TEST
>
> We want to be able to compile this driver for other platforms as well.
I'll fix it.
> > + select VIDEOBUF2_DMA_CONTIG
> > + select V4L2_FWNODE
> > + help
> > + This is V4L2 driver for Toshiba Visconti Camera Interface driver
> > +
> > diff --git a/drivers/media/platform/visconti/Makefile
> b/drivers/media/platform/visconti/Makefile
> > new file mode 100644
> > index 00000000000..e14b904df75
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/Makefile
> > @@ -0,0 +1,8 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +#
> > +# Makefile for the Visconti video input device driver
> > +#
> > +
> > +visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> > +
> > +obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> > diff --git a/drivers/media/platform/visconti/hwd_viif.c
> b/drivers/media/platform/visconti/hwd_viif.c
> > new file mode 100644
> > index 00000000000..260293fa4d0
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif.c
> > @@ -0,0 +1,1690 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
>
> It's odd to see two copyrights from what looks like the same company.
> Just checking: is this correct?
Yes. Both Toshiba company and Toshiba semiconductor device company are involved.
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "hwd_viif.h"
> > +#include "hwd_viif_internal.h"
> > +
> > +/* MIPI CSI2 DataType definition */
> > +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> > +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> > +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> > +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> > +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> > +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> > +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> > +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
> > +
> > +struct hwd_viif_res *allocate_viif_res(struct device *dev, void
> *csi2host_vaddr,
> > + void *capture_vaddr)
> > +{
> > + struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res),
> GFP_KERNEL);
> > +
> > + res->csi2host_reg = csi2host_vaddr;
> > + res->capture_reg = capture_vaddr;
> > + res->run_flag_main = (bool)false;
> > + return res;
> > +}
> > +
> > +/* Convert the unit of time-period (from sysclk, to num lines in the image) */
> > +static u32 sysclk_to_numlines(u64 time_in_sysclk, const struct
> hwd_viif_input_img *img)
> > +{
> > + u64 v1 = time_in_sysclk * (u64)img->pixel_clock;
> > + u64 v2 = (u64)img->htotal_size * HWD_VIIF_SYS_CLK;
> > +
> > + return (u32)(v1 / v2);
>
> Use div64_u64 instead so it will compile on platforms without native 64 bit
> division support.
I'll use div64_u64.
> > +}
> > +
> > +static u32 lineperiod_in_sysclk(u64 hsize, u64 pixel_clock)
> > +{
> > + return (u32)(hsize * HWD_VIIF_SYS_CLK / pixel_clock);
>
> Ditto.
Same as above. I'll use div64_u64.
> > +}
>
> <snip>
>
> > diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h
> b/drivers/media/platform/visconti/hwd_viif_internal.h
> > new file mode 100644
> > index 00000000000..c954e804946
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_internal.h
> > @@ -0,0 +1,340 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_INTERNAL_H
> > +#define HWD_VIIF_INTERNAL_H
> > +
> > +#include "hwd_viif_reg.h"
> > +
> > +#define HWD_VIIF_CSI2_MAX_VC (3U)
> > +#define HWD_VIIF_CSI2_MIN_DT (0x10U)
> > +#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
> > +#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
> > +#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
> > +#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
> > +#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
> > +#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
> > +#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
> > +
> > +/* maximum horizontal/vertical position/dimension of CROP with ISP */
> > +#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
> > +#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
> > +#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
> > +#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
> > +
> > +/* maximum horizontal/vertical position/dimension of CROP without ISP */
> > +#define HWD_VIIF_CROP_MAX_X (1920U)
> > +#define HWD_VIIF_CROP_MAX_Y (1408U)
> > +#define HWD_VIIF_CROP_MIN_W (128U)
> > +#define HWD_VIIF_CROP_MAX_W (2048U)
> > +#define HWD_VIIF_CROP_MIN_H (128U)
> > +#define HWD_VIIF_CROP_MAX_H (1536U)
> > +
> > +/* pixel clock: [kHz] */
> > +#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
> > +#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
> > +
> > +/* picture size: [pixel], [ns] */
> > +#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
> > +#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
> > +#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
> > +#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
> > +
> > +/* horizontal back porch size: [system clock] */
> > +#define HWD_VIIF_HBP_SYSCLK (10U)
> > +
> > +/* active picture size: [pixel] */
> > +#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
> > +#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
> > +#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
> > +#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
> > +
> > +/* picture vertical size: [line], [packet] */
> > +#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
> > +#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
> > +#define HWD_VIIF_MIN_VBP_LINE (5U)
> > +#define HWD_VIIF_MAX_VBP_LINE (4095U)
> > +#define HWD_VIIF_MIN_VBP_PACKET (5U)
> > +#define HWD_VIIF_MAX_VBP_PACKET (4095U)
> > +#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
> > +#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
> > +#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
> > +#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
> > +
> > +/* image source select */
> > +#define HWD_VIIF_INPUT_CSI2 (0U)
> > +
> > +#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
> > +#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
> > +#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
> > +#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
> > +#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MAX_PITCH_ISP (32704U)
> > +#define HWD_VIIF_MAX_PITCH (65536U)
> > +
> > +/* size of minimum/maximum input image */
> > +#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
> > +#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
> > +#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
> > +
> > +/* size of minimum/maximum output image */
> > +#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> > +
> > +#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> > +
> > +#define HWD_VIIF_NO_EVENT (0x0U)
> > +
> > +/* System clock: [kHz] */
> > +#define HWD_VIIF_SYS_CLK (500000UL)
> > +
> > +/*
> > + * wait time for force abort to complete(max 1line time = 1228.8[us]
> > + * when width = 4096, RAW24, 80Mbps
> > + */
> > +#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
> > +
> > +/*
> > + * complete time of register buffer transfer.
> > + * actual time is about 30us in case of L1ISP
> > + */
> > +#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
> > +
> > +/* internal operation latencies: [system clock]*/
> > +#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
> > +#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
> > +
> > +/* offset of Vsync delay: [line] */
> > +#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
> > +#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
> > +
> > +/* data width is 32bit */
> > +#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
> > +
> > +/* vsync mode is pulse */
> > +#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
> > +
> > +/* Vlatch mask bit for L1ISP and L2ISP */
> > +#define HWD_VIIF_ISP_VLATCH_MASK (2U)
> > +
> > +/* Register buffer */
> > +#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
> > +#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
> > +#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
> > +#define HWD_VIIF_ISP_REGBUF_READ (1U)
> > +
> > +/* constants for L1 ISP*/
> > +#define HWD_VIIF_L1_INPUT_MODE_NUM (5U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_MIN (8U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_MAX (24U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_SDR_MAX
> (12U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX
> (14U)
> > +#define HWD_VIIF_L1_RAW_MODE_NUM (4U)
> > +#define HWD_VIIF_L1_INPUT_NUM_MIN (1U)
> > +#define HWD_VIIF_L1_INPUT_NUM_MAX (3U)
> > +#define HWD_VIIF_L1_AG_ID_NUM (4U)
> > +#define HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM (3U)
> > +#define HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL (0x3fffU)
> > +#define HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL (0xffffffU)
> > +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL (0xffffffU)
> > +#define HWD_VIIF_L1_OBCC_MAX_AG_VAL (511U)
> > +#define HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL
> (0xffffffU)
> > +#define HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL (1023U)
> > +#define HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL (1U)
> > +#define HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL (31U)
> > +#define HWD_VIIF_L1_VDM_ALIGN (0x8U) /*
> port interface width is 64bit */
> > +#define HWD_VIIF_L1_VDM_CFG_PARAM
> (0x00000310U) /* data width is 64bit */
> > +#define HWD_VIIF_L1_VDM_SRAM_BASE
> (0x00000600U)
> > +#define HWD_VIIF_L1_VDM_SRAM_SIZE
> (0x00000020U)
> > +#define HWD_VIIF_L1_VDM_DPC_TABLE_SIZE
> (0x2000U)
> > +#define HWD_VIIF_L1_VDM_LSC_TABLE_SIZE
> (0x600U)
> > +#define HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL (4095U)
> > +#define HWD_VIIF_L1_PWHB_MAX_GAIN_VAL
> (0x80000U)
> > +#define HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL
> (63U)
> > +#define HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL
> (31U)
> > +#define HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL (3U)
> > +#define HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL (256U)
> > +#define HWD_VIIF_L1_RCNR_MAX_BLEND_VAL
> (16U)
> > +#define HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL
> (64U)
> > +#define HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL (4U)
> > +#define HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL
> (16U)
> > +#define HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL
> (32U)
> > +#define HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL
> (2U)
> > +#define HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO
> (15U)
> > +#define HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO (0x400U)
> > +#define HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL (0xffffffU)
> > +#define HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL (4095U)
> > +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL
> (0xffffffU)
> > +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL
> (0x100000U)
> > +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL
> (0xffffffU)
> > +#define HWD_VIIF_LSC_MIN_GAIN (-4096)
> > +#define HWD_VIIF_LSC_MAX_GAIN (4096)
> > +#define HWD_VIIF_LSC_GRID_MIN_COORDINATE (1U)
> > +#define HWD_VIIF_LSC_PWB_MAX_COEF_VAL
> (0x800U)
> > +#define HWD_VIIF_DAMP_MAX_LSBSEL (15U)
> > +#define HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL
> (0xffffffU)
> > +#define HWD_VIIF_AWB_MIN_GAIN (64U)
> > +#define HWD_VIIF_AWB_MAX_GAIN (1024U)
> > +#define HWD_VIIF_AWB_GATE_LOWER
> (-127)
> > +#define HWD_VIIF_AWB_GATE_UPPER
> (127)
> > +#define HWD_VIIF_AWB_UNSIGNED_GATE_UPPER (127U)
> > +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED
> (15U)
> > +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL
> (31U)
> > +#define HWD_VIIF_AWB_INTEGRATION_STOP_TH (1023U)
> > +#define HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL
> (8U)
> > +#define HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH
> (10U)
> > +#define HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH
> (24U)
> > +#define HWD_VIIF_L1_HDRC_MAX_PT_SLOPE
> (13U)
> > +#define HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO (256U)
> > +#define HWD_VIIF_L1_HDRC_MAX_FLARE_VAL
> (0xffffffU)
> > +#define HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA
> (16U)
> > +#define HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION
> (0x4000U)
> > +#define HWD_VIIF_L1_HDRC_RATIO_OFFSET
> (10U)
> > +#define HWD_VIIF_L1_GAMMA_MAX_VAL (8191U)
> > +#define HWD_VIIF_L1_SUPPRESSION_MAX_VAL
> (0x4000U)
> > +#define HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT
> (15U)
> > +#define HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN (0x1000U)
> > +#define HWD_VIIF_L1_AEXP_MAX_WEIGHT (3U)
> > +#define HWD_VIIF_L1_AEXP_MAX_BLOCK_TH
> (256U)
> > +#define HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH (0xffffffU)
> > +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH (64U)
> > +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT (64U)
> > +#define HWD_VIIF_L1_HIST_COLOR_RGBY (2U)
> > +#define HWD_VIIF_L1_HIST_MAX_BLOCK_NUM
> (8U)
> > +#define HWD_VIIF_L1_HIST_MAX_STEP (15U)
> > +#define HWD_VIIF_L1_HIST_MAX_BIN_SHIFT
> (31U)
> > +#define HWD_VIIF_L1_HIST_MAX_COEF (65536U)
> > +#define HWD_VIIF_L1_HIST_MIN_ADD_B_COEF
> (-65536)
> > +#define HWD_VIIF_L1_HIST_MIN_ADD_A_COEF
> (-16777216)
> > +#define HWD_VIIF_L1_HIST_MAX_ADD_A_COEF
> (16777216)
> > +#define HWD_VIIF_L1_HIST_VDM_SIZE (4096U)
> > +#define HWD_VIIF_L1_HIST_VDM_SRAM_BASE
> (0x00000400U)
> > +#define HWD_VIIF_L1_HIST_VDM_SRAM_SIZE
> (0x00000040U)
> > +#define HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT
> (0x0200U)
> > +#define HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT (0x10BFU)
> > +#define HWD_VIIF_L1_COEF_MIN (256U)
> > +#define HWD_VIIF_L1_COEF_MAX (65024U)
> > +
> > +/* constants for L2 ISP */
> > +#define HWD_VIIF_L2_VDM_ALIGN (0x4U)
> > +#define HWD_VIIF_L2_VDM_GRID_SRAM_BASE
> (0x00000620U)
> > +#define HWD_VIIF_L2_VDM_GRID_SRAM_SIZE
> (0x00000020U)
> > +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE
> (0x00000640U)
> > +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE
> (0x00000020U)
> > +#define HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE (0x00000200U)
> > +#define HWD_VIIF_L2_UNDIST_POLY_NUM (11U)
> > +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H (-4296)
> > +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H (4296)
> > +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V (-2360)
> > +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V (2360)
> > +#define HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE (1677721U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2
> (0x4000000U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA
> (0x800U)
> > +#define HWD_VIIF_L2_UNDIST_MIN_POLY_COEF (-2147352576)
> > +#define HWD_VIIF_L2_UNDIST_MAX_POLY_COEF (2147352576)
> > +#define HWD_VIIF_L2_UNDIST_MIN_GRID_NUM (16U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_GRID_NUM (64U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM
> (2048U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV
> (0x800000U)
> > +#define HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE (0x400U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE (0x2000U)
> > +#define HWD_VIIF_L2_ROI_MIN_NUM (1U)
> > +#define HWD_VIIF_L2_ROI_MAX_NUM (2U)
> > +#define HWD_VIIF_L2_ROI_MIN_SCALE (32768U)
> > +#define HWD_VIIF_L2_ROI_MAX_SCALE (131072U)
> > +#define HWD_VIIF_L2_ROI_MIN_SCALE_INV (32768U)
> > +#define HWD_VIIF_L2_ROI_MAX_SCALE_INV (131072U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE
> (8190U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE (4094U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE (8190U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE (4094U)
> > +#define HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT
> (0x1CU)
> > +#define HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT (0x1FU)
> > +#define HWD_VIIF_L2_ROI_NONE (3U)
> > +#define HWD_VIIF_MAX_POST_NUM (2U)
> > +#define HWD_VIIF_L2_INPUT_OTHER_CH (0x50U)
> > +
> > +/**
> > + * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
> > + *
> > + * @roi_num: the number of ROIs which are used.
> > + * @post_enable_flag: flag to show which of POST is enabled.
> > + * @post_crop_x: CROP x of each L2ISP POST
> > + * @post_crop_y: CROP y of each L2ISP POST
> > + * @post_crop_w: CROP w of each L2ISP POST
> > + * @post_crop_h: CROP h of each L2ISP POST
> > + */
> > +struct hwd_viif_l2_roi_path_info {
> > + u32 roi_num;
> > + bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_res - driver internal resource structure
> > + *
> > + * @clock_id: clock ID of each unit
> > + * @csi2_clock_id: clock ID of CSI-2 RX
> > + * @csi2_reset_id: reset ID of CSI-2 RX
> > + * @pixel_clock: pixel clock
> > + * @htotal_size: horizontal total size
> > + * @dt_image_main_w_isp: Data type of image data for ISP path
> > + * @csi2host_reg: pointer to register access structure of CSI-2 RX host
> controller
> > + * @capture_reg: pointer to register access structure of capture unit
> > + * @l2_roi_path_info: ROI path information of L2ISP
> > + * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
> > + */
> > +struct hwd_viif_res {
> > + //u32 clock_id;
> > + //u32 csi2_clock_id;
> > + //u32 csi2_reset_id;
>
> These are commented out, but they are still present in the kerneldoc above.
>
> Any reason why these three fields aren't just removed?
I'll remove these members.
They are only for experiments and should not be here.
> > + u32 pixel_clock;
> > + u32 htotal_size;
> > + u32 dt_image_main_w_isp;
> > + struct hwd_viif_csi2host_reg *csi2host_reg;
> > + struct hwd_viif_capture_reg *capture_reg;
> > + struct hwd_viif_l2_roi_path_info l2_roi_path_info;
> > + bool run_flag_main;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_dphy_hs_info - dphy hs information
> > + *
> > + * @rate: Data rate [Mbps]
> > + * @hsfreqrange: IP operating frequency(hsfreqrange)
> > + * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
> > + */
> > +struct hwd_viif_dphy_hs_info {
> > + u32 rate;
> > + u32 hsfreqrange;
> > + u32 osc_freq_target;
> > +};
> > +
> > +#endif /* HWD_VIIF_INTERNAL_H */
>
> <snip>
>
> > diff --git a/include/uapi/linux/visconti_viif.h
> b/include/uapi/linux/visconti_viif.h
> > new file mode 100644
> > index 00000000000..f92278425b7
> > --- /dev/null
> > +++ b/include/uapi/linux/visconti_viif.h
> > @@ -0,0 +1,1724 @@
> > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef __UAPI_VISCONTI_VIIF_H_
> > +#define __UAPI_VISCONTI_VIIF_H_
> > +
> > +#include <linux/types.h>
> > +#include <linux/videodev2.h>
> > +
> > +/* Visconti specific compound controls */
> > +#define V4L2_CID_VISCONTI_VIIF_BASE
> (V4L2_CID_USER_BASE + 0x1000)
>
> You need to reserve a range for Visconti controls in the v4l2-controls.h header.
> See e.g. V4L2_CID_USER_DW100_BASE. That ensures that these controls have
> unique
> IDs, not used by other drivers.
All right. I'll reserve controls at v4l2-controls.h.
> > +#define V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE
> (V4L2_CID_VISCONTI_VIIF_BASE + 1)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE
> (V4L2_CID_VISCONTI_VIIF_BASE + 2)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF
> (V4L2_CID_VISCONTI_VIIF_BASE + 3)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE
> (V4L2_CID_VISCONTI_VIIF_BASE + 4)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG
> (V4L2_CID_VISCONTI_VIIF_BASE + 5)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE
> (V4L2_CID_VISCONTI_VIIF_BASE + 6)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION
> (V4L2_CID_VISCONTI_VIIF_BASE + 7)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC
> (V4L2_CID_VISCONTI_VIIF_BASE + 8)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE
> (V4L2_CID_VISCONTI_VIIF_BASE + 9)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION
> \
> > + (V4L2_CID_VISCONTI_VIIF_BASE + 10)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS
> (V4L2_CID_VISCONTI_VIIF_BASE + 11)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION
> (V4L2_CID_VISCONTI_VIIF_BASE + 12)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC
> (V4L2_CID_VISCONTI_VIIF_BASE + 13)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS
> (V4L2_CID_VISCONTI_VIIF_BASE + 14)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB
> (V4L2_CID_VISCONTI_VIIF_BASE + 15)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN
> (V4L2_CID_VISCONTI_VIIF_BASE + 16)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC
> (V4L2_CID_VISCONTI_VIIF_BASE + 17)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM
> (V4L2_CID_VISCONTI_VIIF_BASE + 18)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA
> (V4L2_CID_VISCONTI_VIIF_BASE + 19)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT
> (V4L2_CID_VISCONTI_VIIF_BASE + 20)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION
> (V4L2_CID_VISCONTI_VIIF_BASE + 21)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST
> (V4L2_CID_VISCONTI_VIIF_BASE + 22)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI
> (V4L2_CID_VISCONTI_VIIF_BASE + 23)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA
> (V4L2_CID_VISCONTI_VIIF_BASE + 24)
> > +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS
> (V4L2_CID_VISCONTI_VIIF_BASE + 25)
> > +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS
> (V4L2_CID_VISCONTI_VIIF_BASE + 26)
> > +#define V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS
> (V4L2_CID_VISCONTI_VIIF_BASE + 27)
> > +#define V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS
> (V4L2_CID_VISCONTI_VIIF_BASE + 28)
>
> These controls need to be documented: what do they do, what arguments do
> they have.
>
> Take a look at v4l2-controls.h, for example the
> V4L2_CID_STATELESS_VP9_COMPRESSED_HDR
> define. The data structure it takes is just above the CID define, so it is already
> much easier to see what the control takes as value.
I understand the format. I'll add document to each control.
> But in this case it needs a bit more since these controls are not documented in
> the
> V4L2 spec, so you will have to do that here as well. I.e., describe what the control
> does.
Simple description for each control is in Documentation/driver-api/media/drivers/index.rst
which is provided in patch 5/6. Do we need more detailed information?
> Does the driver configure these controls to sensible default values when it is
> first loaded?
No. Currently, HW registers keep their initial value if ioctl(VIDIOC_S_EXT_CTRLS) is not explicitly called.
I think there should be default value for each control.
To keep compatibility, the default values will be corresponding to HW's initial value.
> Also, if there is public documentation available, then add a URL to it at the top of
> this header.
Sorry. No public documentation for ISP function has been released.
> > +
> > +/* Enable/Disable flag */
> > +#define VIIF_DISABLE (0U)
> > +#define VIIF_ENABLE (1U)
> > +
> > +/**
> > + * enum viif_rawpack_mode - RAW pack mode for
> ioctl(VIDIOC_VIIF_MAIN_SET_RAWPACK_MODE)
> > + *
> > + * @VIIF_RAWPACK_DISABLE: RAW pack disable
> > + * @VIIF_RAWPACK_MSBFIRST: RAW pack enable (MSB First)
> > + * @VIIF_RAWPACK_LSBFIRST: RAW pack enable (LSB First)
> > + */
> > +enum viif_rawpack_mode {
> > + VIIF_RAWPACK_DISABLE = 0,
> > + VIIF_RAWPACK_MSBFIRST = 2,
> > + VIIF_RAWPACK_LSBFIRST = 3,
> > +};
> > +
> > +/**
> > + * enum viif_l1_input - L1ISP preprocessing mode
> > + *
> > + * @VIIF_L1_INPUT_HDR: bypass(HDR input)
> > + * @VIIF_L1_INPUT_PWL: HDRE(PWL input)
> > + * @VIIF_L1_INPUT_HDR_IMG_CORRECT: SLIC-ABPC-PWHB-RCNR-HDRS
> > + * @VIIF_L1_INPUT_PWL_IMG_CORRECT:
> HDRE-SLIC-ABPC-PWHB-RCNR-HDRS
> > + */
> > +enum viif_l1_input {
> > + VIIF_L1_INPUT_HDR = 0,
> > + VIIF_L1_INPUT_PWL = 1,
> > + VIIF_L1_INPUT_HDR_IMG_CORRECT = 3,
> > + VIIF_L1_INPUT_PWL_IMG_CORRECT = 4,
> > +};
> > +
> > +/**
> > + * enum viif_l1_raw - L1ISP RAW color filter mode
> > + *
> > + * @VIIF_L1_RAW_GR_R_B_GB: Gr-R-B-Gb
> > + * @VIIF_L1_RAW_R_GR_GB_B: R-Gr-Gb-B
> > + * @VIIF_L1_RAW_B_GB_GR_R: B-Gb-Gr-R
> > + * @VIIF_L1_RAW_GB_B_R_GR: Gb-B-R-Gr
> > + */
> > +enum viif_l1_raw {
> > + VIIF_L1_RAW_GR_R_B_GB = 0,
> > + VIIF_L1_RAW_R_GR_GB_B = 1,
> > + VIIF_L1_RAW_B_GB_GR_R = 2,
> > + VIIF_L1_RAW_GB_B_R_GR = 3,
> > +};
> > +
> > +/**
> > + * struct viif_l1_input_mode_config - L1ISP INPUT MODE parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE`
> > + * @mode: &enum viif_l1_input value.
> > + * @depth: Color depth (even only). Range for each L1ISP pre-processing
> mode is:
> > + *
> > + * * VIIF_L1_INPUT_HDR/HDR_IMG_CORRECT: Range: [8..24].
> > + * * VIIF_L1_INPUT_PWL/PWL_IMG_CORRECT: Range: [8..14].
> > + * @raw_color_filter: &enum viif_l1_raw value.
> > + */
> > +struct viif_l1_input_mode_config {
> > + __u32 mode;
> > + __u32 depth;
> > + __u32 raw_color_filter;
> > +};
> > +
> > +/**
> > + * struct viif_l1_rgb_to_y_coef_config - L1ISP coefficient for calculating
> > + * Y from RGB parameters
> for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF`
> > + * @coef_r: R co-efficient [256..65024] accuracy: 1/65536
> > + * @coef_g: R co-efficient [256..65024] accuracy: 1/65536
> > + * @coef_b: R co-efficient [256..65024] accuracy: 1/65536
> > + */
> > +struct viif_l1_rgb_to_y_coef_config {
> > + __u16 coef_r;
> > + __u16 coef_g;
> > + __u16 coef_b;
> > +};
> > +
> > +/**
> > + * enum viif_l1_img_sensitivity_mode - L1ISP image sensitivity
> > + *
> > + * @VIIF_L1_IMG_SENSITIVITY_HIGH: high sensitivity
> > + * @VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED: middle sensitivity or led
> > + * @VIIF_L1_IMG_SENSITIVITY_LOW: low sensitivity
> > + */
> > +enum viif_l1_img_sensitivity_mode {
> > + VIIF_L1_IMG_SENSITIVITY_HIGH = 0,
> > + VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED = 1,
> > + VIIF_L1_IMG_SENSITIVITY_LOW = 2,
> > +};
> > +
> > +/**
> > + * struct viif_l1_ag_mode_config - L1ISP AG mode parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE`
> > + * @sysm_ag_grad: Analog gain slope [0..255] (element is id)
> > + * @sysm_ag_ofst: Analog gain offset [0..65535] (element is id)
> > + * @sysm_ag_cont_hobc_en_high: 1:enable/0:disable to control analog gain
> > + * for high sensitivity image of OBCC
> > + * @sysm_ag_psel_hobc_high: Analog gain id for high sensitivity image of
> OBCC [0..3]
> > + * @sysm_ag_cont_hobc_en_middle_led: 1:enable/0:disable to control
> analog gain
> > + * for middle sensitivity or LED image
> of OBCC
> > + * @sysm_ag_psel_hobc_middle_led: Analog gain id for middle sensitivity
> > + * or LED image of OBCC [0..3]
> > + * @sysm_ag_cont_hobc_en_low: 1:enable/0:disable to control analog gain
> > + * for low sensitivity image of OBCC
> > + * @sysm_ag_psel_hobc_low: Analog gain id for low sensitivity image of
> OBCC [0..3]
> > + * @sysm_ag_cont_abpc_en_high: 1:enable/0:disable to control analog gain
> > + * for high sensitivity image of ABPC
> > + * @sysm_ag_psel_abpc_high: Analog gain id for high sensitivity image of
> ABPC [0..3]
> > + * @sysm_ag_cont_abpc_en_middle_led: 1:enable/0:disable to control
> analog gain
> > + * for middle sensitivity or LED image
> of ABPC
> > + * @sysm_ag_psel_abpc_middle_led: Analog gain id for middle sensitivity
> > + * or LED image of ABPC [0..3]
> > + * @sysm_ag_cont_abpc_en_low: 1:enable/0:disable to control analog gain
> > + * for low sensitivity image of ABPC
> > + * @sysm_ag_psel_abpc_low: Analog gain id for low sensitivity image of
> ABPC [0..3]
> > + * @sysm_ag_cont_rcnr_en_high: 1:enable/0:disable to control analog gain
> > + * for high sensitivity image of RCNR
> > + * @sysm_ag_psel_rcnr_high: Analog gain id for high sensitivity image of
> RCNR [0..3]
> > + * @sysm_ag_cont_rcnr_en_middle_led: 1:enable/0:disable to control analog
> gain
> > + * for middle sensitivity or LED image
> of RCNR
> > + * @sysm_ag_psel_rcnr_middle_led: Analog gain id for middle sensitivity
> > + * or LED image of RCNR [0..3]
> > + * @sysm_ag_cont_rcnr_en_low: 1:enable/0:disable to control analog gain
> > + * for low sensitivity image of RCNR
> > + * @sysm_ag_psel_rcnr_low: Analog gain id for low sensitivity image of
> RCNR [0..3]
> > + * @sysm_ag_cont_lssc_en: 1:enable/0:disable to control analog gain for LSC
> > + * @sysm_ag_ssel_lssc: &enum viif_l1_img_sensitivity_mode value. Sensitive
> image used for LSC.
> > + * @sysm_ag_psel_lssc: Analog gain id for LSC [0..3]
> > + * @sysm_ag_cont_mpro_en: 1:enable/0:disable to control analog gain for
> color matrix
> > + * @sysm_ag_ssel_mpro: &enum viif_l1_img_sensitivity_mode value.
> > + * Sensitive image used for color matrix.
> > + * @sysm_ag_psel_mpro:Aanalog gain id for color matrix [0..3]
> > + * @sysm_ag_cont_vpro_en: 1:enable/0:disable to control analog gain for
> image adjustment
> > + * @sysm_ag_ssel_vpro: &enum viif_l1_img_sensitivity_mode value.
> > + * Sensitive image used for image adjustment.
> > + * @sysm_ag_psel_vpro: Analog gain id for image adjustment [0..3]
> > + * @sysm_ag_cont_hobc_test_high: Manual analog gain for high sensitivity
> image
> > + * of OBCC [0..255]
> > + * @sysm_ag_cont_hobc_test_middle_led: Manual analog gain for middle
> sensitivity
> > + * or led image of OBCC [0..255]
> > + * @sysm_ag_cont_hobc_test_low: Manual analog gain for low sensitivity
> image
> > + * of OBCC [0..255]
> > + * @sysm_ag_cont_abpc_test_high: Manual analog gain for high sensitivity
> image
> > + * of ABPC [0..255]
> > + * @sysm_ag_cont_abpc_test_middle_led: Manual analog gain for middle
> sensitivity
> > + * or led image of ABPC [0..255]
> > + * @sysm_ag_cont_abpc_test_low: Manual analog gain for low sensitivity
> image
> > + * of ABPC [0..255]
> > + * @sysm_ag_cont_rcnr_test_high: Manual analog gain for high sensitivity
> image
> > + * of RCNR [0..255]
> > + * @sysm_ag_cont_rcnr_test_middle_led: Manual analog gain for middle
> sensitivity
> > + * or led image of RCNR [0..255]
> > + * @sysm_ag_cont_rcnr_test_low: Manual analog gain for low sensitivity
> image
> > + * of RCNR [0..255]
> > + * @sysm_ag_cont_lssc_test: Manual analog gain for LSSC [0..255]
> > + * @sysm_ag_cont_mpro_test: Manual analog gain for color matrix [0..255]
> > + * @sysm_ag_cont_vpro_test: Manual analog gain for image adjustment
> [0..255]
> > + *
> > + * Operation setting of L1ISP analog gain function.
> > + * Analog gain control is disabled if following settings are done.
> > + * "sysm_ag_cont_*_en = DRV_VIIF_DISABLE" and "sysm_ag_cont_*_test =
> 0"
> > + * In case "VIIF_L1_INPUT_HDR" or "VIIF_L1_INPUT_PWL" is set to "mode"
> which is
> > + * an &struct viif_l1_input_mode_config, analog gain control needs to be
> disabled.
> > + * Even if this condition is not satisfied, this driver doesn't return error.
> > + *
> > + * The value set in sysm_ag_psel_xxx indicates analog gain system to be
> used and
> > + * corresponds to the element number of sysm_ag_grad and sysm_ag_ofst.
> > + * For example, if sysm_ag_psel_hobc_high is set to 2, then values set in
> > + * sysm_ag_grad[2] and sysm_ag_ofst[2] are used for high sensitivity images
> > + * in OBCC processing.
> > + */
> > +struct viif_l1_ag_mode_config {
> > + __u8 sysm_ag_grad[4];
> > + __u16 sysm_ag_ofst[4];
> > + __u32 sysm_ag_cont_hobc_en_high;
> > + __u32 sysm_ag_psel_hobc_high;
> > + __u32 sysm_ag_cont_hobc_en_middle_led;
> > + __u32 sysm_ag_psel_hobc_middle_led;
> > + __u32 sysm_ag_cont_hobc_en_low;
> > + __u32 sysm_ag_psel_hobc_low;
> > + __u32 sysm_ag_cont_abpc_en_high;
> > + __u32 sysm_ag_psel_abpc_high;
> > + __u32 sysm_ag_cont_abpc_en_middle_led;
> > + __u32 sysm_ag_psel_abpc_middle_led;
> > + __u32 sysm_ag_cont_abpc_en_low;
> > + __u32 sysm_ag_psel_abpc_low;
> > + __u32 sysm_ag_cont_rcnr_en_high;
> > + __u32 sysm_ag_psel_rcnr_high;
> > + __u32 sysm_ag_cont_rcnr_en_middle_led;
> > + __u32 sysm_ag_psel_rcnr_middle_led;
> > + __u32 sysm_ag_cont_rcnr_en_low;
> > + __u32 sysm_ag_psel_rcnr_low;
> > + __u32 sysm_ag_cont_lssc_en;
> > + __u32 sysm_ag_ssel_lssc;
> > + __u32 sysm_ag_psel_lssc;
> > + __u32 sysm_ag_cont_mpro_en;
> > + __u32 sysm_ag_ssel_mpro;
> > + __u32 sysm_ag_psel_mpro;
> > + __u32 sysm_ag_cont_vpro_en;
> > + __u32 sysm_ag_ssel_vpro;
> > + __u32 sysm_ag_psel_vpro;
> > + __u8 sysm_ag_cont_hobc_test_high;
> > + __u8 sysm_ag_cont_hobc_test_middle_led;
> > + __u8 sysm_ag_cont_hobc_test_low;
> > + __u8 sysm_ag_cont_abpc_test_high;
> > + __u8 sysm_ag_cont_abpc_test_middle_led;
> > + __u8 sysm_ag_cont_abpc_test_low;
> > + __u8 sysm_ag_cont_rcnr_test_high;
> > + __u8 sysm_ag_cont_rcnr_test_middle_led;
> > + __u8 sysm_ag_cont_rcnr_test_low;
> > + __u8 sysm_ag_cont_lssc_test;
> > + __u8 sysm_ag_cont_mpro_test;
> > + __u8 sysm_ag_cont_vpro_test;
> > +};
> > +
> > +/**
> > + * struct viif_l1_ag_config - L1ISP AG parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG`
> > + * @gain_h: Analog gain for high sensitive image [0..65535]
> > + * @gain_m: Analog gain for middle sensitive image or LED image [0..65535]
> > + * @gain_l: Analog gain for low sensitive image [0..65535]
> > + */
> > +struct viif_l1_ag_config {
> > + __u16 gain_h;
> > + __u16 gain_m;
> > + __u16 gain_l;
> > +};
> > +
> > +/**
> > + * struct viif_l1_hdre_config - L1ISP HDRE parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE`
> > + * @hdre_src_point: Knee point N value of PWL compressed signal
> [0..0x3FFF]
> > + * @hdre_dst_base: Offset value of HDR signal in Knee area M
> [0..0xFFFFFF]
> > + * @hdre_ratio: Slope of output pixel value in Knee area M
> > + * [0..0x3FFFFF], accuracy: 1/64
> > + * @hdre_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
> > + */
> > +struct viif_l1_hdre_config {
> > + __u32 hdre_src_point[16];
> > + __u32 hdre_dst_base[17];
> > + __u32 hdre_ratio[17];
> > + __u32 hdre_dst_max_val;
> > +};
> > +
> > +/**
> > + * struct viif_l1_img_extraction_config - L1ISP image extraction parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION`
> > + * @input_black_gr: Black level of input pixel (Gr) [0..0xFFFFFF]
> > + * @input_black_r: Black level of input pixel (R) [0..0xFFFFFF]
> > + * @input_black_b: Black level of input pixel (B) [0..0xFFFFFF]
> > + * @input_black_gb: Black level of input pixel (Gb) [0..0xFFFFFF]
> > + */
> > +struct viif_l1_img_extraction_config {
> > + __u32 input_black_gr;
> > + __u32 input_black_r;
> > + __u32 input_black_b;
> > + __u32 input_black_gb;
> > +};
> > +
> > +/**
> > + * enum viif_l1_dpc_mode - L1ISP defect pixel correction mode
> > + * @VIIF_L1_DPC_1PIXEL: 1 pixel correction mode
> > + * @VIIF_L1_DPC_2PIXEL: 2 pixel correction mode
> > + */
> > +enum viif_l1_dpc_mode {
> > + VIIF_L1_DPC_1PIXEL = 0,
> > + VIIF_L1_DPC_2PIXEL = 1,
> > +};
> > +
> > +/**
> > + * struct viif_l1_dpc - L1ISP defect pixel correction parameters
> > + * for &struct viif_l1_dpc_config
> > + * @abpc_sta_en: 1:enable/0:disable setting of Static DPC
> > + * @abpc_dyn_en: 1:enable/0:disable setting of Dynamic DPC
> > + * @abpc_dyn_mode: &enume viif_l1_dpc_mode value. Sets dynamic DPC
> mode.
> > + * @abpc_ratio_limit: Variation adjustment of dynamic DPC [0..1023]
> > + * @abpc_dark_limit: White defect judgment limit of dark area [0..1023]
> > + * @abpc_sn_coef_w_ag_min: Luminance difference adjustment of white
> DPC
> > + * (undere lower threshold) [1..31]
> > + * @abpc_sn_coef_w_ag_mid: Luminance difference adjustment of white
> DPC
> > + * (between lower and upper threshold) [1..31]
> > + * @abpc_sn_coef_w_ag_max: Luminance difference adjustment of white
> DPC
> > + * (over upper threshold) [1..31]
> > + * @abpc_sn_coef_b_ag_min: Luminance difference adjustment of black
> DPC
> > + * (undere lower threshold) [1..31]
> > + * @abpc_sn_coef_b_ag_mid: Luminance difference adjustment of black
> DPC
> > + * (between lower and upper threshold) [1..31]
> > + * @abpc_sn_coef_b_ag_max: Luminance difference adjustment of black
> DPC
> > + * (over upper threshold) [1..31]
> > + * @abpc_sn_coef_w_th_min: Luminance difference adjustment of white
> DPC
> > + * analog gain lower threshold [0..255]
> > + * @abpc_sn_coef_w_th_max: Luminance difference adjustment of white
> DPC
> > + * analog gain upper threshold [0..255]
> > + * @abpc_sn_coef_b_th_min: Luminance difference adjustment of black DPC
> > + * analog gain lower threshold [0..255]
> > + * @abpc_sn_coef_b_th_max: Luminance difference adjustment of black
> DPC
> > + * analog gain upper threshold [0..255]
> > + *
> > + * Parameters should meet the following conditions.
> > + * "abpc_sn_coef_w_th_min < abpc_sn_coef_w_th_max" and
> > + * "abpc_sn_coef_b_th_min < abpc_sn_coef_b_th_max"
> > + */
> > +struct viif_l1_dpc {
> > + __u32 abpc_sta_en;
> > + __u32 abpc_dyn_en;
> > + __u32 abpc_dyn_mode;
> > + __u32 abpc_ratio_limit;
> > + __u32 abpc_dark_limit;
> > + __u32 abpc_sn_coef_w_ag_min;
> > + __u32 abpc_sn_coef_w_ag_mid;
> > + __u32 abpc_sn_coef_w_ag_max;
> > + __u32 abpc_sn_coef_b_ag_min;
> > + __u32 abpc_sn_coef_b_ag_mid;
> > + __u32 abpc_sn_coef_b_ag_max;
> > + __u8 abpc_sn_coef_w_th_min;
> > + __u8 abpc_sn_coef_w_th_max;
> > + __u8 abpc_sn_coef_b_th_min;
> > + __u8 abpc_sn_coef_b_th_max;
> > +};
> > +
> > +/**
> > + * struct viif_l1_dpc_config - L1ISP defect pixel correction parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC`
> > + * @param_h: DPC parameter for high sensitive image. Refer to &struct
> viif_l1_dpc
> > + * @param_m: DPC parameter for middle sensitive image. Refer to &struct
> viif_l1_dpc
> > + * @param_l: DPC parameter for low sensitive image. Refer to &struct
> viif_l1_dpc
> > + * @table_h_addr: DPC table address for high sensitive image.
> > + * The table size is sizeof(u32) * 2048.
> > + * Set zero to disable this table.
>
> Addresses in a control struct? Sounds iffy, but I'll comment more on it when I
> review
> the control code.
The control struct has references to optional table.
The tables might better be embedded to the control struct along with table_{h,m,l}_en member.
This solution also removes copy_from_user() for deep copy.
My concern is that the size of the struct gets large.
> > + * @table_m_addr: DPC table address for middle sensitive image or LED
> image.
> > + * The table size is sizeof(u32) * 2048.
> > + * Set zero to disable this table.
> > + * @table_l_addr: DPC table address for low sensitive image.
> > + * The table size is sizeof(u32) * 2048.
> > + * Set zero to disable this table.
> > + *
> > + * The size of each table is fixed at 8192 Byte.
> > + * Application should make sure that the table data is based on HW
> specification
> > + * since this driver does not check the DPC table.
> > + */
> > +struct viif_l1_dpc_config {
> > + struct viif_l1_dpc param_h;
> > + struct viif_l1_dpc param_m;
> > + struct viif_l1_dpc param_l;
> > + __u64 table_h_addr;
> > + __u64 table_m_addr;
> > + __u64 table_l_addr;
> > +};
> > +
> > +/**
> > + * struct viif_l1_preset_wb - L1ISP preset white balance parameters
> > + * for &struct viif_l1_preset_white_balance_config
> > + * @gain_gr: Gr gain [0..524287], accuracy 1/16384
> > + * @gain_r: R gain [0..524287], accuracy 1/16384
> > + * @gain_b: B gain [0..524287], accuracy 1/16384
> > + * @gain_gb: Gb gain [0..524287], accuracy 1/16384
> > + */
> > +struct viif_l1_preset_wb {
> > + __u32 gain_gr;
> > + __u32 gain_r;
> > + __u32 gain_b;
> > + __u32 gain_gb;
> > +};
> > +
> > +/**
> > + * struct viif_l1_preset_white_balance_config - L1ISP preset white balance
> > + * parameters
> for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE`
> > + * @dstmaxval: Maximum value of output pixel [pixel] [0..4095]
> > + * @param_h: Preset white balance parameter for high sensitive image.
> > + * Refer to &struct viif_l1_preset_wb
> > + * @param_m: Preset white balance parameters for middle sensitive image
> or LED image.
> > + * Refer to &struct viif_l1_preset_wb
> > + * @param_l: Preset white balance parameters for low sensitive image.
> > + * Refer to &struct viif_l1_preset_wb
> > + */
> > +struct viif_l1_preset_white_balance_config {
> > + __u32 dstmaxval;
> > + struct viif_l1_preset_wb param_h;
> > + struct viif_l1_preset_wb param_m;
> > + struct viif_l1_preset_wb param_l;
> > +};
> > +
> > +/**
> > + * enum viif_l1_rcnr_type - L1ISP high resolution luminance filter type
> > + *
> > + * @VIIF_L1_RCNR_LOW_RESOLUTION: low resolution
> > + * @VIIF_L1_RCNR_MIDDLE_RESOLUTION: middle resolution
> > + * @VIIF_L1_RCNR_HIGH_RESOLUTION: high resolution
> > + * @VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION: ultra high resolution
> > + */
> > +enum viif_l1_rcnr_type {
> > + VIIF_L1_RCNR_LOW_RESOLUTION = 0,
> > + VIIF_L1_RCNR_MIDDLE_RESOLUTION = 1,
> > + VIIF_L1_RCNR_HIGH_RESOLUTION = 2,
> > + VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION = 3,
> > +};
> > +
> > +/**
> > + * enum viif_l1_msf_blend_ratio - L1ISP MSF blend ratio
> > + *
> > + * @VIIF_L1_MSF_BLEND_RATIO_0_DIV_64: 0/64
> > + * @VIIF_L1_MSF_BLEND_RATIO_1_DIV_64: 1/64
> > + * @VIIF_L1_MSF_BLEND_RATIO_2_DIV_64: 2/64
> > + */
> > +enum viif_l1_msf_blend_ratio {
> > + VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 = 0,
> > + VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 = 1,
> > + VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 = 2,
> > +};
> > +
> > +/**
> > + * struct viif_l1_raw_color_noise_reduction - L1ISP RCNR parameters
> > + * for &struct viif_l1_raw_color_noise_reduction_config
> > + * @rcnr_sw: 1:Enable/0:Disable setting of RAW color noise reduction
> > + * @rcnr_cnf_dark_ag0: Maximum value of LSF dark noise adjustment[0..63]
> > + * @rcnr_cnf_dark_ag1: Middle value of LSF dark noise adjustment [0..63]
> > + * @rcnr_cnf_dark_ag2: Minimum value of LSF dark noise adjustment [0..63]
> > + * @rcnr_cnf_ratio_ag0: Maximum value of LSF luminance interlocking noise
> adjustment [0..31]
> > + * @rcnr_cnf_ratio_ag1: Middle value of LSF luminance interlocking noise
> adjustment [0..31]
> > + * @rcnr_cnf_ratio_ag2: Minimum value of LSF luminance interlocking noise
> adjustment [0..31]
> > + * @rcnr_cnf_clip_gain_r: LSF color correction limit adjustment gain R [0..3]
> > + * @rcnr_cnf_clip_gain_g: LSF color correction limit adjustment gain G [0..3]
> > + * @rcnr_cnf_clip_gain_b: LSF color correction limit adjustment gain B [0..3]
> > + * @rcnr_a1l_dark_ag0: Maximum value of MSF dark noise adjustment
> [0..63]
> > + * @rcnr_a1l_dark_ag1: Middle value of MSF dark noise adjustment [0..63]
> > + * @rcnr_a1l_dark_ag2: Minimum value of MSF dark noise adjustment
> [0..63]
> > + * @rcnr_a1l_ratio_ag0: Maximum value of MSF luminance interlocking noise
> adjustment [0..31]
> > + * @rcnr_a1l_ratio_ag1: Middle value of MSF luminance interlocking noise
> adjustment [0..31]
> > + * @rcnr_a1l_ratio_ag2: Minimum value of MSF luminance interlocking noise
> adjustment [0..31]
> > + * @rcnr_inf_zero_clip: Input stage zero clip setting [0..256]
> > + * @rcnr_merge_d2blend_ag0: Maximum value of filter results and input
> blend ratio [0..16]
> > + * @rcnr_merge_d2blend_ag1: Middle value of filter results and input blend
> ratio [0..16]
> > + * @rcnr_merge_d2blend_ag2: Minimum value of filter results and input
> blend ratio [0..16]
> > + * @rcnr_merge_black: Black level minimum value [0..64]
> > + * @rcnr_merge_mindiv: 0 div guard value of inverse arithmetic unit [4..16]
> > + * @rcnr_hry_type: &enum viif_l1_rcnr_type value. Filter type for HSF filter
> process.
> > + * @rcnr_anf_blend_ag0: &enum viif_l1_msf_blend_ratio value.
> > + * Maximum value of MSF result blend ratio in write
> back data to line memory.
> > + * @rcnr_anf_blend_ag1: &enum viif_l1_msf_blend_ratio value.
> > + * Middle value of MSF result blend ratio in write
> back data to line memory.
> > + * @rcnr_anf_blend_ag2: &enum viif_l1_msf_blend_ratio value.
> > + * Minimum value of MSF result blend ratio in write
> back data to line memory.
> > + * @rcnr_lpf_threshold: Multiplier value for calculating dark noise /
> luminance
> > + * interlock noise of MSF [0..31], accuracy: 1/8
> > + * @rcnr_merge_hlblend_ag0: Maximum value of luminance signal
> generation blend [0..2]
> > + * @rcnr_merge_hlblend_ag1: Middle value of luminance signal generation
> blend [0..2]
> > + * @rcnr_merge_hlblend_ag2: Minimum value of luminance signal generation
> blend [0..2]
> > + * @rcnr_gnr_sw: 1:Enable/0:Disable setting of Gr/Gb sensitivity ratio
> > + * correction function switching
> > + * @rcnr_gnr_ratio: Upper limit of Gr/Gb sensitivity ratio correction factor
> [0..15]
> > + * @rcnr_gnr_wide_en: 1:Enable/0:Disable setting of the function to double
> > + * correction upper limit ratio of rcnr_gnr_ratio
> > + */
> > +struct viif_l1_raw_color_noise_reduction {
> > + __u32 rcnr_sw;
> > + __u32 rcnr_cnf_dark_ag0;
> > + __u32 rcnr_cnf_dark_ag1;
> > + __u32 rcnr_cnf_dark_ag2;
> > + __u32 rcnr_cnf_ratio_ag0;
> > + __u32 rcnr_cnf_ratio_ag1;
> > + __u32 rcnr_cnf_ratio_ag2;
> > + __u32 rcnr_cnf_clip_gain_r;
> > + __u32 rcnr_cnf_clip_gain_g;
> > + __u32 rcnr_cnf_clip_gain_b;
> > + __u32 rcnr_a1l_dark_ag0;
> > + __u32 rcnr_a1l_dark_ag1;
> > + __u32 rcnr_a1l_dark_ag2;
> > + __u32 rcnr_a1l_ratio_ag0;
> > + __u32 rcnr_a1l_ratio_ag1;
> > + __u32 rcnr_a1l_ratio_ag2;
> > + __u32 rcnr_inf_zero_clip;
> > + __u32 rcnr_merge_d2blend_ag0;
> > + __u32 rcnr_merge_d2blend_ag1;
> > + __u32 rcnr_merge_d2blend_ag2;
> > + __u32 rcnr_merge_black;
> > + __u32 rcnr_merge_mindiv;
> > + __u32 rcnr_hry_type;
> > + __u32 rcnr_anf_blend_ag0;
> > + __u32 rcnr_anf_blend_ag1;
> > + __u32 rcnr_anf_blend_ag2;
> > + __u32 rcnr_lpf_threshold;
> > + __u32 rcnr_merge_hlblend_ag0;
> > + __u32 rcnr_merge_hlblend_ag1;
> > + __u32 rcnr_merge_hlblend_ag2;
> > + __u32 rcnr_gnr_sw;
> > + __u32 rcnr_gnr_ratio;
> > + __u32 rcnr_gnr_wide_en;
> > +};
> > +
> > +/**
> > + * struct viif_l1_raw_color_noise_reduction_config - L1ISP RCNR parameters
> > + *
> for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUC
> TION`
> > + * @param_h: RAW color noise reduction parameter for high sensitive image.
> > + * Refer to &struct viif_l1_raw_color_noise_reduction
> > + * @param_m: RAW color noise reduction parameter for middle sensitive
> image or LED image.
> > + * Refer to &struct viif_l1_raw_color_noise_reduction
> > + * @param_l: RAW color noise reduction parameter for low sensitive image.
> > + * Refer to &struct viif_l1_raw_color_noise_reduction
> > + */
> > +struct viif_l1_raw_color_noise_reduction_config {
> > + struct viif_l1_raw_color_noise_reduction param_h;
> > + struct viif_l1_raw_color_noise_reduction param_m;
> > + struct viif_l1_raw_color_noise_reduction param_l;
> > +};
> > +
> > +/**
> > + * enum viif_l1_hdrs_middle_img_mode - L1ISP HDR setting
> > + *
> > + * @VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE: not use middle
> image
> > + * @VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE: use middle image
> > + */
> > +enum viif_l1_hdrs_middle_img_mode {
> > + VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE = 0,
> > + VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE = 1,
> > +};
> > +
> > +/**
> > + * struct viif_l1_hdrs_config - L1ISP HDRS parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS`
> > + * @hdrs_hdr_mode: &enum viif_l1_hdrs_middle_img_mode value.
> > + * Use/No use settings of middle sensitivity image in
> HDRS.
> > + * @hdrs_hdr_ratio_m: Magnification ratio of middle sensitivity image for
> high
> > + * sensitivity image [0x400..0x400000] accuracy:
> 1/1024
> > + * @hdrs_hdr_ratio_l: Magnification ratio of low sensitivity image for high
> > + * sensitivity image [0x400..0x400000], accuracy:
> 1/1024
> > + * @hdrs_hdr_ratio_e: Magnification ratio of LED image for high sensitivity
> image
> > + * [0x400..0x400000], accuracy: 1/1024
> > + * @hdrs_dg_h: High sensitivity image digital gain [0..0x3FFFFF], accuracy:
> 1/1024
> > + * @hdrs_dg_m: Middle sensitivity image digital gain [0..0x3FFFFF],
> accuracy: 1/1024
> > + * @hdrs_dg_l: Low sensitivity image digital gain [0..0x3FFFFF], accuracy:
> 1/1024
> > + * @hdrs_dg_e: LED image digital gain [0..0x3FFFFF], accuracy: 1/1024
> > + * @hdrs_blendend_h: Maximum luminance used for blend high sensitivity
> image [0..4095]
> > + * @hdrs_blendend_m: Maximum luminance used for blend middle
> sensitivity image [0..4095]
> > + * @hdrs_blendend_e: Maximum luminance used for blend LED image
> [0..4095]
> > + * @hdrs_blendbeg_h: Minimum luminance used for blend high sensitivity
> image [0..4095]
> > + * @hdrs_blendbeg_m: Minimum luminance used for blend middle sensitivity
> image [0..4095]
> > + * @hdrs_blendbeg_e: Minimum luminance used for blend LED image
> [0..4095]
> > + * @hdrs_led_mode_on: 1:Enable/0:Disable settings of LED mode
> > + * @hdrs_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
> > + *
> > + * parameter error needs to be returned in the below condition.
> > + * (hdrs_hdr_mode == VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) &&
> (hdrs_led_mode_on == 1)
> > + */
> > +struct viif_l1_hdrs_config {
> > + __u32 hdrs_hdr_mode;
> > + __u32 hdrs_hdr_ratio_m;
> > + __u32 hdrs_hdr_ratio_l;
> > + __u32 hdrs_hdr_ratio_e;
> > + __u32 hdrs_dg_h;
> > + __u32 hdrs_dg_m;
> > + __u32 hdrs_dg_l;
> > + __u32 hdrs_dg_e;
> > + __u32 hdrs_blendend_h;
> > + __u32 hdrs_blendend_m;
> > + __u32 hdrs_blendend_e;
> > + __u32 hdrs_blendbeg_h;
> > + __u32 hdrs_blendbeg_m;
> > + __u32 hdrs_blendbeg_e;
> > + __u32 hdrs_led_mode_on;
> > + __u32 hdrs_dst_max_val;
> > +};
> > +
> > +/**
> > + * struct viif_l1_black_level_correction_config - L1ISP image level
> conversion
> > + * parameters
> for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION
> `
> > + * @srcblacklevel_gr: Black level of Gr input pixel [pixel] [0..0xFFFFFF]
> > + * @srcblacklevel_r: Black level of R input pixel [pixel] [0..0xFFFFFF]
> > + * @srcblacklevel_b: Black level of B input pixel [pixel] [0..0xFFFFFF]
> > + * @srcblacklevel_gb: Black level of Gb input pixel [pixel] [0..0xFFFFFF]
> > + * @mulval_gr: Gr gain [0..0xFFFFF], accuracy: 1/256
> > + * @mulval_r: R gain [0..0xFFFFF], accuracy: 1/256
> > + * @mulval_b: B gain [0..0xFFFFF], accuracy: 1/256
> > + * @mulval_gb: Gb gain [0..0xFFFFF], accuracy: 1/256
> > + * @dstmaxval: Maximum value of output pixel [pixel] [0..0xFFFFFF]
> > + */
> > +struct viif_l1_black_level_correction_config {
> > + __u32 srcblacklevel_gr;
> > + __u32 srcblacklevel_r;
> > + __u32 srcblacklevel_b;
> > + __u32 srcblacklevel_gb;
> > + __u32 mulval_gr;
> > + __u32 mulval_r;
> > + __u32 mulval_b;
> > + __u32 mulval_gb;
> > + __u32 dstmaxval;
> > +};
> > +
> > +/**
> > + * enum viif_l1_para_coef_gain - L1ISP parabola shading correction
> coefficient ratio
> > + *
> > + * @VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH: 1/8
> > + * @VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH: 1/4
> > + * @VIIF_L1_PARA_COEF_GAIN_ONE_SECOND: 1/2
> > + * @VIIF_L1_PARA_COEF_GAIN_ONE_FIRST: 1/1
> > + */
> > +enum viif_l1_para_coef_gain {
> > + VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH = 0, /* 1/8 */
> > + VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH = 1, /* 1/4 */
> > + VIIF_L1_PARA_COEF_GAIN_ONE_SECOND = 2, /* 1/2 */
> > + VIIF_L1_PARA_COEF_GAIN_ONE_FIRST = 3, /* 1/1 */
> > +};
> > +
> > +/**
> > + * enum viif_l1_grid_coef_gain - L1ISP grid shading correction coefficient
> ratio
> > + *
> > + * @VIIF_L1_GRID_COEF_GAIN_X1: x1
> > + * @VIIF_L1_GRID_COEF_GAIN_X2: x2
> > + */
> > +enum viif_l1_grid_coef_gain {
> > + VIIF_L1_GRID_COEF_GAIN_X1 = 0,
> > + VIIF_L1_GRID_COEF_GAIN_X2 = 1,
> > +};
> > +
> > +/**
> > + * struct viif_l1_lsc_parabola_ag_param - L2ISP parabola shading
> parameters
> > + * for &struct viif_l1_lsc_parabola_param
> > + * @lssc_paracoef_h_l_max: Parabola coefficient left maximum gain value
> > + * @lssc_paracoef_h_l_min: Parabola coefficient left minimum gain value
> > + * @lssc_paracoef_h_r_max: Parabola coefficient right maximum gain value
> > + * @lssc_paracoef_h_r_min: Parabola coefficient right minimum gain value
> > + * @lssc_paracoef_v_u_max: Parabola coefficient upper maximum gain value
> > + * @lssc_paracoef_v_u_min: Parabola coefficient upper minimum gain value
> > + * @lssc_paracoef_v_d_max: Parabola coefficient lower maximum gain value
> > + * @lssc_paracoef_v_d_min: Parabola coefficient lower minimum gain value
> > + * @lssc_paracoef_hv_lu_max: Parabola coefficient upper left gain maximum
> value
> > + * @lssc_paracoef_hv_lu_min: Parabola coefficient upper left gain minimum
> value
> > + * @lssc_paracoef_hv_ru_max: Parabola coefficient upper right gain
> maximum value
> > + * @lssc_paracoef_hv_ru_min: Parabola coefficient upper right minimum
> gain value
> > + * @lssc_paracoef_hv_ld_max: Parabola coefficient lower left gain maximum
> value
> > + * @lssc_paracoef_hv_ld_min: Parabola coefficient lower left gain minimum
> value
> > + * @lssc_paracoef_hv_rd_max: Parabola coefficient lower right gain
> maximum value
> > + * @lssc_paracoef_hv_rd_min: Parabola coefficient lower right minimum gain
> value
> > + *
> > + * The range and accuracy of each coefficient are as
> > + * "range: [-4096..4095], accuracy: 1/256 "
> > + *
> > + * Each coefficient should meet the following conditions.
> > + * "lssc_paracoef_xx_xx_min <= lssc_paracoef_xx_xx_max"
> > + */
> > +struct viif_l1_lsc_parabola_ag_param {
> > + __s16 lssc_paracoef_h_l_max;
> > + __s16 lssc_paracoef_h_l_min;
> > + __s16 lssc_paracoef_h_r_max;
> > + __s16 lssc_paracoef_h_r_min;
> > + __s16 lssc_paracoef_v_u_max;
> > + __s16 lssc_paracoef_v_u_min;
> > + __s16 lssc_paracoef_v_d_max;
> > + __s16 lssc_paracoef_v_d_min;
> > + __s16 lssc_paracoef_hv_lu_max;
> > + __s16 lssc_paracoef_hv_lu_min;
> > + __s16 lssc_paracoef_hv_ru_max;
> > + __s16 lssc_paracoef_hv_ru_min;
> > + __s16 lssc_paracoef_hv_ld_max;
> > + __s16 lssc_paracoef_hv_ld_min;
> > + __s16 lssc_paracoef_hv_rd_max;
> > + __s16 lssc_paracoef_hv_rd_min;
> > +};
> > +
> > +/**
> > + * struct viif_l1_lsc_parabola_param - L2ISP parabola shading parameters
> > + * for &struct viif_l1_lsc
> > + * @lssc_para_h_center: Horizontal coordinate of central optical axis [pixel]
> > + * [0..(Input image width - 1)]
> > + * @lssc_para_v_center: Vertical coordinate of central optical axis [line]
> > + * [0..(Input image height - 1)]
> > + * @lssc_para_h_gain: Horizontal distance gain with the optical axis
> > + * [0..4095], accuracy: 1/256
> > + * @lssc_para_v_gain: Vertical distance gain with the optical axis
> > + * [0..4095], accuracy: 1/256
> > + * @lssc_para_mgsel2: &enum viif_l1_para_coef_gain value.
> > + * Parabola 2D correction coefficient gain magnification
> ratio.
> > + * @lssc_para_mgsel4: &enum viif_l1_para_coef_gain value.
> > + * Parabola 4D correction coefficient gain magnification
> ratio.
> > + * @r_2d: 2D parabola coefficient for R.
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @r_4d: 4D parabola coefficient for R.
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @gr_2d: 2D parabola coefficient for Gr
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @gr_4d: 4D parabola coefficient for Gr
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @gb_2d: 2D parabola coefficient for Gb
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @gb_4d: 4D parabola coefficient for Gb
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @b_2d: 2D parabola coefficient for B
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + * @b_4d: 4D parabola coefficient for B
> > + * Refer to &struct viif_l1_lsc_parabola_ag_param
> > + */
> > +struct viif_l1_lsc_parabola_param {
> > + __u32 lssc_para_h_center;
> > + __u32 lssc_para_v_center;
> > + __u32 lssc_para_h_gain;
> > + __u32 lssc_para_v_gain;
> > + __u32 lssc_para_mgsel2;
> > + __u32 lssc_para_mgsel4;
> > + struct viif_l1_lsc_parabola_ag_param r_2d;
> > + struct viif_l1_lsc_parabola_ag_param r_4d;
> > + struct viif_l1_lsc_parabola_ag_param gr_2d;
> > + struct viif_l1_lsc_parabola_ag_param gr_4d;
> > + struct viif_l1_lsc_parabola_ag_param gb_2d;
> > + struct viif_l1_lsc_parabola_ag_param gb_4d;
> > + struct viif_l1_lsc_parabola_ag_param b_2d;
> > + struct viif_l1_lsc_parabola_ag_param b_4d;
> > +};
> > +
> > +/**
> > + * struct viif_l1_lsc_grid_param - L2ISP grid shading parameters
> > + * for &struct viif_l1_lsc
> > + * @lssc_grid_h_size: Grid horizontal direction pixel count [32, 64, 128, 256,
> 512]
> > + * @lssc_grid_v_size: Grid vertical direction pixel count [32, 64, 128, 256, 512]
> > + * @lssc_grid_h_center: Horizontal coordinates of grid (1, 1) [pixel]
> [1..lssc_grid_h_size]
> > + * Should meet the following condition.
> > + * "Input image width <= lssc_grid_h_center +
> lssc_grid_h_size * 31"
> > + * @lssc_grid_v_center: Vertical coordinates of grid (1, 1) [line]
> [1..lssc_grid_v_size]
> > + * Should meet the following condition.
> > + * "Input image height <= lssc_grid_v_center +
> lssc_grid_v_size * 23"
> > + * @lssc_grid_mgsel: &enum viif_l1_grid_coef_gain value.
> > + * Grid correction coefficient gain value magnification
> ratio.
> > + */
> > +struct viif_l1_lsc_grid_param {
> > + __u32 lssc_grid_h_size;
> > + __u32 lssc_grid_v_size;
> > + __u32 lssc_grid_h_center;
> > + __u32 lssc_grid_v_center;
> > + __u32 lssc_grid_mgsel;
> > +};
> > +
> > +/**
> > + * struct viif_l1_lsc - L2ISP LSC parameters for &struct viif_l1_lsc_config
> > + * @lssc_parabola_param_addr: Address of a &struct
> viif_l1_lsc_parabola_param instance.
> > + * Set 0 to disable parabola shading correction.
> > + * @lssc_grid_param_addr: Address of a &struct viif_l1_lsc_grid_param
> instance,
> > + * Set 0 to disable grid shading correction.
> > + * @lssc_pwhb_r_gain_max: PWB R correction processing coefficient
> maximum value
> > + * @lssc_pwhb_r_gain_min: PWB R correction processing coefficient
> minimum value
> > + * @lssc_pwhb_gr_gain_max: PWB Gr correction processing coefficient
> maximum value
> > + * @lssc_pwhb_gr_gain_min: PWB Gr correction processing coefficient
> minimum value
> > + * @lssc_pwhb_gb_gain_max: PWB Gb correction processing coefficient
> maximum value
> > + * @lssc_pwhb_gb_gain_min: PWB Gb correction processing coefficient
> minimum value
> > + * @lssc_pwhb_b_gain_max: PWB B correction processing coefficient
> maximum value
> > + * @lssc_pwhb_b_gain_min: PWB B correction processing coefficient
> minimum value
> > + *
> > + * The range and accuracy of preset white balance (PWB) correction process
> > + * coefficient (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) are as below.
> > + * "range: [0..2047], accuracy: 1/256"
> > + *
> > + * PWB correction process coefficient
> > + * (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) should meet the following
> conditions.
> > + * "lssc_pwhb_{r/gr/gb/b}_gain_min <= lssc_pwhb_{r/gr/gb/b}_gain_max"
> > + */
> > +struct viif_l1_lsc {
> > + __u64 lssc_parabola_param_addr;
> > + __u64 lssc_grid_param_addr;
> > + __u32 lssc_pwhb_r_gain_max;
> > + __u32 lssc_pwhb_r_gain_min;
> > + __u32 lssc_pwhb_gr_gain_max;
> > + __u32 lssc_pwhb_gr_gain_min;
> > + __u32 lssc_pwhb_gb_gain_max;
> > + __u32 lssc_pwhb_gb_gain_min;
> > + __u32 lssc_pwhb_b_gain_max;
> > + __u32 lssc_pwhb_b_gain_min;
> > +};
> > +
> > +/**
> > + * struct viif_l1_lsc_config - L2ISP LSC parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC`
> > + * @param_addr: Address of a &struct viif_l1_lsc instance.
> > + * Set 0 to disable LSC operation.
> > + * @table_gr_addr: Address of the grid table for LSC of Gr component.
> > + * The table size is sizeof(u16) * 768.
> > + * Set 0 to disable this table.
> > + * @table_r_addr: Address of the grid table for LSC of R component.
> > + * The table size is sizeof(u16) * 768.
> > + * Set 0 to disable this table.
> > + * @table_b_addr: Address of the grid table for LSC of B component.
> > + * The table size is sizeof(u16) * 768.
> > + * Set 0 to disable this table.
> > + * @table_gb_addr: Address of the grid table for LSC of Gb component.
> > + * The table size is sizeof(u16) * 768.
> > + * Set 0 to disable this table.
> > + *
> > + * The size of each table is fixed to 1,536 Bytes.
> > + * Application should make sure that the table data is based on HW
> specification
> > + * since this driver does not check the grid table.
> > + */
> > +struct viif_l1_lsc_config {
> > + __u64 param_addr;
> > + __u64 table_gr_addr;
> > + __u64 table_r_addr;
> > + __u64 table_b_addr;
> > + __u64 table_gb_addr;
> > +};
> > +
> > +/**
> > + * enum viif_l1_demosaic_mode - L1ISP demosaic modeenum
> viif_l1_demosaic_mode
> > + *
> > + * @VIIF_L1_DEMOSAIC_ACPI: Toshiba ACPI algorithm
> > + * @VIIF_L1_DEMOSAIC_DMG: DMG algorithm
> > + */
> > +enum viif_l1_demosaic_mode {
> > + VIIF_L1_DEMOSAIC_ACPI = 0,
> > + VIIF_L1_DEMOSAIC_DMG = 1,
> > +};
> > +
> > +/**
> > + * struct viif_l1_color_matrix_correction - L1ISP color matrix correction
> > + * parameters for &struct viif_l1_main_process_config
> > + * @coef_rmg_min: (R-G) Minimum coefficient
> > + * @coef_rmg_max: (R-G) Maximum coefficient
> > + * @coef_rmb_min: (R-B) Minimum coefficient
> > + * @coef_rmb_max: (R-B) Maximum coefficient
> > + * @coef_gmr_min: (G-R) Minimum coefficient
> > + * @coef_gmr_max: (G-R) Maximum coefficient
> > + * @coef_gmb_min: (G-B) Minimum coefficient
> > + * @coef_gmb_max: (G-B) Maximum coefficient
> > + * @coef_bmr_min: (B-R) Minimum coefficient
> > + * @coef_bmr_max: (B-R) Maximum coefficient
> > + * @coef_bmg_min: (B-G) Minimum coefficient
> > + * @coef_bmg_max: (B-G) Maximum coefficient
> > + * @dst_minval: Minimum value of output pixel [0..0xFFFF] [pixel]
> > + *
> > + * The range and accuracy of each coefficient are as
> > + * "range: [-32768..32767], accuracy: 1/ 4096"
> > + *
> > + * Also, each coefficient should meet "coef_xxx_min <= coef_xxx_max"
> condition
> > + */
> > +struct viif_l1_color_matrix_correction {
> > + __s16 coef_rmg_min;
> > + __s16 coef_rmg_max;
> > + __s16 coef_rmb_min;
> > + __s16 coef_rmb_max;
> > + __s16 coef_gmr_min;
> > + __s16 coef_gmr_max;
> > + __s16 coef_gmb_min;
> > + __s16 coef_gmb_max;
> > + __s16 coef_bmr_min;
> > + __s16 coef_bmr_max;
> > + __s16 coef_bmg_min;
> > + __s16 coef_bmg_max;
> > + __u16 dst_minval;
> > +};
> > +
> > +/**
> > + * struct viif_l1_main_process_config - L1ISP Main process operating
> parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS`
> > + * @demosaic_mode: &enum viif_l1_demosaic_mode value. Sets demosaic
> mode.
> > + * @damp_lsbsel: Clipping range of output pixel value to AWB adjustment
> function [0..15]
> > + * @param_addr: Address to a &struct viif_l1_color_matrix_correction
> instance.
> > + * Set 0 to disable color matrix correction.
> > + * @dst_maxval: Maximum value of output pixel [0..0xFFFFFF].
> > + * Applicable to output of each process (digital amplifier,
> > + * demosaicing and color matrix correction) in L1ISP Main
> process.
> > + */
> > +struct viif_l1_main_process_config {
> > + __u32 demosaic_mode;
> > + __u32 damp_lsbsel;
> > + __u64 param_addr;
> > + __u32 dst_maxval;
> > +};
> > +
> > +/**
> > + * enum viif_l1_awb_mag - L1ISP signal magnification before AWB
> adjustment
> > + *
> > + * @VIIF_L1_AWB_ONE_SECOND: x 1/2
> > + * @VIIF_L1_AWB_X1: 1 times
> > + * @VIIF_L1_AWB_X2: 2 times
> > + * @VIIF_L1_AWB_X4: 4 times
> > + */
> > +enum viif_l1_awb_mag {
> > + VIIF_L1_AWB_ONE_SECOND = 0,
> > + VIIF_L1_AWB_X1 = 1,
> > + VIIF_L1_AWB_X2 = 2,
> > + VIIF_L1_AWB_X4 = 3,
> > +};
> > +
> > +/**
> > + * enum viif_l1_awb_area_mode - L1ISP AWB detection target area
> > + *
> > + * @VIIF_L1_AWB_AREA_MODE0: only center area
> > + * @VIIF_L1_AWB_AREA_MODE1: center area when uv is in square gate
> > + * @VIIF_L1_AWB_AREA_MODE2: all area except center area
> > + * @VIIF_L1_AWB_AREA_MODE3: all area
> > + */
> > +enum viif_l1_awb_area_mode {
> > + VIIF_L1_AWB_AREA_MODE0 = 0,
> > + VIIF_L1_AWB_AREA_MODE1 = 1,
> > + VIIF_L1_AWB_AREA_MODE2 = 2,
> > + VIIF_L1_AWB_AREA_MODE3 = 3,
> > +};
> > +
> > +/**
> > + * enum viif_l1_awb_restart_cond - L1ISP AWB adjustment restart conditions
> > + *
> > + * @VIIF_L1_AWB_RESTART_NO: no restart
> > + * @VIIF_L1_AWB_RESTART_128FRAME: restart after 128 frame
> > + * @VIIF_L1_AWB_RESTART_64FRAME: restart after 64 frame
> > + * @VIIF_L1_AWB_RESTART_32FRAME: restart after 32 frame
> > + * @VIIF_L1_AWB_RESTART_16FRAME: restart after 16 frame
> > + * @VIIF_L1_AWB_RESTART_8FRAME: restart after 8 frame
> > + * @VIIF_L1_AWB_RESTART_4FRAME: restart after 4 frame
> > + * @VIIF_L1_AWB_RESTART_2FRAME: restart after 2 frame
> > + */
> > +enum viif_l1_awb_restart_cond {
> > + VIIF_L1_AWB_RESTART_NO = 0,
> > + VIIF_L1_AWB_RESTART_128FRAME = 1,
> > + VIIF_L1_AWB_RESTART_64FRAME = 2,
> > + VIIF_L1_AWB_RESTART_32FRAME = 3,
> > + VIIF_L1_AWB_RESTART_16FRAME = 4,
> > + VIIF_L1_AWB_RESTART_8FRAME = 5,
> > + VIIF_L1_AWB_RESTART_4FRAME = 6,
> > + VIIF_L1_AWB_RESTART_2FRAME = 7,
> > +};
> > +
> > +/**
> > + * struct viif_l1_awb - L1ISP AWB adjustment parameters
> > + * for &struct viif_l1_awb_config
> > + * @awhb_ygate_sel: 1:Enable/0:Disable to fix Y value at YUV conversion
> > + * @awhb_ygate_data: Y value in case Y value is fixed [64, 128, 256, 512]
> > + * @awhb_cgrange: &enum viif_l1_awb_mag value.
> > + * Signal output magnification ratio before AWB adjustment.
> > + * @awhb_ygatesw: 1:Enable/0:Disable settings of luminance gate
> > + * @awhb_hexsw: 1:Enable/0:Disable settings of hexa-gate
> > + * @awhb_areamode: &enum viif_l1_awb_area_mode value.
> > + * Final selection of accumulation area for detection target
> area.
> > + * @awhb_area_hsize: Horizontal size per block in central area [pixel]
> > + * [1..(Input image width -8)/8]
> > + * @awhb_area_vsize: Vertical size per block in central area [line]
> > + * [1..(Input image height -4)/8]
> > + * @awhb_area_hofs: Horizontal offset of block [0] in central area [pixel]
> > + * [0..(Input image width -9)]
> > + * @awhb_area_vofs: Vertical offset of block [0] in central area [line]
> > + * [0..(Input image height -5)]
> > + * @awhb_area_maskh: Setting 1:Enable/0:Disable( of accumulated
> selection.
> > + * Each bit implies the following.
> > + * [31:0] = {
> > + * (7, 3),(6, 3),(5, 3),(4, 3),(3, 3),(2, 3),(1, 3),(0, 3),
> > + * (7, 2),(6, 2),(5, 2),(4, 2),(3, 2),(2, 2),(1, 2),(0, 2),
> > + * (7, 1),(6, 1),(5, 1),(4, 1),(3, 1),(2, 1),(1, 1),(0, 1),
> > + * (7, 0),(6, 0),(5, 0),(4, 0),(3, 0),(2, 0),(1, 0),(0, 0)}
> > + * @awhb_area_maskl: Setting 1:Enable/0:Disable of accumulated selection.
> > + * Each bit implies the following.
> > + * [31:0] = {
> > + * (7, 7),(6, 7),(5, 7),(4, 7),(3, 7),(2, 7),(1, 7),(0, 7),
> > + * (7, 6),(6, 6),(5, 6),(4, 6),(3, 6),(2, 6),(1, 6),(0, 6),
> > + * (7, 5),(6, 5),(5, 5),(4, 5),(3, 5),(2, 5),(1, 5),(0, 5),
> > + * (7, 4),(6, 4),(5, 4),(4, 4),(3, 4),(2, 4),(1, 4),(0, 4)}
> > + * @awhb_sq_sw: 1:Enable/0:Disable each square gate
> > + * @awhb_sq_pol: 1:Enable/0:Disable to add accumulated gate for each
> square gate
> > + * @awhb_bycut0p: U upper end value [pixel] [0..127]
> > + * @awhb_bycut0n: U lower end value [pixel] [0..127]
> > + * @awhb_rycut0p: V upper end value [pixel] [0..127]
> > + * @awhb_rycut0n: V lower end value [pixel] [0..127]
> > + * @awhb_rbcut0h: V-axis intercept upper end [pixel] [-127..127]
> > + * @awhb_rbcut0l: V-axis intercept lower end [pixel] [-127..127]
> > + * @awhb_bycut_h: U direction center value of each square gate [-127..127]
> > + * @awhb_bycut_l: U direction width of each square gate [0..127]
> > + * @awhb_rycut_h: V direction center value of each square gate [-127..127]
> > + * @awhb_rycut_l: V direction width of each square gate [0..127]
> > + * @awhb_awbsftu: U gain offset [-127..127]
> > + * @awhb_awbsftv: V gain offset [-127..127]
> > + * @awhb_awbhuecor: 1:Enable/0:Disable setting of color correlation
> retention function
> > + * @awhb_awbspd: UV convergence speed [0..15] [times] (0 means "stop")
> > + * @awhb_awbulv: U convergence point level [0..31]
> > + * @awhb_awbvlv: V convergence point level [0..31]
> > + * @awhb_awbondot: Accumulation operation stop pixel count threshold
> [pixel] [0..1023]
> > + * @awhb_awbfztim: &enum viif_l1_awb_restart_cond value. Condition to
> restart AWB process.
> > + * @awhb_wbgrmax: B gain adjustment range (Width from center to upper
> limit)
> > + * [0..255], accuracy: 1/64
> > + * @awhb_wbgbmax: R gain adjustment range (Width from center to upper
> limit)
> > + * [0..255], accuracy: 1/64
> > + * @awhb_wbgrmin: B gain adjustment range (Width from center to lower
> limit)
> > + * [0..255], accuracy: 1/64
> > + * @awhb_wbgbmin: R gain adjustment range (Width from center to lower
> limit)
> > + * [0..255], accuracy: 1/64
> > + * @awhb_ygateh: Luminance gate maximum value [pixel] [0..255]
> > + * @awhb_ygatel: Luminance gate minimum value [pixel] [0..255]
> > + * @awhb_awbwait: Number of restart frames after UV convergence freeze
> [0..255]
> > + */
> > +struct viif_l1_awb {
> > + __u32 awhb_ygate_sel;
> > + __u32 awhb_ygate_data;
> > + __u32 awhb_cgrange;
> > + __u32 awhb_ygatesw;
> > + __u32 awhb_hexsw;
> > + __u32 awhb_areamode;
> > + __u32 awhb_area_hsize;
> > + __u32 awhb_area_vsize;
> > + __u32 awhb_area_hofs;
> > + __u32 awhb_area_vofs;
> > + __u32 awhb_area_maskh;
> > + __u32 awhb_area_maskl;
> > + __u32 awhb_sq_sw[3];
> > + __u32 awhb_sq_pol[3];
> > + __u32 awhb_bycut0p;
> > + __u32 awhb_bycut0n;
> > + __u32 awhb_rycut0p;
> > + __u32 awhb_rycut0n;
> > + __s32 awhb_rbcut0h;
> > + __s32 awhb_rbcut0l;
> > + __s32 awhb_bycut_h[3];
> > + __u32 awhb_bycut_l[3];
> > + __s32 awhb_rycut_h[3];
> > + __u32 awhb_rycut_l[3];
> > + __s32 awhb_awbsftu;
> > + __s32 awhb_awbsftv;
> > + __u32 awhb_awbhuecor;
> > + __u32 awhb_awbspd;
> > + __u32 awhb_awbulv;
> > + __u32 awhb_awbvlv;
> > + __u32 awhb_awbondot;
> > + __u32 awhb_awbfztim;
> > + __u8 awhb_wbgrmax;
> > + __u8 awhb_wbgbmax;
> > + __u8 awhb_wbgrmin;
> > + __u8 awhb_wbgbmin;
> > + __u8 awhb_ygateh;
> > + __u8 awhb_ygatel;
> > + __u8 awhb_awbwait;
> > +};
> > +
> > +/**
> > + * struct viif_l1_awb_config - L1ISP AWB parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB`
> > + * @param_addr: Address to a &struct viif_l1_awb instance.
> > + * Set 0 to disable AWB adjustment.
> > + * @awhb_wbmrg: White balance adjustment R gain [64..1023], accuracy:
> 1/256
> > + * @awhb_wbmgg: White balance adjustment G gain [64..1023], accuracy:
> 1/256
> > + * @awhb_wbmbg: White balance adjustment B gain [64..1023], accuracy:
> 1/256
> > + */
> > +struct viif_l1_awb_config {
> > + __u64 param_addr;
> > + __u32 awhb_wbmrg;
> > + __u32 awhb_wbmgg;
> > + __u32 awhb_wbmbg;
> > +};
> > +
> > +/**
> > + * enum viif_l1_hdrc_tone_type - L1ISP HDRC tone type
> > + *
> > + * @VIIF_L1_HDRC_TONE_USER: User Tone
> > + * @VIIF_L1_HDRC_TONE_PRESET: Preset Tone
> > + */
> > +enum viif_l1_hdrc_tone_type {
> > + VIIF_L1_HDRC_TONE_USER = 0,
> > + VIIF_L1_HDRC_TONE_PRESET = 1,
> > +};
> > +
> > +/**
> > + * struct viif_l1_hdrc - L1ISP HDRC parameters for &struct
> viif_l1_hdrc_config
> > + * @hdrc_ratio: Data width of input image [bit] [10..24]
> > + * @hdrc_pt_ratio: Preset Tone curve slope [0..13]
> > + * @hdrc_pt_blend: Preset Tone0 curve blend ratio [0..256], accuracy: 1/256
> > + * @hdrc_pt_blend2: Preset Tone2 curve blend ratio [0..256], accuracy: 1/256
> > + * @hdrc_tn_type: &enum viif_l1_hdrc_tone_type value. L1ISP HDRC tone
> type.
> > + * @hdrc_utn_tbl: HDRC value of User Tone curve [0..0xFFFF]
> > + * @hdrc_flr_val: Constant flare value [0..0xFFFFFF]
> > + * @hdrc_flr_adp: 1:Enable/0:Disable setting of dynamic flare measurement
> > + * @hdrc_ybr_off: 1:Enable(function OFF) / 0:Disable(function ON) settings
> > + * of bilateral luminance filter function OFF
> > + * @hdrc_orgy_blend: Blend settings of luminance correction data after
> HDRC
> > + * and data before luminance correction [0..16].
> > + * (0:Luminance correction 100%, 8:Luminance
> correction 50%,
> > + * 16:Luminance correction 0%)
> > + * @hdrc_pt_sat: Preset Tone saturation value [0..0xFFFF]
> > + *
> > + * Parameter error needs to be returned in
> > + * "hdrc_pt_blend + hdrc_pt_blend2 > 256" condition.
> > + *
> > + * In case application enables dynamic flare control, input image height
> should
> > + * satisfy the following condition. Even if this condition is not satisfied,
> > + * this driver doesn't return error in case other conditions for each parameter
> > + * are satisfied. "Input image height % 64 != 18, 20, 22, 24, 26"
> > + *
> > + * hdrc_utn_tbl should satisfy the following condition. Even if this condition
> > + * is not satisfied, this driver doesn't return error in case other conditions
> > + * for each parameter are satisfied. "hdrc_utn_tbl[N] <= hdrc_utn_tbl[N+1]"
> > + */
> > +struct viif_l1_hdrc {
> > + __u32 hdrc_ratio;
> > + __u32 hdrc_pt_ratio;
> > + __u32 hdrc_pt_blend;
> > + __u32 hdrc_pt_blend2;
> > + __u32 hdrc_tn_type;
> > + __u16 hdrc_utn_tbl[20];
> > + __u32 hdrc_flr_val;
> > + __u32 hdrc_flr_adp;
> > + __u32 hdrc_ybr_off;
> > + __u32 hdrc_orgy_blend;
> > + __u16 hdrc_pt_sat;
> > +};
> > +
> > +/**
> > + * struct viif_l1_hdrc_config - L1ISP HDRC parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC`
> > + * @param_addr: Address to a &struct viif_l1_hdrc instance.
> > + * Set 0 to disable HDR compression.
> > + * @hdrc_thr_sft_amt: Amount of right shift in through mode (HDRC
> disabled) [0..8].
> > + * Should set 0 if HDRC is enabled
> > + */
> > +struct viif_l1_hdrc_config {
> > + __u64 param_addr;
> > + __u32 hdrc_thr_sft_amt;
> > +};
> > +
> > +/**
> > + * struct viif_l1_hdrc_ltm_config - L1ISP HDRC LTM parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM`
> > + * @tnp_max: Tone blend rate maximum value of LTM function
> > + * [0..4194303], accuracy: 1/64. In case of 0, LTM function is OFF
> > + * @tnp_mag: Intensity adjustment of LTM function [0..16383], accuracy:
> 1/64
> > + * @tnp_fil: Smoothing filter coefficient [0..255].
> > + * [0]: coef0, [1]: coef1, [2]: coef2, [3]: coef3, [4]: coef4
> > + * EINVAL needs to be returned in the below condition.
> > + * "(coef1 + coef2 + coef3 + coef4) * 2 + coef0 != 1024"
> > + */
> > +struct viif_l1_hdrc_ltm_config {
> > + __u32 tnp_max;
> > + __u32 tnp_mag;
> > + __u8 tnp_fil[5];
> > +};
> > +
> > +/**
> > + * struct viif_l1_gamma - L1ISP gamma correction parameters
> > + * for &struct viif_l1_gamma_config
> > + * @gam_p: Luminance value after gamma correction [0..8191]
> > + * @blkadj: Black level adjustment value after gamma correction [0..65535]
> > + */
> > +struct viif_l1_gamma {
> > + __u16 gam_p[44];
> > + __u16 blkadj;
> > +};
> > +
> > +/**
> > + * struct viif_l1_gamma_config - L1ISP gamma correction parameters
> > + * @param_addr: Address to a &struct viif_l1_gamma instance.
> > + * Set 0 to disable gamma correction at l1 ISP.
> > + */
> > +struct viif_l1_gamma_config {
> > + __u64 param_addr;
> > +};
> > +
> > +/**
> > + * struct viif_l1_nonlinear_contrast - L1ISP non-linear contrast parameters
> > + * for &struct viif_l1_img_quality_adjustment_config
> > + * @blk_knee: Black side peak luminance value [0..0xFFFF]
> > + * @wht_knee: White side peak luminance value[0..0xFFFF]
> > + * @blk_cont: Black side slope [0..255], accuracy: 1/256
> > + * [0]:the value at AG minimum, [1]:the value at AG less than
> 128,
> > + * [2]:the value at AG equal to or more than 128
> > + * @wht_cont: White side slope [0..255], accuracy: 1/256
> > + * [0]:the value at AG minimum, [1]:the value at AG less than
> 128,
> > + * [2]:the value at AG equal to or more than 128
> > + */
> > +struct viif_l1_nonlinear_contrast {
> > + __u16 blk_knee;
> > + __u16 wht_knee;
> > + __u8 blk_cont[3];
> > + __u8 wht_cont[3];
> > +};
> > +
> > +/**
> > + * struct viif_l1_lum_noise_reduction - L1ISP luminance noise reduction
> > + * parameters for &struct viif_l1_img_quality_adjustment_config
> > + * @gain_min: Minimum value of extracted noise gain [0..0xFFFF], accuracy:
> 1/256
> > + * @gain_max: Maximum value of extracted noise gain [0..0xFFFF],
> accuracy: 1/256
> > + * @lim_min: Minimum value of extracted noise limit [0..0xFFFF]
> > + * @lim_max: Maximum value of extracted noise limit [0..0xFFFF]
> > + *
> > + * Parameter error needs to be returned in the below conditions.
> > + * "gain_min > gain_max" or "lim_min > lim_max"
> > + */
> > +struct viif_l1_lum_noise_reduction {
> > + __u16 gain_min;
> > + __u16 gain_max;
> > + __u16 lim_min;
> > + __u16 lim_max;
> > +};
> > +
> > +/**
> > + * struct viif_l1_edge_enhancement - L1ISP edge enhancement parameters
> > + * for &struct viif_l1_img_quality_adjustment_config
> > + * @gain_min: Extracted edge gain minimum value [0..0xFFFF], accuracy:
> 1/256
> > + * @gain_max: Extracted edge gain maximum value [0..0xFFFF], accuracy:
> 1/256
> > + * @lim_min: Extracted edge limit minimum value [0..0xFFFF]
> > + * @lim_max: Extracted edge limit maximum value [0..0xFFFF]
> > + * @coring_min: Extracted edge coring threshold minimum value [0..0xFFFF]
> > + * @coring_max: Extracted edge coring threshold maximum value
> [0..0xFFFF]
> > + *
> > + * Parameter error needs to be returned in the below conditions.
> > + * "gain_min > gain_max" or "lim_min > lim_max" or "coring_min >
> coring_max"
> > + */
> > +struct viif_l1_edge_enhancement {
> > + __u16 gain_min;
> > + __u16 gain_max;
> > + __u16 lim_min;
> > + __u16 lim_max;
> > + __u16 coring_min;
> > + __u16 coring_max;
> > +};
> > +
> > +/**
> > + * struct viif_l1_uv_suppression - L1ISP UV suppression parameters
> > + * for &struct viif_l1_img_quality_adjustment_config
> > + * @bk_mp: Black side slope [0..0x3FFF], accuracy: 1/16384
> > + * @black: Minimum black side gain [0..0x3FFF], accuracy: 1/16384
> > + * @wh_mp: White side slope [0..0x3FFF], accuracy: 1/16384
> > + * @white: Minimum white side gain [0..0x3FFF], accuracy: 1/16384
> > + * @bk_slv: Black side intercept [0..0xFFFF]
> > + * @wh_slv: White side intercept [0..0xFFFF]
> > + *
> > + * parameter error needs to be returned in "bk_slv >= wh_slv" condition.
> > + */
> > +struct viif_l1_uv_suppression {
> > + __u32 bk_mp;
> > + __u32 black;
> > + __u32 wh_mp;
> > + __u32 white;
> > + __u16 bk_slv;
> > + __u16 wh_slv;
> > +};
> > +
> > +/**
> > + * struct viif_l1_coring_suppression - L1ISP coring suppression parameters
> > + * for &struct viif_l1_img_quality_adjustment_config
> > + * @lv_min: Minimum coring threshold [0..0xFFFF]
> > + * @lv_max: Maximum coring threshold [0..0xFFFF]
> > + * @gain_min: Minimum gain [0..0xFFFF], accuracy: 1/65536
> > + * @gain_max: Maximum gain [0..0xFFFF], accuracy: 1/65536
> > + *
> > + * Parameter error needs to be returned in the below condition.
> > + * "lv_min > lv_max" or "gain_min > gain_max"
> > + */
> > +struct viif_l1_coring_suppression {
> > + __u16 lv_min;
> > + __u16 lv_max;
> > + __u16 gain_min;
> > + __u16 gain_max;
> > +};
> > +
> > +/**
> > + * struct viif_l1_edge_suppression - L1ISP edge suppression parameters
> > + * for &struct viif_l1_img_quality_adjustment_config
> > + * @gain: Gain of edge color suppression [0..0xFFFF], accuracy: 1/256
> > + * @lim: Limiter threshold of edge color suppression [0..15]
> > + */
> > +struct viif_l1_edge_suppression {
> > + __u16 gain;
> > + __u32 lim;
> > +};
> > +
> > +/**
> > + * struct viif_l1_color_level - L1ISP color level parameters
> > + * for &struct viif_l1_img_quality_adjustment_config
> > + * @cb_gain: U component gain [0..0xFFF], accuracy: 1/2048
> > + * @cr_gain: V component gain [0..0xFFF], accuracy: 1/2048
> > + * @cbr_mgain_min: UV component gain [0..0xFFF], accuracy: 1/2048
> > + * @cbp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
> > + * @cbm_gain_max: Negative V component gain [0..0xFFF], accuracy:
> 1/2048
> > + * @crp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
> > + * @crm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
> > + */
> > +struct viif_l1_color_level {
> > + __u32 cb_gain;
> > + __u32 cr_gain;
> > + __u32 cbr_mgain_min;
> > + __u32 cbp_gain_max;
> > + __u32 cbm_gain_max;
> > + __u32 crp_gain_max;
> > + __u32 crm_gain_max;
> > +};
> > +
> > +/**
> > + * struct viif_l1_img_quality_adjustment_config - L1ISP image quality
> > + * adjustment parameters
> for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMEN
> T`
> > + * @coef_cb: Cb coefficient used in RGB to YUV conversion
> > + * [0..0xFFFF], accuracy: 1/65536
> > + * @coef_cr: Cr coefficient used in RGB to YUV conversion
> > + * [0..0xFFFF], accuracy: 1/65536
> > + * @brightness: Brightness value [-32768..32767] (0 means off)
> > + * @linear_contrast: Linear contrast adjustment value
> > + * [0..0xFF], accuracy: 1/128 (128 means off)
> > + * @nonlinear_contrast_addr: Address to a &struct viif_l1_nonlinear_contrast
> instance.
> > + * Set 0 to disable nonlinear contrast
> adjustment.
> > + * @lum_noise_reduction_addr: Address to a &struct
> viif_l1_lum_noise_reduction instance.
> > + * Set 0 to disable luminance noise reduction.
> > + * @edge_enhancement_addr: Address to a &struct
> viif_l1_edge_enhancement instance.
> > + * Set 0 to disable edge enhancement,
> > + * @uv_suppression_addr: Address to a &struct viif_l1_uv_suppression
> instance.
> > + * Set 0 to disable chroma suppression.
> > + * @coring_suppression_addr: Address to a &struct
> viif_l1_coring_suppression instance.
> > + * Set 0 to disable coring suppression.
> > + * @edge_suppression_addr: Address to a &struct viif_l1_edge_suppression
> instance.
> > + * Set 0 to disable chroma edge suppression.
> > + * @color_level_addr: Address to a &struct viif_l1_color_level instance.
> > + * Set 0 to disable color level adjustment.
> > + * @color_noise_reduction_enable: 1:Enable/0:disable setting of
> > + * color component noise reduction
> processing
> > + */
> > +struct viif_l1_img_quality_adjustment_config {
> > + __u16 coef_cb;
> > + __u16 coef_cr;
> > + __s16 brightness;
> > + __u8 linear_contrast;
> > + __u64 nonlinear_contrast_addr;
> > + __u64 lum_noise_reduction_addr;
> > + __u64 edge_enhancement_addr;
> > + __u64 uv_suppression_addr;
> > + __u64 coring_suppression_addr;
> > + __u64 edge_suppression_addr;
> > + __u64 color_level_addr;
> > + __u32 color_noise_reduction_enable;
> > +};
> > +
> > +/**
> > + * struct viif_l1_avg_lum_generation_config - L1ISP average luminance
> generation configuration
> > + *
> for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION`
> > + * @aexp_start_x: horizontal position of block[0] [0.."width of input image -
> 1"] [pixel]
> > + * @aexp_start_y: vertical position of block[0] [0.."height of input image - 1"]
> [line]
> > + * @aexp_block_width: width of one block(needs to be multiple of 64)
> > + * [64.."width of input image"] [pixel]
> > + * @aexp_block_height: height of one block(needs to be multiple of 64)
> > + * [64.."height of input image"] [line]
> > + * @aexp_weight: weight of each block [0..3] [y][x]:
> > + * y means vertical position and x means horizontal position
> > + * @aexp_satur_ratio: threshold to judge whether saturated block or not
> [0..256]
> > + * @aexp_black_ratio: threshold to judge whether black block or not [0..256]
> > + * @aexp_satur_level: threshold to judge whether saturated pixel or not
> [0x0..0xffffff]
> > + * @aexp_ave4linesy: vertical position of the initial line
> > + * for 4-lines average luminance [0.."height of input
> image - 4"] [line]
> > + */
> > +struct viif_l1_avg_lum_generation_config {
> > + __u32 aexp_start_x;
> > + __u32 aexp_start_y;
> > + __u32 aexp_block_width;
> > + __u32 aexp_block_height;
> > + __u32 aexp_weight[8][8];
> > + __u32 aexp_satur_ratio;
> > + __u32 aexp_black_ratio;
> > + __u32 aexp_satur_level;
> > + __u32 aexp_ave4linesy[4];
> > +};
> > +
> > +/**
> > + * enum viif_l2_undist_mode - L2ISP undistortion mode
> > + * @VIIF_L2_UNDIST_POLY: polynomial mode
> > + * @VIIF_L2_UNDIST_GRID: grid table mode
> > + * @VIIF_L2_UNDIST_POLY_TO_GRID: polynomial, then grid table mode
> > + * @VIIF_L2_UNDIST_GRID_TO_POLY: grid table, then polynomial mode
> > + */
> > +enum viif_l2_undist_mode {
> > + VIIF_L2_UNDIST_POLY = 0,
> > + VIIF_L2_UNDIST_GRID = 1,
> > + VIIF_L2_UNDIST_POLY_TO_GRID = 2,
> > + VIIF_L2_UNDIST_GRID_TO_POLY = 3,
> > +};
> > +
> > +/**
> > + * struct viif_l2_undist - L2ISP UNDIST parameters
> > + * for &struct viif_l2_undist_config
> > + * @through_mode: 1:enable or 0:disable through mode of undistortion
> > + * @roi_mode: &enum viif_l2_undist_mode value. Sets L2ISP undistortion
> mode.
> > + * @sensor_crop_ofs_h: Horizontal start position of sensor crop area[pixel]
> > + * [-4296..4296], accuracy: 1/2
> > + * @sensor_crop_ofs_v: Vertical start position of sensor crop area[line]
> > + * [-2360..2360], accuracy: 1/2
> > + * @norm_scale: Normalization coefficient for distance from center
> > + * [0..1677721], accuracy: 1/33554432
> > + * @valid_r_norm2_poly: Setting target area for polynomial correction
> > + * [0..0x3FFFFFF], accuracy: 1/33554432
> > + * @valid_r_norm2_grid: Setting target area for grid table correction
> > + * [0..0x3FFFFFF], accuracy: 1/33554432
> > + * @roi_write_area_delta: Error adjustment value of forward function and
> > + * inverse function for pixel position calculation
> > + * [0..0x7FF], accuracy: 1/1024
> > + * @poly_write_g_coef: 10th-order polynomial coefficient for G write pixel
> position calculation
> > + * [-2147352576..2147352576], accuracy: 1/131072
> > + * @poly_read_b_coef: 10th-order polynomial coefficient for B read pixel
> position calculation
> > + * [-2147352576..2147352576], accuracy: 1/131072
> > + * @poly_read_g_coef: 10th-order polynomial coefficient for G read pixel
> position calculation
> > + * [-2147352576..2147352576], accuracy: 1/131072
> > + * @poly_read_r_coef: 10th-order polynomial coefficient for R read pixel
> position calculation
> > + * [-2147352576..2147352576], accuracy: 1/131072
> > + * @grid_node_num_h: Number of horizontal grids [16..64]
> > + * @grid_node_num_v: Number of vertical grids [16..64]
> > + * @grid_patch_hsize_inv: Inverse pixel size between horizontal grids
> > + * [0..0x7FFFFF], accuracy: 1/8388608
> > + * @grid_patch_vsize_inv: Inverse pixel size between vertical grids
> > + * [0..0x7FFFFF], accuracy: 1/8388608
> > + */
> > +struct viif_l2_undist {
> > + __u32 through_mode;
> > + __u32 roi_mode[2];
> > + __s32 sensor_crop_ofs_h;
> > + __s32 sensor_crop_ofs_v;
> > + __u32 norm_scale;
> > + __u32 valid_r_norm2_poly;
> > + __u32 valid_r_norm2_grid;
> > + __u32 roi_write_area_delta[2];
> > + __s32 poly_write_g_coef[11];
> > + __s32 poly_read_b_coef[11];
> > + __s32 poly_read_g_coef[11];
> > + __s32 poly_read_r_coef[11];
> > + __u32 grid_node_num_h;
> > + __u32 grid_node_num_v;
> > + __u32 grid_patch_hsize_inv;
> > + __u32 grid_patch_vsize_inv;
> > +};
> > +
> > +/**
> > + * struct viif_l2_undist_config - L2ISP UNDIST parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST`
> > + * @param: &struct viif_l2_undist
> > + * @write_g_addr: Address to write-G grid table.
> > + * Table size is specified by member size.
> > + * Set 0 to disable this table.
> > + * @read_b_addr: Address to read-B grid table.
> > + * Table size is specified by member size.
> > + * Set 0 to disable this table.
> > + * @read_g_addr: Address to read-G grid table.
> > + * Table size is specified by member size.
> > + * Set 0 to disable this table.
> > + * @read_r_addr: Address to read-R grid table.
> > + * Table size is specified by member size.
> > + * Set 0 to disable this table.
> > + * @size: Table size [byte]. Range: [1024..8192] or 0.
> > + * The value should be "grid_node_num_h * grid_node_num_v * 4".
> > + * See also &struct viif_l2_undist.
> > + * Set 0 if NULL is set for all tables.
> > + * Set valid size value if at least one table is valid.
> > + *
> > + * Application should make sure that the table data is based on HW
> specification
> > + * since this driver does not check the contents of specified grid table.
> > + */
> > +struct viif_l2_undist_config {
> > + struct viif_l2_undist param;
> > + __u64 write_g_addr;
> > + __u64 read_b_addr;
> > + __u64 read_g_addr;
> > + __u64 read_r_addr;
> > + __u32 size;
> > +};
> > +
> > +/**
> > + * struct viif_l2_roi_config - L2ISP ROI parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI`
> > + * @roi_num:
> > + * 1 when only capture path0 is activated,
> > + * 2 when both capture path 0 and path 1 are activated.
> > + * @roi_scale: Scale value for each ROI [32768..131072], accuracy: 1/65536
> > + * @roi_scale_inv: Inverse scale value for each ROI [32768..131072],
> accuracy: 1/65536
> > + * @corrected_wo_scale_hsize: Corrected image width for each ROI [pixel]
> [128..8190]
> > + * @corrected_wo_scale_vsize: Corrected image height for each ROI [line]
> [128..4094]
> > + * @corrected_hsize: Corrected and scaled image width for each ROI [pixel]
> [128..8190]
> > + * @corrected_vsize: Corrected and scaled image height for each ROI [line]
> [128..4094]
> > + */
> > +struct viif_l2_roi_config {
> > + __u32 roi_num;
> > + __u32 roi_scale[2];
> > + __u32 roi_scale_inv[2];
> > + __u32 corrected_wo_scale_hsize[2];
> > + __u32 corrected_wo_scale_vsize[2];
> > + __u32 corrected_hsize[2];
> > + __u32 corrected_vsize[2];
> > +};
> > +
> > +/** enum viif_gamma_mode - Gamma correction mode
> > + *
> > + * @VIIF_GAMMA_COMPRESSED: compressed table mode
> > + * @VIIF_GAMMA_LINEAR: linear table mode
> > + */
> > +enum viif_gamma_mode {
> > + VIIF_GAMMA_COMPRESSED = 0,
> > + VIIF_GAMMA_LINEAR = 1,
> > +};
> > +
> > +/**
> > + * struct viif_l2_gamma_config - L2ISP gamma correction parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA`
> > + * @pathid: 0 for Capture Path 0, 1 for Capture Path 1.
> > + * @enable: 1:Enable, 0:Disable settings of L2ISP gamma correction control
> > + * @vsplit: Line switching position of first table and second table [line]
> [0..4094].
> > + * Should set 0 in case 0 is set to @enable
> > + * @mode: &enum viif_gamma_mode value.
> > + * Should set VIIF_GAMMA_COMPRESSED when 0 is set to
> @enable
> > + * @table_addr: Address to gamma table for L2ISP gamma.
> > + * The table has 6 channels;
> > + * [0]: G/Y(1st table), [1]: G/Y(2nd table), [2]: B/U(1st table)
> > + * [3]: B/U(2nd table), [4]: R/V(1st table), [5]: R/V(2nd table)
> > + * Each channel of the table is __u16 typed and 512 bytes.
> > + */
> > +struct viif_l2_gamma_config {
> > + __u32 pathid;
> > + __u32 enable;
> > + __u32 vsplit;
> > + __u32 mode;
> > + __u64 table_addr[6];
> > +};
> > +
> > +/**
> > + * enum viif_csi2_cal_status - CSI2RX calibration status
> > + *
> > + * @VIIF_CSI2_CAL_NOT_DONE: Calibration not complete
> > + * @VIIF_CSI2_CAL_SUCCESS: Calibration success
> > + * @VIIF_CSI2_CAL_FAIL: Calibration failed
> > + */
> > +enum viif_csi2_cal_status {
> > + VIIF_CSI2_CAL_NOT_DONE = 0,
> > + VIIF_CSI2_CAL_SUCCESS = 1,
> > + VIIF_CSI2_CAL_FAIL = 2,
> > +};
> > +
> > +/**
> > + * struct viif_csi2rx_dphy_calibration_status - CSI2-RX D-PHY Calibration
> > + * information
> for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS`
> > + * @term_cal_with_rext: Result of termination calibration with rext
> > + * @clock_lane_offset_cal: Result of offset calibration of clock lane
> > + * @data_lane0_offset_cal: Result of offset calibration of data lane0
> > + * @data_lane1_offset_cal: Result of offset calibration of data lane1
> > + * @data_lane2_offset_cal: Result of offset calibration of data lane2
> > + * @data_lane3_offset_cal: Result of offset calibration of data lane3
> > + * @data_lane0_ddl_tuning_cal: Result of digital delay line tuning calibration
> of data lane0
> > + * @data_lane1_ddl_tuning_cal: Result of digital delay line tuning calibration
> of data lane1
> > + * @data_lane2_ddl_tuning_cal: Result of digital delay line tuning calibration
> of data lane2
> > + * @data_lane3_ddl_tuning_cal: Result of digital delay line tuning calibration
> of data lane3
> > + *
> > + * Values for each member is typed &enum viif_csi2_cal_status.
> > + */
> > +struct viif_csi2rx_dphy_calibration_status {
> > + __u32 term_cal_with_rext;
> > + __u32 clock_lane_offset_cal;
> > + __u32 data_lane0_offset_cal;
> > + __u32 data_lane1_offset_cal;
> > + __u32 data_lane2_offset_cal;
> > + __u32 data_lane3_offset_cal;
> > + __u32 data_lane0_ddl_tuning_cal;
> > + __u32 data_lane1_ddl_tuning_cal;
> > + __u32 data_lane2_ddl_tuning_cal;
> > + __u32 data_lane3_ddl_tuning_cal;
> > +};
> > +
> > +/**
> > + * struct viif_csi2rx_err_status - CSI2RX Error status parameters
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS`
> > + * @err_phy_fatal: D-PHY FATAL error.
> > + *
> > + * * bit[3]: Start of transmission error on DATA Lane3.
> > + * * bit[2]: Start of transmission error on DATA Lane2.
> > + * * bit[1]: Start of transmission error on DATA Lane1.
> > + * * bit[0]: Start of transmission error on DATA Lane0.
> > + * @err_pkt_fatal: Packet FATAL error.
> > + *
> > + * * bit[16]: Header ECC contains 2 errors, unrecoverable.
> > + * * bit[3]: Checksum error detected on virtual channel 3.
> > + * * bit[2]: Checksum error detected on virtual channel 2.
> > + * * bit[1]: Checksum error detected on virtual channel 1.
> > + * * bit[0]: Checksum error detected on virtual channel 0.
> > + * @err_frame_fatal: Frame FATAL error.
> > + *
> > + * * bit[19]: Last received Frame, in virtual channel 3, has at least one CRC
> error.
> > + * * bit[18]: Last received Frame, in virtual channel 2, has at least one CRC
> error.
> > + * * bit[17]: Last received Frame, in virtual channel 1, has at least one CRC
> error.
> > + * * bit[16]: Last received Frame, in virtual channel 0, has at least one CRC
> error.
> > + * * bit[11]: Incorrect Frame Sequence detected in virtual channel 3.
> > + * * bit[10]: Incorrect Frame Sequence detected in virtual channel 2.
> > + * * bit[9]: Incorrect Frame Sequence detected in virtual channel 1.
> > + * * bit[8]: Incorrect Frame Sequence detected in virtual channel 0.
> > + * * bit[3]: Error matching Frame Start with Frame End for virtual channel 3.
> > + * * bit[2]: Error matching Frame Start with Frame End for virtual channel 2.
> > + * * bit[1]: Error matching Frame Start with Frame End for virtual channel 1.
> > + * * bit[0]: Error matching Frame Start with Frame End for virtual channel 0.
> > + * @err_phy: D-PHY error.
> > + *
> > + * * bit[19]: Escape Entry Error on Data Lane 3.
> > + * * bit[18]: Escape Entry Error on Data Lane 2.
> > + * * bit[17]: Escape Entry Error on Data Lane 1.
> > + * * bit[16]: Escape Entry Error on Data Lane 0.
> > + * * bit[3]: Start of Transmission Error on Data Lane 3 (synchronization can
> still be achieved).
> > + * * bit[2]: Start of Transmission Error on Data Lane 2 (synchronization can
> still be achieved).
> > + * * bit[1]: Start of Transmission Error on Data Lane 1 (synchronization can
> still be achieved).
> > + * * bit[0]: Start of Transmission Error on Data Lane 0 (synchronization can
> still be achieved).
> > + * @err_pkt: Packet error.
> > + *
> > + * * bit[19]: Header Error detected and corrected on virtual channel 3.
> > + * * bit[18]: Header Error detected and corrected on virtual channel 2.
> > + * * bit[17]: Header Error detected and corrected on virtual channel 1.
> > + * * bit[16]: Header Error detected and corrected on virtual channel 0.
> > + * * bit[3]: Unrecognized or unimplemented data type detected in virtual
> channel 3.
> > + * * bit[2]: Unrecognized or unimplemented data type detected in virtual
> channel 2.
> > + * * bit[1]: Unrecognized or unimplemented data type detected in virtual
> channel 1.
> > + * * bit[0]: Unrecognized or unimplemented data type detected in virtual
> channel 0.
> > + * @err_line: Line error.
> > + *
> > + * * bit[23]: Error in the sequence of lines for vc7 and dt7.
> > + * * bit[22]: Error in the sequence of lines for vc6 and dt6.
> > + * * bit[21]: Error in the sequence of lines for vc5 and dt5.
> > + * * bit[20]: Error in the sequence of lines for vc4 and dt4.
> > + * * bit[19]: Error in the sequence of lines for vc3 and dt3.
> > + * * bit[18]: Error in the sequence of lines for vc2 and dt2.
> > + * * bit[17]: Error in the sequence of lines for vc1 and dt1.
> > + * * bit[16]: Error in the sequence of lines for vc0 and dt0.
> > + * * bit[7]: Error matching Line Start with Line End for vc7 and dt7.
> > + * * bit[6]: Error matching Line Start with Line End for vc6 and dt6.
> > + * * bit[5]: Error matching Line Start with Line End for vc5 and dt5.
> > + * * bit[4]: Error matching Line Start with Line End for vc4 and dt4.
> > + * * bit[3]: Error matching Line Start with Line End for vc3 and dt3.
> > + * * bit[2]: Error matching Line Start with Line End for vc2 and dt2.
> > + * * bit[1]: Error matching Line Start with Line End for vc1 and dt1.
> > + * * bit[0]: Error matching Line Start with Line End for vc0 and dt0.
> > + */
> > +struct viif_csi2rx_err_status {
> > + __u32 err_phy_fatal;
> > + __u32 err_pkt_fatal;
> > + __u32 err_frame_fatal;
> > + __u32 err_phy;
> > + __u32 err_pkt;
> > + __u32 err_line;
> > +};
> > +
> > +/**
> > + * struct viif_l1_info - L1ISP AWB information
> > + * for &struct viif_isp_capture_status
> > + * @avg_lum_weight: weighted average luminance value at average
> luminance generation
> > + * @avg_lum_block: average luminance of each block [y][x]:
> > + * y means vertical position and x means horizontal
> position
> > + * @avg_lum_four_line_lum: 4-lines average luminance.
> > + * avg_lum_four_line_lum[n] corresponds to
> aexp_ave4linesy[n]
> > + * @avg_satur_pixnum: the number of saturated pixel at average luminance
> generation
> > + * @avg_black_pixnum: the number of black pixel at average luminance
> generation
> > + * @awb_ave_u: U average value of AWB adjustment [pixel]
> > + * @awb_ave_v: V average value of AWB adjustment [pixel]
> > + * @awb_accumulated_pixel: Accumulated pixel count of AWB adjustment
> > + * @awb_gain_r: R gain used in the next frame of AWB adjustment
> > + * @awb_gain_g: G gain used in the next frame of AWB adjustment
> > + * @awb_gain_b: B gain used in the next frame of AWB adjustment
> > + * @awb_status_u: boolean value of U convergence state of AWB adjustment
> > + * (0: not-converged, 1: converged)
> > + * @awb_status_v: boolean value of V convergence state of AWB adjustment
> > + * (0: not-converged, 1: converged)
> > + */
> > +struct viif_l1_info {
> > + __u32 avg_lum_weight;
> > + __u32 avg_lum_block[8][8];
> > + __u32 avg_lum_four_line_lum[4];
> > + __u32 avg_satur_pixnum;
> > + __u32 avg_black_pixnum;
> > + __u32 awb_ave_u;
> > + __u32 awb_ave_v;
> > + __u32 awb_accumulated_pixel;
> > + __u32 awb_gain_r;
> > + __u32 awb_gain_g;
> > + __u32 awb_gain_b;
> > + __u8 awb_status_u;
> > + __u8 awb_status_v;
> > +};
> > +
> > +/**
> > + * struct viif_isp_capture_status - L1ISP capture information
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS`
> > + * @l1_info: L1ISP AWB information. Refer to &struct viif_l1_info
> > + */
> > +struct viif_isp_capture_status {
> > + struct viif_l1_info l1_info;
> > +};
> > +
> > +/**
> > + * struct viif_reported_errors - Errors since last call
> > + * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS`
> > + * @main: error flag value for capture device 0 and 1
> > + * @sub: error flag value for capture device 2
> > + * @csi2rx: error flag value for CSI2 receiver
> > + */
> > +struct viif_reported_errors {
> > + __u32 main;
> > + __u32 sub;
> > + __u32 csi2rx;
> > +};
> > +
> > +#endif /* __UAPI_VISCONTI_VIIF_H_ */
>
> Regards,
>
> Hans
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
` (2 preceding siblings ...)
2023-01-17 10:01 ` Hans Verkuil
@ 2023-01-17 22:39 ` Sakari Ailus
2023-02-01 2:02 ` yuji2.ishikawa
2023-01-18 0:52 ` Laurent Pinchart
4 siblings, 1 reply; 42+ messages in thread
From: Sakari Ailus @ 2023-01-17 22:39 UTC (permalink / raw)
To: Yuji Ishikawa
Cc: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown, linux-media, linux-arm-kernel,
linux-kernel, devicetree
Dear Ishikawa-san,
Thanks for the patchset.
I'd say this is a partial review based on a quick glance, I may have
further comments later on. It's a big patch, some 8000 lines. Please see
the comments below.
On Wed, Jan 11, 2023 at 11:24:29AM +0900, Yuji Ishikawa wrote:
> Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> The interface device includes CSI2 Receiver,
> frame grabber, video DMAC and image signal processor.
> This patch provides operations to handle registers of HW listed above.
>
> The Video DMACs have 32bit address space
> and currently corresponding IOMMU driver is not provided.
> Therefore, memory-block address for captured image is 32bit IOVA
> which is equal to 32bit-truncated phisical address.
> When the Visconti IOMMU driver (currently under development) is accepted,
> the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> ---
> Changelog v2:
> - Resend v1 because a patch exceeds size limit.
>
> Changelog v3:
> - Adapted to media control framework
> - Introduced ISP subdevice, capture device
> - Remove private IOCTLs and add vendor specific V4L2 controls
> - Change function name avoiding camelcase and uppercase letters
>
> Changelog v4:
> - Split patches because the v3 patch exceeds size limit
> - Stop using ID number to identify driver instance:
> - Use dynamically allocated structure to hold driver's context,
> instead of static one indexed by ID number.
> - Functions accept driver's context structure instead of ID number.
>
> Changelog v5:
> - no change
> ---
> drivers/media/platform/Kconfig | 1 +
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/visconti/Kconfig | 9 +
> drivers/media/platform/visconti/Makefile | 8 +
> drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
> drivers/media/platform/visconti/hwd_viif.h | 710 +++++
> .../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
> .../platform/visconti/hwd_viif_internal.h | 340 ++
> .../media/platform/visconti/hwd_viif_reg.h | 2802 +++++++++++++++++
> include/uapi/linux/visconti_viif.h | 1724 ++++++++++
> 10 files changed, 7895 insertions(+)
> create mode 100644 drivers/media/platform/visconti/Kconfig
> create mode 100644 drivers/media/platform/visconti/Makefile
> create mode 100644 drivers/media/platform/visconti/hwd_viif.c
> create mode 100644 drivers/media/platform/visconti/hwd_viif.h
> create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
> create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
> create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
> create mode 100644 include/uapi/linux/visconti_viif.h
>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index a9334263fa9..0908158036d 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -83,6 +83,7 @@ source "drivers/media/platform/sunxi/Kconfig"
> source "drivers/media/platform/ti/Kconfig"
> source "drivers/media/platform/verisilicon/Kconfig"
> source "drivers/media/platform/via/Kconfig"
> +source "drivers/media/platform/visconti/Kconfig"
> source "drivers/media/platform/xilinx/Kconfig"
>
> endif # MEDIA_PLATFORM_DRIVERS
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index a91f4202427..1c67cb56244 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -26,6 +26,7 @@ obj-y += sunxi/
> obj-y += ti/
> obj-y += verisilicon/
> obj-y += via/
> +obj-y += visconti/
> obj-y += xilinx/
>
> # Please place here only ancillary drivers that aren't SoC-specific
> diff --git a/drivers/media/platform/visconti/Kconfig b/drivers/media/platform/visconti/Kconfig
> new file mode 100644
> index 00000000000..031e4610809
> --- /dev/null
> +++ b/drivers/media/platform/visconti/Kconfig
> @@ -0,0 +1,9 @@
> +config VIDEO_VISCONTI_VIIF
> + tristate "Visconti Camera Interface driver"
> + depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER && VIDEO_DEV
> + depends on ARCH_VISCONTI
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_FWNODE
> + help
> + This is V4L2 driver for Toshiba Visconti Camera Interface driver
> +
> diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
> new file mode 100644
> index 00000000000..e14b904df75
> --- /dev/null
> +++ b/drivers/media/platform/visconti/Makefile
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for the Visconti video input device driver
> +#
> +
> +visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> +
> +obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> diff --git a/drivers/media/platform/visconti/hwd_viif.c b/drivers/media/platform/visconti/hwd_viif.c
> new file mode 100644
> index 00000000000..260293fa4d0
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif.c
> @@ -0,0 +1,1690 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
Happy new year!
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +#include "hwd_viif.h"
> +#include "hwd_viif_internal.h"
> +
> +/* MIPI CSI2 DataType definition */
> +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
These are generic MIPI CSI-2 definitions, no need to re-define them for
this driver only.
> +
> +struct hwd_viif_res *allocate_viif_res(struct device *dev, void *csi2host_vaddr,
> + void *capture_vaddr)
> +{
> + struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res), GFP_KERNEL);
> +
> + res->csi2host_reg = csi2host_vaddr;
> + res->capture_reg = capture_vaddr;
> + res->run_flag_main = (bool)false;
What happens here if res is NULL?
I'd advise to perform the allocation outside variable declarations, that
way it is more obvious it may fail (and needs to be checked for).
No need for a cast.
> + return res;
> +}
> +
> +/* Convert the unit of time-period (from sysclk, to num lines in the image) */
> +static u32 sysclk_to_numlines(u64 time_in_sysclk, const struct hwd_viif_input_img *img)
Please run:
$ ./scripts/checkpatch.pl --strict --max-line-length=80
on the set.
> +{
> + u64 v1 = time_in_sysclk * (u64)img->pixel_clock;
You can drop the cast.
> + u64 v2 = (u64)img->htotal_size * HWD_VIIF_SYS_CLK;
> +
> + return (u32)(v1 / v2);
div_u64()?
> +}
> +
> +static u32 lineperiod_in_sysclk(u64 hsize, u64 pixel_clock)
> +{
> + return (u32)(hsize * HWD_VIIF_SYS_CLK / pixel_clock);
You can drop the cast.
And I think you need div_u64() instead.
> +}
> +
> +/**
> + * hwd_viif_main_set_unit() - Set static configuration of MAIN unit(CH0 or CH1)
> + *
> + * @dt_image: DT of image [0x10-0x17, 0x1B, 0x1E, 0x1F, 0x22, 0x24-0x27, 0x2A-0x3F])
> + * @in_img: Pointer to input image information
> + * @color_type: Color type of image [0x0, 0x1E, 0x1F, 0x22, 0x24, 0x2A-0x2D]
> + * @rawpack: RAW pack mode. For more refer @ref hwd_viif_raw_pack_mode
> + * @yuv_conv: YUV422 to YUV444 conversion mode. For more refer @ref hwd_viif_yuv_conversion_mode
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "dt_image" is out of range
> + * - [2] "in_img" is NULL
> + * - [3] member of "in_img" is invalid
> + * - [4] "color_type" is out of range
> + * - [5] "color_type" doesn't meet the condition shown in the below note
> + * - [6] "rawpack" is out of range
> + * - [7] "rawpack" is not HWD_VIIF_RAWPACK_DISABLE when color_type is other than RAW(0x2A-0x2C)
> + * - [8] "yuv_conv" is out of range
> + * - [9] "yuv_conv" is not HWD_VIIF_YUV_CONV_REPEAT
> + * when color_type is other than YUV422(0x1E or 0x1F)
> + *
> + * Note: valid combination between "dt_image" and "color_type" is
> + * - when "dt_image" is [0x10-0x17, 0x1B, 0x25-0x27, 0x2E-0x3F], "color_type" must be [0x2A-0x2D].
> + * - when "dt_image" is valid value and other than [0x10-0x17, 0x1B, 0x25-0x27, 0x2E-0x3F],
> + * "color_type" must be "dt_image"
> + */
> +s32 hwd_viif_main_set_unit(struct hwd_viif_res *res, u32 dt_image,
> + const struct hwd_viif_input_img *in_img, u32 color_type, u32 rawpack,
> + u32 yuv_conv)
> +{
> + u32 total_hact_size = 0U, total_vact_size = 0U;
> + u32 sw_delay0, sw_delay1, hw_delay;
> + u32 val, color, sysclk_num;
> + u32 i;
> +
> + /*
> + * 0x00-0x09: ShortPacket/Undefined
> + * 0x18-0x1A: YUV420
> + * 0x1C,0x1D: YUV420 CSPS
> + * 0x20,0x21,0x23: RGB444, RGB555, RGB666
> + * 0x28,0x29: RAW6, RAW7
> + */
> + if (dt_image <= 0x09U || (dt_image >= 0x18U && dt_image <= 0x1AU) || dt_image == 0x1CU ||
> + dt_image == 0x1DU || dt_image == 0x20U || dt_image == 0x21U || dt_image == 0x23U ||
> + dt_image == 0x28U || dt_image == 0x29U || dt_image > HWD_VIIF_CSI2_MAX_DT) {
> + return -EINVAL;
> + }
> +
> + /*Case: Generic Long Packet, Reserved, User-Defined*/
> + if ((dt_image >= 0x10U && dt_image <= 0x17U) || dt_image == 0x1bU ||
> + (dt_image >= 0x25U && dt_image <= 0x27U) || dt_image >= 0x2eU) {
> + if (color_type != CSI2_DT_RAW8 && color_type != CSI2_DT_RAW10 &&
> + color_type != CSI2_DT_RAW12 && color_type != CSI2_DT_RAW14) {
Could you use the data type defines where applicable? Same above.
> + return -EINVAL;
> + }
> + } else {
> + /*Case: Otherwise: YUV, RGB, RAW*/
> + /*Constraint: color_type must be dt_image*/
> + if (color_type != dt_image)
> + return -EINVAL;
> + }
> +
> + if (!in_img)
> + return -EINVAL;
> + if (rawpack != HWD_VIIF_RAWPACK_DISABLE && rawpack != HWD_VIIF_RAWPACK_MSBFIRST &&
> + rawpack != HWD_VIIF_RAWPACK_LSBFIRST) {
> + return -EINVAL;
> + }
> + if (color_type != CSI2_DT_RAW8 && color_type != CSI2_DT_RAW10 &&
> + color_type != CSI2_DT_RAW12 && rawpack != HWD_VIIF_RAWPACK_DISABLE) {
> + return -EINVAL;
> + }
> +
> + if (in_img->pixel_clock < HWD_VIIF_MIN_PIXEL_CLOCK ||
> + in_img->pixel_clock > HWD_VIIF_MAX_PIXEL_CLOCK ||
> + in_img->htotal_size < HWD_VIIF_MIN_HTOTAL_PIXEL ||
> + in_img->htotal_size > HWD_VIIF_MAX_HTOTAL_PIXEL ||
> + in_img->vtotal_size < HWD_VIIF_MIN_VTOTAL_LINE ||
> + in_img->vtotal_size > HWD_VIIF_MAX_VTOTAL_LINE ||
> + in_img->vbp_size < HWD_VIIF_MIN_VBP_LINE || in_img->vbp_size > HWD_VIIF_MAX_VBP_LINE ||
> + ((in_img->hactive_size % 2U) != 0U) || ((in_img->vactive_size % 2U) != 0U)) {
> + return -EINVAL;
> + }
> +
> + if (in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_LINE &&
> + in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL) {
> + return -EINVAL;
> + }
> +
> + if (in_img->input_num < HWD_VIIF_L1_INPUT_NUM_MIN ||
> + in_img->input_num > HWD_VIIF_L1_INPUT_NUM_MAX) {
> + return -EINVAL;
> + }
> +
> + if (in_img->hobc_width != 0U && in_img->hobc_width != 16U && in_img->hobc_width != 32U &&
> + in_img->hobc_width != 64U && in_img->hobc_width != 128U) {
> + return -EINVAL;
> + }
> +
> + if (in_img->hobc_margin > 30U || ((in_img->hobc_margin % 2U) != 0U))
> + return -EINVAL;
> +
> + if (in_img->hobc_width == 0U && in_img->hobc_margin != 0U)
> + return -EINVAL;
> +
> + if (in_img->hobc_width != 0U && in_img->hobc_margin == 0U)
> + return -EINVAL;
> +
> + if (color_type == CSI2_DT_RAW8 || color_type == CSI2_DT_RAW10 ||
> + color_type == CSI2_DT_RAW12 || color_type == CSI2_DT_RAW14) {
> + /* parameter check in case of L1ISP(in case of RAW) */
> + if (in_img->hactive_size < HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP ||
> + in_img->hactive_size > HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP ||
> + in_img->vactive_size < HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP ||
> + in_img->vactive_size > HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP ||
> + ((in_img->hactive_size % 8U) != 0U)) {
> + return -EINVAL;
> + }
> +
> + /* check vbp range in case of L1ISP on */
> + /* the constant value "7" is configuration margin */
> + val = sysclk_to_numlines(
> + HWD_VIIF_TABLE_LOAD_TIME + HWD_VIIF_REGBUF_ACCESS_TIME * 2U, in_img) +
> + HWD_VIIF_L1_DELAY_W_HDRC + 7U;
> + if (in_img->vbp_size < val)
> + return -EINVAL;
> +
> + /* calculate total of horizontal active size and vertical active size */
> + if (rawpack != HWD_VIIF_RAWPACK_DISABLE) {
> + val = (in_img->hactive_size + in_img->hobc_width + in_img->hobc_margin) *
> + 2U;
> + } else {
> + val = in_img->hactive_size + in_img->hobc_width + in_img->hobc_margin;
> + }
> + if (in_img->interpolation_mode == HWD_VIIF_L1_INPUT_INTERPOLATION_LINE) {
> + total_hact_size = val;
> + total_vact_size = in_img->vactive_size * in_img->input_num;
> + } else {
> + total_hact_size = val * in_img->input_num;
> + total_vact_size = in_img->vactive_size;
> + }
> + } else {
> + /* OTHER input than RAW(L1ISP is off) */
> + if (in_img->hactive_size < HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP ||
> + in_img->hactive_size > HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP ||
> + in_img->vactive_size < HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP ||
> + in_img->vactive_size > HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP ||
> + in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_LINE ||
> + in_img->input_num != HWD_VIIF_L1_INPUT_NUM_MIN || in_img->hobc_width != 0U) {
> + return -EINVAL;
> + }
> +
> + /* check vbp range in case of L1ISP off */
> + /* the constant value "16" is configuration margin */
> + val = sysclk_to_numlines(HWD_VIIF_TABLE_LOAD_TIME + HWD_VIIF_REGBUF_ACCESS_TIME,
> + in_img) +
> + 16U;
> + if (in_img->vbp_size < val)
> + return -EINVAL;
> +
> + total_hact_size = in_img->hactive_size;
> + total_vact_size = in_img->vactive_size;
> + }
> +
> + if (in_img->htotal_size <= total_hact_size ||
> + (in_img->vtotal_size <= (in_img->vbp_size + total_vact_size))) {
> + return -EINVAL;
> + }
> +
> + if (yuv_conv != HWD_VIIF_YUV_CONV_REPEAT && yuv_conv != HWD_VIIF_YUV_CONV_INTERPOLATION)
> + return -EINVAL;
> +
> + if (color_type != CSI2_DT_YUV4228B && color_type != CSI2_DT_YUV42210B &&
> + yuv_conv != HWD_VIIF_YUV_CONV_REPEAT) {
> + return -EINVAL;
> + }
> +
> + /* Set DT and color type of image data */
> + writel((color_type << 8U) | dt_image, &res->capture_reg->sys.IPORTM_MAIN_DT);
> + writel(0x00, &res->capture_reg->sys.IPORTM_OTHER);
> + res->dt_image_main_w_isp = dt_image;
> +
> + /* Set back porch*/
> + writel((in_img->vbp_size << 16U) | HWD_VIIF_HBP_SYSCLK,
> + &res->capture_reg->sys.BACK_PORCH_M);
> +
> + /* single pulse of vsync is input to DPGM */
> + writel(HWD_VIIF_DPGM_VSYNC_PULSE, &res->capture_reg->sys.DPGM_VSYNC_SOURCE);
> +
> + /* image data will be input */
> + /* set preprocess type before L2ISP based on color_type. */
> + if (color_type == CSI2_DT_YUV4228B || color_type == CSI2_DT_YUV42210B) {
> + /* YUV422 */
> + color = 3U;
> + } else if (color_type == CSI2_DT_RGB565 || color_type == CSI2_DT_RGB888) {
> + /* RGB */
> + color = 0U;
> + } else {
> + /* RGB or YUV444 from L1ISP */
> + color = 1U;
> + }
> + writel(color << 4U, &res->capture_reg->sys.PREPROCCESS_FMTM);
> +
> + /* set Total size and valid size information of image data */
> + sysclk_num = lineperiod_in_sysclk(in_img->htotal_size, in_img->pixel_clock);
> + sysclk_num &= GENMASK(15, 0);
> + writel((in_img->vtotal_size << 16U) | sysclk_num, &res->capture_reg->sys.TOTALSIZE_M);
> + writel((total_vact_size << 16U) | total_hact_size, &res->capture_reg->sys.VALSIZE_M);
> +
> + /* set image size information to L2ISP */
> + writel(in_img->vactive_size, &res->capture_reg->l2isp.L2_SENSOR_CROP_VSIZE);
> + writel(in_img->hactive_size, &res->capture_reg->l2isp.L2_SENSOR_CROP_HSIZE);
> +
> + /* RAW input case */
> + if (color_type >= CSI2_DT_RAW8) {
> + val = (in_img->interpolation_mode << 3U) | (in_img->input_num);
> + writel(val, &res->capture_reg->l1isp.L1_IBUF_INPUT_ORDER);
> + writel(in_img->vactive_size, &res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> + writel(in_img->hactive_size, &res->capture_reg->l1isp.L1_SYSM_WIDTH);
> + val = (in_img->hobc_margin << 8U) | in_img->hobc_width;
> + writel(val, &res->capture_reg->l1isp.L1_HOBC_MARGIN);
> + }
> +
> + /* Set rawpack */
> + writel(rawpack, &res->capture_reg->sys.IPORTM_MAIN_RAW);
> +
> + /* Set yuv_conv */
> + writel(yuv_conv, &res->capture_reg->sys.PREPROCCESS_C24M);
> +
> + /* Set vsync delay */
> + hw_delay = in_img->vbp_size - sysclk_to_numlines(HWD_VIIF_TABLE_LOAD_TIME, in_img) + 4U;
> + hw_delay = min(hw_delay, 255U);
> +
> + sw_delay0 = hw_delay - sysclk_to_numlines(HWD_VIIF_REGBUF_ACCESS_TIME, in_img) + 2U;
> +
> + if (color_type == CSI2_DT_RAW8 || color_type == CSI2_DT_RAW10 ||
> + color_type == CSI2_DT_RAW12 || color_type == CSI2_DT_RAW14) {
> + sw_delay1 = sysclk_to_numlines(HWD_VIIF_REGBUF_ACCESS_TIME, in_img) +
> + HWD_VIIF_L1_DELAY_WO_HDRC + 1U;
> + } else {
> + sw_delay1 = 10U;
> + }
> + writel(sw_delay0 << 16U, &res->capture_reg->sys.INT_M0_LINE);
> + writel((sw_delay1 << 16U) | hw_delay, &res->capture_reg->sys.INT_M1_LINE);
> +
> + /* M2_LINE is the same condition as M1_LINE */
> + writel((sw_delay1 << 16U) | hw_delay, &res->capture_reg->sys.INT_M2_LINE);
> +
> + /* Update internal information of pixel clock, htotal_size, information of L2 ROI */
> + res->pixel_clock = in_img->pixel_clock;
> + res->htotal_size = in_img->htotal_size;
> + res->l2_roi_path_info.roi_num = 0;
> + for (i = 0; i < HWD_VIIF_MAX_POST_NUM; i++) {
> + res->l2_roi_path_info.post_enable_flag[i] = false;
> + res->l2_roi_path_info.post_crop_x[i] = 0;
> + res->l2_roi_path_info.post_crop_y[i] = 0;
> + res->l2_roi_path_info.post_crop_w[i] = 0;
> + res->l2_roi_path_info.post_crop_h[i] = 0;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_main_mask_vlatch() - Control Vlatch mask of MAIN unit
> + *
> + * @enable: or disable Vlatch mask of MAIN unit. For more refer @ref hwd_viif_enable_flag.
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - "enable" is out of range
> + */
> +s32 hwd_viif_main_mask_vlatch(struct hwd_viif_res *res, u32 enable)
> +{
> + if (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
> + return -EINVAL;
The function would be nicer to use if it took bool as the argument. You
could remove this check, too.
> +
> + if (enable == HWD_VIIF_ENABLE)
> + enable |= HWD_VIIF_ISP_VLATCH_MASK;
> +
> + /* Control Vlatch mask */
> + writel(enable, &res->capture_reg->sys.IPORTM0_LD);
> + writel(enable, &res->capture_reg->sys.IPORTM1_LD);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_main_status_err_set_irq_mask() - Set mask condition for STATUS error of MAIN unit
> + *
> + * @mask: STATUS error mask condition
> + * Return: None
> + */
> +void hwd_viif_main_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> +{
> + writel(mask, &res->capture_reg->sys.INT_M_MASK);
> +}
> +
> +/**
> + * hwd_viif_main_vsync_set_irq_mask() - Set mask condition for Vsync of MAIN unit
> + *
> + * @mask: Vsync mask condition
> + * Return: None
> + */
> +void hwd_viif_main_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> +{
> + writel(mask, &res->capture_reg->sys.INT_M_SYNC_MASK);
> +}
> +
> +#define VDM_BIT_W00 BIT(0)
> +#define VDM_BIT_W01 BIT(1)
> +#define VDM_BIT_W02 BIT(2)
> +#define VDM_BIT_W03 BIT(3)
> +#define VDM_BIT_W04 BIT(4)
> +#define VDM_BIT_W05 BIT(5)
> +#define VDM_BIT_R00 BIT(0)
> +#define VDM_BIT_R01 BIT(1)
> +#define VDM_BIT_R02 BIT(2)
> +
> +#define VDM_ABORT_MASK_SUB_W (VDM_BIT_W03 | VDM_BIT_W04 | VDM_BIT_W05)
> +#define VDM_ABORT_MASK_MAIN_W (VDM_BIT_W00 | VDM_BIT_W01 | VDM_BIT_W02)
> +#define VDM_ABORT_MASK_MAIN_R (VDM_BIT_R00 | VDM_BIT_R01 | VDM_BIT_R02)
> +
> +/**
> + * hwd_viif_sub_set_unit() - Set static configuration of SUB unit
> + *
> + * @dt_image: DT of image [0x1E, 0x1F, 0x22, 0x24, 0x2A-0x2D]
> + * @in_img: Pointer to input image information
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "dt_image" is out of range
> + * - [2] "in_img" is NULL
> + * - [3] member of "in_img" is invalid
> + */
> +s32 hwd_viif_sub_set_unit(struct hwd_viif_res *res, u32 dt_image,
> + const struct hwd_viif_input_img *in_img)
> +{
> + u32 sysclk_num, temp_delay;
> +
> + if (dt_image < 0x2aU || dt_image > 0x2dU)
> + return -EINVAL;
> +
> + if (!in_img)
> + return -EINVAL;
> +
> + if (in_img->hactive_size != 0U ||
> + in_img->interpolation_mode != HWD_VIIF_L1_INPUT_INTERPOLATION_LINE ||
> + in_img->input_num != HWD_VIIF_L1_INPUT_NUM_MIN || in_img->hobc_width != 0U ||
> + in_img->hobc_margin != 0U) {
> + return -EINVAL;
> + }
> +
> + if (in_img->pixel_clock < HWD_VIIF_MIN_PIXEL_CLOCK ||
> + in_img->pixel_clock > HWD_VIIF_MAX_PIXEL_CLOCK ||
> + in_img->htotal_size < HWD_VIIF_MIN_HTOTAL_PIXEL ||
> + in_img->htotal_size > HWD_VIIF_MAX_HTOTAL_PIXEL ||
> + in_img->vtotal_size < HWD_VIIF_MIN_VTOTAL_LINE ||
> + in_img->vtotal_size > HWD_VIIF_MAX_VTOTAL_LINE ||
> + in_img->vbp_size < HWD_VIIF_MIN_VBP_LINE || in_img->vbp_size > HWD_VIIF_MAX_VBP_LINE ||
> + in_img->vactive_size < HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP ||
> + in_img->vactive_size > HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP ||
> + ((in_img->vactive_size % 2U) != 0U)) {
> + return -EINVAL;
> + }
> +
> + if (in_img->vtotal_size <= (in_img->vbp_size + in_img->vactive_size))
> + return -EINVAL;
> +
> + /* Set DT of image data and DT of long packet data*/
> + writel(dt_image, &res->capture_reg->sys.IPORTS_MAIN_DT);
> + writel(0x00, &res->capture_reg->sys.IPORTS_OTHER);
> +
> + /* Set line size and delay value of delayed Vsync */
> + sysclk_num = lineperiod_in_sysclk(in_img->htotal_size, in_img->pixel_clock);
> + writel(sysclk_num & GENMASK(15, 0), &res->capture_reg->sys.INT_SA0_LINE);
> + temp_delay = in_img->vbp_size - 4U;
> + if (temp_delay > 255U) {
> + /* Replace the value with HW max spec */
> + temp_delay = 255U;
> + }
> + writel(temp_delay, &res->capture_reg->sys.INT_SA1_LINE);
> +
> + return 0;
> +}
> +
> +/* DMA settings */
> +#define VDMAC_SRAM_BASE_ADDR_W03 0x440U
> +#define SRAM_SIZE_W_PORT 0x200
> +#define PORT_SEL_SUB_IMAGE 3
> +
> +/**
> + * hwd_viif_sub_set_img_transmission() - Set image transfer condition of SUB unit
> + *
> + * @img: Pointer to output image information
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] Member of "img" is invalid
> + */
> +s32 hwd_viif_sub_set_img_transmission(struct hwd_viif_res *res, const struct hwd_viif_img *img)
> +{
> + struct hwd_viif_vdm_write_port_reg *wport;
> + u32 img_start_addr, img_end_addr;
> + u32 data_width, pitch, height;
> + u32 k, port_control;
> +
> + /* disable VDMAC when img is NULL */
> + if (!img) {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> + port_control = ~((u32)1U << 3U) & readl(&res->capture_reg->vdm.VDM_W_ENABLE);
> + writel(port_control, &res->capture_reg->vdm.VDM_W_ENABLE);
> + return 0;
> + }
> +
> + if (((img->width % 2U) != 0U) || ((img->height % 2U) != 0U))
> + return -EINVAL;
> +
> + if (img->width < HWD_VIIF_MIN_OUTPUT_IMG_WIDTH ||
> + img->height < HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT ||
> + img->width > HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB ||
> + img->height > HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB) {
> + return -EINVAL;
> + }
> +
> + img_start_addr = (u32)img->pixelmap[0].pmap_paddr;
> + pitch = img->pixelmap[0].pitch;
> + height = img->height;
> +
> + switch (img->format) {
> + case HWD_VIIF_ONE_COLOR_8:
> + data_width = 0U;
> + img_end_addr = img_start_addr + img->width - 1U;
> + k = 1;
> + break;
> + case HWD_VIIF_ONE_COLOR_16:
> + data_width = 1U;
> + img_end_addr = img_start_addr + (img->width * 2U) - 1U;
> + k = 2;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + if ((img_start_addr % 4U) != 0U)
> + return -EINVAL;
> +
> + if ((pitch < (img->width * k)) || pitch > HWD_VIIF_MAX_PITCH || ((pitch % 4U) != 0U))
> + return -EINVAL;
> +
> + wport = &res->capture_reg->vdm.w_port[PORT_SEL_SUB_IMAGE];
> + writel(VDMAC_SRAM_BASE_ADDR_W03, &wport->VDM_W_SRAM_BASE);
> + writel(SRAM_SIZE_W_PORT, &wport->VDM_W_SRAM_SIZE);
> + writel(img_start_addr, &wport->VDM_W_STADR);
> + writel(img_end_addr, &wport->VDM_W_ENDADR);
> + writel(height, &wport->VDM_W_HEIGHT);
> + writel(pitch, &wport->VDM_W_PITCH);
> + writel(data_width << 8U, &wport->VDM_W_CFG0);
> + port_control = BIT(3) | readl(&res->capture_reg->vdm.VDM_W_ENABLE);
> + writel(port_control, &res->capture_reg->vdm.VDM_W_ENABLE);
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_sub_status_err_set_irq_mask() -
> + * Set mask condition for STATUS error of SUB unit or VOIF loopback
> + *
> + * @mask: STATUS error mask condition
> + * Return: None
> + */
> +void hwd_viif_sub_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> +{
> + writel(mask, &res->capture_reg->sys.INT_S_MASK);
> +}
> +
> +/**
> + * hwd_viif_sub_vsync_set_irq_mask() - Set mask condition for Vsync of SUB unit or VOIF loopback
> + *
> + * @mask: Vsync mask condition
> + * Return: None
> + */
> +void hwd_viif_sub_vsync_set_irq_mask(struct hwd_viif_res *res, const u32 mask)
> +{
> + writel(mask, &res->capture_reg->sys.INT_S_SYNC_MASK);
> +}
> +
> +/**
> + * hwd_viif_isp_set_regbuf_auto_transmission() - Set register buffer auto transmission
> + *
> + * Return: None
> + */
> +void hwd_viif_isp_set_regbuf_auto_transmission(struct hwd_viif_res *res)
> +{
> + u32 val;
> +
> + /* Set parameters for auto read transmission of register buffer */
> +
> + if (res->dt_image_main_w_isp != 0x0U) {
> + /*
> + * configuration is done
> + * only when dt_image is not 0, means image data is input to ISP.
> + */
> + writel(0x0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> + writel(0x0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> + writel(HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT,
> + &res->capture_reg->l1isp.L1_CRGBF_TRN_RBADDR);
> + writel(HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT,
> + &res->capture_reg->l1isp.L1_CRGBF_TRN_READDR);
> + writel(HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT,
> + &res->capture_reg->l2isp.L2_CRGBF_TRN_RBADDR);
> + writel(HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT,
> + &res->capture_reg->l2isp.L2_CRGBF_TRN_READDR);
> + val = BIT(16);
> + writel(val, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> + writel(val, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> + }
> +}
> +
> +/**
> + * hwd_viif_isp_disable_regbuf_auto_transmission() - Disable register buffer auto transmission
> + *
> + * Return: None
> + */
> +void hwd_viif_isp_disable_regbuf_auto_transmission(struct hwd_viif_res *res)
> +{
> + if (res->dt_image_main_w_isp != 0x0U) {
> + writel(0x0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> + writel(0x0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> + }
> +}
> +
> +/**
> + * hwd_viif_isp_guard_start() - stop register auto update
> + *
> + *
> + * This function call stops update of some hardware registers
> + * while the manual setup of VIIF, L1ISP registers is in progress.
> + *
> + * * regbuf control: load/store HW register (settings, status) values to backup SRAM.
> + * * vlatch control: copy timer-counter register value to status register.
> + */
> +void hwd_viif_isp_guard_start(struct hwd_viif_res *res)
> +{
> + hwd_viif_isp_disable_regbuf_auto_transmission(res);
> + ndelay(500);
> + hwd_viif_main_mask_vlatch(res, HWD_VIIF_ENABLE);
> +}
> +
> +/**
> + * hwd_viif_isp_guard_start() - restart register auto update
> + *
> + *
> + * see also hwd_viif_isp_guard_start().
> + */
> +void hwd_viif_isp_guard_end(struct hwd_viif_res *res)
> +{
> + hwd_viif_main_mask_vlatch(res, HWD_VIIF_DISABLE);
> + hwd_viif_isp_set_regbuf_auto_transmission(res);
> +}
> +
> +#define L2_STATUS_REPORT_MASK 0x1eU
> +
> +/**
> + * hwd_viif_isp_get_info() - Get processing information of L1ISP and L2ISP
> + *
> + * @l1_info: L1ISP processing information
> + * @l2_transfer_status: status of L2ISP transmission
> + * Return: None
> + */
> +void hwd_viif_isp_get_info(struct hwd_viif_res *res, struct hwd_viif_l1_info *l1_info,
> + u32 *l2_transfer_status)
> +{
> + u32 val, l2_status;
> + int i, j;
> +
> + if (l1_info) {
> + /* change register buffer to regbuf0 where driver gets information */
> + writel(HWD_VIIF_ISP_REGBUF_MODE_BUFFER, &res->capture_reg->l1isp.L1_CRGBF_ACC_CONF);
> +
> + /* get AWB info */
> + l1_info->awb_ave_u = readl(&res->capture_reg->l1isp.L1_AWHB_AVE_USIG);
> + l1_info->awb_ave_v = readl(&res->capture_reg->l1isp.L1_AWHB_AVE_VSIG);
> + l1_info->awb_accumulated_pixel = readl(&res->capture_reg->l1isp.L1_AWHB_NUM_UVON);
> + l1_info->awb_gain_r = readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAINR);
> + l1_info->awb_gain_g = readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAING);
> + l1_info->awb_gain_b = readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAINB);
> + val = readl(&res->capture_reg->l1isp.L1_AWHB_R_CTR_STOP);
> + l1_info->awb_status_u = (FIELD_GET(BIT(1), val) != 0);
> + l1_info->awb_status_v = (FIELD_GET(BIT(0), val) != 0);
> +
> + /* get average luminance info */
> + l1_info->avg_lum_weight = readl(&res->capture_reg->l1isp.L1_AEXP_RESULT_AVE);
> + val = readl(&res->capture_reg->l1isp.L1_AEXP_SATUR_BLACK_PIXNUM);
> + l1_info->avg_satur_pixnum = FIELD_GET(GENMASK(31, 16), val);
> + l1_info->avg_black_pixnum = FIELD_GET(GENMASK(15, 0), val);
> + for (i = 0; i < 8; i++) {
> + for (j = 0; j < 8; j++) {
> + l1_info->avg_lum_block[i][j] =
> + readl(&res->capture_reg->l1isp.L1_AEXP_AVE[i][j]);
> + }
> + }
> + l1_info->avg_lum_four_line_lum[0] =
> + readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES0);
> + l1_info->avg_lum_four_line_lum[1] =
> + readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES1);
> + l1_info->avg_lum_four_line_lum[2] =
> + readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES2);
> + l1_info->avg_lum_four_line_lum[3] =
> + readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES3);
> +
> + /* revert to register access from register buffer access */
> + writel(HWD_VIIF_ISP_REGBUF_MODE_BYPASS, &res->capture_reg->l1isp.L1_CRGBF_ACC_CONF);
> + }
> +
> + if (l2_transfer_status) {
> + /* get L2ISP abort information */
> + l2_status = readl(&res->capture_reg->l2isp.L2_CRGBF_ISP_INT);
> + writel(l2_status, &res->capture_reg->l2isp.L2_CRGBF_ISP_INT);
> + *l2_transfer_status = l2_status & L2_STATUS_REPORT_MASK;
> + }
> +}
> +
> +/**
> + * hwd_viif_isp_set_regbuf_irq_mask() - Set mask condition for ISP register buffer
> + *
> + * @mask_l1: Pointer to mask configuration for L1ISP register buffer interruption
> + * @mask_l2: Pointer to mask configuration for L2ISP register buffer interruption
> + * Return: None
> + */
> +void hwd_viif_isp_set_regbuf_irq_mask(struct hwd_viif_res *res, const u32 *mask_l1,
> + const u32 *mask_l2)
> +{
> + writel(*mask_l1, &res->capture_reg->l1isp.L1_CRGBF_INT_MASK);
> + writel(*mask_l2, &res->capture_reg->l2isp.L2_CRGBF_INT_MASK);
> +}
> +
> +/**
> + * hwd_viif_l2_set_input_csc() - Set input CSC parameters of L2ISP
> + *
> + * @param: Pointer to input csc parameters of L2ISP
> + * @is_l1_rgb: input information of L2ISP
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] Member of "param" is invalid
> + */
> +s32 hwd_viif_l2_set_input_csc(struct hwd_viif_res *res, const struct hwd_viif_csc_param *param,
> + bool is_l1_rgb)
> +{
> + struct hwd_viif_csc_param hwd_param;
> + u32 enable = HWD_VIIF_ENABLE;
> + bool csc_enable_flag = true;
> + u32 i, val;
> +
> + if (param) {
> + if (param->r_cr_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->g_y_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->b_cb_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->r_cr_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->g_y_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->b_cb_out_offset > HWD_VIIF_CSC_MAX_OFFSET) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < HWD_VIIF_CSC_MAX_COEF_NUM; i++) {
> + if (param->coef[i] > HWD_VIIF_CSC_MAX_COEF_VALUE)
> + return -EINVAL;
> + }
> +
> + if (is_l1_rgb) {
> + /* translated parameters are used */
> + hwd_param.r_cr_in_offset = param->b_cb_in_offset;
> + hwd_param.g_y_in_offset = param->r_cr_in_offset;
> + hwd_param.b_cb_in_offset = param->g_y_in_offset;
> + hwd_param.r_cr_out_offset = param->r_cr_out_offset;
> + hwd_param.g_y_out_offset = param->g_y_out_offset;
> + hwd_param.b_cb_out_offset = param->b_cb_out_offset;
> + hwd_param.coef[0] = param->coef[2];
> + hwd_param.coef[1] = param->coef[0];
> + hwd_param.coef[2] = param->coef[1];
> + hwd_param.coef[3] = param->coef[5];
> + hwd_param.coef[4] = param->coef[3];
> + hwd_param.coef[5] = param->coef[4];
> + hwd_param.coef[6] = param->coef[8];
> + hwd_param.coef[7] = param->coef[6];
> + hwd_param.coef[8] = param->coef[7];
> + } else {
> + /* original parameters are used */
> + hwd_param.r_cr_in_offset = param->r_cr_in_offset;
> + hwd_param.g_y_in_offset = param->g_y_in_offset;
> + hwd_param.b_cb_in_offset = param->b_cb_in_offset;
> + hwd_param.r_cr_out_offset = param->r_cr_out_offset;
> + hwd_param.g_y_out_offset = param->g_y_out_offset;
> + hwd_param.b_cb_out_offset = param->b_cb_out_offset;
> + hwd_param.coef[0] = param->coef[0];
> + hwd_param.coef[1] = param->coef[1];
> + hwd_param.coef[2] = param->coef[2];
> + hwd_param.coef[3] = param->coef[3];
> + hwd_param.coef[4] = param->coef[4];
> + hwd_param.coef[5] = param->coef[5];
> + hwd_param.coef[6] = param->coef[6];
> + hwd_param.coef[7] = param->coef[7];
> + hwd_param.coef[8] = param->coef[8];
> + }
> + } else {
> + if (is_l1_rgb) {
> + /* fixed parameters are used */
> + hwd_param.r_cr_in_offset = 0U;
> + hwd_param.g_y_in_offset = 0U;
> + hwd_param.b_cb_in_offset = 0U;
> + hwd_param.r_cr_out_offset = 0U;
> + hwd_param.g_y_out_offset = 0U;
> + hwd_param.b_cb_out_offset = 0U;
> + hwd_param.coef[0] = 0U;
> + hwd_param.coef[1] = 0x1000U;
> + hwd_param.coef[2] = 0U;
> + hwd_param.coef[3] = 0U;
> + hwd_param.coef[4] = 0U;
> + hwd_param.coef[5] = 0x1000U;
> + hwd_param.coef[6] = 0x1000U;
> + hwd_param.coef[7] = 0U;
> + hwd_param.coef[8] = 0U;
> + } else {
> + /* csc is disabled */
> + enable = HWD_VIIF_DISABLE;
> + csc_enable_flag = false;
> + }
> + }
> +
> + if (csc_enable_flag) {
> + writel(hwd_param.g_y_in_offset,
> + &res->capture_reg->sys.l2isp_input_csc.MTB_YG_OFFSETI);
> + writel(hwd_param.coef[0], &res->capture_reg->sys.l2isp_input_csc.MTB_YG1);
> + val = (hwd_param.coef[1] << HWD_VIIF_MTB_CB_YG_COEF_OFFSET) |
> + (hwd_param.coef[2] << HWD_VIIF_MTB_CR_YG_COEF_OFFSET);
> + writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_YG2);
> + writel(hwd_param.g_y_out_offset,
> + &res->capture_reg->sys.l2isp_input_csc.MTB_YG_OFFSETO);
> + writel(hwd_param.b_cb_in_offset,
> + &res->capture_reg->sys.l2isp_input_csc.MTB_CB_OFFSETI);
> + writel(hwd_param.coef[3], &res->capture_reg->sys.l2isp_input_csc.MTB_CB1);
> + val = (hwd_param.coef[4] << HWD_VIIF_MTB_CB_CB_COEF_OFFSET) |
> + (hwd_param.coef[5] << HWD_VIIF_MTB_CR_CB_COEF_OFFSET);
> + writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_CB2);
> + writel(hwd_param.b_cb_out_offset,
> + &res->capture_reg->sys.l2isp_input_csc.MTB_CB_OFFSETO);
> + writel(hwd_param.r_cr_in_offset,
> + &res->capture_reg->sys.l2isp_input_csc.MTB_CR_OFFSETI);
> + writel(hwd_param.coef[6], &res->capture_reg->sys.l2isp_input_csc.MTB_CR1);
> + val = (hwd_param.coef[7] << HWD_VIIF_MTB_CB_CR_COEF_OFFSET) |
> + (hwd_param.coef[8] << HWD_VIIF_MTB_CR_CR_COEF_OFFSET);
> + writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_CR2);
> + writel(hwd_param.r_cr_out_offset,
> + &res->capture_reg->sys.l2isp_input_csc.MTB_CR_OFFSETO);
> + }
> +
> + writel(enable, &res->capture_reg->sys.l2isp_input_csc.MTB);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_undist() - Set undistortion parameters of L2ISP
> + *
> + * @param: Pointer to undistortion parameters of L2ISP
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "param" is NULL
> + * - [2] Member of "param" is invalid
> + */
> +s32 hwd_viif_l2_set_undist(struct hwd_viif_res *res, const struct viif_l2_undist *param)
> +{
> + u32 grid_num_h, grid_num_v;
> + u32 i, val;
> +
> + if (!param)
> + return -EINVAL;
> +
> + if (param->through_mode != HWD_VIIF_ENABLE && param->through_mode != HWD_VIIF_DISABLE)
> + return -EINVAL;
> +
> + if (param->roi_mode[0] != HWD_VIIF_L2_UNDIST_POLY &&
> + param->roi_mode[0] != HWD_VIIF_L2_UNDIST_GRID &&
> + param->roi_mode[0] != HWD_VIIF_L2_UNDIST_POLY_TO_GRID &&
> + param->roi_mode[0] != HWD_VIIF_L2_UNDIST_GRID_TO_POLY) {
> + return -EINVAL;
> + }
> + if (param->roi_mode[1] != HWD_VIIF_L2_UNDIST_POLY &&
> + param->roi_mode[1] != HWD_VIIF_L2_UNDIST_GRID &&
> + param->roi_mode[1] != HWD_VIIF_L2_UNDIST_POLY_TO_GRID &&
> + param->roi_mode[1] != HWD_VIIF_L2_UNDIST_GRID_TO_POLY) {
> + return -EINVAL;
> + }
> + if (param->roi_write_area_delta[0] >= HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA ||
> + param->roi_write_area_delta[1] >= HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA ||
> + param->sensor_crop_ofs_h < HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H ||
> + param->sensor_crop_ofs_h > HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H ||
> + param->sensor_crop_ofs_v < HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V ||
> + param->sensor_crop_ofs_v > HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V ||
> + param->norm_scale > HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE ||
> + param->valid_r_norm2_poly >= HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2 ||
> + param->valid_r_norm2_grid >= HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < HWD_VIIF_L2_UNDIST_POLY_NUM; i++) {
> + if (param->poly_write_g_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> + param->poly_write_g_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
> + param->poly_read_b_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> + param->poly_read_b_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
> + param->poly_read_g_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> + param->poly_read_g_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
> + param->poly_read_r_coef[i] < HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> + param->poly_read_r_coef[i] > HWD_VIIF_L2_UNDIST_MAX_POLY_COEF) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param->grid_node_num_h < HWD_VIIF_L2_UNDIST_MIN_GRID_NUM ||
> + param->grid_node_num_h > HWD_VIIF_L2_UNDIST_MAX_GRID_NUM ||
> + param->grid_node_num_v < HWD_VIIF_L2_UNDIST_MIN_GRID_NUM ||
> + param->grid_node_num_v > HWD_VIIF_L2_UNDIST_MAX_GRID_NUM) {
> + return -EINVAL;
> + }
> +
> + grid_num_h = param->grid_node_num_h;
> + grid_num_v = param->grid_node_num_v;
> + if ((grid_num_h % 2U) != 0U)
> + grid_num_h += 1U;
> +
> + if ((grid_num_v % 2U) != 0U)
> + grid_num_v += 1U;
> +
> + if ((grid_num_v * grid_num_h) > HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM ||
> + param->grid_patch_hsize_inv >= HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV ||
> + param->grid_patch_vsize_inv >= HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV) {
> + return -EINVAL;
> + }
> +
> + val = readl(&res->capture_reg->l2isp.L2_SENSOR_CROP_HSIZE) & GENMASK(12, 0);
> + if (((param->sensor_crop_ofs_h / 2) + ((s16)val)) > 4095)
> + return -EINVAL;
> +
> + val = readl(&res->capture_reg->l2isp.L2_SENSOR_CROP_VSIZE) & GENMASK(11, 0);
> + if (((param->sensor_crop_ofs_v / 2) + ((s16)val)) > 2047)
> + return -EINVAL;
> +
> + /* set parameters related to L2ISP UNDIST */
> + if (param->through_mode == HWD_VIIF_ENABLE) {
> + /* Enable through mode */
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l2isp.L2_MODE);
> + } else {
> + val = (param->roi_mode[0] << 1U) | (param->roi_mode[1] << 3U);
> + writel(val, &res->capture_reg->l2isp.L2_MODE);
> + val = (u32)param->sensor_crop_ofs_h & GENMASK(13, 0);
> + writel(val, &res->capture_reg->l2isp.L2_SENSOR_CROP_OFS_H);
> + val = (u32)param->sensor_crop_ofs_v & GENMASK(12, 0);
> + writel(val, &res->capture_reg->l2isp.L2_SENSOR_CROP_OFS_V);
> + writel(param->norm_scale, &res->capture_reg->l2isp.L2_NORM_SCALE);
> + writel(param->valid_r_norm2_poly, &res->capture_reg->l2isp.L2_VALID_R_NORM2_POLY);
> + writel(param->valid_r_norm2_grid, &res->capture_reg->l2isp.L2_VALID_R_NORM2_GRID);
> + writel(param->roi_write_area_delta[0],
> + &res->capture_reg->l2isp.L2_ROI_WRITE_AREA_DELTA[0]);
> + writel(param->roi_write_area_delta[1],
> + &res->capture_reg->l2isp.L2_ROI_WRITE_AREA_DELTA[1]);
> +
> + for (i = 0; i < HWD_VIIF_L2_UNDIST_POLY_NUM; i++) {
> + val = (u32)param->poly_write_g_coef[i];
> + writel(val, &res->capture_reg->l2isp.L2_POLY10_WRITE_G_COEF[i]);
> + val = (u32)param->poly_read_b_coef[i];
> + writel(val, &res->capture_reg->l2isp.L2_POLY10_READ_B_COEF[i]);
> + val = (u32)param->poly_read_g_coef[i];
> + writel(val, &res->capture_reg->l2isp.L2_POLY10_READ_G_COEF[i]);
> + val = (u32)param->poly_read_r_coef[i];
> + writel(val, &res->capture_reg->l2isp.L2_POLY10_READ_R_COEF[i]);
> + }
> + writel(param->grid_node_num_h, &res->capture_reg->l2isp.L2_GRID_NODE_NUM_H);
> + writel(param->grid_node_num_v, &res->capture_reg->l2isp.L2_GRID_NODE_NUM_V);
> + writel(param->grid_patch_hsize_inv,
> + &res->capture_reg->l2isp.L2_GRID_PATCH_HSIZE_INV);
> + writel(param->grid_patch_vsize_inv,
> + &res->capture_reg->l2isp.L2_GRID_PATCH_VSIZE_INV);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_undist_table_transmission() -
> + * Configure L2ISP transferring grid table for undistortion.
> + *
> + * @write_g: grid table address for G-WRITE(physical address)
> + * @read_b: grid table address for B-READ(physical address)
> + * @read_g: grid table address for G-READ(physical address)
> + * @read_r: grid table address for R-READ(physical address)
> + * @size: of each table [1024..8192] [byte]
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "write_g", "read_b", "read_g" or "read_r" is not 4byte alignment
> + * - "size" is out of range
> + * - "size" is not 0 when all table addresses are 0
> + */
> +s32 hwd_viif_l2_set_undist_table_transmission(struct hwd_viif_res *res, uintptr_t write_g,
> + uintptr_t read_b, uintptr_t read_g, uintptr_t read_r,
> + u32 size)
> +{
> + u32 val = 0U;
> +
> + if (((write_g % HWD_VIIF_L2_VDM_ALIGN) != 0U) || ((read_b % HWD_VIIF_L2_VDM_ALIGN) != 0U) ||
> + ((read_g % HWD_VIIF_L2_VDM_ALIGN) != 0U) || ((read_r % HWD_VIIF_L2_VDM_ALIGN) != 0U)) {
> + return -EINVAL;
> + }
> +
> + if ((size != 0U && size < HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE) ||
> + size > HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE) {
> + return -EINVAL;
> + }
> +
> + if ((size % 4U) != 0U)
size % 4 is enough.
> + return -EINVAL;
> +
> + if (write_g == 0U && read_b == 0U && read_g == 0U && read_r == 0U && size != 0U)
> + return -EINVAL;
> +
> + if ((write_g != 0U || read_b != 0U || read_g != 0U || read_r != 0U) && size == 0U)
> + return -EINVAL;
No explicit comparison with zero is needed here. Same below.
> +
> + /* read_b: t_port[8], read_g: t_port[9], read_r: t_port[10], write_g: t_port[11] */
> + if (read_b != 0U) {
> + writel((u32)read_b, &res->capture_reg->vdm.t_port[8].VDM_T_STADR);
> + writel(size, &res->capture_reg->vdm.t_port[8].VDM_T_SIZE);
> + val |= BIT(8);
> + }
> + if (read_g != 0U) {
> + writel((u32)read_g, &res->capture_reg->vdm.t_port[9].VDM_T_STADR);
> + writel(size, &res->capture_reg->vdm.t_port[9].VDM_T_SIZE);
> + val |= BIT(9);
> + }
> + if (read_r != 0U) {
> + writel((u32)read_r, &res->capture_reg->vdm.t_port[10].VDM_T_STADR);
> + writel(size, &res->capture_reg->vdm.t_port[10].VDM_T_SIZE);
> + val |= BIT(10);
> + }
> + if (write_g != 0U) {
> + writel((u32)write_g, &res->capture_reg->vdm.t_port[11].VDM_T_STADR);
> + writel(size, &res->capture_reg->vdm.t_port[11].VDM_T_SIZE);
> + val |= BIT(11);
> + }
> +
> + if (val != 0U) {
> + /*
> + * Set SRAM base address and size.
> + * t_group[1] is used only to transfer UNDIST table
> + */
> + writel(HWD_VIIF_VDM_CFG_PARAM, &res->capture_reg->vdm.t_group[1].VDM_T_CFG);
> + writel(HWD_VIIF_L2_VDM_GRID_SRAM_BASE,
> + &res->capture_reg->vdm.t_group[1].VDM_T_SRAM_BASE);
> + writel(HWD_VIIF_L2_VDM_GRID_SRAM_SIZE,
> + &res->capture_reg->vdm.t_group[1].VDM_T_SRAM_SIZE);
> + }
> +
> + val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) & ~((u32)0xfU << 8U));
> + writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_roi_num_1() - Set ROI path condition when ROI num is 1
> + */
> +static void hwd_viif_l2_set_roi_num_1(struct hwd_viif_res *res)
> +{
> + struct hwd_viif_l2_roi_path_info *info = &res->l2_roi_path_info;
> + u32 val, x_min, x_max, y_min, y_max;
> + u32 i, x, y, w, h;
> +
> + /* ROI0 is input to POST0 and POST1 */
> + if (info->post_enable_flag[0]) {
> + /* POST0 is enabled */
> + x_min = info->post_crop_x[0];
> + x_max = info->post_crop_x[0] + info->post_crop_w[0];
> + y_min = info->post_crop_y[0];
> + y_max = info->post_crop_y[0] + info->post_crop_h[0];
> + if (info->post_enable_flag[1]) {
> + /* POST1 is enabled */
> + x_min = min(x_min, info->post_crop_x[1]);
> + val = info->post_crop_x[1] + info->post_crop_w[1];
> + x_max = max(x_max, val);
> + y_min = min(y_min, info->post_crop_y[1]);
> + val = info->post_crop_y[1] + info->post_crop_h[1];
> + y_max = max(y_max, val);
> + }
> + x = x_min;
> + y = y_min;
> + w = x_max - x_min;
> + h = y_max - y_min;
> + } else if (info->post_enable_flag[1]) {
> + /* POST0 is disabled and POST1 is enabled */
> + x = info->post_crop_x[1];
> + w = info->post_crop_w[1];
> + y = info->post_crop_y[1];
> + h = info->post_crop_h[1];
> + } else {
> + /* All POSTs are disabled */
> + x = 0;
> + y = 0;
> + w = HWD_VIIF_CROP_MIN_W;
> + h = HWD_VIIF_CROP_MIN_H;
> + }
> + writel(x, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_OFS_H);
> + writel(y, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_OFS_V);
> + writel(w, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_HSIZE);
> + writel(h, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_VSIZE);
> +
> + for (i = 0; i < HWD_VIIF_MAX_POST_NUM; i++) {
> + if (info->post_enable_flag[i])
> + writel(0, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
> + else
> + writel(HWD_VIIF_L2_ROI_NONE, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
This might be more readable as
writel (info->post_enable_flag[i] ? 0 : HWD_VIIF_L2_ROI_NONE,
...);
Up to you.
> + }
> +}
> +
> +/**
> + * hwd_viif_l2_set_roi_num_2() - Set ROI path condition when ROI num is 2
> + */
> +static void hwd_viif_l2_set_roi_num_2(struct hwd_viif_res *res)
> +{
> + struct hwd_viif_l2_roi_path_info *info = &res->l2_roi_path_info;
> + u32 i;
> +
> + for (i = 0; i < HWD_VIIF_L2_ROI_MAX_NUM; i++) {
> + /* ROI-n is the same as CROP area of POST-n */
> + if (info->post_enable_flag[i]) {
> + writel(info->post_crop_x[i],
> + &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_H);
> + writel(info->post_crop_y[i],
> + &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_V);
> + writel(info->post_crop_w[i],
> + &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_HSIZE);
> + writel(info->post_crop_h[i],
> + &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_VSIZE);
> + writel(i, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
> + } else {
> + writel(0, &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_H);
> + writel(0, &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_V);
> + writel(HWD_VIIF_CROP_MIN_W,
> + &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_HSIZE);
> + writel(HWD_VIIF_CROP_MIN_H,
> + &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_VSIZE);
> + writel(HWD_VIIF_L2_ROI_NONE, &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
> + }
> + }
> +}
> +
> +/**
> + * hwd_viif_l2_set_roi_path() - Set ROI path condition
> + */
> +static void hwd_viif_l2_set_roi_path(struct hwd_viif_res *res)
> +{
> + if (res->l2_roi_path_info.roi_num == 1U)
> + hwd_viif_l2_set_roi_num_1(res);
> + else
> + hwd_viif_l2_set_roi_num_2(res);
> +}
> +
> +/**
> + * hwd_viif_l2_set_roi() - Set ROI parameters of L2ISP
> + *
> + * @param: Pointer to ROI parameters of L2ISP
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "param" is NULL
> + * - [2] Member of "param" is invalid
> + *
> + * see also: #hwd_viif_l2_set_roi_path
> + */
> +s32 hwd_viif_l2_set_roi(struct hwd_viif_res *res, const struct viif_l2_roi_config *param)
> +{
> + u32 val;
> + int i;
> +
> + if (!param)
> + return -EINVAL;
> +
> + if (param->roi_num < 1 || param->roi_num > 2)
> + return -EINVAL;
> +
> + for (i = 0; i < 2; i++) {
> + if (param->roi_scale[i] < HWD_VIIF_L2_ROI_MIN_SCALE ||
> + param->roi_scale[i] > HWD_VIIF_L2_ROI_MAX_SCALE ||
> + param->roi_scale_inv[i] < HWD_VIIF_L2_ROI_MIN_SCALE_INV ||
> + param->roi_scale_inv[i] > HWD_VIIF_L2_ROI_MAX_SCALE_INV ||
> + param->corrected_wo_scale_hsize[i] <
> + HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE ||
> + param->corrected_wo_scale_hsize[i] >
> + HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE ||
> + param->corrected_wo_scale_vsize[i] <
> + HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE ||
> + param->corrected_wo_scale_vsize[i] >
> + HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE ||
> + param->corrected_hsize[i] < HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE ||
> + param->corrected_hsize[i] > HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE ||
> + param->corrected_vsize[i] < HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE ||
> + param->corrected_vsize[i] > HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE) {
> + return -EINVAL;
> + }
> + }
> +
> + /* Set the number of ROI and update resource info with roi_num */
> + writel(param->roi_num, &res->capture_reg->l2isp.L2_ROI_NUM);
> + res->l2_roi_path_info.roi_num = param->roi_num;
> +
> + /* Update ROI area and input to each POST */
> + hwd_viif_l2_set_roi_path(res);
> +
> + /* Set the remaining parameters */
> + for (i = 0; i < 2; i++) {
> + writel(param->roi_scale[i], &res->capture_reg->l2isp.roi[i].L2_ROI_SCALE);
> + writel(param->roi_scale_inv[i], &res->capture_reg->l2isp.roi[i].L2_ROI_SCALE_INV);
> + val = (param->corrected_wo_scale_hsize[i] << 13U) | param->corrected_hsize[i];
> + writel(val, &res->capture_reg->l2isp.roi[i].L2_ROI_CORRECTED_HSIZE);
> + val = (param->corrected_wo_scale_vsize[i] << 12U) | param->corrected_vsize[i];
> + writel(val, &res->capture_reg->l2isp.roi[i].L2_ROI_CORRECTED_VSIZE);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_gamma() - Set Gamma correction parameters of L2ISP
> + *
> + * @post_id: POST ID [0..1]
> + * @enable: or disable gamma correction of L2ISP. For more refer @ref hwd_viif_enable_flag.
> + * @vsplit: changing line position from 1st table to 2nd table [0..4094]
> + * @mode: Gamma correction mode. For more refer @ref hwd_viif_gamma_table_mode.
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "post_id", "enable", "vsplit" or "mode" is out of range
> + * - [2] "vsplit" is not 0 when "enable" is HWD_VIIF_DISABLE
> + * - [3] "mode" is not HWD_VIIF_GAMMA_COMPRESSED when enable is HWD_VIIF_DISABLE
> + *
> + * see also: #hwd_viif_l2_set_gamma
> + */
> +s32 hwd_viif_l2_set_gamma(struct hwd_viif_res *res, u32 post_id, u32 enable, u32 vsplit, u32 mode)
> +{
> + u32 val;
> +
> + if (post_id >= HWD_VIIF_MAX_POST_NUM ||
> + (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE) ||
> + vsplit > HWD_VIIF_GAMMA_MAX_VSPLIT ||
> + (mode != HWD_VIIF_GAMMA_COMPRESSED && mode != HWD_VIIF_GAMMA_LINEAR) ||
> + (enable == HWD_VIIF_DISABLE && vsplit != 0x0U) ||
> + (enable == HWD_VIIF_DISABLE && mode != HWD_VIIF_GAMMA_COMPRESSED)) {
> + return -EINVAL;
> + }
> +
> + /* Set gamma parameters of L2ISP */
> + val = (vsplit << 16U) | (mode << 4U) | enable;
> + writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_GAMMA_M);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_gamma_table_transmission() - Configure L2ISP transferring gamma table.
> + *
> + * @post_id: POST ID [0..1]
> + * @gamma_table: Pointer to gamma table information
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "post_id" is out of range
> + * - [2] Member of "gamma_table" is invalid
> + */
> +s32 hwd_viif_l2_set_gamma_table_transmission(struct hwd_viif_res *res, u32 post_id,
> + const struct hwd_viif_l2_gamma_table *gamma_table)
> +{
> + u32 vdm_enable = 0U;
> + u32 i, base_addr;
> +
> + if (post_id >= HWD_VIIF_MAX_POST_NUM)
> + return -EINVAL;
> +
> + for (i = 0; i < 6U; i++) {
> + if ((gamma_table->table[i] % HWD_VIIF_L2_VDM_ALIGN) != 0U)
> + return -EINVAL;
> + }
> +
> + /* table[0]: LUT0-G/Y: t_port[12 + post_id * 6] */
> + /* table[1]: LUT1-G/Y: t_port[13 + post_id * 6] */
> + /* table[2]: LUT0-B/U: t_port[14 + post_id * 6] */
> + /* table[3]: LUT1-B/U: t_port[15 + post_id * 6] */
> + /* table[4]: LUT0-R/V: t_port[16 + post_id * 6] */
> + /* table[5]: LUT1-R/V: t_port[17 + post_id * 6] */
> + for (i = 0; i < 6U; i++) {
> + if (gamma_table->table[i] != 0U) {
> + int idx = 12U + i + post_id * 6U;
> +
> + writel((u32)gamma_table->table[i],
> + &res->capture_reg->vdm.t_port[idx].VDM_T_STADR);
> + writel(HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE,
> + &res->capture_reg->vdm.t_port[idx].VDM_T_SIZE);
> + vdm_enable |= BIT(i);
> + }
> + }
> + if (vdm_enable != 0U) {
> + /* t_group[2..3] is used only to transfer GAMMA table */
> + /* [2]: POST0, [3]: POST1 */
> + writel(HWD_VIIF_VDM_CFG_PARAM,
> + &res->capture_reg->vdm.t_group[(post_id + 2U)].VDM_T_CFG);
> + base_addr = HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE +
> + (HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE * post_id);
> + writel(base_addr, &res->capture_reg->vdm.t_group[(post_id + 2U)].VDM_T_SRAM_BASE);
> + writel(HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE,
> + &res->capture_reg->vdm.t_group[(post_id + 2U)].VDM_T_SRAM_SIZE);
> + vdm_enable = vdm_enable << (12U + (post_id * 6U));
> + }
> + vdm_enable |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) &
> + ~((u32)0x3fU << (12U + (post_id * 6U))));
> + writel(vdm_enable, &res->capture_reg->vdm.VDM_T_ENABLE);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_output_csc() - Set output CSC parameters of L2ISP
> + *
> + * @post_id: POST ID [0..1]
> + * @param: Pointer to output csc parameters of L2ISP
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "post_id" is out of range
> + * - [2] Member of "param" is invalid
> + */
> +s32 hwd_viif_l2_set_output_csc(struct hwd_viif_res *res, u32 post_id,
> + const struct hwd_viif_csc_param *param)
> +{
> + struct hwd_viif_l2isp_post_reg *reg_l2isp_post;
> + u32 i, val;
> +
> + if (post_id >= HWD_VIIF_MAX_POST_NUM)
> + return -EINVAL;
> +
> + /* disable csc matrix when param is NULL */
> + if (!param) {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l2isp.post[post_id].csc.MTB);
> + return 0;
> + }
> +
> + /* param is specified: go further check */
> + if (param->r_cr_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->g_y_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->b_cb_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->r_cr_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->g_y_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> + param->b_cb_out_offset > HWD_VIIF_CSC_MAX_OFFSET) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < HWD_VIIF_CSC_MAX_COEF_NUM; i++) {
> + if (param->coef[i] > HWD_VIIF_CSC_MAX_COEF_VALUE)
> + return -EINVAL;
> + }
> +
> + reg_l2isp_post = &res->capture_reg->l2isp.post[post_id];
> +
> + writel(param->g_y_in_offset, ®_l2isp_post->csc.MTB_YG_OFFSETI);
> + writel(param->coef[0], ®_l2isp_post->csc.MTB_YG1);
> + val = (param->coef[1] << HWD_VIIF_MTB_CB_YG_COEF_OFFSET) |
> + (param->coef[2] << HWD_VIIF_MTB_CR_YG_COEF_OFFSET);
> + writel(val, ®_l2isp_post->csc.MTB_YG2);
> + writel(param->g_y_out_offset, ®_l2isp_post->csc.MTB_YG_OFFSETO);
> + writel(param->b_cb_in_offset, ®_l2isp_post->csc.MTB_CB_OFFSETI);
> + writel(param->coef[3], ®_l2isp_post->csc.MTB_CB1);
> + val = (param->coef[4] << HWD_VIIF_MTB_CB_CB_COEF_OFFSET) |
> + (param->coef[5] << HWD_VIIF_MTB_CR_CB_COEF_OFFSET);
> + writel(val, ®_l2isp_post->csc.MTB_CB2);
> + writel(param->b_cb_out_offset, ®_l2isp_post->csc.MTB_CB_OFFSETO);
> + writel(param->r_cr_in_offset, ®_l2isp_post->csc.MTB_CR_OFFSETI);
> + writel(param->coef[6], ®_l2isp_post->csc.MTB_CR1);
> + val = (param->coef[7] << HWD_VIIF_MTB_CB_CR_COEF_OFFSET) |
> + (param->coef[8] << HWD_VIIF_MTB_CR_CR_COEF_OFFSET);
> + writel(val, ®_l2isp_post->csc.MTB_CR2);
> + writel(param->r_cr_out_offset, ®_l2isp_post->csc.MTB_CR_OFFSETO);
> + writel(HWD_VIIF_ENABLE, ®_l2isp_post->csc.MTB);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l2_set_img_transmission() - Set image transfer condition of L2ISP
> + *
> + * @post_id: POST ID [0..1]
> + * @enable: or disable image transfer of MAIN unit. For more refer @ref hwd_viif_enable_flag.
> + * @src: Pointer to crop area information
> + * @out_process: Pointer to output process information
> + * @img: Pointer to output image information
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "post_id" or "enable" is out of range
> + * - [2] "src" or "out_process" is NULL when "enable" is HWD_VIIF_ENABLE
> + * - [3] "src" or "out_process" is not NULL when "enable" is HWD_VIIF_DISABLE
> + * - [4] Member of "src" is out of range
> + * - [5] "w" of "src" is not equal to 2 * "width" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> + * - [6] "h" of "src" is not equal to 2 * "height" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> + * - [7] "w" of "src" is not equal to "width" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> + * - [8] "h" of "src" is not equal to "height" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> + * - [9] Member of "out_process" is invalid
> + * - [10] "alpha" of "out_process" is not 0 when "format" of "img" is not HWD_VIIF_ARGB8888_PACKED
> + * - [11] "format" of "img" is not HWD_VIIF_ONE_COLOR_8 or HWD_VIIF_ONE_COLOR_16
> + * when "select_color" of "out_process"
> + * is HWD_VIIF_COLOR_Y_G, HWD_VIIF_COLOR_U_B or HWD_VIIF_COLOR_V_R
> + * - [12] Member of "img" is invalid
> + *
> + * see also: #hwd_viif_l2_set_roi_path
> + */
> +s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id, u32 enable,
> + const struct hwd_viif_img_area *src,
> + const struct hwd_viif_out_process *out_process,
> + const struct hwd_viif_img *img)
> +{
> + u32 pitch[HWD_VIIF_MAX_PLANE_NUM], img_start_addr[HWD_VIIF_MAX_PLANE_NUM];
> + u32 i, val, loop, k, r[HWD_VIIF_MAX_PLANE_NUM];
> + s32 ret = 0;
> +
> + /* pitch alignment for planar or one color format */
> + u32 pitch_align = 128U;
> +
> + if (post_id >= HWD_VIIF_MAX_POST_NUM ||
> + (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE) ||
> + (enable == HWD_VIIF_ENABLE && (!src || !out_process)) ||
> + (enable == HWD_VIIF_DISABLE && (src || out_process))) {
> + return -EINVAL;
> + }
> +
> + /* DISABLE: no DMA transmission setup, set minimum crop rectangle */
> + if (enable == HWD_VIIF_DISABLE) {
> + res->l2_roi_path_info.post_enable_flag[post_id] = false;
> + res->l2_roi_path_info.post_crop_x[post_id] = 0U;
> + res->l2_roi_path_info.post_crop_y[post_id] = 0U;
> + res->l2_roi_path_info.post_crop_w[post_id] = HWD_VIIF_CROP_MIN_W;
> + res->l2_roi_path_info.post_crop_h[post_id] = HWD_VIIF_CROP_MIN_H;
> + hwd_viif_l2_set_roi_path(res);
> +
> + return 0;
> + }
> +
> + /* further parameter check for ENABLE */
> + if (out_process->half_scale != HWD_VIIF_ENABLE &&
> + out_process->half_scale != HWD_VIIF_DISABLE) {
> + return -EINVAL;
> + }
> +
> + if (out_process->select_color != HWD_VIIF_COLOR_Y_G &&
> + out_process->select_color != HWD_VIIF_COLOR_U_B &&
> + out_process->select_color != HWD_VIIF_COLOR_V_R &&
> + out_process->select_color != HWD_VIIF_COLOR_YUV_RGB) {
> + return -EINVAL;
> + }
> +
> + if (img->format != HWD_VIIF_ARGB8888_PACKED && out_process->alpha != 0U)
> + return -EINVAL;
> +
> + if (((img->width % 2U) != 0U) || ((img->height % 2U) != 0U) ||
> + img->width < HWD_VIIF_MIN_OUTPUT_IMG_WIDTH ||
> + img->height < HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT ||
> + img->width > HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP ||
> + img->height > HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP) {
> + return -EINVAL;
> + }
> +
> + if (src->x > HWD_VIIF_CROP_MAX_X_ISP || src->y > HWD_VIIF_CROP_MAX_Y_ISP ||
> + src->w < HWD_VIIF_CROP_MIN_W || src->w > HWD_VIIF_CROP_MAX_W_ISP ||
> + src->h < HWD_VIIF_CROP_MIN_H || src->h > HWD_VIIF_CROP_MAX_H_ISP) {
> + return -EINVAL;
> + }
> +
> + if (out_process->half_scale == HWD_VIIF_ENABLE) {
> + if ((src->w != (img->width * 2U)) || (src->h != (img->height * 2U)))
> + return -EINVAL;
> + } else {
> + if (src->w != img->width || src->h != img->height)
> + return -EINVAL;
> + }
> +
> + if (out_process->select_color == HWD_VIIF_COLOR_Y_G ||
> + out_process->select_color == HWD_VIIF_COLOR_U_B ||
> + out_process->select_color == HWD_VIIF_COLOR_V_R) {
> + if (img->format != HWD_VIIF_ONE_COLOR_8 && img->format != HWD_VIIF_ONE_COLOR_16)
> + return -EINVAL;
> + }
> +
> + /* build DMAC parameter */
> + switch (img->format) {
> + case HWD_VIIF_YCBCR422_8_PACKED:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 2U;
> + r[0] = 1U;
> + pitch_align = 256U;
> + break;
> + case HWD_VIIF_RGB888_PACKED:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 3U;
> + r[0] = 1U;
> + pitch_align = 384U;
> + break;
> + case HWD_VIIF_ARGB8888_PACKED:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 4U;
> + r[0] = 1U;
> + pitch_align = 512U;
> + break;
> + case HWD_VIIF_ONE_COLOR_8:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 1U;
> + r[0] = 1U;
> + break;
> + case HWD_VIIF_ONE_COLOR_16:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 2U;
> + r[0] = 1U;
> + break;
> + case HWD_VIIF_YCBCR422_8_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 1U;
> + r[0] = 1U;
> + r[1] = 2U;
> + r[2] = 2U;
> + break;
> + case HWD_VIIF_RGB888_YCBCR444_8_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 1U;
> + r[0] = 1U;
> + r[1] = 1U;
> + r[2] = 1U;
> + break;
> + case HWD_VIIF_YCBCR422_16_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 2U;
> + r[0] = 1U;
> + r[1] = 2U;
> + r[2] = 2U;
> + break;
> + case HWD_VIIF_RGB161616_YCBCR444_16_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 2U;
> + r[0] = 1U;
> + r[1] = 1U;
> + r[2] = 1U;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < loop; i++) {
> + val = max(((img->width * k) / r[i]), 128U);
> + if (pitch[i] < val || pitch[i] > HWD_VIIF_MAX_PITCH_ISP ||
> + ((pitch[i] % pitch_align) != 0U) || ((img_start_addr[i] % 4U) != 0U)) {
> + return -EINVAL;
> + }
> + }
> +
> + writel(img_start_addr[0], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_G);
> + writel(pitch[0], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_G);
> + if (loop == HWD_VIIF_MAX_PLANE_NUM) {
> + writel(img_start_addr[1],
> + &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_B);
> + writel(img_start_addr[2],
> + &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_R);
> + writel(pitch[1], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_B);
> + writel(pitch[2], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_R);
> + }
> +
> + /* Set CROP */
> + val = (src->y << 16U) | src->x;
> + writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_OFFSET);
> + val = (src->h << 16U) | src->w;
> + writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_SIZE);
> +
> + /* Set output process */
> + writel(out_process->half_scale,
> + &res->capture_reg->l2isp.post[post_id].L2_POST_HALF_SCALE_EN);
> + writel(out_process->select_color, &res->capture_reg->l2isp.post[post_id].L2_POST_C_SELECT);
> + writel((u32)out_process->alpha, &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTALP);
> + writel(img->format, &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTFMT);
> +
> + /* Update ROI area and input to each POST */
> + res->l2_roi_path_info.post_enable_flag[post_id] = true;
> + res->l2_roi_path_info.post_crop_x[post_id] = src->x;
> + res->l2_roi_path_info.post_crop_y[post_id] = src->y;
> + res->l2_roi_path_info.post_crop_w[post_id] = src->w;
> + res->l2_roi_path_info.post_crop_h[post_id] = src->h;
> + hwd_viif_l2_set_roi_path(res);
> +
> + return ret;
> +}
> +
> +/**
> + * hwd_viif_l2_set_irq_mask() - Set mask condition for L2ISP
> + *
> + * @mask: L2ISP mask condition
> + * Return: None
> + */
> +void hwd_viif_l2_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> +{
> + writel(mask, &res->capture_reg->l2isp.L2_CRGBF_ISP_INT_MASK);
> +}
> +
> +/**
> + * hwd_viif_csi2rx_err_irq_handler() - CSI-2 RX error interruption handler
> + *
> + * Return: event information of CSI-2 RX error interruption
> + */
> +u32 hwd_viif_csi2rx_err_irq_handler(struct hwd_viif_res *res)
> +{
> + return readl(&res->csi2host_reg->CSI2RX_INT_ST_MAIN);
> +}
> +
> +/**
> + * hwd_viif_status_err_irq_handler() - STATUS error interruption handler
> + *
> + * @event_main: information of STATUS error interruption of MAIN unit
> + * @event_sub: information of STATUS error interruption of SUB unit(CH0 and CH1)
> + * Return: None
> + */
> +void hwd_viif_status_err_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub)
> +{
> + u32 val, mask;
> +
> + *event_main = HWD_VIIF_NO_EVENT;
> + *event_sub = HWD_VIIF_NO_EVENT;
> +
> + val = readl(&res->capture_reg->sys.INT_M_STATUS);
> + mask = readl(&res->capture_reg->sys.INT_M_MASK);
> + val = val & ~mask;
> + if (val != HWD_VIIF_NO_EVENT) {
> + writel(val, &res->capture_reg->sys.INT_M_STATUS);
> + *event_main = val;
> + }
> +
> + val = readl(&res->capture_reg->sys.INT_S_STATUS);
> + mask = readl(&res->capture_reg->sys.INT_S_MASK);
> + val = val & ~mask;
> + if (val != HWD_VIIF_NO_EVENT) {
> + writel(val, &res->capture_reg->sys.INT_S_STATUS);
> + *event_sub = val;
> + }
> +}
> +
> +/**
> + * hwd_viif_vsync_irq_handler() - Vsync interruption handler
> + *
> + * @event_main: information of Vsync interruption of MAIN unit
> + * @event_sub: information of Vsync interruption of SUB unit(CH0 and CH1)
> + * Return: None
> + */
> +void hwd_viif_vsync_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub)
> +{
> + u32 val, mask;
> +
> + *event_main = HWD_VIIF_NO_EVENT;
> + *event_sub = HWD_VIIF_NO_EVENT;
> +
> + val = readl(&res->capture_reg->sys.INT_M_SYNC);
> + mask = readl(&res->capture_reg->sys.INT_M_SYNC_MASK);
> + val = val & ~mask;
> + if (val != HWD_VIIF_NO_EVENT) {
> + writel(val, &res->capture_reg->sys.INT_M_SYNC);
> + *event_main = val;
> + }
> +
> + val = readl(&res->capture_reg->sys.INT_S_SYNC);
> + mask = readl(&res->capture_reg->sys.INT_S_SYNC_MASK);
> + val = val & ~mask;
> + if (val != HWD_VIIF_NO_EVENT) {
> + writel(val, &res->capture_reg->sys.INT_S_SYNC);
> + *event_sub = val;
> + }
> +}
> +
> +/**
> + * hwd_viif_isp_regbuf_irq_handler() - ISP register buffer interruption handler
> + *
> + * @event_l1: information of register buffer interruption of L1ISP
> + * @event_l2: information of register buffer interruption of L2ISP
> + * Return: None
> + */
> +void hwd_viif_isp_regbuf_irq_handler(struct hwd_viif_res *res, u32 *event_l1, u32 *event_l2)
> +{
> + u32 val;
> +
> + *event_l1 = HWD_VIIF_NO_EVENT;
> + *event_l2 = HWD_VIIF_NO_EVENT;
> +
> + val = readl(&res->capture_reg->l1isp.L1_CRGBF_INT_MASKED_STAT);
> + if (val != HWD_VIIF_NO_EVENT) {
> + *event_l1 = val;
> + writel(val, &res->capture_reg->l1isp.L1_CRGBF_INT_STAT);
> + }
> +
> + val = readl(&res->capture_reg->l2isp.L2_CRGBF_INT_MASKED_STAT);
> + if (val != HWD_VIIF_NO_EVENT) {
> + *event_l2 = val;
> + writel(val, &res->capture_reg->l2isp.L2_CRGBF_INT_STAT);
> + }
> +}
> diff --git a/drivers/media/platform/visconti/hwd_viif.h b/drivers/media/platform/visconti/hwd_viif.h
> new file mode 100644
> index 00000000000..100afda8436
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif.h
> @@ -0,0 +1,710 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_H
> +#define HWD_VIIF_H
> +
> +#include <linux/errno.h>
> +#include <linux/types.h>
> +
> +#include <linux/visconti_viif.h>
> +
> +enum hwd_power_ctrl {
> + HWD_POWER_OFF = 0, /**< Power off */
> + HWD_POWER_ON /**< Power on */
> +};
> +
> +/* MIPI CSI2 Data Types */
> +#define VISCONTI_CSI2_DT_YUV4228B 0x1E
> +#define VISCONTI_CSI2_DT_YUV42210B 0x1F
> +#define VISCONTI_CSI2_DT_RGB565 0x22
> +#define VISCONTI_CSI2_DT_RGB888 0x24
> +#define VISCONTI_CSI2_DT_RAW8 0x2A
> +#define VISCONTI_CSI2_DT_RAW10 0x2B
> +#define VISCONTI_CSI2_DT_RAW12 0x2C
> +#define VISCONTI_CSI2_DT_RAW14 0x2D
Please use the definitions in media/mipi-csi2.h .
> +
> +/* hwd_viif_enable_flag */
> +#define HWD_VIIF_DISABLE (0U)
> +#define HWD_VIIF_ENABLE (1U)
> +
> +/* hwd_viif_memory_sync_type */
> +#define HWD_VIIF_MEM_SYNC_INTERNAL (0U)
> +#define HWD_VIIF_MEM_SYNC_CSI2 (1U)
> +
> +/* hwd_viif_color_format */
> +#define HWD_VIIF_YCBCR422_8_PACKED (0U)
> +#define HWD_VIIF_RGB888_PACKED (1U)
> +#define HWD_VIIF_ARGB8888_PACKED (3U)
> +#define HWD_VIIF_YCBCR422_8_PLANAR (8U)
> +#define HWD_VIIF_RGB888_YCBCR444_8_PLANAR (9U)
> +#define HWD_VIIF_ONE_COLOR_8 (11U)
> +#define HWD_VIIF_YCBCR422_16_PLANAR (12U)
> +#define HWD_VIIF_RGB161616_YCBCR444_16_PLANAR (13U)
> +#define HWD_VIIF_ONE_COLOR_16 (15U)
> +
> +/* hwd_viif_raw_pack_mode */
> +#define HWD_VIIF_RAWPACK_DISABLE (0U)
> +#define HWD_VIIF_RAWPACK_MSBFIRST (2U)
> +#define HWD_VIIF_RAWPACK_LSBFIRST (3U)
> +
> +/* hwd_viif_yuv_conversion_mode */
> +#define HWD_VIIF_YUV_CONV_REPEAT (0U)
> +#define HWD_VIIF_YUV_CONV_INTERPOLATION (1U)
> +
> +/* hwd_viif_gamma_table_mode */
> +#define HWD_VIIF_GAMMA_COMPRESSED (0U)
> +#define HWD_VIIF_GAMMA_LINEAR (1U)
> +
> +/* hwd_viif_output_color_mode */
> +#define HWD_VIIF_COLOR_Y_G (0U)
> +#define HWD_VIIF_COLOR_U_B (1U)
> +#define HWD_VIIF_COLOR_V_R (2U)
> +#define HWD_VIIF_COLOR_YUV_RGB (4U)
> +
> +/* hwd_viif_hw_params */
> +#define HWD_VIIF_MAX_CH (6U)
> +#define HWD_VIIF_MAX_PLANE_NUM (3U)
> +
> +/**
> + * enum hwd_viif_csi2_dphy - D-PHY Lane assignment
> + *
> + * specifies which line(L0-L3) is assigned to D0-D3
> + */
> +enum hwd_viif_csi2_dphy {
> + HWD_VIIF_CSI2_DPHY_L0L1L2L3 = 0U,
> + HWD_VIIF_CSI2_DPHY_L0L3L1L2 = 1U,
> + HWD_VIIF_CSI2_DPHY_L0L2L3L1 = 2U,
> + HWD_VIIF_CSI2_DPHY_L0L1L3L2 = 4U,
> + HWD_VIIF_CSI2_DPHY_L0L3L2L1 = 5U,
> + HWD_VIIF_CSI2_DPHY_L0L2L1L3 = 6U
> +};
> +
> +/* hwd_viif_csi2rx_cal_status */
> +#define HWD_VIIF_CSI2_CAL_NOT_DONE (0U)
> +#define HWD_VIIF_CSI2_CAL_SUCCESS (1U)
> +#define HWD_VIIF_CSI2_CAL_FAIL (2U)
> +
> +/* hwd_viif_csi2rx_not_capture */
> +#define HWD_VIIF_CSI2_NOT_CAPTURE (-1) /**< csi2 not capture */
> +
> +/* hwd_viif_l1_input_mode */
> +#define HWD_VIIF_L1_INPUT_HDR (0U)
> +#define HWD_VIIF_L1_INPUT_PWL (1U)
> +#define HWD_VIIF_L1_INPUT_SDR (2U)
> +#define HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT (3U)
> +#define HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT (4U)
> +
> +/* hwd_viif_l1_raw_color_filter_mode */
> +#define HWD_VIIF_L1_RAW_GR_R_B_GB (0U)
> +#define HWD_VIIF_L1_RAW_R_GR_GB_B (1U)
> +#define HWD_VIIF_L1_RAW_B_GB_GR_R (2U)
> +#define HWD_VIIF_L1_RAW_GB_B_R_GR (3U)
> +
> +/* hwd_viif_l1_input_interpolation_mode */
> +#define HWD_VIIF_L1_INPUT_INTERPOLATION_LINE (0U)
> +#define HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL (1U)
> +
> +/* hwd_viif_l1_img_sens */
> +#define HWD_VIIF_L1_IMG_SENSITIVITY_HIGH (0U)
> +#define HWD_VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED (1U)
> +#define HWD_VIIF_L1_IMG_SENSITIVITY_LOW (2U)
> +
> +/* hwd_viif_l1_dpc */
> +#define HWD_VIIF_L1_DPC_1PIXEL (0U)
> +#define HWD_VIIF_L1_DPC_2PIXEL (1U)
> +
> +/* hwd_viif_l1_rcnr_hry_type */
> +#define HWD_VIIF_L1_RCNR_LOW_RESOLUTION (0U)
> +#define HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION (1U)
> +#define HWD_VIIF_L1_RCNR_HIGH_RESOLUTION (2U)
> +#define HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION (3U)
> +
> +/* hwd_viif_l1_rcnr_msf_blend_ratio */
> +#define HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 (0U)
> +#define HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 (1U)
> +#define HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 (2U)
> +
> +/* hwd_viif_l1_hdrs */
> +#define HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE (0U)
> +#define HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE (1U)
> +
> +/* hwd_viif_l1_lsc_para_mag */
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH (0U)
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH (1U)
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND (2U)
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST (3U)
> +
> +/* hwd_viif_l1_lsc_grid_mag */
> +#define HWD_VIIF_L1_GRID_COEF_GAIN_X1 (0U)
> +#define HWD_VIIF_L1_GRID_COEF_GAIN_X2 (1U)
> +
> +/* hwd_viif_l1_demosaic */
> +#define HWD_VIIF_L1_DEMOSAIC_ACPI (0U)
> +#define HWD_VIIF_L1_DEMOSAIC_DMG (1U)
> +
> +/* hwd_viif_l1_awb_restart_cond */
> +/* macros for L1ISP condition to restart auto white balance */
> +#define HWD_VIIF_L1_AWB_RESTART_NO (0U)
> +#define HWD_VIIF_L1_AWB_RESTART_128FRAME (1U)
> +#define HWD_VIIF_L1_AWB_RESTART_64FRAME (2U)
> +#define HWD_VIIF_L1_AWB_RESTART_32FRAME (3U)
> +#define HWD_VIIF_L1_AWB_RESTART_16FRAME (4U)
> +#define HWD_VIIF_L1_AWB_RESTART_8FRAME (5U)
> +#define HWD_VIIF_L1_AWB_RESTART_4FRAME (6U)
> +#define HWD_VIIF_L1_AWB_RESTART_2FRAME (7U)
> +
> +/* hwd_viif_l1_awb_mag */
> +#define HWD_VIIF_L1_AWB_ONE_SECOND (0U)
> +#define HWD_VIIF_L1_AWB_X1 (1U)
> +#define HWD_VIIF_L1_AWB_X2 (2U)
> +#define HWD_VIIF_L1_AWB_X4 (3U)
> +
> +/* hwd_viif_l1_awb_area_mode */
> +#define HWD_VIIF_L1_AWB_AREA_MODE0 (0U)
> +#define HWD_VIIF_L1_AWB_AREA_MODE1 (1U)
> +#define HWD_VIIF_L1_AWB_AREA_MODE2 (2U)
> +#define HWD_VIIF_L1_AWB_AREA_MODE3 (3U)
> +
> +/* hwd_viif_l1_hdrc_tone_type */
> +#define HWD_VIIF_L1_HDRC_TONE_USER (0U)
> +#define HWD_VIIF_L1_HDRC_TONE_PRESET (1U)
> +
> +/* hwd_viif_l1_bin_mode */
> +#define HWD_VIIF_L1_HIST_BIN_MODE_LINEAR (0U)
> +#define HWD_VIIF_L1_HIST_BIN_MODE_LOG (1U)
> +
> +/* hwd_viif_l2_undist_mode */
> +#define HWD_VIIF_L2_UNDIST_POLY (0U)
> +#define HWD_VIIF_L2_UNDIST_GRID (1U)
> +#define HWD_VIIF_L2_UNDIST_POLY_TO_GRID (2U)
> +#define HWD_VIIF_L2_UNDIST_GRID_TO_POLY (3U)
> +
> +/**
> + * struct hwd_viif_csi2rx_line_err_target
> + *
> + * Virtual Channel and Data Type pair for CSI2RX line error monitor
> + *
> + * When 0 is set to dt, line error detection is disabled.
> + *
> + * * VC can be 0 .. 3
> + * * DT can be 0 or 0x10 .. 0x3F
> + */
> +#define VISCONTI_CSI2_ERROR_MONITORS_NUM 8
> +struct hwd_viif_csi2rx_line_err_target {
> + u32 vc[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> + u32 dt[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_csi2rx_irq_mask
> + * @mask: mask setting for CSI2RX error interruption
> + *
> + * * mask[0]: D-PHY fatal error
> + * * mask[1]: Packet fatal error
> + * * mask[2]: Frame fatal error
> + * * mask[3]: D-PHY error
> + * * mask[4]: Packet error
> + * * mask[5]: Line error
> + */
> +#define VISCONTI_CSI2RX_IRQ_MASKS_NUM 6
> +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_FATAL 0
> +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_FATAL 1
> +#define VISCONTI_CSI2RX_IRQ_MASK_FRAME_FATAL 2
> +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_ERROR 3
> +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_ERROR 4
> +#define VISCONTI_CSI2RX_IRQ_MASK_LINE_ERROR 5
> +struct hwd_viif_csi2rx_irq_mask {
> + u32 mask[VISCONTI_CSI2RX_IRQ_MASKS_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_csi2rx_packet - CSI2 packet information
> + * @word_count: word count included in one packet[byte] [0..16384]
> + * @packet_num: the number of packet included in one packet [0..8192]
> + *
> + * each element means as below.
> + * * [0]: embedded data of MAIN unit
> + * * [1]: long packet data of MAIN unit
> + * * [2]: embedded data of SUB unit
> + * * [3]: long packet data of SUB unit
> + *
> + * Regarding word_count of long packet data,
> + * word count of odd line needs to be set in case of DT = 0x18, 0x19, 0x1C or 0x1D.
> + */
> +#define VISCONTI_CSI2RX_PACKET_TYPES_NUM 4
> +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN 0
> +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN 1
> +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB 2
> +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB 3
> +struct hwd_viif_csi2rx_packet {
> + u32 word_count[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> + u32 packet_num[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_pixelmap - pixelmap information
> + * @pmap_paddr: start address of pixel data(physical address). 4byte alignment.
> + * @pitch: pitch size of pixel map[byte]
> + *
> + * Condition of pitch in case of L2ISP output is as below.
> + * * max: 32704[byte]
> + * * min: the larger value of (active width of image * k / r) and 128[byte]
> + * * alignment: 64[byte]
> + *
> + * Condition of pitch in the other cases is as below.
> + * * max: 65536[byte]
> + * * min: active width of image * k / r[byte]
> + * * alignment: 4[byte]
> + *
> + * k is the size of 1 pixel and the value is as below.
> + * * HWD_VIIF_YCBCR422_8_PACKED: 2
> + * * HWD_VIIF_RGB888_PACKED: 3
> + * * HWD_VIIF_ARGB8888_PACKED: 4
> + * * HWD_VIIF_YCBCR422_8_PLANAR: 1
> + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR: 1
> + * * HWD_VIIF_ONE_COLOR_8: 1
> + * * HWD_VIIF_YCBCR422_16_PLANAR: 2
> + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR: 2
> + * * HWD_VIIF_ONE_COLOR_16: 2
> + *
> + * r is the correction factor for Cb or Cr of YCbCr422 planar and the value is as below.
> + * * YCbCr422 Cb-planar: 2
> + * * YCbCr422 Cr-planar: 2
> + * * others: 1
> + *
> + */
> +struct hwd_viif_pixelmap {
> + uintptr_t pmap_paddr;
> + u32 pitch;
> +};
> +
> +/**
> + * struct hwd_viif_img - image information
> + * @width: active width of image[pixel]
> + * * [128..5760](output from L2ISP)
> + * * [128..4096](input to MAIN unit(memory input))
> + * * [128..4096](output from SUB unit)
> + * * The value should be even.
> + *
> + * @height: active height of image[line]
> + * * [128..3240](output from L2ISP)
> + * * [128..2160](input to MAIN unit(memory input))
> + * * [128..2160](output from SUB unit)
> + * * The value should be even.
> + *
> + * @format: hwd_viif_color_format "color format"
> + * * Below color formats are supported for input and output of MAIN unit
> + * * HWD_VIIF_YCBCR422_8_PACKED
> + * * HWD_VIIF_RGB888_PACKED
> + * * HWD_VIIF_ARGB8888_PACKED
> + * * HWD_VIIF_YCBCR422_8_PLANAR
> + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR
> + * * HWD_VIIF_ONE_COLOR_8
> + * * HWD_VIIF_YCBCR422_16_PLANAR
> + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR
> + * * HWD_VIIF_ONE_COLOR_16
> + * * Below color formats are supported for output of SUB unit
> + * * HWD_VIIF_ONE_COLOR_8
> + * * HWD_VIIF_ONE_COLOR_16
> + *
> + * @pixelmap: pixelmap information
> + * * [0]: Y/G-planar, packed/Y/RAW
> + * * [1]: Cb/B-planar
> + * * [2]: Cr/R-planar
> + */
> +struct hwd_viif_img {
> + u32 width;
> + u32 height;
> + u32 format;
> + struct hwd_viif_pixelmap pixelmap[3];
> +};
> +
> +/**
> + * struct hwd_viif_input_img - input image information
> + * @pixel_clock: pixel clock [3375..600000] [kHz]. 0 needs to be set for long packet data.
> + * @htotal_size: horizontal total size
> + * * [143..65535] [pixel] for image data
> + * * [239..109225] [ns] for long packet data
> + * @hactive_size: horizontal active size [pixel]
> + * * [128..4096] without L1ISP
> + * * [640..3840] with L1ISP
> + * * The value should be even. In addition, the value should be a multiple of 8 with L1ISP
> + * * 0 needs to be set for the configuration of long packet data or SUB unit output.
> + * @vtotal_size: vertical total size [line]
> + * * [144..16383] for image data
> + * * 0 needs to be set for the configuration of long packet data.
> + * @vbp_size: vertical back porch size
> + * * [5..4095] [line] for image data
> + * * [5..4095] [the number of packet] for long packet data
> + * @vactive_size: vertical active size [line]
> + * * [128..2160] without L1ISP
> + * * [480..2160] with L1ISP
> + * * The value should be even.
> + * * 0 needs to be set for the configuration of long packet data.
> + * @interpolation_mode: input image interpolation mode for hwd_viif_l1_input_interpolation_mode
> + * * HWD_VIIF_L1_INPUT_INTERPOLATION_LINE needs to be set in the below cases.
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + * @input_num: the number of input images [1..3]
> + * * 1 needs to be set in the below cases.
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + * @hobc_width: the number of horizontal optical black pixels [0,16,32,64 or 128]
> + * * 0 needs to be set in the below cases.
> + * * in case of hobc_margin = 0
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + * @hobc_margin: the number of horizontal optical black margin[0..30] (even number)
> + * * 0 needs to be set in the below cases.
> + * * in case of hobc_width = 0
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + *
> + * Below conditions need to be satisfied.
> + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_LINE:
> + * (htotal_size > (hactive_size + hobc_width + hobc_margin)) &&
> + * (vtotal_size > (vbp_size + vactive_size * input_num))
> + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL:
> + * (htotal_size > ((hactive_size + hobc_width + hobc_margin) * input_num)) &&
> + * (vtotal_size > (vbp_size + vactive_size))
> + * * L1ISP is used:
> + * vbp_size >= (54720[cycle] / 500000[kHz]) * (pixel_clock / htotal_size) + 38 + ISST time
> + * * L1ISP is not used:
> + * vbp_size >= (39360[cycle] / 500000[kHz]) * (pixel_clock / htotal_size) + 16 + ISST time
> + *
> + * Note: L1ISP is used when RAW data is input to MAIN unit
> + */
> +struct hwd_viif_input_img {
> + u32 pixel_clock;
> + u32 htotal_size;
> + u32 hactive_size;
> + u32 vtotal_size;
> + u32 vbp_size;
> + u32 vactive_size;
> + u32 interpolation_mode;
> + u32 input_num;
> + u32 hobc_width;
> + u32 hobc_margin;
> +};
> +
> +/**
> + * struct hwd_viif_csc_param - color conversion information
> + * @r_cr_in_offset: input offset of R/Cr[pix value] [0x0..0x1FFFF]
> + * @g_y_in_offset: input offset of G/Y[pix value] [0x0..0x1FFFF]
> + * @b_cb_in_offset: input offset of B/Cb[pix value] [0x0..0x1FFFF]
> + * @coef: coefficient of matrix [0x0..0xFFFF]
> + * * [0] : c00(YG_YG), [1] : c01(UB_YG), [2] : c02(VR_YG),
> + * * [3] : c10(YG_UB), [4] : c11(UB_UB), [5] : c12(VR_UB),
> + * * [6] : c20(YG_VR), [7] : c21(UB_VR), [8] : c22(VR_VR)
> + * @r_cr_out_offset: output offset of R/Cr[pix value] [0x0..0x1FFFF]
> + * @g_y_out_offset: output offset of G/Y[pix value] [0x0..0x1FFFF]
> + * @b_cb_out_offset: output offset of B/Cb[pix value] [0x0..0x1FFFF]
> + */
> +struct hwd_viif_csc_param {
> + u32 r_cr_in_offset;
> + u32 g_y_in_offset;
> + u32 b_cb_in_offset;
> + u32 coef[9];
> + u32 r_cr_out_offset;
> + u32 g_y_out_offset;
> + u32 b_cb_out_offset;
> +};
> +
> +/**
> + * struct hwd_viif_img_area - image area definition
> + * @x: x position [0..8062] [pixel]
> + * @y: y position [0..3966] [line]
> + * @w: image width [128..8190] [pixel]
> + * @h: image height [128..4094] [line]
> + */
> +struct hwd_viif_img_area {
> + u32 x;
> + u32 y;
> + u32 w;
> + u32 h;
> +};
> +
> +/**
> + * struct hwd_viif_out_process - configuration of output process of MAIN unit and L2ISP
> + * @half_scale: hwd_viif_enable_flag "enable or disable half scale"
> + * @select_color: hwd_viif_output_color_mode "select output color"
> + * @alpha: alpha value used in case of ARGB8888 output [0..255]
> + */
> +struct hwd_viif_out_process {
> + u32 half_scale;
> + u32 select_color;
> + u8 alpha;
> +};
> +
> +/**
> + * struct hwd_viif_l1_lsc - HWD L1ISP lens shading correction parameters
> + * @lssc_parabola_param: parabola shading correction parameter
> + * * NULL: disable parabola shading correction
> + * * not NULL: enable parabola shading correction
> + * @lssc_grid_param: grid shading correction parameter
> + * * NULL: disable grid shading correction
> + * * not NULL: enable grid shading correction
> + * @lssc_pwhb_r_gain_max: maximum R gain of preset white balance correction
> + * @lssc_pwhb_r_gain_min: minimum R gain of preset white balance correction
> + * @lssc_pwhb_gr_gain_max: maximum Gr gain of preset white balance correction
> + * @lssc_pwhb_gr_gain_min: minimum Gr gain of preset white balance correction
> + * @lssc_pwhb_gb_gain_max: maximum Gb gain of preset white balance correction
> + * @lssc_pwhb_gb_gain_min: minimum Gb gain of preset white balance correction
> + * @lssc_pwhb_b_gain_max: maximum B gain of preset white balance correction
> + * @lssc_pwhb_b_gain_min: minimum B gain of preset white balance correction
> + *
> + * Range and accuracy of lssc_pwhb_xxx_gain_xxx are as below.
> + * - range: [0x0..0x7FF]
> + * - accuracy : 1/256
> + */
> +struct hwd_viif_l1_lsc {
> + struct viif_l1_lsc_parabola_param *lssc_parabola_param;
> + struct viif_l1_lsc_grid_param *lssc_grid_param;
> + u32 lssc_pwhb_r_gain_max;
> + u32 lssc_pwhb_r_gain_min;
> + u32 lssc_pwhb_gr_gain_max;
> + u32 lssc_pwhb_gr_gain_min;
> + u32 lssc_pwhb_gb_gain_max;
> + u32 lssc_pwhb_gb_gain_min;
> + u32 lssc_pwhb_b_gain_max;
> + u32 lssc_pwhb_b_gain_min;
> +};
> +
> +/**
> + * struct hwd_viif_l1_img_quality_adjustment - HWD L1ISP image quality adjustment parameters
> + * @coef_cb: Cb coefficient [0x0..0xffff] accuracy: 1/65536
> + * @coef_cr: Cr coefficient [0x0..0xffff] accuracy: 1/65536
> + * @brightness: brightness value [-32768..32767] (0 means off.)
> + * @linear_contrast: linear contrast value [0x0..0xff] accuracy: 1/128 (128 means off.)
> + * @*nonlinear_contrast: pointer to nonlinear contrast parameter
> + * @*lum_noise_reduction: pointer to luminance noise reduction parameter
> + * @*edge_enhancement: pointer to edge enhancement parameter
> + * @*uv_suppression: pointer to UV suppression parameter
> + * @*coring_suppression: pointer to coring suppression parameter
> + * @*edge_suppression: pointer to edge enhancement parameter
> + * @*color_level: pointer to color level adjustment parameter
> + * @color_noise_reduction_enable: enable/disable color noise reduction @ref hwd_viif_enable_flag
> + */
> +struct hwd_viif_l1_img_quality_adjustment {
> + u16 coef_cb;
> + u16 coef_cr;
> + s16 brightness;
> + u8 linear_contrast;
> + struct viif_l1_nonlinear_contrast *nonlinear_contrast;
> + struct viif_l1_lum_noise_reduction *lum_noise_reduction;
> + struct viif_l1_edge_enhancement *edge_enhancement;
> + struct viif_l1_uv_suppression *uv_suppression;
> + struct viif_l1_coring_suppression *coring_suppression;
> + struct viif_l1_edge_suppression *edge_suppression;
> + struct viif_l1_color_level *color_level;
> + u32 color_noise_reduction_enable;
> +};
> +
> +/**
> + * struct hwd_viif_l1_info - HWD L1ISP processing information
> + * @context_id: context id
> + * @ag_cont_hobc_high: analog gain for high sensitivity image of OBCC
> + * @ag_cont_hobc_middle_led: analog gain for middle sensitivity or led image of OBCC
> + * @ag_cont_hobc_low: analog gain for low sensitivity image of OBCC
> + * @ag_cont_abpc_high: analog gain for high sensitivity image of ABPC
> + * @ag_cont_abpc_middle_led: analog gain for middle sensitivity or led image of ABPC
> + * @ag_cont_abpc_low: analog gain for low sensitivity image of ABPC
> + * @ag_cont_rcnr_high: analog gain for high sensitivity image of RCNR
> + * @ag_cont_rcnr_middle_led: analog gain for middle sensitivity or led image of RCNR
> + * @ag_cont_rcnr_low: analog gain for low sensitivity image of RCNR
> + * @ag_cont_lssc: analog gain for LSSC
> + * @ag_cont_mpro: analog gain for color matrix correction
> + * @ag_cont_vpro: analog gain for image quality adjustment
> + * @dpc_defect_num_h:
> + * the number of dynamically corrected defective pixel(high sensitivity image)
> + * @dpc_defect_num_m:
> + * the number of dynamically corrected defective pixel(middle sensitivity or led image)
> + * @dpc_defect_num_l:
> + * the number of dynamically corrected defective pixel(low sensitivity image)
> + * @hdrc_tnp_fb_smth_max: the maximum value of luminance information after smoothing filter at HDRC
> + * @avg_lum_weight: weighted average luminance value at average luminance generation
> + * @avg_lum_block[8][8]:
> + * average luminance of each block [y][x]:
> + * y means vertical position and x means horizontal position.
> + * @avg_lum_four_line_lum[4]:
> + * 4-lines average luminance. avg_lum_four_line_lum[n] corresponds to aexp_ave4linesy[n]
> + * @avg_satur_pixnum: the number of saturated pixel at average luminance generation
> + * @avg_black_pixnum: the number of black pixel at average luminance generation
> + * @awb_ave_u: average U at AWHB [pixel]
> + * @awb_ave_v: average V at AWHB [pixel]
> + * @awb_accumulated_pixel: the number of accumulated pixel at AWHB
> + * @awb_gain_r: R gain applied in the next frame at AWHB
> + * @awb_gain_g: G gain applied in the next frame at AWHB
> + * @awb_gain_b: B gain applied in the next frame at AWHB
> + * @awb_status_u: status of U convergence at AWHB (true: converged, false: not converged)
> + * @awb_status_v: status of V convergence at AWHB (true: converged, false: not converged)
> + */
> +struct hwd_viif_l1_info {
> + u32 context_id;
> + u8 ag_cont_hobc_high;
> + u8 ag_cont_hobc_middle_led;
> + u8 ag_cont_hobc_low;
> + u8 ag_cont_abpc_high;
> + u8 ag_cont_abpc_middle_led;
> + u8 ag_cont_abpc_low;
> + u8 ag_cont_rcnr_high;
> + u8 ag_cont_rcnr_middle_led;
> + u8 ag_cont_rcnr_low;
> + u8 ag_cont_lssc;
> + u8 ag_cont_mpro;
> + u8 ag_cont_vpro;
> + u32 dpc_defect_num_h;
> + u32 dpc_defect_num_m;
> + u32 dpc_defect_num_l;
> + u32 hdrc_tnp_fb_smth_max;
> + u32 avg_lum_weight;
> + u32 avg_lum_block[8][8];
> + u32 avg_lum_four_line_lum[4];
> + u16 avg_satur_pixnum;
> + u16 avg_black_pixnum;
> + u32 awb_ave_u;
> + u32 awb_ave_v;
> + u32 awb_accumulated_pixel;
> + u32 awb_gain_r;
> + u32 awb_gain_g;
> + u32 awb_gain_b;
> + bool awb_status_u;
> + bool awb_status_v;
> +};
> +
> +/**
> + * struct hwd_viif_l2_gamma_table - HWD L2ISP Gamma table physical address
> + * @table[6]: table address(physical address) 4byte alignment
> + *
> + * relation between element and table is as below.
> + * * [0]: G/Y(1st table)
> + * * [1]: G/Y(2nd table)
> + * * [2]: B/U(1st table)
> + * * [3]: B/U(2nd table)
> + * * [4]: R/V(1st table)
> + * * [5]: R/V(2nd table)
> + *
> + * when 0 is set to table address, table transfer is disabled.
> + */
> +struct hwd_viif_l2_gamma_table {
> + uintptr_t table[6];
> +};
> +
> +struct hwd_viif_res;
> +
> +/* VIIF common */
> +u32 hwd_viif_csi2rx_err_irq_handler(struct hwd_viif_res *res);
> +void hwd_viif_status_err_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub);
> +void hwd_viif_vsync_irq_handler(struct hwd_viif_res *res, u32 *event_main, u32 *event_sub);
> +void hwd_viif_isp_regbuf_irq_handler(struct hwd_viif_res *res, u32 *event_l1, u32 *event_l2);
> +
> +/* control MAIN unit */
> +s32 hwd_viif_main_set_unit(struct hwd_viif_res *res, u32 dt_image,
> + const struct hwd_viif_input_img *in_img, u32 color_type, u32 rawpack,
> + u32 yuv_conv);
> +s32 hwd_viif_main_mask_vlatch(struct hwd_viif_res *res, u32 enable);
> +void hwd_viif_main_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> +void hwd_viif_main_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> +
> +/* conrol SUB unit */
> +s32 hwd_viif_sub_set_unit(struct hwd_viif_res *res, u32 dt_image,
> + const struct hwd_viif_input_img *in_img);
> +s32 hwd_viif_sub_set_img_transmission(struct hwd_viif_res *res, const struct hwd_viif_img *img);
> +void hwd_viif_sub_status_err_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> +void hwd_viif_sub_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> +
> +/* control MIPI CSI2 Receiver unit */
> +s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32 lane_assign,
> + u32 dphy_rate, u32 rext_calibration,
> + const struct hwd_viif_csi2rx_line_err_target *err_target,
> + const struct hwd_viif_csi2rx_irq_mask *mask);
> +s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res);
> +s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
> + const struct hwd_viif_csi2rx_packet *packet);
> +s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res);
> +s32 hwd_viif_csi2rx_get_calibration_status(
> + struct hwd_viif_res *res, struct viif_csi2rx_dphy_calibration_status *calibration_status);
> +s32 hwd_viif_csi2rx_get_err_status(struct hwd_viif_res *res, u32 *err_phy_fatal, u32 *err_pkt_fatal,
> + u32 *err_frame_fatal, u32 *err_phy, u32 *err_pkt, u32 *err_line);
> +
> +/* control L1 Image Signal Processor */
> +void hwd_viif_isp_set_regbuf_auto_transmission(struct hwd_viif_res *res);
> +void hwd_viif_isp_disable_regbuf_auto_transmission(struct hwd_viif_res *res);
> +void hwd_viif_isp_get_info(struct hwd_viif_res *res, struct hwd_viif_l1_info *l1_info,
> + u32 *l2_transfer_status);
> +void hwd_viif_isp_set_regbuf_irq_mask(struct hwd_viif_res *res, const u32 *mask_l1,
> + const u32 *mask_l2);
> +
> +s32 hwd_viif_l1_set_input_mode(struct hwd_viif_res *res, u32 mode, u32 depth, u32 raw_color_filter);
> +s32 hwd_viif_l1_set_rgb_to_y_coef(struct hwd_viif_res *res, u16 coef_r, u16 coef_g, u16 coef_b);
> +s32 hwd_viif_l1_set_ag_mode(struct hwd_viif_res *res, const struct viif_l1_ag_mode_config *param);
> +s32 hwd_viif_l1_set_ag(struct hwd_viif_res *res, u16 gain_h, u16 gain_m, u16 gain_l);
> +s32 hwd_viif_l1_set_hdre(struct hwd_viif_res *res, const struct viif_l1_hdre_config *param);
> +s32 hwd_viif_l1_set_img_extraction(struct hwd_viif_res *res, u32 input_black_gr, u32 input_black_r,
> + u32 input_black_b, u32 input_black_gb);
> +s32 hwd_viif_l1_set_dpc(struct hwd_viif_res *res, const struct viif_l1_dpc *param_h,
> + const struct viif_l1_dpc *param_m, const struct viif_l1_dpc *param_l);
> +s32 hwd_viif_l1_set_dpc_table_transmission(struct hwd_viif_res *res, uintptr_t table_h,
> + uintptr_t table_m, uintptr_t table_l);
> +s32 hwd_viif_l1_set_preset_white_balance(struct hwd_viif_res *res, u32 dstmaxval,
> + const struct viif_l1_preset_wb *param_h,
> + const struct viif_l1_preset_wb *param_m,
> + const struct viif_l1_preset_wb *param_l);
> +s32 hwd_viif_l1_set_raw_color_noise_reduction(
> + struct hwd_viif_res *res, const struct viif_l1_raw_color_noise_reduction *param_h,
> + const struct viif_l1_raw_color_noise_reduction *param_m,
> + const struct viif_l1_raw_color_noise_reduction *param_l);
> +s32 hwd_viif_l1_set_hdrs(struct hwd_viif_res *res, const struct viif_l1_hdrs_config *param);
> +s32 hwd_viif_l1_set_black_level_correction(
> + struct hwd_viif_res *res, const struct viif_l1_black_level_correction_config *param);
> +s32 hwd_viif_l1_set_lsc(struct hwd_viif_res *res, const struct hwd_viif_l1_lsc *param);
> +s32 hwd_viif_l1_set_lsc_table_transmission(struct hwd_viif_res *res, uintptr_t table_gr,
> + uintptr_t table_r, uintptr_t table_b,
> + uintptr_t table_gb);
> +s32 hwd_viif_l1_set_main_process(struct hwd_viif_res *res, u32 demosaic_mode, u32 damp_lsbsel,
> + const struct viif_l1_color_matrix_correction *color_matrix,
> + u32 dst_maxval);
> +s32 hwd_viif_l1_set_awb(struct hwd_viif_res *res, const struct viif_l1_awb *param, u32 awhb_wbmrg,
> + u32 awhb_wbmgg, u32 awhb_wbmbg);
> +s32 hwd_viif_l1_lock_awb_gain(struct hwd_viif_res *res, u32 enable);
> +s32 hwd_viif_l1_set_hdrc(struct hwd_viif_res *res, const struct viif_l1_hdrc *param,
> + u32 hdrc_thr_sft_amt);
> +s32 hwd_viif_l1_set_hdrc_ltm(struct hwd_viif_res *res, const struct viif_l1_hdrc_ltm_config *param);
> +s32 hwd_viif_l1_set_gamma(struct hwd_viif_res *res, const struct viif_l1_gamma *param);
> +s32 hwd_viif_l1_set_img_quality_adjustment(struct hwd_viif_res *res,
> + const struct hwd_viif_l1_img_quality_adjustment *param);
> +s32 hwd_viif_l1_set_avg_lum_generation(struct hwd_viif_res *res,
> + const struct viif_l1_avg_lum_generation_config *param);
> +void hwd_viif_l1_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> +
> +/* control L2 Image Signal Processor */
> +s32 hwd_viif_l2_set_input_csc(struct hwd_viif_res *res, const struct hwd_viif_csc_param *param,
> + bool is_l1_rgb);
> +s32 hwd_viif_l2_set_undist(struct hwd_viif_res *res, const struct viif_l2_undist *param);
> +s32 hwd_viif_l2_set_undist_table_transmission(struct hwd_viif_res *res, uintptr_t write_g,
> + uintptr_t read_b, uintptr_t read_g, uintptr_t read_r,
> + u32 size);
> +s32 hwd_viif_l2_set_roi(struct hwd_viif_res *res, const struct viif_l2_roi_config *param);
> +s32 hwd_viif_l2_set_gamma(struct hwd_viif_res *res, u32 post_id, u32 enable, u32 vsplit, u32 mode);
> +s32 hwd_viif_l2_set_gamma_table_transmission(struct hwd_viif_res *res, u32 post_id,
> + const struct hwd_viif_l2_gamma_table *gamma_table);
> +s32 hwd_viif_l2_set_output_csc(struct hwd_viif_res *res, u32 post_id,
> + const struct hwd_viif_csc_param *param);
> +s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id, u32 enable,
> + const struct hwd_viif_img_area *src,
> + const struct hwd_viif_out_process *out_process,
> + const struct hwd_viif_img *img);
> +void hwd_viif_l2_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> +
> +void hwd_viif_isp_guard_start(struct hwd_viif_res *res);
> +void hwd_viif_isp_guard_end(struct hwd_viif_res *res);
> +
> +struct hwd_viif_res *allocate_viif_res(struct device *dev, void *csi2host_vaddr,
> + void *capture_vaddr);
> +
> +#endif /* HWD_VIIF_H */
> diff --git a/drivers/media/platform/visconti/hwd_viif_csi2rx.c b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> new file mode 100644
> index 00000000000..f49869c5bdd
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> @@ -0,0 +1,610 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/timekeeping.h>
> +#include "hwd_viif.h"
> +#include "hwd_viif_internal.h"
> +
> +#define CSI2_DT_YUV4208 0x18
> +#define CSI2_DT_YUV42010 0x19
> +#define CSI2_DT_YUV4208L 0x1A
> +#define CSI2_DT_YUV4208C 0x1C
> +#define CSI2_DT_YUV42010C 0x1D
> +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> +#define CSI2_DT_RGB444 0x20
> +#define CSI2_DT_RGB555 0x21
> +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> +#define CSI2_DT_RGB666 0x23
> +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
Same here.
> +
> +#define TESTCTRL0_PHY_TESTCLK_1 0x2
> +#define TESTCTRL0_PHY_TESTCLK_0 0x0
> +#define TESTCTRL1_PHY_TESTEN 0x10000
> +#define TESTCTRL1_PHY_TESTDOUT_SHIFT 8U
> +
> +/**
> + * write_dphy_param() - Write CSI2RX DPHY params
> + *
> + * @test_mode: test code address
> + * @test_in: test code data
> + * Return: None
> + */
> +static void write_dphy_param(u32 test_mode, u8 test_in, struct hwd_viif_res *res)
> +{
> + /* select MSB address register */
> + writel(TESTCTRL1_PHY_TESTEN, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* set MSB address of test_mode */
> + writel(FIELD_GET(0xF00, test_mode), &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* select and set LSB address register */
> + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* set the test code data */
> + writel((u32)test_in, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +}
> +
> +/**
> + * read_dphy_param() - Read CSI2RX DPHY params
> + *
> + * @test_mode: test code address
> + * Return: test code data
> + */
> +static u8 read_dphy_param(u32 test_mode, struct hwd_viif_res *res)
> +{
> + u32 read_data;
> +
> + /* select MSB address register */
> + writel(TESTCTRL1_PHY_TESTEN, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* set MSB address of test_mode */
> + writel(FIELD_GET(0xF00, test_mode), &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* select and set LSB address register */
> + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* read the test code data */
> + read_data = readl(&res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> + return (u8)(read_data >> TESTCTRL1_PHY_TESTDOUT_SHIFT);
> +}
> +
> +/**
> + * enum dphy_testcode - DPHY registers via the local communication path
> + */
> +enum dphy_testcode {
> + DIG_RDWR_RX_SYS_0 = 0x001,
> + DIG_RDWR_RX_SYS_1 = 0x002,
> + DIG_RDWR_RX_SYS_3 = 0x004,
> + DIG_RDWR_RX_SYS_7 = 0x008,
> + DIG_RDWR_RX_RX_STARTUP_OVR_2 = 0x0E2,
> + DIG_RDWR_RX_RX_STARTUP_OVR_3 = 0x0E3,
> + DIG_RDWR_RX_RX_STARTUP_OVR_4 = 0x0E4,
> + DIG_RDWR_RX_RX_STARTUP_OVR_5 = 0x0E5,
> + DIG_RDWR_RX_CB_2 = 0x1AC,
> + DIG_RD_RX_TERM_CAL_0 = 0x220,
> + DIG_RD_RX_TERM_CAL_1 = 0x221,
> + DIG_RD_RX_TERM_CAL_2 = 0x222,
> + DIG_RDWR_RX_CLKLANE_LANE_6 = 0x307,
> + DIG_RD_RX_CLKLANE_OFFSET_CAL_0 = 0x39D,
> + DIG_RD_RX_LANE0_OFFSET_CAL_0 = 0x59F,
> + DIG_RD_RX_LANE0_DDL_0 = 0x5E0,
> + DIG_RD_RX_LANE1_OFFSET_CAL_0 = 0x79F,
> + DIG_RD_RX_LANE1_DDL_0 = 0x7E0,
> + DIG_RD_RX_LANE2_OFFSET_CAL_0 = 0x99F,
> + DIG_RD_RX_LANE2_DDL_0 = 0x9E0,
> + DIG_RD_RX_LANE3_OFFSET_CAL_0 = 0xB9F,
> + DIG_RD_RX_LANE3_DDL_0 = 0xBE0,
> +};
> +
> +#define SYS_0_HSFREQRANGE_OVR BIT(5)
> +#define SYS_7_RESERVED FIELD_PREP(0x1F, 0x0C)
> +#define SYS_7_DESKEW_POL BIT(5)
> +#define STARTUP_OVR_4_CNTVAL FIELD_PREP(0x70, 0x01)
> +#define STARTUP_OVR_4_DDL_EN BIT(0)
> +#define STARTUP_OVR_5_BYPASS BIT(0)
> +#define CB_2_LPRX_BIAS BIT(6)
> +#define CB_2_RESERVED FIELD_PREP(0x3F, 0x0B)
> +#define CLKLANE_RXHS_PULL_LONG BIT(7)
> +
> +static const struct hwd_viif_dphy_hs_info dphy_hs_info[] = {
> + { 80, 0x0, 0x1cc }, { 85, 0x10, 0x1cc }, { 95, 0x20, 0x1cc }, { 105, 0x30, 0x1cc },
> + { 115, 0x1, 0x1cc }, { 125, 0x11, 0x1cc }, { 135, 0x21, 0x1cc }, { 145, 0x31, 0x1cc },
> + { 155, 0x2, 0x1cc }, { 165, 0x12, 0x1cc }, { 175, 0x22, 0x1cc }, { 185, 0x32, 0x1cc },
> + { 198, 0x3, 0x1cc }, { 213, 0x13, 0x1cc }, { 228, 0x23, 0x1cc }, { 243, 0x33, 0x1cc },
> + { 263, 0x4, 0x1cc }, { 288, 0x14, 0x1cc }, { 313, 0x25, 0x1cc }, { 338, 0x35, 0x1cc },
> + { 375, 0x5, 0x1cc }, { 425, 0x16, 0x1cc }, { 475, 0x26, 0x1cc }, { 525, 0x37, 0x1cc },
> + { 575, 0x7, 0x1cc }, { 625, 0x18, 0x1cc }, { 675, 0x28, 0x1cc }, { 725, 0x39, 0x1cc },
> + { 775, 0x9, 0x1cc }, { 825, 0x19, 0x1cc }, { 875, 0x29, 0x1cc }, { 925, 0x3a, 0x1cc },
> + { 975, 0xa, 0x1cc }, { 1025, 0x1a, 0x1cc }, { 1075, 0x2a, 0x1cc }, { 1125, 0x3b, 0x1cc },
> + { 1175, 0xb, 0x1cc }, { 1225, 0x1b, 0x1cc }, { 1275, 0x2b, 0x1cc }, { 1325, 0x3c, 0x1cc },
> + { 1375, 0xc, 0x1cc }, { 1425, 0x1c, 0x1cc }, { 1475, 0x2c, 0x1cc }
> +};
> +
> +/**
> + * get_dphy_hs_transfer_info() - Get DPHY HS info from table
> + *
> + * @dphy_rate: DPHY clock in MHz
> + * @hsfreqrange: HS Frequency Range
> + * @osc_freq_target: OSC Frequency Target
> + * Return: None
> + */
> +static void get_dphy_hs_transfer_info(u32 dphy_rate, u32 *hsfreqrange, u32 *osc_freq_target,
> + struct hwd_viif_res *res)
> +{
> + int table_size = ARRAY_SIZE(dphy_hs_info);
No need for a local variable.
> + int i;
unsigned int
> +
> + for (i = 1; i < table_size; i++) {
> + if (dphy_rate < dphy_hs_info[i].rate) {
> + *hsfreqrange = dphy_hs_info[i - 1].hsfreqrange;
> + *osc_freq_target = dphy_hs_info[i - 1].osc_freq_target;
> + return;
> + }
> + }
> +
> + /* not found; return the largest entry */
> + *hsfreqrange = dphy_hs_info[table_size - 1].hsfreqrange;
> + *osc_freq_target = dphy_hs_info[table_size - 1].osc_freq_target;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_set_dphy_rate() - Set D-PHY rate
> + *
> + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> + * Return: None
> + */
> +static void hwd_viif_csi2rx_set_dphy_rate(u32 dphy_rate, struct hwd_viif_res *res)
> +{
> + u32 hsfreqrange, osc_freq_target;
> +
> + get_dphy_hs_transfer_info(dphy_rate, &hsfreqrange, &osc_freq_target, res);
> +
> + write_dphy_param(DIG_RDWR_RX_SYS_1, (u8)hsfreqrange, res);
> + write_dphy_param(DIG_RDWR_RX_SYS_0, SYS_0_HSFREQRANGE_OVR, res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_5, STARTUP_OVR_5_BYPASS, res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4, STARTUP_OVR_4_CNTVAL, res);
> + write_dphy_param(DIG_RDWR_RX_CB_2, CB_2_LPRX_BIAS | CB_2_RESERVED, res);
> + write_dphy_param(DIG_RDWR_RX_SYS_7, SYS_7_DESKEW_POL | SYS_7_RESERVED, res);
> + write_dphy_param(DIG_RDWR_RX_CLKLANE_LANE_6, CLKLANE_RXHS_PULL_LONG, res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_2, FIELD_GET(0xff, osc_freq_target), res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_3, FIELD_GET(0xf00, osc_freq_target), res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4, STARTUP_OVR_4_CNTVAL | STARTUP_OVR_4_DDL_EN,
> + res);
> +
> + writel(HWD_VIIF_DPHY_CFG_CLK_25M, &res->capture_reg->sys.DPHY_FREQRANGE);
> +}
> +
> +/**
> + * check_dphy_calibration_status() - Check D-PHY calibration status
> + *
> + * @test_mode: test code related to calibration information
> + * @shift_val_err: shift value related to error information
> + * @shift_val_done: shift value related to done information
> + * Return: HWD_VIIF_CSI2_CAL_NOT_DONE calibration is not done(out of target or not completed)
> + * Return: HWD_VIIF_CSI2_CAL_FAIL calibration was failed
> + * Return: HWD_VIIF_CSI2_CAL_SUCCESS calibration was succeeded
> + */
> +static u32 check_dphy_calibration_status(u32 test_mode, u32 shift_val_err, u32 shift_val_done,
> + struct hwd_viif_res *res)
> +{
> + u32 read_data = (u32)read_dphy_param(test_mode, res);
> +
> + if (!(read_data & BIT(shift_val_done)))
> + return HWD_VIIF_CSI2_CAL_NOT_DONE;
> +
> + /* error check is not required for termination calibration with REXT(0x221) */
> + if (test_mode == DIG_RD_RX_TERM_CAL_1)
> + return HWD_VIIF_CSI2_CAL_SUCCESS;
> +
> + /* done with error */
> + if (read_data & BIT(shift_val_err))
> + return HWD_VIIF_CSI2_CAL_FAIL;
> +
> + return HWD_VIIF_CSI2_CAL_SUCCESS;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_initialize() - Initialize CSI-2 RX driver
> + *
> + * @num_lane: [1..4](VIIF CH0-CH1)
> + * @lane_assign: lane connection. For more refer @ref hwd_viif_dphy_lane_assignment
> + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> + * @rext_calibration: enable or disable rext calibration.
> + * For more refer @ref hwd_viif_csi2rx_cal_status
> + * @err_target: Pointer to configuration for Line error detection.
> + * @mask: MASK of CSI-2 RX error interruption
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "num_lane", "lane_assign", "dphy_rate", "rext_calibration" or "input_mode" is out of range
> + * - [2] "err_target" is NULL
> + * - [3] member of "err_target" is invalid
> + */
> +s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32 lane_assign,
> + u32 dphy_rate, u32 rext_calibration,
> + const struct hwd_viif_csi2rx_line_err_target *err_target,
> + const struct hwd_viif_csi2rx_irq_mask *mask)
> +{
> + u32 i, val;
> +
> + if (num_lane == 0U || num_lane > 4U || lane_assign > HWD_VIIF_CSI2_DPHY_L0L2L1L3)
> + return -EINVAL;
> +
> + if (dphy_rate < HWD_VIIF_DPHY_MIN_DATA_RATE || dphy_rate > HWD_VIIF_DPHY_MAX_DATA_RATE ||
> + (rext_calibration != HWD_VIIF_ENABLE && rext_calibration != HWD_VIIF_DISABLE) ||
> + !err_target) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < 8U; i++) {
> + if (err_target->vc[i] > HWD_VIIF_CSI2_MAX_VC ||
> + err_target->dt[i] > HWD_VIIF_CSI2_MAX_DT ||
> + (err_target->dt[i] < HWD_VIIF_CSI2_MIN_DT && err_target->dt[i] != 0U)) {
> + return -EINVAL;
> + }
> + }
> +
> + /* 1st phase of initialization */
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_RESETN);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + ndelay(15U);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* Configure D-PHY frequency range */
> + hwd_viif_csi2rx_set_dphy_rate(dphy_rate, res);
> +
> + /* 2nd phase of initialization */
> + writel((num_lane - 1U), &res->csi2host_reg->CSI2RX_NLANES);
> + ndelay(5U);
> +
> + /* configuration not to use rext */
> + if (rext_calibration == HWD_VIIF_DISABLE) {
> + write_dphy_param(0x004, 0x10, res);
> + ndelay(5U);
> + }
> +
> + /* Release D-PHY from Reset */
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> + ndelay(5U);
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> +
> + /* configuration of line error target */
> + val = (err_target->vc[3] << 30U) | (err_target->dt[3] << 24U) | (err_target->vc[2] << 22U) |
> + (err_target->dt[2] << 16U) | (err_target->vc[1] << 14U) | (err_target->dt[1] << 8U) |
> + (err_target->vc[0] << 6U) | (err_target->dt[0]);
> + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_1);
> + val = (err_target->vc[7] << 30U) | (err_target->dt[7] << 24U) | (err_target->vc[6] << 22U) |
> + (err_target->dt[6] << 16U) | (err_target->vc[5] << 14U) | (err_target->dt[5] << 8U) |
> + (err_target->vc[4] << 6U) | (err_target->dt[4]);
> + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_2);
> +
> + /* configuration of mask */
> + writel(mask->mask[0], &res->csi2host_reg->CSI2RX_INT_MSK_PHY_FATAL);
> + writel(mask->mask[1], &res->csi2host_reg->CSI2RX_INT_MSK_PKT_FATAL);
> + writel(mask->mask[2], &res->csi2host_reg->CSI2RX_INT_MSK_FRAME_FATAL);
> + writel(mask->mask[3], &res->csi2host_reg->CSI2RX_INT_MSK_PHY);
> + writel(mask->mask[4], &res->csi2host_reg->CSI2RX_INT_MSK_PKT);
> + writel(mask->mask[5], &res->csi2host_reg->CSI2RX_INT_MSK_LINE);
> +
> + /* configuration of lane assignment */
> + writel(lane_assign, &res->capture_reg->sys.DPHY_LANE);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_uninitialize() - Uninitialize CSI-2 RX driver
> + *
> + * Return: 0 Operation completes successfully
> + */
> +s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res)
> +{
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_RESETN);
> +
> + return 0;
> +}
> +
> +#define PORT_SEL_MAIN_LONG 0
> +#define PORT_SEL_MAIN_EMBED 1
> +#define PORT_SEL_SUB_LONG 4
> +#define PORT_SEL_SUB_EMBED 5
> +
> +static void config_vdm_wport(struct hwd_viif_res *res, int port_sel, u32 height, u32 pitch)
> +{
> + struct hwd_viif_vdm_write_port_reg *wport;
> + u32 start_addr, end_addr;
> +
> + wport = &res->capture_reg->vdm.w_port[port_sel];
> +
> + writel(pitch, &wport->VDM_W_PITCH);
> + writel(height, &wport->VDM_W_HEIGHT);
> + start_addr = readl(&wport->VDM_W_STADR);
> + end_addr = start_addr + pitch - 1U;
> + writel(end_addr, &wport->VDM_W_ENDADR);
> +}
> +
> +/**
> + * hwd_viif_csi2rx_start() - Start CSI-2 input
> + *
> + * @vc_main: control CSI-2 input of MAIN unit.
> + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> + * @vc_sub: control CSI-2 input of SUB unit.
> + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> + * @packet: Pointer to packet information of embedded data and long packet data
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * HWD_VIIF_CSI2_NOT_CAPTURE
> + * HWD_VIIF_CSI2_NOT_CAPTURE
> + * - [1] "vc_main" or "vc_sub" is out of range
> + * - [2] member of "packet" is invalid
> + */
> +s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
> + const struct hwd_viif_csi2rx_packet *packet)
> +{
> + u32 val, i, pitch, height, dt;
> + u32 enable_vc0 = HWD_VIIF_DISABLE;
> + u32 enable_vc1 = HWD_VIIF_DISABLE;
> +
> + if (vc_main > 3 || vc_main < HWD_VIIF_CSI2_NOT_CAPTURE || vc_sub > 3 ||
> + vc_sub < HWD_VIIF_CSI2_NOT_CAPTURE) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < VISCONTI_CSI2RX_PACKET_TYPES_NUM; i++) {
> + if (packet->word_count[i] > HWD_VIIF_CSI2_MAX_WORD_COUNT ||
> + packet->packet_num[i] > HWD_VIIF_CSI2_MAX_PACKET_NUM) {
> + return -EINVAL;
> + }
> + }
> +
> + writel(HWD_VIIF_INPUT_CSI2, &res->capture_reg->sys.IPORTM);
> +
> + if (vc_main != HWD_VIIF_CSI2_NOT_CAPTURE) {
> + writel((u32)vc_main, &res->capture_reg->sys.VCID0SELECT);
> + enable_vc0 = HWD_VIIF_ENABLE;
> + }
> + if (vc_sub != HWD_VIIF_CSI2_NOT_CAPTURE) {
> + writel((u32)vc_sub, &res->capture_reg->sys.VCID1SELECT);
> + enable_vc1 = HWD_VIIF_ENABLE;
> + }
> +
> + /* configure Embedded Data transfer of MAIN unit */
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN];
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN], 4);
> + config_vdm_wport(res, PORT_SEL_MAIN_EMBED, height, pitch);
> +
> + /* configure Long Packet transfer of MAIN unit */
> + dt = readl(&res->capture_reg->sys.IPORTM_OTHER);
> + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208C ||
> + dt == CSI2_DT_YUV42010C) {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN], 4) +
> + ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] * 2U, 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] >> 1U;
> + } else {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN], 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN];
> + }
> + config_vdm_wport(res, PORT_SEL_MAIN_LONG, height, pitch);
> +
> + /* configure Embedded Data transfer of SUB unit */
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB];
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB], 4);
> + config_vdm_wport(res, PORT_SEL_SUB_EMBED, height, pitch);
> +
> + /* configure Long Packet transfer of SUB unit */
> + dt = readl(&res->capture_reg->sys.IPORTS_OTHER);
> + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV42010 || dt == CSI2_DT_YUV4208C ||
> + dt == CSI2_DT_YUV42010C) {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB], 4) +
> + ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] * 2U, 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] >> 1U;
> + } else {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB], 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB];
> + }
> + config_vdm_wport(res, PORT_SEL_SUB_LONG, height, pitch);
> +
> + /* Control VC port enable */
> + val = enable_vc0 | (enable_vc1 << 4U);
> + writel(val, &res->capture_reg->sys.VCPORTEN);
> +
> + if (enable_vc0 == HWD_VIIF_ENABLE) {
> + /* Update flag information for run status of MAIN unit */
> + res->run_flag_main = true;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_stop() - Stop CSI-2 input
> + *
> + * Return: 0 Operation completes successfully
> + * Return: -ETIMEDOUT Driver timeout error
> + */
> +s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res)
> +{
> + u32 status_r, status_w, status_t, l2_status;
> + u64 timeout_ns, cur_ns;
> + bool run_flag = true;
> + s32 ret = 0;
int, please. The same for return type.
This applies to the rest of the patch. Use s32 if you're e.g. dealing with
hardware registers with a sign bit.
> +
> + /* Disable auto transmission of register buffer */
> + writel(0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> + writel(0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> +
> + /* Wait for completion of register buffer transmission */
> + udelay(HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME);
> +
> + /* Stop all VCs, long packet input and emb data input of MAIN unit */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.VCPORTEN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTM_OTHEREN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTM_EMBEN);
> +
> + /* Stop image data input, long packet input and emb data input of SUB unit */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_OTHEREN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_EMBEN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> +
> + /* Stop VDMAC for all table ports, input ports and write ports */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_T_ENABLE);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_R_ENABLE);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_W_ENABLE);
> +
> + /* Stop all groups(g00, g01 and g02) of VDMAC */
> + writel(0x7, &res->capture_reg->vdm.VDM_ABORTSET);
> +
> + timeout_ns = ktime_get_ns() + HWD_VIIF_WAIT_ABORT_COMPLETE_TIME * 1000;
Wouldn't it be better to calculate how long you expect to busy loop here?
> +
> + do {
> + /* Get VDMAC transfer status */
> + status_r = readl(&res->capture_reg->vdm.VDM_R_RUN);
> + status_w = readl(&res->capture_reg->vdm.VDM_W_RUN);
> + status_t = readl(&res->capture_reg->vdm.VDM_T_RUN);
> +
> + l2_status = readl(&res->capture_reg->l2isp.L2_BUS_L2_STATUS);
> +
> + if (status_r == 0U && status_w == 0U && status_t == 0U && l2_status == 0U)
> + run_flag = false;
> +
> + cur_ns = ktime_get_ns();
> +
> + if (cur_ns > timeout_ns) {
> + ret = -ETIMEDOUT;
> + run_flag = false;
> + }
> + } while (run_flag);
> +
> + if (ret == 0) {
> + /* Clear run flag of MAIN unit */
> + res->run_flag_main = false;
> + }
> +
> + return ret;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_get_calibration_status() - Get CSI-2 RX calibration status
> + *
> + * @calibration_status: Pointer to D-PHY calibration status information
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "calibration_status" is NULL
> + */
> +s32 hwd_viif_csi2rx_get_calibration_status(
> + struct hwd_viif_res *res, struct viif_csi2rx_dphy_calibration_status *calibration_status)
> +{
> + if (!calibration_status)
> + return -EINVAL;
> +
> + /* arg0; test register, arg1: error bit, arg2: done bit */
> + /* 0x221: termination calibration with REXT */
> + calibration_status->term_cal_with_rext =
> + check_dphy_calibration_status(DIG_RD_RX_TERM_CAL_1, 0, 7, res);
> + /* 0x39D: clock lane offset calibration */
> + calibration_status->clock_lane_offset_cal =
> + check_dphy_calibration_status(DIG_RD_RX_CLKLANE_OFFSET_CAL_0, 4, 0, res);
> + /* 0x59F: data lane0 offset calibration */
> + calibration_status->data_lane0_offset_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE0_OFFSET_CAL_0, 2, 1, res);
> + /* 0x79F: data lane1 offset calibration */
> + calibration_status->data_lane1_offset_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE1_OFFSET_CAL_0, 2, 1, res);
> + /* 0x99F: data lane2 offset calibration */
> + calibration_status->data_lane2_offset_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE2_OFFSET_CAL_0, 2, 1, res);
> + /* 0xB9F: data lane3 offset calibration */
> + calibration_status->data_lane3_offset_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE3_OFFSET_CAL_0, 2, 1, res);
> +
> + /* 0x5E0: data lane0 DDL(Digital Delay Line) calibration */
> + calibration_status->data_lane0_ddl_tuning_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE0_DDL_0, 1, 2, res);
> + /* 0x7E0: data lane1 DDL calibration */
> + calibration_status->data_lane1_ddl_tuning_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE1_DDL_0, 1, 2, res);
> + /* 0x9E0: data lane2 DDL calibration */
> + calibration_status->data_lane2_ddl_tuning_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE2_DDL_0, 1, 2, res);
> + /* 0xBE0: data lane3 DDL calibration */
> + calibration_status->data_lane3_ddl_tuning_cal =
> + check_dphy_calibration_status(DIG_RD_RX_LANE3_DDL_0, 1, 2, res);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_get_err_status() - Get CSI-2 RX error status
> + *
> + * @err_phy_fatal: Pointer to D-PHY fatal error information
> + * @err_pkt_fatal: Pointer to Packet fatal error information
> + * @err_frame_fatal: Pointer to Frame fatal error information
> + * @err_phy: Pointer to D-PHY error information
> + * @err_pkt: Pointer to Packet error information
> + * @err_line: Pointer to Line error information
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error,
> + * when "err_phy_fatal", "err_pkt_fatal", "err_frame_fatal",
> + * "err_phy", "err_pkt" or "err_line" is NULL
> + */
> +s32 hwd_viif_csi2rx_get_err_status(struct hwd_viif_res *res, u32 *err_phy_fatal, u32 *err_pkt_fatal,
> + u32 *err_frame_fatal, u32 *err_phy, u32 *err_pkt, u32 *err_line)
> +{
> + if (!err_phy_fatal || !err_pkt_fatal || !err_frame_fatal || !err_phy || !err_pkt ||
> + !err_line) {
> + return -EINVAL;
> + }
> + *err_phy_fatal = readl(&res->csi2host_reg->CSI2RX_INT_ST_PHY_FATAL);
> + *err_pkt_fatal = readl(&res->csi2host_reg->CSI2RX_INT_ST_PKT_FATAL);
> + *err_frame_fatal = readl(&res->csi2host_reg->CSI2RX_INT_ST_FRAME_FATAL);
> + *err_phy = readl(&res->csi2host_reg->CSI2RX_INT_ST_PHY);
> + *err_pkt = readl(&res->csi2host_reg->CSI2RX_INT_ST_PKT);
> + *err_line = readl(&res->csi2host_reg->CSI2RX_INT_ST_LINE);
> +
> + return 0;
> +}
> diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h b/drivers/media/platform/visconti/hwd_viif_internal.h
> new file mode 100644
> index 00000000000..c954e804946
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_internal.h
> @@ -0,0 +1,340 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_INTERNAL_H
> +#define HWD_VIIF_INTERNAL_H
> +
> +#include "hwd_viif_reg.h"
> +
> +#define HWD_VIIF_CSI2_MAX_VC (3U)
> +#define HWD_VIIF_CSI2_MIN_DT (0x10U)
> +#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
> +#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
> +#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
> +#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
> +#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
> +#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
> +#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
> +
> +/* maximum horizontal/vertical position/dimension of CROP with ISP */
> +#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
> +#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
> +#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
> +#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
> +
> +/* maximum horizontal/vertical position/dimension of CROP without ISP */
> +#define HWD_VIIF_CROP_MAX_X (1920U)
> +#define HWD_VIIF_CROP_MAX_Y (1408U)
> +#define HWD_VIIF_CROP_MIN_W (128U)
> +#define HWD_VIIF_CROP_MAX_W (2048U)
> +#define HWD_VIIF_CROP_MIN_H (128U)
> +#define HWD_VIIF_CROP_MAX_H (1536U)
> +
> +/* pixel clock: [kHz] */
> +#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
> +#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
> +
> +/* picture size: [pixel], [ns] */
> +#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
> +#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
> +#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
> +#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
> +
> +/* horizontal back porch size: [system clock] */
> +#define HWD_VIIF_HBP_SYSCLK (10U)
> +
> +/* active picture size: [pixel] */
> +#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
> +#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
> +#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
> +#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
> +
> +/* picture vertical size: [line], [packet] */
> +#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
> +#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
> +#define HWD_VIIF_MIN_VBP_LINE (5U)
> +#define HWD_VIIF_MAX_VBP_LINE (4095U)
> +#define HWD_VIIF_MIN_VBP_PACKET (5U)
> +#define HWD_VIIF_MAX_VBP_PACKET (4095U)
> +#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
> +#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
> +#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
> +#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
> +
> +/* image source select */
> +#define HWD_VIIF_INPUT_CSI2 (0U)
> +
> +#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
> +#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
> +#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
> +#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
> +#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
> +#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
> +#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
> +#define HWD_VIIF_MAX_PITCH_ISP (32704U)
> +#define HWD_VIIF_MAX_PITCH (65536U)
> +
> +/* size of minimum/maximum input image */
> +#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
> +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
> +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
> +#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
> +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
> +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
> +#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
> +
> +/* size of minimum/maximum output image */
> +#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> +
> +#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> +
> +#define HWD_VIIF_NO_EVENT (0x0U)
> +
> +/* System clock: [kHz] */
> +#define HWD_VIIF_SYS_CLK (500000UL)
> +
> +/*
> + * wait time for force abort to complete(max 1line time = 1228.8[us]
> + * when width = 4096, RAW24, 80Mbps
> + */
> +#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
> +
> +/*
> + * complete time of register buffer transfer.
> + * actual time is about 30us in case of L1ISP
> + */
> +#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
> +
> +/* internal operation latencies: [system clock]*/
> +#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
> +#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
> +
> +/* offset of Vsync delay: [line] */
> +#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
> +#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
> +
> +/* data width is 32bit */
> +#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
> +
> +/* vsync mode is pulse */
> +#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
> +
> +/* Vlatch mask bit for L1ISP and L2ISP */
> +#define HWD_VIIF_ISP_VLATCH_MASK (2U)
> +
> +/* Register buffer */
> +#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
> +#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
> +#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
> +#define HWD_VIIF_ISP_REGBUF_READ (1U)
> +
> +/* constants for L1 ISP*/
> +#define HWD_VIIF_L1_INPUT_MODE_NUM (5U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_MIN (8U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_MAX (24U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_SDR_MAX (12U)
> +#define HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX (14U)
> +#define HWD_VIIF_L1_RAW_MODE_NUM (4U)
> +#define HWD_VIIF_L1_INPUT_NUM_MIN (1U)
> +#define HWD_VIIF_L1_INPUT_NUM_MAX (3U)
> +#define HWD_VIIF_L1_AG_ID_NUM (4U)
> +#define HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM (3U)
> +#define HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL (0x3fffU)
> +#define HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL (0xffffffU)
> +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO (0x400000U)
> +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL (0xffffffU)
> +#define HWD_VIIF_L1_OBCC_MAX_AG_VAL (511U)
> +#define HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL (0xffffffU)
> +#define HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL (1023U)
> +#define HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL (1U)
> +#define HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL (31U)
> +#define HWD_VIIF_L1_VDM_ALIGN (0x8U) /* port interface width is 64bit */
> +#define HWD_VIIF_L1_VDM_CFG_PARAM (0x00000310U) /* data width is 64bit */
> +#define HWD_VIIF_L1_VDM_SRAM_BASE (0x00000600U)
> +#define HWD_VIIF_L1_VDM_SRAM_SIZE (0x00000020U)
> +#define HWD_VIIF_L1_VDM_DPC_TABLE_SIZE (0x2000U)
> +#define HWD_VIIF_L1_VDM_LSC_TABLE_SIZE (0x600U)
> +#define HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL (4095U)
> +#define HWD_VIIF_L1_PWHB_MAX_GAIN_VAL (0x80000U)
> +#define HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL (63U)
> +#define HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL (31U)
> +#define HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL (3U)
> +#define HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL (256U)
> +#define HWD_VIIF_L1_RCNR_MAX_BLEND_VAL (16U)
> +#define HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL (64U)
> +#define HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL (4U)
> +#define HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL (16U)
> +#define HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL (32U)
> +#define HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL (2U)
> +#define HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO (15U)
> +#define HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO (0x400U)
> +#define HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO (0x400000U)
> +#define HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL (0x400000U)
> +#define HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL (0xffffffU)
> +#define HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL (4095U)
> +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL (0xffffffU)
> +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL (0x100000U)
> +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL (0xffffffU)
> +#define HWD_VIIF_LSC_MIN_GAIN (-4096)
> +#define HWD_VIIF_LSC_MAX_GAIN (4096)
> +#define HWD_VIIF_LSC_GRID_MIN_COORDINATE (1U)
> +#define HWD_VIIF_LSC_PWB_MAX_COEF_VAL (0x800U)
> +#define HWD_VIIF_DAMP_MAX_LSBSEL (15U)
> +#define HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL (0xffffffU)
> +#define HWD_VIIF_AWB_MIN_GAIN (64U)
> +#define HWD_VIIF_AWB_MAX_GAIN (1024U)
> +#define HWD_VIIF_AWB_GATE_LOWER (-127)
> +#define HWD_VIIF_AWB_GATE_UPPER (127)
> +#define HWD_VIIF_AWB_UNSIGNED_GATE_UPPER (127U)
> +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED (15U)
> +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL (31U)
> +#define HWD_VIIF_AWB_INTEGRATION_STOP_TH (1023U)
> +#define HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL (8U)
> +#define HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH (10U)
> +#define HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH (24U)
> +#define HWD_VIIF_L1_HDRC_MAX_PT_SLOPE (13U)
> +#define HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO (256U)
> +#define HWD_VIIF_L1_HDRC_MAX_FLARE_VAL (0xffffffU)
> +#define HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA (16U)
> +#define HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO (0x400000U)
> +#define HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION (0x4000U)
> +#define HWD_VIIF_L1_HDRC_RATIO_OFFSET (10U)
> +#define HWD_VIIF_L1_GAMMA_MAX_VAL (8191U)
> +#define HWD_VIIF_L1_SUPPRESSION_MAX_VAL (0x4000U)
> +#define HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT (15U)
> +#define HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN (0x1000U)
> +#define HWD_VIIF_L1_AEXP_MAX_WEIGHT (3U)
> +#define HWD_VIIF_L1_AEXP_MAX_BLOCK_TH (256U)
> +#define HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH (0xffffffU)
> +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH (64U)
> +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT (64U)
> +#define HWD_VIIF_L1_HIST_COLOR_RGBY (2U)
> +#define HWD_VIIF_L1_HIST_MAX_BLOCK_NUM (8U)
> +#define HWD_VIIF_L1_HIST_MAX_STEP (15U)
> +#define HWD_VIIF_L1_HIST_MAX_BIN_SHIFT (31U)
> +#define HWD_VIIF_L1_HIST_MAX_COEF (65536U)
> +#define HWD_VIIF_L1_HIST_MIN_ADD_B_COEF (-65536)
> +#define HWD_VIIF_L1_HIST_MIN_ADD_A_COEF (-16777216)
> +#define HWD_VIIF_L1_HIST_MAX_ADD_A_COEF (16777216)
> +#define HWD_VIIF_L1_HIST_VDM_SIZE (4096U)
> +#define HWD_VIIF_L1_HIST_VDM_SRAM_BASE (0x00000400U)
> +#define HWD_VIIF_L1_HIST_VDM_SRAM_SIZE (0x00000040U)
> +#define HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT (0x0200U)
> +#define HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT (0x10BFU)
> +#define HWD_VIIF_L1_COEF_MIN (256U)
> +#define HWD_VIIF_L1_COEF_MAX (65024U)
> +
> +/* constants for L2 ISP */
> +#define HWD_VIIF_L2_VDM_ALIGN (0x4U)
> +#define HWD_VIIF_L2_VDM_GRID_SRAM_BASE (0x00000620U)
> +#define HWD_VIIF_L2_VDM_GRID_SRAM_SIZE (0x00000020U)
> +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE (0x00000640U)
> +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE (0x00000020U)
> +#define HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE (0x00000200U)
> +#define HWD_VIIF_L2_UNDIST_POLY_NUM (11U)
> +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H (-4296)
> +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H (4296)
> +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V (-2360)
> +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V (2360)
> +#define HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE (1677721U)
> +#define HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2 (0x4000000U)
> +#define HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA (0x800U)
> +#define HWD_VIIF_L2_UNDIST_MIN_POLY_COEF (-2147352576)
> +#define HWD_VIIF_L2_UNDIST_MAX_POLY_COEF (2147352576)
> +#define HWD_VIIF_L2_UNDIST_MIN_GRID_NUM (16U)
> +#define HWD_VIIF_L2_UNDIST_MAX_GRID_NUM (64U)
> +#define HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM (2048U)
> +#define HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV (0x800000U)
> +#define HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE (0x400U)
> +#define HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE (0x2000U)
> +#define HWD_VIIF_L2_ROI_MIN_NUM (1U)
> +#define HWD_VIIF_L2_ROI_MAX_NUM (2U)
> +#define HWD_VIIF_L2_ROI_MIN_SCALE (32768U)
> +#define HWD_VIIF_L2_ROI_MAX_SCALE (131072U)
> +#define HWD_VIIF_L2_ROI_MIN_SCALE_INV (32768U)
> +#define HWD_VIIF_L2_ROI_MAX_SCALE_INV (131072U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE (8190U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE (4094U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE (8190U)
> +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE (128U)
> +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE (4094U)
> +#define HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT (0x1CU)
> +#define HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT (0x1FU)
> +#define HWD_VIIF_L2_ROI_NONE (3U)
> +#define HWD_VIIF_MAX_POST_NUM (2U)
> +#define HWD_VIIF_L2_INPUT_OTHER_CH (0x50U)
> +
> +/**
> + * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
> + *
> + * @roi_num: the number of ROIs which are used.
> + * @post_enable_flag: flag to show which of POST is enabled.
> + * @post_crop_x: CROP x of each L2ISP POST
> + * @post_crop_y: CROP y of each L2ISP POST
> + * @post_crop_w: CROP w of each L2ISP POST
> + * @post_crop_h: CROP h of each L2ISP POST
> + */
> +struct hwd_viif_l2_roi_path_info {
> + u32 roi_num;
> + bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_res - driver internal resource structure
> + *
> + * @clock_id: clock ID of each unit
> + * @csi2_clock_id: clock ID of CSI-2 RX
> + * @csi2_reset_id: reset ID of CSI-2 RX
> + * @pixel_clock: pixel clock
> + * @htotal_size: horizontal total size
> + * @dt_image_main_w_isp: Data type of image data for ISP path
> + * @csi2host_reg: pointer to register access structure of CSI-2 RX host controller
> + * @capture_reg: pointer to register access structure of capture unit
> + * @l2_roi_path_info: ROI path information of L2ISP
> + * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
> + */
> +struct hwd_viif_res {
> + //u32 clock_id;
> + //u32 csi2_clock_id;
> + //u32 csi2_reset_id;
Please remove these if they're not needed.
> + u32 pixel_clock;
> + u32 htotal_size;
> + u32 dt_image_main_w_isp;
> + struct hwd_viif_csi2host_reg *csi2host_reg;
> + struct hwd_viif_capture_reg *capture_reg;
> + struct hwd_viif_l2_roi_path_info l2_roi_path_info;
> + bool run_flag_main;
> +};
> +
> +/**
> + * struct hwd_viif_dphy_hs_info - dphy hs information
> + *
> + * @rate: Data rate [Mbps]
> + * @hsfreqrange: IP operating frequency(hsfreqrange)
> + * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
> + */
> +struct hwd_viif_dphy_hs_info {
> + u32 rate;
> + u32 hsfreqrange;
> + u32 osc_freq_target;
> +};
> +
> +#endif /* HWD_VIIF_INTERNAL_H */
> diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h b/drivers/media/platform/visconti/hwd_viif_reg.h
> new file mode 100644
> index 00000000000..b7f43c5fe95
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_reg.h
> @@ -0,0 +1,2802 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_REG_H
> +#define HWD_VIIF_REG_H
> +
> +/**
> + * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST control
> + */
> +struct hwd_viif_csi2host_reg {
> + u32 RESERVED_A_1;
> + u32 CSI2RX_NLANES;
> + u32 CSI2RX_RESETN;
> + u32 CSI2RX_INT_ST_MAIN;
> + u32 CSI2RX_DATA_IDS_1;
> + u32 CSI2RX_DATA_IDS_2;
> + u32 RESERVED_B_1[10];
> + u32 CSI2RX_PHY_SHUTDOWNZ;
> + u32 CSI2RX_PHY_RSTZ;
> + u32 CSI2RX_PHY_RX;
> + u32 CSI2RX_PHY_STOPSTATE;
> + u32 CSI2RX_PHY_TESTCTRL0;
> + u32 CSI2RX_PHY_TESTCTRL1;
> + u32 RESERVED_B_2[34];
> + u32 CSI2RX_INT_ST_PHY_FATAL;
> + u32 CSI2RX_INT_MSK_PHY_FATAL;
> + u32 CSI2RX_INT_FORCE_PHY_FATAL;
> + u32 RESERVED_B_3[1];
> + u32 CSI2RX_INT_ST_PKT_FATAL;
> + u32 CSI2RX_INT_MSK_PKT_FATAL;
> + u32 CSI2RX_INT_FORCE_PKT_FATAL;
> + u32 RESERVED_B_4[1];
> + u32 CSI2RX_INT_ST_FRAME_FATAL;
> + u32 CSI2RX_INT_MSK_FRAME_FATAL;
> + u32 CSI2RX_INT_FORCE_FRAME_FATAL;
> + u32 RESERVED_B_5[1];
> + u32 CSI2RX_INT_ST_PHY;
> + u32 CSI2RX_INT_MSK_PHY;
> + u32 CSI2RX_INT_FORCE_PHY;
> + u32 RESERVED_B_6[1];
> + u32 CSI2RX_INT_ST_PKT;
> + u32 CSI2RX_INT_MSK_PKT;
> + u32 CSI2RX_INT_FORCE_PKT;
> + u32 RESERVED_B_7[1];
> + u32 CSI2RX_INT_ST_LINE;
> + u32 CSI2RX_INT_MSK_LINE;
> + u32 CSI2RX_INT_FORCE_LINE;
> + u32 RESERVED_B_8[113];
> + u32 RESERVED_A_2;
> + u32 RESERVED_A_3;
> + u32 RESERVED_A_4;
> + u32 RESERVED_A_5;
> + u32 RESERVED_A_6;
> + u32 RESERVED_B_9[58];
> + u32 RESERVED_A_7;
These should be lower case, they're struct members.
This way of defining a hardware register interface is highly
unconventional. I'm not saying no to it, not now at least, but something
should be done to make this more robust against accidental changes: adding
a field in the middle changes the address of anything that comes after it,
and it's really difficult to say from the code alone that the address of a
given register is what it's intended to be. Maybe pahole would still help?
But some documentation would be needed in that case.
I wonder what others think.
> +};
> +
> +/**
> + * struct hwd_viif_csc_reg - Registers for VIIF system control
> + */
> +struct hwd_viif_csc_reg {
> + u32 MTB;
> + u32 RESERVED_B_16[3];
> + u32 MTB_YG_OFFSETI;
> + u32 MTB_YG1;
> + u32 MTB_YG2;
> + u32 MTB_YG_OFFSETO;
> + u32 MTB_CB_OFFSETI;
> + u32 MTB_CB1;
> + u32 MTB_CB2;
> + u32 MTB_CB_OFFSETO;
> + u32 MTB_CR_OFFSETI;
> + u32 MTB_CR1;
> + u32 MTB_CR2;
> + u32 MTB_CR_OFFSETO;
> +};
> +
> +struct hwd_viif_system_reg {
> + u32 IPORTM0_LD;
> + u32 IPORTM1_LD;
> + u32 RESERVED_B_1[6];
> + u32 IPORTS0_LD;
> + u32 RESERVED_A_1;
> + u32 RESERVED_B_2[2];
> + u32 VCID0SELECT;
> + u32 VCID1SELECT;
> + u32 RESERVED_A_2;
> + u32 VCPORTEN;
> + u32 CSI2SELECT;
> + u32 CSI2THROUGHEN;
> + u32 RESERVED_B_3[2];
> + u32 IPORTM_TEST;
> + u32 IPORTM;
> + u32 IPORTM_MAIN_DT;
> + u32 IPORTM_MAIN_RAW;
> + u32 IPORTM_OTHER;
> + u32 IPORTM_OTHEREN;
> + u32 IPORTM_EMBEN;
> + u32 RESERVED_B_4[2];
> + u32 IPORTS;
> + u32 IPORTS_MAIN_DT;
> + u32 IPORTS_MAIN_RAW;
> + u32 IPORTS_OTHER;
> + u32 IPORTS_OTHEREN;
> + u32 IPORTS_EMBEN;
> + u32 IPORTS_IMGEN;
> + u32 RESERVED_A_3;
> + u32 RESERVED_A_4;
> + u32 RESERVED_B_5[2];
> + u32 IPORTI_M_SYNCEN;
> + u32 IPORTI_M_SYNCMODE;
> + u32 IPORTI_M_PIXFMT;
> + u32 RESERVED_B_6[5];
> + u32 TOTALSIZE_M;
> + u32 VALSIZE_M;
> + u32 BACK_PORCH_M;
> + u32 RESERVED_B_7[5];
> + u32 MAINIMG_PKTSIZE;
> + u32 MAINIMG_HEIGHT;
> + u32 MAINOTHER_PKTSIZE;
> + u32 MAINOTHER_HEIGHT;
> + u32 MAINEMBTOP_SIZE;
> + u32 MAINEMBBOT_SIZE;
> + u32 RESERVED_B_8[2];
> + u32 SUBIMG_PKTSIZE;
> + u32 SUBIMG_HEIGHT;
> + u32 SUBOTHER_PKTSIZE;
> + u32 SUBOTHER_HEIGHT;
> + u32 SUBEMBTOP_SIZE;
> + u32 SUBEMBBOT_SIZE;
> + u32 RESERVED_A_5;
> + u32 RESERVED_A_6;
> + u32 TESTAREA_M_START;
> + u32 TESTAREA_M_SIZE;
> + u32 RESERVED_B_9[2];
> + u32 INT_M_SYNC;
> + u32 INT_M_SYNC_MASK;
> + u32 INT_S_SYNC;
> + u32 INT_S_SYNC_MASK;
> + u32 INT_M0_LINE;
> + u32 INT_M1_LINE;
> + u32 INT_M2_LINE;
> + u32 RESERVED_B_10[5];
> + u32 INT_SA0_LINE;
> + u32 INT_SA1_LINE;
> + u32 RESERVED_B_11[2];
> + u32 RESERVED_A_9;
> + u32 RESERVED_A_10;
> + u32 RESERVED_B_12[2];
> + u32 INT_M_STATUS;
> + u32 INT_M_MASK;
> + u32 INT_S_STATUS;
> + u32 INT_S_MASK;
> + u32 RESERVED_B_13[28];
> + u32 MAIN_TEST_DEN;
> + u32 RESERVED_B_14[3];
> + u32 PREPROCCESS_FMTM;
> + u32 PREPROCCESS_C24M;
> + u32 FRAMEPACK_M;
> + u32 RESERVED_B_15[1];
> + struct hwd_viif_csc_reg l2isp_input_csc;
> + u32 COM0_CK_ENABLE;
> + u32 RESERVED_A_13;
> + u32 RESERVED_A_14;
> + u32 RESERVED_B_17[1];
> + u32 COM0EN;
> + u32 RESERVED_A_16;
> + u32 RESERVED_A_17;
> + u32 RESERVED_B_18[33];
> + u32 COM0_CAP_OFFSET;
> + u32 COM0_CAP_SIZE;
> + u32 RESERVED_B_19[18];
> + u32 GAMMA_M;
> + u32 RESERVED_B_20[3];
> + u32 COM0_C_SELECT;
> + u32 RESERVED_B_21[3];
> + struct hwd_viif_csc_reg com0_csc;
> + u32 COM0_OPORTALP;
> + u32 COM0_OPORTFMT;
> + u32 RESERVED_B_23[2];
> + u32 RESERVED_A_37;
> + u32 RESERVED_A_38;
> + u32 RESERVED_A_39;
> + u32 RESERVED_B_24[1];
> + u32 RESERVED_A_40;
> + u32 RESERVED_A_41;
> + u32 RESERVED_A_42;
> + u32 RESERVED_B_25[1];
> + u32 RESERVED_A_43;
> + u32 RESERVED_A_44;
> + u32 RESERVED_A_45;
> + u32 RESERVED_B_26[1];
> + u32 RESERVED_A_46;
> + u32 RESERVED_B_27[3];
> + u32 RESERVED_A_47;
> + u32 RESERVED_A_48;
> + u32 RESERVED_B_28[18];
> + u32 RESERVED_A_49;
> + u32 RESERVED_B_29[3];
> + u32 RESERVED_A_50;
> + u32 RESERVED_B_30[3];
> + u32 RESERVED_A_51;
> + u32 RESERVED_B_31[3];
> + u32 RESERVED_A_52;
> + u32 RESERVED_A_53;
> + u32 RESERVED_A_54;
> + u32 RESERVED_A_55;
> + u32 RESERVED_A_56;
> + u32 RESERVED_A_57;
> + u32 RESERVED_A_58;
> + u32 RESERVED_A_59;
> + u32 RESERVED_A_60;
> + u32 RESERVED_A_61;
> + u32 RESERVED_A_62;
> + u32 RESERVED_A_63;
> + u32 RESERVED_A_64;
> + u32 RESERVED_A_65;
> + u32 RESERVED_B_32[2];
> + u32 RESERVED_A_66;
> + u32 RESERVED_A_67;
> + u32 RESERVED_A_68;
> + u32 RESERVED_B_33[1];
> + u32 RESERVED_A_69;
> + u32 RESERVED_A_70;
> + u32 RESERVED_A_71;
> + u32 RESERVED_B_34[1];
> + u32 RESERVED_A_72;
> + u32 RESERVED_A_73;
> + u32 RESERVED_A_74;
> + u32 RESERVED_B_35[1];
> + u32 RESERVED_A_75;
> + u32 RESERVED_B_36[3];
> + u32 RESERVED_A_76;
> + u32 RESERVED_A_77;
> + u32 RESERVED_B_37[18];
> + u32 RESERVED_A_78;
> + u32 RESERVED_B_38[3];
> + u32 RESERVED_A_79;
> + u32 RESERVED_B_39[3];
> + u32 RESERVED_A_80;
> + u32 RESERVED_B_40[3];
> + u32 RESERVED_A_81;
> + u32 RESERVED_A_82;
> + u32 RESERVED_A_83;
> + u32 RESERVED_A_84;
> + u32 RESERVED_A_85;
> + u32 RESERVED_A_86;
> + u32 RESERVED_A_87;
> + u32 RESERVED_A_88;
> + u32 RESERVED_A_89;
> + u32 RESERVED_A_90;
> + u32 RESERVED_A_91;
> + u32 RESERVED_A_92;
> + u32 RESERVED_A_93;
> + u32 RESERVED_A_94;
> + u32 RESERVED_B_41[2];
> + u32 RESERVED_A_95;
> + u32 RESERVED_A_96;
> + u32 RESERVED_A_97;
> + u32 RESERVED_B_42[1];
> + u32 RESERVED_A_98;
> + u32 RESERVED_A_99;
> + u32 RESERVED_A_100;
> + u32 RESERVED_B_43[1];
> + u32 RESERVED_A_101;
> + u32 RESERVED_A_102;
> + u32 RESERVED_A_103;
> + u32 RESERVED_B_44[1];
> + u32 RESERVED_A_104;
> + u32 RESERVED_B_45[3];
> + u32 FN_M0;
> + u32 FN_M1;
> + u32 FN_M2;
> + u32 RESERVED_B_46[5];
> + u32 FN_SA0;
> + u32 FN_SA1;
> + u32 RESERVED_B_47[2];
> + u32 RESERVED_A_105;
> + u32 RESERVED_A_106;
> + u32 RESERVED_B_48[18];
> + u32 LBIST_STAT;
> + u32 MEM_ECC_DCLS_ALARM;
> + u32 RESERVED_B_49[30];
> + u32 DPHY_FREQRANGE;
> + u32 RESERVED_B_50[3];
> + u32 DPHY_LANE;
> + u32 RESERVED_B_51[59];
> + u32 INT_SOURCE;
> + u32 DPGM_VSYNC_SOURCE;
> + u32 RESERVED_B_52[23];
> + u32 RESERVED_A_107;
> + u32 RESERVED_A_108;
> + u32 RESERVED_B_53[6];
> + u32 RESERVED_A_109;
> + u32 RESERVED_A_110;
> + u32 RESERVED_A_111;
> + u32 RESERVED_B_54[1];
> + u32 RESERVED_A_112;
> + u32 RESERVED_B_55[35];
> + u32 RESERVED_A_113;
> + u32 RESERVED_B_56[54];
> + u32 RESERVED_A_114;
> + u32 RESERVED_B_57[3];
> + u32 RESERVED_A_115;
> + u32 RESERVED_A_116;
> + u32 RESERVED_A_117;
> + u32 RESERVED_B_58[1];
> + u32 RESERVED_A_118;
> + u32 RESERVED_B_59[3];
> + u32 RESERVED_A_119;
> + u32 RESERVED_A_120;
> + u32 RESERVED_A_121;
> + u32 RESERVED_A_122;
> + u32 RESERVED_A_123;
> + u32 RESERVED_A_124;
> + u32 RESERVED_A_125;
> + u32 RESERVED_A_126;
> + u32 RESERVED_A_127;
> + u32 RESERVED_A_128;
> + u32 RESERVED_A_129;
> + u32 RESERVED_A_130;
> + u32 RESERVED_B_60[4];
> + u32 RESERVED_A_131;
> + u32 RESERVED_A_132;
> + u32 RESERVED_A_133;
> + u32 RESERVED_B_61[33];
> + u32 RESERVED_A_134;
> + u32 RESERVED_A_135;
> + u32 RESERVED_B_62[18];
> + u32 RESERVED_A_136;
> + u32 RESERVED_B_63[3];
> + u32 RESERVED_A_137;
> + u32 RESERVED_B_64[3];
> + u32 RESERVED_A_138;
> + u32 RESERVED_B_65[3];
> + u32 RESERVED_A_139;
> + u32 RESERVED_A_140;
> + u32 RESERVED_A_141;
> + u32 RESERVED_A_142;
> + u32 RESERVED_A_143;
> + u32 RESERVED_A_144;
> + u32 RESERVED_A_145;
> + u32 RESERVED_A_146;
> + u32 RESERVED_A_147;
> + u32 RESERVED_A_148;
> + u32 RESERVED_A_149;
> + u32 RESERVED_A_150;
> + u32 RESERVED_A_151;
> + u32 RESERVED_A_152;
> + u32 RESERVED_B_66[2];
> + u32 RESERVED_A_153;
> + u32 RESERVED_A_154;
> + u32 RESERVED_A_155;
> + u32 RESERVED_B_67[1];
> + u32 RESERVED_A_156;
> + u32 RESERVED_A_157;
> + u32 RESERVED_A_158;
> + u32 RESERVED_B_68[1];
> + u32 RESERVED_A_159;
> + u32 RESERVED_A_160;
> + u32 RESERVED_A_161;
> + u32 RESERVED_B_69[1];
> + u32 RESERVED_A_162;
> + u32 RESERVED_B_70[3];
> + u32 RESERVED_A_163;
> + u32 RESERVED_A_164;
> + u32 RESERVED_B_71[18];
> + u32 RESERVED_A_165;
> + u32 RESERVED_B_72[3];
> + u32 RESERVED_A_166;
> + u32 RESERVED_B_73[3];
> + u32 RESERVED_A_167;
> + u32 RESERVED_B_74[3];
> + u32 RESERVED_A_168;
> + u32 RESERVED_A_169;
> + u32 RESERVED_A_170;
> + u32 RESERVED_A_171;
> + u32 RESERVED_A_172;
> + u32 RESERVED_A_173;
> + u32 RESERVED_A_174;
> + u32 RESERVED_A_175;
> + u32 RESERVED_A_176;
> + u32 RESERVED_A_177;
> + u32 RESERVED_A_178;
> + u32 RESERVED_A_179;
> + u32 RESERVED_A_180;
> + u32 RESERVED_A_181;
> + u32 RESERVED_B_75[2];
> + u32 RESERVED_A_182;
> + u32 RESERVED_A_183;
> + u32 RESERVED_A_184;
> + u32 RESERVED_B_76[1];
> + u32 RESERVED_A_185;
> + u32 RESERVED_A_186;
> + u32 RESERVED_A_187;
> + u32 RESERVED_B_77[1];
> + u32 RESERVED_A_188;
> + u32 RESERVED_A_189;
> + u32 RESERVED_A_190;
> + u32 RESERVED_B_78[1];
> + u32 RESERVED_A_191;
> + u32 RESERVED_B_79[3];
> + u32 RESERVED_A_192;
> + u32 RESERVED_A_193;
> + u32 RESERVED_B_80[18];
> + u32 RESERVED_A_194;
> + u32 RESERVED_B_81[3];
> + u32 RESERVED_A_195;
> + u32 RESERVED_B_82[3];
> + u32 RESERVED_A_196;
> + u32 RESERVED_B_83[3];
> + u32 RESERVED_A_197;
> + u32 RESERVED_A_198;
> + u32 RESERVED_A_199;
> + u32 RESERVED_A_200;
> + u32 RESERVED_A_201;
> + u32 RESERVED_A_202;
> + u32 RESERVED_A_203;
> + u32 RESERVED_A_204;
> + u32 RESERVED_A_205;
> + u32 RESERVED_A_206;
> + u32 RESERVED_A_207;
> + u32 RESERVED_A_208;
> + u32 RESERVED_A_209;
> + u32 RESERVED_A_210;
> + u32 RESERVED_B_84[2];
> + u32 RESERVED_A_211;
> + u32 RESERVED_A_212;
> + u32 RESERVED_A_213;
> + u32 RESERVED_B_85[1];
> + u32 RESERVED_A_214;
> + u32 RESERVED_A_215;
> + u32 RESERVED_A_216;
> + u32 RESERVED_B_86[1];
> + u32 RESERVED_A_217;
> + u32 RESERVED_A_218;
> + u32 RESERVED_A_219;
> + u32 RESERVED_B_87[1];
> + u32 RESERVED_A_220;
> + u32 RESERVED_B_88[130];
> + u32 RESERVED_A_221;
> +};
> +
> +/**
> + * struct hwd_viif_vdm_table_group_reg - Registers for VIIF vdm control
> + */
> +struct hwd_viif_vdm_table_group_reg {
> + u32 VDM_T_CFG;
> + u32 VDM_T_SRAM_BASE;
> + u32 VDM_T_SRAM_SIZE;
> + u32 RESERVED_A_4;
> +};
> +
> +struct hwd_viif_vdm_table_port_reg {
> + u32 VDM_T_STADR;
> + u32 VDM_T_SIZE;
> +};
> +
> +struct hwd_viif_vdm_read_port_reg {
> + u32 VDM_R_STADR;
> + u32 VDM_R_ENDADR;
> + u32 VDM_R_HEIGHT;
> + u32 VDM_R_PITCH;
> + u32 VDM_R_CFG0;
> + u32 RESERVED_A_11;
> + u32 VDM_R_SRAM_BASE;
> + u32 VDM_R_SRAM_SIZE;
> + u32 RESERVED_A_12;
> + u32 RESERVED_B_5[7];
> +};
> +
> +struct hwd_viif_vdm_write_port_reg {
> + u32 VDM_W_STADR;
> + u32 VDM_W_ENDADR;
> + u32 VDM_W_HEIGHT;
> + u32 VDM_W_PITCH;
> + u32 VDM_W_CFG0;
> + u32 RESERVED_A_17;
> + u32 VDM_W_SRAM_BASE;
> + u32 VDM_W_SRAM_SIZE;
> + u32 RESERVED_A_18;
> + u32 RESERVED_B_8[7];
> +};
> +
> +struct hwd_viif_vdm_write_port_buf_reg {
> + u32 VDM_W_STADR_BUF;
> + u32 RESERVED_A_120;
> + u32 RESERVED_A_121;
> + u32 RESERVED_A_122;
> + u32 RESERVED_A_123;
> + u32 RESERVED_A_124;
> + u32 RESERVED_B_20[2];
> +};
> +
> +struct hwd_viif_vdm_reg {
> + u32 RESERVED_A_1;
> + u32 RESERVED_A_2;
> + u32 RESERVED_B_1[4];
> + u32 RESERVED_A_3;
> + u32 VDM_CFG;
> + u32 VDM_INT_MASK;
> + u32 RESERVED_B_2[3];
> + u32 VDM_R_ENABLE;
> + u32 VDM_W_ENABLE;
> + u32 VDM_T_ENABLE;
> + u32 VDM_ABORTSET;
> + struct hwd_viif_vdm_table_group_reg t_group[4];
> + u32 RESERVED_A_8;
> + u32 RESERVED_A_9;
> + u32 RESERVED_A_10;
> + u32 RESERVED_A_11;
> + u32 RESERVED_B_3[28];
> + struct hwd_viif_vdm_table_port_reg t_port[24];
> + u32 RESERVED_A_14;
> + u32 RESERVED_A_15;
> + u32 RESERVED_A_16;
> + u32 RESERVED_A_17;
> + u32 RESERVED_A_18;
> + u32 RESERVED_A_19;
> + u32 RESERVED_A_20;
> + u32 RESERVED_A_21;
> + u32 RESERVED_A_22;
> + u32 RESERVED_A_23;
> + u32 RESERVED_A_24;
> + u32 RESERVED_A_25;
> + u32 RESERVED_B_4[4];
> + struct hwd_viif_vdm_read_port_reg r_port[3];
> + u32 RESERVED_B_7[16];
> + struct hwd_viif_vdm_write_port_reg w_port[6];
> + u32 RESERVED_A_29;
> + u32 RESERVED_A_30;
> + u32 RESERVED_A_31;
> + u32 RESERVED_A_32;
> + u32 RESERVED_A_33;
> + u32 RESERVED_A_34;
> + u32 RESERVED_A_35;
> + u32 RESERVED_A_36;
> + u32 RESERVED_A_37;
> + u32 RESERVED_B_14[215];
> + u32 RESERVED_A_38;
> + u32 RESERVED_A_39;
> + u32 RESERVED_A_40;
> + u32 RESERVED_B_15[61];
> + u32 RESERVED_A_41;
> + u32 RESERVED_A_42;
> + u32 RESERVED_A_43;
> + u32 RESERVED_A_44;
> + u32 RESERVED_A_45;
> + u32 RESERVED_A_46;
> + u32 RESERVED_A_47;
> + u32 RESERVED_A_48;
> + u32 RESERVED_A_49;
> + u32 RESERVED_A_50;
> + u32 RESERVED_A_51;
> + u32 RESERVED_A_52;
> + u32 RESERVED_A_53;
> + u32 RESERVED_A_54;
> + u32 RESERVED_A_55;
> + u32 RESERVED_A_56;
> + u32 RESERVED_A_57;
> + u32 RESERVED_A_58;
> + u32 RESERVED_A_59;
> + u32 RESERVED_A_60;
> + u32 RESERVED_A_61;
> + u32 RESERVED_A_62;
> + u32 RESERVED_A_63;
> + u32 RESERVED_A_64;
> + u32 RESERVED_A_65;
> + u32 RESERVED_A_66;
> + u32 RESERVED_A_67;
> + u32 RESERVED_A_68;
> + u32 RESERVED_A_69;
> + u32 RESERVED_A_70;
> + u32 RESERVED_A_71;
> + u32 RESERVED_A_72;
> + u32 RESERVED_A_73;
> + u32 RESERVED_A_74;
> + u32 RESERVED_A_75;
> + u32 RESERVED_A_76;
> + u32 RESERVED_A_77;
> + u32 RESERVED_A_78;
> + u32 RESERVED_A_79;
> + u32 RESERVED_A_80;
> + u32 RESERVED_A_81;
> + u32 RESERVED_A_82;
> + u32 RESERVED_A_83;
> + u32 RESERVED_A_84;
> + u32 RESERVED_A_85;
> + u32 RESERVED_A_86;
> + u32 RESERVED_A_87;
> + u32 RESERVED_A_88;
> + u32 RESERVED_A_89;
> + u32 RESERVED_A_90;
> + u32 RESERVED_A_91;
> + u32 RESERVED_A_92;
> + u32 RESERVED_A_93;
> + u32 RESERVED_A_94;
> + u32 RESERVED_A_95;
> + u32 RESERVED_A_96;
> + u32 RESERVED_A_97;
> + u32 RESERVED_A_98;
> + u32 RESERVED_A_99;
> + u32 RESERVED_A_100;
> + u32 RESERVED_B_16[4];
> + u32 RESERVED_A_101;
> + u32 RESERVED_A_102;
> + u32 RESERVED_A_103;
> + u32 RESERVED_A_104;
> + u32 RESERVED_A_105;
> + u32 RESERVED_A_106;
> + u32 RESERVED_B_17[2];
> + u32 RESERVED_A_107;
> + u32 RESERVED_A_108;
> + u32 RESERVED_A_109;
> + u32 RESERVED_A_110;
> + u32 RESERVED_A_111;
> + u32 RESERVED_A_112;
> + u32 RESERVED_B_18[2];
> + u32 RESERVED_A_113;
> + u32 RESERVED_A_114;
> + u32 RESERVED_A_115;
> + u32 RESERVED_A_116;
> + u32 RESERVED_A_117;
> + u32 RESERVED_A_118;
> + u32 RESERVED_B_19[42];
> + struct hwd_viif_vdm_write_port_buf_reg w_port_buf[6];
> + u32 RESERVED_A_155;
> + u32 RESERVED_A_156;
> + u32 RESERVED_A_157;
> + u32 RESERVED_A_158;
> + u32 RESERVED_A_159;
> + u32 RESERVED_A_160;
> + u32 RESERVED_B_26[138];
> + u32 RESERVED_A_161;
> + u32 VDM_INT;
> + u32 RESERVED_A_162;
> + u32 RESERVED_A_163;
> + u32 VDM_R_STOP;
> + u32 VDM_W_STOP;
> + u32 VDM_R_RUN;
> + u32 VDM_W_RUN;
> + u32 VDM_T_RUN;
> + u32 RESERVED_B_27[7];
> + u32 RESERVED_A_164;
> + u32 RESERVED_A_165;
> + u32 RESERVED_A_166;
> + u32 RESERVED_A_167;
> + u32 RESERVED_B_28[12];
> + u32 RESERVED_A_168;
> + u32 RESERVED_A_169;
> + u32 RESERVED_A_170;
> + u32 RESERVED_A_171;
> + u32 RESERVED_A_172;
> + u32 RESERVED_B_29[27];
> + u32 RESERVED_A_173;
> + u32 RESERVED_A_174;
> + u32 RESERVED_A_175;
> + u32 RESERVED_A_176;
> + u32 RESERVED_A_177;
> + u32 RESERVED_A_178;
> + u32 RESERVED_B_30[10];
> + u32 RESERVED_A_179;
> + u32 RESERVED_A_180;
> + u32 RESERVED_A_181;
> + u32 RESERVED_A_182;
> + u32 RESERVED_A_183;
> + u32 RESERVED_A_184;
> + u32 RESERVED_A_185;
> + u32 RESERVED_A_186;
> + u32 RESERVED_A_187;
> + u32 RESERVED_A_188;
> + u32 RESERVED_A_189;
> + u32 RESERVED_A_190;
> + u32 RESERVED_A_191;
> + u32 RESERVED_A_192;
> + u32 RESERVED_B_31[33];
> + u32 RESERVED_A_193;
> +};
> +
> +/**
> + * struct hwd_viif_l1isp_reg - Registers for VIIF L1ISP control
> + */
> +struct hwd_viif_l1isp_reg {
> + u32 L1_SYSM_WIDTH;
> + u32 L1_SYSM_HEIGHT;
> + u32 L1_SYSM_START_COLOR;
> + u32 L1_SYSM_INPUT_MODE;
> + u32 RESERVED_A_1;
> + u32 L1_SYSM_YCOEF_R;
> + u32 L1_SYSM_YCOEF_G;
> + u32 L1_SYSM_YCOEF_B;
> + u32 L1_SYSM_INT_STAT;
> + u32 L1_SYSM_INT_MASKED_STAT;
> + u32 L1_SYSM_INT_MASK;
> + u32 RESERVED_A_2;
> + u32 RESERVED_A_3;
> + u32 RESERVED_A_4;
> + u32 RESERVED_B_1[2];
> + u32 L1_SYSM_AG_H;
> + u32 L1_SYSM_AG_M;
> + u32 L1_SYSM_AG_L;
> + u32 L1_SYSM_AG_PARAM_A;
> + u32 L1_SYSM_AG_PARAM_B;
> + u32 L1_SYSM_AG_PARAM_C;
> + u32 L1_SYSM_AG_PARAM_D;
> + u32 L1_SYSM_AG_SEL_HOBC;
> + u32 L1_SYSM_AG_SEL_ABPC;
> + u32 L1_SYSM_AG_SEL_RCNR;
> + u32 L1_SYSM_AG_SEL_LSSC;
> + u32 L1_SYSM_AG_SEL_MPRO;
> + u32 L1_SYSM_AG_SEL_VPRO;
> + u32 L1_SYSM_AG_CONT_HOBC01_EN;
> + u32 L1_SYSM_AG_CONT_HOBC2_EN;
> + u32 L1_SYSM_AG_CONT_ABPC01_EN;
> + u32 L1_SYSM_AG_CONT_ABPC2_EN;
> + u32 L1_SYSM_AG_CONT_RCNR01_EN;
> + u32 L1_SYSM_AG_CONT_RCNR2_EN;
> + u32 L1_SYSM_AG_CONT_LSSC_EN;
> + u32 L1_SYSM_AG_CONT_MPRO_EN;
> + u32 L1_SYSM_AG_CONT_VPRO_EN;
> + u32 L1_SYSM_CTXT;
> + u32 L1_SYSM_MAN_CTXT;
> + u32 RESERVED_A_5;
> + u32 RESERVED_B_2[7];
> + u32 RESERVED_A_6;
> + u32 L1_HDRE_SRCPOINT00;
> + u32 L1_HDRE_SRCPOINT01;
> + u32 L1_HDRE_SRCPOINT02;
> + u32 L1_HDRE_SRCPOINT03;
> + u32 L1_HDRE_SRCPOINT04;
> + u32 L1_HDRE_SRCPOINT05;
> + u32 L1_HDRE_SRCPOINT06;
> + u32 L1_HDRE_SRCPOINT07;
> + u32 L1_HDRE_SRCPOINT08;
> + u32 L1_HDRE_SRCPOINT09;
> + u32 L1_HDRE_SRCPOINT10;
> + u32 L1_HDRE_SRCPOINT11;
> + u32 L1_HDRE_SRCPOINT12;
> + u32 L1_HDRE_SRCPOINT13;
> + u32 L1_HDRE_SRCPOINT14;
> + u32 L1_HDRE_SRCPOINT15;
> + u32 L1_HDRE_SRCBASE00;
> + u32 L1_HDRE_SRCBASE01;
> + u32 L1_HDRE_SRCBASE02;
> + u32 L1_HDRE_SRCBASE03;
> + u32 L1_HDRE_SRCBASE04;
> + u32 L1_HDRE_SRCBASE05;
> + u32 L1_HDRE_SRCBASE06;
> + u32 L1_HDRE_SRCBASE07;
> + u32 L1_HDRE_SRCBASE08;
> + u32 L1_HDRE_SRCBASE09;
> + u32 L1_HDRE_SRCBASE10;
> + u32 L1_HDRE_SRCBASE11;
> + u32 L1_HDRE_SRCBASE12;
> + u32 L1_HDRE_SRCBASE13;
> + u32 L1_HDRE_SRCBASE14;
> + u32 L1_HDRE_SRCBASE15;
> + u32 L1_HDRE_SRCBASE16;
> + u32 L1_HDRE_RATIO00;
> + u32 L1_HDRE_RATIO01;
> + u32 L1_HDRE_RATIO02;
> + u32 L1_HDRE_RATIO03;
> + u32 L1_HDRE_RATIO04;
> + u32 L1_HDRE_RATIO05;
> + u32 L1_HDRE_RATIO06;
> + u32 L1_HDRE_RATIO07;
> + u32 L1_HDRE_RATIO08;
> + u32 L1_HDRE_RATIO09;
> + u32 L1_HDRE_RATIO10;
> + u32 L1_HDRE_RATIO11;
> + u32 L1_HDRE_RATIO12;
> + u32 L1_HDRE_RATIO13;
> + u32 L1_HDRE_RATIO14;
> + u32 L1_HDRE_RATIO15;
> + u32 L1_HDRE_RATIO16;
> + u32 L1_HDRE_DSTBASE00;
> + u32 L1_HDRE_DSTBASE01;
> + u32 L1_HDRE_DSTBASE02;
> + u32 L1_HDRE_DSTBASE03;
> + u32 L1_HDRE_DSTBASE04;
> + u32 L1_HDRE_DSTBASE05;
> + u32 L1_HDRE_DSTBASE06;
> + u32 L1_HDRE_DSTBASE07;
> + u32 L1_HDRE_DSTBASE08;
> + u32 L1_HDRE_DSTBASE09;
> + u32 L1_HDRE_DSTBASE10;
> + u32 L1_HDRE_DSTBASE11;
> + u32 L1_HDRE_DSTBASE12;
> + u32 L1_HDRE_DSTBASE13;
> + u32 L1_HDRE_DSTBASE14;
> + u32 L1_HDRE_DSTBASE15;
> + u32 L1_HDRE_DSTBASE16;
> + u32 L1_HDRE_DSTMAXVAL;
> + u32 RESERVED_B_3[11];
> + u32 L1_AEXP_ON;
> + u32 L1_AEXP_RESULT_AVE;
> + u32 RESERVED_A_7;
> + u32 L1_AEXP_FORCE_INTERRUPT_Y;
> + u32 L1_AEXP_START_X;
> + u32 L1_AEXP_START_Y;
> + u32 L1_AEXP_BLOCK_WIDTH;
> + u32 L1_AEXP_BLOCK_HEIGHT;
> + u32 L1_AEXP_WEIGHT_0;
> + u32 L1_AEXP_WEIGHT_1;
> + u32 L1_AEXP_WEIGHT_2;
> + u32 L1_AEXP_WEIGHT_3;
> + u32 L1_AEXP_WEIGHT_4;
> + u32 L1_AEXP_WEIGHT_5;
> + u32 L1_AEXP_WEIGHT_6;
> + u32 L1_AEXP_WEIGHT_7;
> + u32 L1_AEXP_SATUR_RATIO;
> + u32 L1_AEXP_BLACK_RATIO;
> + u32 L1_AEXP_SATUR_LEVEL;
> + u32 RESERVED_A_8;
> + /* [y][x] */
> + u32 L1_AEXP_AVE[8][8];
> + u32 L1_AEXP_SATUR_BLACK_PIXNUM;
> + u32 L1_AEXP_AVE4LINESY0;
> + u32 L1_AEXP_AVE4LINESY1;
> + u32 L1_AEXP_AVE4LINESY2;
> + u32 L1_AEXP_AVE4LINESY3;
> + u32 L1_AEXP_AVE4LINES0;
> + u32 L1_AEXP_AVE4LINES1;
> + u32 L1_AEXP_AVE4LINES2;
> + u32 L1_AEXP_AVE4LINES3;
> + u32 RESERVED_B_4[3];
> + u32 L1_IBUF_DEPTH;
> + u32 L1_IBUF_INPUT_ORDER;
> + u32 RESERVED_B_5[2];
> + u32 L1_SLIC_SRCBLACKLEVEL_GR;
> + u32 L1_SLIC_SRCBLACKLEVEL_R;
> + u32 L1_SLIC_SRCBLACKLEVEL_B;
> + u32 L1_SLIC_SRCBLACKLEVEL_GB;
> + u32 RESERVED_A_9;
> + u32 RESERVED_A_10;
> + u32 RESERVED_A_11;
> + u32 RESERVED_A_12;
> + u32 RESERVED_A_13;
> + u32 RESERVED_B_6[19];
> + u32 RESERVED_A_14;
> + u32 RESERVED_A_15;
> + u32 L1_ABPC012_AG_CONT;
> + u32 L1_ABPC012_STA_EN;
> + u32 L1_ABPC012_DYN_EN;
> + u32 L1_ABPC012_DYN_MODE;
> + u32 RESERVED_A_16;
> + u32 RESERVED_A_17;
> + u32 RESERVED_A_18;
> + u32 L1_ABPC0_RATIO_LIMIT;
> + u32 RESERVED_A_19;
> + u32 L1_ABPC0_DARK_LIMIT;
> + u32 L1_ABPC0_SN_COEF_W_AG_MIN;
> + u32 L1_ABPC0_SN_COEF_W_AG_MID;
> + u32 L1_ABPC0_SN_COEF_W_AG_MAX;
> + u32 L1_ABPC0_SN_COEF_W_TH_MIN;
> + u32 L1_ABPC0_SN_COEF_W_TH_MAX;
> + u32 L1_ABPC0_SN_COEF_B_AG_MIN;
> + u32 L1_ABPC0_SN_COEF_B_AG_MID;
> + u32 L1_ABPC0_SN_COEF_B_AG_MAX;
> + u32 L1_ABPC0_SN_COEF_B_TH_MIN;
> + u32 L1_ABPC0_SN_COEF_B_TH_MAX;
> + u32 RESERVED_A_20;
> + u32 L1_ABPC0_DETECT;
> + u32 L1_ABPC1_RATIO_LIMIT;
> + u32 RESERVED_A_21;
> + u32 L1_ABPC1_DARK_LIMIT;
> + u32 L1_ABPC1_SN_COEF_W_AG_MIN;
> + u32 L1_ABPC1_SN_COEF_W_AG_MID;
> + u32 L1_ABPC1_SN_COEF_W_AG_MAX;
> + u32 L1_ABPC1_SN_COEF_W_TH_MIN;
> + u32 L1_ABPC1_SN_COEF_W_TH_MAX;
> + u32 L1_ABPC1_SN_COEF_B_AG_MIN;
> + u32 L1_ABPC1_SN_COEF_B_AG_MID;
> + u32 L1_ABPC1_SN_COEF_B_AG_MAX;
> + u32 L1_ABPC1_SN_COEF_B_TH_MIN;
> + u32 L1_ABPC1_SN_COEF_B_TH_MAX;
> + u32 RESERVED_A_22;
> + u32 L1_ABPC1_DETECT;
> + u32 L1_ABPC2_RATIO_LIMIT;
> + u32 RESERVED_A_23;
> + u32 L1_ABPC2_DARK_LIMIT;
> + u32 L1_ABPC2_SN_COEF_W_AG_MIN;
> + u32 L1_ABPC2_SN_COEF_W_AG_MID;
> + u32 L1_ABPC2_SN_COEF_W_AG_MAX;
> + u32 L1_ABPC2_SN_COEF_W_TH_MIN;
> + u32 L1_ABPC2_SN_COEF_W_TH_MAX;
> + u32 L1_ABPC2_SN_COEF_B_AG_MIN;
> + u32 L1_ABPC2_SN_COEF_B_AG_MID;
> + u32 L1_ABPC2_SN_COEF_B_AG_MAX;
> + u32 L1_ABPC2_SN_COEF_B_TH_MIN;
> + u32 L1_ABPC2_SN_COEF_B_TH_MAX;
> + u32 RESERVED_A_24;
> + u32 L1_ABPC2_DETECT;
> + u32 RESERVED_B_7[42];
> + u32 RESERVED_A_25;
> + u32 L1_PWHB_H_GR;
> + u32 L1_PWHB_HR;
> + u32 L1_PWHB_HB;
> + u32 L1_PWHB_H_GB;
> + u32 L1_PWHB_M_GR;
> + u32 L1_PWHB_MR;
> + u32 L1_PWHB_MB;
> + u32 L1_PWHB_M_GB;
> + u32 L1_PWHB_L_GR;
> + u32 L1_PWHB_LR;
> + u32 L1_PWHB_LB;
> + u32 L1_PWHB_L_GB;
> + u32 L1_PWHB_DSTMAXVAL;
> + u32 RESERVED_B_8[18];
> + u32 L1_RCNR0_AG_CONT;
> + u32 RESERVED_A_26;
> + u32 L1_RCNR0_SW;
> + u32 L1_RCNR0_CNF_DARK_AG0;
> + u32 L1_RCNR0_CNF_DARK_AG1;
> + u32 L1_RCNR0_CNF_DARK_AG2;
> + u32 L1_RCNR0_CNF_RATIO_AG0;
> + u32 L1_RCNR0_CNF_RATIO_AG1;
> + u32 L1_RCNR0_CNF_RATIO_AG2;
> + u32 L1_RCNR0_CNF_CLIP_GAIN_R;
> + u32 L1_RCNR0_CNF_CLIP_GAIN_G;
> + u32 L1_RCNR0_CNF_CLIP_GAIN_B;
> + u32 L1_RCNR0_A1L_DARK_AG0;
> + u32 L1_RCNR0_A1L_DARK_AG1;
> + u32 L1_RCNR0_A1L_DARK_AG2;
> + u32 L1_RCNR0_A1L_RATIO_AG0;
> + u32 L1_RCNR0_A1L_RATIO_AG1;
> + u32 L1_RCNR0_A1L_RATIO_AG2;
> + u32 L1_RCNR0_INF_ZERO_CLIP;
> + u32 RESERVED_A_27;
> + u32 L1_RCNR0_MERGE_D2BLEND_AG0;
> + u32 L1_RCNR0_MERGE_D2BLEND_AG1;
> + u32 L1_RCNR0_MERGE_D2BLEND_AG2;
> + u32 L1_RCNR0_MERGE_BLACK;
> + u32 L1_RCNR0_MERGE_MINDIV;
> + u32 L1_RCNR0_HRY_TYPE;
> + u32 L1_RCNR0_ANF_BLEND_AG0;
> + u32 L1_RCNR0_ANF_BLEND_AG1;
> + u32 L1_RCNR0_ANF_BLEND_AG2;
> + u32 RESERVED_A_28;
> + u32 L1_RCNR0_LPF_THRESHOLD;
> + u32 L1_RCNR0_MERGE_HLBLEND_AG0;
> + u32 L1_RCNR0_MERGE_HLBLEND_AG1;
> + u32 L1_RCNR0_MERGE_HLBLEND_AG2;
> + u32 L1_RCNR0_GNR_SW;
> + u32 L1_RCNR0_GNR_RATIO;
> + u32 L1_RCNR0_GNR_WIDE_EN;
> + u32 L1_RCNR1_AG_CONT;
> + u32 RESERVED_A_29;
> + u32 L1_RCNR1_SW;
> + u32 L1_RCNR1_CNF_DARK_AG0;
> + u32 L1_RCNR1_CNF_DARK_AG1;
> + u32 L1_RCNR1_CNF_DARK_AG2;
> + u32 L1_RCNR1_CNF_RATIO_AG0;
> + u32 L1_RCNR1_CNF_RATIO_AG1;
> + u32 L1_RCNR1_CNF_RATIO_AG2;
> + u32 L1_RCNR1_CNF_CLIP_GAIN_R;
> + u32 L1_RCNR1_CNF_CLIP_GAIN_G;
> + u32 L1_RCNR1_CNF_CLIP_GAIN_B;
> + u32 L1_RCNR1_A1L_DARK_AG0;
> + u32 L1_RCNR1_A1L_DARK_AG1;
> + u32 L1_RCNR1_A1L_DARK_AG2;
> + u32 L1_RCNR1_A1L_RATIO_AG0;
> + u32 L1_RCNR1_A1L_RATIO_AG1;
> + u32 L1_RCNR1_A1L_RATIO_AG2;
> + u32 L1_RCNR1_INF_ZERO_CLIP;
> + u32 RESERVED_A_30;
> + u32 L1_RCNR1_MERGE_D2BLEND_AG0;
> + u32 L1_RCNR1_MERGE_D2BLEND_AG1;
> + u32 L1_RCNR1_MERGE_D2BLEND_AG2;
> + u32 L1_RCNR1_MERGE_BLACK;
> + u32 L1_RCNR1_MERGE_MINDIV;
> + u32 L1_RCNR1_HRY_TYPE;
> + u32 L1_RCNR1_ANF_BLEND_AG0;
> + u32 L1_RCNR1_ANF_BLEND_AG1;
> + u32 L1_RCNR1_ANF_BLEND_AG2;
> + u32 RESERVED_A_31;
> + u32 L1_RCNR1_LPF_THRESHOLD;
> + u32 L1_RCNR1_MERGE_HLBLEND_AG0;
> + u32 L1_RCNR1_MERGE_HLBLEND_AG1;
> + u32 L1_RCNR1_MERGE_HLBLEND_AG2;
> + u32 L1_RCNR1_GNR_SW;
> + u32 L1_RCNR1_GNR_RATIO;
> + u32 L1_RCNR1_GNR_WIDE_EN;
> + u32 L1_RCNR2_AG_CONT;
> + u32 RESERVED_A_32;
> + u32 L1_RCNR2_SW;
> + u32 L1_RCNR2_CNF_DARK_AG0;
> + u32 L1_RCNR2_CNF_DARK_AG1;
> + u32 L1_RCNR2_CNF_DARK_AG2;
> + u32 L1_RCNR2_CNF_RATIO_AG0;
> + u32 L1_RCNR2_CNF_RATIO_AG1;
> + u32 L1_RCNR2_CNF_RATIO_AG2;
> + u32 L1_RCNR2_CNF_CLIP_GAIN_R;
> + u32 L1_RCNR2_CNF_CLIP_GAIN_G;
> + u32 L1_RCNR2_CNF_CLIP_GAIN_B;
> + u32 L1_RCNR2_A1L_DARK_AG0;
> + u32 L1_RCNR2_A1L_DARK_AG1;
> + u32 L1_RCNR2_A1L_DARK_AG2;
> + u32 L1_RCNR2_A1L_RATIO_AG0;
> + u32 L1_RCNR2_A1L_RATIO_AG1;
> + u32 L1_RCNR2_A1L_RATIO_AG2;
> + u32 L1_RCNR2_INF_ZERO_CLIP;
> + u32 RESERVED_A_33;
> + u32 L1_RCNR2_MERGE_D2BLEND_AG0;
> + u32 L1_RCNR2_MERGE_D2BLEND_AG1;
> + u32 L1_RCNR2_MERGE_D2BLEND_AG2;
> + u32 L1_RCNR2_MERGE_BLACK;
> + u32 L1_RCNR2_MERGE_MINDIV;
> + u32 L1_RCNR2_HRY_TYPE;
> + u32 L1_RCNR2_ANF_BLEND_AG0;
> + u32 L1_RCNR2_ANF_BLEND_AG1;
> + u32 L1_RCNR2_ANF_BLEND_AG2;
> + u32 RESERVED_A_34;
> + u32 L1_RCNR2_LPF_THRESHOLD;
> + u32 L1_RCNR2_MERGE_HLBLEND_AG0;
> + u32 L1_RCNR2_MERGE_HLBLEND_AG1;
> + u32 L1_RCNR2_MERGE_HLBLEND_AG2;
> + u32 L1_RCNR2_GNR_SW;
> + u32 L1_RCNR2_GNR_RATIO;
> + u32 L1_RCNR2_GNR_WIDE_EN;
> + u32 RESERVED_B_9[49];
> + u32 RESERVED_A_35;
> + u32 L1_HDRS_HDRRATIO_M;
> + u32 L1_HDRS_HDRRATIO_L;
> + u32 L1_HDRS_HDRRATIO_E;
> + u32 RESERVED_A_36;
> + u32 RESERVED_A_37;
> + u32 L1_HDRS_BLENDEND_H;
> + u32 L1_HDRS_BLENDEND_M;
> + u32 L1_HDRS_BLENDEND_E;
> + u32 L1_HDRS_BLENDBEG_H;
> + u32 L1_HDRS_BLENDBEG_M;
> + u32 L1_HDRS_BLENDBEG_E;
> + u32 RESERVED_A_38;
> + u32 RESERVED_A_39;
> + u32 RESERVED_A_40;
> + u32 RESERVED_A_41;
> + u32 RESERVED_A_42;
> + u32 RESERVED_A_43;
> + u32 L1_HDRS_DG_H;
> + u32 L1_HDRS_DG_M;
> + u32 L1_HDRS_DG_L;
> + u32 L1_HDRS_DG_E;
> + u32 L1_HDRS_LEDMODE_ON;
> + u32 L1_HDRS_HDRMODE;
> + u32 RESERVED_A_44;
> + u32 RESERVED_A_45;
> + u32 RESERVED_A_46;
> + u32 L1_HDRS_DSTMAXVAL;
> + u32 RESERVED_B_10[4];
> + u32 L1_BLVC_SRCBLACKLEVEL_GR;
> + u32 L1_BLVC_SRCBLACKLEVEL_R;
> + u32 L1_BLVC_SRCBLACKLEVEL_B;
> + u32 L1_BLVC_SRCBLACKLEVELGB;
> + u32 L1_BLVC_MULTVAL_GR;
> + u32 L1_BLVC_MULTVAL_R;
> + u32 L1_BLVC_MULTVAL_B;
> + u32 L1_BLVC_MULTVAL_GB;
> + u32 L1_BLVC_DSTMAXVAL;
> + u32 RESERVED_A_47;
> + u32 RESERVED_A_48;
> + u32 RESERVED_A_49;
> + u32 RESERVED_A_50;
> + u32 RESERVED_A_51;
> + u32 RESERVED_A_52;
> + u32 RESERVED_B_11[17];
> + u32 L1_LSSC_EN;
> + u32 L1_LSSC_AG_CONT;
> + u32 RESERVED_A_53;
> + u32 RESERVED_A_54;
> + u32 L1_LSSC_PWHB_R_GAIN;
> + u32 L1_LSSC_PWHB_GR_GAIN;
> + u32 L1_LSSC_PWHB_GB_GAIN;
> + u32 L1_LSSC_PWHB_B_GAIN;
> + u32 L1_LSSC_PARA_EN;
> + u32 L1_LSSC_PARA_H_CENTER;
> + u32 L1_LSSC_PARA_V_CENTER;
> + u32 L1_LSSC_PARA_H_GAIN;
> + u32 L1_LSSC_PARA_V_GAIN;
> + u32 L1_LSSC_PARA_MGSEL2;
> + u32 L1_LSSC_PARA_MGSEL4;
> + u32 L1_LSSC_PARA_R_COEF_2D_H_L;
> + u32 L1_LSSC_PARA_R_COEF_2D_H_R;
> + u32 L1_LSSC_PARA_R_COEF_2D_V_U;
> + u32 L1_LSSC_PARA_R_COEF_2D_V_D;
> + u32 L1_LSSC_PARA_R_COEF_2D_HV_LU;
> + u32 L1_LSSC_PARA_R_COEF_2D_HV_RU;
> + u32 L1_LSSC_PARA_R_COEF_2D_HV_LD;
> + u32 L1_LSSC_PARA_R_COEF_2D_HV_RD;
> + u32 L1_LSSC_PARA_R_COEF_4D_H_L;
> + u32 L1_LSSC_PARA_R_COEF_4D_H_R;
> + u32 L1_LSSC_PARA_R_COEF_4D_V_U;
> + u32 L1_LSSC_PARA_R_COEF_4D_V_D;
> + u32 L1_LSSC_PARA_R_COEF_4D_HV_LU;
> + u32 L1_LSSC_PARA_R_COEF_4D_HV_RU;
> + u32 L1_LSSC_PARA_R_COEF_4D_HV_LD;
> + u32 L1_LSSC_PARA_R_COEF_4D_HV_RD;
> + u32 L1_LSSC_PARA_GR_COEF_2D_H_L;
> + u32 L1_LSSC_PARA_GR_COEF_2D_H_R;
> + u32 L1_LSSC_PARA_GR_COEF_2D_V_U;
> + u32 L1_LSSC_PARA_GR_COEF_2D_V_D;
> + u32 L1_LSSC_PARA_GR_COEF_2D_HV_LU;
> + u32 L1_LSSC_PARA_GR_COEF_2D_HV_RU;
> + u32 L1_LSSC_PARA_GR_COEF_2D_HV_LD;
> + u32 L1_LSSC_PARA_GR_COEF_2D_HV_RD;
> + u32 L1_LSSC_PARA_GR_COEF_4D_H_L;
> + u32 L1_LSSC_PARA_GR_COEF_4D_H_R;
> + u32 L1_LSSC_PARA_GR_COEF_4D_V_U;
> + u32 L1_LSSC_PARA_GR_COEF_4D_V_D;
> + u32 L1_LSSC_PARA_GR_COEF_4D_HV_LU;
> + u32 L1_LSSC_PARA_GR_COEF_4D_HV_RU;
> + u32 L1_LSSC_PARA_GR_COEF_4D_HV_LD;
> + u32 L1_LSSC_PARA_GR_COEF_4D_HV_RD;
> + u32 L1_LSSC_PARA_GB_COEF_2D_H_L;
> + u32 L1_LSSC_PARA_GB_COEF_2D_H_R;
> + u32 L1_LSSC_PARA_GB_COEF_2D_V_U;
> + u32 L1_LSSC_PARA_GB_COEF_2D_V_D;
> + u32 L1_LSSC_PARA_GB_COEF_2D_HV_LU;
> + u32 L1_LSSC_PARA_GB_COEF_2D_HV_RU;
> + u32 L1_LSSC_PARA_GB_COEF_2D_HV_LD;
> + u32 L1_LSSC_PARA_GB_COEF_2D_HV_RD;
> + u32 L1_LSSC_PARA_GB_COEF_4D_H_L;
> + u32 L1_LSSC_PARA_GB_COEF_4D_H_R;
> + u32 L1_LSSC_PARA_GB_COEF_4D_V_U;
> + u32 L1_LSSC_PARA_GB_COEF_4D_V_D;
> + u32 L1_LSSC_PARA_GB_COEF_4D_HV_LU;
> + u32 L1_LSSC_PARA_GB_COEF_4D_HV_RU;
> + u32 L1_LSSC_PARA_GB_COEF_4D_HV_LD;
> + u32 L1_LSSC_PARA_GB_COEF_4D_HV_RD;
> + u32 L1_LSSC_PARA_B_COEF_2D_H_L;
> + u32 L1_LSSC_PARA_B_COEF_2D_H_R;
> + u32 L1_LSSC_PARA_B_COEF_2D_V_U;
> + u32 L1_LSSC_PARA_B_COEF_2D_V_D;
> + u32 L1_LSSC_PARA_B_COEF_2D_HV_LU;
> + u32 L1_LSSC_PARA_B_COEF_2D_HV_RU;
> + u32 L1_LSSC_PARA_B_COEF_2D_HV_LD;
> + u32 L1_LSSC_PARA_B_COEF_2D_HV_RD;
> + u32 L1_LSSC_PARA_B_COEF_4D_H_L;
> + u32 L1_LSSC_PARA_B_COEF_4D_H_R;
> + u32 L1_LSSC_PARA_B_COEF_4D_V_U;
> + u32 L1_LSSC_PARA_B_COEF_4D_V_D;
> + u32 L1_LSSC_PARA_B_COEF_4D_HV_LU;
> + u32 L1_LSSC_PARA_B_COEF_4D_HV_RU;
> + u32 L1_LSSC_PARA_B_COEF_4D_HV_LD;
> + u32 L1_LSSC_PARA_B_COEF_4D_HV_RD;
> + u32 L1_LSSC_GRID_EN;
> + u32 L1_LSSC_GRID_H_CENTER;
> + u32 L1_LSSC_GRID_V_CENTER;
> + u32 L1_LSSC_GRID_H_SIZE;
> + u32 L1_LSSC_GRID_V_SIZE;
> + u32 L1_LSSC_GRID_MGSEL;
> + u32 RESERVED_B_12[11];
> + u32 L1_MPRO_SW;
> + u32 L1_MPRO_CONF;
> + u32 RESERVED_A_55;
> + u32 L1_MPRO_DST_MINVAL;
> + u32 L1_MPRO_DST_MAXVAL;
> + u32 L1_MPRO_AG_CONT;
> + u32 RESERVED_A_56;
> + u32 RESERVED_A_57;
> + u32 L1_MPRO_LM0_RMG_MIN;
> + u32 L1_MPRO_LM0_RMB_MIN;
> + u32 L1_MPRO_LM0_GMR_MIN;
> + u32 L1_MPRO_LM0_GMB_MIN;
> + u32 L1_MPRO_LM0_BMR_MIN;
> + u32 L1_MPRO_LM0_BMG_MIN;
> + u32 L1_MPRO_LM0_RMG_MAX;
> + u32 L1_MPRO_LM0_RMB_MAX;
> + u32 L1_MPRO_LM0_GMR_MAX;
> + u32 L1_MPRO_LM0_GMB_MAX;
> + u32 L1_MPRO_LM0_BMR_MAX;
> + u32 L1_MPRO_LM0_BMG_MAX;
> + u32 RESERVED_A_58;
> + u32 RESERVED_A_59;
> + u32 RESERVED_A_60;
> + u32 RESERVED_A_61;
> + u32 RESERVED_A_62;
> + u32 RESERVED_A_63;
> + u32 RESERVED_A_64;
> + u32 RESERVED_A_65;
> + u32 RESERVED_A_66;
> + u32 RESERVED_A_67;
> + u32 RESERVED_A_68;
> + u32 RESERVED_A_69;
> + u32 RESERVED_A_70;
> + u32 RESERVED_A_71;
> + u32 RESERVED_A_72;
> + u32 RESERVED_A_73;
> + u32 RESERVED_A_74;
> + u32 RESERVED_A_75;
> + u32 RESERVED_A_76;
> + u32 RESERVED_A_77;
> + u32 RESERVED_A_78;
> + u32 RESERVED_A_79;
> + u32 RESERVED_A_80;
> + u32 RESERVED_A_81;
> + u32 RESERVED_A_82;
> + u32 RESERVED_A_83;
> + u32 RESERVED_A_84;
> + u32 RESERVED_A_85;
> + u32 RESERVED_A_86;
> + u32 RESERVED_A_87;
> + u32 RESERVED_A_88;
> + u32 RESERVED_A_89;
> + u32 RESERVED_A_90;
> + u32 RESERVED_A_91;
> + u32 RESERVED_A_92;
> + u32 RESERVED_A_93;
> + u32 RESERVED_A_94;
> + u32 RESERVED_A_95;
> + u32 RESERVED_A_96;
> + u32 RESERVED_B_13[1];
> + u32 L1_MPRO_LCS_MODE;
> + u32 RESERVED_A_97;
> + u32 RESERVED_A_98;
> + u32 RESERVED_A_99;
> + u32 RESERVED_A_100;
> + u32 RESERVED_A_101;
> + u32 RESERVED_A_102;
> + u32 RESERVED_A_103;
> + u32 RESERVED_A_104;
> + u32 RESERVED_A_105;
> + u32 RESERVED_A_106;
> + u32 RESERVED_A_107;
> + u32 RESERVED_A_108;
> + u32 RESERVED_A_109;
> + u32 RESERVED_A_110;
> + u32 RESERVED_A_111;
> + u32 RESERVED_A_112;
> + u32 RESERVED_A_113;
> + u32 RESERVED_A_114;
> + u32 RESERVED_A_115;
> + u32 RESERVED_A_116;
> + u32 RESERVED_A_117;
> + u32 RESERVED_A_118;
> + u32 RESERVED_A_119;
> + u32 RESERVED_A_120;
> + u32 RESERVED_A_121;
> + u32 RESERVED_A_122;
> + u32 RESERVED_A_123;
> + u32 RESERVED_A_124;
> + u32 RESERVED_A_125;
> + u32 RESERVED_B_14[70];
> + u32 L1_VPRO_PGC_SW;
> + u32 RESERVED_A_126;
> + u32 L1_VPRO_YUVC_SW;
> + u32 L1_VPRO_YNR_SW;
> + u32 L1_VPRO_ETE_SW;
> + u32 L1_VPRO_CSUP_UVSUP_SW;
> + u32 L1_VPRO_CSUP_CORING_SW;
> + u32 L1_VPRO_BRIGHT_SW;
> + u32 L1_VPRO_LCNT_SW;
> + u32 L1_VPRO_NLCNT_SW;
> + u32 RESERVED_A_127;
> + u32 L1_VPRO_EDGE_SUP_SW;
> + u32 L1_VPRO_CNR_SW;
> + u32 L1_VPRO_AG_CONT;
> + u32 L1_VPRO_BLKADJ;
> + u32 L1_VPRO_GAM01P;
> + u32 L1_VPRO_GAM02P;
> + u32 L1_VPRO_GAM03P;
> + u32 L1_VPRO_GAM04P;
> + u32 L1_VPRO_GAM05P;
> + u32 L1_VPRO_GAM06P;
> + u32 L1_VPRO_GAM07P;
> + u32 L1_VPRO_GAM08P;
> + u32 L1_VPRO_GAM09P;
> + u32 L1_VPRO_GAM10P;
> + u32 L1_VPRO_GAM11P;
> + u32 L1_VPRO_GAM12P;
> + u32 L1_VPRO_GAM13P;
> + u32 L1_VPRO_GAM14P;
> + u32 L1_VPRO_GAM15P;
> + u32 L1_VPRO_GAM16P;
> + u32 L1_VPRO_GAM17P;
> + u32 L1_VPRO_GAM18P;
> + u32 L1_VPRO_GAM19P;
> + u32 L1_VPRO_GAM20P;
> + u32 L1_VPRO_GAM21P;
> + u32 L1_VPRO_GAM22P;
> + u32 L1_VPRO_GAM23P;
> + u32 L1_VPRO_GAM24P;
> + u32 L1_VPRO_GAM25P;
> + u32 L1_VPRO_GAM26P;
> + u32 L1_VPRO_GAM27P;
> + u32 L1_VPRO_GAM28P;
> + u32 L1_VPRO_GAM29P;
> + u32 L1_VPRO_GAM30P;
> + u32 L1_VPRO_GAM31P;
> + u32 L1_VPRO_GAM32P;
> + u32 L1_VPRO_GAM33P;
> + u32 L1_VPRO_GAM34P;
> + u32 L1_VPRO_GAM35P;
> + u32 L1_VPRO_GAM36P;
> + u32 L1_VPRO_GAM37P;
> + u32 L1_VPRO_GAM38P;
> + u32 L1_VPRO_GAM39P;
> + u32 L1_VPRO_GAM40P;
> + u32 L1_VPRO_GAM41P;
> + u32 L1_VPRO_GAM42P;
> + u32 L1_VPRO_GAM43P;
> + u32 L1_VPRO_GAM44P;
> + u32 L1_VPRO_CB_MAT;
> + u32 L1_VPRO_CR_MAT;
> + u32 L1_VPRO_BRIGHT;
> + u32 L1_VPRO_LCONT_LEV;
> + u32 L1_VPRO_BLK_KNEE;
> + u32 L1_VPRO_WHT_KNEE;
> + u32 L1_VPRO_BLK_CONT0;
> + u32 L1_VPRO_BLK_CONT1;
> + u32 L1_VPRO_BLK_CONT2;
> + u32 L1_VPRO_WHT_CONT0;
> + u32 L1_VPRO_WHT_CONT1;
> + u32 L1_VPRO_WHT_CONT2;
> + u32 RESERVED_A_128;
> + u32 RESERVED_A_129;
> + u32 RESERVED_A_130;
> + u32 RESERVED_A_131;
> + u32 RESERVED_A_132;
> + u32 RESERVED_A_133;
> + u32 L1_VPRO_YNR_GAIN_MIN;
> + u32 L1_VPRO_YNR_GAIN_MAX;
> + u32 L1_VPRO_YNR_LIM_MIN;
> + u32 L1_VPRO_YNR_LIM_MAX;
> + u32 L1_VPRO_ETE_GAIN_MIN;
> + u32 L1_VPRO_ETE_GAIN_MAX;
> + u32 L1_VPRO_ETE_LIM_MIN;
> + u32 L1_VPRO_ETE_LIM_MAX;
> + u32 L1_VPRO_ETE_CORING_MIN;
> + u32 L1_VPRO_ETE_CORING_MAX;
> + u32 L1_VPRO_CB_GAIN;
> + u32 L1_VPRO_CR_GAIN;
> + u32 L1_VPRO_CBR_MGAIN_MIN;
> + u32 L1_VPRO_CB_P_GAIN_MAX;
> + u32 L1_VPRO_CB_M_GAIN_MAX;
> + u32 L1_VPRO_CR_P_GAIN_MAX;
> + u32 L1_VPRO_CR_M_GAIN_MAX;
> + u32 L1_VPRO_CSUP_CORING_LV_MIN;
> + u32 L1_VPRO_CSUP_CORING_LV_MAX;
> + u32 L1_VPRO_CSUP_CORING_GAIN_MIN;
> + u32 L1_VPRO_CSUP_CORING_GAIN_MAX;
> + u32 L1_VPRO_CSUP_BK_SLV;
> + u32 L1_VPRO_CSUP_BK_MP;
> + u32 L1_VPRO_CSUP_BLACK;
> + u32 L1_VPRO_CSUP_WH_SLV;
> + u32 L1_VPRO_CSUP_WH_MP;
> + u32 L1_VPRO_CSUP_WHITE;
> + u32 L1_VPRO_EDGE_SUP_GAIN;
> + u32 L1_VPRO_EDGE_SUP_LIM;
> + u32 RESERVED_B_15[22];
> + u32 L1_AWHB_SW;
> + u32 RESERVED_A_134;
> + u32 L1_AWHB_WBMRG;
> + u32 L1_AWHB_WBMGG;
> + u32 L1_AWHB_WBMBG;
> + u32 L1_AWHB_GATE_CONF0;
> + u32 L1_AWHB_GATE_CONF1;
> + u32 L1_AWHB_AREA_HSIZE;
> + u32 L1_AWHB_AREA_VSIZE;
> + u32 L1_AWHB_AREA_HOFS;
> + u32 L1_AWHB_AREA_VOFS;
> + u32 L1_AWHB_AREA_MASKH;
> + u32 L1_AWHB_AREA_MASKL;
> + u32 L1_AWHB_SQ_CONF;
> + u32 L1_AWHB_YGATEH;
> + u32 L1_AWHB_YGATEL;
> + u32 RESERVED_A_135;
> + u32 RESERVED_A_136;
> + u32 L1_AWHB_BYCUT0P;
> + u32 L1_AWHB_BYCUT0N;
> + u32 L1_AWHB_RYCUT0P;
> + u32 L1_AWHB_RYCUT0N;
> + u32 L1_AWHB_RBCUT0H;
> + u32 L1_AWHB_RBCUT0L;
> + u32 RESERVED_A_137;
> + u32 RESERVED_A_138;
> + u32 RESERVED_A_139;
> + u32 RESERVED_A_140;
> + u32 RESERVED_A_141;
> + u32 RESERVED_A_142;
> + u32 L1_AWHB_BYCUT1H;
> + u32 L1_AWHB_BYCUT1L;
> + u32 L1_AWHB_RYCUT1H;
> + u32 L1_AWHB_RYCUT1L;
> + u32 L1_AWHB_BYCUT2H;
> + u32 L1_AWHB_BYCUT2L;
> + u32 L1_AWHB_RYCUT2H;
> + u32 L1_AWHB_RYCUT2L;
> + u32 L1_AWHB_BYCUT3H;
> + u32 L1_AWHB_BYCUT3L;
> + u32 L1_AWHB_RYCUT3H;
> + u32 L1_AWHB_RYCUT3L;
> + u32 L1_AWHB_AWBSFTU;
> + u32 L1_AWHB_AWBSFTV;
> + u32 L1_AWHB_AWBSPD;
> + u32 L1_AWHB_AWBULV;
> + u32 L1_AWHB_AWBVLV;
> + u32 L1_AWHB_AWBWAIT;
> + u32 L1_AWHB_AWBONDOT;
> + u32 L1_AWHB_AWBFZTIM;
> + u32 L1_AWHB_WBGRMAX;
> + u32 L1_AWHB_WBGRMIN;
> + u32 L1_AWHB_WBGBMAX;
> + u32 L1_AWHB_WBGBMIN;
> + u32 RESERVED_A_143;
> + u32 RESERVED_A_144;
> + u32 RESERVED_A_145;
> + u32 RESERVED_A_146;
> + u32 RESERVED_A_147;
> + u32 RESERVED_A_148;
> + u32 RESERVED_A_149;
> + u32 RESERVED_A_150;
> + u32 RESERVED_A_151;
> + u32 RESERVED_A_152;
> + u32 RESERVED_A_153;
> + u32 RESERVED_A_154;
> + u32 RESERVED_A_155;
> + u32 L1_AWHB_AVE_USIG;
> + u32 L1_AWHB_AVE_VSIG;
> + u32 L1_AWHB_NUM_UVON;
> + u32 L1_AWHB_AWBGAINR;
> + u32 L1_AWHB_AWBGAING;
> + u32 L1_AWHB_AWBGAINB;
> + u32 RESERVED_A_156;
> + u32 RESERVED_A_157;
> + u32 RESERVED_A_158;
> + u32 L1_AWHB_R_CTR_STOP;
> + u32 RESERVED_A_159;
> + u32 RESERVED_B_16[2];
> + u32 L1_HOBC_EN;
> + u32 L1_HOBC_MARGIN;
> + u32 L1_HOBC01_AG_CONT;
> + u32 L1_HOBC2_AG_CONT;
> + u32 L1_HOBC0_LOB_REFLV_GR;
> + u32 L1_HOBC0_LOB_WIDTH_GR;
> + u32 L1_HOBC0_LOB_REFLV_R;
> + u32 L1_HOBC0_LOB_WIDTH_R;
> + u32 L1_HOBC0_LOB_REFLV_B;
> + u32 L1_HOBC0_LOB_WIDTH_B;
> + u32 L1_HOBC0_LOB_REFLV_GB;
> + u32 L1_HOBC0_LOB_WIDTH_GB;
> + u32 L1_HOBC1_LOB_REFLV_GR;
> + u32 L1_HOBC1_LOB_WIDTH_GR;
> + u32 L1_HOBC1_LOB_REFLV_R;
> + u32 L1_HOBC1_LOB_WIDTH_R;
> + u32 L1_HOBC1_LOB_REFLV_B;
> + u32 L1_HOBC1_LOB_WIDTH_B;
> + u32 L1_HOBC1_LOB_REFLV_GB;
> + u32 L1_HOBC1_LOB_WIDTH_GB;
> + u32 L1_HOBC2_LOB_REFLV_GR;
> + u32 L1_HOBC2_LOB_WIDTH_GR;
> + u32 L1_HOBC2_LOB_REFLV_R;
> + u32 L1_HOBC2_LOB_WIDTH_R;
> + u32 L1_HOBC2_LOB_REFLV_B;
> + u32 L1_HOBC2_LOB_WIDTH_B;
> + u32 L1_HOBC2_LOB_REFLV_GB;
> + u32 L1_HOBC2_LOB_WIDTH_GB;
> + u32 L1_HOBC0_SRC_BLKLV_GR;
> + u32 L1_HOBC0_SRC_BLKLV_R;
> + u32 L1_HOBC0_SRC_BLKLV_B;
> + u32 L1_HOBC0_SRC_BLKLV_GB;
> + u32 L1_HOBC1_SRC_BLKLV_GR;
> + u32 L1_HOBC1_SRC_BLKLV_R;
> + u32 L1_HOBC1_SRC_BLKLV_B;
> + u32 L1_HOBC1_SRC_BLKLV_GB;
> + u32 L1_HOBC2_SRC_BLKLV_GR;
> + u32 L1_HOBC2_SRC_BLKLV_R;
> + u32 L1_HOBC2_SRC_BLKLV_B;
> + u32 L1_HOBC2_SRC_BLKLV_GB;
> + u32 RESERVED_A_160;
> + u32 RESERVED_A_161;
> + u32 RESERVED_A_162;
> + u32 RESERVED_A_163;
> + u32 RESERVED_A_164;
> + u32 RESERVED_A_165;
> + u32 L1_HOBC_MAX_VAL;
> + u32 RESERVED_B_17[33];
> + u32 L1_HDRC_EN;
> + u32 L1_HDRC_THR_SFT_AMT;
> + u32 RESERVED_A_166;
> + u32 L1_HDRC_RATIO;
> + u32 RESERVED_A_167;
> + u32 RESERVED_A_168;
> + u32 RESERVED_A_169;
> + u32 L1_HDRC_PT_RATIO;
> + u32 L1_HDRC_PT_BLEND;
> + u32 L1_HDRC_PT_BLEND2;
> + u32 L1_HDRC_PT_SAT;
> + u32 L1_HDRC_TN_TYPE;
> + u32 L1_HDRC_TNP_MAX;
> + u32 L1_HDRC_TNP_MAG;
> + u32 L1_HDRC_TNP_FB_SMTH_MAX0;
> + u32 L1_HDRC_TNP_FB_SMTH_MAX1;
> + u32 L1_HDRC_TNP_FB_SMTH_MAX2;
> + u32 L1_HDRC_TNP_FB_SMTH_MAX3;
> + u32 L1_HDRC_TNP_FIL0;
> + u32 L1_HDRC_TNP_FIL1;
> + u32 L1_HDRC_TNP_FIL2;
> + u32 L1_HDRC_TNP_FIL3;
> + u32 L1_HDRC_TNP_FIL4;
> + u32 L1_HDRC_UTN_TBL0;
> + u32 L1_HDRC_UTN_TBL1;
> + u32 L1_HDRC_UTN_TBL2;
> + u32 L1_HDRC_UTN_TBL3;
> + u32 L1_HDRC_UTN_TBL4;
> + u32 L1_HDRC_UTN_TBL5;
> + u32 L1_HDRC_UTN_TBL6;
> + u32 L1_HDRC_UTN_TBL7;
> + u32 L1_HDRC_UTN_TBL8;
> + u32 L1_HDRC_UTN_TBL9;
> + u32 L1_HDRC_UTN_TBL10;
> + u32 L1_HDRC_UTN_TBL11;
> + u32 L1_HDRC_UTN_TBL12;
> + u32 L1_HDRC_UTN_TBL13;
> + u32 L1_HDRC_UTN_TBL14;
> + u32 L1_HDRC_UTN_TBL15;
> + u32 L1_HDRC_UTN_TBL16;
> + u32 L1_HDRC_UTN_TBL17;
> + u32 L1_HDRC_UTN_TBL18;
> + u32 L1_HDRC_UTN_TBL19;
> + u32 L1_HDRC_FLR_VAL;
> + u32 L1_HDRC_FLR_ADP;
> + u32 RESERVED_A_170;
> + u32 RESERVED_A_171;
> + u32 RESERVED_A_172;
> + u32 RESERVED_A_173;
> + u32 RESERVED_A_174;
> + u32 RESERVED_A_175;
> + u32 RESERVED_A_176;
> + u32 RESERVED_A_177;
> + u32 RESERVED_A_178;
> + u32 RESERVED_A_179;
> + u32 RESERVED_A_180;
> + u32 RESERVED_A_181;
> + u32 RESERVED_A_182;
> + u32 RESERVED_A_183;
> + u32 L1_HDRC_YBR_OFF;
> + u32 L1_HDRC_ORGY_BLEND;
> + u32 RESERVED_A_184;
> + u32 RESERVED_A_185;
> + u32 RESERVED_A_186;
> + u32 L1_HDRC_MAR_TOP;
> + u32 L1_HDRC_MAR_LEFT;
> + u32 RESERVED_A_187;
> + u32 RESERVED_A_188;
> + u32 RESERVED_B_18[28];
> + u32 L1_HIST_EN;
> + u32 L1_HIST_MODE;
> + u32 L1_HIST_BLOCK_OFST;
> + u32 L1_HIST_BLOCK_SIZE;
> + u32 L1_HIST_BLOCK_NUM;
> + u32 L1_HIST_BLOCK_STEP;
> + u32 L1_HIST_LINEAR_SFT;
> + u32 L1_HIST_MULT_A_R;
> + u32 L1_HIST_ADD_A_R;
> + u32 L1_HIST_MULT_B_R;
> + u32 L1_HIST_ADD_B_R;
> + u32 L1_HIST_MULT_A_G;
> + u32 L1_HIST_ADD_A_G;
> + u32 L1_HIST_MULT_B_G;
> + u32 L1_HIST_ADD_B_G;
> + u32 L1_HIST_MULT_A_B;
> + u32 L1_HIST_ADD_A_B;
> + u32 L1_HIST_MULT_B_B;
> + u32 L1_HIST_ADD_B_B;
> + u32 L1_HIST_MULT_A_Y;
> + u32 L1_HIST_ADD_A_Y;
> + u32 L1_HIST_MULT_B_Y;
> + u32 L1_HIST_ADD_B_Y;
> + u32 RESERVED_B_19[201];
> + u32 L1_CRGBF_ACC_CONF;
> + u32 L1_CRGBF_TRN_M_RUN;
> + u32 L1_CRGBF_TRN_M_CONF;
> + u32 L1_CRGBF_TRN_A_CONF;
> + u32 L1_CRGBF_TRN_STAT_CLR;
> + u32 L1_CRGBF_TRN_STAT;
> + u32 L1_CRGBF_INT_STAT;
> + u32 L1_CRGBF_INT_MASK;
> + u32 L1_CRGBF_INT_MASKED_STAT;
> + u32 L1_CRGBF_TRN_WBADDR;
> + u32 L1_CRGBF_TRN_WEADDR;
> + u32 L1_CRGBF_TRN_RBADDR;
> + u32 L1_CRGBF_TRN_READDR;
> + u32 L1_CRGBF_ISP_INT;
> + u32 L1_CRGBF_ISP_INT_MASK;
> + u32 L1_CRGBF_ISP_INT_MASKED_STAT;
> + u32 RESERVED_A_189;
> + u32 RESERVED_B_20[47];
> + u32 L1_VLATCH_SYSM_WIDTH;
> + u32 L1_VLATCH_SYSM_HEIGHT;
> + u32 L1_VLATCH_SYSM_START_COLOR;
> + u32 L1_VLATCH_SYSM_INPUT_MODE;
> + u32 RESERVED_A_190;
> + u32 L1_VLATCH_SYSM_YCOEF_R;
> + u32 L1_VLATCH_SYSM_YCOEF_G;
> + u32 L1_VLATCH_SYSM_YCOEF_B;
> + u32 RESERVED_A_191;
> + u32 RESERVED_A_192;
> + u32 RESERVED_A_193;
> + u32 RESERVED_A_194;
> + u32 RESERVED_A_195;
> + u32 RESERVED_A_196;
> + u32 RESERVED_B_21[2];
> + u32 L1_VLATCH_SYSM_AG_H;
> + u32 L1_VLATCH_SYSM_AG_M;
> + u32 L1_VLATCH_SYSM_AG_L;
> + u32 L1_VLATCH_SYSM_AG_PARAM_A;
> + u32 L1_VLATCH_SYSM_AG_PARAM_B;
> + u32 L1_VLATCH_SYSM_AG_PARAM_C;
> + u32 L1_VLATCH_SYSM_AG_PARAM_D;
> + u32 L1_VLATCH_SYSM_AG_SEL_HOBC;
> + u32 L1_VLATCH_SYSM_AG_SEL_ABPC;
> + u32 L1_VLATCH_SYSM_AG_SEL_RCNR;
> + u32 L1_VLATCH_SYSM_AG_SEL_LSSC;
> + u32 L1_VLATCH_SYSM_AG_SEL_MPRO;
> + u32 L1_VLATCH_SYSM_AG_SEL_VPRO;
> + u32 L1_VLATCH_SYSM_AG_CONT_HOBC01_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_HOBC2_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_ABPC01_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_ABPC2_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_RCNR01_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_RCNR2_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_LSSC_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_MPRO_EN;
> + u32 L1_VLATCH_SYSM_AG_CONT_VPRO_EN;
> + u32 RESERVED_A_197;
> + u32 L1_VLATCH_SYSM_MAN_CTXT;
> + u32 RESERVED_A_198;
> + u32 RESERVED_B_22[7];
> + u32 RESERVED_A_199;
> + u32 L1_VLATCH_HDRE_SRCPOINT00;
> + u32 L1_VLATCH_HDRE_SRCPOINT01;
> + u32 L1_VLATCH_HDRE_SRCPOINT02;
> + u32 L1_VLATCH_HDRE_SRCPOINT03;
> + u32 L1_VLATCH_HDRE_SRCPOINT04;
> + u32 L1_VLATCH_HDRE_SRCPOINT05;
> + u32 L1_VLATCH_HDRE_SRCPOINT06;
> + u32 L1_VLATCH_HDRE_SRCPOINT07;
> + u32 L1_VLATCH_HDRE_SRCPOINT08;
> + u32 L1_VLATCH_HDRE_SRCPOINT09;
> + u32 L1_VLATCH_HDRE_SRCPOINT10;
> + u32 L1_VLATCH_HDRE_SRCPOINT11;
> + u32 L1_VLATCH_HDRE_SRCPOINT12;
> + u32 L1_VLATCH_HDRE_SRCPOINT13;
> + u32 L1_VLATCH_HDRE_SRCPOINT14;
> + u32 L1_VLATCH_HDRE_SRCPOINT15;
> + u32 L1_VLATCH_HDRE_SRCBASE00;
> + u32 L1_VLATCH_HDRE_SRCBASE01;
> + u32 L1_VLATCH_HDRE_SRCBASE02;
> + u32 L1_VLATCH_HDRE_SRCBASE03;
> + u32 L1_VLATCH_HDRE_SRCBASE04;
> + u32 L1_VLATCH_HDRE_SRCBASE05;
> + u32 L1_VLATCH_HDRE_SRCBASE06;
> + u32 L1_VLATCH_HDRE_SRCBASE07;
> + u32 L1_VLATCH_HDRE_SRCBASE08;
> + u32 L1_VLATCH_HDRE_SRCBASE09;
> + u32 L1_VLATCH_HDRE_SRCBASE10;
> + u32 L1_VLATCH_HDRE_SRCBASE11;
> + u32 L1_VLATCH_HDRE_SRCBASE12;
> + u32 L1_VLATCH_HDRE_SRCBASE13;
> + u32 L1_VLATCH_HDRE_SRCBASE14;
> + u32 L1_VLATCH_HDRE_SRCBASE15;
> + u32 L1_VLATCH_HDRE_SRCBASE16;
> + u32 L1_VLATCH_HDRE_RATIO00;
> + u32 L1_VLATCH_HDRE_RATIO01;
> + u32 L1_VLATCH_HDRE_RATIO02;
> + u32 L1_VLATCH_HDRE_RATIO03;
> + u32 L1_VLATCH_HDRE_RATIO04;
> + u32 L1_VLATCH_HDRE_RATIO05;
> + u32 L1_VLATCH_HDRE_RATIO06;
> + u32 L1_VLATCH_HDRE_RATIO07;
> + u32 L1_VLATCH_HDRE_RATIO08;
> + u32 L1_VLATCH_HDRE_RATIO09;
> + u32 L1_VLATCH_HDRE_RATIO10;
> + u32 L1_VLATCH_HDRE_RATIO11;
> + u32 L1_VLATCH_HDRE_RATIO12;
> + u32 L1_VLATCH_HDRE_RATIO13;
> + u32 L1_VLATCH_HDRE_RATIO14;
> + u32 L1_VLATCH_HDRE_RATIO15;
> + u32 L1_VLATCH_HDRE_RATIO16;
> + u32 L1_VLATCH_HDRE_DSTBASE00;
> + u32 L1_VLATCH_HDRE_DSTBASE01;
> + u32 L1_VLATCH_HDRE_DSTBASE02;
> + u32 L1_VLATCH_HDRE_DSTBASE03;
> + u32 L1_VLATCH_HDRE_DSTBASE04;
> + u32 L1_VLATCH_HDRE_DSTBASE05;
> + u32 L1_VLATCH_HDRE_DSTBASE06;
> + u32 L1_VLATCH_HDRE_DSTBASE07;
> + u32 L1_VLATCH_HDRE_DSTBASE08;
> + u32 L1_VLATCH_HDRE_DSTBASE09;
> + u32 L1_VLATCH_HDRE_DSTBASE10;
> + u32 L1_VLATCH_HDRE_DSTBASE11;
> + u32 L1_VLATCH_HDRE_DSTBASE12;
> + u32 L1_VLATCH_HDRE_DSTBASE13;
> + u32 L1_VLATCH_HDRE_DSTBASE14;
> + u32 L1_VLATCH_HDRE_DSTBASE15;
> + u32 L1_VLATCH_HDRE_DSTBASE16;
> + u32 L1_VLATCH_HDRE_DSTMAXVAL;
> + u32 RESERVED_B_23[11];
> + u32 L1_VLATCH_AEXP_ON;
> + u32 RESERVED_A_200;
> + u32 RESERVED_A_201;
> + u32 L1_VLATCH_AEXP_FORCE_INTERRUPT_Y;
> + u32 L1_VLATCH_AEXP_START_X;
> + u32 L1_VLATCH_AEXP_START_Y;
> + u32 L1_VLATCH_AEXP_BLOCK_WIDTH;
> + u32 L1_VLATCH_AEXP_BLOCK_HEIGHT;
> + u32 L1_VLATCH_AEXP_WEIGHT_0;
> + u32 L1_VLATCH_AEXP_WEIGHT_1;
> + u32 L1_VLATCH_AEXP_WEIGHT_2;
> + u32 L1_VLATCH_AEXP_WEIGHT_3;
> + u32 L1_VLATCH_AEXP_WEIGHT_4;
> + u32 L1_VLATCH_AEXP_WEIGHT_5;
> + u32 L1_VLATCH_AEXP_WEIGHT_6;
> + u32 L1_VLATCH_AEXP_WEIGHT_7;
> + u32 L1_VLATCH_AEXP_SATUR_RATIO;
> + u32 L1_VLATCH_AEXP_BLACK_RATIO;
> + u32 L1_VLATCH_AEXP_SATUR_LEVEL;
> + u32 RESERVED_A_202;
> + u32 RESERVED_A_203;
> + u32 RESERVED_A_204;
> + u32 RESERVED_A_205;
> + u32 RESERVED_A_206;
> + u32 RESERVED_A_207;
> + u32 RESERVED_A_208;
> + u32 RESERVED_A_209;
> + u32 RESERVED_A_210;
> + u32 RESERVED_A_211;
> + u32 RESERVED_A_212;
> + u32 RESERVED_A_213;
> + u32 RESERVED_A_214;
> + u32 RESERVED_A_215;
> + u32 RESERVED_A_216;
> + u32 RESERVED_A_217;
> + u32 RESERVED_A_218;
> + u32 RESERVED_A_219;
> + u32 RESERVED_A_220;
> + u32 RESERVED_A_221;
> + u32 RESERVED_A_222;
> + u32 RESERVED_A_223;
> + u32 RESERVED_A_224;
> + u32 RESERVED_A_225;
> + u32 RESERVED_A_226;
> + u32 RESERVED_A_227;
> + u32 RESERVED_A_228;
> + u32 RESERVED_A_229;
> + u32 RESERVED_A_230;
> + u32 RESERVED_A_231;
> + u32 RESERVED_A_232;
> + u32 RESERVED_A_233;
> + u32 RESERVED_A_234;
> + u32 RESERVED_A_235;
> + u32 RESERVED_A_236;
> + u32 RESERVED_A_237;
> + u32 RESERVED_A_238;
> + u32 RESERVED_A_239;
> + u32 RESERVED_A_240;
> + u32 RESERVED_A_241;
> + u32 RESERVED_A_242;
> + u32 RESERVED_A_243;
> + u32 RESERVED_A_244;
> + u32 RESERVED_A_245;
> + u32 RESERVED_A_246;
> + u32 RESERVED_A_247;
> + u32 RESERVED_A_248;
> + u32 RESERVED_A_249;
> + u32 RESERVED_A_250;
> + u32 RESERVED_A_251;
> + u32 RESERVED_A_252;
> + u32 RESERVED_A_253;
> + u32 RESERVED_A_254;
> + u32 RESERVED_A_255;
> + u32 RESERVED_A_256;
> + u32 RESERVED_A_257;
> + u32 RESERVED_A_258;
> + u32 RESERVED_A_259;
> + u32 RESERVED_A_260;
> + u32 RESERVED_A_261;
> + u32 RESERVED_A_262;
> + u32 RESERVED_A_263;
> + u32 RESERVED_A_264;
> + u32 RESERVED_A_265;
> + u32 RESERVED_A_266;
> + u32 RESERVED_A_267;
> + u32 L1_VLATCH_AEXP_AVE4LINESY0;
> + u32 L1_VLATCH_AEXP_AVE4LINESY1;
> + u32 L1_VLATCH_AEXP_AVE4LINESY2;
> + u32 L1_VLATCH_AEXP_AVE4LINESY3;
> + u32 RESERVED_A_268;
> + u32 RESERVED_A_269;
> + u32 RESERVED_A_270;
> + u32 RESERVED_A_271;
> + u32 RESERVED_B_24[3];
> + u32 L1_VLATCH_IBUF_DEPTH;
> + u32 L1_VLATCH_IBUF_INPUT_ORDER;
> + u32 RESERVED_B_25[2];
> + u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_GR;
> + u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_R;
> + u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_B;
> + u32 L1_VLATCH_SLIC_SRCBLACKLEVEL_GB;
> + u32 RESERVED_A_272;
> + u32 RESERVED_A_273;
> + u32 RESERVED_A_274;
> + u32 RESERVED_A_275;
> + u32 RESERVED_A_276;
> + u32 RESERVED_B_26[19];
> + u32 RESERVED_A_277;
> + u32 RESERVED_A_278;
> + u32 RESERVED_A_279;
> + u32 L1_VLATCH_ABPC012_STA_EN;
> + u32 L1_VLATCH_ABPC012_DYN_EN;
> + u32 L1_VLATCH_ABPC012_DYN_MODE;
> + u32 RESERVED_A_280;
> + u32 RESERVED_A_281;
> + u32 RESERVED_A_282;
> + u32 L1_VLATCH_ABPC0_RATIO_LIMIT;
> + u32 RESERVED_A_283;
> + u32 L1_VLATCH_ABPC0_DARK_LIMIT;
> + u32 L1_VLATCH_ABPC0_SN_COEF_W_AG_MIN;
> + u32 L1_VLATCH_ABPC0_SN_COEF_W_AG_MID;
> + u32 L1_VLATCH_ABPC0_SN_COEF_W_AG_MAX;
> + u32 L1_VLATCH_ABPC0_SN_COEF_W_TH_MIN;
> + u32 L1_VLATCH_ABPC0_SN_COEF_W_TH_MAX;
> + u32 L1_VLATCH_ABPC0_SN_COEF_B_AG_MIN;
> + u32 L1_VLATCH_ABPC0_SN_COEF_B_AG_MID;
> + u32 L1_VLATCH_ABPC0_SN_COEF_B_AG_MAX;
> + u32 L1_VLATCH_ABPC0_SN_COEF_B_TH_MIN;
> + u32 L1_VLATCH_ABPC0_SN_COEF_B_TH_MAX;
> + u32 RESERVED_A_284;
> + u32 RESERVED_A_285;
> + u32 L1_VLATCH_ABPC1_RATIO_LIMIT;
> + u32 RESERVED_A_286;
> + u32 L1_VLATCH_ABPC1_DARK_LIMIT;
> + u32 L1_VLATCH_ABPC1_SN_COEF_W_AG_MIN;
> + u32 L1_VLATCH_ABPC1_SN_COEF_W_AG_MID;
> + u32 L1_VLATCH_ABPC1_SN_COEF_W_AG_MAX;
> + u32 L1_VLATCH_ABPC1_SN_COEF_W_TH_MIN;
> + u32 L1_VLATCH_ABPC1_SN_COEF_W_TH_MAX;
> + u32 L1_VLATCH_ABPC1_SN_COEF_B_AG_MIN;
> + u32 L1_VLATCH_ABPC1_SN_COEF_B_AG_MID;
> + u32 L1_VLATCH_ABPC1_SN_COEF_B_AG_MAX;
> + u32 L1_VLATCH_ABPC1_SN_COEF_B_TH_MIN;
> + u32 L1_VLATCH_ABPC1_SN_COEF_B_TH_MAX;
> + u32 RESERVED_A_287;
> + u32 RESERVED_A_288;
> + u32 L1_VLATCH_ABPC2_RATIO_LIMIT;
> + u32 RESERVED_A_289;
> + u32 L1_VLATCH_ABPC2_DARK_LIMIT;
> + u32 L1_VLATCH_ABPC2_SN_COEF_W_AG_MIN;
> + u32 L1_VLATCH_ABPC2_SN_COEF_W_AG_MID;
> + u32 L1_VLATCH_ABPC2_SN_COEF_W_AG_MAX;
> + u32 L1_VLATCH_ABPC2_SN_COEF_W_TH_MIN;
> + u32 L1_VLATCH_ABPC2_SN_COEF_W_TH_MAX;
> + u32 L1_VLATCH_ABPC2_SN_COEF_B_AG_MIN;
> + u32 L1_VLATCH_ABPC2_SN_COEF_B_AG_MID;
> + u32 L1_VLATCH_ABPC2_SN_COEF_B_AG_MAX;
> + u32 L1_VLATCH_ABPC2_SN_COEF_B_TH_MIN;
> + u32 L1_VLATCH_ABPC2_SN_COEF_B_TH_MAX;
> + u32 RESERVED_A_290;
> + u32 RESERVED_A_291;
> + u32 RESERVED_B_27[42];
> + u32 RESERVED_A_292;
> + u32 L1_VLATCH_PWHB_H_GR;
> + u32 L1_VLATCH_PWHB_HR;
> + u32 L1_VLATCH_PWHB_HB;
> + u32 L1_VLATCH_PWHB_H_GB;
> + u32 L1_VLATCH_PWHB_M_GR;
> + u32 L1_VLATCH_PWHB_MR;
> + u32 L1_VLATCH_PWHB_MB;
> + u32 L1_VLATCH_PWHB_M_GB;
> + u32 L1_VLATCH_PWHB_L_GR;
> + u32 L1_VLATCH_PWHB_LR;
> + u32 L1_VLATCH_PWHB_LB;
> + u32 L1_VLATCH_PWHB_L_GB;
> + u32 L1_VLATCH_PWHB_DSTMAXVAL;
> + u32 RESERVED_B_28[18];
> + u32 RESERVED_A_293;
> + u32 RESERVED_A_294;
> + u32 L1_VLATCH_RCNR0_SW;
> + u32 L1_VLATCH_RCNR0_CNF_DARK_AG0;
> + u32 L1_VLATCH_RCNR0_CNF_DARK_AG1;
> + u32 L1_VLATCH_RCNR0_CNF_DARK_AG2;
> + u32 L1_VLATCH_RCNR0_CNF_RATIO_AG0;
> + u32 L1_VLATCH_RCNR0_CNF_RATIO_AG1;
> + u32 L1_VLATCH_RCNR0_CNF_RATIO_AG2;
> + u32 L1_VLATCH_RCNR0_CNF_CLIP_GAIN_R;
> + u32 L1_VLATCH_RCNR0_CNF_CLIP_GAIN_G;
> + u32 L1_VLATCH_RCNR0_CNF_CLIP_GAIN_B;
> + u32 L1_VLATCH_RCNR0_A1L_DARK_AG0;
> + u32 L1_VLATCH_RCNR0_A1L_DARK_AG1;
> + u32 L1_VLATCH_RCNR0_A1L_DARK_AG2;
> + u32 L1_VLATCH_RCNR0_A1L_RATIO_AG0;
> + u32 L1_VLATCH_RCNR0_A1L_RATIO_AG1;
> + u32 L1_VLATCH_RCNR0_A1L_RATIO_AG2;
> + u32 L1_VLATCH_RCNR0_INF_ZERO_CLIP;
> + u32 RESERVED_A_295;
> + u32 L1_VLATCH_RCNR0_MERGE_D2BLEND_AG0;
> + u32 L1_VLATCH_RCNR0_MERGE_D2BLEND_AG1;
> + u32 L1_VLATCH_RCNR0_MERGE_D2BLEND_AG2;
> + u32 L1_VLATCH_RCNR0_MERGE_BLACK;
> + u32 L1_VLATCH_RCNR0_MERGE_MINDIV;
> + u32 L1_VLATCH_RCNR0_HRY_TYPE;
> + u32 L1_VLATCH_RCNR0_ANF_BLEND_AG0;
> + u32 L1_VLATCH_RCNR0_ANF_BLEND_AG1;
> + u32 L1_VLATCH_RCNR0_ANF_BLEND_AG2;
> + u32 RESERVED_A_296;
> + u32 L1_VLATCH_RCNR0_LPF_THRESHOLD;
> + u32 L1_VLATCH_RCNR0_MERGE_HLBLEND_AG0;
> + u32 L1_VLATCH_RCNR0_MERGE_HLBLEND_AG1;
> + u32 L1_VLATCH_RCNR0_MERGE_HLBLEND_AG2;
> + u32 L1_VLATCH_RCNR0_GNR_SW;
> + u32 L1_VLATCH_RCNR0_GNR_RATIO;
> + u32 L1_VLATCH_RCNR0_GNR_WIDE_EN;
> + u32 RESERVED_A_297;
> + u32 RESERVED_A_298;
> + u32 L1_VLATCH_RCNR1_SW;
> + u32 L1_VLATCH_RCNR1_CNF_DARK_AG0;
> + u32 L1_VLATCH_RCNR1_CNF_DARK_AG1;
> + u32 L1_VLATCH_RCNR1_CNF_DARK_AG2;
> + u32 L1_VLATCH_RCNR1_CNF_RATIO_AG0;
> + u32 L1_VLATCH_RCNR1_CNF_RATIO_AG1;
> + u32 L1_VLATCH_RCNR1_CNF_RATIO_AG2;
> + u32 L1_VLATCH_RCNR1_CNF_CLIP_GAIN_R;
> + u32 L1_VLATCH_RCNR1_CNF_CLIP_GAIN_G;
> + u32 L1_VLATCH_RCNR1_CNF_CLIP_GAIN_B;
> + u32 L1_VLATCH_RCNR1_A1L_DARK_AG0;
> + u32 L1_VLATCH_RCNR1_A1L_DARK_AG1;
> + u32 L1_VLATCH_RCNR1_A1L_DARK_AG2;
> + u32 L1_VLATCH_RCNR1_A1L_RATIO_AG0;
> + u32 L1_VLATCH_RCNR1_A1L_RATIO_AG1;
> + u32 L1_VLATCH_RCNR1_A1L_RATIO_AG2;
> + u32 L1_VLATCH_RCNR1_INF_ZERO_CLIP;
> + u32 RESERVED_A_299;
> + u32 L1_VLATCH_RCNR1_MERGE_D2BLEND_AG0;
> + u32 L1_VLATCH_RCNR1_MERGE_D2BLEND_AG1;
> + u32 L1_VLATCH_RCNR1_MERGE_D2BLEND_AG2;
> + u32 L1_VLATCH_RCNR1_MERGE_BLACK;
> + u32 L1_VLATCH_RCNR1_MERGE_MINDIV;
> + u32 L1_VLATCH_RCNR1_HRY_TYPE;
> + u32 L1_VLATCH_RCNR1_ANF_BLEND_AG0;
> + u32 L1_VLATCH_RCNR1_ANF_BLEND_AG1;
> + u32 L1_VLATCH_RCNR1_ANF_BLEND_AG2;
> + u32 RESERVED_A_300;
> + u32 L1_VLATCH_RCNR1_LPF_THRESHOLD;
> + u32 L1_VLATCH_RCNR1_MERGE_HLBLEND_AG0;
> + u32 L1_VLATCH_RCNR1_MERGE_HLBLEND_AG1;
> + u32 L1_VLATCH_RCNR1_MERGE_HLBLEND_AG2;
> + u32 L1_VLATCH_RCNR1_GNR_SW;
> + u32 L1_VLATCH_RCNR1_GNR_RATIO;
> + u32 L1_VLATCH_RCNR1_GNR_WIDE_EN;
> + u32 RESERVED_A_301;
> + u32 RESERVED_A_302;
> + u32 L1_VLATCH_RCNR2_SW;
> + u32 L1_VLATCH_RCNR2_CNF_DARK_AG0;
> + u32 L1_VLATCH_RCNR2_CNF_DARK_AG1;
> + u32 L1_VLATCH_RCNR2_CNF_DARK_AG2;
> + u32 L1_VLATCH_RCNR2_CNF_RATIO_AG0;
> + u32 L1_VLATCH_RCNR2_CNF_RATIO_AG1;
> + u32 L1_VLATCH_RCNR2_CNF_RATIO_AG2;
> + u32 L1_VLATCH_RCNR2_CNF_CLIP_GAIN_R;
> + u32 L1_VLATCH_RCNR2_CNF_CLIP_GAIN_G;
> + u32 L1_VLATCH_RCNR2_CNF_CLIP_GAIN_B;
> + u32 L1_VLATCH_RCNR2_A1L_DARK_AG0;
> + u32 L1_VLATCH_RCNR2_A1L_DARK_AG1;
> + u32 L1_VLATCH_RCNR2_A1L_DARK_AG2;
> + u32 L1_VLATCH_RCNR2_A1L_RATIO_AG0;
> + u32 L1_VLATCH_RCNR2_A1L_RATIO_AG1;
> + u32 L1_VLATCH_RCNR2_A1L_RATIO_AG2;
> + u32 L1_VLATCH_RCNR2_INF_ZERO_CLIP;
> + u32 RESERVED_A_303;
> + u32 L1_VLATCH_RCNR2_MERGE_D2BLEND_AG0;
> + u32 L1_VLATCH_RCNR2_MERGE_D2BLEND_AG1;
> + u32 L1_VLATCH_RCNR2_MERGE_D2BLEND_AG2;
> + u32 L1_VLATCH_RCNR2_MERGE_BLACK;
> + u32 L1_VLATCH_RCNR2_MERGE_MINDIV;
> + u32 L1_VLATCH_RCNR2_HRY_TYPE;
> + u32 L1_VLATCH_RCNR2_ANF_BLEND_AG0;
> + u32 L1_VLATCH_RCNR2_ANF_BLEND_AG1;
> + u32 L1_VLATCH_RCNR2_ANF_BLEND_AG2;
> + u32 RESERVED_A_304;
> + u32 L1_VLATCH_RCNR2_LPF_THRESHOLD;
> + u32 L1_VLATCH_RCNR2_MERGE_HLBLEND_AG0;
> + u32 L1_VLATCH_RCNR2_MERGE_HLBLEND_AG1;
> + u32 L1_VLATCH_RCNR2_MERGE_HLBLEND_AG2;
> + u32 L1_VLATCH_RCNR2_GNR_SW;
> + u32 L1_VLATCH_RCNR2_GNR_RATIO;
> + u32 L1_VLATCH_RCNR2_GNR_WIDE_EN;
> + u32 RESERVED_B_29[49];
> + u32 RESERVED_A_305;
> + u32 L1_VLATCH_HDRS_HDRRATIO_M;
> + u32 L1_VLATCH_HDRS_HDRRATIO_L;
> + u32 L1_VLATCH_HDRS_HDRRATIO_E;
> + u32 RESERVED_A_306;
> + u32 RESERVED_A_307;
> + u32 L1_VLATCH_HDRS_BLENDEND_H;
> + u32 L1_VLATCH_HDRS_BLENDEND_M;
> + u32 L1_VLATCH_HDRS_BLENDEND_E;
> + u32 L1_VLATCH_HDRS_BLENDBEG_H;
> + u32 L1_VLATCH_HDRS_BLENDBEG_M;
> + u32 L1_VLATCH_HDRS_BLENDBEG_E;
> + u32 RESERVED_A_308;
> + u32 RESERVED_A_309;
> + u32 RESERVED_A_310;
> + u32 RESERVED_A_311;
> + u32 RESERVED_A_312;
> + u32 RESERVED_A_313;
> + u32 L1_VLATCH_HDRS_DgH;
> + u32 L1_VLATCH_HDRS_DgM;
> + u32 L1_VLATCH_HDRS_DgL;
> + u32 L1_VLATCH_HDRS_DgE;
> + u32 L1_VLATCH_HDRS_LEDMODE_ON;
> + u32 L1_VLATCH_HDRS_HDRMODE;
> + u32 RESERVED_A_314;
> + u32 RESERVED_A_315;
> + u32 RESERVED_A_316;
> + u32 L1_VLATCH_HDRS_DSTMAXVAL;
> + u32 RESERVED_B_30[4];
> + u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_GR;
> + u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_R;
> + u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_B;
> + u32 L1_VLATCH_BLVC_SRCBLACKLEVEL_GB;
> + u32 L1_VLATCH_BLVC_MULTVAL_GR;
> + u32 L1_VLATCH_BLVC_MULTVALR;
> + u32 L1_VLATCH_BLVC_MULTVALB;
> + u32 L1_VLATCH_BLVC_MULTVAL_GB;
> + u32 L1_VLATCH_BLVC_DSTMAXVAL;
> + u32 RESERVED_A_317;
> + u32 RESERVED_A_318;
> + u32 RESERVED_A_319;
> + u32 RESERVED_A_320;
> + u32 RESERVED_A_321;
> + u32 RESERVED_A_322;
> + u32 RESERVED_B_31[17];
> + u32 L1_VLATCH_LSSC_EN;
> + u32 RESERVED_A_323;
> + u32 RESERVED_A_324;
> + u32 RESERVED_A_325;
> + u32 L1_VLATCH_LSSC_PWHB_R_GAIN;
> + u32 L1_VLATCH_LSSC_PWHB_GR_GAIN;
> + u32 L1_VLATCH_LSSC_PWHB_GB_GAIN;
> + u32 L1_VLATCH_LSSC_PWHB_B_GAIN;
> + u32 L1_VLATCH_LSSC_PARA_EN;
> + u32 L1_VLATCH_LSSC_PARA_H_CENTER;
> + u32 L1_VLATCH_LSSC_PARA_V_CENTER;
> + u32 L1_VLATCH_LSSC_PARA_H_GAIN;
> + u32 L1_VLATCH_LSSC_PARA_V_GAIN;
> + u32 L1_VLATCH_LSSC_PARA_MGSEL2;
> + u32 L1_VLATCH_LSSC_PARA_MGSEL4;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_2D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_R_COEF_4D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_2D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_GR_COEF_4D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_2D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_GB_COEF_4D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_2D_HV_RD;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_H_L;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_H_R;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_V_U;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_V_D;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_LU;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_RU;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_LD;
> + u32 L1_VLATCH_LSSC_PARA_B_COEF_4D_HV_RD;
> + u32 L1_VLATCH_LSSC_GRID_EN;
> + u32 L1_VLATCH_LSSC_GRID_H_CENTER;
> + u32 L1_VLATCH_LSSC_GRID_V_CENTER;
> + u32 L1_VLATCH_LSSC_GRID_H_SIZE;
> + u32 L1_VLATCH_LSSC_GRID_V_SIZE;
> + u32 L1_VLATCH_LSSC_GRID_MGSEL;
> + u32 RESERVED_B_32[11];
> + u32 L1_VLATCH_MPRO_SW;
> + u32 L1_VLATCH_MPRO_CONF;
> + u32 RESERVED_A_326;
> + u32 L1_VLATCH_MPRO_DST_MINVAL;
> + u32 L1_VLATCH_MPRO_DST_MAXVAL;
> + u32 RESERVED_A_327;
> + u32 RESERVED_A_328;
> + u32 RESERVED_A_329;
> + u32 L1_VLATCH_MPRO_LM0_RMG_MIN;
> + u32 L1_VLATCH_MPRO_LM0_RMB_MIN;
> + u32 L1_VLATCH_MPRO_LM0_GMR_MIN;
> + u32 L1_VLATCH_MPRO_LM0_GMB_MIN;
> + u32 L1_VLATCH_MPRO_LM0_BMR_MIN;
> + u32 L1_VLATCH_MPRO_LM0_BMG_MIN;
> + u32 L1_VLATCH_MPRO_LM0_RMG_MAX;
> + u32 L1_VLATCH_MPRO_LM0_RMB_MAX;
> + u32 L1_VLATCH_MPRO_LM0_GMR_MAX;
> + u32 L1_VLATCH_MPRO_LM0_GMB_MAX;
> + u32 L1_VLATCH_MPRO_LM0_BMR_MAX;
> + u32 L1_VLATCH_MPRO_LM0_BMG_MAX;
> + u32 RESERVED_A_330;
> + u32 RESERVED_A_331;
> + u32 RESERVED_A_332;
> + u32 RESERVED_A_333;
> + u32 RESERVED_A_334;
> + u32 RESERVED_A_335;
> + u32 RESERVED_A_336;
> + u32 RESERVED_A_337;
> + u32 RESERVED_A_338;
> + u32 RESERVED_A_339;
> + u32 RESERVED_A_340;
> + u32 RESERVED_A_341;
> + u32 RESERVED_A_342;
> + u32 RESERVED_A_343;
> + u32 RESERVED_A_344;
> + u32 RESERVED_A_345;
> + u32 RESERVED_A_346;
> + u32 RESERVED_A_347;
> + u32 RESERVED_A_348;
> + u32 RESERVED_A_349;
> + u32 RESERVED_A_350;
> + u32 RESERVED_A_351;
> + u32 RESERVED_A_352;
> + u32 RESERVED_A_353;
> + u32 RESERVED_A_354;
> + u32 RESERVED_A_355;
> + u32 RESERVED_A_356;
> + u32 RESERVED_A_357;
> + u32 RESERVED_A_358;
> + u32 RESERVED_A_359;
> + u32 RESERVED_A_360;
> + u32 RESERVED_A_361;
> + u32 RESERVED_A_362;
> + u32 RESERVED_A_363;
> + u32 RESERVED_A_364;
> + u32 RESERVED_A_365;
> + u32 RESERVED_A_366;
> + u32 RESERVED_A_367;
> + u32 RESERVED_A_368;
> + u32 RESERVED_B_33[1];
> + u32 L1_VLATCH_MPRO_LCS_MODE;
> + u32 RESERVED_A_369;
> + u32 RESERVED_A_370;
> + u32 RESERVED_A_371;
> + u32 RESERVED_A_372;
> + u32 RESERVED_A_373;
> + u32 RESERVED_A_374;
> + u32 RESERVED_A_375;
> + u32 RESERVED_A_376;
> + u32 RESERVED_A_377;
> + u32 RESERVED_A_378;
> + u32 RESERVED_A_379;
> + u32 RESERVED_A_380;
> + u32 RESERVED_A_381;
> + u32 RESERVED_A_382;
> + u32 RESERVED_A_383;
> + u32 RESERVED_A_384;
> + u32 RESERVED_A_385;
> + u32 RESERVED_A_386;
> + u32 RESERVED_A_387;
> + u32 RESERVED_A_388;
> + u32 RESERVED_A_389;
> + u32 RESERVED_A_390;
> + u32 RESERVED_A_391;
> + u32 RESERVED_A_392;
> + u32 RESERVED_A_393;
> + u32 RESERVED_A_394;
> + u32 RESERVED_A_395;
> + u32 RESERVED_A_396;
> + u32 RESERVED_A_397;
> + u32 RESERVED_B_34[70];
> + u32 L1_VLATCH_VPRO_PGC_SW;
> + u32 RESERVED_A_398;
> + u32 L1_VLATCH_VPRO_YUVC_SW;
> + u32 L1_VLATCH_VPRO_YNR_SW;
> + u32 L1_VLATCH_VPRO_ETE_SW;
> + u32 L1_VLATCH_VPRO_CSUP_UVSUP_SW;
> + u32 L1_VLATCH_VPRO_CSUP_CORING_SW;
> + u32 L1_VLATCH_VPRO_BRIGHT_SW;
> + u32 L1_VLATCH_VPRO_LCNT_SW;
> + u32 L1_VLATCH_VPRO_NLCNT_SW;
> + u32 RESERVED_A_399;
> + u32 L1_VLATCH_VPRO_EDGE_SUP_SW;
> + u32 L1_VLATCH_VPRO_CNR_SW;
> + u32 RESERVED_A_400;
> + u32 L1_VLATCH_VPRO_BLKADJ;
> + u32 L1_VLATCH_VPRO_GAM01P;
> + u32 L1_VLATCH_VPRO_GAM02P;
> + u32 L1_VLATCH_VPRO_GAM03P;
> + u32 L1_VLATCH_VPRO_GAM04P;
> + u32 L1_VLATCH_VPRO_GAM05P;
> + u32 L1_VLATCH_VPRO_GAM06P;
> + u32 L1_VLATCH_VPRO_GAM07P;
> + u32 L1_VLATCH_VPRO_GAM08P;
> + u32 L1_VLATCH_VPRO_GAM09P;
> + u32 L1_VLATCH_VPRO_GAM10P;
> + u32 L1_VLATCH_VPRO_GAM11P;
> + u32 L1_VLATCH_VPRO_GAM12P;
> + u32 L1_VLATCH_VPRO_GAM13P;
> + u32 L1_VLATCH_VPRO_GAM14P;
> + u32 L1_VLATCH_VPRO_GAM15P;
> + u32 L1_VLATCH_VPRO_GAM16P;
> + u32 L1_VLATCH_VPRO_GAM17P;
> + u32 L1_VLATCH_VPRO_GAM18P;
> + u32 L1_VLATCH_VPRO_GAM19P;
> + u32 L1_VLATCH_VPRO_GAM20P;
> + u32 L1_VLATCH_VPRO_GAM21P;
> + u32 L1_VLATCH_VPRO_GAM22P;
> + u32 L1_VLATCH_VPRO_GAM23P;
> + u32 L1_VLATCH_VPRO_GAM24P;
> + u32 L1_VLATCH_VPRO_GAM25P;
> + u32 L1_VLATCH_VPRO_GAM26P;
> + u32 L1_VLATCH_VPRO_GAM27P;
> + u32 L1_VLATCH_VPRO_GAM28P;
> + u32 L1_VLATCH_VPRO_GAM29P;
> + u32 L1_VLATCH_VPRO_GAM30P;
> + u32 L1_VLATCH_VPRO_GAM31P;
> + u32 L1_VLATCH_VPRO_GAM32P;
> + u32 L1_VLATCH_VPRO_GAM33P;
> + u32 L1_VLATCH_VPRO_GAM34P;
> + u32 L1_VLATCH_VPRO_GAM35P;
> + u32 L1_VLATCH_VPRO_GAM36P;
> + u32 L1_VLATCH_VPRO_GAM37P;
> + u32 L1_VLATCH_VPRO_GAM38P;
> + u32 L1_VLATCH_VPRO_GAM39P;
> + u32 L1_VLATCH_VPRO_GAM40P;
> + u32 L1_VLATCH_VPRO_GAM41P;
> + u32 L1_VLATCH_VPRO_GAM42P;
> + u32 L1_VLATCH_VPRO_GAM43P;
> + u32 L1_VLATCH_VPRO_GAM44P;
> + u32 L1_VLATCH_VPRO_CB_MAT;
> + u32 L1_VLATCH_VPRO_CR_MAT;
> + u32 L1_VLATCH_VPRO_BRIGHT;
> + u32 L1_VLATCH_VPRO_LCONT_LEV;
> + u32 L1_VLATCH_VPRO_BLK_KNEE;
> + u32 L1_VLATCH_VPRO_WHT_KNEE;
> + u32 L1_VLATCH_VPRO_BLK_CONT0;
> + u32 L1_VLATCH_VPRO_BLK_CONT1;
> + u32 L1_VLATCH_VPRO_BLK_CONT2;
> + u32 L1_VLATCH_VPRO_WHT_CONT0;
> + u32 L1_VLATCH_VPRO_WHT_CONT1;
> + u32 L1_VLATCH_VPRO_WHT_CONT2;
> + u32 RESERVED_A_401;
> + u32 RESERVED_A_402;
> + u32 RESERVED_A_403;
> + u32 RESERVED_A_404;
> + u32 RESERVED_A_405;
> + u32 RESERVED_A_406;
> + u32 L1_VLATCH_VPRO_YNR_GAIN_MIN;
> + u32 L1_VLATCH_VPRO_YNR_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_YNR_LIM_MIN;
> + u32 L1_VLATCH_VPRO_YNR_LIM_MAX;
> + u32 L1_VLATCH_VPRO_ETE_GAIN_MIN;
> + u32 L1_VLATCH_VPRO_ETE_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_ETE_LIM_MIN;
> + u32 L1_VLATCH_VPRO_ETE_LIM_MAX;
> + u32 L1_VLATCH_VPRO_ETE_CORING_MIN;
> + u32 L1_VLATCH_VPRO_ETE_CORING_MAX;
> + u32 L1_VLATCH_VPRO_CB_GAIN;
> + u32 L1_VLATCH_VPRO_CR_GAIN;
> + u32 L1_VLATCH_VPRO_CBR_MGAIN_MIN;
> + u32 L1_VLATCH_VPRO_CbP_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_CbM_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_CrP_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_CrM_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_CSUP_CORING_LV_MIN;
> + u32 L1_VLATCH_VPRO_CSUP_CORING_LV_MAX;
> + u32 L1_VLATCH_VPRO_CSUP_CORING_GAIN_MIN;
> + u32 L1_VLATCH_VPRO_CSUP_CORING_GAIN_MAX;
> + u32 L1_VLATCH_VPRO_CSUP_BK_SLV;
> + u32 L1_VLATCH_VPRO_CSUP_BK_MP;
> + u32 L1_VLATCH_VPRO_CSUP_BLACK;
> + u32 L1_VLATCH_VPRO_CSUP_WH_SLV;
> + u32 L1_VLATCH_VPRO_CSUP_WH_MP;
> + u32 L1_VLATCH_VPRO_CSUP_WHITE;
> + u32 L1_VLATCH_VPRO_EDGE_SUP_GAIN;
> + u32 L1_VLATCH_VPRO_EDGE_SUP_LIM;
> + u32 RESERVED_B_35[22];
> + u32 L1_VLATCH_AWHB_SW;
> + u32 RESERVED_A_407;
> + u32 L1_VLATCH_AWHB_WBMRG;
> + u32 L1_VLATCH_AWHB_WBMGG;
> + u32 L1_VLATCH_AWHB_WBMBG;
> + u32 L1_VLATCH_AWHB_GATE_CONF0;
> + u32 L1_VLATCH_AWHB_GATE_CONF1;
> + u32 L1_VLATCH_AWHB_AREA_HSIZE;
> + u32 L1_VLATCH_AWHB_AREA_VSIZE;
> + u32 L1_VLATCH_AWHB_AREA_HOFS;
> + u32 L1_VLATCH_AWHB_AREA_VOFS;
> + u32 L1_VLATCH_AWHB_AREA_MASKH;
> + u32 L1_VLATCH_AWHB_AREA_MASKL;
> + u32 L1_VLATCH_AWHB_SQ_CONF;
> + u32 L1_VLATCH_AWHB_YGATEH;
> + u32 L1_VLATCH_AWHB_YGATEL;
> + u32 RESERVED_A_408;
> + u32 RESERVED_A_409;
> + u32 L1_VLATCH_AWHB_BYCUT0P;
> + u32 L1_VLATCH_AWHB_BYCUT0N;
> + u32 L1_VLATCH_AWHB_RYCUT0P;
> + u32 L1_VLATCH_AWHB_RYCUT0N;
> + u32 L1_VLATCH_AWHB_RBCUT0H;
> + u32 L1_VLATCH_AWHB_RBCUT0L;
> + u32 RESERVED_A_410;
> + u32 RESERVED_A_411;
> + u32 RESERVED_A_412;
> + u32 RESERVED_A_413;
> + u32 RESERVED_A_414;
> + u32 RESERVED_A_415;
> + u32 L1_VLATCH_AWHB_BYCUT1H;
> + u32 L1_VLATCH_AWHB_BYCUT1L;
> + u32 L1_VLATCH_AWHB_RYCUT1H;
> + u32 L1_VLATCH_AWHB_RYCUT1L;
> + u32 L1_VLATCH_AWHB_BYCUT2H;
> + u32 L1_VLATCH_AWHB_BYCUT2L;
> + u32 L1_VLATCH_AWHB_RYCUT2H;
> + u32 L1_VLATCH_AWHB_RYCUT2L;
> + u32 L1_VLATCH_AWHB_BYCUT3H;
> + u32 L1_VLATCH_AWHB_BYCUT3L;
> + u32 L1_VLATCH_AWHB_RYCUT3H;
> + u32 L1_VLATCH_AWHB_RYCUT3L;
> + u32 L1_VLATCH_AWHB_AWBSFTU;
> + u32 L1_VLATCH_AWHB_AWBSFTV;
> + u32 L1_VLATCH_AWHB_AWBSPD;
> + u32 L1_VLATCH_AWHB_AWBULV;
> + u32 L1_VLATCH_AWHB_AWBVLV;
> + u32 L1_VLATCH_AWHB_AWBWAIT;
> + u32 L1_VLATCH_AWHB_AWBONDOT;
> + u32 L1_VLATCH_AWHB_AWBFZTIM;
> + u32 L1_VLATCH_AWHB_WBGRMAX;
> + u32 L1_VLATCH_AWHB_WBGRMIN;
> + u32 L1_VLATCH_AWHB_WBGBMAX;
> + u32 L1_VLATCH_AWHB_WBGBMIN;
> + u32 RESERVED_A_416;
> + u32 RESERVED_A_417;
> + u32 RESERVED_A_418;
> + u32 RESERVED_A_419;
> + u32 RESERVED_A_420;
> + u32 RESERVED_A_421;
> + u32 RESERVED_A_422;
> + u32 RESERVED_A_423;
> + u32 RESERVED_A_424;
> + u32 RESERVED_A_425;
> + u32 RESERVED_A_426;
> + u32 RESERVED_A_427;
> + u32 RESERVED_A_428;
> + u32 RESERVED_A_429;
> + u32 RESERVED_A_430;
> + u32 RESERVED_A_431;
> + u32 RESERVED_A_432;
> + u32 RESERVED_A_433;
> + u32 RESERVED_A_434;
> + u32 RESERVED_A_435;
> + u32 RESERVED_A_436;
> + u32 RESERVED_A_437;
> + u32 RESERVED_A_438;
> + u32 RESERVED_A_439;
> + u32 RESERVED_B_36[2];
> + u32 L1_VLATCH_HOBC_EN;
> + u32 L1_VLATCH_HOBC_MARGIN;
> + u32 RESERVED_A_440;
> + u32 RESERVED_A_441;
> + u32 L1_VLATCH_HOBC0_LOB_REFLV_GR;
> + u32 L1_VLATCH_HOBC0_LOB_WIDTH_GR;
> + u32 L1_VLATCH_HOBC0_LOB_REFLV_R;
> + u32 L1_VLATCH_HOBC0_LOB_WIDTH_R;
> + u32 L1_VLATCH_HOBC0_LOB_REFLV_B;
> + u32 L1_VLATCH_HOBC0_LOB_WIDTH_B;
> + u32 L1_VLATCH_HOBC0_LOB_REFLV_GB;
> + u32 L1_VLATCH_HOBC0_LOB_WIDTH_GB;
> + u32 L1_VLATCH_HOBC1_LOB_REFLV_GR;
> + u32 L1_VLATCH_HOBC1_LOB_WIDTH_GR;
> + u32 L1_VLATCH_HOBC1_LOB_REFLV_R;
> + u32 L1_VLATCH_HOBC1_LOB_WIDTH_R;
> + u32 L1_VLATCH_HOBC1_LOB_REFLV_B;
> + u32 L1_VLATCH_HOBC1_LOB_WIDTH_B;
> + u32 L1_VLATCH_HOBC1_LOB_REFLV_GB;
> + u32 L1_VLATCH_HOBC1_LOB_WIDTH_GB;
> + u32 L1_VLATCH_HOBC2_LOB_REFLV_GR;
> + u32 L1_VLATCH_HOBC2_LOB_WIDTH_GR;
> + u32 L1_VLATCH_HOBC2_LOB_REFLV_R;
> + u32 L1_VLATCH_HOBC2_LOB_WIDTH_R;
> + u32 L1_VLATCH_HOBC2_LOB_REFLV_B;
> + u32 L1_VLATCH_HOBC2_LOB_WIDTH_B;
> + u32 L1_VLATCH_HOBC2_LOB_REFLV_GB;
> + u32 L1_VLATCH_HOBC2_LOB_WIDTH_GB;
> + u32 L1_VLATCH_HOBC0_SRC_BLKLV_GR;
> + u32 L1_VLATCH_HOBC0_SRC_BLKLV_R;
> + u32 L1_VLATCH_HOBC0_SRC_BLKLV_B;
> + u32 L1_VLATCH_HOBC0_SRC_BLKLV_GB;
> + u32 L1_VLATCH_HOBC1_SRC_BLKLV_GR;
> + u32 L1_VLATCH_HOBC1_SRC_BLKLV_R;
> + u32 L1_VLATCH_HOBC1_SRC_BLKLV_B;
> + u32 L1_VLATCH_HOBC1_SRC_BLKLV_GB;
> + u32 L1_VLATCH_HOBC2_SRC_BLKLV_GR;
> + u32 L1_VLATCH_HOBC2_SRC_BLKLV_R;
> + u32 L1_VLATCH_HOBC2_SRC_BLKLV_B;
> + u32 L1_VLATCH_HOBC2_SRC_BLKLV_GB;
> + u32 RESERVED_A_442;
> + u32 RESERVED_A_443;
> + u32 RESERVED_A_444;
> + u32 RESERVED_A_445;
> + u32 RESERVED_A_446;
> + u32 RESERVED_A_447;
> + u32 L1_VLATCH_HOBC_MAX_VAL;
> + u32 RESERVED_B_37[33];
> + u32 L1_VLATCH_HDRC_EN;
> + u32 L1_VLATCH_HDRC_THR_SFT_AMT;
> + u32 RESERVED_A_448;
> + u32 L1_VLATCH_HDRC_RATIO;
> + u32 RESERVED_A_449;
> + u32 RESERVED_A_450;
> + u32 RESERVED_A_451;
> + u32 L1_VLATCH_HDRC_PT_RATIO;
> + u32 L1_VLATCH_HDRC_PT_BLEND;
> + u32 L1_VLATCH_HDRC_PT_BLEND2;
> + u32 L1_VLATCH_HDRC_PT_SAT;
> + u32 L1_VLATCH_HDRC_TN_TYPE;
> + u32 L1_VLATCH_HDRC_TNP_MAX;
> + u32 L1_VLATCH_HDRC_TNP_MAG;
> + u32 RESERVED_A_452;
> + u32 RESERVED_A_453;
> + u32 RESERVED_A_454;
> + u32 RESERVED_A_455;
> + u32 L1_VLATCH_HDRC_TNP_FIL0;
> + u32 L1_VLATCH_HDRC_TNP_FIL1;
> + u32 L1_VLATCH_HDRC_TNP_FIL2;
> + u32 L1_VLATCH_HDRC_TNP_FIL3;
> + u32 L1_VLATCH_HDRC_TNP_FIL4;
> + u32 L1_VLATCH_HDRC_UTN_TBL0;
> + u32 L1_VLATCH_HDRC_UTN_TBL1;
> + u32 L1_VLATCH_HDRC_UTN_TBL2;
> + u32 L1_VLATCH_HDRC_UTN_TBL3;
> + u32 L1_VLATCH_HDRC_UTN_TBL4;
> + u32 L1_VLATCH_HDRC_UTN_TBL5;
> + u32 L1_VLATCH_HDRC_UTN_TBL6;
> + u32 L1_VLATCH_HDRC_UTN_TBL7;
> + u32 L1_VLATCH_HDRC_UTN_TBL8;
> + u32 L1_VLATCH_HDRC_UTN_TBL9;
> + u32 L1_VLATCH_HDRC_UTN_TBL10;
> + u32 L1_VLATCH_HDRC_UTN_TBL11;
> + u32 L1_VLATCH_HDRC_UTN_TBL12;
> + u32 L1_VLATCH_HDRC_UTN_TBL13;
> + u32 L1_VLATCH_HDRC_UTN_TBL14;
> + u32 L1_VLATCH_HDRC_UTN_TBL15;
> + u32 L1_VLATCH_HDRC_UTN_TBL16;
> + u32 L1_VLATCH_HDRC_UTN_TBL17;
> + u32 L1_VLATCH_HDRC_UTN_TBL18;
> + u32 L1_VLATCH_HDRC_UTN_TBL19;
> + u32 L1_VLATCH_HDRC_FLR_VAL;
> + u32 L1_VLATCH_HDRC_FLR_ADP;
> + u32 RESERVED_A_456;
> + u32 RESERVED_A_457;
> + u32 RESERVED_A_458;
> + u32 RESERVED_A_459;
> + u32 RESERVED_A_460;
> + u32 RESERVED_A_461;
> + u32 RESERVED_A_462;
> + u32 RESERVED_A_463;
> + u32 RESERVED_A_464;
> + u32 RESERVED_A_465;
> + u32 RESERVED_A_466;
> + u32 RESERVED_A_467;
> + u32 RESERVED_A_468;
> + u32 RESERVED_A_469;
> + u32 L1_VLATCH_HDRC_YBR_OFF;
> + u32 L1_VLATCH_HDRC_ORGY_BLEND;
> + u32 RESERVED_A_470;
> + u32 RESERVED_A_471;
> + u32 RESERVED_A_472;
> + u32 L1_VLATCH_HDRC_MAR_TOP;
> + u32 L1_VLATCH_HDRC_MAR_LEFT;
> + u32 RESERVED_A_473;
> + u32 RESERVED_A_474;
> + u32 RESERVED_B_38[28];
> + u32 L1_VLATCH_HIST_EN;
> + u32 L1_VLATCH_HIST_MODE;
> + u32 L1_VLATCH_HIST_BLOCK_OFST;
> + u32 L1_VLATCH_HIST_BLOCK_SIZE;
> + u32 L1_VLATCH_HIST_BLOCK_NUM;
> + u32 L1_VLATCH_HIST_BLOCK_STEP;
> + u32 L1_VLATCH_HIST_LINEAR_SFT;
> + u32 L1_VLATCH_HIST_MULT_A_R;
> + u32 L1_VLATCH_HIST_ADD_A_R;
> + u32 L1_VLATCH_HIST_MULT_B_R;
> + u32 L1_VLATCH_HIST_ADD_B_R;
> + u32 L1_VLATCH_HIST_MULT_A_G;
> + u32 L1_VLATCH_HIST_ADD_A_G;
> + u32 L1_VLATCH_HIST_MULT_B_G;
> + u32 L1_VLATCH_HIST_ADD_B_G;
> + u32 L1_VLATCH_HIST_MULT_A_B;
> + u32 L1_VLATCH_HIST_ADD_A_B;
> + u32 L1_VLATCH_HIST_MULT_B_B;
> + u32 L1_VLATCH_HIST_ADD_B_B;
> + u32 L1_VLATCH_HIST_MULT_A_Y;
> + u32 L1_VLATCH_HIST_ADD_A_Y;
> + u32 L1_VLATCH_HIST_MULT_B_Y;
> + u32 L1_VLATCH_HIST_ADD_B_Y;
> + u32 RESERVED_B_39[265];
> +};
> +
> +/**
> + * struct hwd_viif_l2isp_stadr_buf_reg - Registers for L2ISP control
> + */
> +struct hwd_viif_l2isp_stadr_buf_reg {
> + u32 L2_POST_OUT_STADR_B_BUF;
> + u32 L2_POST_OUT_STADR_G_BUF;
> + u32 L2_POST_OUT_STADR_R_BUF;
> +};
> +
> +struct hwd_viif_l2isp_roi_reg {
> + u32 L2_ROI_SCALE;
> + u32 L2_ROI_SCALE_INV;
> + u32 L2_ROI_CORRECTED_HSIZE;
> + u32 L2_ROI_CORRECTED_VSIZE;
> + u32 L2_ROI_OUT_OFS_H;
> + u32 L2_ROI_OUT_OFS_V;
> + u32 L2_ROI_OUT_HSIZE;
> + u32 L2_ROI_OUT_VSIZE;
> +};
> +
> +struct hwd_viif_l2isp_post_reg {
> + u32 L2_POST_CAP_OFFSET;
> + u32 L2_POST_CAP_SIZE;
> + u32 L2_POST_HALF_SCALE_EN;
> + u32 RESERVED_B_47[17];
> + u32 L2_POST_GAMMA_M;
> + u32 RESERVED_B_48[3];
> + u32 L2_POST_C_SELECT;
> + u32 RESERVED_B_49[3];
> + struct hwd_viif_csc_reg csc;
> + u32 L2_POST_OPORTALP;
> + u32 L2_POST_OPORTFMT;
> + u32 L2_POST_OUT_STADR_B;
> + u32 L2_POST_OUT_STADR_G;
> + u32 L2_POST_OUT_STADR_R;
> + u32 L2_POST_OUT_PITCH_B;
> + u32 L2_POST_OUT_PITCH_G;
> + u32 L2_POST_OUT_PITCH_R;
> + u32 L2_POST_DUMMY_READ_EN;
> + u32 RESERVED_B_51[11];
> +};
> +
> +struct hwd_viif_l2isp_reg {
> + u32 L2_SENSOR_CROP_OFS_H;
> + u32 L2_SENSOR_CROP_OFS_V;
> + u32 L2_SENSOR_CROP_HSIZE;
> + u32 L2_SENSOR_CROP_VSIZE;
> + u32 RESERVED_A_475;
> + u32 L2_L2_STATUS;
> + u32 L2_BUS_L2_STATUS;
> + /* [0]: POST0, [1]: POST1 */
> + struct hwd_viif_l2isp_stadr_buf_reg stadr_buf[2];
> + u32 RESERVED_B_40[3];
> + u32 L2_ROI_NUM;
> + /* [0]: POST0, [1]: POST1 */
> + u32 L2_ROI_TO_POST[2];
> + u32 RESERVED_B_41;
> + /* [0]: ROI0, [1]: ROI1 */
> + struct hwd_viif_l2isp_roi_reg roi[2];
> + u32 RESERVED_B_42[8];
> + u32 L2_VALID_R_NORM2_POLY;
> + u32 L2_VALID_R_NORM2_GRID;
> + u32 RESERVED_A_476;
> + u32 RESERVED_B_43[17];
> + u32 L2_MODE;
> + u32 L2_NORM_SCALE;
> + u32 RESERVED_B_44;
> + /* [0]: ROI0, [1]: ROI1 */
> + u32 L2_ROI_WRITE_AREA_DELTA[2];
> + u32 RESERVED_B_45;
> + u32 L2_GRID_NODE_NUM_H;
> + u32 L2_GRID_NODE_NUM_V;
> + u32 L2_GRID_PATCH_HSIZE_INV;
> + u32 L2_GRID_PATCH_VSIZE_INV;
> + u32 L2_POLY10_WRITE_G_COEF[11];
> + u32 L2_POLY10_READ_B_COEF[11];
> + u32 L2_POLY10_READ_G_COEF[11];
> + u32 L2_POLY10_READ_R_COEF[11];
> + u32 RESERVED_B_46[10];
> + /* [0]: POST0, [1]: POST1 */
> + struct hwd_viif_l2isp_post_reg post[2];
> + u32 RESERVED_B_56[192];
> + u32 L2_CRGBF_ACC_CONF;
> + u32 L2_CRGBF_TRN_M_RUN;
> + u32 L2_CRGBF_TRN_M_CONF;
> + u32 L2_CRGBF_TRN_A_CONF;
> + u32 L2_CRGBF_TRN_STAT_CLR;
> + u32 L2_CRGBF_TRN_STAT;
> + u32 L2_CRGBF_INT_STAT;
> + u32 L2_CRGBF_INT_MASK;
> + u32 L2_CRGBF_INT_MASKED_STAT;
> + u32 L2_CRGBF_TRN_WBADDR;
> + u32 L2_CRGBF_TRN_WEADDR;
> + u32 L2_CRGBF_TRN_RBADDR;
> + u32 L2_CRGBF_TRN_READDR;
> + u32 L2_CRGBF_ISP_INT;
> + u32 L2_CRGBF_ISP_INT_MASK;
> + u32 L2_CRGBF_ISP_INT_MASKED_STAT;
> + u32 RESERVED_A_477;
> + u32 RESERVED_B_57[47];
> + u32 L2_SENSOR_CROP_OFS_H_BUF;
> + u32 L2_SENSOR_CROP_OFS_V_BUF;
> + u32 L2_SENSOR_CROP_HSIZE_BUF;
> + u32 L2_SENSOR_CROP_VSIZE_BUF;
> + u32 RESERVED_A_478;
> + u32 RESERVED_B_58[11];
> + u32 L2_ROI_NUM_BUF;
> + u32 L2_ROI_TO_POST0_BUF;
> + u32 L2_ROI_TO_POST1_BUF;
> + u32 RESERVED_B_59;
> + u32 L2_ROI0_SCALE_BUF;
> + u32 L2_ROI0_SCALE_INV_BUF;
> + u32 L2_ROI0_CORRECTED_HSIZE_BUF;
> + u32 L2_ROI0_CORRECTED_VSIZE_BUF;
> + u32 L2_ROI0_OUT_OFS_H_BUF;
> + u32 L2_ROI0_OUT_OFS_V_BUF;
> + u32 L2_ROI0_OUT_HSIZE_BUF;
> + u32 L2_ROI0_OUT_VSIZE_BUF;
> + u32 L2_ROI1_SCALE_BUF;
> + u32 L2_ROI1_SCALE_INV_BUF;
> + u32 L2_ROI1_CORRECTED_HSIZE_BUF;
> + u32 L2_ROI1_CORRECTED_VSIZE_BUF;
> + u32 L2_ROI1_OUT_OFS_H_BUF;
> + u32 L2_ROI1_OUT_OFS_V_BUF;
> + u32 L2_ROI1_OUT_HSIZE_BUF;
> + u32 L2_ROI1_OUT_VSIZE_BUF;
> + u32 RESERVED_B_60[8];
> + u32 L2_VALID_R_NORM2_POLY_BUF;
> + u32 L2_VALID_R_NORM2_GRID_BUF;
> + u32 RESERVED_A_479;
> + u32 RESERVED_B_61[17];
> + u32 L2_MODE_BUF;
> + u32 L2_NORM_SCALE_BUF;
> + u32 RESERVED_B_62;
> + u32 L2_ROI0_WRITE_AREA_DELTA_BUF;
> + u32 L2_ROI1_WRITE_AREA_DELTA_BUF;
> + u32 RESERVED_B_63;
> + u32 L2_GRID_NODE_NUM_H_BUF;
> + u32 L2_GRID_NODE_NUM_V_BUF;
> + u32 L2_GRID_PATCH_HSIZE_INV_BUF;
> + u32 L2_GRID_PATCH_VSIZE_INV_BUF;
> + u32 L2_POLY10_WRITE_G_COEF00_BUF;
> + u32 L2_POLY10_WRITE_G_COEF01_BUF;
> + u32 L2_POLY10_WRITE_G_COEF02_BUF;
> + u32 L2_POLY10_WRITE_G_COEF03_BUF;
> + u32 L2_POLY10_WRITE_G_COEF04_BUF;
> + u32 L2_POLY10_WRITE_G_COEF05_BUF;
> + u32 L2_POLY10_WRITE_G_COEF06_BUF;
> + u32 L2_POLY10_WRITE_G_COEF07_BUF;
> + u32 L2_POLY10_WRITE_G_COEF08_BUF;
> + u32 L2_POLY10_WRITE_G_COEF09_BUF;
> + u32 L2_POLY10_WRITE_G_COEF10_BUF;
> + u32 L2_POLY10_READ_B_COEF00_BUF;
> + u32 L2_POLY10_READ_B_COEF01_BUF;
> + u32 L2_POLY10_READ_B_COEF02_BUF;
> + u32 L2_POLY10_READ_B_COEF03_BUF;
> + u32 L2_POLY10_READ_B_COEF04_BUF;
> + u32 L2_POLY10_READ_B_COEF05_BUF;
> + u32 L2_POLY10_READ_B_COEF06_BUF;
> + u32 L2_POLY10_READ_B_COEF07_BUF;
> + u32 L2_POLY10_READ_B_COEF08_BUF;
> + u32 L2_POLY10_READ_B_COEF09_BUF;
> + u32 L2_POLY10_READ_B_COEF10_BUF;
> + u32 L2_POLY10_READ_G_COEF00_BUF;
> + u32 L2_POLY10_READ_G_COEF01_BUF;
> + u32 L2_POLY10_READ_G_COEF02_BUF;
> + u32 L2_POLY10_READ_G_COEF03_BUF;
> + u32 L2_POLY10_READ_G_COEF04_BUF;
> + u32 L2_POLY10_READ_G_COEF05_BUF;
> + u32 L2_POLY10_READ_G_COEF06_BUF;
> + u32 L2_POLY10_READ_G_COEF07_BUF;
> + u32 L2_POLY10_READ_G_COEF08_BUF;
> + u32 L2_POLY10_READ_G_COEF09_BUF;
> + u32 L2_POLY10_READ_G_COEF10_BUF;
> + u32 L2_POLY10_READ_R_COEF00_BUF;
> + u32 L2_POLY10_READ_R_COEF01_BUF;
> + u32 L2_POLY10_READ_R_COEF02_BUF;
> + u32 L2_POLY10_READ_R_COEF03_BUF;
> + u32 L2_POLY10_READ_R_COEF04_BUF;
> + u32 L2_POLY10_READ_R_COEF05_BUF;
> + u32 L2_POLY10_READ_R_COEF06_BUF;
> + u32 L2_POLY10_READ_R_COEF07_BUF;
> + u32 L2_POLY10_READ_R_COEF08_BUF;
> + u32 L2_POLY10_READ_R_COEF09_BUF;
> + u32 L2_POLY10_READ_R_COEF10_BUF;
> + u32 RESERVED_B_64[10];
> + u32 L2_POST0_CAP_OFFSET_BUF;
> + u32 L2_POST0_CAP_SIZE_BUF;
> + u32 L2_POST0_HALF_SCALE_EN_BUF;
> + u32 RESERVED_B_65[17];
> + u32 L2_POST0_GAMMA_M_BUF;
> + u32 RESERVED_B_66[3];
> + u32 L2_POST0_C_SELECT_BUF;
> + u32 RESERVED_B_67[3];
> + u32 L2_POST0_MTB_BUF;
> + u32 RESERVED_B_68[3];
> + u32 L2_POST0_MTB_YG_OFFSETI_BUF;
> + u32 L2_POST0_MTB_YG1_BUF;
> + u32 L2_POST0_MTB_YG2_BUF;
> + u32 L2_POST0_MTB_YG_OFFSETO_BUF;
> + u32 L2_POST0_MTB_CB_OFFSETI_BUF;
> + u32 L2_POST0_MTB_CB1_BUF;
> + u32 L2_POST0_MTB_CB2_BUF;
> + u32 L2_POST0_MTB_CB_OFFSETO_BUF;
> + u32 L2_POST0_MTB_CR_OFFSETI_BUF;
> + u32 L2_POST0_MTB_CR1_BUF;
> + u32 L2_POST0_MTB_CR2_BUF;
> + u32 L2_POST0_MTB_CR_OFFSETO_BUF;
> + u32 L2_POST0_OPORTALP_BUF;
> + u32 L2_POST0_OPORTFMT_BUF;
> + u32 RESERVED_B_69[3];
> + u32 L2_POST0_OUT_PITCH_B_BUF;
> + u32 L2_POST0_OUT_PITCH_G_BUF;
> + u32 L2_POST0_OUT_PITCH_R_BUF;
> + u32 L2_POST0_DUMMY_READ_EN_BUF;
> + u32 RESERVED_B_70[11];
> + u32 L2_POST1_CAP_OFFSET_BUF;
> + u32 L2_POST1_CAP_SIZE_BUF;
> + u32 L2_POST1_HALF_SCALE_EN_BUF;
> + u32 RESERVED_B_71[17];
> + u32 L2_POST1_GAMMA_M_BUF;
> + u32 RESERVED_B_72[3];
> + u32 L2_POST1_C_SELECT_BUF;
> + u32 RESERVED_B_73[3];
> + u32 L2_POST1_MTB_BUF;
> + u32 RESERVED_B_74[3];
> + u32 L2_POST1_MTB_YG_OFFSETI_BUF;
> + u32 L2_POST1_MTB_YG1_BUF;
> + u32 L2_POST1_MTB_YG2_BUF;
> + u32 L2_POST1_MTB_YG_OFFSETO_BUF;
> + u32 L2_POST1_MTB_CB_OFFSETI_BUF;
> + u32 L2_POST1_MTB_CB1_BUF;
> + u32 L2_POST1_MTB_CB2_BUF;
> + u32 L2_POST1_MTB_CB_OFFSETO_BUF;
> + u32 L2_POST1_MTB_CR_OFFSETI_BUF;
> + u32 L2_POST1_MTB_CR1_BUF;
> + u32 L2_POST1_MTB_CR2_BUF;
> + u32 L2_POST1_MTB_CR_OFFSETO_BUF;
> + u32 L2_POST1_OPORTALP_BUF;
> + u32 L2_POST1_OPORTFMT_BUF;
> + u32 RESERVED_B_75[3];
> + u32 L2_POST1_OUT_PITCH_B_BUF;
> + u32 L2_POST1_OUT_PITCH_G_BUF;
> + u32 L2_POST1_OUT_PITCH_R_BUF;
> + u32 L2_POST1_DUMMY_READ_EN_BUF;
> + u32 RESERVED_B_76[64];
> +};
> +
> +/**
> + * struct hwd_viif_capture_reg - Registers for VIIF CAPTURE control
> + */
> +struct hwd_viif_capture_reg {
> + struct hwd_viif_system_reg sys;
> + struct hwd_viif_vdm_reg vdm;
> + struct hwd_viif_l1isp_reg l1isp;
> + struct hwd_viif_l2isp_reg l2isp;
> +};
> +
> +#endif /* HWD_VIIF_REG_H */
> diff --git a/include/uapi/linux/visconti_viif.h b/include/uapi/linux/visconti_viif.h
> new file mode 100644
> index 00000000000..f92278425b7
> --- /dev/null
> +++ b/include/uapi/linux/visconti_viif.h
> @@ -0,0 +1,1724 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef __UAPI_VISCONTI_VIIF_H_
> +#define __UAPI_VISCONTI_VIIF_H_
> +
> +#include <linux/types.h>
> +#include <linux/videodev2.h>
> +
> +/* Visconti specific compound controls */
> +#define V4L2_CID_VISCONTI_VIIF_BASE (V4L2_CID_USER_BASE + 0x1000)
> +#define V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 1)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 2)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF (V4L2_CID_VISCONTI_VIIF_BASE + 3)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 4)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG (V4L2_CID_VISCONTI_VIIF_BASE + 5)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE (V4L2_CID_VISCONTI_VIIF_BASE + 6)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION (V4L2_CID_VISCONTI_VIIF_BASE + 7)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC (V4L2_CID_VISCONTI_VIIF_BASE + 8)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE (V4L2_CID_VISCONTI_VIIF_BASE + 9)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION \
> + (V4L2_CID_VISCONTI_VIIF_BASE + 10)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS (V4L2_CID_VISCONTI_VIIF_BASE + 11)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION (V4L2_CID_VISCONTI_VIIF_BASE + 12)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC (V4L2_CID_VISCONTI_VIIF_BASE + 13)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS (V4L2_CID_VISCONTI_VIIF_BASE + 14)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB (V4L2_CID_VISCONTI_VIIF_BASE + 15)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN (V4L2_CID_VISCONTI_VIIF_BASE + 16)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC (V4L2_CID_VISCONTI_VIIF_BASE + 17)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM (V4L2_CID_VISCONTI_VIIF_BASE + 18)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 19)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT (V4L2_CID_VISCONTI_VIIF_BASE + 20)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION (V4L2_CID_VISCONTI_VIIF_BASE + 21)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST (V4L2_CID_VISCONTI_VIIF_BASE + 22)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI (V4L2_CID_VISCONTI_VIIF_BASE + 23)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 24)
> +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 25)
> +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 26)
> +#define V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 27)
> +#define V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS (V4L2_CID_VISCONTI_VIIF_BASE + 28)
> +
> +/* Enable/Disable flag */
> +#define VIIF_DISABLE (0U)
> +#define VIIF_ENABLE (1U)
> +
> +/**
> + * enum viif_rawpack_mode - RAW pack mode for ioctl(VIDIOC_VIIF_MAIN_SET_RAWPACK_MODE)
> + *
> + * @VIIF_RAWPACK_DISABLE: RAW pack disable
> + * @VIIF_RAWPACK_MSBFIRST: RAW pack enable (MSB First)
> + * @VIIF_RAWPACK_LSBFIRST: RAW pack enable (LSB First)
> + */
> +enum viif_rawpack_mode {
> + VIIF_RAWPACK_DISABLE = 0,
> + VIIF_RAWPACK_MSBFIRST = 2,
> + VIIF_RAWPACK_LSBFIRST = 3,
> +};
> +
> +/**
> + * enum viif_l1_input - L1ISP preprocessing mode
> + *
> + * @VIIF_L1_INPUT_HDR: bypass(HDR input)
> + * @VIIF_L1_INPUT_PWL: HDRE(PWL input)
> + * @VIIF_L1_INPUT_HDR_IMG_CORRECT: SLIC-ABPC-PWHB-RCNR-HDRS
> + * @VIIF_L1_INPUT_PWL_IMG_CORRECT: HDRE-SLIC-ABPC-PWHB-RCNR-HDRS
> + */
> +enum viif_l1_input {
> + VIIF_L1_INPUT_HDR = 0,
> + VIIF_L1_INPUT_PWL = 1,
> + VIIF_L1_INPUT_HDR_IMG_CORRECT = 3,
> + VIIF_L1_INPUT_PWL_IMG_CORRECT = 4,
> +};
> +
> +/**
> + * enum viif_l1_raw - L1ISP RAW color filter mode
> + *
> + * @VIIF_L1_RAW_GR_R_B_GB: Gr-R-B-Gb
> + * @VIIF_L1_RAW_R_GR_GB_B: R-Gr-Gb-B
> + * @VIIF_L1_RAW_B_GB_GR_R: B-Gb-Gr-R
> + * @VIIF_L1_RAW_GB_B_R_GR: Gb-B-R-Gr
> + */
> +enum viif_l1_raw {
> + VIIF_L1_RAW_GR_R_B_GB = 0,
> + VIIF_L1_RAW_R_GR_GB_B = 1,
> + VIIF_L1_RAW_B_GB_GR_R = 2,
> + VIIF_L1_RAW_GB_B_R_GR = 3,
> +};
> +
> +/**
> + * struct viif_l1_input_mode_config - L1ISP INPUT MODE parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE`
> + * @mode: &enum viif_l1_input value.
> + * @depth: Color depth (even only). Range for each L1ISP pre-processing mode is:
> + *
> + * * VIIF_L1_INPUT_HDR/HDR_IMG_CORRECT: Range: [8..24].
> + * * VIIF_L1_INPUT_PWL/PWL_IMG_CORRECT: Range: [8..14].
> + * @raw_color_filter: &enum viif_l1_raw value.
> + */
> +struct viif_l1_input_mode_config {
> + __u32 mode;
> + __u32 depth;
> + __u32 raw_color_filter;
> +};
> +
> +/**
> + * struct viif_l1_rgb_to_y_coef_config - L1ISP coefficient for calculating
> + * Y from RGB parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF`
> + * @coef_r: R co-efficient [256..65024] accuracy: 1/65536
> + * @coef_g: R co-efficient [256..65024] accuracy: 1/65536
> + * @coef_b: R co-efficient [256..65024] accuracy: 1/65536
> + */
> +struct viif_l1_rgb_to_y_coef_config {
> + __u16 coef_r;
> + __u16 coef_g;
> + __u16 coef_b;
> +};
> +
> +/**
> + * enum viif_l1_img_sensitivity_mode - L1ISP image sensitivity
> + *
> + * @VIIF_L1_IMG_SENSITIVITY_HIGH: high sensitivity
> + * @VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED: middle sensitivity or led
> + * @VIIF_L1_IMG_SENSITIVITY_LOW: low sensitivity
> + */
> +enum viif_l1_img_sensitivity_mode {
> + VIIF_L1_IMG_SENSITIVITY_HIGH = 0,
> + VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED = 1,
> + VIIF_L1_IMG_SENSITIVITY_LOW = 2,
> +};
> +
> +/**
> + * struct viif_l1_ag_mode_config - L1ISP AG mode parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE`
> + * @sysm_ag_grad: Analog gain slope [0..255] (element is id)
> + * @sysm_ag_ofst: Analog gain offset [0..65535] (element is id)
> + * @sysm_ag_cont_hobc_en_high: 1:enable/0:disable to control analog gain
> + * for high sensitivity image of OBCC
> + * @sysm_ag_psel_hobc_high: Analog gain id for high sensitivity image of OBCC [0..3]
> + * @sysm_ag_cont_hobc_en_middle_led: 1:enable/0:disable to control analog gain
> + * for middle sensitivity or LED image of OBCC
> + * @sysm_ag_psel_hobc_middle_led: Analog gain id for middle sensitivity
> + * or LED image of OBCC [0..3]
> + * @sysm_ag_cont_hobc_en_low: 1:enable/0:disable to control analog gain
> + * for low sensitivity image of OBCC
> + * @sysm_ag_psel_hobc_low: Analog gain id for low sensitivity image of OBCC [0..3]
> + * @sysm_ag_cont_abpc_en_high: 1:enable/0:disable to control analog gain
> + * for high sensitivity image of ABPC
> + * @sysm_ag_psel_abpc_high: Analog gain id for high sensitivity image of ABPC [0..3]
> + * @sysm_ag_cont_abpc_en_middle_led: 1:enable/0:disable to control analog gain
> + * for middle sensitivity or LED image of ABPC
> + * @sysm_ag_psel_abpc_middle_led: Analog gain id for middle sensitivity
> + * or LED image of ABPC [0..3]
> + * @sysm_ag_cont_abpc_en_low: 1:enable/0:disable to control analog gain
> + * for low sensitivity image of ABPC
> + * @sysm_ag_psel_abpc_low: Analog gain id for low sensitivity image of ABPC [0..3]
> + * @sysm_ag_cont_rcnr_en_high: 1:enable/0:disable to control analog gain
> + * for high sensitivity image of RCNR
> + * @sysm_ag_psel_rcnr_high: Analog gain id for high sensitivity image of RCNR [0..3]
> + * @sysm_ag_cont_rcnr_en_middle_led: 1:enable/0:disable to control analog gain
> + * for middle sensitivity or LED image of RCNR
> + * @sysm_ag_psel_rcnr_middle_led: Analog gain id for middle sensitivity
> + * or LED image of RCNR [0..3]
> + * @sysm_ag_cont_rcnr_en_low: 1:enable/0:disable to control analog gain
> + * for low sensitivity image of RCNR
> + * @sysm_ag_psel_rcnr_low: Analog gain id for low sensitivity image of RCNR [0..3]
> + * @sysm_ag_cont_lssc_en: 1:enable/0:disable to control analog gain for LSC
> + * @sysm_ag_ssel_lssc: &enum viif_l1_img_sensitivity_mode value. Sensitive image used for LSC.
> + * @sysm_ag_psel_lssc: Analog gain id for LSC [0..3]
> + * @sysm_ag_cont_mpro_en: 1:enable/0:disable to control analog gain for color matrix
> + * @sysm_ag_ssel_mpro: &enum viif_l1_img_sensitivity_mode value.
> + * Sensitive image used for color matrix.
> + * @sysm_ag_psel_mpro:Aanalog gain id for color matrix [0..3]
> + * @sysm_ag_cont_vpro_en: 1:enable/0:disable to control analog gain for image adjustment
> + * @sysm_ag_ssel_vpro: &enum viif_l1_img_sensitivity_mode value.
> + * Sensitive image used for image adjustment.
> + * @sysm_ag_psel_vpro: Analog gain id for image adjustment [0..3]
> + * @sysm_ag_cont_hobc_test_high: Manual analog gain for high sensitivity image
> + * of OBCC [0..255]
> + * @sysm_ag_cont_hobc_test_middle_led: Manual analog gain for middle sensitivity
> + * or led image of OBCC [0..255]
> + * @sysm_ag_cont_hobc_test_low: Manual analog gain for low sensitivity image
> + * of OBCC [0..255]
> + * @sysm_ag_cont_abpc_test_high: Manual analog gain for high sensitivity image
> + * of ABPC [0..255]
> + * @sysm_ag_cont_abpc_test_middle_led: Manual analog gain for middle sensitivity
> + * or led image of ABPC [0..255]
> + * @sysm_ag_cont_abpc_test_low: Manual analog gain for low sensitivity image
> + * of ABPC [0..255]
> + * @sysm_ag_cont_rcnr_test_high: Manual analog gain for high sensitivity image
> + * of RCNR [0..255]
> + * @sysm_ag_cont_rcnr_test_middle_led: Manual analog gain for middle sensitivity
> + * or led image of RCNR [0..255]
> + * @sysm_ag_cont_rcnr_test_low: Manual analog gain for low sensitivity image
> + * of RCNR [0..255]
> + * @sysm_ag_cont_lssc_test: Manual analog gain for LSSC [0..255]
> + * @sysm_ag_cont_mpro_test: Manual analog gain for color matrix [0..255]
> + * @sysm_ag_cont_vpro_test: Manual analog gain for image adjustment [0..255]
> + *
> + * Operation setting of L1ISP analog gain function.
> + * Analog gain control is disabled if following settings are done.
> + * "sysm_ag_cont_*_en = DRV_VIIF_DISABLE" and "sysm_ag_cont_*_test = 0"
> + * In case "VIIF_L1_INPUT_HDR" or "VIIF_L1_INPUT_PWL" is set to "mode" which is
> + * an &struct viif_l1_input_mode_config, analog gain control needs to be disabled.
> + * Even if this condition is not satisfied, this driver doesn't return error.
> + *
> + * The value set in sysm_ag_psel_xxx indicates analog gain system to be used and
> + * corresponds to the element number of sysm_ag_grad and sysm_ag_ofst.
> + * For example, if sysm_ag_psel_hobc_high is set to 2, then values set in
> + * sysm_ag_grad[2] and sysm_ag_ofst[2] are used for high sensitivity images
> + * in OBCC processing.
> + */
> +struct viif_l1_ag_mode_config {
> + __u8 sysm_ag_grad[4];
> + __u16 sysm_ag_ofst[4];
> + __u32 sysm_ag_cont_hobc_en_high;
> + __u32 sysm_ag_psel_hobc_high;
> + __u32 sysm_ag_cont_hobc_en_middle_led;
> + __u32 sysm_ag_psel_hobc_middle_led;
> + __u32 sysm_ag_cont_hobc_en_low;
> + __u32 sysm_ag_psel_hobc_low;
> + __u32 sysm_ag_cont_abpc_en_high;
> + __u32 sysm_ag_psel_abpc_high;
> + __u32 sysm_ag_cont_abpc_en_middle_led;
> + __u32 sysm_ag_psel_abpc_middle_led;
> + __u32 sysm_ag_cont_abpc_en_low;
> + __u32 sysm_ag_psel_abpc_low;
> + __u32 sysm_ag_cont_rcnr_en_high;
> + __u32 sysm_ag_psel_rcnr_high;
> + __u32 sysm_ag_cont_rcnr_en_middle_led;
> + __u32 sysm_ag_psel_rcnr_middle_led;
> + __u32 sysm_ag_cont_rcnr_en_low;
> + __u32 sysm_ag_psel_rcnr_low;
> + __u32 sysm_ag_cont_lssc_en;
> + __u32 sysm_ag_ssel_lssc;
> + __u32 sysm_ag_psel_lssc;
> + __u32 sysm_ag_cont_mpro_en;
> + __u32 sysm_ag_ssel_mpro;
> + __u32 sysm_ag_psel_mpro;
> + __u32 sysm_ag_cont_vpro_en;
> + __u32 sysm_ag_ssel_vpro;
> + __u32 sysm_ag_psel_vpro;
> + __u8 sysm_ag_cont_hobc_test_high;
> + __u8 sysm_ag_cont_hobc_test_middle_led;
> + __u8 sysm_ag_cont_hobc_test_low;
> + __u8 sysm_ag_cont_abpc_test_high;
> + __u8 sysm_ag_cont_abpc_test_middle_led;
> + __u8 sysm_ag_cont_abpc_test_low;
> + __u8 sysm_ag_cont_rcnr_test_high;
> + __u8 sysm_ag_cont_rcnr_test_middle_led;
> + __u8 sysm_ag_cont_rcnr_test_low;
> + __u8 sysm_ag_cont_lssc_test;
> + __u8 sysm_ag_cont_mpro_test;
> + __u8 sysm_ag_cont_vpro_test;
> +};
> +
> +/**
> + * struct viif_l1_ag_config - L1ISP AG parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG`
> + * @gain_h: Analog gain for high sensitive image [0..65535]
> + * @gain_m: Analog gain for middle sensitive image or LED image [0..65535]
> + * @gain_l: Analog gain for low sensitive image [0..65535]
> + */
> +struct viif_l1_ag_config {
> + __u16 gain_h;
> + __u16 gain_m;
> + __u16 gain_l;
> +};
> +
> +/**
> + * struct viif_l1_hdre_config - L1ISP HDRE parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE`
> + * @hdre_src_point: Knee point N value of PWL compressed signal [0..0x3FFF]
> + * @hdre_dst_base: Offset value of HDR signal in Knee area M [0..0xFFFFFF]
> + * @hdre_ratio: Slope of output pixel value in Knee area M
> + * [0..0x3FFFFF], accuracy: 1/64
> + * @hdre_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
> + */
> +struct viif_l1_hdre_config {
> + __u32 hdre_src_point[16];
> + __u32 hdre_dst_base[17];
> + __u32 hdre_ratio[17];
> + __u32 hdre_dst_max_val;
> +};
> +
> +/**
> + * struct viif_l1_img_extraction_config - L1ISP image extraction parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION`
> + * @input_black_gr: Black level of input pixel (Gr) [0..0xFFFFFF]
> + * @input_black_r: Black level of input pixel (R) [0..0xFFFFFF]
> + * @input_black_b: Black level of input pixel (B) [0..0xFFFFFF]
> + * @input_black_gb: Black level of input pixel (Gb) [0..0xFFFFFF]
> + */
> +struct viif_l1_img_extraction_config {
> + __u32 input_black_gr;
> + __u32 input_black_r;
> + __u32 input_black_b;
> + __u32 input_black_gb;
> +};
> +
> +/**
> + * enum viif_l1_dpc_mode - L1ISP defect pixel correction mode
> + * @VIIF_L1_DPC_1PIXEL: 1 pixel correction mode
> + * @VIIF_L1_DPC_2PIXEL: 2 pixel correction mode
> + */
> +enum viif_l1_dpc_mode {
> + VIIF_L1_DPC_1PIXEL = 0,
> + VIIF_L1_DPC_2PIXEL = 1,
> +};
> +
> +/**
> + * struct viif_l1_dpc - L1ISP defect pixel correction parameters
> + * for &struct viif_l1_dpc_config
> + * @abpc_sta_en: 1:enable/0:disable setting of Static DPC
> + * @abpc_dyn_en: 1:enable/0:disable setting of Dynamic DPC
> + * @abpc_dyn_mode: &enume viif_l1_dpc_mode value. Sets dynamic DPC mode.
> + * @abpc_ratio_limit: Variation adjustment of dynamic DPC [0..1023]
> + * @abpc_dark_limit: White defect judgment limit of dark area [0..1023]
> + * @abpc_sn_coef_w_ag_min: Luminance difference adjustment of white DPC
> + * (undere lower threshold) [1..31]
> + * @abpc_sn_coef_w_ag_mid: Luminance difference adjustment of white DPC
> + * (between lower and upper threshold) [1..31]
> + * @abpc_sn_coef_w_ag_max: Luminance difference adjustment of white DPC
> + * (over upper threshold) [1..31]
> + * @abpc_sn_coef_b_ag_min: Luminance difference adjustment of black DPC
> + * (undere lower threshold) [1..31]
> + * @abpc_sn_coef_b_ag_mid: Luminance difference adjustment of black DPC
> + * (between lower and upper threshold) [1..31]
> + * @abpc_sn_coef_b_ag_max: Luminance difference adjustment of black DPC
> + * (over upper threshold) [1..31]
> + * @abpc_sn_coef_w_th_min: Luminance difference adjustment of white DPC
> + * analog gain lower threshold [0..255]
> + * @abpc_sn_coef_w_th_max: Luminance difference adjustment of white DPC
> + * analog gain upper threshold [0..255]
> + * @abpc_sn_coef_b_th_min: Luminance difference adjustment of black DPC
> + * analog gain lower threshold [0..255]
> + * @abpc_sn_coef_b_th_max: Luminance difference adjustment of black DPC
> + * analog gain upper threshold [0..255]
> + *
> + * Parameters should meet the following conditions.
> + * "abpc_sn_coef_w_th_min < abpc_sn_coef_w_th_max" and
> + * "abpc_sn_coef_b_th_min < abpc_sn_coef_b_th_max"
> + */
> +struct viif_l1_dpc {
> + __u32 abpc_sta_en;
> + __u32 abpc_dyn_en;
> + __u32 abpc_dyn_mode;
> + __u32 abpc_ratio_limit;
> + __u32 abpc_dark_limit;
> + __u32 abpc_sn_coef_w_ag_min;
> + __u32 abpc_sn_coef_w_ag_mid;
> + __u32 abpc_sn_coef_w_ag_max;
> + __u32 abpc_sn_coef_b_ag_min;
> + __u32 abpc_sn_coef_b_ag_mid;
> + __u32 abpc_sn_coef_b_ag_max;
> + __u8 abpc_sn_coef_w_th_min;
> + __u8 abpc_sn_coef_w_th_max;
> + __u8 abpc_sn_coef_b_th_min;
> + __u8 abpc_sn_coef_b_th_max;
> +};
> +
> +/**
> + * struct viif_l1_dpc_config - L1ISP defect pixel correction parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC`
> + * @param_h: DPC parameter for high sensitive image. Refer to &struct viif_l1_dpc
> + * @param_m: DPC parameter for middle sensitive image. Refer to &struct viif_l1_dpc
> + * @param_l: DPC parameter for low sensitive image. Refer to &struct viif_l1_dpc
> + * @table_h_addr: DPC table address for high sensitive image.
> + * The table size is sizeof(u32) * 2048.
> + * Set zero to disable this table.
> + * @table_m_addr: DPC table address for middle sensitive image or LED image.
> + * The table size is sizeof(u32) * 2048.
> + * Set zero to disable this table.
> + * @table_l_addr: DPC table address for low sensitive image.
> + * The table size is sizeof(u32) * 2048.
> + * Set zero to disable this table.
> + *
> + * The size of each table is fixed at 8192 Byte.
> + * Application should make sure that the table data is based on HW specification
> + * since this driver does not check the DPC table.
> + */
> +struct viif_l1_dpc_config {
> + struct viif_l1_dpc param_h;
> + struct viif_l1_dpc param_m;
> + struct viif_l1_dpc param_l;
> + __u64 table_h_addr;
> + __u64 table_m_addr;
> + __u64 table_l_addr;
> +};
> +
> +/**
> + * struct viif_l1_preset_wb - L1ISP preset white balance parameters
> + * for &struct viif_l1_preset_white_balance_config
> + * @gain_gr: Gr gain [0..524287], accuracy 1/16384
> + * @gain_r: R gain [0..524287], accuracy 1/16384
> + * @gain_b: B gain [0..524287], accuracy 1/16384
> + * @gain_gb: Gb gain [0..524287], accuracy 1/16384
> + */
> +struct viif_l1_preset_wb {
> + __u32 gain_gr;
> + __u32 gain_r;
> + __u32 gain_b;
> + __u32 gain_gb;
> +};
> +
> +/**
> + * struct viif_l1_preset_white_balance_config - L1ISP preset white balance
> + * parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE`
> + * @dstmaxval: Maximum value of output pixel [pixel] [0..4095]
> + * @param_h: Preset white balance parameter for high sensitive image.
> + * Refer to &struct viif_l1_preset_wb
> + * @param_m: Preset white balance parameters for middle sensitive image or LED image.
> + * Refer to &struct viif_l1_preset_wb
> + * @param_l: Preset white balance parameters for low sensitive image.
> + * Refer to &struct viif_l1_preset_wb
> + */
> +struct viif_l1_preset_white_balance_config {
> + __u32 dstmaxval;
> + struct viif_l1_preset_wb param_h;
> + struct viif_l1_preset_wb param_m;
> + struct viif_l1_preset_wb param_l;
> +};
> +
> +/**
> + * enum viif_l1_rcnr_type - L1ISP high resolution luminance filter type
> + *
> + * @VIIF_L1_RCNR_LOW_RESOLUTION: low resolution
> + * @VIIF_L1_RCNR_MIDDLE_RESOLUTION: middle resolution
> + * @VIIF_L1_RCNR_HIGH_RESOLUTION: high resolution
> + * @VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION: ultra high resolution
> + */
> +enum viif_l1_rcnr_type {
> + VIIF_L1_RCNR_LOW_RESOLUTION = 0,
> + VIIF_L1_RCNR_MIDDLE_RESOLUTION = 1,
> + VIIF_L1_RCNR_HIGH_RESOLUTION = 2,
> + VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION = 3,
> +};
> +
> +/**
> + * enum viif_l1_msf_blend_ratio - L1ISP MSF blend ratio
> + *
> + * @VIIF_L1_MSF_BLEND_RATIO_0_DIV_64: 0/64
> + * @VIIF_L1_MSF_BLEND_RATIO_1_DIV_64: 1/64
> + * @VIIF_L1_MSF_BLEND_RATIO_2_DIV_64: 2/64
> + */
> +enum viif_l1_msf_blend_ratio {
> + VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 = 0,
> + VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 = 1,
> + VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 = 2,
> +};
> +
> +/**
> + * struct viif_l1_raw_color_noise_reduction - L1ISP RCNR parameters
> + * for &struct viif_l1_raw_color_noise_reduction_config
> + * @rcnr_sw: 1:Enable/0:Disable setting of RAW color noise reduction
> + * @rcnr_cnf_dark_ag0: Maximum value of LSF dark noise adjustment[0..63]
> + * @rcnr_cnf_dark_ag1: Middle value of LSF dark noise adjustment [0..63]
> + * @rcnr_cnf_dark_ag2: Minimum value of LSF dark noise adjustment [0..63]
> + * @rcnr_cnf_ratio_ag0: Maximum value of LSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_cnf_ratio_ag1: Middle value of LSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_cnf_ratio_ag2: Minimum value of LSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_cnf_clip_gain_r: LSF color correction limit adjustment gain R [0..3]
> + * @rcnr_cnf_clip_gain_g: LSF color correction limit adjustment gain G [0..3]
> + * @rcnr_cnf_clip_gain_b: LSF color correction limit adjustment gain B [0..3]
> + * @rcnr_a1l_dark_ag0: Maximum value of MSF dark noise adjustment [0..63]
> + * @rcnr_a1l_dark_ag1: Middle value of MSF dark noise adjustment [0..63]
> + * @rcnr_a1l_dark_ag2: Minimum value of MSF dark noise adjustment [0..63]
> + * @rcnr_a1l_ratio_ag0: Maximum value of MSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_a1l_ratio_ag1: Middle value of MSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_a1l_ratio_ag2: Minimum value of MSF luminance interlocking noise adjustment [0..31]
> + * @rcnr_inf_zero_clip: Input stage zero clip setting [0..256]
> + * @rcnr_merge_d2blend_ag0: Maximum value of filter results and input blend ratio [0..16]
> + * @rcnr_merge_d2blend_ag1: Middle value of filter results and input blend ratio [0..16]
> + * @rcnr_merge_d2blend_ag2: Minimum value of filter results and input blend ratio [0..16]
> + * @rcnr_merge_black: Black level minimum value [0..64]
> + * @rcnr_merge_mindiv: 0 div guard value of inverse arithmetic unit [4..16]
> + * @rcnr_hry_type: &enum viif_l1_rcnr_type value. Filter type for HSF filter process.
> + * @rcnr_anf_blend_ag0: &enum viif_l1_msf_blend_ratio value.
> + * Maximum value of MSF result blend ratio in write back data to line memory.
> + * @rcnr_anf_blend_ag1: &enum viif_l1_msf_blend_ratio value.
> + * Middle value of MSF result blend ratio in write back data to line memory.
> + * @rcnr_anf_blend_ag2: &enum viif_l1_msf_blend_ratio value.
> + * Minimum value of MSF result blend ratio in write back data to line memory.
> + * @rcnr_lpf_threshold: Multiplier value for calculating dark noise / luminance
> + * interlock noise of MSF [0..31], accuracy: 1/8
> + * @rcnr_merge_hlblend_ag0: Maximum value of luminance signal generation blend [0..2]
> + * @rcnr_merge_hlblend_ag1: Middle value of luminance signal generation blend [0..2]
> + * @rcnr_merge_hlblend_ag2: Minimum value of luminance signal generation blend [0..2]
> + * @rcnr_gnr_sw: 1:Enable/0:Disable setting of Gr/Gb sensitivity ratio
> + * correction function switching
> + * @rcnr_gnr_ratio: Upper limit of Gr/Gb sensitivity ratio correction factor [0..15]
> + * @rcnr_gnr_wide_en: 1:Enable/0:Disable setting of the function to double
> + * correction upper limit ratio of rcnr_gnr_ratio
> + */
> +struct viif_l1_raw_color_noise_reduction {
> + __u32 rcnr_sw;
> + __u32 rcnr_cnf_dark_ag0;
> + __u32 rcnr_cnf_dark_ag1;
> + __u32 rcnr_cnf_dark_ag2;
> + __u32 rcnr_cnf_ratio_ag0;
> + __u32 rcnr_cnf_ratio_ag1;
> + __u32 rcnr_cnf_ratio_ag2;
> + __u32 rcnr_cnf_clip_gain_r;
> + __u32 rcnr_cnf_clip_gain_g;
> + __u32 rcnr_cnf_clip_gain_b;
> + __u32 rcnr_a1l_dark_ag0;
> + __u32 rcnr_a1l_dark_ag1;
> + __u32 rcnr_a1l_dark_ag2;
> + __u32 rcnr_a1l_ratio_ag0;
> + __u32 rcnr_a1l_ratio_ag1;
> + __u32 rcnr_a1l_ratio_ag2;
> + __u32 rcnr_inf_zero_clip;
> + __u32 rcnr_merge_d2blend_ag0;
> + __u32 rcnr_merge_d2blend_ag1;
> + __u32 rcnr_merge_d2blend_ag2;
> + __u32 rcnr_merge_black;
> + __u32 rcnr_merge_mindiv;
> + __u32 rcnr_hry_type;
> + __u32 rcnr_anf_blend_ag0;
> + __u32 rcnr_anf_blend_ag1;
> + __u32 rcnr_anf_blend_ag2;
> + __u32 rcnr_lpf_threshold;
> + __u32 rcnr_merge_hlblend_ag0;
> + __u32 rcnr_merge_hlblend_ag1;
> + __u32 rcnr_merge_hlblend_ag2;
> + __u32 rcnr_gnr_sw;
> + __u32 rcnr_gnr_ratio;
> + __u32 rcnr_gnr_wide_en;
> +};
> +
> +/**
> + * struct viif_l1_raw_color_noise_reduction_config - L1ISP RCNR parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION`
> + * @param_h: RAW color noise reduction parameter for high sensitive image.
> + * Refer to &struct viif_l1_raw_color_noise_reduction
> + * @param_m: RAW color noise reduction parameter for middle sensitive image or LED image.
> + * Refer to &struct viif_l1_raw_color_noise_reduction
> + * @param_l: RAW color noise reduction parameter for low sensitive image.
> + * Refer to &struct viif_l1_raw_color_noise_reduction
> + */
> +struct viif_l1_raw_color_noise_reduction_config {
> + struct viif_l1_raw_color_noise_reduction param_h;
> + struct viif_l1_raw_color_noise_reduction param_m;
> + struct viif_l1_raw_color_noise_reduction param_l;
> +};
> +
> +/**
> + * enum viif_l1_hdrs_middle_img_mode - L1ISP HDR setting
> + *
> + * @VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE: not use middle image
> + * @VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE: use middle image
> + */
> +enum viif_l1_hdrs_middle_img_mode {
> + VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE = 0,
> + VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE = 1,
> +};
> +
> +/**
> + * struct viif_l1_hdrs_config - L1ISP HDRS parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS`
> + * @hdrs_hdr_mode: &enum viif_l1_hdrs_middle_img_mode value.
> + * Use/No use settings of middle sensitivity image in HDRS.
> + * @hdrs_hdr_ratio_m: Magnification ratio of middle sensitivity image for high
> + * sensitivity image [0x400..0x400000] accuracy: 1/1024
> + * @hdrs_hdr_ratio_l: Magnification ratio of low sensitivity image for high
> + * sensitivity image [0x400..0x400000], accuracy: 1/1024
> + * @hdrs_hdr_ratio_e: Magnification ratio of LED image for high sensitivity image
> + * [0x400..0x400000], accuracy: 1/1024
> + * @hdrs_dg_h: High sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_dg_m: Middle sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_dg_l: Low sensitivity image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_dg_e: LED image digital gain [0..0x3FFFFF], accuracy: 1/1024
> + * @hdrs_blendend_h: Maximum luminance used for blend high sensitivity image [0..4095]
> + * @hdrs_blendend_m: Maximum luminance used for blend middle sensitivity image [0..4095]
> + * @hdrs_blendend_e: Maximum luminance used for blend LED image [0..4095]
> + * @hdrs_blendbeg_h: Minimum luminance used for blend high sensitivity image [0..4095]
> + * @hdrs_blendbeg_m: Minimum luminance used for blend middle sensitivity image [0..4095]
> + * @hdrs_blendbeg_e: Minimum luminance used for blend LED image [0..4095]
> + * @hdrs_led_mode_on: 1:Enable/0:Disable settings of LED mode
> + * @hdrs_dst_max_val: Maximum value of output pixel [0..0xFFFFFF]
> + *
> + * parameter error needs to be returned in the below condition.
> + * (hdrs_hdr_mode == VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) && (hdrs_led_mode_on == 1)
> + */
> +struct viif_l1_hdrs_config {
> + __u32 hdrs_hdr_mode;
> + __u32 hdrs_hdr_ratio_m;
> + __u32 hdrs_hdr_ratio_l;
> + __u32 hdrs_hdr_ratio_e;
> + __u32 hdrs_dg_h;
> + __u32 hdrs_dg_m;
> + __u32 hdrs_dg_l;
> + __u32 hdrs_dg_e;
> + __u32 hdrs_blendend_h;
> + __u32 hdrs_blendend_m;
> + __u32 hdrs_blendend_e;
> + __u32 hdrs_blendbeg_h;
> + __u32 hdrs_blendbeg_m;
> + __u32 hdrs_blendbeg_e;
> + __u32 hdrs_led_mode_on;
> + __u32 hdrs_dst_max_val;
> +};
> +
> +/**
> + * struct viif_l1_black_level_correction_config - L1ISP image level conversion
> + * parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION`
> + * @srcblacklevel_gr: Black level of Gr input pixel [pixel] [0..0xFFFFFF]
> + * @srcblacklevel_r: Black level of R input pixel [pixel] [0..0xFFFFFF]
> + * @srcblacklevel_b: Black level of B input pixel [pixel] [0..0xFFFFFF]
> + * @srcblacklevel_gb: Black level of Gb input pixel [pixel] [0..0xFFFFFF]
> + * @mulval_gr: Gr gain [0..0xFFFFF], accuracy: 1/256
> + * @mulval_r: R gain [0..0xFFFFF], accuracy: 1/256
> + * @mulval_b: B gain [0..0xFFFFF], accuracy: 1/256
> + * @mulval_gb: Gb gain [0..0xFFFFF], accuracy: 1/256
> + * @dstmaxval: Maximum value of output pixel [pixel] [0..0xFFFFFF]
> + */
> +struct viif_l1_black_level_correction_config {
> + __u32 srcblacklevel_gr;
> + __u32 srcblacklevel_r;
> + __u32 srcblacklevel_b;
> + __u32 srcblacklevel_gb;
> + __u32 mulval_gr;
> + __u32 mulval_r;
> + __u32 mulval_b;
> + __u32 mulval_gb;
> + __u32 dstmaxval;
> +};
> +
> +/**
> + * enum viif_l1_para_coef_gain - L1ISP parabola shading correction coefficient ratio
> + *
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH: 1/8
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH: 1/4
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_SECOND: 1/2
> + * @VIIF_L1_PARA_COEF_GAIN_ONE_FIRST: 1/1
> + */
> +enum viif_l1_para_coef_gain {
> + VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH = 0, /* 1/8 */
> + VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH = 1, /* 1/4 */
> + VIIF_L1_PARA_COEF_GAIN_ONE_SECOND = 2, /* 1/2 */
> + VIIF_L1_PARA_COEF_GAIN_ONE_FIRST = 3, /* 1/1 */
> +};
> +
> +/**
> + * enum viif_l1_grid_coef_gain - L1ISP grid shading correction coefficient ratio
> + *
> + * @VIIF_L1_GRID_COEF_GAIN_X1: x1
> + * @VIIF_L1_GRID_COEF_GAIN_X2: x2
> + */
> +enum viif_l1_grid_coef_gain {
> + VIIF_L1_GRID_COEF_GAIN_X1 = 0,
> + VIIF_L1_GRID_COEF_GAIN_X2 = 1,
> +};
> +
> +/**
> + * struct viif_l1_lsc_parabola_ag_param - L2ISP parabola shading parameters
> + * for &struct viif_l1_lsc_parabola_param
> + * @lssc_paracoef_h_l_max: Parabola coefficient left maximum gain value
> + * @lssc_paracoef_h_l_min: Parabola coefficient left minimum gain value
> + * @lssc_paracoef_h_r_max: Parabola coefficient right maximum gain value
> + * @lssc_paracoef_h_r_min: Parabola coefficient right minimum gain value
> + * @lssc_paracoef_v_u_max: Parabola coefficient upper maximum gain value
> + * @lssc_paracoef_v_u_min: Parabola coefficient upper minimum gain value
> + * @lssc_paracoef_v_d_max: Parabola coefficient lower maximum gain value
> + * @lssc_paracoef_v_d_min: Parabola coefficient lower minimum gain value
> + * @lssc_paracoef_hv_lu_max: Parabola coefficient upper left gain maximum value
> + * @lssc_paracoef_hv_lu_min: Parabola coefficient upper left gain minimum value
> + * @lssc_paracoef_hv_ru_max: Parabola coefficient upper right gain maximum value
> + * @lssc_paracoef_hv_ru_min: Parabola coefficient upper right minimum gain value
> + * @lssc_paracoef_hv_ld_max: Parabola coefficient lower left gain maximum value
> + * @lssc_paracoef_hv_ld_min: Parabola coefficient lower left gain minimum value
> + * @lssc_paracoef_hv_rd_max: Parabola coefficient lower right gain maximum value
> + * @lssc_paracoef_hv_rd_min: Parabola coefficient lower right minimum gain value
> + *
> + * The range and accuracy of each coefficient are as
> + * "range: [-4096..4095], accuracy: 1/256 "
> + *
> + * Each coefficient should meet the following conditions.
> + * "lssc_paracoef_xx_xx_min <= lssc_paracoef_xx_xx_max"
> + */
> +struct viif_l1_lsc_parabola_ag_param {
> + __s16 lssc_paracoef_h_l_max;
> + __s16 lssc_paracoef_h_l_min;
> + __s16 lssc_paracoef_h_r_max;
> + __s16 lssc_paracoef_h_r_min;
> + __s16 lssc_paracoef_v_u_max;
> + __s16 lssc_paracoef_v_u_min;
> + __s16 lssc_paracoef_v_d_max;
> + __s16 lssc_paracoef_v_d_min;
> + __s16 lssc_paracoef_hv_lu_max;
> + __s16 lssc_paracoef_hv_lu_min;
> + __s16 lssc_paracoef_hv_ru_max;
> + __s16 lssc_paracoef_hv_ru_min;
> + __s16 lssc_paracoef_hv_ld_max;
> + __s16 lssc_paracoef_hv_ld_min;
> + __s16 lssc_paracoef_hv_rd_max;
> + __s16 lssc_paracoef_hv_rd_min;
> +};
> +
> +/**
> + * struct viif_l1_lsc_parabola_param - L2ISP parabola shading parameters
> + * for &struct viif_l1_lsc
> + * @lssc_para_h_center: Horizontal coordinate of central optical axis [pixel]
> + * [0..(Input image width - 1)]
> + * @lssc_para_v_center: Vertical coordinate of central optical axis [line]
> + * [0..(Input image height - 1)]
> + * @lssc_para_h_gain: Horizontal distance gain with the optical axis
> + * [0..4095], accuracy: 1/256
> + * @lssc_para_v_gain: Vertical distance gain with the optical axis
> + * [0..4095], accuracy: 1/256
> + * @lssc_para_mgsel2: &enum viif_l1_para_coef_gain value.
> + * Parabola 2D correction coefficient gain magnification ratio.
> + * @lssc_para_mgsel4: &enum viif_l1_para_coef_gain value.
> + * Parabola 4D correction coefficient gain magnification ratio.
> + * @r_2d: 2D parabola coefficient for R.
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @r_4d: 4D parabola coefficient for R.
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gr_2d: 2D parabola coefficient for Gr
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gr_4d: 4D parabola coefficient for Gr
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gb_2d: 2D parabola coefficient for Gb
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @gb_4d: 4D parabola coefficient for Gb
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @b_2d: 2D parabola coefficient for B
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + * @b_4d: 4D parabola coefficient for B
> + * Refer to &struct viif_l1_lsc_parabola_ag_param
> + */
> +struct viif_l1_lsc_parabola_param {
> + __u32 lssc_para_h_center;
> + __u32 lssc_para_v_center;
> + __u32 lssc_para_h_gain;
> + __u32 lssc_para_v_gain;
> + __u32 lssc_para_mgsel2;
> + __u32 lssc_para_mgsel4;
> + struct viif_l1_lsc_parabola_ag_param r_2d;
> + struct viif_l1_lsc_parabola_ag_param r_4d;
> + struct viif_l1_lsc_parabola_ag_param gr_2d;
> + struct viif_l1_lsc_parabola_ag_param gr_4d;
> + struct viif_l1_lsc_parabola_ag_param gb_2d;
> + struct viif_l1_lsc_parabola_ag_param gb_4d;
> + struct viif_l1_lsc_parabola_ag_param b_2d;
> + struct viif_l1_lsc_parabola_ag_param b_4d;
> +};
> +
> +/**
> + * struct viif_l1_lsc_grid_param - L2ISP grid shading parameters
> + * for &struct viif_l1_lsc
> + * @lssc_grid_h_size: Grid horizontal direction pixel count [32, 64, 128, 256, 512]
> + * @lssc_grid_v_size: Grid vertical direction pixel count [32, 64, 128, 256, 512]
> + * @lssc_grid_h_center: Horizontal coordinates of grid (1, 1) [pixel] [1..lssc_grid_h_size]
> + * Should meet the following condition.
> + * "Input image width <= lssc_grid_h_center + lssc_grid_h_size * 31"
> + * @lssc_grid_v_center: Vertical coordinates of grid (1, 1) [line] [1..lssc_grid_v_size]
> + * Should meet the following condition.
> + * "Input image height <= lssc_grid_v_center + lssc_grid_v_size * 23"
> + * @lssc_grid_mgsel: &enum viif_l1_grid_coef_gain value.
> + * Grid correction coefficient gain value magnification ratio.
> + */
> +struct viif_l1_lsc_grid_param {
> + __u32 lssc_grid_h_size;
> + __u32 lssc_grid_v_size;
> + __u32 lssc_grid_h_center;
> + __u32 lssc_grid_v_center;
> + __u32 lssc_grid_mgsel;
> +};
> +
> +/**
> + * struct viif_l1_lsc - L2ISP LSC parameters for &struct viif_l1_lsc_config
> + * @lssc_parabola_param_addr: Address of a &struct viif_l1_lsc_parabola_param instance.
> + * Set 0 to disable parabola shading correction.
> + * @lssc_grid_param_addr: Address of a &struct viif_l1_lsc_grid_param instance,
> + * Set 0 to disable grid shading correction.
> + * @lssc_pwhb_r_gain_max: PWB R correction processing coefficient maximum value
> + * @lssc_pwhb_r_gain_min: PWB R correction processing coefficient minimum value
> + * @lssc_pwhb_gr_gain_max: PWB Gr correction processing coefficient maximum value
> + * @lssc_pwhb_gr_gain_min: PWB Gr correction processing coefficient minimum value
> + * @lssc_pwhb_gb_gain_max: PWB Gb correction processing coefficient maximum value
> + * @lssc_pwhb_gb_gain_min: PWB Gb correction processing coefficient minimum value
> + * @lssc_pwhb_b_gain_max: PWB B correction processing coefficient maximum value
> + * @lssc_pwhb_b_gain_min: PWB B correction processing coefficient minimum value
> + *
> + * The range and accuracy of preset white balance (PWB) correction process
> + * coefficient (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) are as below.
> + * "range: [0..2047], accuracy: 1/256"
> + *
> + * PWB correction process coefficient
> + * (lssc_pwhb_{r/gr/gb/b}_gain_{max/min}) should meet the following conditions.
> + * "lssc_pwhb_{r/gr/gb/b}_gain_min <= lssc_pwhb_{r/gr/gb/b}_gain_max"
> + */
> +struct viif_l1_lsc {
> + __u64 lssc_parabola_param_addr;
> + __u64 lssc_grid_param_addr;
> + __u32 lssc_pwhb_r_gain_max;
> + __u32 lssc_pwhb_r_gain_min;
> + __u32 lssc_pwhb_gr_gain_max;
> + __u32 lssc_pwhb_gr_gain_min;
> + __u32 lssc_pwhb_gb_gain_max;
> + __u32 lssc_pwhb_gb_gain_min;
> + __u32 lssc_pwhb_b_gain_max;
> + __u32 lssc_pwhb_b_gain_min;
> +};
> +
> +/**
> + * struct viif_l1_lsc_config - L2ISP LSC parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC`
> + * @param_addr: Address of a &struct viif_l1_lsc instance.
> + * Set 0 to disable LSC operation.
> + * @table_gr_addr: Address of the grid table for LSC of Gr component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + * @table_r_addr: Address of the grid table for LSC of R component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + * @table_b_addr: Address of the grid table for LSC of B component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + * @table_gb_addr: Address of the grid table for LSC of Gb component.
> + * The table size is sizeof(u16) * 768.
> + * Set 0 to disable this table.
> + *
> + * The size of each table is fixed to 1,536 Bytes.
> + * Application should make sure that the table data is based on HW specification
> + * since this driver does not check the grid table.
> + */
> +struct viif_l1_lsc_config {
> + __u64 param_addr;
> + __u64 table_gr_addr;
> + __u64 table_r_addr;
> + __u64 table_b_addr;
> + __u64 table_gb_addr;
> +};
> +
> +/**
> + * enum viif_l1_demosaic_mode - L1ISP demosaic modeenum viif_l1_demosaic_mode
> + *
> + * @VIIF_L1_DEMOSAIC_ACPI: Toshiba ACPI algorithm
> + * @VIIF_L1_DEMOSAIC_DMG: DMG algorithm
> + */
> +enum viif_l1_demosaic_mode {
> + VIIF_L1_DEMOSAIC_ACPI = 0,
> + VIIF_L1_DEMOSAIC_DMG = 1,
> +};
> +
> +/**
> + * struct viif_l1_color_matrix_correction - L1ISP color matrix correction
> + * parameters for &struct viif_l1_main_process_config
> + * @coef_rmg_min: (R-G) Minimum coefficient
> + * @coef_rmg_max: (R-G) Maximum coefficient
> + * @coef_rmb_min: (R-B) Minimum coefficient
> + * @coef_rmb_max: (R-B) Maximum coefficient
> + * @coef_gmr_min: (G-R) Minimum coefficient
> + * @coef_gmr_max: (G-R) Maximum coefficient
> + * @coef_gmb_min: (G-B) Minimum coefficient
> + * @coef_gmb_max: (G-B) Maximum coefficient
> + * @coef_bmr_min: (B-R) Minimum coefficient
> + * @coef_bmr_max: (B-R) Maximum coefficient
> + * @coef_bmg_min: (B-G) Minimum coefficient
> + * @coef_bmg_max: (B-G) Maximum coefficient
> + * @dst_minval: Minimum value of output pixel [0..0xFFFF] [pixel]
> + *
> + * The range and accuracy of each coefficient are as
> + * "range: [-32768..32767], accuracy: 1/ 4096"
> + *
> + * Also, each coefficient should meet "coef_xxx_min <= coef_xxx_max" condition
> + */
> +struct viif_l1_color_matrix_correction {
> + __s16 coef_rmg_min;
> + __s16 coef_rmg_max;
> + __s16 coef_rmb_min;
> + __s16 coef_rmb_max;
> + __s16 coef_gmr_min;
> + __s16 coef_gmr_max;
> + __s16 coef_gmb_min;
> + __s16 coef_gmb_max;
> + __s16 coef_bmr_min;
> + __s16 coef_bmr_max;
> + __s16 coef_bmg_min;
> + __s16 coef_bmg_max;
> + __u16 dst_minval;
> +};
> +
> +/**
> + * struct viif_l1_main_process_config - L1ISP Main process operating parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS`
> + * @demosaic_mode: &enum viif_l1_demosaic_mode value. Sets demosaic mode.
> + * @damp_lsbsel: Clipping range of output pixel value to AWB adjustment function [0..15]
> + * @param_addr: Address to a &struct viif_l1_color_matrix_correction instance.
> + * Set 0 to disable color matrix correction.
> + * @dst_maxval: Maximum value of output pixel [0..0xFFFFFF].
> + * Applicable to output of each process (digital amplifier,
> + * demosaicing and color matrix correction) in L1ISP Main process.
> + */
> +struct viif_l1_main_process_config {
> + __u32 demosaic_mode;
> + __u32 damp_lsbsel;
> + __u64 param_addr;
> + __u32 dst_maxval;
> +};
> +
> +/**
> + * enum viif_l1_awb_mag - L1ISP signal magnification before AWB adjustment
> + *
> + * @VIIF_L1_AWB_ONE_SECOND: x 1/2
> + * @VIIF_L1_AWB_X1: 1 times
> + * @VIIF_L1_AWB_X2: 2 times
> + * @VIIF_L1_AWB_X4: 4 times
> + */
> +enum viif_l1_awb_mag {
> + VIIF_L1_AWB_ONE_SECOND = 0,
> + VIIF_L1_AWB_X1 = 1,
> + VIIF_L1_AWB_X2 = 2,
> + VIIF_L1_AWB_X4 = 3,
> +};
> +
> +/**
> + * enum viif_l1_awb_area_mode - L1ISP AWB detection target area
> + *
> + * @VIIF_L1_AWB_AREA_MODE0: only center area
> + * @VIIF_L1_AWB_AREA_MODE1: center area when uv is in square gate
> + * @VIIF_L1_AWB_AREA_MODE2: all area except center area
> + * @VIIF_L1_AWB_AREA_MODE3: all area
> + */
> +enum viif_l1_awb_area_mode {
> + VIIF_L1_AWB_AREA_MODE0 = 0,
> + VIIF_L1_AWB_AREA_MODE1 = 1,
> + VIIF_L1_AWB_AREA_MODE2 = 2,
> + VIIF_L1_AWB_AREA_MODE3 = 3,
> +};
> +
> +/**
> + * enum viif_l1_awb_restart_cond - L1ISP AWB adjustment restart conditions
> + *
> + * @VIIF_L1_AWB_RESTART_NO: no restart
> + * @VIIF_L1_AWB_RESTART_128FRAME: restart after 128 frame
> + * @VIIF_L1_AWB_RESTART_64FRAME: restart after 64 frame
> + * @VIIF_L1_AWB_RESTART_32FRAME: restart after 32 frame
> + * @VIIF_L1_AWB_RESTART_16FRAME: restart after 16 frame
> + * @VIIF_L1_AWB_RESTART_8FRAME: restart after 8 frame
> + * @VIIF_L1_AWB_RESTART_4FRAME: restart after 4 frame
> + * @VIIF_L1_AWB_RESTART_2FRAME: restart after 2 frame
> + */
> +enum viif_l1_awb_restart_cond {
> + VIIF_L1_AWB_RESTART_NO = 0,
> + VIIF_L1_AWB_RESTART_128FRAME = 1,
> + VIIF_L1_AWB_RESTART_64FRAME = 2,
> + VIIF_L1_AWB_RESTART_32FRAME = 3,
> + VIIF_L1_AWB_RESTART_16FRAME = 4,
> + VIIF_L1_AWB_RESTART_8FRAME = 5,
> + VIIF_L1_AWB_RESTART_4FRAME = 6,
> + VIIF_L1_AWB_RESTART_2FRAME = 7,
> +};
> +
> +/**
> + * struct viif_l1_awb - L1ISP AWB adjustment parameters
> + * for &struct viif_l1_awb_config
> + * @awhb_ygate_sel: 1:Enable/0:Disable to fix Y value at YUV conversion
> + * @awhb_ygate_data: Y value in case Y value is fixed [64, 128, 256, 512]
> + * @awhb_cgrange: &enum viif_l1_awb_mag value.
> + * Signal output magnification ratio before AWB adjustment.
> + * @awhb_ygatesw: 1:Enable/0:Disable settings of luminance gate
> + * @awhb_hexsw: 1:Enable/0:Disable settings of hexa-gate
> + * @awhb_areamode: &enum viif_l1_awb_area_mode value.
> + * Final selection of accumulation area for detection target area.
> + * @awhb_area_hsize: Horizontal size per block in central area [pixel]
> + * [1..(Input image width -8)/8]
> + * @awhb_area_vsize: Vertical size per block in central area [line]
> + * [1..(Input image height -4)/8]
> + * @awhb_area_hofs: Horizontal offset of block [0] in central area [pixel]
> + * [0..(Input image width -9)]
> + * @awhb_area_vofs: Vertical offset of block [0] in central area [line]
> + * [0..(Input image height -5)]
> + * @awhb_area_maskh: Setting 1:Enable/0:Disable( of accumulated selection.
> + * Each bit implies the following.
> + * [31:0] = {
> + * (7, 3),(6, 3),(5, 3),(4, 3),(3, 3),(2, 3),(1, 3),(0, 3),
> + * (7, 2),(6, 2),(5, 2),(4, 2),(3, 2),(2, 2),(1, 2),(0, 2),
> + * (7, 1),(6, 1),(5, 1),(4, 1),(3, 1),(2, 1),(1, 1),(0, 1),
> + * (7, 0),(6, 0),(5, 0),(4, 0),(3, 0),(2, 0),(1, 0),(0, 0)}
> + * @awhb_area_maskl: Setting 1:Enable/0:Disable of accumulated selection.
> + * Each bit implies the following.
> + * [31:0] = {
> + * (7, 7),(6, 7),(5, 7),(4, 7),(3, 7),(2, 7),(1, 7),(0, 7),
> + * (7, 6),(6, 6),(5, 6),(4, 6),(3, 6),(2, 6),(1, 6),(0, 6),
> + * (7, 5),(6, 5),(5, 5),(4, 5),(3, 5),(2, 5),(1, 5),(0, 5),
> + * (7, 4),(6, 4),(5, 4),(4, 4),(3, 4),(2, 4),(1, 4),(0, 4)}
> + * @awhb_sq_sw: 1:Enable/0:Disable each square gate
> + * @awhb_sq_pol: 1:Enable/0:Disable to add accumulated gate for each square gate
> + * @awhb_bycut0p: U upper end value [pixel] [0..127]
> + * @awhb_bycut0n: U lower end value [pixel] [0..127]
> + * @awhb_rycut0p: V upper end value [pixel] [0..127]
> + * @awhb_rycut0n: V lower end value [pixel] [0..127]
> + * @awhb_rbcut0h: V-axis intercept upper end [pixel] [-127..127]
> + * @awhb_rbcut0l: V-axis intercept lower end [pixel] [-127..127]
> + * @awhb_bycut_h: U direction center value of each square gate [-127..127]
> + * @awhb_bycut_l: U direction width of each square gate [0..127]
> + * @awhb_rycut_h: V direction center value of each square gate [-127..127]
> + * @awhb_rycut_l: V direction width of each square gate [0..127]
> + * @awhb_awbsftu: U gain offset [-127..127]
> + * @awhb_awbsftv: V gain offset [-127..127]
> + * @awhb_awbhuecor: 1:Enable/0:Disable setting of color correlation retention function
> + * @awhb_awbspd: UV convergence speed [0..15] [times] (0 means "stop")
> + * @awhb_awbulv: U convergence point level [0..31]
> + * @awhb_awbvlv: V convergence point level [0..31]
> + * @awhb_awbondot: Accumulation operation stop pixel count threshold [pixel] [0..1023]
> + * @awhb_awbfztim: &enum viif_l1_awb_restart_cond value. Condition to restart AWB process.
> + * @awhb_wbgrmax: B gain adjustment range (Width from center to upper limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_wbgbmax: R gain adjustment range (Width from center to upper limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_wbgrmin: B gain adjustment range (Width from center to lower limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_wbgbmin: R gain adjustment range (Width from center to lower limit)
> + * [0..255], accuracy: 1/64
> + * @awhb_ygateh: Luminance gate maximum value [pixel] [0..255]
> + * @awhb_ygatel: Luminance gate minimum value [pixel] [0..255]
> + * @awhb_awbwait: Number of restart frames after UV convergence freeze [0..255]
> + */
> +struct viif_l1_awb {
> + __u32 awhb_ygate_sel;
> + __u32 awhb_ygate_data;
> + __u32 awhb_cgrange;
> + __u32 awhb_ygatesw;
> + __u32 awhb_hexsw;
> + __u32 awhb_areamode;
> + __u32 awhb_area_hsize;
> + __u32 awhb_area_vsize;
> + __u32 awhb_area_hofs;
> + __u32 awhb_area_vofs;
> + __u32 awhb_area_maskh;
> + __u32 awhb_area_maskl;
> + __u32 awhb_sq_sw[3];
> + __u32 awhb_sq_pol[3];
> + __u32 awhb_bycut0p;
> + __u32 awhb_bycut0n;
> + __u32 awhb_rycut0p;
> + __u32 awhb_rycut0n;
> + __s32 awhb_rbcut0h;
> + __s32 awhb_rbcut0l;
> + __s32 awhb_bycut_h[3];
> + __u32 awhb_bycut_l[3];
> + __s32 awhb_rycut_h[3];
> + __u32 awhb_rycut_l[3];
> + __s32 awhb_awbsftu;
> + __s32 awhb_awbsftv;
> + __u32 awhb_awbhuecor;
> + __u32 awhb_awbspd;
> + __u32 awhb_awbulv;
> + __u32 awhb_awbvlv;
> + __u32 awhb_awbondot;
> + __u32 awhb_awbfztim;
> + __u8 awhb_wbgrmax;
> + __u8 awhb_wbgbmax;
> + __u8 awhb_wbgrmin;
> + __u8 awhb_wbgbmin;
> + __u8 awhb_ygateh;
> + __u8 awhb_ygatel;
> + __u8 awhb_awbwait;
> +};
> +
> +/**
> + * struct viif_l1_awb_config - L1ISP AWB parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB`
> + * @param_addr: Address to a &struct viif_l1_awb instance.
> + * Set 0 to disable AWB adjustment.
> + * @awhb_wbmrg: White balance adjustment R gain [64..1023], accuracy: 1/256
> + * @awhb_wbmgg: White balance adjustment G gain [64..1023], accuracy: 1/256
> + * @awhb_wbmbg: White balance adjustment B gain [64..1023], accuracy: 1/256
> + */
> +struct viif_l1_awb_config {
> + __u64 param_addr;
> + __u32 awhb_wbmrg;
> + __u32 awhb_wbmgg;
> + __u32 awhb_wbmbg;
> +};
> +
> +/**
> + * enum viif_l1_hdrc_tone_type - L1ISP HDRC tone type
> + *
> + * @VIIF_L1_HDRC_TONE_USER: User Tone
> + * @VIIF_L1_HDRC_TONE_PRESET: Preset Tone
> + */
> +enum viif_l1_hdrc_tone_type {
> + VIIF_L1_HDRC_TONE_USER = 0,
> + VIIF_L1_HDRC_TONE_PRESET = 1,
> +};
> +
> +/**
> + * struct viif_l1_hdrc - L1ISP HDRC parameters for &struct viif_l1_hdrc_config
> + * @hdrc_ratio: Data width of input image [bit] [10..24]
> + * @hdrc_pt_ratio: Preset Tone curve slope [0..13]
> + * @hdrc_pt_blend: Preset Tone0 curve blend ratio [0..256], accuracy: 1/256
> + * @hdrc_pt_blend2: Preset Tone2 curve blend ratio [0..256], accuracy: 1/256
> + * @hdrc_tn_type: &enum viif_l1_hdrc_tone_type value. L1ISP HDRC tone type.
> + * @hdrc_utn_tbl: HDRC value of User Tone curve [0..0xFFFF]
> + * @hdrc_flr_val: Constant flare value [0..0xFFFFFF]
> + * @hdrc_flr_adp: 1:Enable/0:Disable setting of dynamic flare measurement
> + * @hdrc_ybr_off: 1:Enable(function OFF) / 0:Disable(function ON) settings
> + * of bilateral luminance filter function OFF
> + * @hdrc_orgy_blend: Blend settings of luminance correction data after HDRC
> + * and data before luminance correction [0..16].
> + * (0:Luminance correction 100%, 8:Luminance correction 50%,
> + * 16:Luminance correction 0%)
> + * @hdrc_pt_sat: Preset Tone saturation value [0..0xFFFF]
> + *
> + * Parameter error needs to be returned in
> + * "hdrc_pt_blend + hdrc_pt_blend2 > 256" condition.
> + *
> + * In case application enables dynamic flare control, input image height should
> + * satisfy the following condition. Even if this condition is not satisfied,
> + * this driver doesn't return error in case other conditions for each parameter
> + * are satisfied. "Input image height % 64 != 18, 20, 22, 24, 26"
> + *
> + * hdrc_utn_tbl should satisfy the following condition. Even if this condition
> + * is not satisfied, this driver doesn't return error in case other conditions
> + * for each parameter are satisfied. "hdrc_utn_tbl[N] <= hdrc_utn_tbl[N+1]"
> + */
> +struct viif_l1_hdrc {
> + __u32 hdrc_ratio;
> + __u32 hdrc_pt_ratio;
> + __u32 hdrc_pt_blend;
> + __u32 hdrc_pt_blend2;
> + __u32 hdrc_tn_type;
> + __u16 hdrc_utn_tbl[20];
> + __u32 hdrc_flr_val;
> + __u32 hdrc_flr_adp;
> + __u32 hdrc_ybr_off;
> + __u32 hdrc_orgy_blend;
> + __u16 hdrc_pt_sat;
> +};
> +
> +/**
> + * struct viif_l1_hdrc_config - L1ISP HDRC parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC`
> + * @param_addr: Address to a &struct viif_l1_hdrc instance.
> + * Set 0 to disable HDR compression.
> + * @hdrc_thr_sft_amt: Amount of right shift in through mode (HDRC disabled) [0..8].
> + * Should set 0 if HDRC is enabled
> + */
> +struct viif_l1_hdrc_config {
> + __u64 param_addr;
> + __u32 hdrc_thr_sft_amt;
> +};
> +
> +/**
> + * struct viif_l1_hdrc_ltm_config - L1ISP HDRC LTM parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM`
> + * @tnp_max: Tone blend rate maximum value of LTM function
> + * [0..4194303], accuracy: 1/64. In case of 0, LTM function is OFF
> + * @tnp_mag: Intensity adjustment of LTM function [0..16383], accuracy: 1/64
> + * @tnp_fil: Smoothing filter coefficient [0..255].
> + * [0]: coef0, [1]: coef1, [2]: coef2, [3]: coef3, [4]: coef4
> + * EINVAL needs to be returned in the below condition.
> + * "(coef1 + coef2 + coef3 + coef4) * 2 + coef0 != 1024"
> + */
> +struct viif_l1_hdrc_ltm_config {
> + __u32 tnp_max;
> + __u32 tnp_mag;
> + __u8 tnp_fil[5];
> +};
> +
> +/**
> + * struct viif_l1_gamma - L1ISP gamma correction parameters
> + * for &struct viif_l1_gamma_config
> + * @gam_p: Luminance value after gamma correction [0..8191]
> + * @blkadj: Black level adjustment value after gamma correction [0..65535]
> + */
> +struct viif_l1_gamma {
> + __u16 gam_p[44];
> + __u16 blkadj;
> +};
> +
> +/**
> + * struct viif_l1_gamma_config - L1ISP gamma correction parameters
> + * @param_addr: Address to a &struct viif_l1_gamma instance.
> + * Set 0 to disable gamma correction at l1 ISP.
> + */
> +struct viif_l1_gamma_config {
> + __u64 param_addr;
> +};
> +
> +/**
> + * struct viif_l1_nonlinear_contrast - L1ISP non-linear contrast parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @blk_knee: Black side peak luminance value [0..0xFFFF]
> + * @wht_knee: White side peak luminance value[0..0xFFFF]
> + * @blk_cont: Black side slope [0..255], accuracy: 1/256
> + * [0]:the value at AG minimum, [1]:the value at AG less than 128,
> + * [2]:the value at AG equal to or more than 128
> + * @wht_cont: White side slope [0..255], accuracy: 1/256
> + * [0]:the value at AG minimum, [1]:the value at AG less than 128,
> + * [2]:the value at AG equal to or more than 128
> + */
> +struct viif_l1_nonlinear_contrast {
> + __u16 blk_knee;
> + __u16 wht_knee;
> + __u8 blk_cont[3];
> + __u8 wht_cont[3];
> +};
> +
> +/**
> + * struct viif_l1_lum_noise_reduction - L1ISP luminance noise reduction
> + * parameters for &struct viif_l1_img_quality_adjustment_config
> + * @gain_min: Minimum value of extracted noise gain [0..0xFFFF], accuracy: 1/256
> + * @gain_max: Maximum value of extracted noise gain [0..0xFFFF], accuracy: 1/256
> + * @lim_min: Minimum value of extracted noise limit [0..0xFFFF]
> + * @lim_max: Maximum value of extracted noise limit [0..0xFFFF]
> + *
> + * Parameter error needs to be returned in the below conditions.
> + * "gain_min > gain_max" or "lim_min > lim_max"
> + */
> +struct viif_l1_lum_noise_reduction {
> + __u16 gain_min;
> + __u16 gain_max;
> + __u16 lim_min;
> + __u16 lim_max;
> +};
> +
> +/**
> + * struct viif_l1_edge_enhancement - L1ISP edge enhancement parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @gain_min: Extracted edge gain minimum value [0..0xFFFF], accuracy: 1/256
> + * @gain_max: Extracted edge gain maximum value [0..0xFFFF], accuracy: 1/256
> + * @lim_min: Extracted edge limit minimum value [0..0xFFFF]
> + * @lim_max: Extracted edge limit maximum value [0..0xFFFF]
> + * @coring_min: Extracted edge coring threshold minimum value [0..0xFFFF]
> + * @coring_max: Extracted edge coring threshold maximum value [0..0xFFFF]
> + *
> + * Parameter error needs to be returned in the below conditions.
> + * "gain_min > gain_max" or "lim_min > lim_max" or "coring_min > coring_max"
> + */
> +struct viif_l1_edge_enhancement {
> + __u16 gain_min;
> + __u16 gain_max;
> + __u16 lim_min;
> + __u16 lim_max;
> + __u16 coring_min;
> + __u16 coring_max;
> +};
> +
> +/**
> + * struct viif_l1_uv_suppression - L1ISP UV suppression parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @bk_mp: Black side slope [0..0x3FFF], accuracy: 1/16384
> + * @black: Minimum black side gain [0..0x3FFF], accuracy: 1/16384
> + * @wh_mp: White side slope [0..0x3FFF], accuracy: 1/16384
> + * @white: Minimum white side gain [0..0x3FFF], accuracy: 1/16384
> + * @bk_slv: Black side intercept [0..0xFFFF]
> + * @wh_slv: White side intercept [0..0xFFFF]
> + *
> + * parameter error needs to be returned in "bk_slv >= wh_slv" condition.
> + */
> +struct viif_l1_uv_suppression {
> + __u32 bk_mp;
> + __u32 black;
> + __u32 wh_mp;
> + __u32 white;
> + __u16 bk_slv;
> + __u16 wh_slv;
> +};
> +
> +/**
> + * struct viif_l1_coring_suppression - L1ISP coring suppression parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @lv_min: Minimum coring threshold [0..0xFFFF]
> + * @lv_max: Maximum coring threshold [0..0xFFFF]
> + * @gain_min: Minimum gain [0..0xFFFF], accuracy: 1/65536
> + * @gain_max: Maximum gain [0..0xFFFF], accuracy: 1/65536
> + *
> + * Parameter error needs to be returned in the below condition.
> + * "lv_min > lv_max" or "gain_min > gain_max"
> + */
> +struct viif_l1_coring_suppression {
> + __u16 lv_min;
> + __u16 lv_max;
> + __u16 gain_min;
> + __u16 gain_max;
> +};
> +
> +/**
> + * struct viif_l1_edge_suppression - L1ISP edge suppression parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @gain: Gain of edge color suppression [0..0xFFFF], accuracy: 1/256
> + * @lim: Limiter threshold of edge color suppression [0..15]
> + */
> +struct viif_l1_edge_suppression {
> + __u16 gain;
> + __u32 lim;
> +};
> +
> +/**
> + * struct viif_l1_color_level - L1ISP color level parameters
> + * for &struct viif_l1_img_quality_adjustment_config
> + * @cb_gain: U component gain [0..0xFFF], accuracy: 1/2048
> + * @cr_gain: V component gain [0..0xFFF], accuracy: 1/2048
> + * @cbr_mgain_min: UV component gain [0..0xFFF], accuracy: 1/2048
> + * @cbp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
> + * @cbm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
> + * @crp_gain_max: Positive U component gain [0..0xFFF], accuracy: 1/2048
> + * @crm_gain_max: Negative V component gain [0..0xFFF], accuracy: 1/2048
> + */
> +struct viif_l1_color_level {
> + __u32 cb_gain;
> + __u32 cr_gain;
> + __u32 cbr_mgain_min;
> + __u32 cbp_gain_max;
> + __u32 cbm_gain_max;
> + __u32 crp_gain_max;
> + __u32 crm_gain_max;
> +};
> +
> +/**
> + * struct viif_l1_img_quality_adjustment_config - L1ISP image quality
> + * adjustment parameters for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT`
> + * @coef_cb: Cb coefficient used in RGB to YUV conversion
> + * [0..0xFFFF], accuracy: 1/65536
> + * @coef_cr: Cr coefficient used in RGB to YUV conversion
> + * [0..0xFFFF], accuracy: 1/65536
> + * @brightness: Brightness value [-32768..32767] (0 means off)
> + * @linear_contrast: Linear contrast adjustment value
> + * [0..0xFF], accuracy: 1/128 (128 means off)
> + * @nonlinear_contrast_addr: Address to a &struct viif_l1_nonlinear_contrast instance.
> + * Set 0 to disable nonlinear contrast adjustment.
> + * @lum_noise_reduction_addr: Address to a &struct viif_l1_lum_noise_reduction instance.
> + * Set 0 to disable luminance noise reduction.
> + * @edge_enhancement_addr: Address to a &struct viif_l1_edge_enhancement instance.
> + * Set 0 to disable edge enhancement,
> + * @uv_suppression_addr: Address to a &struct viif_l1_uv_suppression instance.
> + * Set 0 to disable chroma suppression.
> + * @coring_suppression_addr: Address to a &struct viif_l1_coring_suppression instance.
> + * Set 0 to disable coring suppression.
> + * @edge_suppression_addr: Address to a &struct viif_l1_edge_suppression instance.
> + * Set 0 to disable chroma edge suppression.
> + * @color_level_addr: Address to a &struct viif_l1_color_level instance.
> + * Set 0 to disable color level adjustment.
> + * @color_noise_reduction_enable: 1:Enable/0:disable setting of
> + * color component noise reduction processing
> + */
> +struct viif_l1_img_quality_adjustment_config {
> + __u16 coef_cb;
> + __u16 coef_cr;
> + __s16 brightness;
> + __u8 linear_contrast;
> + __u64 nonlinear_contrast_addr;
> + __u64 lum_noise_reduction_addr;
> + __u64 edge_enhancement_addr;
> + __u64 uv_suppression_addr;
> + __u64 coring_suppression_addr;
> + __u64 edge_suppression_addr;
> + __u64 color_level_addr;
> + __u32 color_noise_reduction_enable;
> +};
> +
> +/**
> + * struct viif_l1_avg_lum_generation_config - L1ISP average luminance generation configuration
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION`
> + * @aexp_start_x: horizontal position of block[0] [0.."width of input image - 1"] [pixel]
> + * @aexp_start_y: vertical position of block[0] [0.."height of input image - 1"] [line]
> + * @aexp_block_width: width of one block(needs to be multiple of 64)
> + * [64.."width of input image"] [pixel]
> + * @aexp_block_height: height of one block(needs to be multiple of 64)
> + * [64.."height of input image"] [line]
> + * @aexp_weight: weight of each block [0..3] [y][x]:
> + * y means vertical position and x means horizontal position
> + * @aexp_satur_ratio: threshold to judge whether saturated block or not [0..256]
> + * @aexp_black_ratio: threshold to judge whether black block or not [0..256]
> + * @aexp_satur_level: threshold to judge whether saturated pixel or not [0x0..0xffffff]
> + * @aexp_ave4linesy: vertical position of the initial line
> + * for 4-lines average luminance [0.."height of input image - 4"] [line]
> + */
> +struct viif_l1_avg_lum_generation_config {
> + __u32 aexp_start_x;
> + __u32 aexp_start_y;
> + __u32 aexp_block_width;
> + __u32 aexp_block_height;
> + __u32 aexp_weight[8][8];
> + __u32 aexp_satur_ratio;
> + __u32 aexp_black_ratio;
> + __u32 aexp_satur_level;
> + __u32 aexp_ave4linesy[4];
> +};
> +
> +/**
> + * enum viif_l2_undist_mode - L2ISP undistortion mode
> + * @VIIF_L2_UNDIST_POLY: polynomial mode
> + * @VIIF_L2_UNDIST_GRID: grid table mode
> + * @VIIF_L2_UNDIST_POLY_TO_GRID: polynomial, then grid table mode
> + * @VIIF_L2_UNDIST_GRID_TO_POLY: grid table, then polynomial mode
> + */
> +enum viif_l2_undist_mode {
> + VIIF_L2_UNDIST_POLY = 0,
> + VIIF_L2_UNDIST_GRID = 1,
> + VIIF_L2_UNDIST_POLY_TO_GRID = 2,
> + VIIF_L2_UNDIST_GRID_TO_POLY = 3,
> +};
> +
> +/**
> + * struct viif_l2_undist - L2ISP UNDIST parameters
> + * for &struct viif_l2_undist_config
> + * @through_mode: 1:enable or 0:disable through mode of undistortion
> + * @roi_mode: &enum viif_l2_undist_mode value. Sets L2ISP undistortion mode.
> + * @sensor_crop_ofs_h: Horizontal start position of sensor crop area[pixel]
> + * [-4296..4296], accuracy: 1/2
> + * @sensor_crop_ofs_v: Vertical start position of sensor crop area[line]
> + * [-2360..2360], accuracy: 1/2
> + * @norm_scale: Normalization coefficient for distance from center
> + * [0..1677721], accuracy: 1/33554432
> + * @valid_r_norm2_poly: Setting target area for polynomial correction
> + * [0..0x3FFFFFF], accuracy: 1/33554432
> + * @valid_r_norm2_grid: Setting target area for grid table correction
> + * [0..0x3FFFFFF], accuracy: 1/33554432
> + * @roi_write_area_delta: Error adjustment value of forward function and
> + * inverse function for pixel position calculation
> + * [0..0x7FF], accuracy: 1/1024
> + * @poly_write_g_coef: 10th-order polynomial coefficient for G write pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @poly_read_b_coef: 10th-order polynomial coefficient for B read pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @poly_read_g_coef: 10th-order polynomial coefficient for G read pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @poly_read_r_coef: 10th-order polynomial coefficient for R read pixel position calculation
> + * [-2147352576..2147352576], accuracy: 1/131072
> + * @grid_node_num_h: Number of horizontal grids [16..64]
> + * @grid_node_num_v: Number of vertical grids [16..64]
> + * @grid_patch_hsize_inv: Inverse pixel size between horizontal grids
> + * [0..0x7FFFFF], accuracy: 1/8388608
> + * @grid_patch_vsize_inv: Inverse pixel size between vertical grids
> + * [0..0x7FFFFF], accuracy: 1/8388608
> + */
> +struct viif_l2_undist {
> + __u32 through_mode;
> + __u32 roi_mode[2];
> + __s32 sensor_crop_ofs_h;
> + __s32 sensor_crop_ofs_v;
> + __u32 norm_scale;
> + __u32 valid_r_norm2_poly;
> + __u32 valid_r_norm2_grid;
> + __u32 roi_write_area_delta[2];
> + __s32 poly_write_g_coef[11];
> + __s32 poly_read_b_coef[11];
> + __s32 poly_read_g_coef[11];
> + __s32 poly_read_r_coef[11];
> + __u32 grid_node_num_h;
> + __u32 grid_node_num_v;
> + __u32 grid_patch_hsize_inv;
> + __u32 grid_patch_vsize_inv;
> +};
> +
> +/**
> + * struct viif_l2_undist_config - L2ISP UNDIST parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST`
> + * @param: &struct viif_l2_undist
> + * @write_g_addr: Address to write-G grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @read_b_addr: Address to read-B grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @read_g_addr: Address to read-G grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @read_r_addr: Address to read-R grid table.
> + * Table size is specified by member size.
> + * Set 0 to disable this table.
> + * @size: Table size [byte]. Range: [1024..8192] or 0.
> + * The value should be "grid_node_num_h * grid_node_num_v * 4".
> + * See also &struct viif_l2_undist.
> + * Set 0 if NULL is set for all tables.
> + * Set valid size value if at least one table is valid.
> + *
> + * Application should make sure that the table data is based on HW specification
> + * since this driver does not check the contents of specified grid table.
> + */
> +struct viif_l2_undist_config {
> + struct viif_l2_undist param;
> + __u64 write_g_addr;
> + __u64 read_b_addr;
> + __u64 read_g_addr;
> + __u64 read_r_addr;
> + __u32 size;
> +};
> +
> +/**
> + * struct viif_l2_roi_config - L2ISP ROI parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI`
> + * @roi_num:
> + * 1 when only capture path0 is activated,
> + * 2 when both capture path 0 and path 1 are activated.
> + * @roi_scale: Scale value for each ROI [32768..131072], accuracy: 1/65536
> + * @roi_scale_inv: Inverse scale value for each ROI [32768..131072], accuracy: 1/65536
> + * @corrected_wo_scale_hsize: Corrected image width for each ROI [pixel] [128..8190]
> + * @corrected_wo_scale_vsize: Corrected image height for each ROI [line] [128..4094]
> + * @corrected_hsize: Corrected and scaled image width for each ROI [pixel] [128..8190]
> + * @corrected_vsize: Corrected and scaled image height for each ROI [line] [128..4094]
> + */
> +struct viif_l2_roi_config {
> + __u32 roi_num;
> + __u32 roi_scale[2];
> + __u32 roi_scale_inv[2];
> + __u32 corrected_wo_scale_hsize[2];
> + __u32 corrected_wo_scale_vsize[2];
> + __u32 corrected_hsize[2];
> + __u32 corrected_vsize[2];
> +};
> +
> +/** enum viif_gamma_mode - Gamma correction mode
> + *
> + * @VIIF_GAMMA_COMPRESSED: compressed table mode
> + * @VIIF_GAMMA_LINEAR: linear table mode
> + */
> +enum viif_gamma_mode {
> + VIIF_GAMMA_COMPRESSED = 0,
> + VIIF_GAMMA_LINEAR = 1,
> +};
> +
> +/**
> + * struct viif_l2_gamma_config - L2ISP gamma correction parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA`
> + * @pathid: 0 for Capture Path 0, 1 for Capture Path 1.
> + * @enable: 1:Enable, 0:Disable settings of L2ISP gamma correction control
> + * @vsplit: Line switching position of first table and second table [line] [0..4094].
> + * Should set 0 in case 0 is set to @enable
> + * @mode: &enum viif_gamma_mode value.
> + * Should set VIIF_GAMMA_COMPRESSED when 0 is set to @enable
> + * @table_addr: Address to gamma table for L2ISP gamma.
> + * The table has 6 channels;
> + * [0]: G/Y(1st table), [1]: G/Y(2nd table), [2]: B/U(1st table)
> + * [3]: B/U(2nd table), [4]: R/V(1st table), [5]: R/V(2nd table)
> + * Each channel of the table is __u16 typed and 512 bytes.
> + */
> +struct viif_l2_gamma_config {
> + __u32 pathid;
> + __u32 enable;
> + __u32 vsplit;
> + __u32 mode;
> + __u64 table_addr[6];
> +};
> +
> +/**
> + * enum viif_csi2_cal_status - CSI2RX calibration status
> + *
> + * @VIIF_CSI2_CAL_NOT_DONE: Calibration not complete
> + * @VIIF_CSI2_CAL_SUCCESS: Calibration success
> + * @VIIF_CSI2_CAL_FAIL: Calibration failed
> + */
> +enum viif_csi2_cal_status {
> + VIIF_CSI2_CAL_NOT_DONE = 0,
> + VIIF_CSI2_CAL_SUCCESS = 1,
> + VIIF_CSI2_CAL_FAIL = 2,
> +};
> +
> +/**
> + * struct viif_csi2rx_dphy_calibration_status - CSI2-RX D-PHY Calibration
> + * information for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS`
> + * @term_cal_with_rext: Result of termination calibration with rext
> + * @clock_lane_offset_cal: Result of offset calibration of clock lane
> + * @data_lane0_offset_cal: Result of offset calibration of data lane0
> + * @data_lane1_offset_cal: Result of offset calibration of data lane1
> + * @data_lane2_offset_cal: Result of offset calibration of data lane2
> + * @data_lane3_offset_cal: Result of offset calibration of data lane3
> + * @data_lane0_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane0
> + * @data_lane1_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane1
> + * @data_lane2_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane2
> + * @data_lane3_ddl_tuning_cal: Result of digital delay line tuning calibration of data lane3
> + *
> + * Values for each member is typed &enum viif_csi2_cal_status.
> + */
> +struct viif_csi2rx_dphy_calibration_status {
> + __u32 term_cal_with_rext;
> + __u32 clock_lane_offset_cal;
> + __u32 data_lane0_offset_cal;
> + __u32 data_lane1_offset_cal;
> + __u32 data_lane2_offset_cal;
> + __u32 data_lane3_offset_cal;
> + __u32 data_lane0_ddl_tuning_cal;
> + __u32 data_lane1_ddl_tuning_cal;
> + __u32 data_lane2_ddl_tuning_cal;
> + __u32 data_lane3_ddl_tuning_cal;
> +};
> +
> +/**
> + * struct viif_csi2rx_err_status - CSI2RX Error status parameters
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS`
> + * @err_phy_fatal: D-PHY FATAL error.
> + *
> + * * bit[3]: Start of transmission error on DATA Lane3.
> + * * bit[2]: Start of transmission error on DATA Lane2.
> + * * bit[1]: Start of transmission error on DATA Lane1.
> + * * bit[0]: Start of transmission error on DATA Lane0.
> + * @err_pkt_fatal: Packet FATAL error.
> + *
> + * * bit[16]: Header ECC contains 2 errors, unrecoverable.
> + * * bit[3]: Checksum error detected on virtual channel 3.
> + * * bit[2]: Checksum error detected on virtual channel 2.
> + * * bit[1]: Checksum error detected on virtual channel 1.
> + * * bit[0]: Checksum error detected on virtual channel 0.
> + * @err_frame_fatal: Frame FATAL error.
> + *
> + * * bit[19]: Last received Frame, in virtual channel 3, has at least one CRC error.
> + * * bit[18]: Last received Frame, in virtual channel 2, has at least one CRC error.
> + * * bit[17]: Last received Frame, in virtual channel 1, has at least one CRC error.
> + * * bit[16]: Last received Frame, in virtual channel 0, has at least one CRC error.
> + * * bit[11]: Incorrect Frame Sequence detected in virtual channel 3.
> + * * bit[10]: Incorrect Frame Sequence detected in virtual channel 2.
> + * * bit[9]: Incorrect Frame Sequence detected in virtual channel 1.
> + * * bit[8]: Incorrect Frame Sequence detected in virtual channel 0.
> + * * bit[3]: Error matching Frame Start with Frame End for virtual channel 3.
> + * * bit[2]: Error matching Frame Start with Frame End for virtual channel 2.
> + * * bit[1]: Error matching Frame Start with Frame End for virtual channel 1.
> + * * bit[0]: Error matching Frame Start with Frame End for virtual channel 0.
> + * @err_phy: D-PHY error.
> + *
> + * * bit[19]: Escape Entry Error on Data Lane 3.
> + * * bit[18]: Escape Entry Error on Data Lane 2.
> + * * bit[17]: Escape Entry Error on Data Lane 1.
> + * * bit[16]: Escape Entry Error on Data Lane 0.
> + * * bit[3]: Start of Transmission Error on Data Lane 3 (synchronization can still be achieved).
> + * * bit[2]: Start of Transmission Error on Data Lane 2 (synchronization can still be achieved).
> + * * bit[1]: Start of Transmission Error on Data Lane 1 (synchronization can still be achieved).
> + * * bit[0]: Start of Transmission Error on Data Lane 0 (synchronization can still be achieved).
> + * @err_pkt: Packet error.
> + *
> + * * bit[19]: Header Error detected and corrected on virtual channel 3.
> + * * bit[18]: Header Error detected and corrected on virtual channel 2.
> + * * bit[17]: Header Error detected and corrected on virtual channel 1.
> + * * bit[16]: Header Error detected and corrected on virtual channel 0.
> + * * bit[3]: Unrecognized or unimplemented data type detected in virtual channel 3.
> + * * bit[2]: Unrecognized or unimplemented data type detected in virtual channel 2.
> + * * bit[1]: Unrecognized or unimplemented data type detected in virtual channel 1.
> + * * bit[0]: Unrecognized or unimplemented data type detected in virtual channel 0.
> + * @err_line: Line error.
> + *
> + * * bit[23]: Error in the sequence of lines for vc7 and dt7.
> + * * bit[22]: Error in the sequence of lines for vc6 and dt6.
> + * * bit[21]: Error in the sequence of lines for vc5 and dt5.
> + * * bit[20]: Error in the sequence of lines for vc4 and dt4.
> + * * bit[19]: Error in the sequence of lines for vc3 and dt3.
> + * * bit[18]: Error in the sequence of lines for vc2 and dt2.
> + * * bit[17]: Error in the sequence of lines for vc1 and dt1.
> + * * bit[16]: Error in the sequence of lines for vc0 and dt0.
> + * * bit[7]: Error matching Line Start with Line End for vc7 and dt7.
> + * * bit[6]: Error matching Line Start with Line End for vc6 and dt6.
> + * * bit[5]: Error matching Line Start with Line End for vc5 and dt5.
> + * * bit[4]: Error matching Line Start with Line End for vc4 and dt4.
> + * * bit[3]: Error matching Line Start with Line End for vc3 and dt3.
> + * * bit[2]: Error matching Line Start with Line End for vc2 and dt2.
> + * * bit[1]: Error matching Line Start with Line End for vc1 and dt1.
> + * * bit[0]: Error matching Line Start with Line End for vc0 and dt0.
> + */
> +struct viif_csi2rx_err_status {
> + __u32 err_phy_fatal;
> + __u32 err_pkt_fatal;
> + __u32 err_frame_fatal;
> + __u32 err_phy;
> + __u32 err_pkt;
> + __u32 err_line;
> +};
> +
> +/**
> + * struct viif_l1_info - L1ISP AWB information
> + * for &struct viif_isp_capture_status
> + * @avg_lum_weight: weighted average luminance value at average luminance generation
> + * @avg_lum_block: average luminance of each block [y][x]:
> + * y means vertical position and x means horizontal position
> + * @avg_lum_four_line_lum: 4-lines average luminance.
> + * avg_lum_four_line_lum[n] corresponds to aexp_ave4linesy[n]
> + * @avg_satur_pixnum: the number of saturated pixel at average luminance generation
> + * @avg_black_pixnum: the number of black pixel at average luminance generation
> + * @awb_ave_u: U average value of AWB adjustment [pixel]
> + * @awb_ave_v: V average value of AWB adjustment [pixel]
> + * @awb_accumulated_pixel: Accumulated pixel count of AWB adjustment
> + * @awb_gain_r: R gain used in the next frame of AWB adjustment
> + * @awb_gain_g: G gain used in the next frame of AWB adjustment
> + * @awb_gain_b: B gain used in the next frame of AWB adjustment
> + * @awb_status_u: boolean value of U convergence state of AWB adjustment
> + * (0: not-converged, 1: converged)
> + * @awb_status_v: boolean value of V convergence state of AWB adjustment
> + * (0: not-converged, 1: converged)
> + */
> +struct viif_l1_info {
> + __u32 avg_lum_weight;
> + __u32 avg_lum_block[8][8];
> + __u32 avg_lum_four_line_lum[4];
> + __u32 avg_satur_pixnum;
> + __u32 avg_black_pixnum;
> + __u32 awb_ave_u;
> + __u32 awb_ave_v;
> + __u32 awb_accumulated_pixel;
> + __u32 awb_gain_r;
> + __u32 awb_gain_g;
> + __u32 awb_gain_b;
> + __u8 awb_status_u;
> + __u8 awb_status_v;
> +};
> +
> +/**
> + * struct viif_isp_capture_status - L1ISP capture information
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS`
> + * @l1_info: L1ISP AWB information. Refer to &struct viif_l1_info
> + */
> +struct viif_isp_capture_status {
> + struct viif_l1_info l1_info;
> +};
> +
> +/**
> + * struct viif_reported_errors - Errors since last call
> + * for :ref:`V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS`
> + * @main: error flag value for capture device 0 and 1
> + * @sub: error flag value for capture device 2
> + * @csi2rx: error flag value for CSI2 receiver
> + */
> +struct viif_reported_errors {
> + __u32 main;
> + __u32 sub;
> + __u32 csi2rx;
> +};
> +
> +#endif /* __UAPI_VISCONTI_VIIF_H_ */
--
Kind regards,
Sakari Ailus
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-17 22:39 ` Sakari Ailus
@ 2023-02-01 2:02 ` yuji2.ishikawa
2023-02-01 9:41 ` Laurent Pinchart
0 siblings, 1 reply; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-01 2:02 UTC (permalink / raw)
To: sakari.ailus
Cc: hverkuil, laurent.pinchart, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Sakari,
Sorry for sending the reply again.
My mail agent posted the previous one with HTML format.
Thank you for reviewing and your comments.
> -----Original Message-----
> From: Sakari Ailus sakari.ailus@iki.fi
> Sent: Wednesday, January 18, 2023 7:40 AM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> yuji2.ishikawa@toshiba.co.jp
> Cc: Hans Verkuil hverkuil@xs4all.nl; Laurent Pinchart
> laurent.pinchart@ideasonboard.com; Mauro Carvalho Chehab
> mchehab@kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> nobuhiro1.iwamatsu@toshiba.co.jp; Rob Herring robh+dt@kernel.org;
> Krzysztof Kozlowski krzysztof.kozlowski+dt@linaro.org; Rafael J . Wysocki
> rafael.j.wysocki@intel.com; Mark Brown broonie@kernel.org;
> linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver
>
> Dear Ishikawa-san,
>
> Thanks for the patchset.
>
> I'd say this is a partial review based on a quick glance, I may have
> further comments later on. It's a big patch, some 8000 lines. Please see
> the comments below.
>
> On Wed, Jan 11, 2023 at 11:24:29AM +0900, Yuji Ishikawa wrote:
> > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > The interface device includes CSI2 Receiver,
> > frame grabber, video DMAC and image signal processor.
> > This patch provides operations to handle registers of HW listed above.
> >
> > The Video DMACs have 32bit address space
> > and currently corresponding IOMMU driver is not provided.
> > Therefore, memory-block address for captured image is 32bit IOVA
> > which is equal to 32bit-truncated phisical address.
> > When the Visconti IOMMU driver (currently under development) is accepted,
> > the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
> >
> > Signed-off-by: Yuji Ishikawa yuji2.ishikawa@toshiba.co.jp
> > ---
> > Changelog v2:
> > - Resend v1 because a patch exceeds size limit.
> >
> > Changelog v3:
> > - Adapted to media control framework
> > - Introduced ISP subdevice, capture device
> > - Remove private IOCTLs and add vendor specific V4L2 controls
> > - Change function name avoiding camelcase and uppercase letters
> >
> > Changelog v4:
> > - Split patches because the v3 patch exceeds size limit
> > - Stop using ID number to identify driver instance:
> > - Use dynamically allocated structure to hold driver's context,
> > instead of static one indexed by ID number.
> > - Functions accept driver's context structure instead of ID number.
> >
> > Changelog v5:
> > - no change
> > ---
> > drivers/media/platform/Kconfig | 1 +
> > drivers/media/platform/Makefile | 1 +
> > drivers/media/platform/visconti/Kconfig | 9 +
> > drivers/media/platform/visconti/Makefile | 8 +
> > drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
> > drivers/media/platform/visconti/hwd_viif.h | 710 +++++
> > .../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
> > .../platform/visconti/hwd_viif_internal.h | 340 ++
> > .../media/platform/visconti/hwd_viif_reg.h | 2802
> +++++++++++++++++
> > include/uapi/linux/visconti_viif.h | 1724 ++++++++++
> > 10 files changed, 7895 insertions(+)
> > create mode 100644 drivers/media/platform/visconti/Kconfig
> > create mode 100644 drivers/media/platform/visconti/Makefile
> > create mode 100644 drivers/media/platform/visconti/hwd_viif.c
> > create mode 100644 drivers/media/platform/visconti/hwd_viif.h
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
> > create mode 100644 include/uapi/linux/visconti_viif.h
> >
> > diff --git a/drivers/media/platform/Kconfig
> b/drivers/media/platform/Kconfig
> > index a9334263fa9..0908158036d 100644
> > --- a/drivers/media/platform/Kconfig
> > +++ b/drivers/media/platform/Kconfig
> > @@ -83,6 +83,7 @@ source "drivers/media/platform/sunxi/Kconfig"
> > source "drivers/media/platform/ti/Kconfig"
> > source "drivers/media/platform/verisilicon/Kconfig"
> > source "drivers/media/platform/via/Kconfig"
> > +source "drivers/media/platform/visconti/Kconfig"
> > source "drivers/media/platform/xilinx/Kconfig"
> >
> > endif # MEDIA_PLATFORM_DRIVERS
> > diff --git a/drivers/media/platform/Makefile
> b/drivers/media/platform/Makefile
> > index a91f4202427..1c67cb56244 100644
> > --- a/drivers/media/platform/Makefile
> > +++ b/drivers/media/platform/Makefile
> > @@ -26,6 +26,7 @@ obj-y += sunxi/
> > obj-y += ti/
> > obj-y += verisilicon/
> > obj-y += via/
> > +obj-y += visconti/
> > obj-y += xilinx/
> >
> > # Please place here only ancillary drivers that aren't SoC-specific
> > diff --git a/drivers/media/platform/visconti/Kconfig
> b/drivers/media/platform/visconti/Kconfig
> > new file mode 100644
> > index 00000000000..031e4610809
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/Kconfig
> > @@ -0,0 +1,9 @@
> > +config VIDEO_VISCONTI_VIIF
> > + tristate "Visconti Camera Interface driver"
> > + depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER &&
> VIDEO_DEV
> > + depends on ARCH_VISCONTI
> > + select VIDEOBUF2_DMA_CONTIG
> > + select V4L2_FWNODE
> > + help
> > + This is V4L2 driver for Toshiba Visconti Camera Interface driver
> > +
> > diff --git a/drivers/media/platform/visconti/Makefile
> b/drivers/media/platform/visconti/Makefile
> > new file mode 100644
> > index 00000000000..e14b904df75
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/Makefile
> > @@ -0,0 +1,8 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +#
> > +# Makefile for the Visconti video input device driver
> > +#
> > +
> > +visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> > +
> > +obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> > diff --git a/drivers/media/platform/visconti/hwd_viif.c
> b/drivers/media/platform/visconti/hwd_viif.c
> > new file mode 100644
> > index 00000000000..260293fa4d0
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif.c
> > @@ -0,0 +1,1690 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
>
> Happy new year!
Oh! Another year has come.
I'll update copyright notice.
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "hwd_viif.h"
> > +#include "hwd_viif_internal.h"
> > +
> > +/* MIPI CSI2 DataType definition */
> > +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> > +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> > +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> > +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> > +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> > +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> > +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> > +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
>
> These are generic MIPI CSI-2 definitions, no need to re-define them for
> this driver only.
I'll use definitions in mipi-csi2.h
> > +
> > +struct hwd_viif_res *allocate_viif_res(struct device *dev, void
> *csi2host_vaddr,
> > + void *capture_vaddr)
> > +{
> > + struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res),
> GFP_KERNEL);
> > +
> > + res->csi2host_reg = csi2host_vaddr;
> > + res->capture_reg = capture_vaddr;
> > + res->run_flag_main = (bool)false;
>
> What happens here if res is NULL?
>
> I'd advise to perform the allocation outside variable declarations, that
> way it is more obvious it may fail (and needs to be checked for).
>
> No need for a cast.
I'll fix them.
> > + return res;
> > +}
> > +
> > +/* Convert the unit of time-period (from sysclk, to num lines in the image) */
> > +static u32 sysclk_to_numlines(u64 time_in_sysclk, const struct
> hwd_viif_input_img *img)
>
> Please run:
>
> $ ./scripts/checkpatch.pl --strict --max-line-length=80
>
> on the set.
I found that extra newlines inserted by a mailer surely made the patch difficult to read.
Currently, a source file has maximum 100 characters for a line.
I’ll limit to 80 characters.
Is it just for review process, or the source files should always have maximum 80 characters for a line?
> > +{
> > + u64 v1 = time_in_sysclk * (u64)img->pixel_clock;
>
> You can drop the cast.
I'll drop the cast.
> > + u64 v2 = (u64)img->htotal_size * HWD_VIIF_SYS_CLK;
> > +
> > + return (u32)(v1 / v2);
>
> div_u64()?
I'll use div_u64().
> > +}
> > +
> > +static u32 lineperiod_in_sysclk(u64 hsize, u64 pixel_clock)
> > +{
> > + return (u32)(hsize * HWD_VIIF_SYS_CLK / pixel_clock);
>
> You can drop the cast.
>
> And I think you need div_u64() instead.
I'll use div_u64().
> > +}
> > +
> > +/**
> > + * hwd_viif_main_set_unit() - Set static configuration of MAIN unit(CH0 or
> CH1)
> > + *
> > + * @dt_image: DT of image [0x10-0x17, 0x1B, 0x1E, 0x1F, 0x22, 0x24-0x27,
> 0x2A-0x3F])
> > + * @in_img: Pointer to input image information
> > + * @color_type: Color type of image [0x0, 0x1E, 0x1F, 0x22, 0x24, 0x2A-0x2D]
> > + * @rawpack: RAW pack mode. For more refer @ref
> hwd_viif_raw_pack_mode
> > + * @yuv_conv: YUV422 to YUV444 conversion mode. For more refer @ref
> hwd_viif_yuv_conversion_mode
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "dt_image" is out of range
> > + * - [2] "in_img" is NULL
> > + * - [3] member of "in_img" is invalid
> > + * - [4] "color_type" is out of range
> > + * - [5] "color_type" doesn't meet the condition shown in the below note
> > + * - [6] "rawpack" is out of range
> > + * - [7] "rawpack" is not HWD_VIIF_RAWPACK_DISABLE when color_type is
> other than RAW(0x2A-0x2C)
> > + * - [8] "yuv_conv" is out of range
> > + * - [9] "yuv_conv" is not HWD_VIIF_YUV_CONV_REPEAT
> > + * when color_type is other than YUV422(0x1E or 0x1F)
> > + *
> > + * Note: valid combination between "dt_image" and "color_type" is
> > + * - when "dt_image" is [0x10-0x17, 0x1B, 0x25-0x27, 0x2E-0x3F],
> "color_type" must be [0x2A-0x2D].
> > + * - when "dt_image" is valid value and other than [0x10-0x17, 0x1B,
> 0x25-0x27, 0x2E-0x3F],
> > + * "color_type" must be "dt_image"
> > + */
> > +s32 hwd_viif_main_set_unit(struct hwd_viif_res *res, u32 dt_image,
> > + const struct hwd_viif_input_img *in_img, u32
> color_type, u32 rawpack,
> > + u32 yuv_conv)
> > +{
> > + u32 total_hact_size = 0U, total_vact_size = 0U;
> > + u32 sw_delay0, sw_delay1, hw_delay;
> > + u32 val, color, sysclk_num;
> > + u32 i;
> > +
> > + /*
> > + * 0x00-0x09: ShortPacket/Undefined
> > + * 0x18-0x1A: YUV420
> > + * 0x1C,0x1D: YUV420 CSPS
> > + * 0x20,0x21,0x23: RGB444, RGB555, RGB666
> > + * 0x28,0x29: RAW6, RAW7
> > + */
> > + if (dt_image <= 0x09U || (dt_image >= 0x18U && dt_image <= 0x1AU)
> || dt_image == 0x1CU ||
> > + dt_image == 0x1DU || dt_image == 0x20U || dt_image == 0x21U
> || dt_image == 0x23U ||
> > + dt_image == 0x28U || dt_image == 0x29U || dt_image >
> HWD_VIIF_CSI2_MAX_DT) {
> > + return -EINVAL;
> > + }
> > +
> > + /*Case: Generic Long Packet, Reserved, User-Defined*/
> > + if ((dt_image >= 0x10U && dt_image <= 0x17U) || dt_image == 0x1bU
> ||
> > + (dt_image >= 0x25U && dt_image <= 0x27U) || dt_image >=
> 0x2eU) {
> > + if (color_type != CSI2_DT_RAW8 && color_type !=
> CSI2_DT_RAW10 &&
> > + color_type != CSI2_DT_RAW12 && color_type !=
> CSI2_DT_RAW14) {
>
> Could you use the data type defines where applicable? Same above.
I'll use definitions in mipi-csi2.h .
> > + return -EINVAL;
> > + }
> > + } else {
> > + /*Case: Otherwise: YUV, RGB, RAW*/
> > + /*Constraint: color_type must be dt_image*/
> > + if (color_type != dt_image)
> > + return -EINVAL;
> > + }
> > +
> > + if (!in_img)
> > + return -EINVAL;
> > + if (rawpack != HWD_VIIF_RAWPACK_DISABLE && rawpack !=
> HWD_VIIF_RAWPACK_MSBFIRST &&
> > + rawpack != HWD_VIIF_RAWPACK_LSBFIRST) {
> > + return -EINVAL;
> > + }
> > + if (color_type != CSI2_DT_RAW8 && color_type != CSI2_DT_RAW10 &&
> > + color_type != CSI2_DT_RAW12 && rawpack !=
> HWD_VIIF_RAWPACK_DISABLE) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->pixel_clock < HWD_VIIF_MIN_PIXEL_CLOCK ||
> > + in_img->pixel_clock > HWD_VIIF_MAX_PIXEL_CLOCK ||
> > + in_img->htotal_size < HWD_VIIF_MIN_HTOTAL_PIXEL ||
> > + in_img->htotal_size > HWD_VIIF_MAX_HTOTAL_PIXEL ||
> > + in_img->vtotal_size < HWD_VIIF_MIN_VTOTAL_LINE ||
> > + in_img->vtotal_size > HWD_VIIF_MAX_VTOTAL_LINE ||
> > + in_img->vbp_size < HWD_VIIF_MIN_VBP_LINE ||
> in_img->vbp_size > HWD_VIIF_MAX_VBP_LINE ||
> > + ((in_img->hactive_size % 2U) != 0U) || ((in_img->vactive_size %
> 2U) != 0U)) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->interpolation_mode !=
> HWD_VIIF_L1_INPUT_INTERPOLATION_LINE &&
> > + in_img->interpolation_mode !=
> HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->input_num < HWD_VIIF_L1_INPUT_NUM_MIN ||
> > + in_img->input_num > HWD_VIIF_L1_INPUT_NUM_MAX) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->hobc_width != 0U && in_img->hobc_width != 16U &&
> in_img->hobc_width != 32U &&
> > + in_img->hobc_width != 64U && in_img->hobc_width != 128U) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->hobc_margin > 30U || ((in_img->hobc_margin % 2U) !=
> 0U))
> > + return -EINVAL;
> > +
> > + if (in_img->hobc_width == 0U && in_img->hobc_margin != 0U)
> > + return -EINVAL;
> > +
> > + if (in_img->hobc_width != 0U && in_img->hobc_margin == 0U)
> > + return -EINVAL;
> > +
> > + if (color_type == CSI2_DT_RAW8 || color_type == CSI2_DT_RAW10 ||
> > + color_type == CSI2_DT_RAW12 || color_type == CSI2_DT_RAW14)
> {
> > + /* parameter check in case of L1ISP(in case of RAW) */
> > + if (in_img->hactive_size <
> HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP ||
> > + in_img->hactive_size >
> HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP ||
> > + in_img->vactive_size <
> HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP ||
> > + in_img->vactive_size >
> HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP ||
> > + ((in_img->hactive_size % 8U) != 0U)) {
> > + return -EINVAL;
> > + }
> > +
> > + /* check vbp range in case of L1ISP on */
> > + /* the constant value "7" is configuration margin */
> > + val = sysclk_to_numlines(
> > + HWD_VIIF_TABLE_LOAD_TIME +
> HWD_VIIF_REGBUF_ACCESS_TIME * 2U, in_img) +
> > + HWD_VIIF_L1_DELAY_W_HDRC + 7U;
> > + if (in_img->vbp_size < val)
> > + return -EINVAL;
> > +
> > + /* calculate total of horizontal active size and vertical active size
> */
> > + if (rawpack != HWD_VIIF_RAWPACK_DISABLE) {
> > + val = (in_img->hactive_size + in_img->hobc_width +
> in_img->hobc_margin) *
> > + 2U;
> > + } else {
> > + val = in_img->hactive_size + in_img->hobc_width +
> in_img->hobc_margin;
> > + }
> > + if (in_img->interpolation_mode ==
> HWD_VIIF_L1_INPUT_INTERPOLATION_LINE) {
> > + total_hact_size = val;
> > + total_vact_size = in_img->vactive_size *
> in_img->input_num;
> > + } else {
> > + total_hact_size = val * in_img->input_num;
> > + total_vact_size = in_img->vactive_size;
> > + }
> > + } else {
> > + /* OTHER input than RAW(L1ISP is off) */
> > + if (in_img->hactive_size <
> HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP ||
> > + in_img->hactive_size >
> HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP ||
> > + in_img->vactive_size <
> HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP ||
> > + in_img->vactive_size >
> HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP ||
> > + in_img->interpolation_mode !=
> HWD_VIIF_L1_INPUT_INTERPOLATION_LINE ||
> > + in_img->input_num != HWD_VIIF_L1_INPUT_NUM_MIN
> || in_img->hobc_width != 0U) {
> > + return -EINVAL;
> > + }
> > +
> > + /* check vbp range in case of L1ISP off */
> > + /* the constant value "16" is configuration margin */
> > + val = sysclk_to_numlines(HWD_VIIF_TABLE_LOAD_TIME +
> HWD_VIIF_REGBUF_ACCESS_TIME,
> > + in_img) +
> > + 16U;
> > + if (in_img->vbp_size < val)
> > + return -EINVAL;
> > +
> > + total_hact_size = in_img->hactive_size;
> > + total_vact_size = in_img->vactive_size;
> > + }
> > +
> > + if (in_img->htotal_size <= total_hact_size ||
> > + (in_img->vtotal_size <= (in_img->vbp_size + total_vact_size))) {
> > + return -EINVAL;
> > + }
> > +
> > + if (yuv_conv != HWD_VIIF_YUV_CONV_REPEAT && yuv_conv !=
> HWD_VIIF_YUV_CONV_INTERPOLATION)
> > + return -EINVAL;
> > +
> > + if (color_type != CSI2_DT_YUV4228B && color_type !=
> CSI2_DT_YUV42210B &&
> > + yuv_conv != HWD_VIIF_YUV_CONV_REPEAT) {
> > + return -EINVAL;
> > + }
> > +
> > + /* Set DT and color type of image data */
> > + writel((color_type << 8U) | dt_image,
> &res->capture_reg->sys.IPORTM_MAIN_DT);
> > + writel(0x00, &res->capture_reg->sys.IPORTM_OTHER);
> > + res->dt_image_main_w_isp = dt_image;
> > +
> > + /* Set back porch*/
> > + writel((in_img->vbp_size << 16U) | HWD_VIIF_HBP_SYSCLK,
> > + &res->capture_reg->sys.BACK_PORCH_M);
> > +
> > + /* single pulse of vsync is input to DPGM */
> > + writel(HWD_VIIF_DPGM_VSYNC_PULSE,
> &res->capture_reg->sys.DPGM_VSYNC_SOURCE);
> > +
> > + /* image data will be input */
> > + /* set preprocess type before L2ISP based on color_type. */
> > + if (color_type == CSI2_DT_YUV4228B || color_type ==
> CSI2_DT_YUV42210B) {
> > + /* YUV422 */
> > + color = 3U;
> > + } else if (color_type == CSI2_DT_RGB565 || color_type ==
> CSI2_DT_RGB888) {
> > + /* RGB */
> > + color = 0U;
> > + } else {
> > + /* RGB or YUV444 from L1ISP */
> > + color = 1U;
> > + }
> > + writel(color << 4U, &res->capture_reg->sys.PREPROCCESS_FMTM);
> > +
> > + /* set Total size and valid size information of image data */
> > + sysclk_num = lineperiod_in_sysclk(in_img->htotal_size,
> in_img->pixel_clock);
> > + sysclk_num &= GENMASK(15, 0);
> > + writel((in_img->vtotal_size << 16U) | sysclk_num,
> &res->capture_reg->sys.TOTALSIZE_M);
> > + writel((total_vact_size << 16U) | total_hact_size,
> &res->capture_reg->sys.VALSIZE_M);
> > +
> > + /* set image size information to L2ISP */
> > + writel(in_img->vactive_size,
> &res->capture_reg->l2isp.L2_SENSOR_CROP_VSIZE);
> > + writel(in_img->hactive_size,
> &res->capture_reg->l2isp.L2_SENSOR_CROP_HSIZE);
> > +
> > + /* RAW input case */
> > + if (color_type >= CSI2_DT_RAW8) {
> > + val = (in_img->interpolation_mode << 3U) |
> (in_img->input_num);
> > + writel(val,
> &res->capture_reg->l1isp.L1_IBUF_INPUT_ORDER);
> > + writel(in_img->vactive_size,
> &res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> > + writel(in_img->hactive_size,
> &res->capture_reg->l1isp.L1_SYSM_WIDTH);
> > + val = (in_img->hobc_margin << 8U) | in_img->hobc_width;
> > + writel(val, &res->capture_reg->l1isp.L1_HOBC_MARGIN);
> > + }
> > +
> > + /* Set rawpack */
> > + writel(rawpack, &res->capture_reg->sys.IPORTM_MAIN_RAW);
> > +
> > + /* Set yuv_conv */
> > + writel(yuv_conv, &res->capture_reg->sys.PREPROCCESS_C24M);
> > +
> > + /* Set vsync delay */
> > + hw_delay = in_img->vbp_size -
> sysclk_to_numlines(HWD_VIIF_TABLE_LOAD_TIME, in_img) + 4U;
> > + hw_delay = min(hw_delay, 255U);
> > +
> > + sw_delay0 = hw_delay -
> sysclk_to_numlines(HWD_VIIF_REGBUF_ACCESS_TIME, in_img) + 2U;
> > +
> > + if (color_type == CSI2_DT_RAW8 || color_type == CSI2_DT_RAW10 ||
> > + color_type == CSI2_DT_RAW12 || color_type == CSI2_DT_RAW14)
> {
> > + sw_delay1 =
> sysclk_to_numlines(HWD_VIIF_REGBUF_ACCESS_TIME, in_img) +
> > + HWD_VIIF_L1_DELAY_WO_HDRC + 1U;
> > + } else {
> > + sw_delay1 = 10U;
> > + }
> > + writel(sw_delay0 << 16U, &res->capture_reg->sys.INT_M0_LINE);
> > + writel((sw_delay1 << 16U) | hw_delay,
> &res->capture_reg->sys.INT_M1_LINE);
> > +
> > + /* M2_LINE is the same condition as M1_LINE */
> > + writel((sw_delay1 << 16U) | hw_delay,
> &res->capture_reg->sys.INT_M2_LINE);
> > +
> > + /* Update internal information of pixel clock, htotal_size, information of
> L2 ROI */
> > + res->pixel_clock = in_img->pixel_clock;
> > + res->htotal_size = in_img->htotal_size;
> > + res->l2_roi_path_info.roi_num = 0;
> > + for (i = 0; i < HWD_VIIF_MAX_POST_NUM; i++) {
> > + res->l2_roi_path_info.post_enable_flag[i] = false;
> > + res->l2_roi_path_info.post_crop_x[i] = 0;
> > + res->l2_roi_path_info.post_crop_y[i] = 0;
> > + res->l2_roi_path_info.post_crop_w[i] = 0;
> > + res->l2_roi_path_info.post_crop_h[i] = 0;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_main_mask_vlatch() - Control Vlatch mask of MAIN unit
> > + *
> > + * @enable: or disable Vlatch mask of MAIN unit. For more refer @ref
> hwd_viif_enable_flag.
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - "enable" is out of range
> > + */
> > +s32 hwd_viif_main_mask_vlatch(struct hwd_viif_res *res, u32 enable)
> > +{
> > + if (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
> > + return -EINVAL;
>
> The function would be nicer to use if it took bool as the argument. You
> could remove this check, too.
I'll use bool type. Same for other functions.
> > +
> > + if (enable == HWD_VIIF_ENABLE)
> > + enable |= HWD_VIIF_ISP_VLATCH_MASK;
> > +
> > + /* Control Vlatch mask */
> > + writel(enable, &res->capture_reg->sys.IPORTM0_LD);
> > + writel(enable, &res->capture_reg->sys.IPORTM1_LD);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_main_status_err_set_irq_mask() - Set mask condition for
> STATUS error of MAIN unit
> > + *
> > + * @mask: STATUS error mask condition
> > + * Return: None
> > + */
> > +void hwd_viif_main_status_err_set_irq_mask(struct hwd_viif_res *res, u32
> mask)
> > +{
> > + writel(mask, &res->capture_reg->sys.INT_M_MASK);
> > +}
> > +
> > +/**
> > + * hwd_viif_main_vsync_set_irq_mask() - Set mask condition for Vsync of
> MAIN unit
> > + *
> > + * @mask: Vsync mask condition
> > + * Return: None
> > + */
> > +void hwd_viif_main_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> > +{
> > + writel(mask, &res->capture_reg->sys.INT_M_SYNC_MASK);
> > +}
> > +
> > +#define VDM_BIT_W00 BIT(0)
> > +#define VDM_BIT_W01 BIT(1)
> > +#define VDM_BIT_W02 BIT(2)
> > +#define VDM_BIT_W03 BIT(3)
> > +#define VDM_BIT_W04 BIT(4)
> > +#define VDM_BIT_W05 BIT(5)
> > +#define VDM_BIT_R00 BIT(0)
> > +#define VDM_BIT_R01 BIT(1)
> > +#define VDM_BIT_R02 BIT(2)
> > +
> > +#define VDM_ABORT_MASK_SUB_W (VDM_BIT_W03 | VDM_BIT_W04 |
> VDM_BIT_W05)
> > +#define VDM_ABORT_MASK_MAIN_W (VDM_BIT_W00 | VDM_BIT_W01 |
> VDM_BIT_W02)
> > +#define VDM_ABORT_MASK_MAIN_R (VDM_BIT_R00 | VDM_BIT_R01 |
> VDM_BIT_R02)
> > +
> > +/**
> > + * hwd_viif_sub_set_unit() - Set static configuration of SUB unit
> > + *
> > + * @dt_image: DT of image [0x1E, 0x1F, 0x22, 0x24, 0x2A-0x2D]
> > + * @in_img: Pointer to input image information
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "dt_image" is out of range
> > + * - [2] "in_img" is NULL
> > + * - [3] member of "in_img" is invalid
> > + */
> > +s32 hwd_viif_sub_set_unit(struct hwd_viif_res *res, u32 dt_image,
> > + const struct hwd_viif_input_img *in_img)
> > +{
> > + u32 sysclk_num, temp_delay;
> > +
> > + if (dt_image < 0x2aU || dt_image > 0x2dU)
> > + return -EINVAL;
> > +
> > + if (!in_img)
> > + return -EINVAL;
> > +
> > + if (in_img->hactive_size != 0U ||
> > + in_img->interpolation_mode !=
> HWD_VIIF_L1_INPUT_INTERPOLATION_LINE ||
> > + in_img->input_num != HWD_VIIF_L1_INPUT_NUM_MIN ||
> in_img->hobc_width != 0U ||
> > + in_img->hobc_margin != 0U) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->pixel_clock < HWD_VIIF_MIN_PIXEL_CLOCK ||
> > + in_img->pixel_clock > HWD_VIIF_MAX_PIXEL_CLOCK ||
> > + in_img->htotal_size < HWD_VIIF_MIN_HTOTAL_PIXEL ||
> > + in_img->htotal_size > HWD_VIIF_MAX_HTOTAL_PIXEL ||
> > + in_img->vtotal_size < HWD_VIIF_MIN_VTOTAL_LINE ||
> > + in_img->vtotal_size > HWD_VIIF_MAX_VTOTAL_LINE ||
> > + in_img->vbp_size < HWD_VIIF_MIN_VBP_LINE ||
> in_img->vbp_size > HWD_VIIF_MAX_VBP_LINE ||
> > + in_img->vactive_size <
> HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP ||
> > + in_img->vactive_size >
> HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP ||
> > + ((in_img->vactive_size % 2U) != 0U)) {
> > + return -EINVAL;
> > + }
> > +
> > + if (in_img->vtotal_size <= (in_img->vbp_size + in_img->vactive_size))
> > + return -EINVAL;
> > +
> > + /* Set DT of image data and DT of long packet data*/
> > + writel(dt_image, &res->capture_reg->sys.IPORTS_MAIN_DT);
> > + writel(0x00, &res->capture_reg->sys.IPORTS_OTHER);
> > +
> > + /* Set line size and delay value of delayed Vsync */
> > + sysclk_num = lineperiod_in_sysclk(in_img->htotal_size,
> in_img->pixel_clock);
> > + writel(sysclk_num & GENMASK(15, 0),
> &res->capture_reg->sys.INT_SA0_LINE);
> > + temp_delay = in_img->vbp_size - 4U;
> > + if (temp_delay > 255U) {
> > + /* Replace the value with HW max spec */
> > + temp_delay = 255U;
> > + }
> > + writel(temp_delay, &res->capture_reg->sys.INT_SA1_LINE);
> > +
> > + return 0;
> > +}
> > +
> > +/* DMA settings */
> > +#define VDMAC_SRAM_BASE_ADDR_W03 0x440U
> > +#define SRAM_SIZE_W_PORT 0x200
> > +#define PORT_SEL_SUB_IMAGE 3
> > +
> > +/**
> > + * hwd_viif_sub_set_img_transmission() - Set image transfer condition of
> SUB unit
> > + *
> > + * @img: Pointer to output image information
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] Member of "img" is invalid
> > + */
> > +s32 hwd_viif_sub_set_img_transmission(struct hwd_viif_res *res, const
> struct hwd_viif_img *img)
> > +{
> > + struct hwd_viif_vdm_write_port_reg *wport;
> > + u32 img_start_addr, img_end_addr;
> > + u32 data_width, pitch, height;
> > + u32 k, port_control;
> > +
> > + /* disable VDMAC when img is NULL */
> > + if (!img) {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTS_IMGEN);
> > + port_control = ~((u32)1U << 3U) &
> readl(&res->capture_reg->vdm.VDM_W_ENABLE);
> > + writel(port_control,
> &res->capture_reg->vdm.VDM_W_ENABLE);
> > + return 0;
> > + }
> > +
> > + if (((img->width % 2U) != 0U) || ((img->height % 2U) != 0U))
> > + return -EINVAL;
> > +
> > + if (img->width < HWD_VIIF_MIN_OUTPUT_IMG_WIDTH ||
> > + img->height < HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT ||
> > + img->width > HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB ||
> > + img->height > HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB) {
> > + return -EINVAL;
> > + }
> > +
> > + img_start_addr = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch = img->pixelmap[0].pitch;
> > + height = img->height;
> > +
> > + switch (img->format) {
> > + case HWD_VIIF_ONE_COLOR_8:
> > + data_width = 0U;
> > + img_end_addr = img_start_addr + img->width - 1U;
> > + k = 1;
> > + break;
> > + case HWD_VIIF_ONE_COLOR_16:
> > + data_width = 1U;
> > + img_end_addr = img_start_addr + (img->width * 2U) - 1U;
> > + k = 2;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + if ((img_start_addr % 4U) != 0U)
> > + return -EINVAL;
> > +
> > + if ((pitch < (img->width * k)) || pitch > HWD_VIIF_MAX_PITCH ||
> ((pitch % 4U) != 0U))
> > + return -EINVAL;
> > +
> > + wport = &res->capture_reg->vdm.w_port[PORT_SEL_SUB_IMAGE];
> > + writel(VDMAC_SRAM_BASE_ADDR_W03,
> &wport->VDM_W_SRAM_BASE);
> > + writel(SRAM_SIZE_W_PORT, &wport->VDM_W_SRAM_SIZE);
> > + writel(img_start_addr, &wport->VDM_W_STADR);
> > + writel(img_end_addr, &wport->VDM_W_ENDADR);
> > + writel(height, &wport->VDM_W_HEIGHT);
> > + writel(pitch, &wport->VDM_W_PITCH);
> > + writel(data_width << 8U, &wport->VDM_W_CFG0);
> > + port_control = BIT(3) |
> readl(&res->capture_reg->vdm.VDM_W_ENABLE);
> > + writel(port_control, &res->capture_reg->vdm.VDM_W_ENABLE);
> > + writel(HWD_VIIF_ENABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_sub_status_err_set_irq_mask() -
> > + * Set mask condition for STATUS error of SUB unit or VOIF loopback
> > + *
> > + * @mask: STATUS error mask condition
> > + * Return: None
> > + */
> > +void hwd_viif_sub_status_err_set_irq_mask(struct hwd_viif_res *res, u32
> mask)
> > +{
> > + writel(mask, &res->capture_reg->sys.INT_S_MASK);
> > +}
> > +
> > +/**
> > + * hwd_viif_sub_vsync_set_irq_mask() - Set mask condition for Vsync of SUB
> unit or VOIF loopback
> > + *
> > + * @mask: Vsync mask condition
> > + * Return: None
> > + */
> > +void hwd_viif_sub_vsync_set_irq_mask(struct hwd_viif_res *res, const u32
> mask)
> > +{
> > + writel(mask, &res->capture_reg->sys.INT_S_SYNC_MASK);
> > +}
> > +
> > +/**
> > + * hwd_viif_isp_set_regbuf_auto_transmission() - Set register buffer auto
> transmission
> > + *
> > + * Return: None
> > + */
> > +void hwd_viif_isp_set_regbuf_auto_transmission(struct hwd_viif_res *res)
> > +{
> > + u32 val;
> > +
> > + /* Set parameters for auto read transmission of register buffer */
> > +
> > + if (res->dt_image_main_w_isp != 0x0U) {
> > + /*
> > + * configuration is done
> > + * only when dt_image is not 0, means image data is input to
> ISP.
> > + */
> > + writel(0x0,
> &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> > + writel(0x0,
> &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> > + writel(HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT,
> > + &res->capture_reg->l1isp.L1_CRGBF_TRN_RBADDR);
> > + writel(HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT,
> > + &res->capture_reg->l1isp.L1_CRGBF_TRN_READDR);
> > + writel(HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT,
> > + &res->capture_reg->l2isp.L2_CRGBF_TRN_RBADDR);
> > + writel(HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT,
> > + &res->capture_reg->l2isp.L2_CRGBF_TRN_READDR);
> > + val = BIT(16);
> > + writel(val,
> &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> > + writel(val,
> &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_isp_disable_regbuf_auto_transmission() - Disable register buffer
> auto transmission
> > + *
> > + * Return: None
> > + */
> > +void hwd_viif_isp_disable_regbuf_auto_transmission(struct hwd_viif_res
> *res)
> > +{
> > + if (res->dt_image_main_w_isp != 0x0U) {
> > + writel(0x0,
> &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> > + writel(0x0,
> &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_isp_guard_start() - stop register auto update
> > + *
> > + *
> > + * This function call stops update of some hardware registers
> > + * while the manual setup of VIIF, L1ISP registers is in progress.
> > + *
> > + * * regbuf control: load/store HW register (settings, status) values to backup
> SRAM.
> > + * * vlatch control: copy timer-counter register value to status register.
> > + */
> > +void hwd_viif_isp_guard_start(struct hwd_viif_res *res)
> > +{
> > + hwd_viif_isp_disable_regbuf_auto_transmission(res);
> > + ndelay(500);
> > + hwd_viif_main_mask_vlatch(res, HWD_VIIF_ENABLE);
> > +}
> > +
> > +/**
> > + * hwd_viif_isp_guard_start() - restart register auto update
> > + *
> > + *
> > + * see also hwd_viif_isp_guard_start().
> > + */
> > +void hwd_viif_isp_guard_end(struct hwd_viif_res *res)
> > +{
> > + hwd_viif_main_mask_vlatch(res, HWD_VIIF_DISABLE);
> > + hwd_viif_isp_set_regbuf_auto_transmission(res);
> > +}
> > +
> > +#define L2_STATUS_REPORT_MASK 0x1eU
> > +
> > +/**
> > + * hwd_viif_isp_get_info() - Get processing information of L1ISP and L2ISP
> > + *
> > + * @l1_info: L1ISP processing information
> > + * @l2_transfer_status: status of L2ISP transmission
> > + * Return: None
> > + */
> > +void hwd_viif_isp_get_info(struct hwd_viif_res *res, struct hwd_viif_l1_info
> *l1_info,
> > + u32 *l2_transfer_status)
> > +{
> > + u32 val, l2_status;
> > + int i, j;
> > +
> > + if (l1_info) {
> > + /* change register buffer to regbuf0 where driver gets
> information */
> > + writel(HWD_VIIF_ISP_REGBUF_MODE_BUFFER,
> &res->capture_reg->l1isp.L1_CRGBF_ACC_CONF);
> > +
> > + /* get AWB info */
> > + l1_info->awb_ave_u =
> readl(&res->capture_reg->l1isp.L1_AWHB_AVE_USIG);
> > + l1_info->awb_ave_v =
> readl(&res->capture_reg->l1isp.L1_AWHB_AVE_VSIG);
> > + l1_info->awb_accumulated_pixel =
> readl(&res->capture_reg->l1isp.L1_AWHB_NUM_UVON);
> > + l1_info->awb_gain_r =
> readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAINR);
> > + l1_info->awb_gain_g =
> readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAING);
> > + l1_info->awb_gain_b =
> readl(&res->capture_reg->l1isp.L1_AWHB_AWBGAINB);
> > + val =
> readl(&res->capture_reg->l1isp.L1_AWHB_R_CTR_STOP);
> > + l1_info->awb_status_u = (FIELD_GET(BIT(1), val) != 0);
> > + l1_info->awb_status_v = (FIELD_GET(BIT(0), val) != 0);
> > +
> > + /* get average luminance info */
> > + l1_info->avg_lum_weight =
> readl(&res->capture_reg->l1isp.L1_AEXP_RESULT_AVE);
> > + val =
> readl(&res->capture_reg->l1isp.L1_AEXP_SATUR_BLACK_PIXNUM);
> > + l1_info->avg_satur_pixnum = FIELD_GET(GENMASK(31, 16),
> val);
> > + l1_info->avg_black_pixnum = FIELD_GET(GENMASK(15, 0),
> val);
> > + for (i = 0; i < 8; i++) {
> > + for (j = 0; j < 8; j++) {
> > + l1_info->avg_lum_block[i][j] =
> > +
> readl(&res->capture_reg->l1isp.L1_AEXP_AVE[i][j]);
> > + }
> > + }
> > + l1_info->avg_lum_four_line_lum[0] =
> > +
> readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES0);
> > + l1_info->avg_lum_four_line_lum[1] =
> > +
> readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES1);
> > + l1_info->avg_lum_four_line_lum[2] =
> > +
> readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES2);
> > + l1_info->avg_lum_four_line_lum[3] =
> > +
> readl(&res->capture_reg->l1isp.L1_AEXP_AVE4LINES3);
> > +
> > + /* revert to register access from register buffer access */
> > + writel(HWD_VIIF_ISP_REGBUF_MODE_BYPASS,
> &res->capture_reg->l1isp.L1_CRGBF_ACC_CONF);
> > + }
> > +
> > + if (l2_transfer_status) {
> > + /* get L2ISP abort information */
> > + l2_status =
> readl(&res->capture_reg->l2isp.L2_CRGBF_ISP_INT);
> > + writel(l2_status,
> &res->capture_reg->l2isp.L2_CRGBF_ISP_INT);
> > + *l2_transfer_status = l2_status &
> L2_STATUS_REPORT_MASK;
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_isp_set_regbuf_irq_mask() - Set mask condition for ISP register
> buffer
> > + *
> > + * @mask_l1: Pointer to mask configuration for L1ISP register buffer
> interruption
> > + * @mask_l2: Pointer to mask configuration for L2ISP register buffer
> interruption
> > + * Return: None
> > + */
> > +void hwd_viif_isp_set_regbuf_irq_mask(struct hwd_viif_res *res, const u32
> *mask_l1,
> > + const u32 *mask_l2)
> > +{
> > + writel(*mask_l1, &res->capture_reg->l1isp.L1_CRGBF_INT_MASK);
> > + writel(*mask_l2, &res->capture_reg->l2isp.L2_CRGBF_INT_MASK);
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_input_csc() - Set input CSC parameters of L2ISP
> > + *
> > + * @param: Pointer to input csc parameters of L2ISP
> > + * @is_l1_rgb: input information of L2ISP
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] Member of "param" is invalid
> > + */
> > +s32 hwd_viif_l2_set_input_csc(struct hwd_viif_res *res, const struct
> hwd_viif_csc_param *param,
> > + bool is_l1_rgb)
> > +{
> > + struct hwd_viif_csc_param hwd_param;
> > + u32 enable = HWD_VIIF_ENABLE;
> > + bool csc_enable_flag = true;
> > + u32 i, val;
> > +
> > + if (param) {
> > + if (param->r_cr_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->g_y_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->b_cb_in_offset > HWD_VIIF_CSC_MAX_OFFSET
> ||
> > + param->r_cr_out_offset > HWD_VIIF_CSC_MAX_OFFSET
> ||
> > + param->g_y_out_offset > HWD_VIIF_CSC_MAX_OFFSET
> ||
> > + param->b_cb_out_offset >
> HWD_VIIF_CSC_MAX_OFFSET) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < HWD_VIIF_CSC_MAX_COEF_NUM; i++) {
> > + if (param->coef[i] >
> HWD_VIIF_CSC_MAX_COEF_VALUE)
> > + return -EINVAL;
> > + }
> > +
> > + if (is_l1_rgb) {
> > + /* translated parameters are used */
> > + hwd_param.r_cr_in_offset = param->b_cb_in_offset;
> > + hwd_param.g_y_in_offset = param->r_cr_in_offset;
> > + hwd_param.b_cb_in_offset = param->g_y_in_offset;
> > + hwd_param.r_cr_out_offset = param->r_cr_out_offset;
> > + hwd_param.g_y_out_offset = param->g_y_out_offset;
> > + hwd_param.b_cb_out_offset =
> param->b_cb_out_offset;
> > + hwd_param.coef[0] = param->coef[2];
> > + hwd_param.coef[1] = param->coef[0];
> > + hwd_param.coef[2] = param->coef[1];
> > + hwd_param.coef[3] = param->coef[5];
> > + hwd_param.coef[4] = param->coef[3];
> > + hwd_param.coef[5] = param->coef[4];
> > + hwd_param.coef[6] = param->coef[8];
> > + hwd_param.coef[7] = param->coef[6];
> > + hwd_param.coef[8] = param->coef[7];
> > + } else {
> > + /* original parameters are used */
> > + hwd_param.r_cr_in_offset = param->r_cr_in_offset;
> > + hwd_param.g_y_in_offset = param->g_y_in_offset;
> > + hwd_param.b_cb_in_offset = param->b_cb_in_offset;
> > + hwd_param.r_cr_out_offset = param->r_cr_out_offset;
> > + hwd_param.g_y_out_offset = param->g_y_out_offset;
> > + hwd_param.b_cb_out_offset =
> param->b_cb_out_offset;
> > + hwd_param.coef[0] = param->coef[0];
> > + hwd_param.coef[1] = param->coef[1];
> > + hwd_param.coef[2] = param->coef[2];
> > + hwd_param.coef[3] = param->coef[3];
> > + hwd_param.coef[4] = param->coef[4];
> > + hwd_param.coef[5] = param->coef[5];
> > + hwd_param.coef[6] = param->coef[6];
> > + hwd_param.coef[7] = param->coef[7];
> > + hwd_param.coef[8] = param->coef[8];
> > + }
> > + } else {
> > + if (is_l1_rgb) {
> > + /* fixed parameters are used */
> > + hwd_param.r_cr_in_offset = 0U;
> > + hwd_param.g_y_in_offset = 0U;
> > + hwd_param.b_cb_in_offset = 0U;
> > + hwd_param.r_cr_out_offset = 0U;
> > + hwd_param.g_y_out_offset = 0U;
> > + hwd_param.b_cb_out_offset = 0U;
> > + hwd_param.coef[0] = 0U;
> > + hwd_param.coef[1] = 0x1000U;
> > + hwd_param.coef[2] = 0U;
> > + hwd_param.coef[3] = 0U;
> > + hwd_param.coef[4] = 0U;
> > + hwd_param.coef[5] = 0x1000U;
> > + hwd_param.coef[6] = 0x1000U;
> > + hwd_param.coef[7] = 0U;
> > + hwd_param.coef[8] = 0U;
> > + } else {
> > + /* csc is disabled */
> > + enable = HWD_VIIF_DISABLE;
> > + csc_enable_flag = false;
> > + }
> > + }
> > +
> > + if (csc_enable_flag) {
> > + writel(hwd_param.g_y_in_offset,
> > +
> &res->capture_reg->sys.l2isp_input_csc.MTB_YG_OFFSETI);
> > + writel(hwd_param.coef[0],
> &res->capture_reg->sys.l2isp_input_csc.MTB_YG1);
> > + val = (hwd_param.coef[1] <<
> HWD_VIIF_MTB_CB_YG_COEF_OFFSET) |
> > + (hwd_param.coef[2] <<
> HWD_VIIF_MTB_CR_YG_COEF_OFFSET);
> > + writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_YG2);
> > + writel(hwd_param.g_y_out_offset,
> > +
> &res->capture_reg->sys.l2isp_input_csc.MTB_YG_OFFSETO);
> > + writel(hwd_param.b_cb_in_offset,
> > +
> &res->capture_reg->sys.l2isp_input_csc.MTB_CB_OFFSETI);
> > + writel(hwd_param.coef[3],
> &res->capture_reg->sys.l2isp_input_csc.MTB_CB1);
> > + val = (hwd_param.coef[4] <<
> HWD_VIIF_MTB_CB_CB_COEF_OFFSET) |
> > + (hwd_param.coef[5] <<
> HWD_VIIF_MTB_CR_CB_COEF_OFFSET);
> > + writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_CB2);
> > + writel(hwd_param.b_cb_out_offset,
> > +
> &res->capture_reg->sys.l2isp_input_csc.MTB_CB_OFFSETO);
> > + writel(hwd_param.r_cr_in_offset,
> > +
> &res->capture_reg->sys.l2isp_input_csc.MTB_CR_OFFSETI);
> > + writel(hwd_param.coef[6],
> &res->capture_reg->sys.l2isp_input_csc.MTB_CR1);
> > + val = (hwd_param.coef[7] <<
> HWD_VIIF_MTB_CB_CR_COEF_OFFSET) |
> > + (hwd_param.coef[8] <<
> HWD_VIIF_MTB_CR_CR_COEF_OFFSET);
> > + writel(val, &res->capture_reg->sys.l2isp_input_csc.MTB_CR2);
> > + writel(hwd_param.r_cr_out_offset,
> > +
> &res->capture_reg->sys.l2isp_input_csc.MTB_CR_OFFSETO);
> > + }
> > +
> > + writel(enable, &res->capture_reg->sys.l2isp_input_csc.MTB);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_undist() - Set undistortion parameters of L2ISP
> > + *
> > + * @param: Pointer to undistortion parameters of L2ISP
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "param" is NULL
> > + * - [2] Member of "param" is invalid
> > + */
> > +s32 hwd_viif_l2_set_undist(struct hwd_viif_res *res, const struct
> viif_l2_undist *param)
> > +{
> > + u32 grid_num_h, grid_num_v;
> > + u32 i, val;
> > +
> > + if (!param)
> > + return -EINVAL;
> > +
> > + if (param->through_mode != HWD_VIIF_ENABLE &&
> param->through_mode != HWD_VIIF_DISABLE)
> > + return -EINVAL;
> > +
> > + if (param->roi_mode[0] != HWD_VIIF_L2_UNDIST_POLY &&
> > + param->roi_mode[0] != HWD_VIIF_L2_UNDIST_GRID &&
> > + param->roi_mode[0] != HWD_VIIF_L2_UNDIST_POLY_TO_GRID
> &&
> > + param->roi_mode[0] != HWD_VIIF_L2_UNDIST_GRID_TO_POLY)
> {
> > + return -EINVAL;
> > + }
> > + if (param->roi_mode[1] != HWD_VIIF_L2_UNDIST_POLY &&
> > + param->roi_mode[1] != HWD_VIIF_L2_UNDIST_GRID &&
> > + param->roi_mode[1] != HWD_VIIF_L2_UNDIST_POLY_TO_GRID
> &&
> > + param->roi_mode[1] != HWD_VIIF_L2_UNDIST_GRID_TO_POLY)
> {
> > + return -EINVAL;
> > + }
> > + if (param->roi_write_area_delta[0] >=
> HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA ||
> > + param->roi_write_area_delta[1] >=
> HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA ||
> > + param->sensor_crop_ofs_h <
> HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H ||
> > + param->sensor_crop_ofs_h >
> HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H ||
> > + param->sensor_crop_ofs_v <
> HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V ||
> > + param->sensor_crop_ofs_v >
> HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V ||
> > + param->norm_scale >
> HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE ||
> > + param->valid_r_norm2_poly >=
> HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2 ||
> > + param->valid_r_norm2_grid >=
> HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < HWD_VIIF_L2_UNDIST_POLY_NUM; i++) {
> > + if (param->poly_write_g_coef[i] <
> HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> > + param->poly_write_g_coef[i] >
> HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
> > + param->poly_read_b_coef[i] <
> HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> > + param->poly_read_b_coef[i] >
> HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
> > + param->poly_read_g_coef[i] <
> HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> > + param->poly_read_g_coef[i] >
> HWD_VIIF_L2_UNDIST_MAX_POLY_COEF ||
> > + param->poly_read_r_coef[i] <
> HWD_VIIF_L2_UNDIST_MIN_POLY_COEF ||
> > + param->poly_read_r_coef[i] >
> HWD_VIIF_L2_UNDIST_MAX_POLY_COEF) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->grid_node_num_h <
> HWD_VIIF_L2_UNDIST_MIN_GRID_NUM ||
> > + param->grid_node_num_h >
> HWD_VIIF_L2_UNDIST_MAX_GRID_NUM ||
> > + param->grid_node_num_v <
> HWD_VIIF_L2_UNDIST_MIN_GRID_NUM ||
> > + param->grid_node_num_v >
> HWD_VIIF_L2_UNDIST_MAX_GRID_NUM) {
> > + return -EINVAL;
> > + }
> > +
> > + grid_num_h = param->grid_node_num_h;
> > + grid_num_v = param->grid_node_num_v;
> > + if ((grid_num_h % 2U) != 0U)
> > + grid_num_h += 1U;
> > +
> > + if ((grid_num_v % 2U) != 0U)
> > + grid_num_v += 1U;
> > +
> > + if ((grid_num_v * grid_num_h) >
> HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM ||
> > + param->grid_patch_hsize_inv >=
> HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV ||
> > + param->grid_patch_vsize_inv >=
> HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV) {
> > + return -EINVAL;
> > + }
> > +
> > + val = readl(&res->capture_reg->l2isp.L2_SENSOR_CROP_HSIZE) &
> GENMASK(12, 0);
> > + if (((param->sensor_crop_ofs_h / 2) + ((s16)val)) > 4095)
> > + return -EINVAL;
> > +
> > + val = readl(&res->capture_reg->l2isp.L2_SENSOR_CROP_VSIZE) &
> GENMASK(11, 0);
> > + if (((param->sensor_crop_ofs_v / 2) + ((s16)val)) > 2047)
> > + return -EINVAL;
> > +
> > + /* set parameters related to L2ISP UNDIST */
> > + if (param->through_mode == HWD_VIIF_ENABLE) {
> > + /* Enable through mode */
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l2isp.L2_MODE);
> > + } else {
> > + val = (param->roi_mode[0] << 1U) | (param->roi_mode[1] <<
> 3U);
> > + writel(val, &res->capture_reg->l2isp.L2_MODE);
> > + val = (u32)param->sensor_crop_ofs_h & GENMASK(13, 0);
> > + writel(val,
> &res->capture_reg->l2isp.L2_SENSOR_CROP_OFS_H);
> > + val = (u32)param->sensor_crop_ofs_v & GENMASK(12, 0);
> > + writel(val,
> &res->capture_reg->l2isp.L2_SENSOR_CROP_OFS_V);
> > + writel(param->norm_scale,
> &res->capture_reg->l2isp.L2_NORM_SCALE);
> > + writel(param->valid_r_norm2_poly,
> &res->capture_reg->l2isp.L2_VALID_R_NORM2_POLY);
> > + writel(param->valid_r_norm2_grid,
> &res->capture_reg->l2isp.L2_VALID_R_NORM2_GRID);
> > + writel(param->roi_write_area_delta[0],
> > +
> &res->capture_reg->l2isp.L2_ROI_WRITE_AREA_DELTA[0]);
> > + writel(param->roi_write_area_delta[1],
> > +
> &res->capture_reg->l2isp.L2_ROI_WRITE_AREA_DELTA[1]);
> > +
> > + for (i = 0; i < HWD_VIIF_L2_UNDIST_POLY_NUM; i++) {
> > + val = (u32)param->poly_write_g_coef[i];
> > + writel(val,
> &res->capture_reg->l2isp.L2_POLY10_WRITE_G_COEF[i]);
> > + val = (u32)param->poly_read_b_coef[i];
> > + writel(val,
> &res->capture_reg->l2isp.L2_POLY10_READ_B_COEF[i]);
> > + val = (u32)param->poly_read_g_coef[i];
> > + writel(val,
> &res->capture_reg->l2isp.L2_POLY10_READ_G_COEF[i]);
> > + val = (u32)param->poly_read_r_coef[i];
> > + writel(val,
> &res->capture_reg->l2isp.L2_POLY10_READ_R_COEF[i]);
> > + }
> > + writel(param->grid_node_num_h,
> &res->capture_reg->l2isp.L2_GRID_NODE_NUM_H);
> > + writel(param->grid_node_num_v,
> &res->capture_reg->l2isp.L2_GRID_NODE_NUM_V);
> > + writel(param->grid_patch_hsize_inv,
> > +
> &res->capture_reg->l2isp.L2_GRID_PATCH_HSIZE_INV);
> > + writel(param->grid_patch_vsize_inv,
> > +
> &res->capture_reg->l2isp.L2_GRID_PATCH_VSIZE_INV);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_undist_table_transmission() -
> > + * Configure L2ISP transferring grid table for undistortion.
> > + *
> > + * @write_g: grid table address for G-WRITE(physical address)
> > + * @read_b: grid table address for B-READ(physical address)
> > + * @read_g: grid table address for G-READ(physical address)
> > + * @read_r: grid table address for R-READ(physical address)
> > + * @size: of each table [1024..8192] [byte]
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "write_g", "read_b", "read_g" or "read_r" is not 4byte alignment
> > + * - "size" is out of range
> > + * - "size" is not 0 when all table addresses are 0
> > + */
> > +s32 hwd_viif_l2_set_undist_table_transmission(struct hwd_viif_res *res,
> uintptr_t write_g,
> > + uintptr_t read_b, uintptr_t
> read_g, uintptr_t read_r,
> > + u32 size)
> > +{
> > + u32 val = 0U;
> > +
> > + if (((write_g % HWD_VIIF_L2_VDM_ALIGN) != 0U) || ((read_b %
> HWD_VIIF_L2_VDM_ALIGN) != 0U) ||
> > + ((read_g % HWD_VIIF_L2_VDM_ALIGN) != 0U) || ((read_r %
> HWD_VIIF_L2_VDM_ALIGN) != 0U)) {
> > + return -EINVAL;
> > + }
> > +
> > + if ((size != 0U && size < HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE) ||
> > + size > HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE) {
> > + return -EINVAL;
> > + }
> > +
> > + if ((size % 4U) != 0U)
>
> size % 4 is enough.
I'll drop comparison with zero.
> > + return -EINVAL;
> > +
> > + if (write_g == 0U && read_b == 0U && read_g == 0U && read_r == 0U
> && size != 0U)
> > + return -EINVAL;
> > +
> > + if ((write_g != 0U || read_b != 0U || read_g != 0U || read_r != 0U) &&
> size == 0U)
> > + return -EINVAL;
>
> No explicit comparison with zero is needed here. Same below.
I'll drop explicit comparison with zero. Same for other lines.
> > +
> > + /* read_b: t_port[8], read_g: t_port[9], read_r: t_port[10], write_g:
> t_port[11] */
> > + if (read_b != 0U) {
> > + writel((u32)read_b,
> &res->capture_reg->vdm.t_port[8].VDM_T_STADR);
> > + writel(size, &res->capture_reg->vdm.t_port[8].VDM_T_SIZE);
> > + val |= BIT(8);
> > + }
> > + if (read_g != 0U) {
> > + writel((u32)read_g,
> &res->capture_reg->vdm.t_port[9].VDM_T_STADR);
> > + writel(size, &res->capture_reg->vdm.t_port[9].VDM_T_SIZE);
> > + val |= BIT(9);
> > + }
> > + if (read_r != 0U) {
> > + writel((u32)read_r,
> &res->capture_reg->vdm.t_port[10].VDM_T_STADR);
> > + writel(size, &res->capture_reg->vdm.t_port[10].VDM_T_SIZE);
> > + val |= BIT(10);
> > + }
> > + if (write_g != 0U) {
> > + writel((u32)write_g,
> &res->capture_reg->vdm.t_port[11].VDM_T_STADR);
> > + writel(size, &res->capture_reg->vdm.t_port[11].VDM_T_SIZE);
> > + val |= BIT(11);
> > + }
> > +
> > + if (val != 0U) {
> > + /*
> > + * Set SRAM base address and size.
> > + * t_group[1] is used only to transfer UNDIST table
> > + */
> > + writel(HWD_VIIF_VDM_CFG_PARAM,
> &res->capture_reg->vdm.t_group[1].VDM_T_CFG);
> > + writel(HWD_VIIF_L2_VDM_GRID_SRAM_BASE,
> > +
> &res->capture_reg->vdm.t_group[1].VDM_T_SRAM_BASE);
> > + writel(HWD_VIIF_L2_VDM_GRID_SRAM_SIZE,
> > +
> &res->capture_reg->vdm.t_group[1].VDM_T_SRAM_SIZE);
> > + }
> > +
> > + val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) &
> ~((u32)0xfU << 8U));
> > + writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_roi_num_1() - Set ROI path condition when ROI num is 1
> > + */
> > +static void hwd_viif_l2_set_roi_num_1(struct hwd_viif_res *res)
> > +{
> > + struct hwd_viif_l2_roi_path_info *info = &res->l2_roi_path_info;
> > + u32 val, x_min, x_max, y_min, y_max;
> > + u32 i, x, y, w, h;
> > +
> > + /* ROI0 is input to POST0 and POST1 */
> > + if (info->post_enable_flag[0]) {
> > + /* POST0 is enabled */
> > + x_min = info->post_crop_x[0];
> > + x_max = info->post_crop_x[0] + info->post_crop_w[0];
> > + y_min = info->post_crop_y[0];
> > + y_max = info->post_crop_y[0] + info->post_crop_h[0];
> > + if (info->post_enable_flag[1]) {
> > + /* POST1 is enabled */
> > + x_min = min(x_min, info->post_crop_x[1]);
> > + val = info->post_crop_x[1] + info->post_crop_w[1];
> > + x_max = max(x_max, val);
> > + y_min = min(y_min, info->post_crop_y[1]);
> > + val = info->post_crop_y[1] + info->post_crop_h[1];
> > + y_max = max(y_max, val);
> > + }
> > + x = x_min;
> > + y = y_min;
> > + w = x_max - x_min;
> > + h = y_max - y_min;
> > + } else if (info->post_enable_flag[1]) {
> > + /* POST0 is disabled and POST1 is enabled */
> > + x = info->post_crop_x[1];
> > + w = info->post_crop_w[1];
> > + y = info->post_crop_y[1];
> > + h = info->post_crop_h[1];
> > + } else {
> > + /* All POSTs are disabled */
> > + x = 0;
> > + y = 0;
> > + w = HWD_VIIF_CROP_MIN_W;
> > + h = HWD_VIIF_CROP_MIN_H;
> > + }
> > + writel(x, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_OFS_H);
> > + writel(y, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_OFS_V);
> > + writel(w, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_HSIZE);
> > + writel(h, &res->capture_reg->l2isp.roi[0].L2_ROI_OUT_VSIZE);
> > +
> > + for (i = 0; i < HWD_VIIF_MAX_POST_NUM; i++) {
> > + if (info->post_enable_flag[i])
> > + writel(0,
> &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
> > + else
> > + writel(HWD_VIIF_L2_ROI_NONE,
> &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
>
> This might be more readable as
>
> writel (info->post_enable_flag[i] ? 0 : HWD_VIIF_L2_ROI_NONE,
> ...);
>
> Up to you.
Thank you for an advice. I'll try.
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_roi_num_2() - Set ROI path condition when ROI num is 2
> > + */
> > +static void hwd_viif_l2_set_roi_num_2(struct hwd_viif_res *res)
> > +{
> > + struct hwd_viif_l2_roi_path_info *info = &res->l2_roi_path_info;
> > + u32 i;
> > +
> > + for (i = 0; i < HWD_VIIF_L2_ROI_MAX_NUM; i++) {
> > + /* ROI-n is the same as CROP area of POST-n */
> > + if (info->post_enable_flag[i]) {
> > + writel(info->post_crop_x[i],
> > +
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_H);
> > + writel(info->post_crop_y[i],
> > +
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_V);
> > + writel(info->post_crop_w[i],
> > +
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_HSIZE);
> > + writel(info->post_crop_h[i],
> > +
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_VSIZE);
> > + writel(i,
> &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
> > + } else {
> > + writel(0,
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_H);
> > + writel(0,
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_OFS_V);
> > + writel(HWD_VIIF_CROP_MIN_W,
> > +
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_HSIZE);
> > + writel(HWD_VIIF_CROP_MIN_H,
> > +
> &res->capture_reg->l2isp.roi[i].L2_ROI_OUT_VSIZE);
> > + writel(HWD_VIIF_L2_ROI_NONE,
> &res->capture_reg->l2isp.L2_ROI_TO_POST[i]);
> > + }
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_roi_path() - Set ROI path condition
> > + */
> > +static void hwd_viif_l2_set_roi_path(struct hwd_viif_res *res)
> > +{
> > + if (res->l2_roi_path_info.roi_num == 1U)
> > + hwd_viif_l2_set_roi_num_1(res);
> > + else
> > + hwd_viif_l2_set_roi_num_2(res);
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_roi() - Set ROI parameters of L2ISP
> > + *
> > + * @param: Pointer to ROI parameters of L2ISP
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "param" is NULL
> > + * - [2] Member of "param" is invalid
> > + *
> > + * see also: #hwd_viif_l2_set_roi_path
> > + */
> > +s32 hwd_viif_l2_set_roi(struct hwd_viif_res *res, const struct
> viif_l2_roi_config *param)
> > +{
> > + u32 val;
> > + int i;
> > +
> > + if (!param)
> > + return -EINVAL;
> > +
> > + if (param->roi_num < 1 || param->roi_num > 2)
> > + return -EINVAL;
> > +
> > + for (i = 0; i < 2; i++) {
> > + if (param->roi_scale[i] < HWD_VIIF_L2_ROI_MIN_SCALE ||
> > + param->roi_scale[i] > HWD_VIIF_L2_ROI_MAX_SCALE ||
> > + param->roi_scale_inv[i] <
> HWD_VIIF_L2_ROI_MIN_SCALE_INV ||
> > + param->roi_scale_inv[i] >
> HWD_VIIF_L2_ROI_MAX_SCALE_INV ||
> > + param->corrected_wo_scale_hsize[i] <
> > +
> HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE ||
> > + param->corrected_wo_scale_hsize[i] >
> > +
> HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE ||
> > + param->corrected_wo_scale_vsize[i] <
> > +
> HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE ||
> > + param->corrected_wo_scale_vsize[i] >
> > +
> HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE ||
> > + param->corrected_hsize[i] <
> HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE ||
> > + param->corrected_hsize[i] >
> HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE ||
> > + param->corrected_vsize[i] <
> HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE ||
> > + param->corrected_vsize[i] >
> HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + /* Set the number of ROI and update resource info with roi_num */
> > + writel(param->roi_num, &res->capture_reg->l2isp.L2_ROI_NUM);
> > + res->l2_roi_path_info.roi_num = param->roi_num;
> > +
> > + /* Update ROI area and input to each POST */
> > + hwd_viif_l2_set_roi_path(res);
> > +
> > + /* Set the remaining parameters */
> > + for (i = 0; i < 2; i++) {
> > + writel(param->roi_scale[i],
> &res->capture_reg->l2isp.roi[i].L2_ROI_SCALE);
> > + writel(param->roi_scale_inv[i],
> &res->capture_reg->l2isp.roi[i].L2_ROI_SCALE_INV);
> > + val = (param->corrected_wo_scale_hsize[i] << 13U) |
> param->corrected_hsize[i];
> > + writel(val,
> &res->capture_reg->l2isp.roi[i].L2_ROI_CORRECTED_HSIZE);
> > + val = (param->corrected_wo_scale_vsize[i] << 12U) |
> param->corrected_vsize[i];
> > + writel(val,
> &res->capture_reg->l2isp.roi[i].L2_ROI_CORRECTED_VSIZE);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_gamma() - Set Gamma correction parameters of L2ISP
> > + *
> > + * @post_id: POST ID [0..1]
> > + * @enable: or disable gamma correction of L2ISP. For more refer @ref
> hwd_viif_enable_flag.
> > + * @vsplit: changing line position from 1st table to 2nd table [0..4094]
> > + * @mode: Gamma correction mode. For more refer @ref
> hwd_viif_gamma_table_mode.
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "post_id", "enable", "vsplit" or "mode" is out of range
> > + * - [2] "vsplit" is not 0 when "enable" is HWD_VIIF_DISABLE
> > + * - [3] "mode" is not HWD_VIIF_GAMMA_COMPRESSED when enable is
> HWD_VIIF_DISABLE
> > + *
> > + * see also: #hwd_viif_l2_set_gamma
> > + */
> > +s32 hwd_viif_l2_set_gamma(struct hwd_viif_res *res, u32 post_id, u32
> enable, u32 vsplit, u32 mode)
> > +{
> > + u32 val;
> > +
> > + if (post_id >= HWD_VIIF_MAX_POST_NUM ||
> > + (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
> ||
> > + vsplit > HWD_VIIF_GAMMA_MAX_VSPLIT ||
> > + (mode != HWD_VIIF_GAMMA_COMPRESSED && mode !=
> HWD_VIIF_GAMMA_LINEAR) ||
> > + (enable == HWD_VIIF_DISABLE && vsplit != 0x0U) ||
> > + (enable == HWD_VIIF_DISABLE && mode !=
> HWD_VIIF_GAMMA_COMPRESSED)) {
> > + return -EINVAL;
> > + }
> > +
> > + /* Set gamma parameters of L2ISP */
> > + val = (vsplit << 16U) | (mode << 4U) | enable;
> > + writel(val,
> &res->capture_reg->l2isp.post[post_id].L2_POST_GAMMA_M);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_gamma_table_transmission() - Configure L2ISP
> transferring gamma table.
> > + *
> > + * @post_id: POST ID [0..1]
> > + * @gamma_table: Pointer to gamma table information
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "post_id" is out of range
> > + * - [2] Member of "gamma_table" is invalid
> > + */
> > +s32 hwd_viif_l2_set_gamma_table_transmission(struct hwd_viif_res *res,
> u32 post_id,
> > + const struct
> hwd_viif_l2_gamma_table *gamma_table)
> > +{
> > + u32 vdm_enable = 0U;
> > + u32 i, base_addr;
> > +
> > + if (post_id >= HWD_VIIF_MAX_POST_NUM)
> > + return -EINVAL;
> > +
> > + for (i = 0; i < 6U; i++) {
> > + if ((gamma_table->table[i] % HWD_VIIF_L2_VDM_ALIGN) !=
> 0U)
> > + return -EINVAL;
> > + }
> > +
> > + /* table[0]: LUT0-G/Y: t_port[12 + post_id * 6] */
> > + /* table[1]: LUT1-G/Y: t_port[13 + post_id * 6] */
> > + /* table[2]: LUT0-B/U: t_port[14 + post_id * 6] */
> > + /* table[3]: LUT1-B/U: t_port[15 + post_id * 6] */
> > + /* table[4]: LUT0-R/V: t_port[16 + post_id * 6] */
> > + /* table[5]: LUT1-R/V: t_port[17 + post_id * 6] */
> > + for (i = 0; i < 6U; i++) {
> > + if (gamma_table->table[i] != 0U) {
> > + int idx = 12U + i + post_id * 6U;
> > +
> > + writel((u32)gamma_table->table[i],
> > +
> &res->capture_reg->vdm.t_port[idx].VDM_T_STADR);
> > + writel(HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE,
> > +
> &res->capture_reg->vdm.t_port[idx].VDM_T_SIZE);
> > + vdm_enable |= BIT(i);
> > + }
> > + }
> > + if (vdm_enable != 0U) {
> > + /* t_group[2..3] is used only to transfer GAMMA table */
> > + /* [2]: POST0, [3]: POST1 */
> > + writel(HWD_VIIF_VDM_CFG_PARAM,
> > + &res->capture_reg->vdm.t_group[(post_id +
> 2U)].VDM_T_CFG);
> > + base_addr = HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE +
> > + (HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE *
> post_id);
> > + writel(base_addr, &res->capture_reg->vdm.t_group[(post_id +
> 2U)].VDM_T_SRAM_BASE);
> > + writel(HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE,
> > + &res->capture_reg->vdm.t_group[(post_id +
> 2U)].VDM_T_SRAM_SIZE);
> > + vdm_enable = vdm_enable << (12U + (post_id * 6U));
> > + }
> > + vdm_enable |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) &
> > + ~((u32)0x3fU << (12U + (post_id * 6U))));
> > + writel(vdm_enable, &res->capture_reg->vdm.VDM_T_ENABLE);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_output_csc() - Set output CSC parameters of L2ISP
> > + *
> > + * @post_id: POST ID [0..1]
> > + * @param: Pointer to output csc parameters of L2ISP
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "post_id" is out of range
> > + * - [2] Member of "param" is invalid
> > + */
> > +s32 hwd_viif_l2_set_output_csc(struct hwd_viif_res *res, u32 post_id,
> > + const struct hwd_viif_csc_param *param)
> > +{
> > + struct hwd_viif_l2isp_post_reg *reg_l2isp_post;
> > + u32 i, val;
> > +
> > + if (post_id >= HWD_VIIF_MAX_POST_NUM)
> > + return -EINVAL;
> > +
> > + /* disable csc matrix when param is NULL */
> > + if (!param) {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l2isp.post[post_id].csc.MTB);
> > + return 0;
> > + }
> > +
> > + /* param is specified: go further check */
> > + if (param->r_cr_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->g_y_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->b_cb_in_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->r_cr_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->g_y_out_offset > HWD_VIIF_CSC_MAX_OFFSET ||
> > + param->b_cb_out_offset > HWD_VIIF_CSC_MAX_OFFSET) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < HWD_VIIF_CSC_MAX_COEF_NUM; i++) {
> > + if (param->coef[i] > HWD_VIIF_CSC_MAX_COEF_VALUE)
> > + return -EINVAL;
> > + }
> > +
> > + reg_l2isp_post = &res->capture_reg->l2isp.post[post_id];
> > +
> > + writel(param->g_y_in_offset,
> ®_l2isp_post->csc.MTB_YG_OFFSETI);
> > + writel(param->coef[0], ®_l2isp_post->csc.MTB_YG1);
> > + val = (param->coef[1] << HWD_VIIF_MTB_CB_YG_COEF_OFFSET) |
> > + (param->coef[2] << HWD_VIIF_MTB_CR_YG_COEF_OFFSET);
> > + writel(val, ®_l2isp_post->csc.MTB_YG2);
> > + writel(param->g_y_out_offset,
> ®_l2isp_post->csc.MTB_YG_OFFSETO);
> > + writel(param->b_cb_in_offset,
> ®_l2isp_post->csc.MTB_CB_OFFSETI);
> > + writel(param->coef[3], ®_l2isp_post->csc.MTB_CB1);
> > + val = (param->coef[4] << HWD_VIIF_MTB_CB_CB_COEF_OFFSET) |
> > + (param->coef[5] << HWD_VIIF_MTB_CR_CB_COEF_OFFSET);
> > + writel(val, ®_l2isp_post->csc.MTB_CB2);
> > + writel(param->b_cb_out_offset,
> ®_l2isp_post->csc.MTB_CB_OFFSETO);
> > + writel(param->r_cr_in_offset,
> ®_l2isp_post->csc.MTB_CR_OFFSETI);
> > + writel(param->coef[6], ®_l2isp_post->csc.MTB_CR1);
> > + val = (param->coef[7] << HWD_VIIF_MTB_CB_CR_COEF_OFFSET) |
> > + (param->coef[8] << HWD_VIIF_MTB_CR_CR_COEF_OFFSET);
> > + writel(val, ®_l2isp_post->csc.MTB_CR2);
> > + writel(param->r_cr_out_offset,
> ®_l2isp_post->csc.MTB_CR_OFFSETO);
> > + writel(HWD_VIIF_ENABLE, ®_l2isp_post->csc.MTB);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_img_transmission() - Set image transfer condition of
> L2ISP
> > + *
> > + * @post_id: POST ID [0..1]
> > + * @enable: or disable image transfer of MAIN unit. For more refer @ref
> hwd_viif_enable_flag.
> > + * @src: Pointer to crop area information
> > + * @out_process: Pointer to output process information
> > + * @img: Pointer to output image information
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "post_id" or "enable" is out of range
> > + * - [2] "src" or "out_process" is NULL when "enable" is HWD_VIIF_ENABLE
> > + * - [3] "src" or "out_process" is not NULL when "enable" is
> HWD_VIIF_DISABLE
> > + * - [4] Member of "src" is out of range
> > + * - [5] "w" of "src" is not equal to 2 * "width" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> > + * - [6] "h" of "src" is not equal to 2 * "height" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> > + * - [7] "w" of "src" is not equal to "width" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> > + * - [8] "h" of "src" is not equal to "height" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> > + * - [9] Member of "out_process" is invalid
> > + * - [10] "alpha" of "out_process" is not 0 when "format" of "img" is not
> HWD_VIIF_ARGB8888_PACKED
> > + * - [11] "format" of "img" is not HWD_VIIF_ONE_COLOR_8 or
> HWD_VIIF_ONE_COLOR_16
> > + * when "select_color" of "out_process"
> > + * is HWD_VIIF_COLOR_Y_G, HWD_VIIF_COLOR_U_B or
> HWD_VIIF_COLOR_V_R
> > + * - [12] Member of "img" is invalid
> > + *
> > + * see also: #hwd_viif_l2_set_roi_path
> > + */
> > +s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id,
> u32 enable,
> > + const struct hwd_viif_img_area *src,
> > + const struct hwd_viif_out_process
> *out_process,
> > + const struct hwd_viif_img *img)
> > +{
> > + u32 pitch[HWD_VIIF_MAX_PLANE_NUM],
> img_start_addr[HWD_VIIF_MAX_PLANE_NUM];
> > + u32 i, val, loop, k, r[HWD_VIIF_MAX_PLANE_NUM];
> > + s32 ret = 0;
> > +
> > + /* pitch alignment for planar or one color format */
> > + u32 pitch_align = 128U;
> > +
> > + if (post_id >= HWD_VIIF_MAX_POST_NUM ||
> > + (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
> ||
> > + (enable == HWD_VIIF_ENABLE && (!src || !out_process)) ||
> > + (enable == HWD_VIIF_DISABLE && (src || out_process))) {
> > + return -EINVAL;
> > + }
> > +
> > + /* DISABLE: no DMA transmission setup, set minimum crop rectangle
> */
> > + if (enable == HWD_VIIF_DISABLE) {
> > + res->l2_roi_path_info.post_enable_flag[post_id] = false;
> > + res->l2_roi_path_info.post_crop_x[post_id] = 0U;
> > + res->l2_roi_path_info.post_crop_y[post_id] = 0U;
> > + res->l2_roi_path_info.post_crop_w[post_id] =
> HWD_VIIF_CROP_MIN_W;
> > + res->l2_roi_path_info.post_crop_h[post_id] =
> HWD_VIIF_CROP_MIN_H;
> > + hwd_viif_l2_set_roi_path(res);
> > +
> > + return 0;
> > + }
> > +
> > + /* further parameter check for ENABLE */
> > + if (out_process->half_scale != HWD_VIIF_ENABLE &&
> > + out_process->half_scale != HWD_VIIF_DISABLE) {
> > + return -EINVAL;
> > + }
> > +
> > + if (out_process->select_color != HWD_VIIF_COLOR_Y_G &&
> > + out_process->select_color != HWD_VIIF_COLOR_U_B &&
> > + out_process->select_color != HWD_VIIF_COLOR_V_R &&
> > + out_process->select_color != HWD_VIIF_COLOR_YUV_RGB) {
> > + return -EINVAL;
> > + }
> > +
> > + if (img->format != HWD_VIIF_ARGB8888_PACKED &&
> out_process->alpha != 0U)
> > + return -EINVAL;
> > +
> > + if (((img->width % 2U) != 0U) || ((img->height % 2U) != 0U) ||
> > + img->width < HWD_VIIF_MIN_OUTPUT_IMG_WIDTH ||
> > + img->height < HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT ||
> > + img->width > HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP ||
> > + img->height > HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP) {
> > + return -EINVAL;
> > + }
> > +
> > + if (src->x > HWD_VIIF_CROP_MAX_X_ISP || src->y >
> HWD_VIIF_CROP_MAX_Y_ISP ||
> > + src->w < HWD_VIIF_CROP_MIN_W || src->w >
> HWD_VIIF_CROP_MAX_W_ISP ||
> > + src->h < HWD_VIIF_CROP_MIN_H || src->h >
> HWD_VIIF_CROP_MAX_H_ISP) {
> > + return -EINVAL;
> > + }
> > +
> > + if (out_process->half_scale == HWD_VIIF_ENABLE) {
> > + if ((src->w != (img->width * 2U)) || (src->h != (img->height *
> 2U)))
> > + return -EINVAL;
> > + } else {
> > + if (src->w != img->width || src->h != img->height)
> > + return -EINVAL;
> > + }
> > +
> > + if (out_process->select_color == HWD_VIIF_COLOR_Y_G ||
> > + out_process->select_color == HWD_VIIF_COLOR_U_B ||
> > + out_process->select_color == HWD_VIIF_COLOR_V_R) {
> > + if (img->format != HWD_VIIF_ONE_COLOR_8 &&
> img->format != HWD_VIIF_ONE_COLOR_16)
> > + return -EINVAL;
> > + }
> > +
> > + /* build DMAC parameter */
> > + switch (img->format) {
> > + case HWD_VIIF_YCBCR422_8_PACKED:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 2U;
> > + r[0] = 1U;
> > + pitch_align = 256U;
> > + break;
> > + case HWD_VIIF_RGB888_PACKED:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 3U;
> > + r[0] = 1U;
> > + pitch_align = 384U;
> > + break;
> > + case HWD_VIIF_ARGB8888_PACKED:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 4U;
> > + r[0] = 1U;
> > + pitch_align = 512U;
> > + break;
> > + case HWD_VIIF_ONE_COLOR_8:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 1U;
> > + r[0] = 1U;
> > + break;
> > + case HWD_VIIF_ONE_COLOR_16:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 2U;
> > + r[0] = 1U;
> > + break;
> > + case HWD_VIIF_YCBCR422_8_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 1U;
> > + r[0] = 1U;
> > + r[1] = 2U;
> > + r[2] = 2U;
> > + break;
> > + case HWD_VIIF_RGB888_YCBCR444_8_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 1U;
> > + r[0] = 1U;
> > + r[1] = 1U;
> > + r[2] = 1U;
> > + break;
> > + case HWD_VIIF_YCBCR422_16_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 2U;
> > + r[0] = 1U;
> > + r[1] = 2U;
> > + r[2] = 2U;
> > + break;
> > + case HWD_VIIF_RGB161616_YCBCR444_16_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 2U;
> > + r[0] = 1U;
> > + r[1] = 1U;
> > + r[2] = 1U;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < loop; i++) {
> > + val = max(((img->width * k) / r[i]), 128U);
> > + if (pitch[i] < val || pitch[i] > HWD_VIIF_MAX_PITCH_ISP ||
> > + ((pitch[i] % pitch_align) != 0U) || ((img_start_addr[i] %
> 4U) != 0U)) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + writel(img_start_addr[0],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_G);
> > + writel(pitch[0],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_G);
> > + if (loop == HWD_VIIF_MAX_PLANE_NUM) {
> > + writel(img_start_addr[1],
> > +
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_B);
> > + writel(img_start_addr[2],
> > +
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_R);
> > + writel(pitch[1],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_B);
> > + writel(pitch[2],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_R);
> > + }
> > +
> > + /* Set CROP */
> > + val = (src->y << 16U) | src->x;
> > + writel(val,
> &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_OFFSET);
> > + val = (src->h << 16U) | src->w;
> > + writel(val,
> &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_SIZE);
> > +
> > + /* Set output process */
> > + writel(out_process->half_scale,
> > +
> &res->capture_reg->l2isp.post[post_id].L2_POST_HALF_SCALE_EN);
> > + writel(out_process->select_color,
> &res->capture_reg->l2isp.post[post_id].L2_POST_C_SELECT);
> > + writel((u32)out_process->alpha,
> &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTALP);
> > + writel(img->format,
> &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTFMT);
> > +
> > + /* Update ROI area and input to each POST */
> > + res->l2_roi_path_info.post_enable_flag[post_id] = true;
> > + res->l2_roi_path_info.post_crop_x[post_id] = src->x;
> > + res->l2_roi_path_info.post_crop_y[post_id] = src->y;
> > + res->l2_roi_path_info.post_crop_w[post_id] = src->w;
> > + res->l2_roi_path_info.post_crop_h[post_id] = src->h;
> > + hwd_viif_l2_set_roi_path(res);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * hwd_viif_l2_set_irq_mask() - Set mask condition for L2ISP
> > + *
> > + * @mask: L2ISP mask condition
> > + * Return: None
> > + */
> > +void hwd_viif_l2_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> > +{
> > + writel(mask, &res->capture_reg->l2isp.L2_CRGBF_ISP_INT_MASK);
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_err_irq_handler() - CSI-2 RX error interruption handler
> > + *
> > + * Return: event information of CSI-2 RX error interruption
> > + */
> > +u32 hwd_viif_csi2rx_err_irq_handler(struct hwd_viif_res *res)
> > +{
> > + return readl(&res->csi2host_reg->CSI2RX_INT_ST_MAIN);
> > +}
> > +
> > +/**
> > + * hwd_viif_status_err_irq_handler() - STATUS error interruption handler
> > + *
> > + * @event_main: information of STATUS error interruption of MAIN unit
> > + * @event_sub: information of STATUS error interruption of SUB unit(CH0
> and CH1)
> > + * Return: None
> > + */
> > +void hwd_viif_status_err_irq_handler(struct hwd_viif_res *res, u32
> *event_main, u32 *event_sub)
> > +{
> > + u32 val, mask;
> > +
> > + *event_main = HWD_VIIF_NO_EVENT;
> > + *event_sub = HWD_VIIF_NO_EVENT;
> > +
> > + val = readl(&res->capture_reg->sys.INT_M_STATUS);
> > + mask = readl(&res->capture_reg->sys.INT_M_MASK);
> > + val = val & ~mask;
> > + if (val != HWD_VIIF_NO_EVENT) {
> > + writel(val, &res->capture_reg->sys.INT_M_STATUS);
> > + *event_main = val;
> > + }
> > +
> > + val = readl(&res->capture_reg->sys.INT_S_STATUS);
> > + mask = readl(&res->capture_reg->sys.INT_S_MASK);
> > + val = val & ~mask;
> > + if (val != HWD_VIIF_NO_EVENT) {
> > + writel(val, &res->capture_reg->sys.INT_S_STATUS);
> > + *event_sub = val;
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_vsync_irq_handler() - Vsync interruption handler
> > + *
> > + * @event_main: information of Vsync interruption of MAIN unit
> > + * @event_sub: information of Vsync interruption of SUB unit(CH0 and CH1)
> > + * Return: None
> > + */
> > +void hwd_viif_vsync_irq_handler(struct hwd_viif_res *res, u32 *event_main,
> u32 *event_sub)
> > +{
> > + u32 val, mask;
> > +
> > + *event_main = HWD_VIIF_NO_EVENT;
> > + *event_sub = HWD_VIIF_NO_EVENT;
> > +
> > + val = readl(&res->capture_reg->sys.INT_M_SYNC);
> > + mask = readl(&res->capture_reg->sys.INT_M_SYNC_MASK);
> > + val = val & ~mask;
> > + if (val != HWD_VIIF_NO_EVENT) {
> > + writel(val, &res->capture_reg->sys.INT_M_SYNC);
> > + *event_main = val;
> > + }
> > +
> > + val = readl(&res->capture_reg->sys.INT_S_SYNC);
> > + mask = readl(&res->capture_reg->sys.INT_S_SYNC_MASK);
> > + val = val & ~mask;
> > + if (val != HWD_VIIF_NO_EVENT) {
> > + writel(val, &res->capture_reg->sys.INT_S_SYNC);
> > + *event_sub = val;
> > + }
> > +}
> > +
> > +/**
> > + * hwd_viif_isp_regbuf_irq_handler() - ISP register buffer interruption
> handler
> > + *
> > + * @event_l1: information of register buffer interruption of L1ISP
> > + * @event_l2: information of register buffer interruption of L2ISP
> > + * Return: None
> > + */
> > +void hwd_viif_isp_regbuf_irq_handler(struct hwd_viif_res *res, u32 *event_l1,
> u32 *event_l2)
> > +{
> > + u32 val;
> > +
> > + *event_l1 = HWD_VIIF_NO_EVENT;
> > + *event_l2 = HWD_VIIF_NO_EVENT;
> > +
> > + val =
> readl(&res->capture_reg->l1isp.L1_CRGBF_INT_MASKED_STAT);
> > + if (val != HWD_VIIF_NO_EVENT) {
> > + *event_l1 = val;
> > + writel(val, &res->capture_reg->l1isp.L1_CRGBF_INT_STAT);
> > + }
> > +
> > + val =
> readl(&res->capture_reg->l2isp.L2_CRGBF_INT_MASKED_STAT);
> > + if (val != HWD_VIIF_NO_EVENT) {
> > + *event_l2 = val;
> > + writel(val, &res->capture_reg->l2isp.L2_CRGBF_INT_STAT);
> > + }
> > +}
> > diff --git a/drivers/media/platform/visconti/hwd_viif.h
> b/drivers/media/platform/visconti/hwd_viif.h
> > new file mode 100644
> > index 00000000000..100afda8436
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif.h
> > @@ -0,0 +1,710 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_H
> > +#define HWD_VIIF_H
> > +
> > +#include <linux/errno.h>
> > +#include <linux/types.h>
> > +
> > +#include <linux/visconti_viif.h>
> > +
> > +enum hwd_power_ctrl {
> > + HWD_POWER_OFF = 0, /**< Power off */
> > + HWD_POWER_ON /**< Power on */
> > +};
> > +
> > +/* MIPI CSI2 Data Types */
> > +#define VISCONTI_CSI2_DT_YUV4228B 0x1E
> > +#define VISCONTI_CSI2_DT_YUV42210B 0x1F
> > +#define VISCONTI_CSI2_DT_RGB565 0x22
> > +#define VISCONTI_CSI2_DT_RGB888 0x24
> > +#define VISCONTI_CSI2_DT_RAW8 0x2A
> > +#define VISCONTI_CSI2_DT_RAW10 0x2B
> > +#define VISCONTI_CSI2_DT_RAW12 0x2C
> > +#define VISCONTI_CSI2_DT_RAW14 0x2D
>
> Please use the definitions in media/mipi-csi2.h .
I'll use definitions in mipi-csi2.h .
> > +
> > +/* hwd_viif_enable_flag */
> > +#define HWD_VIIF_DISABLE (0U)
> > +#define HWD_VIIF_ENABLE (1U)
> > +
> > +/* hwd_viif_memory_sync_type */
> > +#define HWD_VIIF_MEM_SYNC_INTERNAL (0U)
> > +#define HWD_VIIF_MEM_SYNC_CSI2 (1U)
> > +
> > +/* hwd_viif_color_format */
> > +#define HWD_VIIF_YCBCR422_8_PACKED (0U)
> > +#define HWD_VIIF_RGB888_PACKED (1U)
> > +#define HWD_VIIF_ARGB8888_PACKED (3U)
> > +#define HWD_VIIF_YCBCR422_8_PLANAR (8U)
> > +#define HWD_VIIF_RGB888_YCBCR444_8_PLANAR (9U)
> > +#define HWD_VIIF_ONE_COLOR_8 (11U)
> > +#define HWD_VIIF_YCBCR422_16_PLANAR (12U)
> > +#define HWD_VIIF_RGB161616_YCBCR444_16_PLANAR (13U)
> > +#define HWD_VIIF_ONE_COLOR_16 (15U)
> > +
> > +/* hwd_viif_raw_pack_mode */
> > +#define HWD_VIIF_RAWPACK_DISABLE (0U)
> > +#define HWD_VIIF_RAWPACK_MSBFIRST (2U)
> > +#define HWD_VIIF_RAWPACK_LSBFIRST (3U)
> > +
> > +/* hwd_viif_yuv_conversion_mode */
> > +#define HWD_VIIF_YUV_CONV_REPEAT (0U)
> > +#define HWD_VIIF_YUV_CONV_INTERPOLATION (1U)
> > +
> > +/* hwd_viif_gamma_table_mode */
> > +#define HWD_VIIF_GAMMA_COMPRESSED (0U)
> > +#define HWD_VIIF_GAMMA_LINEAR (1U)
> > +
> > +/* hwd_viif_output_color_mode */
> > +#define HWD_VIIF_COLOR_Y_G (0U)
> > +#define HWD_VIIF_COLOR_U_B (1U)
> > +#define HWD_VIIF_COLOR_V_R (2U)
> > +#define HWD_VIIF_COLOR_YUV_RGB (4U)
> > +
> > +/* hwd_viif_hw_params */
> > +#define HWD_VIIF_MAX_CH (6U)
> > +#define HWD_VIIF_MAX_PLANE_NUM (3U)
> > +
> > +/**
> > + * enum hwd_viif_csi2_dphy - D-PHY Lane assignment
> > + *
> > + * specifies which line(L0-L3) is assigned to D0-D3
> > + */
> > +enum hwd_viif_csi2_dphy {
> > + HWD_VIIF_CSI2_DPHY_L0L1L2L3 = 0U,
> > + HWD_VIIF_CSI2_DPHY_L0L3L1L2 = 1U,
> > + HWD_VIIF_CSI2_DPHY_L0L2L3L1 = 2U,
> > + HWD_VIIF_CSI2_DPHY_L0L1L3L2 = 4U,
> > + HWD_VIIF_CSI2_DPHY_L0L3L2L1 = 5U,
> > + HWD_VIIF_CSI2_DPHY_L0L2L1L3 = 6U
> > +};
> > +
> > +/* hwd_viif_csi2rx_cal_status */
> > +#define HWD_VIIF_CSI2_CAL_NOT_DONE (0U)
> > +#define HWD_VIIF_CSI2_CAL_SUCCESS (1U)
> > +#define HWD_VIIF_CSI2_CAL_FAIL (2U)
> > +
> > +/* hwd_viif_csi2rx_not_capture */
> > +#define HWD_VIIF_CSI2_NOT_CAPTURE (-1) /**< csi2 not capture */
> > +
> > +/* hwd_viif_l1_input_mode */
> > +#define HWD_VIIF_L1_INPUT_HDR (0U)
> > +#define HWD_VIIF_L1_INPUT_PWL (1U)
> > +#define HWD_VIIF_L1_INPUT_SDR (2U)
> > +#define HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT (3U)
> > +#define HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT (4U)
> > +
> > +/* hwd_viif_l1_raw_color_filter_mode */
> > +#define HWD_VIIF_L1_RAW_GR_R_B_GB (0U)
> > +#define HWD_VIIF_L1_RAW_R_GR_GB_B (1U)
> > +#define HWD_VIIF_L1_RAW_B_GB_GR_R (2U)
> > +#define HWD_VIIF_L1_RAW_GB_B_R_GR (3U)
> > +
> > +/* hwd_viif_l1_input_interpolation_mode */
> > +#define HWD_VIIF_L1_INPUT_INTERPOLATION_LINE (0U)
> > +#define HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL (1U)
> > +
> > +/* hwd_viif_l1_img_sens */
> > +#define HWD_VIIF_L1_IMG_SENSITIVITY_HIGH (0U)
> > +#define HWD_VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED (1U)
> > +#define HWD_VIIF_L1_IMG_SENSITIVITY_LOW (2U)
> > +
> > +/* hwd_viif_l1_dpc */
> > +#define HWD_VIIF_L1_DPC_1PIXEL (0U)
> > +#define HWD_VIIF_L1_DPC_2PIXEL (1U)
> > +
> > +/* hwd_viif_l1_rcnr_hry_type */
> > +#define HWD_VIIF_L1_RCNR_LOW_RESOLUTION (0U)
> > +#define HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION (1U)
> > +#define HWD_VIIF_L1_RCNR_HIGH_RESOLUTION (2U)
> > +#define HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION (3U)
> > +
> > +/* hwd_viif_l1_rcnr_msf_blend_ratio */
> > +#define HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 (0U)
> > +#define HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 (1U)
> > +#define HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 (2U)
> > +
> > +/* hwd_viif_l1_hdrs */
> > +#define HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE (0U)
> > +#define HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE (1U)
> > +
> > +/* hwd_viif_l1_lsc_para_mag */
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH (0U)
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH (1U)
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND (2U)
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST (3U)
> > +
> > +/* hwd_viif_l1_lsc_grid_mag */
> > +#define HWD_VIIF_L1_GRID_COEF_GAIN_X1 (0U)
> > +#define HWD_VIIF_L1_GRID_COEF_GAIN_X2 (1U)
> > +
> > +/* hwd_viif_l1_demosaic */
> > +#define HWD_VIIF_L1_DEMOSAIC_ACPI (0U)
> > +#define HWD_VIIF_L1_DEMOSAIC_DMG (1U)
> > +
> > +/* hwd_viif_l1_awb_restart_cond */
> > +/* macros for L1ISP condition to restart auto white balance */
> > +#define HWD_VIIF_L1_AWB_RESTART_NO (0U)
> > +#define HWD_VIIF_L1_AWB_RESTART_128FRAME (1U)
> > +#define HWD_VIIF_L1_AWB_RESTART_64FRAME (2U)
> > +#define HWD_VIIF_L1_AWB_RESTART_32FRAME (3U)
> > +#define HWD_VIIF_L1_AWB_RESTART_16FRAME (4U)
> > +#define HWD_VIIF_L1_AWB_RESTART_8FRAME (5U)
> > +#define HWD_VIIF_L1_AWB_RESTART_4FRAME (6U)
> > +#define HWD_VIIF_L1_AWB_RESTART_2FRAME (7U)
> > +
> > +/* hwd_viif_l1_awb_mag */
> > +#define HWD_VIIF_L1_AWB_ONE_SECOND (0U)
> > +#define HWD_VIIF_L1_AWB_X1 (1U)
> > +#define HWD_VIIF_L1_AWB_X2 (2U)
> > +#define HWD_VIIF_L1_AWB_X4 (3U)
> > +
> > +/* hwd_viif_l1_awb_area_mode */
> > +#define HWD_VIIF_L1_AWB_AREA_MODE0 (0U)
> > +#define HWD_VIIF_L1_AWB_AREA_MODE1 (1U)
> > +#define HWD_VIIF_L1_AWB_AREA_MODE2 (2U)
> > +#define HWD_VIIF_L1_AWB_AREA_MODE3 (3U)
> > +
> > +/* hwd_viif_l1_hdrc_tone_type */
> > +#define HWD_VIIF_L1_HDRC_TONE_USER (0U)
> > +#define HWD_VIIF_L1_HDRC_TONE_PRESET (1U)
> > +
> > +/* hwd_viif_l1_bin_mode */
> > +#define HWD_VIIF_L1_HIST_BIN_MODE_LINEAR (0U)
> > +#define HWD_VIIF_L1_HIST_BIN_MODE_LOG (1U)
> > +
> > +/* hwd_viif_l2_undist_mode */
> > +#define HWD_VIIF_L2_UNDIST_POLY (0U)
> > +#define HWD_VIIF_L2_UNDIST_GRID (1U)
> > +#define HWD_VIIF_L2_UNDIST_POLY_TO_GRID (2U)
> > +#define HWD_VIIF_L2_UNDIST_GRID_TO_POLY (3U)
> > +
> > +/**
> > + * struct hwd_viif_csi2rx_line_err_target
> > + *
> > + * Virtual Channel and Data Type pair for CSI2RX line error monitor
> > + *
> > + * When 0 is set to dt, line error detection is disabled.
> > + *
> > + * * VC can be 0 .. 3
> > + * * DT can be 0 or 0x10 .. 0x3F
> > + */
> > +#define VISCONTI_CSI2_ERROR_MONITORS_NUM 8
> > +struct hwd_viif_csi2rx_line_err_target {
> > + u32 vc[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> > + u32 dt[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_csi2rx_irq_mask
> > + * @mask: mask setting for CSI2RX error interruption
> > + *
> > + * * mask[0]: D-PHY fatal error
> > + * * mask[1]: Packet fatal error
> > + * * mask[2]: Frame fatal error
> > + * * mask[3]: D-PHY error
> > + * * mask[4]: Packet error
> > + * * mask[5]: Line error
> > + */
> > +#define VISCONTI_CSI2RX_IRQ_MASKS_NUM 6
> > +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_FATAL 0
> > +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_FATAL 1
> > +#define VISCONTI_CSI2RX_IRQ_MASK_FRAME_FATAL 2
> > +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_ERROR 3
> > +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_ERROR 4
> > +#define VISCONTI_CSI2RX_IRQ_MASK_LINE_ERROR 5
> > +struct hwd_viif_csi2rx_irq_mask {
> > + u32 mask[VISCONTI_CSI2RX_IRQ_MASKS_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_csi2rx_packet - CSI2 packet information
> > + * @word_count: word count included in one packet[byte] [0..16384]
> > + * @packet_num: the number of packet included in one packet [0..8192]
> > + *
> > + * each element means as below.
> > + * * [0]: embedded data of MAIN unit
> > + * * [1]: long packet data of MAIN unit
> > + * * [2]: embedded data of SUB unit
> > + * * [3]: long packet data of SUB unit
> > + *
> > + * Regarding word_count of long packet data,
> > + * word count of odd line needs to be set in case of DT = 0x18, 0x19, 0x1C or
> 0x1D.
> > + */
> > +#define VISCONTI_CSI2RX_PACKET_TYPES_NUM 4
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN 0
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN 1
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB 2
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB 3
> > +struct hwd_viif_csi2rx_packet {
> > + u32 word_count[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> > + u32 packet_num[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_pixelmap - pixelmap information
> > + * @pmap_paddr: start address of pixel data(physical address). 4byte
> alignment.
> > + * @pitch: pitch size of pixel map[byte]
> > + *
> > + * Condition of pitch in case of L2ISP output is as below.
> > + * * max: 32704[byte]
> > + * * min: the larger value of (active width of image * k / r) and 128[byte]
> > + * * alignment: 64[byte]
> > + *
> > + * Condition of pitch in the other cases is as below.
> > + * * max: 65536[byte]
> > + * * min: active width of image * k / r[byte]
> > + * * alignment: 4[byte]
> > + *
> > + * k is the size of 1 pixel and the value is as below.
> > + * * HWD_VIIF_YCBCR422_8_PACKED: 2
> > + * * HWD_VIIF_RGB888_PACKED: 3
> > + * * HWD_VIIF_ARGB8888_PACKED: 4
> > + * * HWD_VIIF_YCBCR422_8_PLANAR: 1
> > + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR: 1
> > + * * HWD_VIIF_ONE_COLOR_8: 1
> > + * * HWD_VIIF_YCBCR422_16_PLANAR: 2
> > + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR: 2
> > + * * HWD_VIIF_ONE_COLOR_16: 2
> > + *
> > + * r is the correction factor for Cb or Cr of YCbCr422 planar and the value is
> as below.
> > + * * YCbCr422 Cb-planar: 2
> > + * * YCbCr422 Cr-planar: 2
> > + * * others: 1
> > + *
> > + */
> > +struct hwd_viif_pixelmap {
> > + uintptr_t pmap_paddr;
> > + u32 pitch;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_img - image information
> > + * @width: active width of image[pixel]
> > + * * [128..5760](output from L2ISP)
> > + * * [128..4096](input to MAIN unit(memory input))
> > + * * [128..4096](output from SUB unit)
> > + * * The value should be even.
> > + *
> > + * @height: active height of image[line]
> > + * * [128..3240](output from L2ISP)
> > + * * [128..2160](input to MAIN unit(memory input))
> > + * * [128..2160](output from SUB unit)
> > + * * The value should be even.
> > + *
> > + * @format: hwd_viif_color_format "color format"
> > + * * Below color formats are supported for input and output of MAIN unit
> > + * * HWD_VIIF_YCBCR422_8_PACKED
> > + * * HWD_VIIF_RGB888_PACKED
> > + * * HWD_VIIF_ARGB8888_PACKED
> > + * * HWD_VIIF_YCBCR422_8_PLANAR
> > + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR
> > + * * HWD_VIIF_ONE_COLOR_8
> > + * * HWD_VIIF_YCBCR422_16_PLANAR
> > + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR
> > + * * HWD_VIIF_ONE_COLOR_16
> > + * * Below color formats are supported for output of SUB unit
> > + * * HWD_VIIF_ONE_COLOR_8
> > + * * HWD_VIIF_ONE_COLOR_16
> > + *
> > + * @pixelmap: pixelmap information
> > + * * [0]: Y/G-planar, packed/Y/RAW
> > + * * [1]: Cb/B-planar
> > + * * [2]: Cr/R-planar
> > + */
> > +struct hwd_viif_img {
> > + u32 width;
> > + u32 height;
> > + u32 format;
> > + struct hwd_viif_pixelmap pixelmap[3];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_input_img - input image information
> > + * @pixel_clock: pixel clock [3375..600000] [kHz]. 0 needs to be set for long
> packet data.
> > + * @htotal_size: horizontal total size
> > + * * [143..65535] [pixel] for image data
> > + * * [239..109225] [ns] for long packet data
> > + * @hactive_size: horizontal active size [pixel]
> > + * * [128..4096] without L1ISP
> > + * * [640..3840] with L1ISP
> > + * * The value should be even. In addition, the value should be a multiple of 8
> with L1ISP
> > + * * 0 needs to be set for the configuration of long packet data or SUB unit
> output.
> > + * @vtotal_size: vertical total size [line]
> > + * * [144..16383] for image data
> > + * * 0 needs to be set for the configuration of long packet data.
> > + * @vbp_size: vertical back porch size
> > + * * [5..4095] [line] for image data
> > + * * [5..4095] [the number of packet] for long packet data
> > + * @vactive_size: vertical active size [line]
> > + * * [128..2160] without L1ISP
> > + * * [480..2160] with L1ISP
> > + * * The value should be even.
> > + * * 0 needs to be set for the configuration of long packet data.
> > + * @interpolation_mode: input image interpolation mode for
> hwd_viif_l1_input_interpolation_mode
> > + * * HWD_VIIF_L1_INPUT_INTERPOLATION_LINE needs to be set in the
> below cases.
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + * @input_num: the number of input images [1..3]
> > + * * 1 needs to be set in the below cases.
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + * @hobc_width: the number of horizontal optical black pixels [0,16,32,64 or
> 128]
> > + * * 0 needs to be set in the below cases.
> > + * * in case of hobc_margin = 0
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + * @hobc_margin: the number of horizontal optical black margin[0..30] (even
> number)
> > + * * 0 needs to be set in the below cases.
> > + * * in case of hobc_width = 0
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + *
> > + * Below conditions need to be satisfied.
> > + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_LINE:
> > + * (htotal_size > (hactive_size + hobc_width + hobc_margin)) &&
> > + * (vtotal_size > (vbp_size + vactive_size * input_num))
> > + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL:
> > + * (htotal_size > ((hactive_size + hobc_width + hobc_margin) *
> input_num)) &&
> > + * (vtotal_size > (vbp_size + vactive_size))
> > + * * L1ISP is used:
> > + * vbp_size >= (54720[cycle] / 500000[kHz]) * (pixel_clock / htotal_size)
> + 38 + ISST time
> > + * * L1ISP is not used:
> > + * vbp_size >= (39360[cycle] / 500000[kHz]) * (pixel_clock / htotal_size)
> + 16 + ISST time
> > + *
> > + * Note: L1ISP is used when RAW data is input to MAIN unit
> > + */
> > +struct hwd_viif_input_img {
> > + u32 pixel_clock;
> > + u32 htotal_size;
> > + u32 hactive_size;
> > + u32 vtotal_size;
> > + u32 vbp_size;
> > + u32 vactive_size;
> > + u32 interpolation_mode;
> > + u32 input_num;
> > + u32 hobc_width;
> > + u32 hobc_margin;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_csc_param - color conversion information
> > + * @r_cr_in_offset: input offset of R/Cr[pix value] [0x0..0x1FFFF]
> > + * @g_y_in_offset: input offset of G/Y[pix value] [0x0..0x1FFFF]
> > + * @b_cb_in_offset: input offset of B/Cb[pix value] [0x0..0x1FFFF]
> > + * @coef: coefficient of matrix [0x0..0xFFFF]
> > + * * [0] : c00(YG_YG), [1] : c01(UB_YG), [2] : c02(VR_YG),
> > + * * [3] : c10(YG_UB), [4] : c11(UB_UB), [5] : c12(VR_UB),
> > + * * [6] : c20(YG_VR), [7] : c21(UB_VR), [8] : c22(VR_VR)
> > + * @r_cr_out_offset: output offset of R/Cr[pix value] [0x0..0x1FFFF]
> > + * @g_y_out_offset: output offset of G/Y[pix value] [0x0..0x1FFFF]
> > + * @b_cb_out_offset: output offset of B/Cb[pix value] [0x0..0x1FFFF]
> > + */
> > +struct hwd_viif_csc_param {
> > + u32 r_cr_in_offset;
> > + u32 g_y_in_offset;
> > + u32 b_cb_in_offset;
> > + u32 coef[9];
> > + u32 r_cr_out_offset;
> > + u32 g_y_out_offset;
> > + u32 b_cb_out_offset;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_img_area - image area definition
> > + * @x: x position [0..8062] [pixel]
> > + * @y: y position [0..3966] [line]
> > + * @w: image width [128..8190] [pixel]
> > + * @h: image height [128..4094] [line]
> > + */
> > +struct hwd_viif_img_area {
> > + u32 x;
> > + u32 y;
> > + u32 w;
> > + u32 h;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_out_process - configuration of output process of MAIN unit
> and L2ISP
> > + * @half_scale: hwd_viif_enable_flag "enable or disable half scale"
> > + * @select_color: hwd_viif_output_color_mode "select output color"
> > + * @alpha: alpha value used in case of ARGB8888 output [0..255]
> > + */
> > +struct hwd_viif_out_process {
> > + u32 half_scale;
> > + u32 select_color;
> > + u8 alpha;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l1_lsc - HWD L1ISP lens shading correction parameters
> > + * @lssc_parabola_param: parabola shading correction parameter
> > + * * NULL: disable parabola shading correction
> > + * * not NULL: enable parabola shading correction
> > + * @lssc_grid_param: grid shading correction parameter
> > + * * NULL: disable grid shading correction
> > + * * not NULL: enable grid shading correction
> > + * @lssc_pwhb_r_gain_max: maximum R gain of preset white balance
> correction
> > + * @lssc_pwhb_r_gain_min: minimum R gain of preset white balance
> correction
> > + * @lssc_pwhb_gr_gain_max: maximum Gr gain of preset white balance
> correction
> > + * @lssc_pwhb_gr_gain_min: minimum Gr gain of preset white balance
> correction
> > + * @lssc_pwhb_gb_gain_max: maximum Gb gain of preset white balance
> correction
> > + * @lssc_pwhb_gb_gain_min: minimum Gb gain of preset white balance
> correction
> > + * @lssc_pwhb_b_gain_max: maximum B gain of preset white balance
> correction
> > + * @lssc_pwhb_b_gain_min: minimum B gain of preset white balance
> correction
> > + *
> > + * Range and accuracy of lssc_pwhb_xxx_gain_xxx are as below.
> > + * - range: [0x0..0x7FF]
> > + * - accuracy : 1/256
> > + */
> > +struct hwd_viif_l1_lsc {
> > + struct viif_l1_lsc_parabola_param *lssc_parabola_param;
> > + struct viif_l1_lsc_grid_param *lssc_grid_param;
> > + u32 lssc_pwhb_r_gain_max;
> > + u32 lssc_pwhb_r_gain_min;
> > + u32 lssc_pwhb_gr_gain_max;
> > + u32 lssc_pwhb_gr_gain_min;
> > + u32 lssc_pwhb_gb_gain_max;
> > + u32 lssc_pwhb_gb_gain_min;
> > + u32 lssc_pwhb_b_gain_max;
> > + u32 lssc_pwhb_b_gain_min;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l1_img_quality_adjustment - HWD L1ISP image quality
> adjustment parameters
> > + * @coef_cb: Cb coefficient [0x0..0xffff] accuracy: 1/65536
> > + * @coef_cr: Cr coefficient [0x0..0xffff] accuracy: 1/65536
> > + * @brightness: brightness value [-32768..32767] (0 means off.)
> > + * @linear_contrast: linear contrast value [0x0..0xff] accuracy: 1/128 (128
> means off.)
> > + * @*nonlinear_contrast: pointer to nonlinear contrast parameter
> > + * @*lum_noise_reduction: pointer to luminance noise reduction parameter
> > + * @*edge_enhancement: pointer to edge enhancement parameter
> > + * @*uv_suppression: pointer to UV suppression parameter
> > + * @*coring_suppression: pointer to coring suppression parameter
> > + * @*edge_suppression: pointer to edge enhancement parameter
> > + * @*color_level: pointer to color level adjustment parameter
> > + * @color_noise_reduction_enable: enable/disable color noise reduction @ref
> hwd_viif_enable_flag
> > + */
> > +struct hwd_viif_l1_img_quality_adjustment {
> > + u16 coef_cb;
> > + u16 coef_cr;
> > + s16 brightness;
> > + u8 linear_contrast;
> > + struct viif_l1_nonlinear_contrast *nonlinear_contrast;
> > + struct viif_l1_lum_noise_reduction *lum_noise_reduction;
> > + struct viif_l1_edge_enhancement *edge_enhancement;
> > + struct viif_l1_uv_suppression *uv_suppression;
> > + struct viif_l1_coring_suppression *coring_suppression;
> > + struct viif_l1_edge_suppression *edge_suppression;
> > + struct viif_l1_color_level *color_level;
> > + u32 color_noise_reduction_enable;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l1_info - HWD L1ISP processing information
> > + * @context_id: context id
> > + * @ag_cont_hobc_high: analog gain for high sensitivity image of OBCC
> > + * @ag_cont_hobc_middle_led: analog gain for middle sensitivity or led image
> of OBCC
> > + * @ag_cont_hobc_low: analog gain for low sensitivity image of OBCC
> > + * @ag_cont_abpc_high: analog gain for high sensitivity image of ABPC
> > + * @ag_cont_abpc_middle_led: analog gain for middle sensitivity or led image
> of ABPC
> > + * @ag_cont_abpc_low: analog gain for low sensitivity image of ABPC
> > + * @ag_cont_rcnr_high: analog gain for high sensitivity image of RCNR
> > + * @ag_cont_rcnr_middle_led: analog gain for middle sensitivity or led image
> of RCNR
> > + * @ag_cont_rcnr_low: analog gain for low sensitivity image of RCNR
> > + * @ag_cont_lssc: analog gain for LSSC
> > + * @ag_cont_mpro: analog gain for color matrix correction
> > + * @ag_cont_vpro: analog gain for image quality adjustment
> > + * @dpc_defect_num_h:
> > + * the number of dynamically corrected defective pixel(high sensitivity
> image)
> > + * @dpc_defect_num_m:
> > + * the number of dynamically corrected defective pixel(middle
> sensitivity or led image)
> > + * @dpc_defect_num_l:
> > + * the number of dynamically corrected defective pixel(low sensitivity
> image)
> > + * @hdrc_tnp_fb_smth_max: the maximum value of luminance information
> after smoothing filter at HDRC
> > + * @avg_lum_weight: weighted average luminance value at average
> luminance generation
> > + * @avg_lum_block[8][8]:
> > + * average luminance of each block [y][x]:
> > + * y means vertical position and x means horizontal position.
> > + * @avg_lum_four_line_lum[4]:
> > + * 4-lines average luminance. avg_lum_four_line_lum[n] corresponds to
> aexp_ave4linesy[n]
> > + * @avg_satur_pixnum: the number of saturated pixel at average luminance
> generation
> > + * @avg_black_pixnum: the number of black pixel at average luminance
> generation
> > + * @awb_ave_u: average U at AWHB [pixel]
> > + * @awb_ave_v: average V at AWHB [pixel]
> > + * @awb_accumulated_pixel: the number of accumulated pixel at AWHB
> > + * @awb_gain_r: R gain applied in the next frame at AWHB
> > + * @awb_gain_g: G gain applied in the next frame at AWHB
> > + * @awb_gain_b: B gain applied in the next frame at AWHB
> > + * @awb_status_u: status of U convergence at AWHB (true: converged, false:
> not converged)
> > + * @awb_status_v: status of V convergence at AWHB (true: converged, false:
> not converged)
> > + */
> > +struct hwd_viif_l1_info {
> > + u32 context_id;
> > + u8 ag_cont_hobc_high;
> > + u8 ag_cont_hobc_middle_led;
> > + u8 ag_cont_hobc_low;
> > + u8 ag_cont_abpc_high;
> > + u8 ag_cont_abpc_middle_led;
> > + u8 ag_cont_abpc_low;
> > + u8 ag_cont_rcnr_high;
> > + u8 ag_cont_rcnr_middle_led;
> > + u8 ag_cont_rcnr_low;
> > + u8 ag_cont_lssc;
> > + u8 ag_cont_mpro;
> > + u8 ag_cont_vpro;
> > + u32 dpc_defect_num_h;
> > + u32 dpc_defect_num_m;
> > + u32 dpc_defect_num_l;
> > + u32 hdrc_tnp_fb_smth_max;
> > + u32 avg_lum_weight;
> > + u32 avg_lum_block[8][8];
> > + u32 avg_lum_four_line_lum[4];
> > + u16 avg_satur_pixnum;
> > + u16 avg_black_pixnum;
> > + u32 awb_ave_u;
> > + u32 awb_ave_v;
> > + u32 awb_accumulated_pixel;
> > + u32 awb_gain_r;
> > + u32 awb_gain_g;
> > + u32 awb_gain_b;
> > + bool awb_status_u;
> > + bool awb_status_v;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l2_gamma_table - HWD L2ISP Gamma table physical
> address
> > + * @table[6]: table address(physical address) 4byte alignment
> > + *
> > + * relation between element and table is as below.
> > + * * [0]: G/Y(1st table)
> > + * * [1]: G/Y(2nd table)
> > + * * [2]: B/U(1st table)
> > + * * [3]: B/U(2nd table)
> > + * * [4]: R/V(1st table)
> > + * * [5]: R/V(2nd table)
> > + *
> > + * when 0 is set to table address, table transfer is disabled.
> > + */
> > +struct hwd_viif_l2_gamma_table {
> > + uintptr_t table[6];
> > +};
> > +
> > +struct hwd_viif_res;
> > +
> > +/* VIIF common */
> > +u32 hwd_viif_csi2rx_err_irq_handler(struct hwd_viif_res *res);
> > +void hwd_viif_status_err_irq_handler(struct hwd_viif_res *res, u32
> *event_main, u32 *event_sub);
> > +void hwd_viif_vsync_irq_handler(struct hwd_viif_res *res, u32 *event_main,
> u32 *event_sub);
> > +void hwd_viif_isp_regbuf_irq_handler(struct hwd_viif_res *res, u32 *event_l1,
> u32 *event_l2);
> > +
> > +/* control MAIN unit */
> > +s32 hwd_viif_main_set_unit(struct hwd_viif_res *res, u32 dt_image,
> > + const struct hwd_viif_input_img *in_img, u32
> color_type, u32 rawpack,
> > + u32 yuv_conv);
> > +s32 hwd_viif_main_mask_vlatch(struct hwd_viif_res *res, u32 enable);
> > +void hwd_viif_main_status_err_set_irq_mask(struct hwd_viif_res *res, u32
> mask);
> > +void hwd_viif_main_vsync_set_irq_mask(struct hwd_viif_res *res, u32
> mask);
> > +
> > +/* conrol SUB unit */
> > +s32 hwd_viif_sub_set_unit(struct hwd_viif_res *res, u32 dt_image,
> > + const struct hwd_viif_input_img *in_img);
> > +s32 hwd_viif_sub_set_img_transmission(struct hwd_viif_res *res, const
> struct hwd_viif_img *img);
> > +void hwd_viif_sub_status_err_set_irq_mask(struct hwd_viif_res *res, u32
> mask);
> > +void hwd_viif_sub_vsync_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> > +
> > +/* control MIPI CSI2 Receiver unit */
> > +s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32
> lane_assign,
> > + u32 dphy_rate, u32 rext_calibration,
> > + const struct hwd_viif_csi2rx_line_err_target
> *err_target,
> > + const struct hwd_viif_csi2rx_irq_mask *mask);
> > +s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res);
> > +s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
> > + const struct hwd_viif_csi2rx_packet *packet);
> > +s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res);
> > +s32 hwd_viif_csi2rx_get_calibration_status(
> > + struct hwd_viif_res *res, struct viif_csi2rx_dphy_calibration_status
> *calibration_status);
> > +s32 hwd_viif_csi2rx_get_err_status(struct hwd_viif_res *res, u32
> *err_phy_fatal, u32 *err_pkt_fatal,
> > + u32 *err_frame_fatal, u32 *err_phy, u32
> *err_pkt, u32 *err_line);
> > +
> > +/* control L1 Image Signal Processor */
> > +void hwd_viif_isp_set_regbuf_auto_transmission(struct hwd_viif_res *res);
> > +void hwd_viif_isp_disable_regbuf_auto_transmission(struct hwd_viif_res
> *res);
> > +void hwd_viif_isp_get_info(struct hwd_viif_res *res, struct hwd_viif_l1_info
> *l1_info,
> > + u32 *l2_transfer_status);
> > +void hwd_viif_isp_set_regbuf_irq_mask(struct hwd_viif_res *res, const u32
> *mask_l1,
> > + const u32 *mask_l2);
> > +
> > +s32 hwd_viif_l1_set_input_mode(struct hwd_viif_res *res, u32 mode, u32
> depth, u32 raw_color_filter);
> > +s32 hwd_viif_l1_set_rgb_to_y_coef(struct hwd_viif_res *res, u16 coef_r, u16
> coef_g, u16 coef_b);
> > +s32 hwd_viif_l1_set_ag_mode(struct hwd_viif_res *res, const struct
> viif_l1_ag_mode_config *param);
> > +s32 hwd_viif_l1_set_ag(struct hwd_viif_res *res, u16 gain_h, u16 gain_m,
> u16 gain_l);
> > +s32 hwd_viif_l1_set_hdre(struct hwd_viif_res *res, const struct
> viif_l1_hdre_config *param);
> > +s32 hwd_viif_l1_set_img_extraction(struct hwd_viif_res *res, u32
> input_black_gr, u32 input_black_r,
> > + u32 input_black_b, u32 input_black_gb);
> > +s32 hwd_viif_l1_set_dpc(struct hwd_viif_res *res, const struct viif_l1_dpc
> *param_h,
> > + const struct viif_l1_dpc *param_m, const struct
> viif_l1_dpc *param_l);
> > +s32 hwd_viif_l1_set_dpc_table_transmission(struct hwd_viif_res *res,
> uintptr_t table_h,
> > + uintptr_t table_m, uintptr_t
> table_l);
> > +s32 hwd_viif_l1_set_preset_white_balance(struct hwd_viif_res *res, u32
> dstmaxval,
> > + const struct viif_l1_preset_wb
> *param_h,
> > + const struct viif_l1_preset_wb
> *param_m,
> > + const struct viif_l1_preset_wb
> *param_l);
> > +s32 hwd_viif_l1_set_raw_color_noise_reduction(
> > + struct hwd_viif_res *res, const struct viif_l1_raw_color_noise_reduction
> *param_h,
> > + const struct viif_l1_raw_color_noise_reduction *param_m,
> > + const struct viif_l1_raw_color_noise_reduction *param_l);
> > +s32 hwd_viif_l1_set_hdrs(struct hwd_viif_res *res, const struct
> viif_l1_hdrs_config *param);
> > +s32 hwd_viif_l1_set_black_level_correction(
> > + struct hwd_viif_res *res, const struct
> viif_l1_black_level_correction_config *param);
> > +s32 hwd_viif_l1_set_lsc(struct hwd_viif_res *res, const struct hwd_viif_l1_lsc
> *param);
> > +s32 hwd_viif_l1_set_lsc_table_transmission(struct hwd_viif_res *res,
> uintptr_t table_gr,
> > + uintptr_t table_r, uintptr_t table_b,
> > + uintptr_t table_gb);
> > +s32 hwd_viif_l1_set_main_process(struct hwd_viif_res *res, u32
> demosaic_mode, u32 damp_lsbsel,
> > + const struct viif_l1_color_matrix_correction
> *color_matrix,
> > + u32 dst_maxval);
> > +s32 hwd_viif_l1_set_awb(struct hwd_viif_res *res, const struct viif_l1_awb
> *param, u32 awhb_wbmrg,
> > + u32 awhb_wbmgg, u32 awhb_wbmbg);
> > +s32 hwd_viif_l1_lock_awb_gain(struct hwd_viif_res *res, u32 enable);
> > +s32 hwd_viif_l1_set_hdrc(struct hwd_viif_res *res, const struct viif_l1_hdrc
> *param,
> > + u32 hdrc_thr_sft_amt);
> > +s32 hwd_viif_l1_set_hdrc_ltm(struct hwd_viif_res *res, const struct
> viif_l1_hdrc_ltm_config *param);
> > +s32 hwd_viif_l1_set_gamma(struct hwd_viif_res *res, const struct
> viif_l1_gamma *param);
> > +s32 hwd_viif_l1_set_img_quality_adjustment(struct hwd_viif_res *res,
> > + const struct
> hwd_viif_l1_img_quality_adjustment *param);
> > +s32 hwd_viif_l1_set_avg_lum_generation(struct hwd_viif_res *res,
> > + const struct
> viif_l1_avg_lum_generation_config *param);
> > +void hwd_viif_l1_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> > +
> > +/* control L2 Image Signal Processor */
> > +s32 hwd_viif_l2_set_input_csc(struct hwd_viif_res *res, const struct
> hwd_viif_csc_param *param,
> > + bool is_l1_rgb);
> > +s32 hwd_viif_l2_set_undist(struct hwd_viif_res *res, const struct
> viif_l2_undist *param);
> > +s32 hwd_viif_l2_set_undist_table_transmission(struct hwd_viif_res *res,
> uintptr_t write_g,
> > + uintptr_t read_b, uintptr_t
> read_g, uintptr_t read_r,
> > + u32 size);
> > +s32 hwd_viif_l2_set_roi(struct hwd_viif_res *res, const struct
> viif_l2_roi_config *param);
> > +s32 hwd_viif_l2_set_gamma(struct hwd_viif_res *res, u32 post_id, u32
> enable, u32 vsplit, u32 mode);
> > +s32 hwd_viif_l2_set_gamma_table_transmission(struct hwd_viif_res *res,
> u32 post_id,
> > + const struct
> hwd_viif_l2_gamma_table *gamma_table);
> > +s32 hwd_viif_l2_set_output_csc(struct hwd_viif_res *res, u32 post_id,
> > + const struct hwd_viif_csc_param *param);
> > +s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id,
> u32 enable,
> > + const struct hwd_viif_img_area *src,
> > + const struct hwd_viif_out_process
> *out_process,
> > + const struct hwd_viif_img *img);
> > +void hwd_viif_l2_set_irq_mask(struct hwd_viif_res *res, u32 mask);
> > +
> > +void hwd_viif_isp_guard_start(struct hwd_viif_res *res);
> > +void hwd_viif_isp_guard_end(struct hwd_viif_res *res);
> > +
> > +struct hwd_viif_res *allocate_viif_res(struct device *dev, void
> *csi2host_vaddr,
> > + void *capture_vaddr);
> > +
> > +#endif /* HWD_VIIF_H */
> > diff --git a/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > new file mode 100644
> > index 00000000000..f49869c5bdd
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > @@ -0,0 +1,610 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/timekeeping.h>
> > +#include "hwd_viif.h"
> > +#include "hwd_viif_internal.h"
> > +
> > +#define CSI2_DT_YUV4208 0x18
> > +#define CSI2_DT_YUV42010 0x19
> > +#define CSI2_DT_YUV4208L 0x1A
> > +#define CSI2_DT_YUV4208C 0x1C
> > +#define CSI2_DT_YUV42010C 0x1D
> > +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> > +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> > +#define CSI2_DT_RGB444 0x20
> > +#define CSI2_DT_RGB555 0x21
> > +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> > +#define CSI2_DT_RGB666 0x23
> > +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> > +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> > +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> > +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> > +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
>
> Same here.
I'll use definitions in mipi-csi2.h
> > +
> > +#define TESTCTRL0_PHY_TESTCLK_1 0x2
> > +#define TESTCTRL0_PHY_TESTCLK_0 0x0
> > +#define TESTCTRL1_PHY_TESTEN 0x10000
> > +#define TESTCTRL1_PHY_TESTDOUT_SHIFT 8U
> > +
> > +/**
> > + * write_dphy_param() - Write CSI2RX DPHY params
> > + *
> > + * @test_mode: test code address
> > + * @test_in: test code data
> > + * Return: None
> > + */
> > +static void write_dphy_param(u32 test_mode, u8 test_in, struct hwd_viif_res
> *res)
> > +{
> > + /* select MSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* set MSB address of test_mode */
> > + writel(FIELD_GET(0xF00, test_mode),
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* select and set LSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> > + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* set the test code data */
> > + writel((u32)test_in, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +}
> > +
> > +/**
> > + * read_dphy_param() - Read CSI2RX DPHY params
> > + *
> > + * @test_mode: test code address
> > + * Return: test code data
> > + */
> > +static u8 read_dphy_param(u32 test_mode, struct hwd_viif_res *res)
> > +{
> > + u32 read_data;
> > +
> > + /* select MSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* set MSB address of test_mode */
> > + writel(FIELD_GET(0xF00, test_mode),
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* select and set LSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> > + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* read the test code data */
> > + read_data = readl(&res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > + return (u8)(read_data >> TESTCTRL1_PHY_TESTDOUT_SHIFT);
> > +}
> > +
> > +/**
> > + * enum dphy_testcode - DPHY registers via the local communication path
> > + */
> > +enum dphy_testcode {
> > + DIG_RDWR_RX_SYS_0 = 0x001,
> > + DIG_RDWR_RX_SYS_1 = 0x002,
> > + DIG_RDWR_RX_SYS_3 = 0x004,
> > + DIG_RDWR_RX_SYS_7 = 0x008,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_2 = 0x0E2,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_3 = 0x0E3,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_4 = 0x0E4,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_5 = 0x0E5,
> > + DIG_RDWR_RX_CB_2 = 0x1AC,
> > + DIG_RD_RX_TERM_CAL_0 = 0x220,
> > + DIG_RD_RX_TERM_CAL_1 = 0x221,
> > + DIG_RD_RX_TERM_CAL_2 = 0x222,
> > + DIG_RDWR_RX_CLKLANE_LANE_6 = 0x307,
> > + DIG_RD_RX_CLKLANE_OFFSET_CAL_0 = 0x39D,
> > + DIG_RD_RX_LANE0_OFFSET_CAL_0 = 0x59F,
> > + DIG_RD_RX_LANE0_DDL_0 = 0x5E0,
> > + DIG_RD_RX_LANE1_OFFSET_CAL_0 = 0x79F,
> > + DIG_RD_RX_LANE1_DDL_0 = 0x7E0,
> > + DIG_RD_RX_LANE2_OFFSET_CAL_0 = 0x99F,
> > + DIG_RD_RX_LANE2_DDL_0 = 0x9E0,
> > + DIG_RD_RX_LANE3_OFFSET_CAL_0 = 0xB9F,
> > + DIG_RD_RX_LANE3_DDL_0 = 0xBE0,
> > +};
> > +
> > +#define SYS_0_HSFREQRANGE_OVR BIT(5)
> > +#define SYS_7_RESERVED FIELD_PREP(0x1F, 0x0C)
> > +#define SYS_7_DESKEW_POL BIT(5)
> > +#define STARTUP_OVR_4_CNTVAL FIELD_PREP(0x70, 0x01)
> > +#define STARTUP_OVR_4_DDL_EN BIT(0)
> > +#define STARTUP_OVR_5_BYPASS BIT(0)
> > +#define CB_2_LPRX_BIAS BIT(6)
> > +#define CB_2_RESERVED FIELD_PREP(0x3F, 0x0B)
> > +#define CLKLANE_RXHS_PULL_LONG BIT(7)
> > +
> > +static const struct hwd_viif_dphy_hs_info dphy_hs_info[] = {
> > + { 80, 0x0, 0x1cc }, { 85, 0x10, 0x1cc }, { 95, 0x20, 0x1cc }, { 105,
> 0x30, 0x1cc },
> > + { 115, 0x1, 0x1cc }, { 125, 0x11, 0x1cc }, { 135, 0x21, 0x1cc }, { 145,
> 0x31, 0x1cc },
> > + { 155, 0x2, 0x1cc }, { 165, 0x12, 0x1cc }, { 175, 0x22, 0x1cc }, { 185,
> 0x32, 0x1cc },
> > + { 198, 0x3, 0x1cc }, { 213, 0x13, 0x1cc }, { 228, 0x23, 0x1cc }, { 243,
> 0x33, 0x1cc },
> > + { 263, 0x4, 0x1cc }, { 288, 0x14, 0x1cc }, { 313, 0x25, 0x1cc }, { 338,
> 0x35, 0x1cc },
> > + { 375, 0x5, 0x1cc }, { 425, 0x16, 0x1cc }, { 475, 0x26, 0x1cc }, { 525,
> 0x37, 0x1cc },
> > + { 575, 0x7, 0x1cc }, { 625, 0x18, 0x1cc }, { 675, 0x28, 0x1cc }, { 725,
> 0x39, 0x1cc },
> > + { 775, 0x9, 0x1cc }, { 825, 0x19, 0x1cc }, { 875, 0x29, 0x1cc }, { 925,
> 0x3a, 0x1cc },
> > + { 975, 0xa, 0x1cc }, { 1025, 0x1a, 0x1cc }, { 1075, 0x2a, 0x1cc }, { 1125,
> 0x3b, 0x1cc },
> > + { 1175, 0xb, 0x1cc }, { 1225, 0x1b, 0x1cc }, { 1275, 0x2b, 0x1cc }, { 1325,
> 0x3c, 0x1cc },
> > + { 1375, 0xc, 0x1cc }, { 1425, 0x1c, 0x1cc }, { 1475, 0x2c, 0x1cc }
> > +};
> > +
> > +/**
> > + * get_dphy_hs_transfer_info() - Get DPHY HS info from table
> > + *
> > + * @dphy_rate: DPHY clock in MHz
> > + * @hsfreqrange: HS Frequency Range
> > + * @osc_freq_target: OSC Frequency Target
> > + * Return: None
> > + */
> > +static void get_dphy_hs_transfer_info(u32 dphy_rate, u32 *hsfreqrange, u32
> *osc_freq_target,
> > + struct hwd_viif_res *res)
> > +{
> > + int table_size = ARRAY_SIZE(dphy_hs_info);
>
> No need for a local variable.
I'll drop it.
> > + int i;
>
> unsigned int
I'll fix it. Same for similar cases.
> > +
> > + for (i = 1; i < table_size; i++) {
> > + if (dphy_rate < dphy_hs_info[i].rate) {
> > + *hsfreqrange = dphy_hs_info[i - 1].hsfreqrange;
> > + *osc_freq_target = dphy_hs_info[i - 1].osc_freq_target;
> > + return;
> > + }
> > + }
> > +
> > + /* not found; return the largest entry */
> > + *hsfreqrange = dphy_hs_info[table_size - 1].hsfreqrange;
> > + *osc_freq_target = dphy_hs_info[table_size - 1].osc_freq_target;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_set_dphy_rate() - Set D-PHY rate
> > + *
> > + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> > + * Return: None
> > + */
> > +static void hwd_viif_csi2rx_set_dphy_rate(u32 dphy_rate, struct hwd_viif_res
> *res)
> > +{
> > + u32 hsfreqrange, osc_freq_target;
> > +
> > + get_dphy_hs_transfer_info(dphy_rate, &hsfreqrange, &osc_freq_target,
> res);
> > +
> > + write_dphy_param(DIG_RDWR_RX_SYS_1, (u8)hsfreqrange, res);
> > + write_dphy_param(DIG_RDWR_RX_SYS_0,
> SYS_0_HSFREQRANGE_OVR, res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_5,
> STARTUP_OVR_5_BYPASS, res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4,
> STARTUP_OVR_4_CNTVAL, res);
> > + write_dphy_param(DIG_RDWR_RX_CB_2, CB_2_LPRX_BIAS |
> CB_2_RESERVED, res);
> > + write_dphy_param(DIG_RDWR_RX_SYS_7, SYS_7_DESKEW_POL |
> SYS_7_RESERVED, res);
> > + write_dphy_param(DIG_RDWR_RX_CLKLANE_LANE_6,
> CLKLANE_RXHS_PULL_LONG, res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_2,
> FIELD_GET(0xff, osc_freq_target), res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_3,
> FIELD_GET(0xf00, osc_freq_target), res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4,
> STARTUP_OVR_4_CNTVAL | STARTUP_OVR_4_DDL_EN,
> > + res);
> > +
> > + writel(HWD_VIIF_DPHY_CFG_CLK_25M,
> &res->capture_reg->sys.DPHY_FREQRANGE);
> > +}
> > +
> > +/**
> > + * check_dphy_calibration_status() - Check D-PHY calibration status
> > + *
> > + * @test_mode: test code related to calibration information
> > + * @shift_val_err: shift value related to error information
> > + * @shift_val_done: shift value related to done information
> > + * Return: HWD_VIIF_CSI2_CAL_NOT_DONE calibration is not done(out of
> target or not completed)
> > + * Return: HWD_VIIF_CSI2_CAL_FAIL calibration was failed
> > + * Return: HWD_VIIF_CSI2_CAL_SUCCESS calibration was succeeded
> > + */
> > +static u32 check_dphy_calibration_status(u32 test_mode, u32 shift_val_err,
> u32 shift_val_done,
> > + struct hwd_viif_res *res)
> > +{
> > + u32 read_data = (u32)read_dphy_param(test_mode, res);
> > +
> > + if (!(read_data & BIT(shift_val_done)))
> > + return HWD_VIIF_CSI2_CAL_NOT_DONE;
> > +
> > + /* error check is not required for termination calibration with
> REXT(0x221) */
> > + if (test_mode == DIG_RD_RX_TERM_CAL_1)
> > + return HWD_VIIF_CSI2_CAL_SUCCESS;
> > +
> > + /* done with error */
> > + if (read_data & BIT(shift_val_err))
> > + return HWD_VIIF_CSI2_CAL_FAIL;
> > +
> > + return HWD_VIIF_CSI2_CAL_SUCCESS;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_initialize() - Initialize CSI-2 RX driver
> > + *
> > + * @num_lane: [1..4](VIIF CH0-CH1)
> > + * @lane_assign: lane connection. For more refer @ref
> hwd_viif_dphy_lane_assignment
> > + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> > + * @rext_calibration: enable or disable rext calibration.
> > + * For more refer @ref hwd_viif_csi2rx_cal_status
> > + * @err_target: Pointer to configuration for Line error detection.
> > + * @mask: MASK of CSI-2 RX error interruption
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "num_lane", "lane_assign", "dphy_rate", "rext_calibration" or
> "input_mode" is out of range
> > + * - [2] "err_target" is NULL
> > + * - [3] member of "err_target" is invalid
> > + */
> > +s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32
> lane_assign,
> > + u32 dphy_rate, u32 rext_calibration,
> > + const struct hwd_viif_csi2rx_line_err_target
> *err_target,
> > + const struct hwd_viif_csi2rx_irq_mask *mask)
> > +{
> > + u32 i, val;
> > +
> > + if (num_lane == 0U || num_lane > 4U || lane_assign >
> HWD_VIIF_CSI2_DPHY_L0L2L1L3)
> > + return -EINVAL;
> > +
> > + if (dphy_rate < HWD_VIIF_DPHY_MIN_DATA_RATE || dphy_rate >
> HWD_VIIF_DPHY_MAX_DATA_RATE ||
> > + (rext_calibration != HWD_VIIF_ENABLE && rext_calibration !=
> HWD_VIIF_DISABLE) ||
> > + !err_target) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < 8U; i++) {
> > + if (err_target->vc[i] > HWD_VIIF_CSI2_MAX_VC ||
> > + err_target->dt[i] > HWD_VIIF_CSI2_MAX_DT ||
> > + (err_target->dt[i] < HWD_VIIF_CSI2_MIN_DT &&
> err_target->dt[i] != 0U)) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + /* 1st phase of initialization */
> > + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_RESETN);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> > + writel(HWD_VIIF_ENABLE,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + ndelay(15U);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* Configure D-PHY frequency range */
> > + hwd_viif_csi2rx_set_dphy_rate(dphy_rate, res);
> > +
> > + /* 2nd phase of initialization */
> > + writel((num_lane - 1U), &res->csi2host_reg->CSI2RX_NLANES);
> > + ndelay(5U);
> > +
> > + /* configuration not to use rext */
> > + if (rext_calibration == HWD_VIIF_DISABLE) {
> > + write_dphy_param(0x004, 0x10, res);
> > + ndelay(5U);
> > + }
> > +
> > + /* Release D-PHY from Reset */
> > + writel(HWD_VIIF_ENABLE,
> &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> > + ndelay(5U);
> > + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> > +
> > + /* configuration of line error target */
> > + val = (err_target->vc[3] << 30U) | (err_target->dt[3] << 24U) |
> (err_target->vc[2] << 22U) |
> > + (err_target->dt[2] << 16U) | (err_target->vc[1] << 14U) |
> (err_target->dt[1] << 8U) |
> > + (err_target->vc[0] << 6U) | (err_target->dt[0]);
> > + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_1);
> > + val = (err_target->vc[7] << 30U) | (err_target->dt[7] << 24U) |
> (err_target->vc[6] << 22U) |
> > + (err_target->dt[6] << 16U) | (err_target->vc[5] << 14U) |
> (err_target->dt[5] << 8U) |
> > + (err_target->vc[4] << 6U) | (err_target->dt[4]);
> > + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_2);
> > +
> > + /* configuration of mask */
> > + writel(mask->mask[0],
> &res->csi2host_reg->CSI2RX_INT_MSK_PHY_FATAL);
> > + writel(mask->mask[1],
> &res->csi2host_reg->CSI2RX_INT_MSK_PKT_FATAL);
> > + writel(mask->mask[2],
> &res->csi2host_reg->CSI2RX_INT_MSK_FRAME_FATAL);
> > + writel(mask->mask[3], &res->csi2host_reg->CSI2RX_INT_MSK_PHY);
> > + writel(mask->mask[4], &res->csi2host_reg->CSI2RX_INT_MSK_PKT);
> > + writel(mask->mask[5],
> &res->csi2host_reg->CSI2RX_INT_MSK_LINE);
> > +
> > + /* configuration of lane assignment */
> > + writel(lane_assign, &res->capture_reg->sys.DPHY_LANE);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_uninitialize() - Uninitialize CSI-2 RX driver
> > + *
> > + * Return: 0 Operation completes successfully
> > + */
> > +s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res)
> > +{
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> > + writel(HWD_VIIF_ENABLE,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_RESETN);
> > +
> > + return 0;
> > +}
> > +
> > +#define PORT_SEL_MAIN_LONG 0
> > +#define PORT_SEL_MAIN_EMBED 1
> > +#define PORT_SEL_SUB_LONG 4
> > +#define PORT_SEL_SUB_EMBED 5
> > +
> > +static void config_vdm_wport(struct hwd_viif_res *res, int port_sel, u32
> height, u32 pitch)
> > +{
> > + struct hwd_viif_vdm_write_port_reg *wport;
> > + u32 start_addr, end_addr;
> > +
> > + wport = &res->capture_reg->vdm.w_port[port_sel];
> > +
> > + writel(pitch, &wport->VDM_W_PITCH);
> > + writel(height, &wport->VDM_W_HEIGHT);
> > + start_addr = readl(&wport->VDM_W_STADR);
> > + end_addr = start_addr + pitch - 1U;
> > + writel(end_addr, &wport->VDM_W_ENDADR);
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_start() - Start CSI-2 input
> > + *
> > + * @vc_main: control CSI-2 input of MAIN unit.
> > + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> > + * @vc_sub: control CSI-2 input of SUB unit.
> > + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> > + * @packet: Pointer to packet information of embedded data and long packet
> data
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * HWD_VIIF_CSI2_NOT_CAPTURE
> > + * HWD_VIIF_CSI2_NOT_CAPTURE
> > + * - [1] "vc_main" or "vc_sub" is out of range
> > + * - [2] member of "packet" is invalid
> > + */
> > +s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
> > + const struct hwd_viif_csi2rx_packet *packet)
> > +{
> > + u32 val, i, pitch, height, dt;
> > + u32 enable_vc0 = HWD_VIIF_DISABLE;
> > + u32 enable_vc1 = HWD_VIIF_DISABLE;
> > +
> > + if (vc_main > 3 || vc_main < HWD_VIIF_CSI2_NOT_CAPTURE || vc_sub
> > 3 ||
> > + vc_sub < HWD_VIIF_CSI2_NOT_CAPTURE) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < VISCONTI_CSI2RX_PACKET_TYPES_NUM; i++) {
> > + if (packet->word_count[i] >
> HWD_VIIF_CSI2_MAX_WORD_COUNT ||
> > + packet->packet_num[i] >
> HWD_VIIF_CSI2_MAX_PACKET_NUM) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + writel(HWD_VIIF_INPUT_CSI2, &res->capture_reg->sys.IPORTM);
> > +
> > + if (vc_main != HWD_VIIF_CSI2_NOT_CAPTURE) {
> > + writel((u32)vc_main, &res->capture_reg->sys.VCID0SELECT);
> > + enable_vc0 = HWD_VIIF_ENABLE;
> > + }
> > + if (vc_sub != HWD_VIIF_CSI2_NOT_CAPTURE) {
> > + writel((u32)vc_sub, &res->capture_reg->sys.VCID1SELECT);
> > + enable_vc1 = HWD_VIIF_ENABLE;
> > + }
> > +
> > + /* configure Embedded Data transfer of MAIN unit */
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN];
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN],
> 4);
> > + config_vdm_wport(res, PORT_SEL_MAIN_EMBED, height, pitch);
> > +
> > + /* configure Long Packet transfer of MAIN unit */
> > + dt = readl(&res->capture_reg->sys.IPORTM_OTHER);
> > + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208 || dt ==
> CSI2_DT_YUV4208C ||
> > + dt == CSI2_DT_YUV42010C) {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN],
> 4) +
> > +
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LON
> G_MAIN] * 2U, 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] >>
> 1U;
> > + } else {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN],
> 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN];
> > + }
> > + config_vdm_wport(res, PORT_SEL_MAIN_LONG, height, pitch);
> > +
> > + /* configure Embedded Data transfer of SUB unit */
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB];
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB],
> 4);
> > + config_vdm_wport(res, PORT_SEL_SUB_EMBED, height, pitch);
> > +
> > + /* configure Long Packet transfer of SUB unit */
> > + dt = readl(&res->capture_reg->sys.IPORTS_OTHER);
> > + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV42010 || dt ==
> CSI2_DT_YUV4208C ||
> > + dt == CSI2_DT_YUV42010C) {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB],
> 4) +
> > +
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LON
> G_SUB] * 2U, 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] >> 1U;
> > + } else {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB],
> 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB];
> > + }
> > + config_vdm_wport(res, PORT_SEL_SUB_LONG, height, pitch);
> > +
> > + /* Control VC port enable */
> > + val = enable_vc0 | (enable_vc1 << 4U);
> > + writel(val, &res->capture_reg->sys.VCPORTEN);
> > +
> > + if (enable_vc0 == HWD_VIIF_ENABLE) {
> > + /* Update flag information for run status of MAIN unit */
> > + res->run_flag_main = true;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_stop() - Stop CSI-2 input
> > + *
> > + * Return: 0 Operation completes successfully
> > + * Return: -ETIMEDOUT Driver timeout error
> > + */
> > +s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res)
> > +{
> > + u32 status_r, status_w, status_t, l2_status;
> > + u64 timeout_ns, cur_ns;
> > + bool run_flag = true;
> > + s32 ret = 0;
>
> int, please. The same for return type.
>
> This applies to the rest of the patch. Use s32 if you're e.g. dealing with
> hardware registers with a sign bit.
I'll fix it. Same for other functions.
> > +
> > + /* Disable auto transmission of register buffer */
> > + writel(0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> > + writel(0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
> > +
> > + /* Wait for completion of register buffer transmission */
> > + udelay(HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME);
> > +
> > + /* Stop all VCs, long packet input and emb data input of MAIN unit */
> > + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.VCPORTEN);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTM_OTHEREN);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTM_EMBEN);
> > +
> > + /* Stop image data input, long packet input and emb data input of SUB
> unit */
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTS_OTHEREN);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTS_EMBEN);
> > + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> > +
> > + /* Stop VDMAC for all table ports, input ports and write ports */
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->vdm.VDM_T_ENABLE);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->vdm.VDM_R_ENABLE);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->vdm.VDM_W_ENABLE);
> > +
> > + /* Stop all groups(g00, g01 and g02) of VDMAC */
> > + writel(0x7, &res->capture_reg->vdm.VDM_ABORTSET);
> > +
> > + timeout_ns = ktime_get_ns() +
> HWD_VIIF_WAIT_ABORT_COMPLETE_TIME * 1000;
>
> Wouldn't it be better to calculate how long you expect to busy loop here?
Sorry I couldn't catch the point.
The maximum time to spend at busy loop is HWD_VIIF_WAIT_ABORT_COMPLETE_TIME * 1000 [ns].
Do you mean that it is better to clearly show the timeout? Like...
ret = -ETIMEOUT;
do {
if (...) {
ret = 0;
break;
}
} while (timeout_ns > cur_ns);
> > +
> > + do {
> > + /* Get VDMAC transfer status */
> > + status_r = readl(&res->capture_reg->vdm.VDM_R_RUN);
> > + status_w = readl(&res->capture_reg->vdm.VDM_W_RUN);
> > + status_t = readl(&res->capture_reg->vdm.VDM_T_RUN);
> > +
> > + l2_status =
> readl(&res->capture_reg->l2isp.L2_BUS_L2_STATUS);
> > +
> > + if (status_r == 0U && status_w == 0U && status_t == 0U &&
> l2_status == 0U)
> > + run_flag = false;
> > +
> > + cur_ns = ktime_get_ns();
> > +
> > + if (cur_ns > timeout_ns) {
> > + ret = -ETIMEDOUT;
> > + run_flag = false;
> > + }
> > + } while (run_flag);
> > +
> > + if (ret == 0) {
> > + /* Clear run flag of MAIN unit */
> > + res->run_flag_main = false;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_get_calibration_status() - Get CSI-2 RX calibration status
> > + *
> > + * @calibration_status: Pointer to D-PHY calibration status information
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "calibration_status" is NULL
> > + */
> > +s32 hwd_viif_csi2rx_get_calibration_status(
> > + struct hwd_viif_res *res, struct viif_csi2rx_dphy_calibration_status
> *calibration_status)
> > +{
> > + if (!calibration_status)
> > + return -EINVAL;
> > +
> > + /* arg0; test register, arg1: error bit, arg2: done bit */
> > + /* 0x221: termination calibration with REXT */
> > + calibration_status->term_cal_with_rext =
> > + check_dphy_calibration_status(DIG_RD_RX_TERM_CAL_1, 0, 7,
> res);
> > + /* 0x39D: clock lane offset calibration */
> > + calibration_status->clock_lane_offset_cal =
> > +
> check_dphy_calibration_status(DIG_RD_RX_CLKLANE_OFFSET_CAL_
> 0, 4, 0, res);
> > + /* 0x59F: data lane0 offset calibration */
> > + calibration_status->data_lane0_offset_cal =
> > +
> check_dphy_calibration_status(DIG_RD_RX_LANE0_OFFSET_CAL_0, 2,
> 1, res);
> > + /* 0x79F: data lane1 offset calibration */
> > + calibration_status->data_lane1_offset_cal =
> > +
> check_dphy_calibration_status(DIG_RD_RX_LANE1_OFFSET_CAL_0, 2,
> 1, res);
> > + /* 0x99F: data lane2 offset calibration */
> > + calibration_status->data_lane2_offset_cal =
> > +
> check_dphy_calibration_status(DIG_RD_RX_LANE2_OFFSET_CAL_0, 2,
> 1, res);
> > + /* 0xB9F: data lane3 offset calibration */
> > + calibration_status->data_lane3_offset_cal =
> > +
> check_dphy_calibration_status(DIG_RD_RX_LANE3_OFFSET_CAL_0, 2,
> 1, res);
> > +
> > + /* 0x5E0: data lane0 DDL(Digital Delay Line) calibration */
> > + calibration_status->data_lane0_ddl_tuning_cal =
> > + check_dphy_calibration_status(DIG_RD_RX_LANE0_DDL_0, 1,
> 2, res);
> > + /* 0x7E0: data lane1 DDL calibration */
> > + calibration_status->data_lane1_ddl_tuning_cal =
> > + check_dphy_calibration_status(DIG_RD_RX_LANE1_DDL_0, 1,
> 2, res);
> > + /* 0x9E0: data lane2 DDL calibration */
> > + calibration_status->data_lane2_ddl_tuning_cal =
> > + check_dphy_calibration_status(DIG_RD_RX_LANE2_DDL_0, 1,
> 2, res);
> > + /* 0xBE0: data lane3 DDL calibration */
> > + calibration_status->data_lane3_ddl_tuning_cal =
> > + check_dphy_calibration_status(DIG_RD_RX_LANE3_DDL_0, 1,
> 2, res);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_get_err_status() - Get CSI-2 RX error status
> > + *
> > + * @err_phy_fatal: Pointer to D-PHY fatal error information
> > + * @err_pkt_fatal: Pointer to Packet fatal error information
> > + * @err_frame_fatal: Pointer to Frame fatal error information
> > + * @err_phy: Pointer to D-PHY error information
> > + * @err_pkt: Pointer to Packet error information
> > + * @err_line: Pointer to Line error information
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error,
> > + * when "err_phy_fatal", "err_pkt_fatal", "err_frame_fatal",
> > + * "err_phy", "err_pkt" or "err_line" is NULL
> > + */
> > +s32 hwd_viif_csi2rx_get_err_status(struct hwd_viif_res *res, u32
> *err_phy_fatal, u32 *err_pkt_fatal,
> > + u32 *err_frame_fatal, u32 *err_phy, u32
> *err_pkt, u32 *err_line)
> > +{
> > + if (!err_phy_fatal || !err_pkt_fatal || !err_frame_fatal || !err_phy
> || !err_pkt ||
> > + !err_line) {
> > + return -EINVAL;
> > + }
> > + *err_phy_fatal =
> readl(&res->csi2host_reg->CSI2RX_INT_ST_PHY_FATAL);
> > + *err_pkt_fatal =
> readl(&res->csi2host_reg->CSI2RX_INT_ST_PKT_FATAL);
> > + *err_frame_fatal =
> readl(&res->csi2host_reg->CSI2RX_INT_ST_FRAME_FATAL);
> > + *err_phy = readl(&res->csi2host_reg->CSI2RX_INT_ST_PHY);
> > + *err_pkt = readl(&res->csi2host_reg->CSI2RX_INT_ST_PKT);
> > + *err_line = readl(&res->csi2host_reg->CSI2RX_INT_ST_LINE);
> > +
> > + return 0;
> > +}
> > diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h
> b/drivers/media/platform/visconti/hwd_viif_internal.h
> > new file mode 100644
> > index 00000000000..c954e804946
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_internal.h
> > @@ -0,0 +1,340 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_INTERNAL_H
> > +#define HWD_VIIF_INTERNAL_H
> > +
> > +#include "hwd_viif_reg.h"
> > +
> > +#define HWD_VIIF_CSI2_MAX_VC (3U)
> > +#define HWD_VIIF_CSI2_MIN_DT (0x10U)
> > +#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
> > +#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
> > +#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
> > +#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
> > +#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
> > +#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
> > +#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
> > +
> > +/* maximum horizontal/vertical position/dimension of CROP with ISP */
> > +#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
> > +#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
> > +#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
> > +#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
> > +
> > +/* maximum horizontal/vertical position/dimension of CROP without ISP */
> > +#define HWD_VIIF_CROP_MAX_X (1920U)
> > +#define HWD_VIIF_CROP_MAX_Y (1408U)
> > +#define HWD_VIIF_CROP_MIN_W (128U)
> > +#define HWD_VIIF_CROP_MAX_W (2048U)
> > +#define HWD_VIIF_CROP_MIN_H (128U)
> > +#define HWD_VIIF_CROP_MAX_H (1536U)
> > +
> > +/* pixel clock: [kHz] */
> > +#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
> > +#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
> > +
> > +/* picture size: [pixel], [ns] */
> > +#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
> > +#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
> > +#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
> > +#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
> > +
> > +/* horizontal back porch size: [system clock] */
> > +#define HWD_VIIF_HBP_SYSCLK (10U)
> > +
> > +/* active picture size: [pixel] */
> > +#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
> > +#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
> > +#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
> > +#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
> > +
> > +/* picture vertical size: [line], [packet] */
> > +#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
> > +#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
> > +#define HWD_VIIF_MIN_VBP_LINE (5U)
> > +#define HWD_VIIF_MAX_VBP_LINE (4095U)
> > +#define HWD_VIIF_MIN_VBP_PACKET (5U)
> > +#define HWD_VIIF_MAX_VBP_PACKET (4095U)
> > +#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
> > +#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
> > +#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
> > +#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
> > +
> > +/* image source select */
> > +#define HWD_VIIF_INPUT_CSI2 (0U)
> > +
> > +#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
> > +#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
> > +#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
> > +#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
> > +#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MAX_PITCH_ISP (32704U)
> > +#define HWD_VIIF_MAX_PITCH (65536U)
> > +
> > +/* size of minimum/maximum input image */
> > +#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
> > +#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
> > +#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
> > +
> > +/* size of minimum/maximum output image */
> > +#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> > +
> > +#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> > +
> > +#define HWD_VIIF_NO_EVENT (0x0U)
> > +
> > +/* System clock: [kHz] */
> > +#define HWD_VIIF_SYS_CLK (500000UL)
> > +
> > +/*
> > + * wait time for force abort to complete(max 1line time = 1228.8[us]
> > + * when width = 4096, RAW24, 80Mbps
> > + */
> > +#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
> > +
> > +/*
> > + * complete time of register buffer transfer.
> > + * actual time is about 30us in case of L1ISP
> > + */
> > +#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
> > +
> > +/* internal operation latencies: [system clock]*/
> > +#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
> > +#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
> > +
> > +/* offset of Vsync delay: [line] */
> > +#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
> > +#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
> > +
> > +/* data width is 32bit */
> > +#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
> > +
> > +/* vsync mode is pulse */
> > +#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
> > +
> > +/* Vlatch mask bit for L1ISP and L2ISP */
> > +#define HWD_VIIF_ISP_VLATCH_MASK (2U)
> > +
> > +/* Register buffer */
> > +#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
> > +#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
> > +#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
> > +#define HWD_VIIF_ISP_REGBUF_READ (1U)
> > +
> > +/* constants for L1 ISP*/
> > +#define HWD_VIIF_L1_INPUT_MODE_NUM (5U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_MIN (8U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_MAX (24U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_SDR_MAX
> (12U)
> > +#define HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX
> (14U)
> > +#define HWD_VIIF_L1_RAW_MODE_NUM (4U)
> > +#define HWD_VIIF_L1_INPUT_NUM_MIN (1U)
> > +#define HWD_VIIF_L1_INPUT_NUM_MAX (3U)
> > +#define HWD_VIIF_L1_AG_ID_NUM (4U)
> > +#define HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM (3U)
> > +#define HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL (0x3fffU)
> > +#define HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL (0xffffffU)
> > +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL (0xffffffU)
> > +#define HWD_VIIF_L1_OBCC_MAX_AG_VAL (511U)
> > +#define HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL
> (0xffffffU)
> > +#define HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL (1023U)
> > +#define HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL (1U)
> > +#define HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL (31U)
> > +#define HWD_VIIF_L1_VDM_ALIGN (0x8U) /*
> port interface width is 64bit */
> > +#define HWD_VIIF_L1_VDM_CFG_PARAM
> (0x00000310U) /* data width is 64bit */
> > +#define HWD_VIIF_L1_VDM_SRAM_BASE
> (0x00000600U)
> > +#define HWD_VIIF_L1_VDM_SRAM_SIZE
> (0x00000020U)
> > +#define HWD_VIIF_L1_VDM_DPC_TABLE_SIZE
> (0x2000U)
> > +#define HWD_VIIF_L1_VDM_LSC_TABLE_SIZE
> (0x600U)
> > +#define HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL (4095U)
> > +#define HWD_VIIF_L1_PWHB_MAX_GAIN_VAL
> (0x80000U)
> > +#define HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL
> (63U)
> > +#define HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL
> (31U)
> > +#define HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL (3U)
> > +#define HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL (256U)
> > +#define HWD_VIIF_L1_RCNR_MAX_BLEND_VAL
> (16U)
> > +#define HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL
> (64U)
> > +#define HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL (4U)
> > +#define HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL
> (16U)
> > +#define HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL
> (32U)
> > +#define HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL
> (2U)
> > +#define HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO
> (15U)
> > +#define HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO (0x400U)
> > +#define HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL (0xffffffU)
> > +#define HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL (4095U)
> > +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL
> (0xffffffU)
> > +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL
> (0x100000U)
> > +#define HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL
> (0xffffffU)
> > +#define HWD_VIIF_LSC_MIN_GAIN (-4096)
> > +#define HWD_VIIF_LSC_MAX_GAIN (4096)
> > +#define HWD_VIIF_LSC_GRID_MIN_COORDINATE (1U)
> > +#define HWD_VIIF_LSC_PWB_MAX_COEF_VAL
> (0x800U)
> > +#define HWD_VIIF_DAMP_MAX_LSBSEL (15U)
> > +#define HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL
> (0xffffffU)
> > +#define HWD_VIIF_AWB_MIN_GAIN (64U)
> > +#define HWD_VIIF_AWB_MAX_GAIN (1024U)
> > +#define HWD_VIIF_AWB_GATE_LOWER
> (-127)
> > +#define HWD_VIIF_AWB_GATE_UPPER
> (127)
> > +#define HWD_VIIF_AWB_UNSIGNED_GATE_UPPER (127U)
> > +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED
> (15U)
> > +#define HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL
> (31U)
> > +#define HWD_VIIF_AWB_INTEGRATION_STOP_TH (1023U)
> > +#define HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL
> (8U)
> > +#define HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH
> (10U)
> > +#define HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH
> (24U)
> > +#define HWD_VIIF_L1_HDRC_MAX_PT_SLOPE
> (13U)
> > +#define HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO (256U)
> > +#define HWD_VIIF_L1_HDRC_MAX_FLARE_VAL
> (0xffffffU)
> > +#define HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA
> (16U)
> > +#define HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO
> (0x400000U)
> > +#define HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION
> (0x4000U)
> > +#define HWD_VIIF_L1_HDRC_RATIO_OFFSET
> (10U)
> > +#define HWD_VIIF_L1_GAMMA_MAX_VAL (8191U)
> > +#define HWD_VIIF_L1_SUPPRESSION_MAX_VAL
> (0x4000U)
> > +#define HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT
> (15U)
> > +#define HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN (0x1000U)
> > +#define HWD_VIIF_L1_AEXP_MAX_WEIGHT (3U)
> > +#define HWD_VIIF_L1_AEXP_MAX_BLOCK_TH
> (256U)
> > +#define HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH (0xffffffU)
> > +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH (64U)
> > +#define HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT (64U)
> > +#define HWD_VIIF_L1_HIST_COLOR_RGBY (2U)
> > +#define HWD_VIIF_L1_HIST_MAX_BLOCK_NUM
> (8U)
> > +#define HWD_VIIF_L1_HIST_MAX_STEP (15U)
> > +#define HWD_VIIF_L1_HIST_MAX_BIN_SHIFT
> (31U)
> > +#define HWD_VIIF_L1_HIST_MAX_COEF (65536U)
> > +#define HWD_VIIF_L1_HIST_MIN_ADD_B_COEF
> (-65536)
> > +#define HWD_VIIF_L1_HIST_MIN_ADD_A_COEF
> (-16777216)
> > +#define HWD_VIIF_L1_HIST_MAX_ADD_A_COEF
> (16777216)
> > +#define HWD_VIIF_L1_HIST_VDM_SIZE (4096U)
> > +#define HWD_VIIF_L1_HIST_VDM_SRAM_BASE
> (0x00000400U)
> > +#define HWD_VIIF_L1_HIST_VDM_SRAM_SIZE
> (0x00000040U)
> > +#define HWD_VIIF_L1_CRGBF_R_START_ADDR_LIMIT
> (0x0200U)
> > +#define HWD_VIIF_L1_CRGBF_R_END_ADDR_LIMIT (0x10BFU)
> > +#define HWD_VIIF_L1_COEF_MIN (256U)
> > +#define HWD_VIIF_L1_COEF_MAX (65024U)
> > +
> > +/* constants for L2 ISP */
> > +#define HWD_VIIF_L2_VDM_ALIGN (0x4U)
> > +#define HWD_VIIF_L2_VDM_GRID_SRAM_BASE
> (0x00000620U)
> > +#define HWD_VIIF_L2_VDM_GRID_SRAM_SIZE
> (0x00000020U)
> > +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_BASE
> (0x00000640U)
> > +#define HWD_VIIF_L2_VDM_GAMMA_SRAM_SIZE
> (0x00000020U)
> > +#define HWD_VIIF_L2_VDM_GAMMA_TABLE_SIZE (0x00000200U)
> > +#define HWD_VIIF_L2_UNDIST_POLY_NUM (11U)
> > +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_H (-4296)
> > +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_H (4296)
> > +#define HWD_VIIF_L2_UNDIST_MIN_SENSOR_CROP_OFS_V (-2360)
> > +#define HWD_VIIF_L2_UNDIST_MAX_SENSOR_CROP_OFS_V (2360)
> > +#define HWD_VIIF_L2_UNDIST_MAX_NORM_SCALE (1677721U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_VALID_R_NORM2
> (0x4000000U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_ROI_WRITE_AREA_DELTA
> (0x800U)
> > +#define HWD_VIIF_L2_UNDIST_MIN_POLY_COEF (-2147352576)
> > +#define HWD_VIIF_L2_UNDIST_MAX_POLY_COEF (2147352576)
> > +#define HWD_VIIF_L2_UNDIST_MIN_GRID_NUM (16U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_GRID_NUM (64U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_GRID_TOTAL_NUM
> (2048U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_GRID_PATCH_SIZE_INV
> (0x800000U)
> > +#define HWD_VIIF_L2_UNDIST_MIN_TABLE_SIZE (0x400U)
> > +#define HWD_VIIF_L2_UNDIST_MAX_TABLE_SIZE (0x2000U)
> > +#define HWD_VIIF_L2_ROI_MIN_NUM (1U)
> > +#define HWD_VIIF_L2_ROI_MAX_NUM (2U)
> > +#define HWD_VIIF_L2_ROI_MIN_SCALE (32768U)
> > +#define HWD_VIIF_L2_ROI_MAX_SCALE (131072U)
> > +#define HWD_VIIF_L2_ROI_MIN_SCALE_INV (32768U)
> > +#define HWD_VIIF_L2_ROI_MAX_SCALE_INV (131072U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_HSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_HSIZE
> (8190U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_WO_SCALE_VSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_WO_SCALE_VSIZE (4094U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_HSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_HSIZE (8190U)
> > +#define HWD_VIIF_L2_ROI_MIN_CORRECTED_VSIZE (128U)
> > +#define HWD_VIIF_L2_ROI_MAX_CORRECTED_VSIZE (4094U)
> > +#define HWD_VIIF_L2_CRGBF_R_START_ADDR_LIMIT
> (0x1CU)
> > +#define HWD_VIIF_L2_CRGBF_R_END_ADDR_LIMIT (0x1FU)
> > +#define HWD_VIIF_L2_ROI_NONE (3U)
> > +#define HWD_VIIF_MAX_POST_NUM (2U)
> > +#define HWD_VIIF_L2_INPUT_OTHER_CH (0x50U)
> > +
> > +/**
> > + * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
> > + *
> > + * @roi_num: the number of ROIs which are used.
> > + * @post_enable_flag: flag to show which of POST is enabled.
> > + * @post_crop_x: CROP x of each L2ISP POST
> > + * @post_crop_y: CROP y of each L2ISP POST
> > + * @post_crop_w: CROP w of each L2ISP POST
> > + * @post_crop_h: CROP h of each L2ISP POST
> > + */
> > +struct hwd_viif_l2_roi_path_info {
> > + u32 roi_num;
> > + bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_res - driver internal resource structure
> > + *
> > + * @clock_id: clock ID of each unit
> > + * @csi2_clock_id: clock ID of CSI-2 RX
> > + * @csi2_reset_id: reset ID of CSI-2 RX
> > + * @pixel_clock: pixel clock
> > + * @htotal_size: horizontal total size
> > + * @dt_image_main_w_isp: Data type of image data for ISP path
> > + * @csi2host_reg: pointer to register access structure of CSI-2 RX host
> controller
> > + * @capture_reg: pointer to register access structure of capture unit
> > + * @l2_roi_path_info: ROI path information of L2ISP
> > + * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
> > + */
> > +struct hwd_viif_res {
> > + //u32 clock_id;
> > + //u32 csi2_clock_id;
> > + //u32 csi2_reset_id;
>
> Please remove these if they're not needed.
I'll remove them.
> > + u32 pixel_clock;
> > + u32 htotal_size;
> > + u32 dt_image_main_w_isp;
> > + struct hwd_viif_csi2host_reg *csi2host_reg;
> > + struct hwd_viif_capture_reg *capture_reg;
> > + struct hwd_viif_l2_roi_path_info l2_roi_path_info;
> > + bool run_flag_main;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_dphy_hs_info - dphy hs information
> > + *
> > + * @rate: Data rate [Mbps]
> > + * @hsfreqrange: IP operating frequency(hsfreqrange)
> > + * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
> > + */
> > +struct hwd_viif_dphy_hs_info {
> > + u32 rate;
> > + u32 hsfreqrange;
> > + u32 osc_freq_target;
> > +};
> > +
> > +#endif /* HWD_VIIF_INTERNAL_H */
> > diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h
> b/drivers/media/platform/visconti/hwd_viif_reg.h
> > new file mode 100644
> > index 00000000000..b7f43c5fe95
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_reg.h
> > @@ -0,0 +1,2802 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_REG_H
> > +#define HWD_VIIF_REG_H
> > +
> > +/**
> > + * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST control
> > + */
> > +struct hwd_viif_csi2host_reg {
> > + u32 RESERVED_A_1;
> > + u32 CSI2RX_NLANES;
> > + u32 CSI2RX_RESETN;
> > + u32 CSI2RX_INT_ST_MAIN;
> > + u32 CSI2RX_DATA_IDS_1;
> > + u32 CSI2RX_DATA_IDS_2;
> > + u32 RESERVED_B_1[10];
> > + u32 CSI2RX_PHY_SHUTDOWNZ;
> > + u32 CSI2RX_PHY_RSTZ;
> > + u32 CSI2RX_PHY_RX;
> > + u32 CSI2RX_PHY_STOPSTATE;
> > + u32 CSI2RX_PHY_TESTCTRL0;
> > + u32 CSI2RX_PHY_TESTCTRL1;
> > + u32 RESERVED_B_2[34];
> > + u32 CSI2RX_INT_ST_PHY_FATAL;
> > + u32 CSI2RX_INT_MSK_PHY_FATAL;
> > + u32 CSI2RX_INT_FORCE_PHY_FATAL;
> > + u32 RESERVED_B_3[1];
> > + u32 CSI2RX_INT_ST_PKT_FATAL;
> > + u32 CSI2RX_INT_MSK_PKT_FATAL;
> > + u32 CSI2RX_INT_FORCE_PKT_FATAL;
> > + u32 RESERVED_B_4[1];
> > + u32 CSI2RX_INT_ST_FRAME_FATAL;
> > + u32 CSI2RX_INT_MSK_FRAME_FATAL;
> > + u32 CSI2RX_INT_FORCE_FRAME_FATAL;
> > + u32 RESERVED_B_5[1];
> > + u32 CSI2RX_INT_ST_PHY;
> > + u32 CSI2RX_INT_MSK_PHY;
> > + u32 CSI2RX_INT_FORCE_PHY;
> > + u32 RESERVED_B_6[1];
> > + u32 CSI2RX_INT_ST_PKT;
> > + u32 CSI2RX_INT_MSK_PKT;
> > + u32 CSI2RX_INT_FORCE_PKT;
> > + u32 RESERVED_B_7[1];
> > + u32 CSI2RX_INT_ST_LINE;
> > + u32 CSI2RX_INT_MSK_LINE;
> > + u32 CSI2RX_INT_FORCE_LINE;
> > + u32 RESERVED_B_8[113];
> > + u32 RESERVED_A_2;
> > + u32 RESERVED_A_3;
> > + u32 RESERVED_A_4;
> > + u32 RESERVED_A_5;
> > + u32 RESERVED_A_6;
> > + u32 RESERVED_B_9[58];
> > + u32 RESERVED_A_7;
>
> These should be lower case, they're struct members.
>
> This way of defining a hardware register interface is highly
> unconventional. I'm not saying no to it, not now at least, but something
> should be done to make this more robust against accidental changes: adding
> a field in the middle changes the address of anything that comes after it,
> and it's really difficult to say from the code alone that the address of a
> given register is what it's intended to be. Maybe pahole would still help?
> But some documentation would be needed in that case.
>
> I wonder what others think.
I understand the risk.
I'll remove these struct-style definition and introduce macro style definition.
I've hesitated this migration simply because it seemed difficult to complete without any defects
especially on calculating the offset of each member.
I try find a series of operations that will complete the migration safely.
> > +};
> > +
snip
>
> --
> Kind regards,
>
> Sakari Ailus
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-02-01 2:02 ` yuji2.ishikawa
@ 2023-02-01 9:41 ` Laurent Pinchart
2023-02-01 11:22 ` yuji2.ishikawa
0 siblings, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-02-01 9:41 UTC (permalink / raw)
To: yuji2.ishikawa
Cc: sakari.ailus, hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Ishikawa-san,
On Wed, Feb 01, 2023 at 02:02:43AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> Hello Sakari,
>
> Sorry for sending the reply again.
> My mail agent posted the previous one with HTML format.
>
> Thank you for reviewing and your comments.
>
> > -----Original Message-----
> > From: Sakari Ailus sakari.ailus@iki.fi
> > Sent: Wednesday, January 18, 2023 7:40 AM
> > To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> > yuji2.ishikawa@toshiba.co.jp
> > Cc: Hans Verkuil hverkuil@xs4all.nl; Laurent Pinchart
> > laurent.pinchart@ideasonboard.com; Mauro Carvalho Chehab
> > mchehab@kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> > nobuhiro1.iwamatsu@toshiba.co.jp; Rob Herring robh+dt@kernel.org;
> > Krzysztof Kozlowski krzysztof.kozlowski+dt@linaro.org; Rafael J . Wysocki
> > rafael.j.wysocki@intel.com; Mark Brown broonie@kernel.org;
> > linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> > Subject: Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti
> > Video Input Interface driver
[snip]
> > > diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h b/drivers/media/platform/visconti/hwd_viif_reg.h
> > > new file mode 100644
> > > index 00000000000..b7f43c5fe95
> > > --- /dev/null
> > > +++ b/drivers/media/platform/visconti/hwd_viif_reg.h
> > > @@ -0,0 +1,2802 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > > +/* Toshiba Visconti Video Capture Support
> > > + *
> > > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > > + */
> > > +
> > > +#ifndef HWD_VIIF_REG_H
> > > +#define HWD_VIIF_REG_H
> > > +
> > > +/**
> > > + * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST control
> > > + */
> > > +struct hwd_viif_csi2host_reg {
> > > + u32 RESERVED_A_1;
> > > + u32 CSI2RX_NLANES;
> > > + u32 CSI2RX_RESETN;
> > > + u32 CSI2RX_INT_ST_MAIN;
> > > + u32 CSI2RX_DATA_IDS_1;
> > > + u32 CSI2RX_DATA_IDS_2;
> > > + u32 RESERVED_B_1[10];
> > > + u32 CSI2RX_PHY_SHUTDOWNZ;
> > > + u32 CSI2RX_PHY_RSTZ;
> > > + u32 CSI2RX_PHY_RX;
> > > + u32 CSI2RX_PHY_STOPSTATE;
> > > + u32 CSI2RX_PHY_TESTCTRL0;
> > > + u32 CSI2RX_PHY_TESTCTRL1;
> > > + u32 RESERVED_B_2[34];
> > > + u32 CSI2RX_INT_ST_PHY_FATAL;
> > > + u32 CSI2RX_INT_MSK_PHY_FATAL;
> > > + u32 CSI2RX_INT_FORCE_PHY_FATAL;
> > > + u32 RESERVED_B_3[1];
> > > + u32 CSI2RX_INT_ST_PKT_FATAL;
> > > + u32 CSI2RX_INT_MSK_PKT_FATAL;
> > > + u32 CSI2RX_INT_FORCE_PKT_FATAL;
> > > + u32 RESERVED_B_4[1];
> > > + u32 CSI2RX_INT_ST_FRAME_FATAL;
> > > + u32 CSI2RX_INT_MSK_FRAME_FATAL;
> > > + u32 CSI2RX_INT_FORCE_FRAME_FATAL;
> > > + u32 RESERVED_B_5[1];
> > > + u32 CSI2RX_INT_ST_PHY;
> > > + u32 CSI2RX_INT_MSK_PHY;
> > > + u32 CSI2RX_INT_FORCE_PHY;
> > > + u32 RESERVED_B_6[1];
> > > + u32 CSI2RX_INT_ST_PKT;
> > > + u32 CSI2RX_INT_MSK_PKT;
> > > + u32 CSI2RX_INT_FORCE_PKT;
> > > + u32 RESERVED_B_7[1];
> > > + u32 CSI2RX_INT_ST_LINE;
> > > + u32 CSI2RX_INT_MSK_LINE;
> > > + u32 CSI2RX_INT_FORCE_LINE;
> > > + u32 RESERVED_B_8[113];
> > > + u32 RESERVED_A_2;
> > > + u32 RESERVED_A_3;
> > > + u32 RESERVED_A_4;
> > > + u32 RESERVED_A_5;
> > > + u32 RESERVED_A_6;
> > > + u32 RESERVED_B_9[58];
> > > + u32 RESERVED_A_7;
> >
> > These should be lower case, they're struct members.
> >
> > This way of defining a hardware register interface is highly
> > unconventional. I'm not saying no to it, not now at least, but something
> > should be done to make this more robust against accidental changes: adding
> > a field in the middle changes the address of anything that comes after it,
> > and it's really difficult to say from the code alone that the address of a
> > given register is what it's intended to be. Maybe pahole would still help?
> > But some documentation would be needed in that case.
> >
> > I wonder what others think.
>
> I understand the risk.
> I'll remove these struct-style definition and introduce macro style definition.
> I've hesitated this migration simply because it seemed difficult to complete without any defects
> especially on calculating the offset of each member.
> I try find a series of operations that will complete the migration safely.
I agree with you about the migration risk. Maybe a script that parses
the header file and generates macros would take less time to implement
than doing it manually, and would be safer ?
> > > +};
> > > +
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-02-01 9:41 ` Laurent Pinchart
@ 2023-02-01 11:22 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-01 11:22 UTC (permalink / raw)
To: laurent.pinchart
Cc: sakari.ailus, hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Laurent,
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Wednesday, February 1, 2023 6:42 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>
> Cc: sakari.ailus@iki.fi; hverkuil@xs4all.nl; mchehab@kernel.org; iwamatsu
> nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> rafael.j.wysocki@intel.com; broonie@kernel.org; linux-media@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver
>
> Hello Ishikawa-san,
>
> On Wed, Feb 01, 2023 at 02:02:43AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> > Hello Sakari,
> >
> > Sorry for sending the reply again.
> > My mail agent posted the previous one with HTML format.
> >
> > Thank you for reviewing and your comments.
> >
> > > -----Original Message-----
> > > From: Sakari Ailus sakari.ailus@iki.fi
> > > Sent: Wednesday, January 18, 2023 7:40 AM
> > > To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> > > yuji2.ishikawa@toshiba.co.jp
> > > Cc: Hans Verkuil hverkuil@xs4all.nl; Laurent Pinchart
> > > laurent.pinchart@ideasonboard.com; Mauro Carvalho Chehab
> > > mchehab@kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> > > nobuhiro1.iwamatsu@toshiba.co.jp; Rob Herring robh+dt@kernel.org;
> > > Krzysztof Kozlowski krzysztof.kozlowski+dt@linaro.org; Rafael J .
> > > Wysocki rafael.j.wysocki@intel.com; Mark Brown broonie@kernel.org;
> > > linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> > > Subject: Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba
> > > Visconti Video Input Interface driver
>
> [snip]
>
> > > > diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h
> > > > b/drivers/media/platform/visconti/hwd_viif_reg.h
> > > > new file mode 100644
> > > > index 00000000000..b7f43c5fe95
> > > > --- /dev/null
> > > > +++ b/drivers/media/platform/visconti/hwd_viif_reg.h
> > > > @@ -0,0 +1,2802 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > > > +/* Toshiba Visconti Video Capture Support
> > > > + *
> > > > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > > > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage
> > > > +Corporation */
> > > > +
> > > > +#ifndef HWD_VIIF_REG_H
> > > > +#define HWD_VIIF_REG_H
> > > > +
> > > > +/**
> > > > + * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST
> > > > +control */ struct hwd_viif_csi2host_reg {
> > > > + u32 RESERVED_A_1;
> > > > + u32 CSI2RX_NLANES;
> > > > + u32 CSI2RX_RESETN;
> > > > + u32 CSI2RX_INT_ST_MAIN;
> > > > + u32 CSI2RX_DATA_IDS_1;
> > > > + u32 CSI2RX_DATA_IDS_2;
> > > > + u32 RESERVED_B_1[10];
> > > > + u32 CSI2RX_PHY_SHUTDOWNZ;
> > > > + u32 CSI2RX_PHY_RSTZ;
> > > > + u32 CSI2RX_PHY_RX;
> > > > + u32 CSI2RX_PHY_STOPSTATE;
> > > > + u32 CSI2RX_PHY_TESTCTRL0;
> > > > + u32 CSI2RX_PHY_TESTCTRL1;
> > > > + u32 RESERVED_B_2[34];
> > > > + u32 CSI2RX_INT_ST_PHY_FATAL;
> > > > + u32 CSI2RX_INT_MSK_PHY_FATAL;
> > > > + u32 CSI2RX_INT_FORCE_PHY_FATAL;
> > > > + u32 RESERVED_B_3[1];
> > > > + u32 CSI2RX_INT_ST_PKT_FATAL;
> > > > + u32 CSI2RX_INT_MSK_PKT_FATAL;
> > > > + u32 CSI2RX_INT_FORCE_PKT_FATAL;
> > > > + u32 RESERVED_B_4[1];
> > > > + u32 CSI2RX_INT_ST_FRAME_FATAL;
> > > > + u32 CSI2RX_INT_MSK_FRAME_FATAL;
> > > > + u32 CSI2RX_INT_FORCE_FRAME_FATAL;
> > > > + u32 RESERVED_B_5[1];
> > > > + u32 CSI2RX_INT_ST_PHY;
> > > > + u32 CSI2RX_INT_MSK_PHY;
> > > > + u32 CSI2RX_INT_FORCE_PHY;
> > > > + u32 RESERVED_B_6[1];
> > > > + u32 CSI2RX_INT_ST_PKT;
> > > > + u32 CSI2RX_INT_MSK_PKT;
> > > > + u32 CSI2RX_INT_FORCE_PKT;
> > > > + u32 RESERVED_B_7[1];
> > > > + u32 CSI2RX_INT_ST_LINE;
> > > > + u32 CSI2RX_INT_MSK_LINE;
> > > > + u32 CSI2RX_INT_FORCE_LINE;
> > > > + u32 RESERVED_B_8[113];
> > > > + u32 RESERVED_A_2;
> > > > + u32 RESERVED_A_3;
> > > > + u32 RESERVED_A_4;
> > > > + u32 RESERVED_A_5;
> > > > + u32 RESERVED_A_6;
> > > > + u32 RESERVED_B_9[58];
> > > > + u32 RESERVED_A_7;
> > >
> > > These should be lower case, they're struct members.
> > >
> > > This way of defining a hardware register interface is highly
> > > unconventional. I'm not saying no to it, not now at least, but
> > > something should be done to make this more robust against accidental
> > > changes: adding a field in the middle changes the address of
> > > anything that comes after it, and it's really difficult to say from
> > > the code alone that the address of a given register is what it's intended to be.
> Maybe pahole would still help?
> > > But some documentation would be needed in that case.
> > >
> > > I wonder what others think.
> >
> > I understand the risk.
> > I'll remove these struct-style definition and introduce macro style definition.
> > I've hesitated this migration simply because it seemed difficult to
> > complete without any defects especially on calculating the offset of each
> member.
> > I try find a series of operations that will complete the migration safely.
>
> I agree with you about the migration risk. Maybe a script that parses the header
> file and generates macros would take less time to implement than doing it
> manually, and would be safer ?
Thank you for the advice.
I'm also thinking about generating macro definitions from headers.
The pahole tool might help me checking if the generated macros are correct.
> > > > +};
> > > > +
>
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
` (3 preceding siblings ...)
2023-01-17 22:39 ` Sakari Ailus
@ 2023-01-18 0:52 ` Laurent Pinchart
2023-02-02 4:37 ` yuji2.ishikawa
4 siblings, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-18 0:52 UTC (permalink / raw)
To: Yuji Ishikawa
Cc: Hans Verkuil, Mauro Carvalho Chehab, Nobuhiro Iwamatsu,
Rob Herring, Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown,
linux-media, linux-arm-kernel, linux-kernel, devicetree
Hi Yuji,
Thank you for the patch.
I'll comment on the high-level design first (with a few ad-hoc more
detailed comments here and there).
On Wed, Jan 11, 2023 at 11:24:29AM +0900, Yuji Ishikawa wrote:
> Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> The interface device includes CSI2 Receiver,
> frame grabber, video DMAC and image signal processor.
> This patch provides operations to handle registers of HW listed above.
>
> The Video DMACs have 32bit address space
> and currently corresponding IOMMU driver is not provided.
> Therefore, memory-block address for captured image is 32bit IOVA
> which is equal to 32bit-truncated phisical address.
> When the Visconti IOMMU driver (currently under development) is accepted,
> the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> ---
> Changelog v2:
> - Resend v1 because a patch exceeds size limit.
>
> Changelog v3:
> - Adapted to media control framework
> - Introduced ISP subdevice, capture device
> - Remove private IOCTLs and add vendor specific V4L2 controls
> - Change function name avoiding camelcase and uppercase letters
>
> Changelog v4:
> - Split patches because the v3 patch exceeds size limit
> - Stop using ID number to identify driver instance:
> - Use dynamically allocated structure to hold driver's context,
> instead of static one indexed by ID number.
> - Functions accept driver's context structure instead of ID number.
>
> Changelog v5:
> - no change
> ---
> drivers/media/platform/Kconfig | 1 +
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/visconti/Kconfig | 9 +
> drivers/media/platform/visconti/Makefile | 8 +
> drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
> drivers/media/platform/visconti/hwd_viif.h | 710 +++++
> .../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
> .../platform/visconti/hwd_viif_internal.h | 340 ++
> .../media/platform/visconti/hwd_viif_reg.h | 2802 +++++++++++++++++
> include/uapi/linux/visconti_viif.h | 1724 ++++++++++
> 10 files changed, 7895 insertions(+)
> create mode 100644 drivers/media/platform/visconti/Kconfig
> create mode 100644 drivers/media/platform/visconti/Makefile
> create mode 100644 drivers/media/platform/visconti/hwd_viif.c
> create mode 100644 drivers/media/platform/visconti/hwd_viif.h
> create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
> create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
> create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
> create mode 100644 include/uapi/linux/visconti_viif.h
This file split makes it quite hard to navigate and understand the
driver for people who are not familiar with it (at least for me) :-S It
would be nice to split the driver based on functional area, for instance
as follows:
- viif.c (or viif_drv.c): Top-level driver file, as already done in v5
- viif_csi2rx.c: CSI-2 receiver support code
- viif_l1isp.c: L1 ISP support
- viif_l2isp.c: L2 ISP support
- viif_capture.c: V4L2 video node support
Each of those files should have a corresponding header file to declare
functions and define the related macros and structures that are used by
*other* .c files. Macros and structures that are internal to a .c file
should be defined there.
- viif_reg.h: Register addresses and macros
I'm tempted to split the CSI-2 RX registers from viif_reg.h to
viif_csi2rx_reg.h.
As for the code currently stored in the hwd_*.c files, it could be kept
separate, or be integrated in the corresponding *.c file, up to you. If
you prefer keeping it separate, I would name the files viif_*_hw.c (e.g.
viif_csi2rx_hw.c).
I'll cut parts of the original part out of the reply, as the result
would be too large for the mailing list.
[snip]
> # Please place here only ancillary drivers that aren't SoC-specific
> diff --git a/drivers/media/platform/visconti/Kconfig b/drivers/media/platform/visconti/Kconfig
> new file mode 100644
> index 00000000000..031e4610809
> --- /dev/null
> +++ b/drivers/media/platform/visconti/Kconfig
> @@ -0,0 +1,9 @@
Please add an SPDX header.
> +config VIDEO_VISCONTI_VIIF
> + tristate "Visconti Camera Interface driver"
> + depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER && VIDEO_DEV
> + depends on ARCH_VISCONTI
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_FWNODE
You also need V4L2_ASYNC and VIDEO_V4L2_SUBDEV_API. Sort them
alphabetically:
select V4L2_ASYNC
select V4L2_FWNODE
select VIDEOBUF2_DMA_CONTIG
select VIDEO_V4L2_SUBDEV_API
> + help
> + This is V4L2 driver for Toshiba Visconti Camera Interface driver
> +
[snip]
> diff --git a/drivers/media/platform/visconti/hwd_viif.c b/drivers/media/platform/visconti/hwd_viif.c
> new file mode 100644
> index 00000000000..260293fa4d0
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif.c
> @@ -0,0 +1,1690 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +#include "hwd_viif.h"
> +#include "hwd_viif_internal.h"
> +
> +/* MIPI CSI2 DataType definition */
> +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
You can drop this and replace it with the macros defined in
include/media/mipi-csi2.h.
> +
> +struct hwd_viif_res *allocate_viif_res(struct device *dev, void *csi2host_vaddr,
> + void *capture_vaddr)
> +{
> + struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res), GFP_KERNEL);
Don't allocate this dynamically, it can be embedded in the viif_device
structure.
> +
> + res->csi2host_reg = csi2host_vaddr;
> + res->capture_reg = capture_vaddr;
> + res->run_flag_main = (bool)false;
> + return res;
> +}
[snip]
> +#define VDM_BIT_W00 BIT(0)
> +#define VDM_BIT_W01 BIT(1)
> +#define VDM_BIT_W02 BIT(2)
> +#define VDM_BIT_W03 BIT(3)
> +#define VDM_BIT_W04 BIT(4)
> +#define VDM_BIT_W05 BIT(5)
> +#define VDM_BIT_R00 BIT(0)
> +#define VDM_BIT_R01 BIT(1)
> +#define VDM_BIT_R02 BIT(2)
> +
> +#define VDM_ABORT_MASK_SUB_W (VDM_BIT_W03 | VDM_BIT_W04 | VDM_BIT_W05)
> +#define VDM_ABORT_MASK_MAIN_W (VDM_BIT_W00 | VDM_BIT_W01 | VDM_BIT_W02)
> +#define VDM_ABORT_MASK_MAIN_R (VDM_BIT_R00 | VDM_BIT_R01 | VDM_BIT_R02)
None of these are used.
> +/**
> + * hwd_viif_l2_set_img_transmission() - Set image transfer condition of L2ISP
> + *
> + * @post_id: POST ID [0..1]
> + * @enable: or disable image transfer of MAIN unit. For more refer @ref hwd_viif_enable_flag.
> + * @src: Pointer to crop area information
> + * @out_process: Pointer to output process information
> + * @img: Pointer to output image information
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "post_id" or "enable" is out of range
> + * - [2] "src" or "out_process" is NULL when "enable" is HWD_VIIF_ENABLE
> + * - [3] "src" or "out_process" is not NULL when "enable" is HWD_VIIF_DISABLE
> + * - [4] Member of "src" is out of range
> + * - [5] "w" of "src" is not equal to 2 * "width" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> + * - [6] "h" of "src" is not equal to 2 * "height" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> + * - [7] "w" of "src" is not equal to "width" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> + * - [8] "h" of "src" is not equal to "height" of "image"
> + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> + * - [9] Member of "out_process" is invalid
> + * - [10] "alpha" of "out_process" is not 0 when "format" of "img" is not HWD_VIIF_ARGB8888_PACKED
> + * - [11] "format" of "img" is not HWD_VIIF_ONE_COLOR_8 or HWD_VIIF_ONE_COLOR_16
> + * when "select_color" of "out_process"
> + * is HWD_VIIF_COLOR_Y_G, HWD_VIIF_COLOR_U_B or HWD_VIIF_COLOR_V_R
> + * - [12] Member of "img" is invalid
> + *
> + * see also: #hwd_viif_l2_set_roi_path
> + */
> +s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id, u32 enable,
> + const struct hwd_viif_img_area *src,
> + const struct hwd_viif_out_process *out_process,
> + const struct hwd_viif_img *img)
> +{
> + u32 pitch[HWD_VIIF_MAX_PLANE_NUM], img_start_addr[HWD_VIIF_MAX_PLANE_NUM];
> + u32 i, val, loop, k, r[HWD_VIIF_MAX_PLANE_NUM];
> + s32 ret = 0;
> +
> + /* pitch alignment for planar or one color format */
> + u32 pitch_align = 128U;
[snip]
> + /* build DMAC parameter */
> + switch (img->format) {
> + case HWD_VIIF_YCBCR422_8_PACKED:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 2U;
> + r[0] = 1U;
> + pitch_align = 256U;
> + break;
> + case HWD_VIIF_RGB888_PACKED:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 3U;
> + r[0] = 1U;
> + pitch_align = 384U;
> + break;
> + case HWD_VIIF_ARGB8888_PACKED:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 4U;
> + r[0] = 1U;
> + pitch_align = 512U;
> + break;
> + case HWD_VIIF_ONE_COLOR_8:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 1U;
> + r[0] = 1U;
> + break;
> + case HWD_VIIF_ONE_COLOR_16:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + loop = 1U;
> + k = 2U;
> + r[0] = 1U;
> + break;
> + case HWD_VIIF_YCBCR422_8_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 1U;
> + r[0] = 1U;
> + r[1] = 2U;
> + r[2] = 2U;
> + break;
> + case HWD_VIIF_RGB888_YCBCR444_8_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 1U;
> + r[0] = 1U;
> + r[1] = 1U;
> + r[2] = 1U;
> + break;
> + case HWD_VIIF_YCBCR422_16_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 2U;
> + r[0] = 1U;
> + r[1] = 2U;
> + r[2] = 2U;
> + break;
> + case HWD_VIIF_RGB161616_YCBCR444_16_PLANAR:
> + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> + pitch[0] = img->pixelmap[0].pitch;
> + pitch[1] = img->pixelmap[1].pitch;
> + pitch[2] = img->pixelmap[2].pitch;
> + loop = HWD_VIIF_MAX_PLANE_NUM;
> + k = 2U;
> + r[0] = 1U;
> + r[1] = 1U;
> + r[2] = 1U;
> + break;
> + default:
> + return -EINVAL;
> + }
This is lots of code that could be replaced with static data. Create
struct viif_format_info {
u32 format;
unsigned int num_planes;
unsigned int bpp;
/* whatever other fields are needed */
};
in viif.h, and add to viif.c a static table of those
static const struct viif_format_info viif_formats[] = {
{
.format = HWD_VIIF_YCBCR422_8_PACKED,
.num_planes = 1
.bpp = 2,
}, {
...
},
};
with a lookup function
const struct viif_format_info viif_format_info(u32 format)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(viif_formats); ++i) {
if (viif_formats[i].format == format)
return &viif_formats[i];
}
return NULL;
}
You can then use this wherever you need per-format information through
the driver. I suspect it will be useful to store other per-format
information, such as the V4L2 pixel format for instance.
Now that I wrote this, it seems you already have such a structure called
viif_fmt in a subsequent patch, with a static array. Move them to viif.c
and viif.h, extend the structure with the hardware format, are use it
through the driver.
> +
> + for (i = 0; i < loop; i++) {
> + val = max(((img->width * k) / r[i]), 128U);
> + if (pitch[i] < val || pitch[i] > HWD_VIIF_MAX_PITCH_ISP ||
> + ((pitch[i] % pitch_align) != 0U) || ((img_start_addr[i] % 4U) != 0U)) {
> + return -EINVAL;
> + }
> + }
> +
> + writel(img_start_addr[0], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_G);
> + writel(pitch[0], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_G);
> + if (loop == HWD_VIIF_MAX_PLANE_NUM) {
> + writel(img_start_addr[1],
> + &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_B);
> + writel(img_start_addr[2],
> + &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_R);
> + writel(pitch[1], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_B);
> + writel(pitch[2], &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_R);
> + }
> +
> + /* Set CROP */
> + val = (src->y << 16U) | src->x;
> + writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_OFFSET);
> + val = (src->h << 16U) | src->w;
> + writel(val, &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_SIZE);
> +
> + /* Set output process */
> + writel(out_process->half_scale,
> + &res->capture_reg->l2isp.post[post_id].L2_POST_HALF_SCALE_EN);
> + writel(out_process->select_color, &res->capture_reg->l2isp.post[post_id].L2_POST_C_SELECT);
> + writel((u32)out_process->alpha, &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTALP);
> + writel(img->format, &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTFMT);
> +
> + /* Update ROI area and input to each POST */
> + res->l2_roi_path_info.post_enable_flag[post_id] = true;
> + res->l2_roi_path_info.post_crop_x[post_id] = src->x;
> + res->l2_roi_path_info.post_crop_y[post_id] = src->y;
> + res->l2_roi_path_info.post_crop_w[post_id] = src->w;
> + res->l2_roi_path_info.post_crop_h[post_id] = src->h;
> + hwd_viif_l2_set_roi_path(res);
> +
> + return ret;
> +}
[snip]
> diff --git a/drivers/media/platform/visconti/hwd_viif.h b/drivers/media/platform/visconti/hwd_viif.h
> new file mode 100644
> index 00000000000..100afda8436
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif.h
> @@ -0,0 +1,710 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_H
> +#define HWD_VIIF_H
> +
> +#include <linux/errno.h>
> +#include <linux/types.h>
> +
> +#include <linux/visconti_viif.h>
> +
> +enum hwd_power_ctrl {
> + HWD_POWER_OFF = 0, /**< Power off */
> + HWD_POWER_ON /**< Power on */
> +};
Not used.
> +
> +/* MIPI CSI2 Data Types */
> +#define VISCONTI_CSI2_DT_YUV4228B 0x1E
> +#define VISCONTI_CSI2_DT_YUV42210B 0x1F
> +#define VISCONTI_CSI2_DT_RGB565 0x22
> +#define VISCONTI_CSI2_DT_RGB888 0x24
> +#define VISCONTI_CSI2_DT_RAW8 0x2A
> +#define VISCONTI_CSI2_DT_RAW10 0x2B
> +#define VISCONTI_CSI2_DT_RAW12 0x2C
> +#define VISCONTI_CSI2_DT_RAW14 0x2D
You can drop this and replace it with the macros defined in
include/media/mipi-csi2.h.
> +
> +/* hwd_viif_enable_flag */
> +#define HWD_VIIF_DISABLE (0U)
No need for parentheses, here and below.
> +#define HWD_VIIF_ENABLE (1U)
false/true or 0/1 would be more readable in the code.
> +
> +/* hwd_viif_memory_sync_type */
> +#define HWD_VIIF_MEM_SYNC_INTERNAL (0U)
> +#define HWD_VIIF_MEM_SYNC_CSI2 (1U)
This isn't used anywhere.
> +
> +/* hwd_viif_color_format */
> +#define HWD_VIIF_YCBCR422_8_PACKED (0U)
> +#define HWD_VIIF_RGB888_PACKED (1U)
> +#define HWD_VIIF_ARGB8888_PACKED (3U)
> +#define HWD_VIIF_YCBCR422_8_PLANAR (8U)
> +#define HWD_VIIF_RGB888_YCBCR444_8_PLANAR (9U)
> +#define HWD_VIIF_ONE_COLOR_8 (11U)
> +#define HWD_VIIF_YCBCR422_16_PLANAR (12U)
> +#define HWD_VIIF_RGB161616_YCBCR444_16_PLANAR (13U)
> +#define HWD_VIIF_ONE_COLOR_16 (15U)
Could this be turned into an enum ?
enum hwd_viif_color_format {
HWD_VIIF_YCBCR422_8_PACKED = 0U,
HWD_VIIF_RGB888_PACKED = 1U,
HWD_VIIF_ARGB8888_PACKED = 3U,
HWD_VIIF_YCBCR422_8_PLANAR = 8U,
HWD_VIIF_RGB888_YCBCR444_8_PLANAR = 9U,
HWD_VIIF_ONE_COLOR_8 = 11U,
HWD_VIIF_YCBCR422_16_PLANAR = 12U,
HWD_VIIF_RGB161616_YCBCR444_16_PLANAR = 13U,
HWD_VIIF_ONE_COLOR_16 = 15U,
};
Then you'll be able to use the enum in variables, function parameters
and structure fields, for instance
struct hwd_viif_img {
u32 width;
u32 height;
enum hwd_viif_color_format format;
struct hwd_viif_pixelmap pixelmap[3];
};
which will make it clearer through the code which types and values are
expected in a given place.
Same for all other macros where this would be applicable.
> +
> +/* hwd_viif_raw_pack_mode */
> +#define HWD_VIIF_RAWPACK_DISABLE (0U)
> +#define HWD_VIIF_RAWPACK_MSBFIRST (2U)
> +#define HWD_VIIF_RAWPACK_LSBFIRST (3U)
> +
> +/* hwd_viif_yuv_conversion_mode */
> +#define HWD_VIIF_YUV_CONV_REPEAT (0U)
> +#define HWD_VIIF_YUV_CONV_INTERPOLATION (1U)
> +
> +/* hwd_viif_gamma_table_mode */
> +#define HWD_VIIF_GAMMA_COMPRESSED (0U)
> +#define HWD_VIIF_GAMMA_LINEAR (1U)
> +
> +/* hwd_viif_output_color_mode */
> +#define HWD_VIIF_COLOR_Y_G (0U)
> +#define HWD_VIIF_COLOR_U_B (1U)
> +#define HWD_VIIF_COLOR_V_R (2U)
> +#define HWD_VIIF_COLOR_YUV_RGB (4U)
> +
> +/* hwd_viif_hw_params */
> +#define HWD_VIIF_MAX_CH (6U)
This isn't used.
Could you go through this file and delete all the macros that are not
used and that you don't plan to use in the future ?
> +#define HWD_VIIF_MAX_PLANE_NUM (3U)
This is used inside the hwd_viif_l2_set_img_transmission() function
only. I'm really tempted to move definitions of macros that are local to
a function in the corresponding .c file, just before the function. This
file is huge, and quite difficult to read, anything that would shrink it
would be nice.
> +
> +/**
> + * enum hwd_viif_csi2_dphy - D-PHY Lane assignment
> + *
> + * specifies which line(L0-L3) is assigned to D0-D3
> + */
> +enum hwd_viif_csi2_dphy {
> + HWD_VIIF_CSI2_DPHY_L0L1L2L3 = 0U,
> + HWD_VIIF_CSI2_DPHY_L0L3L1L2 = 1U,
> + HWD_VIIF_CSI2_DPHY_L0L2L3L1 = 2U,
> + HWD_VIIF_CSI2_DPHY_L0L1L3L2 = 4U,
> + HWD_VIIF_CSI2_DPHY_L0L3L2L1 = 5U,
> + HWD_VIIF_CSI2_DPHY_L0L2L1L3 = 6U
> +};
> +
> +/* hwd_viif_csi2rx_cal_status */
> +#define HWD_VIIF_CSI2_CAL_NOT_DONE (0U)
> +#define HWD_VIIF_CSI2_CAL_SUCCESS (1U)
> +#define HWD_VIIF_CSI2_CAL_FAIL (2U)
Custom error codes are usually frowned upon, especially when success is
signaled by a value other than 0. How about using 0 for success, -EAGAIN
for NOT_DONE, and -EIO for failure ? Same comment for other custom
status values, if any.
> +
> +/* hwd_viif_csi2rx_not_capture */
> +#define HWD_VIIF_CSI2_NOT_CAPTURE (-1) /**< csi2 not capture */
[snip]
> +
> +/* hwd_viif_l1_input_mode */
> +#define HWD_VIIF_L1_INPUT_HDR (0U)
> +#define HWD_VIIF_L1_INPUT_PWL (1U)
> +#define HWD_VIIF_L1_INPUT_SDR (2U)
> +#define HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT (3U)
> +#define HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT (4U)
> +
> +/* hwd_viif_l1_raw_color_filter_mode */
> +#define HWD_VIIF_L1_RAW_GR_R_B_GB (0U)
> +#define HWD_VIIF_L1_RAW_R_GR_GB_B (1U)
> +#define HWD_VIIF_L1_RAW_B_GB_GR_R (2U)
> +#define HWD_VIIF_L1_RAW_GB_B_R_GR (3U)
> +
> +/* hwd_viif_l1_input_interpolation_mode */
> +#define HWD_VIIF_L1_INPUT_INTERPOLATION_LINE (0U)
> +#define HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL (1U)
> +
> +/* hwd_viif_l1_img_sens */
> +#define HWD_VIIF_L1_IMG_SENSITIVITY_HIGH (0U)
> +#define HWD_VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED (1U)
> +#define HWD_VIIF_L1_IMG_SENSITIVITY_LOW (2U)
> +
> +/* hwd_viif_l1_dpc */
> +#define HWD_VIIF_L1_DPC_1PIXEL (0U)
> +#define HWD_VIIF_L1_DPC_2PIXEL (1U)
> +
> +/* hwd_viif_l1_rcnr_hry_type */
> +#define HWD_VIIF_L1_RCNR_LOW_RESOLUTION (0U)
> +#define HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION (1U)
> +#define HWD_VIIF_L1_RCNR_HIGH_RESOLUTION (2U)
> +#define HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION (3U)
> +
> +/* hwd_viif_l1_rcnr_msf_blend_ratio */
> +#define HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 (0U)
> +#define HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 (1U)
> +#define HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 (2U)
> +
> +/* hwd_viif_l1_hdrs */
> +#define HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE (0U)
> +#define HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE (1U)
> +
> +/* hwd_viif_l1_lsc_para_mag */
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH (0U)
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH (1U)
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND (2U)
> +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST (3U)
> +
> +/* hwd_viif_l1_lsc_grid_mag */
> +#define HWD_VIIF_L1_GRID_COEF_GAIN_X1 (0U)
> +#define HWD_VIIF_L1_GRID_COEF_GAIN_X2 (1U)
> +
> +/* hwd_viif_l1_demosaic */
> +#define HWD_VIIF_L1_DEMOSAIC_ACPI (0U)
> +#define HWD_VIIF_L1_DEMOSAIC_DMG (1U)
> +
> +/* hwd_viif_l1_awb_restart_cond */
> +/* macros for L1ISP condition to restart auto white balance */
> +#define HWD_VIIF_L1_AWB_RESTART_NO (0U)
> +#define HWD_VIIF_L1_AWB_RESTART_128FRAME (1U)
> +#define HWD_VIIF_L1_AWB_RESTART_64FRAME (2U)
> +#define HWD_VIIF_L1_AWB_RESTART_32FRAME (3U)
> +#define HWD_VIIF_L1_AWB_RESTART_16FRAME (4U)
> +#define HWD_VIIF_L1_AWB_RESTART_8FRAME (5U)
> +#define HWD_VIIF_L1_AWB_RESTART_4FRAME (6U)
> +#define HWD_VIIF_L1_AWB_RESTART_2FRAME (7U)
> +
> +/* hwd_viif_l1_awb_mag */
> +#define HWD_VIIF_L1_AWB_ONE_SECOND (0U)
> +#define HWD_VIIF_L1_AWB_X1 (1U)
> +#define HWD_VIIF_L1_AWB_X2 (2U)
> +#define HWD_VIIF_L1_AWB_X4 (3U)
> +
> +/* hwd_viif_l1_awb_area_mode */
> +#define HWD_VIIF_L1_AWB_AREA_MODE0 (0U)
> +#define HWD_VIIF_L1_AWB_AREA_MODE1 (1U)
> +#define HWD_VIIF_L1_AWB_AREA_MODE2 (2U)
> +#define HWD_VIIF_L1_AWB_AREA_MODE3 (3U)
> +
> +/* hwd_viif_l1_hdrc_tone_type */
> +#define HWD_VIIF_L1_HDRC_TONE_USER (0U)
> +#define HWD_VIIF_L1_HDRC_TONE_PRESET (1U)
> +
> +/* hwd_viif_l1_bin_mode */
> +#define HWD_VIIF_L1_HIST_BIN_MODE_LINEAR (0U)
> +#define HWD_VIIF_L1_HIST_BIN_MODE_LOG (1U)
> +
> +/* hwd_viif_l2_undist_mode */
> +#define HWD_VIIF_L2_UNDIST_POLY (0U)
> +#define HWD_VIIF_L2_UNDIST_GRID (1U)
> +#define HWD_VIIF_L2_UNDIST_POLY_TO_GRID (2U)
> +#define HWD_VIIF_L2_UNDIST_GRID_TO_POLY (3U)
> +
> +/**
> + * struct hwd_viif_csi2rx_line_err_target
> + *
> + * Virtual Channel and Data Type pair for CSI2RX line error monitor
> + *
> + * When 0 is set to dt, line error detection is disabled.
> + *
> + * * VC can be 0 .. 3
> + * * DT can be 0 or 0x10 .. 0x3F
> + */
> +#define VISCONTI_CSI2_ERROR_MONITORS_NUM 8
> +struct hwd_viif_csi2rx_line_err_target {
> + u32 vc[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> + u32 dt[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_csi2rx_irq_mask
> + * @mask: mask setting for CSI2RX error interruption
> + *
> + * * mask[0]: D-PHY fatal error
> + * * mask[1]: Packet fatal error
> + * * mask[2]: Frame fatal error
> + * * mask[3]: D-PHY error
> + * * mask[4]: Packet error
> + * * mask[5]: Line error
> + */
> +#define VISCONTI_CSI2RX_IRQ_MASKS_NUM 6
> +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_FATAL 0
> +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_FATAL 1
> +#define VISCONTI_CSI2RX_IRQ_MASK_FRAME_FATAL 2
> +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_ERROR 3
> +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_ERROR 4
> +#define VISCONTI_CSI2RX_IRQ_MASK_LINE_ERROR 5
> +struct hwd_viif_csi2rx_irq_mask {
> + u32 mask[VISCONTI_CSI2RX_IRQ_MASKS_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_csi2rx_packet - CSI2 packet information
> + * @word_count: word count included in one packet[byte] [0..16384]
> + * @packet_num: the number of packet included in one packet [0..8192]
> + *
> + * each element means as below.
> + * * [0]: embedded data of MAIN unit
> + * * [1]: long packet data of MAIN unit
> + * * [2]: embedded data of SUB unit
> + * * [3]: long packet data of SUB unit
> + *
> + * Regarding word_count of long packet data,
> + * word count of odd line needs to be set in case of DT = 0x18, 0x19, 0x1C or 0x1D.
> + */
> +#define VISCONTI_CSI2RX_PACKET_TYPES_NUM 4
> +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN 0
> +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN 1
> +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB 2
> +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB 3
> +struct hwd_viif_csi2rx_packet {
> + u32 word_count[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> + u32 packet_num[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_pixelmap - pixelmap information
> + * @pmap_paddr: start address of pixel data(physical address). 4byte alignment.
> + * @pitch: pitch size of pixel map[byte]
> + *
> + * Condition of pitch in case of L2ISP output is as below.
> + * * max: 32704[byte]
> + * * min: the larger value of (active width of image * k / r) and 128[byte]
> + * * alignment: 64[byte]
> + *
> + * Condition of pitch in the other cases is as below.
> + * * max: 65536[byte]
> + * * min: active width of image * k / r[byte]
> + * * alignment: 4[byte]
> + *
> + * k is the size of 1 pixel and the value is as below.
> + * * HWD_VIIF_YCBCR422_8_PACKED: 2
> + * * HWD_VIIF_RGB888_PACKED: 3
> + * * HWD_VIIF_ARGB8888_PACKED: 4
> + * * HWD_VIIF_YCBCR422_8_PLANAR: 1
> + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR: 1
> + * * HWD_VIIF_ONE_COLOR_8: 1
> + * * HWD_VIIF_YCBCR422_16_PLANAR: 2
> + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR: 2
> + * * HWD_VIIF_ONE_COLOR_16: 2
> + *
> + * r is the correction factor for Cb or Cr of YCbCr422 planar and the value is as below.
> + * * YCbCr422 Cb-planar: 2
> + * * YCbCr422 Cr-planar: 2
> + * * others: 1
> + *
> + */
> +struct hwd_viif_pixelmap {
> + uintptr_t pmap_paddr;
> + u32 pitch;
> +};
> +
> +/**
> + * struct hwd_viif_img - image information
> + * @width: active width of image[pixel]
> + * * [128..5760](output from L2ISP)
> + * * [128..4096](input to MAIN unit(memory input))
> + * * [128..4096](output from SUB unit)
> + * * The value should be even.
> + *
> + * @height: active height of image[line]
> + * * [128..3240](output from L2ISP)
> + * * [128..2160](input to MAIN unit(memory input))
> + * * [128..2160](output from SUB unit)
> + * * The value should be even.
> + *
> + * @format: hwd_viif_color_format "color format"
> + * * Below color formats are supported for input and output of MAIN unit
> + * * HWD_VIIF_YCBCR422_8_PACKED
> + * * HWD_VIIF_RGB888_PACKED
> + * * HWD_VIIF_ARGB8888_PACKED
> + * * HWD_VIIF_YCBCR422_8_PLANAR
> + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR
> + * * HWD_VIIF_ONE_COLOR_8
> + * * HWD_VIIF_YCBCR422_16_PLANAR
> + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR
> + * * HWD_VIIF_ONE_COLOR_16
> + * * Below color formats are supported for output of SUB unit
> + * * HWD_VIIF_ONE_COLOR_8
> + * * HWD_VIIF_ONE_COLOR_16
> + *
> + * @pixelmap: pixelmap information
> + * * [0]: Y/G-planar, packed/Y/RAW
> + * * [1]: Cb/B-planar
> + * * [2]: Cr/R-planar
> + */
> +struct hwd_viif_img {
> + u32 width;
> + u32 height;
> + u32 format;
> + struct hwd_viif_pixelmap pixelmap[3];
> +};
> +
> +/**
> + * struct hwd_viif_input_img - input image information
> + * @pixel_clock: pixel clock [3375..600000] [kHz]. 0 needs to be set for long packet data.
> + * @htotal_size: horizontal total size
> + * * [143..65535] [pixel] for image data
> + * * [239..109225] [ns] for long packet data
> + * @hactive_size: horizontal active size [pixel]
> + * * [128..4096] without L1ISP
> + * * [640..3840] with L1ISP
> + * * The value should be even. In addition, the value should be a multiple of 8 with L1ISP
> + * * 0 needs to be set for the configuration of long packet data or SUB unit output.
> + * @vtotal_size: vertical total size [line]
> + * * [144..16383] for image data
> + * * 0 needs to be set for the configuration of long packet data.
> + * @vbp_size: vertical back porch size
> + * * [5..4095] [line] for image data
> + * * [5..4095] [the number of packet] for long packet data
> + * @vactive_size: vertical active size [line]
> + * * [128..2160] without L1ISP
> + * * [480..2160] with L1ISP
> + * * The value should be even.
> + * * 0 needs to be set for the configuration of long packet data.
> + * @interpolation_mode: input image interpolation mode for hwd_viif_l1_input_interpolation_mode
> + * * HWD_VIIF_L1_INPUT_INTERPOLATION_LINE needs to be set in the below cases.
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + * @input_num: the number of input images [1..3]
> + * * 1 needs to be set in the below cases.
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + * @hobc_width: the number of horizontal optical black pixels [0,16,32,64 or 128]
> + * * 0 needs to be set in the below cases.
> + * * in case of hobc_margin = 0
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + * @hobc_margin: the number of horizontal optical black margin[0..30] (even number)
> + * * 0 needs to be set in the below cases.
> + * * in case of hobc_width = 0
> + * * image data(without L1ISP) or long packet data
> + * * image data or long packet data of SUB unit
> + *
> + * Below conditions need to be satisfied.
> + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_LINE:
> + * (htotal_size > (hactive_size + hobc_width + hobc_margin)) &&
> + * (vtotal_size > (vbp_size + vactive_size * input_num))
> + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL:
> + * (htotal_size > ((hactive_size + hobc_width + hobc_margin) * input_num)) &&
> + * (vtotal_size > (vbp_size + vactive_size))
> + * * L1ISP is used:
> + * vbp_size >= (54720[cycle] / 500000[kHz]) * (pixel_clock / htotal_size) + 38 + ISST time
> + * * L1ISP is not used:
> + * vbp_size >= (39360[cycle] / 500000[kHz]) * (pixel_clock / htotal_size) + 16 + ISST time
> + *
> + * Note: L1ISP is used when RAW data is input to MAIN unit
> + */
> +struct hwd_viif_input_img {
> + u32 pixel_clock;
> + u32 htotal_size;
> + u32 hactive_size;
> + u32 vtotal_size;
> + u32 vbp_size;
> + u32 vactive_size;
> + u32 interpolation_mode;
> + u32 input_num;
> + u32 hobc_width;
> + u32 hobc_margin;
> +};
> +
> +/**
> + * struct hwd_viif_csc_param - color conversion information
> + * @r_cr_in_offset: input offset of R/Cr[pix value] [0x0..0x1FFFF]
> + * @g_y_in_offset: input offset of G/Y[pix value] [0x0..0x1FFFF]
> + * @b_cb_in_offset: input offset of B/Cb[pix value] [0x0..0x1FFFF]
> + * @coef: coefficient of matrix [0x0..0xFFFF]
> + * * [0] : c00(YG_YG), [1] : c01(UB_YG), [2] : c02(VR_YG),
> + * * [3] : c10(YG_UB), [4] : c11(UB_UB), [5] : c12(VR_UB),
> + * * [6] : c20(YG_VR), [7] : c21(UB_VR), [8] : c22(VR_VR)
> + * @r_cr_out_offset: output offset of R/Cr[pix value] [0x0..0x1FFFF]
> + * @g_y_out_offset: output offset of G/Y[pix value] [0x0..0x1FFFF]
> + * @b_cb_out_offset: output offset of B/Cb[pix value] [0x0..0x1FFFF]
> + */
> +struct hwd_viif_csc_param {
> + u32 r_cr_in_offset;
> + u32 g_y_in_offset;
> + u32 b_cb_in_offset;
> + u32 coef[9];
> + u32 r_cr_out_offset;
> + u32 g_y_out_offset;
> + u32 b_cb_out_offset;
> +};
> +
> +/**
> + * struct hwd_viif_img_area - image area definition
> + * @x: x position [0..8062] [pixel]
> + * @y: y position [0..3966] [line]
> + * @w: image width [128..8190] [pixel]
> + * @h: image height [128..4094] [line]
> + */
> +struct hwd_viif_img_area {
> + u32 x;
> + u32 y;
> + u32 w;
> + u32 h;
> +};
> +
> +/**
> + * struct hwd_viif_out_process - configuration of output process of MAIN unit and L2ISP
> + * @half_scale: hwd_viif_enable_flag "enable or disable half scale"
> + * @select_color: hwd_viif_output_color_mode "select output color"
> + * @alpha: alpha value used in case of ARGB8888 output [0..255]
> + */
> +struct hwd_viif_out_process {
> + u32 half_scale;
> + u32 select_color;
> + u8 alpha;
> +};
> +
> +/**
> + * struct hwd_viif_l1_lsc - HWD L1ISP lens shading correction parameters
> + * @lssc_parabola_param: parabola shading correction parameter
> + * * NULL: disable parabola shading correction
> + * * not NULL: enable parabola shading correction
> + * @lssc_grid_param: grid shading correction parameter
> + * * NULL: disable grid shading correction
> + * * not NULL: enable grid shading correction
> + * @lssc_pwhb_r_gain_max: maximum R gain of preset white balance correction
> + * @lssc_pwhb_r_gain_min: minimum R gain of preset white balance correction
> + * @lssc_pwhb_gr_gain_max: maximum Gr gain of preset white balance correction
> + * @lssc_pwhb_gr_gain_min: minimum Gr gain of preset white balance correction
> + * @lssc_pwhb_gb_gain_max: maximum Gb gain of preset white balance correction
> + * @lssc_pwhb_gb_gain_min: minimum Gb gain of preset white balance correction
> + * @lssc_pwhb_b_gain_max: maximum B gain of preset white balance correction
> + * @lssc_pwhb_b_gain_min: minimum B gain of preset white balance correction
> + *
> + * Range and accuracy of lssc_pwhb_xxx_gain_xxx are as below.
> + * - range: [0x0..0x7FF]
> + * - accuracy : 1/256
> + */
> +struct hwd_viif_l1_lsc {
> + struct viif_l1_lsc_parabola_param *lssc_parabola_param;
> + struct viif_l1_lsc_grid_param *lssc_grid_param;
> + u32 lssc_pwhb_r_gain_max;
> + u32 lssc_pwhb_r_gain_min;
> + u32 lssc_pwhb_gr_gain_max;
> + u32 lssc_pwhb_gr_gain_min;
> + u32 lssc_pwhb_gb_gain_max;
> + u32 lssc_pwhb_gb_gain_min;
> + u32 lssc_pwhb_b_gain_max;
> + u32 lssc_pwhb_b_gain_min;
> +};
> +
> +/**
> + * struct hwd_viif_l1_img_quality_adjustment - HWD L1ISP image quality adjustment parameters
> + * @coef_cb: Cb coefficient [0x0..0xffff] accuracy: 1/65536
> + * @coef_cr: Cr coefficient [0x0..0xffff] accuracy: 1/65536
> + * @brightness: brightness value [-32768..32767] (0 means off.)
> + * @linear_contrast: linear contrast value [0x0..0xff] accuracy: 1/128 (128 means off.)
> + * @*nonlinear_contrast: pointer to nonlinear contrast parameter
> + * @*lum_noise_reduction: pointer to luminance noise reduction parameter
> + * @*edge_enhancement: pointer to edge enhancement parameter
> + * @*uv_suppression: pointer to UV suppression parameter
> + * @*coring_suppression: pointer to coring suppression parameter
> + * @*edge_suppression: pointer to edge enhancement parameter
> + * @*color_level: pointer to color level adjustment parameter
> + * @color_noise_reduction_enable: enable/disable color noise reduction @ref hwd_viif_enable_flag
> + */
> +struct hwd_viif_l1_img_quality_adjustment {
> + u16 coef_cb;
> + u16 coef_cr;
> + s16 brightness;
> + u8 linear_contrast;
> + struct viif_l1_nonlinear_contrast *nonlinear_contrast;
> + struct viif_l1_lum_noise_reduction *lum_noise_reduction;
> + struct viif_l1_edge_enhancement *edge_enhancement;
> + struct viif_l1_uv_suppression *uv_suppression;
> + struct viif_l1_coring_suppression *coring_suppression;
> + struct viif_l1_edge_suppression *edge_suppression;
> + struct viif_l1_color_level *color_level;
> + u32 color_noise_reduction_enable;
> +};
> +
> +/**
> + * struct hwd_viif_l1_info - HWD L1ISP processing information
> + * @context_id: context id
> + * @ag_cont_hobc_high: analog gain for high sensitivity image of OBCC
> + * @ag_cont_hobc_middle_led: analog gain for middle sensitivity or led image of OBCC
> + * @ag_cont_hobc_low: analog gain for low sensitivity image of OBCC
> + * @ag_cont_abpc_high: analog gain for high sensitivity image of ABPC
> + * @ag_cont_abpc_middle_led: analog gain for middle sensitivity or led image of ABPC
> + * @ag_cont_abpc_low: analog gain for low sensitivity image of ABPC
> + * @ag_cont_rcnr_high: analog gain for high sensitivity image of RCNR
> + * @ag_cont_rcnr_middle_led: analog gain for middle sensitivity or led image of RCNR
> + * @ag_cont_rcnr_low: analog gain for low sensitivity image of RCNR
> + * @ag_cont_lssc: analog gain for LSSC
> + * @ag_cont_mpro: analog gain for color matrix correction
> + * @ag_cont_vpro: analog gain for image quality adjustment
> + * @dpc_defect_num_h:
> + * the number of dynamically corrected defective pixel(high sensitivity image)
> + * @dpc_defect_num_m:
> + * the number of dynamically corrected defective pixel(middle sensitivity or led image)
> + * @dpc_defect_num_l:
> + * the number of dynamically corrected defective pixel(low sensitivity image)
> + * @hdrc_tnp_fb_smth_max: the maximum value of luminance information after smoothing filter at HDRC
> + * @avg_lum_weight: weighted average luminance value at average luminance generation
> + * @avg_lum_block[8][8]:
> + * average luminance of each block [y][x]:
> + * y means vertical position and x means horizontal position.
> + * @avg_lum_four_line_lum[4]:
> + * 4-lines average luminance. avg_lum_four_line_lum[n] corresponds to aexp_ave4linesy[n]
> + * @avg_satur_pixnum: the number of saturated pixel at average luminance generation
> + * @avg_black_pixnum: the number of black pixel at average luminance generation
> + * @awb_ave_u: average U at AWHB [pixel]
> + * @awb_ave_v: average V at AWHB [pixel]
> + * @awb_accumulated_pixel: the number of accumulated pixel at AWHB
> + * @awb_gain_r: R gain applied in the next frame at AWHB
> + * @awb_gain_g: G gain applied in the next frame at AWHB
> + * @awb_gain_b: B gain applied in the next frame at AWHB
> + * @awb_status_u: status of U convergence at AWHB (true: converged, false: not converged)
> + * @awb_status_v: status of V convergence at AWHB (true: converged, false: not converged)
> + */
> +struct hwd_viif_l1_info {
> + u32 context_id;
> + u8 ag_cont_hobc_high;
> + u8 ag_cont_hobc_middle_led;
> + u8 ag_cont_hobc_low;
> + u8 ag_cont_abpc_high;
> + u8 ag_cont_abpc_middle_led;
> + u8 ag_cont_abpc_low;
> + u8 ag_cont_rcnr_high;
> + u8 ag_cont_rcnr_middle_led;
> + u8 ag_cont_rcnr_low;
> + u8 ag_cont_lssc;
> + u8 ag_cont_mpro;
> + u8 ag_cont_vpro;
> + u32 dpc_defect_num_h;
> + u32 dpc_defect_num_m;
> + u32 dpc_defect_num_l;
> + u32 hdrc_tnp_fb_smth_max;
> + u32 avg_lum_weight;
> + u32 avg_lum_block[8][8];
> + u32 avg_lum_four_line_lum[4];
> + u16 avg_satur_pixnum;
> + u16 avg_black_pixnum;
> + u32 awb_ave_u;
> + u32 awb_ave_v;
> + u32 awb_accumulated_pixel;
> + u32 awb_gain_r;
> + u32 awb_gain_g;
> + u32 awb_gain_b;
> + bool awb_status_u;
> + bool awb_status_v;
> +};
> +
> +/**
> + * struct hwd_viif_l2_gamma_table - HWD L2ISP Gamma table physical address
> + * @table[6]: table address(physical address) 4byte alignment
> + *
> + * relation between element and table is as below.
> + * * [0]: G/Y(1st table)
> + * * [1]: G/Y(2nd table)
> + * * [2]: B/U(1st table)
> + * * [3]: B/U(2nd table)
> + * * [4]: R/V(1st table)
> + * * [5]: R/V(2nd table)
> + *
> + * when 0 is set to table address, table transfer is disabled.
> + */
> +struct hwd_viif_l2_gamma_table {
> + uintptr_t table[6];
Use dma_addr_t for fields that store DMA addresses. Same comment for all
the other usages of uintptr_t I think. While at it, don't name the
variables "paddr", those are not physical addresses but DMA addresses
(they can differ when an IOMMU is present). Use "dma_addr" or just
"addr" in variable names.
> +};
[snip]
> diff --git a/drivers/media/platform/visconti/hwd_viif_csi2rx.c b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> new file mode 100644
> index 00000000000..f49869c5bdd
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> @@ -0,0 +1,610 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/timekeeping.h>
> +#include "hwd_viif.h"
> +#include "hwd_viif_internal.h"
> +
> +#define CSI2_DT_YUV4208 0x18
> +#define CSI2_DT_YUV42010 0x19
> +#define CSI2_DT_YUV4208L 0x1A
> +#define CSI2_DT_YUV4208C 0x1C
> +#define CSI2_DT_YUV42010C 0x1D
> +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> +#define CSI2_DT_RGB444 0x20
> +#define CSI2_DT_RGB555 0x21
> +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> +#define CSI2_DT_RGB666 0x23
> +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
You can drop this and replace it with the macros defined in
include/media/mipi-csi2.h.
> +
> +#define TESTCTRL0_PHY_TESTCLK_1 0x2
> +#define TESTCTRL0_PHY_TESTCLK_0 0x0
> +#define TESTCTRL1_PHY_TESTEN 0x10000
> +#define TESTCTRL1_PHY_TESTDOUT_SHIFT 8U
> +
> +/**
> + * write_dphy_param() - Write CSI2RX DPHY params
> + *
> + * @test_mode: test code address
> + * @test_in: test code data
> + * Return: None
> + */
> +static void write_dphy_param(u32 test_mode, u8 test_in, struct hwd_viif_res *res)
> +{
> + /* select MSB address register */
> + writel(TESTCTRL1_PHY_TESTEN, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* set MSB address of test_mode */
> + writel(FIELD_GET(0xF00, test_mode), &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* select and set LSB address register */
> + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* set the test code data */
> + writel((u32)test_in, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +}
> +
> +/**
> + * read_dphy_param() - Read CSI2RX DPHY params
> + *
> + * @test_mode: test code address
> + * Return: test code data
> + */
> +static u8 read_dphy_param(u32 test_mode, struct hwd_viif_res *res)
> +{
> + u32 read_data;
> +
> + /* select MSB address register */
> + writel(TESTCTRL1_PHY_TESTEN, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* set MSB address of test_mode */
> + writel(FIELD_GET(0xF00, test_mode), &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* select and set LSB address register */
> + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> +
> + /* rise and clear the testclk */
> + writel(TESTCTRL0_PHY_TESTCLK_1, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(TESTCTRL0_PHY_TESTCLK_0, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* read the test code data */
> + read_data = readl(&res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> + return (u8)(read_data >> TESTCTRL1_PHY_TESTDOUT_SHIFT);
> +}
> +
> +/**
> + * enum dphy_testcode - DPHY registers via the local communication path
> + */
> +enum dphy_testcode {
> + DIG_RDWR_RX_SYS_0 = 0x001,
> + DIG_RDWR_RX_SYS_1 = 0x002,
> + DIG_RDWR_RX_SYS_3 = 0x004,
> + DIG_RDWR_RX_SYS_7 = 0x008,
> + DIG_RDWR_RX_RX_STARTUP_OVR_2 = 0x0E2,
> + DIG_RDWR_RX_RX_STARTUP_OVR_3 = 0x0E3,
> + DIG_RDWR_RX_RX_STARTUP_OVR_4 = 0x0E4,
> + DIG_RDWR_RX_RX_STARTUP_OVR_5 = 0x0E5,
> + DIG_RDWR_RX_CB_2 = 0x1AC,
> + DIG_RD_RX_TERM_CAL_0 = 0x220,
> + DIG_RD_RX_TERM_CAL_1 = 0x221,
> + DIG_RD_RX_TERM_CAL_2 = 0x222,
> + DIG_RDWR_RX_CLKLANE_LANE_6 = 0x307,
> + DIG_RD_RX_CLKLANE_OFFSET_CAL_0 = 0x39D,
> + DIG_RD_RX_LANE0_OFFSET_CAL_0 = 0x59F,
> + DIG_RD_RX_LANE0_DDL_0 = 0x5E0,
> + DIG_RD_RX_LANE1_OFFSET_CAL_0 = 0x79F,
> + DIG_RD_RX_LANE1_DDL_0 = 0x7E0,
> + DIG_RD_RX_LANE2_OFFSET_CAL_0 = 0x99F,
> + DIG_RD_RX_LANE2_DDL_0 = 0x9E0,
> + DIG_RD_RX_LANE3_OFFSET_CAL_0 = 0xB9F,
> + DIG_RD_RX_LANE3_DDL_0 = 0xBE0,
> +};
> +
> +#define SYS_0_HSFREQRANGE_OVR BIT(5)
> +#define SYS_7_RESERVED FIELD_PREP(0x1F, 0x0C)
> +#define SYS_7_DESKEW_POL BIT(5)
> +#define STARTUP_OVR_4_CNTVAL FIELD_PREP(0x70, 0x01)
> +#define STARTUP_OVR_4_DDL_EN BIT(0)
> +#define STARTUP_OVR_5_BYPASS BIT(0)
> +#define CB_2_LPRX_BIAS BIT(6)
> +#define CB_2_RESERVED FIELD_PREP(0x3F, 0x0B)
> +#define CLKLANE_RXHS_PULL_LONG BIT(7)
> +
> +static const struct hwd_viif_dphy_hs_info dphy_hs_info[] = {
> + { 80, 0x0, 0x1cc }, { 85, 0x10, 0x1cc }, { 95, 0x20, 0x1cc }, { 105, 0x30, 0x1cc },
> + { 115, 0x1, 0x1cc }, { 125, 0x11, 0x1cc }, { 135, 0x21, 0x1cc }, { 145, 0x31, 0x1cc },
> + { 155, 0x2, 0x1cc }, { 165, 0x12, 0x1cc }, { 175, 0x22, 0x1cc }, { 185, 0x32, 0x1cc },
> + { 198, 0x3, 0x1cc }, { 213, 0x13, 0x1cc }, { 228, 0x23, 0x1cc }, { 243, 0x33, 0x1cc },
> + { 263, 0x4, 0x1cc }, { 288, 0x14, 0x1cc }, { 313, 0x25, 0x1cc }, { 338, 0x35, 0x1cc },
> + { 375, 0x5, 0x1cc }, { 425, 0x16, 0x1cc }, { 475, 0x26, 0x1cc }, { 525, 0x37, 0x1cc },
> + { 575, 0x7, 0x1cc }, { 625, 0x18, 0x1cc }, { 675, 0x28, 0x1cc }, { 725, 0x39, 0x1cc },
> + { 775, 0x9, 0x1cc }, { 825, 0x19, 0x1cc }, { 875, 0x29, 0x1cc }, { 925, 0x3a, 0x1cc },
> + { 975, 0xa, 0x1cc }, { 1025, 0x1a, 0x1cc }, { 1075, 0x2a, 0x1cc }, { 1125, 0x3b, 0x1cc },
> + { 1175, 0xb, 0x1cc }, { 1225, 0x1b, 0x1cc }, { 1275, 0x2b, 0x1cc }, { 1325, 0x3c, 0x1cc },
> + { 1375, 0xc, 0x1cc }, { 1425, 0x1c, 0x1cc }, { 1475, 0x2c, 0x1cc }
> +};
> +
> +/**
> + * get_dphy_hs_transfer_info() - Get DPHY HS info from table
> + *
> + * @dphy_rate: DPHY clock in MHz
> + * @hsfreqrange: HS Frequency Range
> + * @osc_freq_target: OSC Frequency Target
> + * Return: None
> + */
> +static void get_dphy_hs_transfer_info(u32 dphy_rate, u32 *hsfreqrange, u32 *osc_freq_target,
> + struct hwd_viif_res *res)
> +{
> + int table_size = ARRAY_SIZE(dphy_hs_info);
> + int i;
> +
> + for (i = 1; i < table_size; i++) {
> + if (dphy_rate < dphy_hs_info[i].rate) {
> + *hsfreqrange = dphy_hs_info[i - 1].hsfreqrange;
> + *osc_freq_target = dphy_hs_info[i - 1].osc_freq_target;
> + return;
> + }
> + }
> +
> + /* not found; return the largest entry */
> + *hsfreqrange = dphy_hs_info[table_size - 1].hsfreqrange;
> + *osc_freq_target = dphy_hs_info[table_size - 1].osc_freq_target;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_set_dphy_rate() - Set D-PHY rate
> + *
> + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> + * Return: None
> + */
> +static void hwd_viif_csi2rx_set_dphy_rate(u32 dphy_rate, struct hwd_viif_res *res)
> +{
> + u32 hsfreqrange, osc_freq_target;
> +
> + get_dphy_hs_transfer_info(dphy_rate, &hsfreqrange, &osc_freq_target, res);
> +
> + write_dphy_param(DIG_RDWR_RX_SYS_1, (u8)hsfreqrange, res);
> + write_dphy_param(DIG_RDWR_RX_SYS_0, SYS_0_HSFREQRANGE_OVR, res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_5, STARTUP_OVR_5_BYPASS, res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4, STARTUP_OVR_4_CNTVAL, res);
> + write_dphy_param(DIG_RDWR_RX_CB_2, CB_2_LPRX_BIAS | CB_2_RESERVED, res);
> + write_dphy_param(DIG_RDWR_RX_SYS_7, SYS_7_DESKEW_POL | SYS_7_RESERVED, res);
> + write_dphy_param(DIG_RDWR_RX_CLKLANE_LANE_6, CLKLANE_RXHS_PULL_LONG, res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_2, FIELD_GET(0xff, osc_freq_target), res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_3, FIELD_GET(0xf00, osc_freq_target), res);
> + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4, STARTUP_OVR_4_CNTVAL | STARTUP_OVR_4_DDL_EN,
> + res);
> +
> + writel(HWD_VIIF_DPHY_CFG_CLK_25M, &res->capture_reg->sys.DPHY_FREQRANGE);
> +}
> +
> +/**
> + * check_dphy_calibration_status() - Check D-PHY calibration status
> + *
> + * @test_mode: test code related to calibration information
> + * @shift_val_err: shift value related to error information
> + * @shift_val_done: shift value related to done information
> + * Return: HWD_VIIF_CSI2_CAL_NOT_DONE calibration is not done(out of target or not completed)
> + * Return: HWD_VIIF_CSI2_CAL_FAIL calibration was failed
> + * Return: HWD_VIIF_CSI2_CAL_SUCCESS calibration was succeeded
> + */
> +static u32 check_dphy_calibration_status(u32 test_mode, u32 shift_val_err, u32 shift_val_done,
> + struct hwd_viif_res *res)
> +{
> + u32 read_data = (u32)read_dphy_param(test_mode, res);
> +
> + if (!(read_data & BIT(shift_val_done)))
> + return HWD_VIIF_CSI2_CAL_NOT_DONE;
> +
> + /* error check is not required for termination calibration with REXT(0x221) */
> + if (test_mode == DIG_RD_RX_TERM_CAL_1)
> + return HWD_VIIF_CSI2_CAL_SUCCESS;
> +
> + /* done with error */
> + if (read_data & BIT(shift_val_err))
> + return HWD_VIIF_CSI2_CAL_FAIL;
> +
> + return HWD_VIIF_CSI2_CAL_SUCCESS;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_initialize() - Initialize CSI-2 RX driver
> + *
> + * @num_lane: [1..4](VIIF CH0-CH1)
> + * @lane_assign: lane connection. For more refer @ref hwd_viif_dphy_lane_assignment
> + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> + * @rext_calibration: enable or disable rext calibration.
> + * For more refer @ref hwd_viif_csi2rx_cal_status
> + * @err_target: Pointer to configuration for Line error detection.
> + * @mask: MASK of CSI-2 RX error interruption
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * - [1] "num_lane", "lane_assign", "dphy_rate", "rext_calibration" or "input_mode" is out of range
> + * - [2] "err_target" is NULL
> + * - [3] member of "err_target" is invalid
> + */
> +s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32 lane_assign,
> + u32 dphy_rate, u32 rext_calibration,
> + const struct hwd_viif_csi2rx_line_err_target *err_target,
> + const struct hwd_viif_csi2rx_irq_mask *mask)
> +{
> + u32 i, val;
> +
> + if (num_lane == 0U || num_lane > 4U || lane_assign > HWD_VIIF_CSI2_DPHY_L0L2L1L3)
> + return -EINVAL;
> +
> + if (dphy_rate < HWD_VIIF_DPHY_MIN_DATA_RATE || dphy_rate > HWD_VIIF_DPHY_MAX_DATA_RATE ||
> + (rext_calibration != HWD_VIIF_ENABLE && rext_calibration != HWD_VIIF_DISABLE) ||
> + !err_target) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < 8U; i++) {
> + if (err_target->vc[i] > HWD_VIIF_CSI2_MAX_VC ||
> + err_target->dt[i] > HWD_VIIF_CSI2_MAX_DT ||
> + (err_target->dt[i] < HWD_VIIF_CSI2_MIN_DT && err_target->dt[i] != 0U)) {
> + return -EINVAL;
> + }
> + }
> +
> + /* 1st phase of initialization */
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_RESETN);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + ndelay(15U);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> +
> + /* Configure D-PHY frequency range */
> + hwd_viif_csi2rx_set_dphy_rate(dphy_rate, res);
> +
> + /* 2nd phase of initialization */
> + writel((num_lane - 1U), &res->csi2host_reg->CSI2RX_NLANES);
> + ndelay(5U);
> +
> + /* configuration not to use rext */
> + if (rext_calibration == HWD_VIIF_DISABLE) {
> + write_dphy_param(0x004, 0x10, res);
> + ndelay(5U);
> + }
> +
> + /* Release D-PHY from Reset */
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> + ndelay(5U);
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> +
> + /* configuration of line error target */
> + val = (err_target->vc[3] << 30U) | (err_target->dt[3] << 24U) | (err_target->vc[2] << 22U) |
> + (err_target->dt[2] << 16U) | (err_target->vc[1] << 14U) | (err_target->dt[1] << 8U) |
> + (err_target->vc[0] << 6U) | (err_target->dt[0]);
> + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_1);
> + val = (err_target->vc[7] << 30U) | (err_target->dt[7] << 24U) | (err_target->vc[6] << 22U) |
> + (err_target->dt[6] << 16U) | (err_target->vc[5] << 14U) | (err_target->dt[5] << 8U) |
> + (err_target->vc[4] << 6U) | (err_target->dt[4]);
> + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_2);
> +
> + /* configuration of mask */
> + writel(mask->mask[0], &res->csi2host_reg->CSI2RX_INT_MSK_PHY_FATAL);
> + writel(mask->mask[1], &res->csi2host_reg->CSI2RX_INT_MSK_PKT_FATAL);
> + writel(mask->mask[2], &res->csi2host_reg->CSI2RX_INT_MSK_FRAME_FATAL);
> + writel(mask->mask[3], &res->csi2host_reg->CSI2RX_INT_MSK_PHY);
> + writel(mask->mask[4], &res->csi2host_reg->CSI2RX_INT_MSK_PKT);
> + writel(mask->mask[5], &res->csi2host_reg->CSI2RX_INT_MSK_LINE);
> +
> + /* configuration of lane assignment */
> + writel(lane_assign, &res->capture_reg->sys.DPHY_LANE);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_uninitialize() - Uninitialize CSI-2 RX driver
> + *
> + * Return: 0 Operation completes successfully
> + */
> +s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res)
> +{
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_RESETN);
> +
> + return 0;
> +}
> +
> +#define PORT_SEL_MAIN_LONG 0
> +#define PORT_SEL_MAIN_EMBED 1
> +#define PORT_SEL_SUB_LONG 4
> +#define PORT_SEL_SUB_EMBED 5
> +
> +static void config_vdm_wport(struct hwd_viif_res *res, int port_sel, u32 height, u32 pitch)
> +{
> + struct hwd_viif_vdm_write_port_reg *wport;
> + u32 start_addr, end_addr;
> +
> + wport = &res->capture_reg->vdm.w_port[port_sel];
> +
> + writel(pitch, &wport->VDM_W_PITCH);
> + writel(height, &wport->VDM_W_HEIGHT);
> + start_addr = readl(&wport->VDM_W_STADR);
> + end_addr = start_addr + pitch - 1U;
> + writel(end_addr, &wport->VDM_W_ENDADR);
> +}
The VDM doesn't seem to belong to the CSI-2 RX, I would move this to a
different file.
> +
> +/**
> + * hwd_viif_csi2rx_start() - Start CSI-2 input
> + *
> + * @vc_main: control CSI-2 input of MAIN unit.
> + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> + * @vc_sub: control CSI-2 input of SUB unit.
> + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> + * @packet: Pointer to packet information of embedded data and long packet data
> + * Return: 0 Operation completes successfully
> + * Return: -EINVAL Parameter error
> + * HWD_VIIF_CSI2_NOT_CAPTURE
> + * HWD_VIIF_CSI2_NOT_CAPTURE
> + * - [1] "vc_main" or "vc_sub" is out of range
> + * - [2] member of "packet" is invalid
> + */
> +s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
> + const struct hwd_viif_csi2rx_packet *packet)
> +{
> + u32 val, i, pitch, height, dt;
> + u32 enable_vc0 = HWD_VIIF_DISABLE;
> + u32 enable_vc1 = HWD_VIIF_DISABLE;
> +
> + if (vc_main > 3 || vc_main < HWD_VIIF_CSI2_NOT_CAPTURE || vc_sub > 3 ||
> + vc_sub < HWD_VIIF_CSI2_NOT_CAPTURE) {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < VISCONTI_CSI2RX_PACKET_TYPES_NUM; i++) {
> + if (packet->word_count[i] > HWD_VIIF_CSI2_MAX_WORD_COUNT ||
> + packet->packet_num[i] > HWD_VIIF_CSI2_MAX_PACKET_NUM) {
> + return -EINVAL;
> + }
> + }
> +
> + writel(HWD_VIIF_INPUT_CSI2, &res->capture_reg->sys.IPORTM);
> +
> + if (vc_main != HWD_VIIF_CSI2_NOT_CAPTURE) {
> + writel((u32)vc_main, &res->capture_reg->sys.VCID0SELECT);
> + enable_vc0 = HWD_VIIF_ENABLE;
> + }
> + if (vc_sub != HWD_VIIF_CSI2_NOT_CAPTURE) {
> + writel((u32)vc_sub, &res->capture_reg->sys.VCID1SELECT);
> + enable_vc1 = HWD_VIIF_ENABLE;
> + }
> +
> + /* configure Embedded Data transfer of MAIN unit */
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN];
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN], 4);
> + config_vdm_wport(res, PORT_SEL_MAIN_EMBED, height, pitch);
> +
> + /* configure Long Packet transfer of MAIN unit */
> + dt = readl(&res->capture_reg->sys.IPORTM_OTHER);
> + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208C ||
> + dt == CSI2_DT_YUV42010C) {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN], 4) +
> + ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] * 2U, 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] >> 1U;
> + } else {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN], 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN];
> + }
> + config_vdm_wport(res, PORT_SEL_MAIN_LONG, height, pitch);
> +
> + /* configure Embedded Data transfer of SUB unit */
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB];
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB], 4);
> + config_vdm_wport(res, PORT_SEL_SUB_EMBED, height, pitch);
> +
> + /* configure Long Packet transfer of SUB unit */
> + dt = readl(&res->capture_reg->sys.IPORTS_OTHER);
> + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV42010 || dt == CSI2_DT_YUV4208C ||
> + dt == CSI2_DT_YUV42010C) {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB], 4) +
> + ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] * 2U, 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] >> 1U;
> + } else {
> + pitch = ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB], 4);
> + height = packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB];
> + }
> + config_vdm_wport(res, PORT_SEL_SUB_LONG, height, pitch);
> +
> + /* Control VC port enable */
> + val = enable_vc0 | (enable_vc1 << 4U);
> + writel(val, &res->capture_reg->sys.VCPORTEN);
> +
> + if (enable_vc0 == HWD_VIIF_ENABLE) {
> + /* Update flag information for run status of MAIN unit */
> + res->run_flag_main = true;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_csi2rx_stop() - Stop CSI-2 input
> + *
> + * Return: 0 Operation completes successfully
> + * Return: -ETIMEDOUT Driver timeout error
> + */
> +s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res)
> +{
> + u32 status_r, status_w, status_t, l2_status;
> + u64 timeout_ns, cur_ns;
> + bool run_flag = true;
> + s32 ret = 0;
> +
> + /* Disable auto transmission of register buffer */
> + writel(0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> + writel(0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
Same here, this doesn't belong to the CSI2RX. Same for VDMAC registers
below, and possibly some of the SYS registers (not sure about those).
Overall, the CSI2RX should be isolated in a subdev separate from the ISP
subdev, with a struct viif_csi2rx to model it. It should only control
the CSI2RX. I'm even tempted to move it to a separate driver, but that
maybe difficult due to usage of the SYS registers by the CSI2RX :-S
> +
> + /* Wait for completion of register buffer transmission */
> + udelay(HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME);
> +
> + /* Stop all VCs, long packet input and emb data input of MAIN unit */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.VCPORTEN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTM_OTHEREN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTM_EMBEN);
> +
> + /* Stop image data input, long packet input and emb data input of SUB unit */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_OTHEREN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_EMBEN);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> +
> + /* Stop VDMAC for all table ports, input ports and write ports */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_T_ENABLE);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_R_ENABLE);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->vdm.VDM_W_ENABLE);
> +
> + /* Stop all groups(g00, g01 and g02) of VDMAC */
> + writel(0x7, &res->capture_reg->vdm.VDM_ABORTSET);
> +
> + timeout_ns = ktime_get_ns() + HWD_VIIF_WAIT_ABORT_COMPLETE_TIME * 1000;
> +
> + do {
> + /* Get VDMAC transfer status */
> + status_r = readl(&res->capture_reg->vdm.VDM_R_RUN);
> + status_w = readl(&res->capture_reg->vdm.VDM_W_RUN);
> + status_t = readl(&res->capture_reg->vdm.VDM_T_RUN);
> +
> + l2_status = readl(&res->capture_reg->l2isp.L2_BUS_L2_STATUS);
> +
> + if (status_r == 0U && status_w == 0U && status_t == 0U && l2_status == 0U)
> + run_flag = false;
> +
> + cur_ns = ktime_get_ns();
> +
> + if (cur_ns > timeout_ns) {
> + ret = -ETIMEDOUT;
> + run_flag = false;
> + }
> + } while (run_flag);
> +
> + if (ret == 0) {
> + /* Clear run flag of MAIN unit */
> + res->run_flag_main = false;
> + }
> +
> + return ret;
> +}
[snip]
> diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h b/drivers/media/platform/visconti/hwd_viif_internal.h
> new file mode 100644
> index 00000000000..c954e804946
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_internal.h
> @@ -0,0 +1,340 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_INTERNAL_H
> +#define HWD_VIIF_INTERNAL_H
> +
> +#include "hwd_viif_reg.h"
> +
> +#define HWD_VIIF_CSI2_MAX_VC (3U)
> +#define HWD_VIIF_CSI2_MIN_DT (0x10U)
> +#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
> +#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
> +#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
> +#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
> +#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
> +#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
> +#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
> +
> +/* maximum horizontal/vertical position/dimension of CROP with ISP */
> +#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
> +#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
> +#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
> +#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
> +
> +/* maximum horizontal/vertical position/dimension of CROP without ISP */
> +#define HWD_VIIF_CROP_MAX_X (1920U)
> +#define HWD_VIIF_CROP_MAX_Y (1408U)
> +#define HWD_VIIF_CROP_MIN_W (128U)
> +#define HWD_VIIF_CROP_MAX_W (2048U)
> +#define HWD_VIIF_CROP_MIN_H (128U)
> +#define HWD_VIIF_CROP_MAX_H (1536U)
> +
> +/* pixel clock: [kHz] */
> +#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
> +#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
> +
> +/* picture size: [pixel], [ns] */
> +#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
> +#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
> +#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
> +#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
> +
> +/* horizontal back porch size: [system clock] */
> +#define HWD_VIIF_HBP_SYSCLK (10U)
> +
> +/* active picture size: [pixel] */
> +#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
> +#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
> +#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
> +#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
> +
> +/* picture vertical size: [line], [packet] */
> +#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
> +#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
> +#define HWD_VIIF_MIN_VBP_LINE (5U)
> +#define HWD_VIIF_MAX_VBP_LINE (4095U)
> +#define HWD_VIIF_MIN_VBP_PACKET (5U)
> +#define HWD_VIIF_MAX_VBP_PACKET (4095U)
> +#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
> +#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
> +#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
> +#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
> +
> +/* image source select */
> +#define HWD_VIIF_INPUT_CSI2 (0U)
This macro is related to a hardware register, and should thus be moved
to the hwd_viif_reg.h file. Same for other macros in this file as
applicable.
> +
> +#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
> +#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
> +#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
> +#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
> +#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
> +#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
> +#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
> +#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
> +#define HWD_VIIF_MAX_PITCH_ISP (32704U)
> +#define HWD_VIIF_MAX_PITCH (65536U)
> +
> +/* size of minimum/maximum input image */
> +#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
> +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
> +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
> +#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
> +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
> +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
> +#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
> +
> +/* size of minimum/maximum output image */
> +#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> +
> +#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> +
> +#define HWD_VIIF_NO_EVENT (0x0U)
Just use 0 in the code, as for HWD_VIIF_DISABLE.
> +
> +/* System clock: [kHz] */
> +#define HWD_VIIF_SYS_CLK (500000UL)
Shouldn't the system clock rate be retrieved dynamically at runtime
(possibly at probe time and cached) with clk_get_rate() instead of being
hardcoded ?
> +
> +/*
> + * wait time for force abort to complete(max 1line time = 1228.8[us]
> + * when width = 4096, RAW24, 80Mbps
> + */
> +#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
> +
> +/*
> + * complete time of register buffer transfer.
> + * actual time is about 30us in case of L1ISP
> + */
> +#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
> +
> +/* internal operation latencies: [system clock]*/
> +#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
> +#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
> +
> +/* offset of Vsync delay: [line] */
> +#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
> +#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
> +
> +/* data width is 32bit */
> +#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
> +
> +/* vsync mode is pulse */
> +#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
> +
> +/* Vlatch mask bit for L1ISP and L2ISP */
> +#define HWD_VIIF_ISP_VLATCH_MASK (2U)
> +
> +/* Register buffer */
> +#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
> +#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
> +#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
> +#define HWD_VIIF_ISP_REGBUF_READ (1U)
[snip]
> +/**
> + * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
> + *
> + * @roi_num: the number of ROIs which are used.
> + * @post_enable_flag: flag to show which of POST is enabled.
> + * @post_crop_x: CROP x of each L2ISP POST
> + * @post_crop_y: CROP y of each L2ISP POST
> + * @post_crop_w: CROP w of each L2ISP POST
> + * @post_crop_h: CROP h of each L2ISP POST
> + */
> +struct hwd_viif_l2_roi_path_info {
> + u32 roi_num;
> + bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
> + u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
> +};
> +
> +/**
> + * struct hwd_viif_res - driver internal resource structure
> + *
> + * @clock_id: clock ID of each unit
> + * @csi2_clock_id: clock ID of CSI-2 RX
> + * @csi2_reset_id: reset ID of CSI-2 RX
> + * @pixel_clock: pixel clock
> + * @htotal_size: horizontal total size
> + * @dt_image_main_w_isp: Data type of image data for ISP path
> + * @csi2host_reg: pointer to register access structure of CSI-2 RX host controller
> + * @capture_reg: pointer to register access structure of capture unit
> + * @l2_roi_path_info: ROI path information of L2ISP
> + * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
> + */
> +struct hwd_viif_res {
> + //u32 clock_id;
> + //u32 csi2_clock_id;
> + //u32 csi2_reset_id;
Please drop commented-out code.
> + u32 pixel_clock;
> + u32 htotal_size;
> + u32 dt_image_main_w_isp;
> + struct hwd_viif_csi2host_reg *csi2host_reg;
> + struct hwd_viif_capture_reg *capture_reg;
> + struct hwd_viif_l2_roi_path_info l2_roi_path_info;
> + bool run_flag_main;
> +};
> +
> +/**
> + * struct hwd_viif_dphy_hs_info - dphy hs information
> + *
> + * @rate: Data rate [Mbps]
> + * @hsfreqrange: IP operating frequency(hsfreqrange)
> + * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
> + */
> +struct hwd_viif_dphy_hs_info {
> + u32 rate;
> + u32 hsfreqrange;
> + u32 osc_freq_target;
> +};
> +
> +#endif /* HWD_VIIF_INTERNAL_H */
> diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h b/drivers/media/platform/visconti/hwd_viif_reg.h
> new file mode 100644
> index 00000000000..b7f43c5fe95
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_reg.h
> @@ -0,0 +1,2802 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef HWD_VIIF_REG_H
> +#define HWD_VIIF_REG_H
> +
> +/**
> + * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST control
> + */
> +struct hwd_viif_csi2host_reg {
As noted by Sakari in his review, kernel drivers usually use macros for
register addresses. I'm not entirely opposed to using structures, but I
share his concerns. Furthermore, macros would allow writing convenience
wrappers around writel():
struct viif_csi2rx
{
...
void __iomem *regs;
...
};
static inline void viif_csi2rx_write(struct viif_csi2rx *csi2rx, u32 reg, u32 val)
{
writel(val, csi2rx->regs + reg);
}
Similar functions can be written for other register spaces. This
improves (I think) code readability (I may be biased though).
In any case, grouping all register definitions in a file, separate from
the rest of the headers, is nice, but register bits should also be
defined in the same file, as macros. For instance, in
viif_csi2rx_initialize() you have
/* Define errors to be masked */
csi2rx_mask.mask[0] = 0x0000000F; /*check all for PHY_FATAL*/
csi2rx_mask.mask[1] = 0x0001000F; /*check all for PKT_FATAL*/
csi2rx_mask.mask[2] = 0x000F0F0F; /*check all for FRAME_FATAL*/
csi2rx_mask.mask[3] = 0x000F000F; /*check all for PHY*/
csi2rx_mask.mask[4] = 0x000F000F; /*check all for PKT*/
csi2rx_mask.mask[5] = 0x00FF00FF; /*check all for LINE*/
return hwd_viif_csi2rx_initialize(viif_dev->hwd_res, num_lane, HWD_VIIF_CSI2_DPHY_L0L1L2L3,
dphy_rate, HWD_VIIF_ENABLE, &err_target, &csi2rx_mask);
where csi2rx_mask is then written to the CSI2RX_INT_MSK_* registers.
Those numerical values should use macros that name the bits. The macros
should be named according to the register they're related to (something
like VIIF_CSI2RX_INT_MSK_PHY_FATAL_* for the CSI2RX_INT_MSK_PHY_FATAL
register for instance). I would also place them right after the
CSI2RX_INT_MSK_PHY_FATAL field below, in order to group registers and
their bits together:
u32 CSI2RX_INT_MSK_PHY_FATAL;
#define VIIF_CSI2RX_INT_MSK_PHY_FATAL_FOO BIT(0)
#define VIIF_CSI2RX_INT_MSK_PHY_FATAL_BAR BIT(1)
...
u32 CSI2RX_INT_FORCE_PHY_FATAL;
...
> + u32 RESERVED_A_1;
> + u32 CSI2RX_NLANES;
> + u32 CSI2RX_RESETN;
> + u32 CSI2RX_INT_ST_MAIN;
> + u32 CSI2RX_DATA_IDS_1;
> + u32 CSI2RX_DATA_IDS_2;
> + u32 RESERVED_B_1[10];
> + u32 CSI2RX_PHY_SHUTDOWNZ;
> + u32 CSI2RX_PHY_RSTZ;
> + u32 CSI2RX_PHY_RX;
> + u32 CSI2RX_PHY_STOPSTATE;
> + u32 CSI2RX_PHY_TESTCTRL0;
> + u32 CSI2RX_PHY_TESTCTRL1;
> + u32 RESERVED_B_2[34];
> + u32 CSI2RX_INT_ST_PHY_FATAL;
> + u32 CSI2RX_INT_MSK_PHY_FATAL;
> + u32 CSI2RX_INT_FORCE_PHY_FATAL;
> + u32 RESERVED_B_3[1];
> + u32 CSI2RX_INT_ST_PKT_FATAL;
> + u32 CSI2RX_INT_MSK_PKT_FATAL;
> + u32 CSI2RX_INT_FORCE_PKT_FATAL;
> + u32 RESERVED_B_4[1];
> + u32 CSI2RX_INT_ST_FRAME_FATAL;
> + u32 CSI2RX_INT_MSK_FRAME_FATAL;
> + u32 CSI2RX_INT_FORCE_FRAME_FATAL;
> + u32 RESERVED_B_5[1];
> + u32 CSI2RX_INT_ST_PHY;
> + u32 CSI2RX_INT_MSK_PHY;
> + u32 CSI2RX_INT_FORCE_PHY;
> + u32 RESERVED_B_6[1];
> + u32 CSI2RX_INT_ST_PKT;
> + u32 CSI2RX_INT_MSK_PKT;
> + u32 CSI2RX_INT_FORCE_PKT;
> + u32 RESERVED_B_7[1];
> + u32 CSI2RX_INT_ST_LINE;
> + u32 CSI2RX_INT_MSK_LINE;
> + u32 CSI2RX_INT_FORCE_LINE;
> + u32 RESERVED_B_8[113];
> + u32 RESERVED_A_2;
> + u32 RESERVED_A_3;
> + u32 RESERVED_A_4;
> + u32 RESERVED_A_5;
> + u32 RESERVED_A_6;
Can this be written
u32 RESERVED_A_2_6[5];
? There are large blocks of reserved registers below, it would help
shortening the file.
> + u32 RESERVED_B_9[58];
> + u32 RESERVED_A_7;
> +};
[snip]
> +/**
> + * struct hwd_viif_l1isp_reg - Registers for VIIF L1ISP control
> + */
> +struct hwd_viif_l1isp_reg {
> + u32 L1_SYSM_WIDTH;
> + u32 L1_SYSM_HEIGHT;
> + u32 L1_SYSM_START_COLOR;
> + u32 L1_SYSM_INPUT_MODE;
> + u32 RESERVED_A_1;
> + u32 L1_SYSM_YCOEF_R;
> + u32 L1_SYSM_YCOEF_G;
> + u32 L1_SYSM_YCOEF_B;
> + u32 L1_SYSM_INT_STAT;
> + u32 L1_SYSM_INT_MASKED_STAT;
> + u32 L1_SYSM_INT_MASK;
> + u32 RESERVED_A_2;
> + u32 RESERVED_A_3;
> + u32 RESERVED_A_4;
> + u32 RESERVED_B_1[2];
> + u32 L1_SYSM_AG_H;
> + u32 L1_SYSM_AG_M;
> + u32 L1_SYSM_AG_L;
> + u32 L1_SYSM_AG_PARAM_A;
> + u32 L1_SYSM_AG_PARAM_B;
> + u32 L1_SYSM_AG_PARAM_C;
> + u32 L1_SYSM_AG_PARAM_D;
> + u32 L1_SYSM_AG_SEL_HOBC;
> + u32 L1_SYSM_AG_SEL_ABPC;
> + u32 L1_SYSM_AG_SEL_RCNR;
> + u32 L1_SYSM_AG_SEL_LSSC;
> + u32 L1_SYSM_AG_SEL_MPRO;
> + u32 L1_SYSM_AG_SEL_VPRO;
> + u32 L1_SYSM_AG_CONT_HOBC01_EN;
> + u32 L1_SYSM_AG_CONT_HOBC2_EN;
> + u32 L1_SYSM_AG_CONT_ABPC01_EN;
> + u32 L1_SYSM_AG_CONT_ABPC2_EN;
> + u32 L1_SYSM_AG_CONT_RCNR01_EN;
> + u32 L1_SYSM_AG_CONT_RCNR2_EN;
> + u32 L1_SYSM_AG_CONT_LSSC_EN;
> + u32 L1_SYSM_AG_CONT_MPRO_EN;
> + u32 L1_SYSM_AG_CONT_VPRO_EN;
> + u32 L1_SYSM_CTXT;
> + u32 L1_SYSM_MAN_CTXT;
> + u32 RESERVED_A_5;
> + u32 RESERVED_B_2[7];
> + u32 RESERVED_A_6;
> + u32 L1_HDRE_SRCPOINT00;
> + u32 L1_HDRE_SRCPOINT01;
> + u32 L1_HDRE_SRCPOINT02;
> + u32 L1_HDRE_SRCPOINT03;
> + u32 L1_HDRE_SRCPOINT04;
> + u32 L1_HDRE_SRCPOINT05;
> + u32 L1_HDRE_SRCPOINT06;
> + u32 L1_HDRE_SRCPOINT07;
> + u32 L1_HDRE_SRCPOINT08;
> + u32 L1_HDRE_SRCPOINT09;
> + u32 L1_HDRE_SRCPOINT10;
> + u32 L1_HDRE_SRCPOINT11;
> + u32 L1_HDRE_SRCPOINT12;
> + u32 L1_HDRE_SRCPOINT13;
> + u32 L1_HDRE_SRCPOINT14;
> + u32 L1_HDRE_SRCPOINT15;
This also seems to be a candidate for an array:
u32 L1_HDRE_SRCPOINT[16];
Not only will it shorten this file, it will also make the code simpler
as you'll be able to replace
writel(param->hdre_src_point[0], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT00);
writel(param->hdre_src_point[1], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT01);
writel(param->hdre_src_point[2], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT02);
writel(param->hdre_src_point[3], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT03);
writel(param->hdre_src_point[4], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT04);
writel(param->hdre_src_point[5], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT05);
writel(param->hdre_src_point[6], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT06);
writel(param->hdre_src_point[7], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT07);
writel(param->hdre_src_point[8], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT08);
writel(param->hdre_src_point[9], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT09);
writel(param->hdre_src_point[10], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT10);
writel(param->hdre_src_point[11], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT11);
writel(param->hdre_src_point[12], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT12);
writel(param->hdre_src_point[13], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT13);
writel(param->hdre_src_point[14], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT14);
writel(param->hdre_src_point[15], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT15);
with
for (i = 0; i < ARRAY_SIZE(param->hdre_src_point); ++i)
writel(param->hdre_src_point[i], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT[i]);
Same in quite a few other locations.
[snip]
> +};
[snip]
> diff --git a/include/uapi/linux/visconti_viif.h b/include/uapi/linux/visconti_viif.h
> new file mode 100644
> index 00000000000..f92278425b7
> --- /dev/null
> +++ b/include/uapi/linux/visconti_viif.h
> @@ -0,0 +1,1724 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef __UAPI_VISCONTI_VIIF_H_
> +#define __UAPI_VISCONTI_VIIF_H_
> +
> +#include <linux/types.h>
> +#include <linux/videodev2.h>
> +
> +/* Visconti specific compound controls */
> +#define V4L2_CID_VISCONTI_VIIF_BASE (V4L2_CID_USER_BASE + 0x1000)
> +#define V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 1)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 2)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF (V4L2_CID_VISCONTI_VIIF_BASE + 3)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE (V4L2_CID_VISCONTI_VIIF_BASE + 4)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG (V4L2_CID_VISCONTI_VIIF_BASE + 5)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE (V4L2_CID_VISCONTI_VIIF_BASE + 6)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION (V4L2_CID_VISCONTI_VIIF_BASE + 7)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC (V4L2_CID_VISCONTI_VIIF_BASE + 8)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE (V4L2_CID_VISCONTI_VIIF_BASE + 9)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION \
> + (V4L2_CID_VISCONTI_VIIF_BASE + 10)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS (V4L2_CID_VISCONTI_VIIF_BASE + 11)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION (V4L2_CID_VISCONTI_VIIF_BASE + 12)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC (V4L2_CID_VISCONTI_VIIF_BASE + 13)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS (V4L2_CID_VISCONTI_VIIF_BASE + 14)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB (V4L2_CID_VISCONTI_VIIF_BASE + 15)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN (V4L2_CID_VISCONTI_VIIF_BASE + 16)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC (V4L2_CID_VISCONTI_VIIF_BASE + 17)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM (V4L2_CID_VISCONTI_VIIF_BASE + 18)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 19)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT (V4L2_CID_VISCONTI_VIIF_BASE + 20)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION (V4L2_CID_VISCONTI_VIIF_BASE + 21)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST (V4L2_CID_VISCONTI_VIIF_BASE + 22)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI (V4L2_CID_VISCONTI_VIIF_BASE + 23)
> +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA (V4L2_CID_VISCONTI_VIIF_BASE + 24)
> +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 25)
> +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 26)
> +#define V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS (V4L2_CID_VISCONTI_VIIF_BASE + 27)
> +#define V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS (V4L2_CID_VISCONTI_VIIF_BASE + 28)
First of all, thank you for taking the time to write all these, as well
as the control documentation.
This is a *lot* of controls, and each of them store a potentially large
quantity of data. Unless I'm mistaken, the driver doesn't use the
request API, which means that there's no synchronization between control
values and frames. Isn't that a problem ? I'm wondering if a mechanism
based on parameters buffers (like the rkisp1 driver for instance)
wouldn't be a better fit.
> +/* Enable/Disable flag */
> +#define VIIF_DISABLE (0U)
> +#define VIIF_ENABLE (1U)
No need for parentheses.
[snip]
> +#endif /* __UAPI_VISCONTI_VIIF_H_ */
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver
2023-01-18 0:52 ` Laurent Pinchart
@ 2023-02-02 4:37 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-02 4:37 UTC (permalink / raw)
To: laurent.pinchart
Cc: hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Laurent,
Thank you for your comments.
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Wednesday, January 18, 2023 9:53 AM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>
> Cc: Hans Verkuil <hverkuil@xs4all.nl>; Mauro Carvalho Chehab
> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>;
> linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver
>
> Hi Yuji,
>
> Thank you for the patch.
>
> I'll comment on the high-level design first (with a few ad-hoc more
> detailed comments here and there).
>
> On Wed, Jan 11, 2023 at 11:24:29AM +0900, Yuji Ishikawa wrote:
> > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > The interface device includes CSI2 Receiver,
> > frame grabber, video DMAC and image signal processor.
> > This patch provides operations to handle registers of HW listed above.
> >
> > The Video DMACs have 32bit address space
> > and currently corresponding IOMMU driver is not provided.
> > Therefore, memory-block address for captured image is 32bit IOVA
> > which is equal to 32bit-truncated phisical address.
> > When the Visconti IOMMU driver (currently under development) is accepted,
> > the hardware layer will use 32bit IOVA mapped by the attached IOMMU.
> >
> > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > ---
> > Changelog v2:
> > - Resend v1 because a patch exceeds size limit.
> >
> > Changelog v3:
> > - Adapted to media control framework
> > - Introduced ISP subdevice, capture device
> > - Remove private IOCTLs and add vendor specific V4L2 controls
> > - Change function name avoiding camelcase and uppercase letters
> >
> > Changelog v4:
> > - Split patches because the v3 patch exceeds size limit
> > - Stop using ID number to identify driver instance:
> > - Use dynamically allocated structure to hold driver's context,
> > instead of static one indexed by ID number.
> > - Functions accept driver's context structure instead of ID number.
> >
> > Changelog v5:
> > - no change
> > ---
> > drivers/media/platform/Kconfig | 1 +
> > drivers/media/platform/Makefile | 1 +
> > drivers/media/platform/visconti/Kconfig | 9 +
> > drivers/media/platform/visconti/Makefile | 8 +
> > drivers/media/platform/visconti/hwd_viif.c | 1690 ++++++++++
> > drivers/media/platform/visconti/hwd_viif.h | 710 +++++
> > .../media/platform/visconti/hwd_viif_csi2rx.c | 610 ++++
> > .../platform/visconti/hwd_viif_internal.h | 340 ++
> > .../media/platform/visconti/hwd_viif_reg.h | 2802
> +++++++++++++++++
> > include/uapi/linux/visconti_viif.h | 1724 ++++++++++
> > 10 files changed, 7895 insertions(+)
> > create mode 100644 drivers/media/platform/visconti/Kconfig
> > create mode 100644 drivers/media/platform/visconti/Makefile
> > create mode 100644 drivers/media/platform/visconti/hwd_viif.c
> > create mode 100644 drivers/media/platform/visconti/hwd_viif.h
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_internal.h
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_reg.h
> > create mode 100644 include/uapi/linux/visconti_viif.h
>
> This file split makes it quite hard to navigate and understand the
> driver for people who are not familiar with it (at least for me) :-S It
> would be nice to split the driver based on functional area, for instance
> as follows:
>
> - viif.c (or viif_drv.c): Top-level driver file, as already done in v5
> - viif_csi2rx.c: CSI-2 receiver support code
> - viif_l1isp.c: L1 ISP support
> - viif_l2isp.c: L2 ISP support
> - viif_capture.c: V4L2 video node support
>
> Each of those files should have a corresponding header file to declare
> functions and define the related macros and structures that are used by
> *other* .c files. Macros and structures that are internal to a .c file
> should be defined there.
I'll follow the advised layout of files.
I'm currently not for sure if L1 and L2 ISP support can be written separately. Let me try.
> - viif_reg.h: Register addresses and macros
>
> I'm tempted to split the CSI-2 RX registers from viif_reg.h to
> viif_csi2rx_reg.h.
I'll move CSI-2 RX registers and related definitions to a new file.
> As for the code currently stored in the hwd_*.c files, it could be kept
> separate, or be integrated in the corresponding *.c file, up to you. If
> you prefer keeping it separate, I would name the files viif_*_hw.c (e.g.
> viif_csi2rx_hw.c).
All right. I'll rename them to viif_*_hw.c if they exist after refactoring.
> I'll cut parts of the original part out of the reply, as the result
> would be too large for the mailing list.
>
> [snip]
>
> > # Please place here only ancillary drivers that aren't SoC-specific
> > diff --git a/drivers/media/platform/visconti/Kconfig
> b/drivers/media/platform/visconti/Kconfig
> > new file mode 100644
> > index 00000000000..031e4610809
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/Kconfig
> > @@ -0,0 +1,9 @@
>
> Please add an SPDX header.
I'll add it.
> > +config VIDEO_VISCONTI_VIIF
> > + tristate "Visconti Camera Interface driver"
> > + depends on V4L_PLATFORM_DRIVERS && MEDIA_CONTROLLER &&
> VIDEO_DEV
> > + depends on ARCH_VISCONTI
> > + select VIDEOBUF2_DMA_CONTIG
> > + select V4L2_FWNODE
>
> You also need V4L2_ASYNC and VIDEO_V4L2_SUBDEV_API. Sort them
> alphabetically:
I'll add them.
> select V4L2_ASYNC
> select V4L2_FWNODE
> select VIDEOBUF2_DMA_CONTIG
> select VIDEO_V4L2_SUBDEV_API
>
> > + help
> > + This is V4L2 driver for Toshiba Visconti Camera Interface driver
> > +
>
> [snip]
>
> > diff --git a/drivers/media/platform/visconti/hwd_viif.c
> b/drivers/media/platform/visconti/hwd_viif.c
> > new file mode 100644
> > index 00000000000..260293fa4d0
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif.c
> > @@ -0,0 +1,1690 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "hwd_viif.h"
> > +#include "hwd_viif_internal.h"
> > +
> > +/* MIPI CSI2 DataType definition */
> > +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> > +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> > +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> > +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> > +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> > +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> > +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> > +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
>
> You can drop this and replace it with the macros defined in
> include/media/mipi-csi2.h.
I'll use the definitiions in media/mipi-csi2.h .
> > +
> > +struct hwd_viif_res *allocate_viif_res(struct device *dev, void
> *csi2host_vaddr,
> > + void *capture_vaddr)
> > +{
> > + struct hwd_viif_res *res = devm_kzalloc(dev, sizeof(struct hwd_viif_res),
> GFP_KERNEL);
>
> Don't allocate this dynamically, it can be embedded in the viif_device
> structure.
I'll embed it to struct viif_device.
> > +
> > + res->csi2host_reg = csi2host_vaddr;
> > + res->capture_reg = capture_vaddr;
> > + res->run_flag_main = (bool)false;
> > + return res;
> > +}
>
> [snip]
>
> > +#define VDM_BIT_W00 BIT(0)
> > +#define VDM_BIT_W01 BIT(1)
> > +#define VDM_BIT_W02 BIT(2)
> > +#define VDM_BIT_W03 BIT(3)
> > +#define VDM_BIT_W04 BIT(4)
> > +#define VDM_BIT_W05 BIT(5)
> > +#define VDM_BIT_R00 BIT(0)
> > +#define VDM_BIT_R01 BIT(1)
> > +#define VDM_BIT_R02 BIT(2)
> > +
> > +#define VDM_ABORT_MASK_SUB_W (VDM_BIT_W03 | VDM_BIT_W04 |
> VDM_BIT_W05)
> > +#define VDM_ABORT_MASK_MAIN_W (VDM_BIT_W00 | VDM_BIT_W01 |
> VDM_BIT_W02)
> > +#define VDM_ABORT_MASK_MAIN_R (VDM_BIT_R00 | VDM_BIT_R01 |
> VDM_BIT_R02)
>
> None of these are used.
I'll remove them. Same for other unused definitions.
> > +/**
> > + * hwd_viif_l2_set_img_transmission() - Set image transfer condition of
> L2ISP
> > + *
> > + * @post_id: POST ID [0..1]
> > + * @enable: or disable image transfer of MAIN unit. For more refer @ref
> hwd_viif_enable_flag.
> > + * @src: Pointer to crop area information
> > + * @out_process: Pointer to output process information
> > + * @img: Pointer to output image information
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "post_id" or "enable" is out of range
> > + * - [2] "src" or "out_process" is NULL when "enable" is HWD_VIIF_ENABLE
> > + * - [3] "src" or "out_process" is not NULL when "enable" is
> HWD_VIIF_DISABLE
> > + * - [4] Member of "src" is out of range
> > + * - [5] "w" of "src" is not equal to 2 * "width" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> > + * - [6] "h" of "src" is not equal to 2 * "height" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_ENABLE
> > + * - [7] "w" of "src" is not equal to "width" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> > + * - [8] "h" of "src" is not equal to "height" of "image"
> > + * when "half_scal" of "out_process" is HWD_VIIF_DISABLE
> > + * - [9] Member of "out_process" is invalid
> > + * - [10] "alpha" of "out_process" is not 0 when "format" of "img" is not
> HWD_VIIF_ARGB8888_PACKED
> > + * - [11] "format" of "img" is not HWD_VIIF_ONE_COLOR_8 or
> HWD_VIIF_ONE_COLOR_16
> > + * when "select_color" of "out_process"
> > + * is HWD_VIIF_COLOR_Y_G, HWD_VIIF_COLOR_U_B or
> HWD_VIIF_COLOR_V_R
> > + * - [12] Member of "img" is invalid
> > + *
> > + * see also: #hwd_viif_l2_set_roi_path
> > + */
> > +s32 hwd_viif_l2_set_img_transmission(struct hwd_viif_res *res, u32 post_id,
> u32 enable,
> > + const struct hwd_viif_img_area *src,
> > + const struct hwd_viif_out_process
> *out_process,
> > + const struct hwd_viif_img *img)
> > +{
> > + u32 pitch[HWD_VIIF_MAX_PLANE_NUM],
> img_start_addr[HWD_VIIF_MAX_PLANE_NUM];
> > + u32 i, val, loop, k, r[HWD_VIIF_MAX_PLANE_NUM];
> > + s32 ret = 0;
> > +
> > + /* pitch alignment for planar or one color format */
> > + u32 pitch_align = 128U;
>
> [snip]
>
> > + /* build DMAC parameter */
> > + switch (img->format) {
> > + case HWD_VIIF_YCBCR422_8_PACKED:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 2U;
> > + r[0] = 1U;
> > + pitch_align = 256U;
> > + break;
> > + case HWD_VIIF_RGB888_PACKED:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 3U;
> > + r[0] = 1U;
> > + pitch_align = 384U;
> > + break;
> > + case HWD_VIIF_ARGB8888_PACKED:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 4U;
> > + r[0] = 1U;
> > + pitch_align = 512U;
> > + break;
> > + case HWD_VIIF_ONE_COLOR_8:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 1U;
> > + r[0] = 1U;
> > + break;
> > + case HWD_VIIF_ONE_COLOR_16:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + loop = 1U;
> > + k = 2U;
> > + r[0] = 1U;
> > + break;
> > + case HWD_VIIF_YCBCR422_8_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 1U;
> > + r[0] = 1U;
> > + r[1] = 2U;
> > + r[2] = 2U;
> > + break;
> > + case HWD_VIIF_RGB888_YCBCR444_8_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 1U;
> > + r[0] = 1U;
> > + r[1] = 1U;
> > + r[2] = 1U;
> > + break;
> > + case HWD_VIIF_YCBCR422_16_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 2U;
> > + r[0] = 1U;
> > + r[1] = 2U;
> > + r[2] = 2U;
> > + break;
> > + case HWD_VIIF_RGB161616_YCBCR444_16_PLANAR:
> > + img_start_addr[0] = (u32)img->pixelmap[0].pmap_paddr;
> > + img_start_addr[1] = (u32)img->pixelmap[1].pmap_paddr;
> > + img_start_addr[2] = (u32)img->pixelmap[2].pmap_paddr;
> > + pitch[0] = img->pixelmap[0].pitch;
> > + pitch[1] = img->pixelmap[1].pitch;
> > + pitch[2] = img->pixelmap[2].pitch;
> > + loop = HWD_VIIF_MAX_PLANE_NUM;
> > + k = 2U;
> > + r[0] = 1U;
> > + r[1] = 1U;
> > + r[2] = 1U;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
>
> This is lots of code that could be replaced with static data. Create
>
> struct viif_format_info {
> u32 format;
> unsigned int num_planes;
> unsigned int bpp;
> /* whatever other fields are needed */
> };
>
> in viif.h, and add to viif.c a static table of those
>
> static const struct viif_format_info viif_formats[] = {
> {
> .format = HWD_VIIF_YCBCR422_8_PACKED,
> .num_planes = 1
> .bpp = 2,
> }, {
> ...
> },
> };
>
> with a lookup function
>
> const struct viif_format_info viif_format_info(u32 format)
> {
> unsigned int i;
>
> for (i = 0; i < ARRAY_SIZE(viif_formats); ++i) {
> if (viif_formats[i].format == format)
> return &viif_formats[i];
> }
>
> return NULL;
> }
>
> You can then use this wherever you need per-format information through
> the driver. I suspect it will be useful to store other per-format
> information, such as the V4L2 pixel format for instance.
>
> Now that I wrote this, it seems you already have such a structure called
> viif_fmt in a subsequent patch, with a static array. Move them to viif.c
> and viif.h, extend the structure with the hardware format, are use it
> through the driver.
Thank you for the detailed advice.
I'll move it to a new table.
> > +
> > + for (i = 0; i < loop; i++) {
> > + val = max(((img->width * k) / r[i]), 128U);
> > + if (pitch[i] < val || pitch[i] > HWD_VIIF_MAX_PITCH_ISP ||
> > + ((pitch[i] % pitch_align) != 0U) || ((img_start_addr[i] %
> 4U) != 0U)) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + writel(img_start_addr[0],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_G);
> > + writel(pitch[0],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_G);
> > + if (loop == HWD_VIIF_MAX_PLANE_NUM) {
> > + writel(img_start_addr[1],
> > +
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_B);
> > + writel(img_start_addr[2],
> > +
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_STADR_R);
> > + writel(pitch[1],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_B);
> > + writel(pitch[2],
> &res->capture_reg->l2isp.post[post_id].L2_POST_OUT_PITCH_R);
> > + }
> > +
> > + /* Set CROP */
> > + val = (src->y << 16U) | src->x;
> > + writel(val,
> &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_OFFSET);
> > + val = (src->h << 16U) | src->w;
> > + writel(val,
> &res->capture_reg->l2isp.post[post_id].L2_POST_CAP_SIZE);
> > +
> > + /* Set output process */
> > + writel(out_process->half_scale,
> > +
> &res->capture_reg->l2isp.post[post_id].L2_POST_HALF_SCALE_EN);
> > + writel(out_process->select_color,
> &res->capture_reg->l2isp.post[post_id].L2_POST_C_SELECT);
> > + writel((u32)out_process->alpha,
> &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTALP);
> > + writel(img->format,
> &res->capture_reg->l2isp.post[post_id].L2_POST_OPORTFMT);
> > +
> > + /* Update ROI area and input to each POST */
> > + res->l2_roi_path_info.post_enable_flag[post_id] = true;
> > + res->l2_roi_path_info.post_crop_x[post_id] = src->x;
> > + res->l2_roi_path_info.post_crop_y[post_id] = src->y;
> > + res->l2_roi_path_info.post_crop_w[post_id] = src->w;
> > + res->l2_roi_path_info.post_crop_h[post_id] = src->h;
> > + hwd_viif_l2_set_roi_path(res);
> > +
> > + return ret;
> > +}
>
> [snip]
>
> > diff --git a/drivers/media/platform/visconti/hwd_viif.h
> b/drivers/media/platform/visconti/hwd_viif.h
> > new file mode 100644
> > index 00000000000..100afda8436
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif.h
> > @@ -0,0 +1,710 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_H
> > +#define HWD_VIIF_H
> > +
> > +#include <linux/errno.h>
> > +#include <linux/types.h>
> > +
> > +#include <linux/visconti_viif.h>
> > +
> > +enum hwd_power_ctrl {
> > + HWD_POWER_OFF = 0, /**< Power off */
> > + HWD_POWER_ON /**< Power on */
> > +};
>
> Not used.
I'll remove it.
> > +
> > +/* MIPI CSI2 Data Types */
> > +#define VISCONTI_CSI2_DT_YUV4228B 0x1E
> > +#define VISCONTI_CSI2_DT_YUV42210B 0x1F
> > +#define VISCONTI_CSI2_DT_RGB565 0x22
> > +#define VISCONTI_CSI2_DT_RGB888 0x24
> > +#define VISCONTI_CSI2_DT_RAW8 0x2A
> > +#define VISCONTI_CSI2_DT_RAW10 0x2B
> > +#define VISCONTI_CSI2_DT_RAW12 0x2C
> > +#define VISCONTI_CSI2_DT_RAW14 0x2D
>
> You can drop this and replace it with the macros defined in
> include/media/mipi-csi2.h.
I'll use the definitions in media/mipi-csi2.h .
> > +
> > +/* hwd_viif_enable_flag */
> > +#define HWD_VIIF_DISABLE (0U)
>
> No need for parentheses, here and below.
I'll fix it. Same for similar definitions.
> > +#define HWD_VIIF_ENABLE (1U)
>
> false/true or 0/1 would be more readable in the code.
For struct members and variables, I'll use false/true.
e.g: "enable != HWD_VIIF_ENABLE"; the variable "half_scale" should be boolean type instead of u32, as Sakari advised.
For writing registers. 0/1 would be better.
e.g: "writel(HWD_VIIF_ENABLE, ®_l2isp_post->csc.MTB);"
> > +
> > +/* hwd_viif_memory_sync_type */
> > +#define HWD_VIIF_MEM_SYNC_INTERNAL (0U)
> > +#define HWD_VIIF_MEM_SYNC_CSI2 (1U)
>
> This isn't used anywhere.
I'll remove them.
> > +
> > +/* hwd_viif_color_format */
> > +#define HWD_VIIF_YCBCR422_8_PACKED (0U)
> > +#define HWD_VIIF_RGB888_PACKED (1U)
> > +#define HWD_VIIF_ARGB8888_PACKED (3U)
> > +#define HWD_VIIF_YCBCR422_8_PLANAR (8U)
> > +#define HWD_VIIF_RGB888_YCBCR444_8_PLANAR (9U)
> > +#define HWD_VIIF_ONE_COLOR_8 (11U)
> > +#define HWD_VIIF_YCBCR422_16_PLANAR (12U)
> > +#define HWD_VIIF_RGB161616_YCBCR444_16_PLANAR (13U)
> > +#define HWD_VIIF_ONE_COLOR_16 (15U)
>
> Could this be turned into an enum ?
>
> enum hwd_viif_color_format {
> HWD_VIIF_YCBCR422_8_PACKED = 0U,
> HWD_VIIF_RGB888_PACKED = 1U,
> HWD_VIIF_ARGB8888_PACKED = 3U,
> HWD_VIIF_YCBCR422_8_PLANAR = 8U,
> HWD_VIIF_RGB888_YCBCR444_8_PLANAR = 9U,
> HWD_VIIF_ONE_COLOR_8 = 11U,
> HWD_VIIF_YCBCR422_16_PLANAR = 12U,
> HWD_VIIF_RGB161616_YCBCR444_16_PLANAR = 13U,
> HWD_VIIF_ONE_COLOR_16 = 15U,
> };
>
> Then you'll be able to use the enum in variables, function parameters
> and structure fields, for instance
>
> struct hwd_viif_img {
> u32 width;
> u32 height;
> enum hwd_viif_color_format format;
> struct hwd_viif_pixelmap pixelmap[3];
> };
>
> which will make it clearer through the code which types and values are
> expected in a given place.
>
> Same for all other macros where this would be applicable.
I'll move them to enum. Same for similar cases.
> > +
> > +/* hwd_viif_raw_pack_mode */
> > +#define HWD_VIIF_RAWPACK_DISABLE (0U)
> > +#define HWD_VIIF_RAWPACK_MSBFIRST (2U)
> > +#define HWD_VIIF_RAWPACK_LSBFIRST (3U)
> > +
> > +/* hwd_viif_yuv_conversion_mode */
> > +#define HWD_VIIF_YUV_CONV_REPEAT (0U)
> > +#define HWD_VIIF_YUV_CONV_INTERPOLATION (1U)
> > +
> > +/* hwd_viif_gamma_table_mode */
> > +#define HWD_VIIF_GAMMA_COMPRESSED (0U)
> > +#define HWD_VIIF_GAMMA_LINEAR (1U)
> > +
> > +/* hwd_viif_output_color_mode */
> > +#define HWD_VIIF_COLOR_Y_G (0U)
> > +#define HWD_VIIF_COLOR_U_B (1U)
> > +#define HWD_VIIF_COLOR_V_R (2U)
> > +#define HWD_VIIF_COLOR_YUV_RGB (4U)
> > +
> > +/* hwd_viif_hw_params */
> > +#define HWD_VIIF_MAX_CH (6U)
>
> This isn't used.
>
> Could you go through this file and delete all the macros that are not
> used and that you don't plan to use in the future ?
I'll remove unused definitions.
> > +#define HWD_VIIF_MAX_PLANE_NUM (3U)
>
> This is used inside the hwd_viif_l2_set_img_transmission() function
> only. I'm really tempted to move definitions of macros that are local to
> a function in the corresponding .c file, just before the function. This
> file is huge, and quite difficult to read, anything that would shrink it
> would be nice.
I'll move definitions to local place as possible.
> > +
> > +/**
> > + * enum hwd_viif_csi2_dphy - D-PHY Lane assignment
> > + *
> > + * specifies which line(L0-L3) is assigned to D0-D3
> > + */
> > +enum hwd_viif_csi2_dphy {
> > + HWD_VIIF_CSI2_DPHY_L0L1L2L3 = 0U,
> > + HWD_VIIF_CSI2_DPHY_L0L3L1L2 = 1U,
> > + HWD_VIIF_CSI2_DPHY_L0L2L3L1 = 2U,
> > + HWD_VIIF_CSI2_DPHY_L0L1L3L2 = 4U,
> > + HWD_VIIF_CSI2_DPHY_L0L3L2L1 = 5U,
> > + HWD_VIIF_CSI2_DPHY_L0L2L1L3 = 6U
> > +};
> > +
> > +/* hwd_viif_csi2rx_cal_status */
> > +#define HWD_VIIF_CSI2_CAL_NOT_DONE (0U)
> > +#define HWD_VIIF_CSI2_CAL_SUCCESS (1U)
> > +#define HWD_VIIF_CSI2_CAL_FAIL (2U)
>
> Custom error codes are usually frowned upon, especially when success is
> signaled by a value other than 0. How about using 0 for success, -EAGAIN
> for NOT_DONE, and -EIO for failure ? Same comment for other custom
> status values, if any.
These values are used for description of each CSI2 data lane in V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS control,
They are not used for public functions's return code.
Can I use -EAGAIN and -EIO to describe status of a hardware?
> > +
> > +/* hwd_viif_csi2rx_not_capture */
> > +#define HWD_VIIF_CSI2_NOT_CAPTURE (-1) /**< csi2 not capture */
>
> [snip]
>
> > +
> > +/* hwd_viif_l1_input_mode */
> > +#define HWD_VIIF_L1_INPUT_HDR (0U)
> > +#define HWD_VIIF_L1_INPUT_PWL (1U)
> > +#define HWD_VIIF_L1_INPUT_SDR (2U)
> > +#define HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT (3U)
> > +#define HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT (4U)
> > +
> > +/* hwd_viif_l1_raw_color_filter_mode */
> > +#define HWD_VIIF_L1_RAW_GR_R_B_GB (0U)
> > +#define HWD_VIIF_L1_RAW_R_GR_GB_B (1U)
> > +#define HWD_VIIF_L1_RAW_B_GB_GR_R (2U)
> > +#define HWD_VIIF_L1_RAW_GB_B_R_GR (3U)
> > +
> > +/* hwd_viif_l1_input_interpolation_mode */
> > +#define HWD_VIIF_L1_INPUT_INTERPOLATION_LINE (0U)
> > +#define HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL (1U)
> > +
> > +/* hwd_viif_l1_img_sens */
> > +#define HWD_VIIF_L1_IMG_SENSITIVITY_HIGH (0U)
> > +#define HWD_VIIF_L1_IMG_SENSITIVITY_MIDDLE_LED (1U)
> > +#define HWD_VIIF_L1_IMG_SENSITIVITY_LOW (2U)
> > +
> > +/* hwd_viif_l1_dpc */
> > +#define HWD_VIIF_L1_DPC_1PIXEL (0U)
> > +#define HWD_VIIF_L1_DPC_2PIXEL (1U)
> > +
> > +/* hwd_viif_l1_rcnr_hry_type */
> > +#define HWD_VIIF_L1_RCNR_LOW_RESOLUTION (0U)
> > +#define HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION (1U)
> > +#define HWD_VIIF_L1_RCNR_HIGH_RESOLUTION (2U)
> > +#define HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION (3U)
> > +
> > +/* hwd_viif_l1_rcnr_msf_blend_ratio */
> > +#define HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 (0U)
> > +#define HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 (1U)
> > +#define HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64 (2U)
> > +
> > +/* hwd_viif_l1_hdrs */
> > +#define HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE (0U)
> > +#define HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE (1U)
> > +
> > +/* hwd_viif_l1_lsc_para_mag */
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH (0U)
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH (1U)
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND (2U)
> > +#define HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST (3U)
> > +
> > +/* hwd_viif_l1_lsc_grid_mag */
> > +#define HWD_VIIF_L1_GRID_COEF_GAIN_X1 (0U)
> > +#define HWD_VIIF_L1_GRID_COEF_GAIN_X2 (1U)
> > +
> > +/* hwd_viif_l1_demosaic */
> > +#define HWD_VIIF_L1_DEMOSAIC_ACPI (0U)
> > +#define HWD_VIIF_L1_DEMOSAIC_DMG (1U)
> > +
> > +/* hwd_viif_l1_awb_restart_cond */
> > +/* macros for L1ISP condition to restart auto white balance */
> > +#define HWD_VIIF_L1_AWB_RESTART_NO (0U)
> > +#define HWD_VIIF_L1_AWB_RESTART_128FRAME (1U)
> > +#define HWD_VIIF_L1_AWB_RESTART_64FRAME (2U)
> > +#define HWD_VIIF_L1_AWB_RESTART_32FRAME (3U)
> > +#define HWD_VIIF_L1_AWB_RESTART_16FRAME (4U)
> > +#define HWD_VIIF_L1_AWB_RESTART_8FRAME (5U)
> > +#define HWD_VIIF_L1_AWB_RESTART_4FRAME (6U)
> > +#define HWD_VIIF_L1_AWB_RESTART_2FRAME (7U)
> > +
> > +/* hwd_viif_l1_awb_mag */
> > +#define HWD_VIIF_L1_AWB_ONE_SECOND (0U)
> > +#define HWD_VIIF_L1_AWB_X1 (1U)
> > +#define HWD_VIIF_L1_AWB_X2 (2U)
> > +#define HWD_VIIF_L1_AWB_X4 (3U)
> > +
> > +/* hwd_viif_l1_awb_area_mode */
> > +#define HWD_VIIF_L1_AWB_AREA_MODE0 (0U)
> > +#define HWD_VIIF_L1_AWB_AREA_MODE1 (1U)
> > +#define HWD_VIIF_L1_AWB_AREA_MODE2 (2U)
> > +#define HWD_VIIF_L1_AWB_AREA_MODE3 (3U)
> > +
> > +/* hwd_viif_l1_hdrc_tone_type */
> > +#define HWD_VIIF_L1_HDRC_TONE_USER (0U)
> > +#define HWD_VIIF_L1_HDRC_TONE_PRESET (1U)
> > +
> > +/* hwd_viif_l1_bin_mode */
> > +#define HWD_VIIF_L1_HIST_BIN_MODE_LINEAR (0U)
> > +#define HWD_VIIF_L1_HIST_BIN_MODE_LOG (1U)
> > +
> > +/* hwd_viif_l2_undist_mode */
> > +#define HWD_VIIF_L2_UNDIST_POLY (0U)
> > +#define HWD_VIIF_L2_UNDIST_GRID (1U)
> > +#define HWD_VIIF_L2_UNDIST_POLY_TO_GRID (2U)
> > +#define HWD_VIIF_L2_UNDIST_GRID_TO_POLY (3U)
> > +
> > +/**
> > + * struct hwd_viif_csi2rx_line_err_target
> > + *
> > + * Virtual Channel and Data Type pair for CSI2RX line error monitor
> > + *
> > + * When 0 is set to dt, line error detection is disabled.
> > + *
> > + * * VC can be 0 .. 3
> > + * * DT can be 0 or 0x10 .. 0x3F
> > + */
> > +#define VISCONTI_CSI2_ERROR_MONITORS_NUM 8
> > +struct hwd_viif_csi2rx_line_err_target {
> > + u32 vc[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> > + u32 dt[VISCONTI_CSI2_ERROR_MONITORS_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_csi2rx_irq_mask
> > + * @mask: mask setting for CSI2RX error interruption
> > + *
> > + * * mask[0]: D-PHY fatal error
> > + * * mask[1]: Packet fatal error
> > + * * mask[2]: Frame fatal error
> > + * * mask[3]: D-PHY error
> > + * * mask[4]: Packet error
> > + * * mask[5]: Line error
> > + */
> > +#define VISCONTI_CSI2RX_IRQ_MASKS_NUM 6
> > +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_FATAL 0
> > +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_FATAL 1
> > +#define VISCONTI_CSI2RX_IRQ_MASK_FRAME_FATAL 2
> > +#define VISCONTI_CSI2RX_IRQ_MASK_DPHY_ERROR 3
> > +#define VISCONTI_CSI2RX_IRQ_MASK_PACKET_ERROR 4
> > +#define VISCONTI_CSI2RX_IRQ_MASK_LINE_ERROR 5
> > +struct hwd_viif_csi2rx_irq_mask {
> > + u32 mask[VISCONTI_CSI2RX_IRQ_MASKS_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_csi2rx_packet - CSI2 packet information
> > + * @word_count: word count included in one packet[byte] [0..16384]
> > + * @packet_num: the number of packet included in one packet [0..8192]
> > + *
> > + * each element means as below.
> > + * * [0]: embedded data of MAIN unit
> > + * * [1]: long packet data of MAIN unit
> > + * * [2]: embedded data of SUB unit
> > + * * [3]: long packet data of SUB unit
> > + *
> > + * Regarding word_count of long packet data,
> > + * word count of odd line needs to be set in case of DT = 0x18, 0x19, 0x1C or
> 0x1D.
> > + */
> > +#define VISCONTI_CSI2RX_PACKET_TYPES_NUM 4
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN 0
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN 1
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB 2
> > +#define VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB 3
> > +struct hwd_viif_csi2rx_packet {
> > + u32 word_count[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> > + u32 packet_num[VISCONTI_CSI2RX_PACKET_TYPES_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_pixelmap - pixelmap information
> > + * @pmap_paddr: start address of pixel data(physical address). 4byte
> alignment.
> > + * @pitch: pitch size of pixel map[byte]
> > + *
> > + * Condition of pitch in case of L2ISP output is as below.
> > + * * max: 32704[byte]
> > + * * min: the larger value of (active width of image * k / r) and 128[byte]
> > + * * alignment: 64[byte]
> > + *
> > + * Condition of pitch in the other cases is as below.
> > + * * max: 65536[byte]
> > + * * min: active width of image * k / r[byte]
> > + * * alignment: 4[byte]
> > + *
> > + * k is the size of 1 pixel and the value is as below.
> > + * * HWD_VIIF_YCBCR422_8_PACKED: 2
> > + * * HWD_VIIF_RGB888_PACKED: 3
> > + * * HWD_VIIF_ARGB8888_PACKED: 4
> > + * * HWD_VIIF_YCBCR422_8_PLANAR: 1
> > + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR: 1
> > + * * HWD_VIIF_ONE_COLOR_8: 1
> > + * * HWD_VIIF_YCBCR422_16_PLANAR: 2
> > + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR: 2
> > + * * HWD_VIIF_ONE_COLOR_16: 2
> > + *
> > + * r is the correction factor for Cb or Cr of YCbCr422 planar and the value is
> as below.
> > + * * YCbCr422 Cb-planar: 2
> > + * * YCbCr422 Cr-planar: 2
> > + * * others: 1
> > + *
> > + */
> > +struct hwd_viif_pixelmap {
> > + uintptr_t pmap_paddr;
> > + u32 pitch;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_img - image information
> > + * @width: active width of image[pixel]
> > + * * [128..5760](output from L2ISP)
> > + * * [128..4096](input to MAIN unit(memory input))
> > + * * [128..4096](output from SUB unit)
> > + * * The value should be even.
> > + *
> > + * @height: active height of image[line]
> > + * * [128..3240](output from L2ISP)
> > + * * [128..2160](input to MAIN unit(memory input))
> > + * * [128..2160](output from SUB unit)
> > + * * The value should be even.
> > + *
> > + * @format: hwd_viif_color_format "color format"
> > + * * Below color formats are supported for input and output of MAIN unit
> > + * * HWD_VIIF_YCBCR422_8_PACKED
> > + * * HWD_VIIF_RGB888_PACKED
> > + * * HWD_VIIF_ARGB8888_PACKED
> > + * * HWD_VIIF_YCBCR422_8_PLANAR
> > + * * HWD_VIIF_RGB888_YCBCR444_8_PLANAR
> > + * * HWD_VIIF_ONE_COLOR_8
> > + * * HWD_VIIF_YCBCR422_16_PLANAR
> > + * * HWD_VIIF_RGB161616_YCBCR444_16_PLANAR
> > + * * HWD_VIIF_ONE_COLOR_16
> > + * * Below color formats are supported for output of SUB unit
> > + * * HWD_VIIF_ONE_COLOR_8
> > + * * HWD_VIIF_ONE_COLOR_16
> > + *
> > + * @pixelmap: pixelmap information
> > + * * [0]: Y/G-planar, packed/Y/RAW
> > + * * [1]: Cb/B-planar
> > + * * [2]: Cr/R-planar
> > + */
> > +struct hwd_viif_img {
> > + u32 width;
> > + u32 height;
> > + u32 format;
> > + struct hwd_viif_pixelmap pixelmap[3];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_input_img - input image information
> > + * @pixel_clock: pixel clock [3375..600000] [kHz]. 0 needs to be set for long
> packet data.
> > + * @htotal_size: horizontal total size
> > + * * [143..65535] [pixel] for image data
> > + * * [239..109225] [ns] for long packet data
> > + * @hactive_size: horizontal active size [pixel]
> > + * * [128..4096] without L1ISP
> > + * * [640..3840] with L1ISP
> > + * * The value should be even. In addition, the value should be a multiple of 8
> with L1ISP
> > + * * 0 needs to be set for the configuration of long packet data or SUB unit
> output.
> > + * @vtotal_size: vertical total size [line]
> > + * * [144..16383] for image data
> > + * * 0 needs to be set for the configuration of long packet data.
> > + * @vbp_size: vertical back porch size
> > + * * [5..4095] [line] for image data
> > + * * [5..4095] [the number of packet] for long packet data
> > + * @vactive_size: vertical active size [line]
> > + * * [128..2160] without L1ISP
> > + * * [480..2160] with L1ISP
> > + * * The value should be even.
> > + * * 0 needs to be set for the configuration of long packet data.
> > + * @interpolation_mode: input image interpolation mode for
> hwd_viif_l1_input_interpolation_mode
> > + * * HWD_VIIF_L1_INPUT_INTERPOLATION_LINE needs to be set in the
> below cases.
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + * @input_num: the number of input images [1..3]
> > + * * 1 needs to be set in the below cases.
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + * @hobc_width: the number of horizontal optical black pixels [0,16,32,64 or
> 128]
> > + * * 0 needs to be set in the below cases.
> > + * * in case of hobc_margin = 0
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + * @hobc_margin: the number of horizontal optical black margin[0..30] (even
> number)
> > + * * 0 needs to be set in the below cases.
> > + * * in case of hobc_width = 0
> > + * * image data(without L1ISP) or long packet data
> > + * * image data or long packet data of SUB unit
> > + *
> > + * Below conditions need to be satisfied.
> > + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_LINE:
> > + * (htotal_size > (hactive_size + hobc_width + hobc_margin)) &&
> > + * (vtotal_size > (vbp_size + vactive_size * input_num))
> > + * * interpolation_mode is HWD_VIIF_L1_INPUT_INTERPOLATION_PIXEL:
> > + * (htotal_size > ((hactive_size + hobc_width + hobc_margin) *
> input_num)) &&
> > + * (vtotal_size > (vbp_size + vactive_size))
> > + * * L1ISP is used:
> > + * vbp_size >= (54720[cycle] / 500000[kHz]) * (pixel_clock / htotal_size)
> + 38 + ISST time
> > + * * L1ISP is not used:
> > + * vbp_size >= (39360[cycle] / 500000[kHz]) * (pixel_clock / htotal_size)
> + 16 + ISST time
> > + *
> > + * Note: L1ISP is used when RAW data is input to MAIN unit
> > + */
> > +struct hwd_viif_input_img {
> > + u32 pixel_clock;
> > + u32 htotal_size;
> > + u32 hactive_size;
> > + u32 vtotal_size;
> > + u32 vbp_size;
> > + u32 vactive_size;
> > + u32 interpolation_mode;
> > + u32 input_num;
> > + u32 hobc_width;
> > + u32 hobc_margin;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_csc_param - color conversion information
> > + * @r_cr_in_offset: input offset of R/Cr[pix value] [0x0..0x1FFFF]
> > + * @g_y_in_offset: input offset of G/Y[pix value] [0x0..0x1FFFF]
> > + * @b_cb_in_offset: input offset of B/Cb[pix value] [0x0..0x1FFFF]
> > + * @coef: coefficient of matrix [0x0..0xFFFF]
> > + * * [0] : c00(YG_YG), [1] : c01(UB_YG), [2] : c02(VR_YG),
> > + * * [3] : c10(YG_UB), [4] : c11(UB_UB), [5] : c12(VR_UB),
> > + * * [6] : c20(YG_VR), [7] : c21(UB_VR), [8] : c22(VR_VR)
> > + * @r_cr_out_offset: output offset of R/Cr[pix value] [0x0..0x1FFFF]
> > + * @g_y_out_offset: output offset of G/Y[pix value] [0x0..0x1FFFF]
> > + * @b_cb_out_offset: output offset of B/Cb[pix value] [0x0..0x1FFFF]
> > + */
> > +struct hwd_viif_csc_param {
> > + u32 r_cr_in_offset;
> > + u32 g_y_in_offset;
> > + u32 b_cb_in_offset;
> > + u32 coef[9];
> > + u32 r_cr_out_offset;
> > + u32 g_y_out_offset;
> > + u32 b_cb_out_offset;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_img_area - image area definition
> > + * @x: x position [0..8062] [pixel]
> > + * @y: y position [0..3966] [line]
> > + * @w: image width [128..8190] [pixel]
> > + * @h: image height [128..4094] [line]
> > + */
> > +struct hwd_viif_img_area {
> > + u32 x;
> > + u32 y;
> > + u32 w;
> > + u32 h;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_out_process - configuration of output process of MAIN unit
> and L2ISP
> > + * @half_scale: hwd_viif_enable_flag "enable or disable half scale"
> > + * @select_color: hwd_viif_output_color_mode "select output color"
> > + * @alpha: alpha value used in case of ARGB8888 output [0..255]
> > + */
> > +struct hwd_viif_out_process {
> > + u32 half_scale;
> > + u32 select_color;
> > + u8 alpha;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l1_lsc - HWD L1ISP lens shading correction parameters
> > + * @lssc_parabola_param: parabola shading correction parameter
> > + * * NULL: disable parabola shading correction
> > + * * not NULL: enable parabola shading correction
> > + * @lssc_grid_param: grid shading correction parameter
> > + * * NULL: disable grid shading correction
> > + * * not NULL: enable grid shading correction
> > + * @lssc_pwhb_r_gain_max: maximum R gain of preset white balance
> correction
> > + * @lssc_pwhb_r_gain_min: minimum R gain of preset white balance
> correction
> > + * @lssc_pwhb_gr_gain_max: maximum Gr gain of preset white balance
> correction
> > + * @lssc_pwhb_gr_gain_min: minimum Gr gain of preset white balance
> correction
> > + * @lssc_pwhb_gb_gain_max: maximum Gb gain of preset white balance
> correction
> > + * @lssc_pwhb_gb_gain_min: minimum Gb gain of preset white balance
> correction
> > + * @lssc_pwhb_b_gain_max: maximum B gain of preset white balance
> correction
> > + * @lssc_pwhb_b_gain_min: minimum B gain of preset white balance
> correction
> > + *
> > + * Range and accuracy of lssc_pwhb_xxx_gain_xxx are as below.
> > + * - range: [0x0..0x7FF]
> > + * - accuracy : 1/256
> > + */
> > +struct hwd_viif_l1_lsc {
> > + struct viif_l1_lsc_parabola_param *lssc_parabola_param;
> > + struct viif_l1_lsc_grid_param *lssc_grid_param;
> > + u32 lssc_pwhb_r_gain_max;
> > + u32 lssc_pwhb_r_gain_min;
> > + u32 lssc_pwhb_gr_gain_max;
> > + u32 lssc_pwhb_gr_gain_min;
> > + u32 lssc_pwhb_gb_gain_max;
> > + u32 lssc_pwhb_gb_gain_min;
> > + u32 lssc_pwhb_b_gain_max;
> > + u32 lssc_pwhb_b_gain_min;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l1_img_quality_adjustment - HWD L1ISP image quality
> adjustment parameters
> > + * @coef_cb: Cb coefficient [0x0..0xffff] accuracy: 1/65536
> > + * @coef_cr: Cr coefficient [0x0..0xffff] accuracy: 1/65536
> > + * @brightness: brightness value [-32768..32767] (0 means off.)
> > + * @linear_contrast: linear contrast value [0x0..0xff] accuracy: 1/128 (128
> means off.)
> > + * @*nonlinear_contrast: pointer to nonlinear contrast parameter
> > + * @*lum_noise_reduction: pointer to luminance noise reduction parameter
> > + * @*edge_enhancement: pointer to edge enhancement parameter
> > + * @*uv_suppression: pointer to UV suppression parameter
> > + * @*coring_suppression: pointer to coring suppression parameter
> > + * @*edge_suppression: pointer to edge enhancement parameter
> > + * @*color_level: pointer to color level adjustment parameter
> > + * @color_noise_reduction_enable: enable/disable color noise reduction @ref
> hwd_viif_enable_flag
> > + */
> > +struct hwd_viif_l1_img_quality_adjustment {
> > + u16 coef_cb;
> > + u16 coef_cr;
> > + s16 brightness;
> > + u8 linear_contrast;
> > + struct viif_l1_nonlinear_contrast *nonlinear_contrast;
> > + struct viif_l1_lum_noise_reduction *lum_noise_reduction;
> > + struct viif_l1_edge_enhancement *edge_enhancement;
> > + struct viif_l1_uv_suppression *uv_suppression;
> > + struct viif_l1_coring_suppression *coring_suppression;
> > + struct viif_l1_edge_suppression *edge_suppression;
> > + struct viif_l1_color_level *color_level;
> > + u32 color_noise_reduction_enable;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l1_info - HWD L1ISP processing information
> > + * @context_id: context id
> > + * @ag_cont_hobc_high: analog gain for high sensitivity image of OBCC
> > + * @ag_cont_hobc_middle_led: analog gain for middle sensitivity or led image
> of OBCC
> > + * @ag_cont_hobc_low: analog gain for low sensitivity image of OBCC
> > + * @ag_cont_abpc_high: analog gain for high sensitivity image of ABPC
> > + * @ag_cont_abpc_middle_led: analog gain for middle sensitivity or led image
> of ABPC
> > + * @ag_cont_abpc_low: analog gain for low sensitivity image of ABPC
> > + * @ag_cont_rcnr_high: analog gain for high sensitivity image of RCNR
> > + * @ag_cont_rcnr_middle_led: analog gain for middle sensitivity or led image
> of RCNR
> > + * @ag_cont_rcnr_low: analog gain for low sensitivity image of RCNR
> > + * @ag_cont_lssc: analog gain for LSSC
> > + * @ag_cont_mpro: analog gain for color matrix correction
> > + * @ag_cont_vpro: analog gain for image quality adjustment
> > + * @dpc_defect_num_h:
> > + * the number of dynamically corrected defective pixel(high sensitivity
> image)
> > + * @dpc_defect_num_m:
> > + * the number of dynamically corrected defective pixel(middle
> sensitivity or led image)
> > + * @dpc_defect_num_l:
> > + * the number of dynamically corrected defective pixel(low sensitivity
> image)
> > + * @hdrc_tnp_fb_smth_max: the maximum value of luminance information
> after smoothing filter at HDRC
> > + * @avg_lum_weight: weighted average luminance value at average
> luminance generation
> > + * @avg_lum_block[8][8]:
> > + * average luminance of each block [y][x]:
> > + * y means vertical position and x means horizontal position.
> > + * @avg_lum_four_line_lum[4]:
> > + * 4-lines average luminance. avg_lum_four_line_lum[n] corresponds to
> aexp_ave4linesy[n]
> > + * @avg_satur_pixnum: the number of saturated pixel at average luminance
> generation
> > + * @avg_black_pixnum: the number of black pixel at average luminance
> generation
> > + * @awb_ave_u: average U at AWHB [pixel]
> > + * @awb_ave_v: average V at AWHB [pixel]
> > + * @awb_accumulated_pixel: the number of accumulated pixel at AWHB
> > + * @awb_gain_r: R gain applied in the next frame at AWHB
> > + * @awb_gain_g: G gain applied in the next frame at AWHB
> > + * @awb_gain_b: B gain applied in the next frame at AWHB
> > + * @awb_status_u: status of U convergence at AWHB (true: converged, false:
> not converged)
> > + * @awb_status_v: status of V convergence at AWHB (true: converged, false:
> not converged)
> > + */
> > +struct hwd_viif_l1_info {
> > + u32 context_id;
> > + u8 ag_cont_hobc_high;
> > + u8 ag_cont_hobc_middle_led;
> > + u8 ag_cont_hobc_low;
> > + u8 ag_cont_abpc_high;
> > + u8 ag_cont_abpc_middle_led;
> > + u8 ag_cont_abpc_low;
> > + u8 ag_cont_rcnr_high;
> > + u8 ag_cont_rcnr_middle_led;
> > + u8 ag_cont_rcnr_low;
> > + u8 ag_cont_lssc;
> > + u8 ag_cont_mpro;
> > + u8 ag_cont_vpro;
> > + u32 dpc_defect_num_h;
> > + u32 dpc_defect_num_m;
> > + u32 dpc_defect_num_l;
> > + u32 hdrc_tnp_fb_smth_max;
> > + u32 avg_lum_weight;
> > + u32 avg_lum_block[8][8];
> > + u32 avg_lum_four_line_lum[4];
> > + u16 avg_satur_pixnum;
> > + u16 avg_black_pixnum;
> > + u32 awb_ave_u;
> > + u32 awb_ave_v;
> > + u32 awb_accumulated_pixel;
> > + u32 awb_gain_r;
> > + u32 awb_gain_g;
> > + u32 awb_gain_b;
> > + bool awb_status_u;
> > + bool awb_status_v;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_l2_gamma_table - HWD L2ISP Gamma table physical
> address
> > + * @table[6]: table address(physical address) 4byte alignment
> > + *
> > + * relation between element and table is as below.
> > + * * [0]: G/Y(1st table)
> > + * * [1]: G/Y(2nd table)
> > + * * [2]: B/U(1st table)
> > + * * [3]: B/U(2nd table)
> > + * * [4]: R/V(1st table)
> > + * * [5]: R/V(2nd table)
> > + *
> > + * when 0 is set to table address, table transfer is disabled.
> > + */
> > +struct hwd_viif_l2_gamma_table {
> > + uintptr_t table[6];
>
> Use dma_addr_t for fields that store DMA addresses. Same comment for all
> the other usages of uintptr_t I think. While at it, don't name the
> variables "paddr", those are not physical addresses but DMA addresses
> (they can differ when an IOMMU is present). Use "dma_addr" or just
> "addr" in variable names.
I'll use dma_addr_t for DMA addresses.
Also, I do not use paddr for variable's name.
> > +};
>
> [snip]
>
> > diff --git a/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > new file mode 100644
> > index 00000000000..f49869c5bdd
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_csi2rx.c
> > @@ -0,0 +1,610 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/timekeeping.h>
> > +#include "hwd_viif.h"
> > +#include "hwd_viif_internal.h"
> > +
> > +#define CSI2_DT_YUV4208 0x18
> > +#define CSI2_DT_YUV42010 0x19
> > +#define CSI2_DT_YUV4208L 0x1A
> > +#define CSI2_DT_YUV4208C 0x1C
> > +#define CSI2_DT_YUV42010C 0x1D
> > +#define CSI2_DT_YUV4228B VISCONTI_CSI2_DT_YUV4228B
> > +#define CSI2_DT_YUV42210B VISCONTI_CSI2_DT_YUV42210B
> > +#define CSI2_DT_RGB444 0x20
> > +#define CSI2_DT_RGB555 0x21
> > +#define CSI2_DT_RGB565 VISCONTI_CSI2_DT_RGB565
> > +#define CSI2_DT_RGB666 0x23
> > +#define CSI2_DT_RGB888 VISCONTI_CSI2_DT_RGB888
> > +#define CSI2_DT_RAW8 VISCONTI_CSI2_DT_RAW8
> > +#define CSI2_DT_RAW10 VISCONTI_CSI2_DT_RAW10
> > +#define CSI2_DT_RAW12 VISCONTI_CSI2_DT_RAW12
> > +#define CSI2_DT_RAW14 VISCONTI_CSI2_DT_RAW14
>
> You can drop this and replace it with the macros defined in
> include/media/mipi-csi2.h.
I'll use definitions in media/mipi-csi2.h .
> > +
> > +#define TESTCTRL0_PHY_TESTCLK_1 0x2
> > +#define TESTCTRL0_PHY_TESTCLK_0 0x0
> > +#define TESTCTRL1_PHY_TESTEN 0x10000
> > +#define TESTCTRL1_PHY_TESTDOUT_SHIFT 8U
> > +
> > +/**
> > + * write_dphy_param() - Write CSI2RX DPHY params
> > + *
> > + * @test_mode: test code address
> > + * @test_in: test code data
> > + * Return: None
> > + */
> > +static void write_dphy_param(u32 test_mode, u8 test_in, struct hwd_viif_res
> *res)
> > +{
> > + /* select MSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* set MSB address of test_mode */
> > + writel(FIELD_GET(0xF00, test_mode),
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* select and set LSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> > + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* set the test code data */
> > + writel((u32)test_in, &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +}
> > +
> > +/**
> > + * read_dphy_param() - Read CSI2RX DPHY params
> > + *
> > + * @test_mode: test code address
> > + * Return: test code data
> > + */
> > +static u8 read_dphy_param(u32 test_mode, struct hwd_viif_res *res)
> > +{
> > + u32 read_data;
> > +
> > + /* select MSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* set MSB address of test_mode */
> > + writel(FIELD_GET(0xF00, test_mode),
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* select and set LSB address register */
> > + writel(TESTCTRL1_PHY_TESTEN | FIELD_GET(0xFF, test_mode),
> > + &res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > +
> > + /* rise and clear the testclk */
> > + writel(TESTCTRL0_PHY_TESTCLK_1,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(TESTCTRL0_PHY_TESTCLK_0,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* read the test code data */
> > + read_data = readl(&res->csi2host_reg->CSI2RX_PHY_TESTCTRL1);
> > + return (u8)(read_data >> TESTCTRL1_PHY_TESTDOUT_SHIFT);
> > +}
> > +
> > +/**
> > + * enum dphy_testcode - DPHY registers via the local communication path
> > + */
> > +enum dphy_testcode {
> > + DIG_RDWR_RX_SYS_0 = 0x001,
> > + DIG_RDWR_RX_SYS_1 = 0x002,
> > + DIG_RDWR_RX_SYS_3 = 0x004,
> > + DIG_RDWR_RX_SYS_7 = 0x008,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_2 = 0x0E2,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_3 = 0x0E3,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_4 = 0x0E4,
> > + DIG_RDWR_RX_RX_STARTUP_OVR_5 = 0x0E5,
> > + DIG_RDWR_RX_CB_2 = 0x1AC,
> > + DIG_RD_RX_TERM_CAL_0 = 0x220,
> > + DIG_RD_RX_TERM_CAL_1 = 0x221,
> > + DIG_RD_RX_TERM_CAL_2 = 0x222,
> > + DIG_RDWR_RX_CLKLANE_LANE_6 = 0x307,
> > + DIG_RD_RX_CLKLANE_OFFSET_CAL_0 = 0x39D,
> > + DIG_RD_RX_LANE0_OFFSET_CAL_0 = 0x59F,
> > + DIG_RD_RX_LANE0_DDL_0 = 0x5E0,
> > + DIG_RD_RX_LANE1_OFFSET_CAL_0 = 0x79F,
> > + DIG_RD_RX_LANE1_DDL_0 = 0x7E0,
> > + DIG_RD_RX_LANE2_OFFSET_CAL_0 = 0x99F,
> > + DIG_RD_RX_LANE2_DDL_0 = 0x9E0,
> > + DIG_RD_RX_LANE3_OFFSET_CAL_0 = 0xB9F,
> > + DIG_RD_RX_LANE3_DDL_0 = 0xBE0,
> > +};
> > +
> > +#define SYS_0_HSFREQRANGE_OVR BIT(5)
> > +#define SYS_7_RESERVED FIELD_PREP(0x1F, 0x0C)
> > +#define SYS_7_DESKEW_POL BIT(5)
> > +#define STARTUP_OVR_4_CNTVAL FIELD_PREP(0x70, 0x01)
> > +#define STARTUP_OVR_4_DDL_EN BIT(0)
> > +#define STARTUP_OVR_5_BYPASS BIT(0)
> > +#define CB_2_LPRX_BIAS BIT(6)
> > +#define CB_2_RESERVED FIELD_PREP(0x3F, 0x0B)
> > +#define CLKLANE_RXHS_PULL_LONG BIT(7)
> > +
> > +static const struct hwd_viif_dphy_hs_info dphy_hs_info[] = {
> > + { 80, 0x0, 0x1cc }, { 85, 0x10, 0x1cc }, { 95, 0x20, 0x1cc }, { 105,
> 0x30, 0x1cc },
> > + { 115, 0x1, 0x1cc }, { 125, 0x11, 0x1cc }, { 135, 0x21, 0x1cc }, { 145,
> 0x31, 0x1cc },
> > + { 155, 0x2, 0x1cc }, { 165, 0x12, 0x1cc }, { 175, 0x22, 0x1cc }, { 185,
> 0x32, 0x1cc },
> > + { 198, 0x3, 0x1cc }, { 213, 0x13, 0x1cc }, { 228, 0x23, 0x1cc }, { 243,
> 0x33, 0x1cc },
> > + { 263, 0x4, 0x1cc }, { 288, 0x14, 0x1cc }, { 313, 0x25, 0x1cc }, { 338,
> 0x35, 0x1cc },
> > + { 375, 0x5, 0x1cc }, { 425, 0x16, 0x1cc }, { 475, 0x26, 0x1cc }, { 525,
> 0x37, 0x1cc },
> > + { 575, 0x7, 0x1cc }, { 625, 0x18, 0x1cc }, { 675, 0x28, 0x1cc }, { 725,
> 0x39, 0x1cc },
> > + { 775, 0x9, 0x1cc }, { 825, 0x19, 0x1cc }, { 875, 0x29, 0x1cc }, { 925,
> 0x3a, 0x1cc },
> > + { 975, 0xa, 0x1cc }, { 1025, 0x1a, 0x1cc }, { 1075, 0x2a, 0x1cc }, { 1125,
> 0x3b, 0x1cc },
> > + { 1175, 0xb, 0x1cc }, { 1225, 0x1b, 0x1cc }, { 1275, 0x2b, 0x1cc }, { 1325,
> 0x3c, 0x1cc },
> > + { 1375, 0xc, 0x1cc }, { 1425, 0x1c, 0x1cc }, { 1475, 0x2c, 0x1cc }
> > +};
> > +
> > +/**
> > + * get_dphy_hs_transfer_info() - Get DPHY HS info from table
> > + *
> > + * @dphy_rate: DPHY clock in MHz
> > + * @hsfreqrange: HS Frequency Range
> > + * @osc_freq_target: OSC Frequency Target
> > + * Return: None
> > + */
> > +static void get_dphy_hs_transfer_info(u32 dphy_rate, u32 *hsfreqrange, u32
> *osc_freq_target,
> > + struct hwd_viif_res *res)
> > +{
> > + int table_size = ARRAY_SIZE(dphy_hs_info);
> > + int i;
> > +
> > + for (i = 1; i < table_size; i++) {
> > + if (dphy_rate < dphy_hs_info[i].rate) {
> > + *hsfreqrange = dphy_hs_info[i - 1].hsfreqrange;
> > + *osc_freq_target = dphy_hs_info[i - 1].osc_freq_target;
> > + return;
> > + }
> > + }
> > +
> > + /* not found; return the largest entry */
> > + *hsfreqrange = dphy_hs_info[table_size - 1].hsfreqrange;
> > + *osc_freq_target = dphy_hs_info[table_size - 1].osc_freq_target;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_set_dphy_rate() - Set D-PHY rate
> > + *
> > + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> > + * Return: None
> > + */
> > +static void hwd_viif_csi2rx_set_dphy_rate(u32 dphy_rate, struct hwd_viif_res
> *res)
> > +{
> > + u32 hsfreqrange, osc_freq_target;
> > +
> > + get_dphy_hs_transfer_info(dphy_rate, &hsfreqrange, &osc_freq_target,
> res);
> > +
> > + write_dphy_param(DIG_RDWR_RX_SYS_1, (u8)hsfreqrange, res);
> > + write_dphy_param(DIG_RDWR_RX_SYS_0,
> SYS_0_HSFREQRANGE_OVR, res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_5,
> STARTUP_OVR_5_BYPASS, res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4,
> STARTUP_OVR_4_CNTVAL, res);
> > + write_dphy_param(DIG_RDWR_RX_CB_2, CB_2_LPRX_BIAS |
> CB_2_RESERVED, res);
> > + write_dphy_param(DIG_RDWR_RX_SYS_7, SYS_7_DESKEW_POL |
> SYS_7_RESERVED, res);
> > + write_dphy_param(DIG_RDWR_RX_CLKLANE_LANE_6,
> CLKLANE_RXHS_PULL_LONG, res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_2,
> FIELD_GET(0xff, osc_freq_target), res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_3,
> FIELD_GET(0xf00, osc_freq_target), res);
> > + write_dphy_param(DIG_RDWR_RX_RX_STARTUP_OVR_4,
> STARTUP_OVR_4_CNTVAL | STARTUP_OVR_4_DDL_EN,
> > + res);
> > +
> > + writel(HWD_VIIF_DPHY_CFG_CLK_25M,
> &res->capture_reg->sys.DPHY_FREQRANGE);
> > +}
> > +
> > +/**
> > + * check_dphy_calibration_status() - Check D-PHY calibration status
> > + *
> > + * @test_mode: test code related to calibration information
> > + * @shift_val_err: shift value related to error information
> > + * @shift_val_done: shift value related to done information
> > + * Return: HWD_VIIF_CSI2_CAL_NOT_DONE calibration is not done(out of
> target or not completed)
> > + * Return: HWD_VIIF_CSI2_CAL_FAIL calibration was failed
> > + * Return: HWD_VIIF_CSI2_CAL_SUCCESS calibration was succeeded
> > + */
> > +static u32 check_dphy_calibration_status(u32 test_mode, u32 shift_val_err,
> u32 shift_val_done,
> > + struct hwd_viif_res *res)
> > +{
> > + u32 read_data = (u32)read_dphy_param(test_mode, res);
> > +
> > + if (!(read_data & BIT(shift_val_done)))
> > + return HWD_VIIF_CSI2_CAL_NOT_DONE;
> > +
> > + /* error check is not required for termination calibration with
> REXT(0x221) */
> > + if (test_mode == DIG_RD_RX_TERM_CAL_1)
> > + return HWD_VIIF_CSI2_CAL_SUCCESS;
> > +
> > + /* done with error */
> > + if (read_data & BIT(shift_val_err))
> > + return HWD_VIIF_CSI2_CAL_FAIL;
> > +
> > + return HWD_VIIF_CSI2_CAL_SUCCESS;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_initialize() - Initialize CSI-2 RX driver
> > + *
> > + * @num_lane: [1..4](VIIF CH0-CH1)
> > + * @lane_assign: lane connection. For more refer @ref
> hwd_viif_dphy_lane_assignment
> > + * @dphy_rate: D-PHY rate of 1 Lane[Mbps] [80..1500]
> > + * @rext_calibration: enable or disable rext calibration.
> > + * For more refer @ref hwd_viif_csi2rx_cal_status
> > + * @err_target: Pointer to configuration for Line error detection.
> > + * @mask: MASK of CSI-2 RX error interruption
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * - [1] "num_lane", "lane_assign", "dphy_rate", "rext_calibration" or
> "input_mode" is out of range
> > + * - [2] "err_target" is NULL
> > + * - [3] member of "err_target" is invalid
> > + */
> > +s32 hwd_viif_csi2rx_initialize(struct hwd_viif_res *res, u32 num_lane, u32
> lane_assign,
> > + u32 dphy_rate, u32 rext_calibration,
> > + const struct hwd_viif_csi2rx_line_err_target
> *err_target,
> > + const struct hwd_viif_csi2rx_irq_mask *mask)
> > +{
> > + u32 i, val;
> > +
> > + if (num_lane == 0U || num_lane > 4U || lane_assign >
> HWD_VIIF_CSI2_DPHY_L0L2L1L3)
> > + return -EINVAL;
> > +
> > + if (dphy_rate < HWD_VIIF_DPHY_MIN_DATA_RATE || dphy_rate >
> HWD_VIIF_DPHY_MAX_DATA_RATE ||
> > + (rext_calibration != HWD_VIIF_ENABLE && rext_calibration !=
> HWD_VIIF_DISABLE) ||
> > + !err_target) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < 8U; i++) {
> > + if (err_target->vc[i] > HWD_VIIF_CSI2_MAX_VC ||
> > + err_target->dt[i] > HWD_VIIF_CSI2_MAX_DT ||
> > + (err_target->dt[i] < HWD_VIIF_CSI2_MIN_DT &&
> err_target->dt[i] != 0U)) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + /* 1st phase of initialization */
> > + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_RESETN);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> > + writel(HWD_VIIF_ENABLE,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + ndelay(15U);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > +
> > + /* Configure D-PHY frequency range */
> > + hwd_viif_csi2rx_set_dphy_rate(dphy_rate, res);
> > +
> > + /* 2nd phase of initialization */
> > + writel((num_lane - 1U), &res->csi2host_reg->CSI2RX_NLANES);
> > + ndelay(5U);
> > +
> > + /* configuration not to use rext */
> > + if (rext_calibration == HWD_VIIF_DISABLE) {
> > + write_dphy_param(0x004, 0x10, res);
> > + ndelay(5U);
> > + }
> > +
> > + /* Release D-PHY from Reset */
> > + writel(HWD_VIIF_ENABLE,
> &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> > + ndelay(5U);
> > + writel(HWD_VIIF_ENABLE, &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> > +
> > + /* configuration of line error target */
> > + val = (err_target->vc[3] << 30U) | (err_target->dt[3] << 24U) |
> (err_target->vc[2] << 22U) |
> > + (err_target->dt[2] << 16U) | (err_target->vc[1] << 14U) |
> (err_target->dt[1] << 8U) |
> > + (err_target->vc[0] << 6U) | (err_target->dt[0]);
> > + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_1);
> > + val = (err_target->vc[7] << 30U) | (err_target->dt[7] << 24U) |
> (err_target->vc[6] << 22U) |
> > + (err_target->dt[6] << 16U) | (err_target->vc[5] << 14U) |
> (err_target->dt[5] << 8U) |
> > + (err_target->vc[4] << 6U) | (err_target->dt[4]);
> > + writel(val, &res->csi2host_reg->CSI2RX_DATA_IDS_2);
> > +
> > + /* configuration of mask */
> > + writel(mask->mask[0],
> &res->csi2host_reg->CSI2RX_INT_MSK_PHY_FATAL);
> > + writel(mask->mask[1],
> &res->csi2host_reg->CSI2RX_INT_MSK_PKT_FATAL);
> > + writel(mask->mask[2],
> &res->csi2host_reg->CSI2RX_INT_MSK_FRAME_FATAL);
> > + writel(mask->mask[3], &res->csi2host_reg->CSI2RX_INT_MSK_PHY);
> > + writel(mask->mask[4], &res->csi2host_reg->CSI2RX_INT_MSK_PKT);
> > + writel(mask->mask[5],
> &res->csi2host_reg->CSI2RX_INT_MSK_LINE);
> > +
> > + /* configuration of lane assignment */
> > + writel(lane_assign, &res->capture_reg->sys.DPHY_LANE);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_uninitialize() - Uninitialize CSI-2 RX driver
> > + *
> > + * Return: 0 Operation completes successfully
> > + */
> > +s32 hwd_viif_csi2rx_uninitialize(struct hwd_viif_res *res)
> > +{
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_SHUTDOWNZ);
> > + writel(HWD_VIIF_DISABLE,
> &res->csi2host_reg->CSI2RX_PHY_RSTZ);
> > + writel(HWD_VIIF_ENABLE,
> &res->csi2host_reg->CSI2RX_PHY_TESTCTRL0);
> > + writel(HWD_VIIF_DISABLE, &res->csi2host_reg->CSI2RX_RESETN);
> > +
> > + return 0;
> > +}
> > +
> > +#define PORT_SEL_MAIN_LONG 0
> > +#define PORT_SEL_MAIN_EMBED 1
> > +#define PORT_SEL_SUB_LONG 4
> > +#define PORT_SEL_SUB_EMBED 5
> > +
> > +static void config_vdm_wport(struct hwd_viif_res *res, int port_sel, u32
> height, u32 pitch)
> > +{
> > + struct hwd_viif_vdm_write_port_reg *wport;
> > + u32 start_addr, end_addr;
> > +
> > + wport = &res->capture_reg->vdm.w_port[port_sel];
> > +
> > + writel(pitch, &wport->VDM_W_PITCH);
> > + writel(height, &wport->VDM_W_HEIGHT);
> > + start_addr = readl(&wport->VDM_W_STADR);
> > + end_addr = start_addr + pitch - 1U;
> > + writel(end_addr, &wport->VDM_W_ENDADR);
> > +}
>
> The VDM doesn't seem to belong to the CSI-2 RX, I would move this to a
> different file.
I'll move them to suitable functions.
It's surely not a good idea to handle Video DMAC here.
> > +
> > +/**
> > + * hwd_viif_csi2rx_start() - Start CSI-2 input
> > + *
> > + * @vc_main: control CSI-2 input of MAIN unit.
> > + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> > + * @vc_sub: control CSI-2 input of SUB unit.
> > + * enable with configured VC: 0, 1, 2 or 3, keep disabling:
> > + * @packet: Pointer to packet information of embedded data and long packet
> data
> > + * Return: 0 Operation completes successfully
> > + * Return: -EINVAL Parameter error
> > + * HWD_VIIF_CSI2_NOT_CAPTURE
> > + * HWD_VIIF_CSI2_NOT_CAPTURE
> > + * - [1] "vc_main" or "vc_sub" is out of range
> > + * - [2] member of "packet" is invalid
> > + */
> > +s32 hwd_viif_csi2rx_start(struct hwd_viif_res *res, s32 vc_main, s32 vc_sub,
> > + const struct hwd_viif_csi2rx_packet *packet)
> > +{
> > + u32 val, i, pitch, height, dt;
> > + u32 enable_vc0 = HWD_VIIF_DISABLE;
> > + u32 enable_vc1 = HWD_VIIF_DISABLE;
> > +
> > + if (vc_main > 3 || vc_main < HWD_VIIF_CSI2_NOT_CAPTURE || vc_sub
> > 3 ||
> > + vc_sub < HWD_VIIF_CSI2_NOT_CAPTURE) {
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < VISCONTI_CSI2RX_PACKET_TYPES_NUM; i++) {
> > + if (packet->word_count[i] >
> HWD_VIIF_CSI2_MAX_WORD_COUNT ||
> > + packet->packet_num[i] >
> HWD_VIIF_CSI2_MAX_PACKET_NUM) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + writel(HWD_VIIF_INPUT_CSI2, &res->capture_reg->sys.IPORTM);
> > +
> > + if (vc_main != HWD_VIIF_CSI2_NOT_CAPTURE) {
> > + writel((u32)vc_main, &res->capture_reg->sys.VCID0SELECT);
> > + enable_vc0 = HWD_VIIF_ENABLE;
> > + }
> > + if (vc_sub != HWD_VIIF_CSI2_NOT_CAPTURE) {
> > + writel((u32)vc_sub, &res->capture_reg->sys.VCID1SELECT);
> > + enable_vc1 = HWD_VIIF_ENABLE;
> > + }
> > +
> > + /* configure Embedded Data transfer of MAIN unit */
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN];
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_MAIN],
> 4);
> > + config_vdm_wport(res, PORT_SEL_MAIN_EMBED, height, pitch);
> > +
> > + /* configure Long Packet transfer of MAIN unit */
> > + dt = readl(&res->capture_reg->sys.IPORTM_OTHER);
> > + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV4208 || dt ==
> CSI2_DT_YUV4208C ||
> > + dt == CSI2_DT_YUV42010C) {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN],
> 4) +
> > +
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LON
> G_MAIN] * 2U, 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN] >>
> 1U;
> > + } else {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN],
> 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_MAIN];
> > + }
> > + config_vdm_wport(res, PORT_SEL_MAIN_LONG, height, pitch);
> > +
> > + /* configure Embedded Data transfer of SUB unit */
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB];
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_EMB_SUB],
> 4);
> > + config_vdm_wport(res, PORT_SEL_SUB_EMBED, height, pitch);
> > +
> > + /* configure Long Packet transfer of SUB unit */
> > + dt = readl(&res->capture_reg->sys.IPORTS_OTHER);
> > + if (dt == CSI2_DT_YUV4208 || dt == CSI2_DT_YUV42010 || dt ==
> CSI2_DT_YUV4208C ||
> > + dt == CSI2_DT_YUV42010C) {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB],
> 4) +
> > +
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LON
> G_SUB] * 2U, 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB] >> 1U;
> > + } else {
> > + pitch =
> ALIGN(packet->word_count[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB],
> 4);
> > + height =
> packet->packet_num[VISCONTI_CSI2RX_PACKET_TYPE_LONG_SUB];
> > + }
> > + config_vdm_wport(res, PORT_SEL_SUB_LONG, height, pitch);
> > +
> > + /* Control VC port enable */
> > + val = enable_vc0 | (enable_vc1 << 4U);
> > + writel(val, &res->capture_reg->sys.VCPORTEN);
> > +
> > + if (enable_vc0 == HWD_VIIF_ENABLE) {
> > + /* Update flag information for run status of MAIN unit */
> > + res->run_flag_main = true;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_csi2rx_stop() - Stop CSI-2 input
> > + *
> > + * Return: 0 Operation completes successfully
> > + * Return: -ETIMEDOUT Driver timeout error
> > + */
> > +s32 hwd_viif_csi2rx_stop(struct hwd_viif_res *res)
> > +{
> > + u32 status_r, status_w, status_t, l2_status;
> > + u64 timeout_ns, cur_ns;
> > + bool run_flag = true;
> > + s32 ret = 0;
> > +
> > + /* Disable auto transmission of register buffer */
> > + writel(0, &res->capture_reg->l1isp.L1_CRGBF_TRN_A_CONF);
> > + writel(0, &res->capture_reg->l2isp.L2_CRGBF_TRN_A_CONF);
>
> Same here, this doesn't belong to the CSI2RX. Same for VDMAC registers
> below, and possibly some of the SYS registers (not sure about those).
I'll move VDMAC register accesses.
Let me check in detail for SYS registers, because some operations for CSI2 and DPHY refers to SYS registers.
> Overall, the CSI2RX should be isolated in a subdev separate from the ISP
> subdev, with a struct viif_csi2rx to model it. It should only control
> the CSI2RX. I'm even tempted to move it to a separate driver, but that
> maybe difficult due to usage of the SYS registers by the CSI2RX :-S
I found some drivers implementing CSI2 receiver as a separate phy.
It's difficult to achieve that pattern now, as CSI2RX controls and other operations are not well separated.
I'll try clean up CSI2RX related codes and possibly make a CSI2RX dedicated subdev.
> > +
> > + /* Wait for completion of register buffer transmission */
> > + udelay(HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME);
> > +
> > + /* Stop all VCs, long packet input and emb data input of MAIN unit */
> > + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.VCPORTEN);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTM_OTHEREN);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTM_EMBEN);
> > +
> > + /* Stop image data input, long packet input and emb data input of SUB
> unit */
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTS_OTHEREN);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->sys.IPORTS_EMBEN);
> > + writel(HWD_VIIF_DISABLE, &res->capture_reg->sys.IPORTS_IMGEN);
> > +
> > + /* Stop VDMAC for all table ports, input ports and write ports */
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->vdm.VDM_T_ENABLE);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->vdm.VDM_R_ENABLE);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->vdm.VDM_W_ENABLE);
> > +
> > + /* Stop all groups(g00, g01 and g02) of VDMAC */
> > + writel(0x7, &res->capture_reg->vdm.VDM_ABORTSET);
> > +
> > + timeout_ns = ktime_get_ns() +
> HWD_VIIF_WAIT_ABORT_COMPLETE_TIME * 1000;
> > +
> > + do {
> > + /* Get VDMAC transfer status */
> > + status_r = readl(&res->capture_reg->vdm.VDM_R_RUN);
> > + status_w = readl(&res->capture_reg->vdm.VDM_W_RUN);
> > + status_t = readl(&res->capture_reg->vdm.VDM_T_RUN);
> > +
> > + l2_status =
> readl(&res->capture_reg->l2isp.L2_BUS_L2_STATUS);
> > +
> > + if (status_r == 0U && status_w == 0U && status_t == 0U &&
> l2_status == 0U)
> > + run_flag = false;
> > +
> > + cur_ns = ktime_get_ns();
> > +
> > + if (cur_ns > timeout_ns) {
> > + ret = -ETIMEDOUT;
> > + run_flag = false;
> > + }
> > + } while (run_flag);
> > +
> > + if (ret == 0) {
> > + /* Clear run flag of MAIN unit */
> > + res->run_flag_main = false;
> > + }
> > +
> > + return ret;
> > +}
>
> [snip]
>
> > diff --git a/drivers/media/platform/visconti/hwd_viif_internal.h
> b/drivers/media/platform/visconti/hwd_viif_internal.h
> > new file mode 100644
> > index 00000000000..c954e804946
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_internal.h
> > @@ -0,0 +1,340 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_INTERNAL_H
> > +#define HWD_VIIF_INTERNAL_H
> > +
> > +#include "hwd_viif_reg.h"
> > +
> > +#define HWD_VIIF_CSI2_MAX_VC (3U)
> > +#define HWD_VIIF_CSI2_MIN_DT (0x10U)
> > +#define HWD_VIIF_CSI2_MAX_DT (0x3fU)
> > +#define HWD_VIIF_CSI2_MAX_WORD_COUNT (16384U)
> > +#define HWD_VIIF_CSI2_MAX_PACKET_NUM (8192U)
> > +#define HWD_VIIF_DPHY_MIN_DATA_RATE (80U)
> > +#define HWD_VIIF_DPHY_MAX_DATA_RATE (1500U)
> > +#define HWD_VIIF_DPHY_CFG_CLK_25M (32U)
> > +#define HWD_VIIF_DPHY_TRANSFER_HS_TABLE_NUM (43U)
> > +
> > +/* maximum horizontal/vertical position/dimension of CROP with ISP */
> > +#define HWD_VIIF_CROP_MAX_X_ISP (8062U)
> > +#define HWD_VIIF_CROP_MAX_Y_ISP (3966U)
> > +#define HWD_VIIF_CROP_MAX_W_ISP (8190U)
> > +#define HWD_VIIF_CROP_MAX_H_ISP (4094U)
> > +
> > +/* maximum horizontal/vertical position/dimension of CROP without ISP */
> > +#define HWD_VIIF_CROP_MAX_X (1920U)
> > +#define HWD_VIIF_CROP_MAX_Y (1408U)
> > +#define HWD_VIIF_CROP_MIN_W (128U)
> > +#define HWD_VIIF_CROP_MAX_W (2048U)
> > +#define HWD_VIIF_CROP_MIN_H (128U)
> > +#define HWD_VIIF_CROP_MAX_H (1536U)
> > +
> > +/* pixel clock: [kHz] */
> > +#define HWD_VIIF_MIN_PIXEL_CLOCK (3375U)
> > +#define HWD_VIIF_MAX_PIXEL_CLOCK (600000U)
> > +
> > +/* picture size: [pixel], [ns] */
> > +#define HWD_VIIF_MIN_HTOTAL_PIXEL (143U)
> > +#define HWD_VIIF_MIN_HTOTAL_NSEC (239U)
> > +#define HWD_VIIF_MAX_HTOTAL_PIXEL (65535U)
> > +#define HWD_VIIF_MAX_HTOTAL_NSEC (109225U)
> > +
> > +/* horizontal back porch size: [system clock] */
> > +#define HWD_VIIF_HBP_SYSCLK (10U)
> > +
> > +/* active picture size: [pixel] */
> > +#define HWD_VIIF_MIN_HACTIVE_PIXEL_WO_L1ISP (128U)
> > +#define HWD_VIIF_MAX_HACTIVE_PIXEL_WO_L1ISP (4096U)
> > +#define HWD_VIIF_MIN_HACTIVE_PIXEL_W_L1ISP (640U)
> > +#define HWD_VIIF_MAX_HACTIVE_PIXEL_W_L1ISP (3840U)
> > +
> > +/* picture vertical size: [line], [packet] */
> > +#define HWD_VIIF_MIN_VTOTAL_LINE (144U)
> > +#define HWD_VIIF_MAX_VTOTAL_LINE (16383U)
> > +#define HWD_VIIF_MIN_VBP_LINE (5U)
> > +#define HWD_VIIF_MAX_VBP_LINE (4095U)
> > +#define HWD_VIIF_MIN_VBP_PACKET (5U)
> > +#define HWD_VIIF_MAX_VBP_PACKET (4095U)
> > +#define HWD_VIIF_MIN_VACTIVE_LINE_WO_L1ISP (128U)
> > +#define HWD_VIIF_MAX_VACTIVE_LINE_WO_L1ISP (2160U)
> > +#define HWD_VIIF_MIN_VACTIVE_LINE_W_L1ISP (480U)
> > +#define HWD_VIIF_MAX_VACTIVE_LINE_W_L1ISP (2160U)
> > +
> > +/* image source select */
> > +#define HWD_VIIF_INPUT_CSI2 (0U)
>
> This macro is related to a hardware register, and should thus be moved
> to the hwd_viif_reg.h file. Same for other macros in this file as
> applicable.
I'll move it. Same for other macros.
> > +
> > +#define HWD_VIIF_CSC_MAX_OFFSET (0x0001FFFFU)
> > +#define HWD_VIIF_CSC_MAX_COEF_VALUE (0x0000FFFFU)
> > +#define HWD_VIIF_CSC_MAX_COEF_NUM (9U)
> > +#define HWD_VIIF_GAMMA_MAX_VSPLIT (4094U)
> > +#define HWD_VIIF_MTB_CB_YG_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_YG_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MTB_CB_CB_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_CB_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MTB_CB_CR_COEF_OFFSET (16U)
> > +#define HWD_VIIF_MTB_CR_CR_COEF_OFFSET (0U)
> > +#define HWD_VIIF_MAX_PITCH_ISP (32704U)
> > +#define HWD_VIIF_MAX_PITCH (65536U)
> > +
> > +/* size of minimum/maximum input image */
> > +#define HWD_VIIF_MIN_INPUT_IMG_WIDTH (128U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH_ISP (4096U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_WIDTH (2048U)
> > +#define HWD_VIIF_MIN_INPUT_IMG_HEIGHT (128U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT_ISP (2160U)
> > +#define HWD_VIIF_MAX_INPUT_IMG_HEIGHT (1536U)
> > +#define HWD_VIIF_MAX_INPUT_LINE_SIZE (16384U)
> > +
> > +/* size of minimum/maximum output image */
> > +#define HWD_VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> > +
> > +#define HWD_VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> > +#define HWD_VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> > +
> > +#define HWD_VIIF_NO_EVENT (0x0U)
>
> Just use 0 in the code, as for HWD_VIIF_DISABLE.
I'll fix it.
> > +
> > +/* System clock: [kHz] */
> > +#define HWD_VIIF_SYS_CLK (500000UL)
>
> Shouldn't the system clock rate be retrieved dynamically at runtime
> (possibly at probe time and cached) with clk_get_rate() instead of being
> hardcoded ?
Corresponding clock line is not defined yet in common clock framework for Visconti5.
Should I define 500MHz fixed clock in a device tree and refer to it for now?
> > +
> > +/*
> > + * wait time for force abort to complete(max 1line time = 1228.8[us]
> > + * when width = 4096, RAW24, 80Mbps
> > + */
> > +#define HWD_VIIF_WAIT_ABORT_COMPLETE_TIME (1229U)
> > +
> > +/*
> > + * complete time of register buffer transfer.
> > + * actual time is about 30us in case of L1ISP
> > + */
> > +#define HWD_VIIF_WAIT_ISP_REGBF_TRNS_COMPLETE_TIME (39U)
> > +
> > +/* internal operation latencies: [system clock]*/
> > +#define HWD_VIIF_TABLE_LOAD_TIME (24000UL)
> > +#define HWD_VIIF_REGBUF_ACCESS_TIME (15360UL)
> > +
> > +/* offset of Vsync delay: [line] */
> > +#define HWD_VIIF_L1_DELAY_W_HDRC (31U)
> > +#define HWD_VIIF_L1_DELAY_WO_HDRC (11U)
> > +
> > +/* data width is 32bit */
> > +#define HWD_VIIF_VDM_CFG_PARAM (0x00000210U)
> > +
> > +/* vsync mode is pulse */
> > +#define HWD_VIIF_DPGM_VSYNC_PULSE (1U)
> > +
> > +/* Vlatch mask bit for L1ISP and L2ISP */
> > +#define HWD_VIIF_ISP_VLATCH_MASK (2U)
> > +
> > +/* Register buffer */
> > +#define HWD_VIIF_ISP_MAX_CONTEXT_NUM (4U)
> > +#define HWD_VIIF_ISP_REGBUF_MODE_BYPASS (0U)
> > +#define HWD_VIIF_ISP_REGBUF_MODE_BUFFER (1U)
> > +#define HWD_VIIF_ISP_REGBUF_READ (1U)
>
> [snip]
>
> > +/**
> > + * struct hwd_viif_l2_roi_path_info - L2ISP ROI path control information
> > + *
> > + * @roi_num: the number of ROIs which are used.
> > + * @post_enable_flag: flag to show which of POST is enabled.
> > + * @post_crop_x: CROP x of each L2ISP POST
> > + * @post_crop_y: CROP y of each L2ISP POST
> > + * @post_crop_w: CROP w of each L2ISP POST
> > + * @post_crop_h: CROP h of each L2ISP POST
> > + */
> > +struct hwd_viif_l2_roi_path_info {
> > + u32 roi_num;
> > + bool post_enable_flag[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_x[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_y[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_w[HWD_VIIF_MAX_POST_NUM];
> > + u32 post_crop_h[HWD_VIIF_MAX_POST_NUM];
> > +};
> > +
> > +/**
> > + * struct hwd_viif_res - driver internal resource structure
> > + *
> > + * @clock_id: clock ID of each unit
> > + * @csi2_clock_id: clock ID of CSI-2 RX
> > + * @csi2_reset_id: reset ID of CSI-2 RX
> > + * @pixel_clock: pixel clock
> > + * @htotal_size: horizontal total size
> > + * @dt_image_main_w_isp: Data type of image data for ISP path
> > + * @csi2host_reg: pointer to register access structure of CSI-2 RX host
> controller
> > + * @capture_reg: pointer to register access structure of capture unit
> > + * @l2_roi_path_info: ROI path information of L2ISP
> > + * @run_flag_main: run flag of MAIN unit(true: run, false: not run)
> > + */
> > +struct hwd_viif_res {
> > + //u32 clock_id;
> > + //u32 csi2_clock_id;
> > + //u32 csi2_reset_id;
>
> Please drop commented-out code.
I'll remove them.
> > + u32 pixel_clock;
> > + u32 htotal_size;
> > + u32 dt_image_main_w_isp;
> > + struct hwd_viif_csi2host_reg *csi2host_reg;
> > + struct hwd_viif_capture_reg *capture_reg;
> > + struct hwd_viif_l2_roi_path_info l2_roi_path_info;
> > + bool run_flag_main;
> > +};
> > +
> > +/**
> > + * struct hwd_viif_dphy_hs_info - dphy hs information
> > + *
> > + * @rate: Data rate [Mbps]
> > + * @hsfreqrange: IP operating frequency(hsfreqrange)
> > + * @osc_freq_target: DDL target oscillation frequency(osc_freq_target)
> > + */
> > +struct hwd_viif_dphy_hs_info {
> > + u32 rate;
> > + u32 hsfreqrange;
> > + u32 osc_freq_target;
> > +};
> > +
> > +#endif /* HWD_VIIF_INTERNAL_H */
> > diff --git a/drivers/media/platform/visconti/hwd_viif_reg.h
> b/drivers/media/platform/visconti/hwd_viif_reg.h
> > new file mode 100644
> > index 00000000000..b7f43c5fe95
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_reg.h
> > @@ -0,0 +1,2802 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef HWD_VIIF_REG_H
> > +#define HWD_VIIF_REG_H
> > +
> > +/**
> > + * struct hwd_viif_csi2host_reg - Registers for VIIF CSI2HOST control
> > + */
> > +struct hwd_viif_csi2host_reg {
>
> As noted by Sakari in his review, kernel drivers usually use macros for
> register addresses. I'm not entirely opposed to using structures, but I
> share his concerns. Furthermore, macros would allow writing convenience
> wrappers around writel():
>
> struct viif_csi2rx
> {
> ...
> void __iomem *regs;
> ...
> };
>
> static inline void viif_csi2rx_write(struct viif_csi2rx *csi2rx, u32 reg, u32 val)
> {
> writel(val, csi2rx->regs + reg);
> }
>
> Similar functions can be written for other register spaces. This
> improves (I think) code readability (I may be biased though).
>
I'll remove register-style definition and introduce macro-style definition.
> In any case, grouping all register definitions in a file, separate from
> the rest of the headers, is nice, but register bits should also be
> defined in the same file, as macros. For instance, in
> viif_csi2rx_initialize() you have
>
> /* Define errors to be masked */
> csi2rx_mask.mask[0] = 0x0000000F; /*check all for PHY_FATAL*/
> csi2rx_mask.mask[1] = 0x0001000F; /*check all for PKT_FATAL*/
> csi2rx_mask.mask[2] = 0x000F0F0F; /*check all for FRAME_FATAL*/
> csi2rx_mask.mask[3] = 0x000F000F; /*check all for PHY*/
> csi2rx_mask.mask[4] = 0x000F000F; /*check all for PKT*/
> csi2rx_mask.mask[5] = 0x00FF00FF; /*check all for LINE*/
>
> return hwd_viif_csi2rx_initialize(viif_dev->hwd_res, num_lane,
> HWD_VIIF_CSI2_DPHY_L0L1L2L3,
> dphy_rate, HWD_VIIF_ENABLE,
> &err_target, &csi2rx_mask);
>
> where csi2rx_mask is then written to the CSI2RX_INT_MSK_* registers.
> Those numerical values should use macros that name the bits. The macros
> should be named according to the register they're related to (something
> like VIIF_CSI2RX_INT_MSK_PHY_FATAL_* for the
> CSI2RX_INT_MSK_PHY_FATAL
> register for instance). I would also place them right after the
> CSI2RX_INT_MSK_PHY_FATAL field below, in order to group registers and
> their bits together:
>
> u32 CSI2RX_INT_MSK_PHY_FATAL;
> #define VIIF_CSI2RX_INT_MSK_PHY_FATAL_FOO BIT(0)
> #define VIIF_CSI2RX_INT_MSK_PHY_FATAL_BAR BIT(1)
> ...
> u32 CSI2RX_INT_FORCE_PHY_FATAL;
> ...
I'll put register bit definitions right after the corresponding register defininition.
> > + u32 RESERVED_A_1;
> > + u32 CSI2RX_NLANES;
> > + u32 CSI2RX_RESETN;
> > + u32 CSI2RX_INT_ST_MAIN;
> > + u32 CSI2RX_DATA_IDS_1;
> > + u32 CSI2RX_DATA_IDS_2;
> > + u32 RESERVED_B_1[10];
> > + u32 CSI2RX_PHY_SHUTDOWNZ;
> > + u32 CSI2RX_PHY_RSTZ;
> > + u32 CSI2RX_PHY_RX;
> > + u32 CSI2RX_PHY_STOPSTATE;
> > + u32 CSI2RX_PHY_TESTCTRL0;
> > + u32 CSI2RX_PHY_TESTCTRL1;
> > + u32 RESERVED_B_2[34];
> > + u32 CSI2RX_INT_ST_PHY_FATAL;
> > + u32 CSI2RX_INT_MSK_PHY_FATAL;
> > + u32 CSI2RX_INT_FORCE_PHY_FATAL;
> > + u32 RESERVED_B_3[1];
> > + u32 CSI2RX_INT_ST_PKT_FATAL;
> > + u32 CSI2RX_INT_MSK_PKT_FATAL;
> > + u32 CSI2RX_INT_FORCE_PKT_FATAL;
> > + u32 RESERVED_B_4[1];
> > + u32 CSI2RX_INT_ST_FRAME_FATAL;
> > + u32 CSI2RX_INT_MSK_FRAME_FATAL;
> > + u32 CSI2RX_INT_FORCE_FRAME_FATAL;
> > + u32 RESERVED_B_5[1];
> > + u32 CSI2RX_INT_ST_PHY;
> > + u32 CSI2RX_INT_MSK_PHY;
> > + u32 CSI2RX_INT_FORCE_PHY;
> > + u32 RESERVED_B_6[1];
> > + u32 CSI2RX_INT_ST_PKT;
> > + u32 CSI2RX_INT_MSK_PKT;
> > + u32 CSI2RX_INT_FORCE_PKT;
> > + u32 RESERVED_B_7[1];
> > + u32 CSI2RX_INT_ST_LINE;
> > + u32 CSI2RX_INT_MSK_LINE;
> > + u32 CSI2RX_INT_FORCE_LINE;
> > + u32 RESERVED_B_8[113];
> > + u32 RESERVED_A_2;
> > + u32 RESERVED_A_3;
> > + u32 RESERVED_A_4;
> > + u32 RESERVED_A_5;
> > + u32 RESERVED_A_6;
>
> Can this be written
>
> u32 RESERVED_A_2_6[5];
>
> ? There are large blocks of reserved registers below, it would help
> shortening the file.
>
> > + u32 RESERVED_B_9[58];
> > + u32 RESERVED_A_7;
> > +};
>
> [snip]
>
> > +/**
> > + * struct hwd_viif_l1isp_reg - Registers for VIIF L1ISP control
> > + */
> > +struct hwd_viif_l1isp_reg {
> > + u32 L1_SYSM_WIDTH;
> > + u32 L1_SYSM_HEIGHT;
> > + u32 L1_SYSM_START_COLOR;
> > + u32 L1_SYSM_INPUT_MODE;
> > + u32 RESERVED_A_1;
> > + u32 L1_SYSM_YCOEF_R;
> > + u32 L1_SYSM_YCOEF_G;
> > + u32 L1_SYSM_YCOEF_B;
> > + u32 L1_SYSM_INT_STAT;
> > + u32 L1_SYSM_INT_MASKED_STAT;
> > + u32 L1_SYSM_INT_MASK;
> > + u32 RESERVED_A_2;
> > + u32 RESERVED_A_3;
> > + u32 RESERVED_A_4;
> > + u32 RESERVED_B_1[2];
> > + u32 L1_SYSM_AG_H;
> > + u32 L1_SYSM_AG_M;
> > + u32 L1_SYSM_AG_L;
> > + u32 L1_SYSM_AG_PARAM_A;
> > + u32 L1_SYSM_AG_PARAM_B;
> > + u32 L1_SYSM_AG_PARAM_C;
> > + u32 L1_SYSM_AG_PARAM_D;
> > + u32 L1_SYSM_AG_SEL_HOBC;
> > + u32 L1_SYSM_AG_SEL_ABPC;
> > + u32 L1_SYSM_AG_SEL_RCNR;
> > + u32 L1_SYSM_AG_SEL_LSSC;
> > + u32 L1_SYSM_AG_SEL_MPRO;
> > + u32 L1_SYSM_AG_SEL_VPRO;
> > + u32 L1_SYSM_AG_CONT_HOBC01_EN;
> > + u32 L1_SYSM_AG_CONT_HOBC2_EN;
> > + u32 L1_SYSM_AG_CONT_ABPC01_EN;
> > + u32 L1_SYSM_AG_CONT_ABPC2_EN;
> > + u32 L1_SYSM_AG_CONT_RCNR01_EN;
> > + u32 L1_SYSM_AG_CONT_RCNR2_EN;
> > + u32 L1_SYSM_AG_CONT_LSSC_EN;
> > + u32 L1_SYSM_AG_CONT_MPRO_EN;
> > + u32 L1_SYSM_AG_CONT_VPRO_EN;
> > + u32 L1_SYSM_CTXT;
> > + u32 L1_SYSM_MAN_CTXT;
> > + u32 RESERVED_A_5;
> > + u32 RESERVED_B_2[7];
> > + u32 RESERVED_A_6;
> > + u32 L1_HDRE_SRCPOINT00;
> > + u32 L1_HDRE_SRCPOINT01;
> > + u32 L1_HDRE_SRCPOINT02;
> > + u32 L1_HDRE_SRCPOINT03;
> > + u32 L1_HDRE_SRCPOINT04;
> > + u32 L1_HDRE_SRCPOINT05;
> > + u32 L1_HDRE_SRCPOINT06;
> > + u32 L1_HDRE_SRCPOINT07;
> > + u32 L1_HDRE_SRCPOINT08;
> > + u32 L1_HDRE_SRCPOINT09;
> > + u32 L1_HDRE_SRCPOINT10;
> > + u32 L1_HDRE_SRCPOINT11;
> > + u32 L1_HDRE_SRCPOINT12;
> > + u32 L1_HDRE_SRCPOINT13;
> > + u32 L1_HDRE_SRCPOINT14;
> > + u32 L1_HDRE_SRCPOINT15;
>
> This also seems to be a candidate for an array:
>
> u32 L1_HDRE_SRCPOINT[16];
>
> Not only will it shorten this file, it will also make the code simpler
> as you'll be able to replace
>
> writel(param->hdre_src_point[0],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT00);
> writel(param->hdre_src_point[1],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT01);
> writel(param->hdre_src_point[2],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT02);
> writel(param->hdre_src_point[3],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT03);
> writel(param->hdre_src_point[4],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT04);
> writel(param->hdre_src_point[5],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT05);
> writel(param->hdre_src_point[6],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT06);
> writel(param->hdre_src_point[7],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT07);
> writel(param->hdre_src_point[8],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT08);
> writel(param->hdre_src_point[9],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT09);
> writel(param->hdre_src_point[10],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT10);
> writel(param->hdre_src_point[11],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT11);
> writel(param->hdre_src_point[12],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT12);
> writel(param->hdre_src_point[13],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT13);
> writel(param->hdre_src_point[14],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT14);
> writel(param->hdre_src_point[15],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT15);
>
> with
>
> for (i = 0; i < ARRAY_SIZE(param->hdre_src_point); ++i)
> writel(param->hdre_src_point[i],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT[i]);
>
> Same in quite a few other locations.
I'll keep it in mind when I design macro-style definitions.
> [snip]
>
> > +};
>
> [snip]
>
> > diff --git a/include/uapi/linux/visconti_viif.h
> b/include/uapi/linux/visconti_viif.h
> > new file mode 100644
> > index 00000000000..f92278425b7
> > --- /dev/null
> > +++ b/include/uapi/linux/visconti_viif.h
> > @@ -0,0 +1,1724 @@
> > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef __UAPI_VISCONTI_VIIF_H_
> > +#define __UAPI_VISCONTI_VIIF_H_
> > +
> > +#include <linux/types.h>
> > +#include <linux/videodev2.h>
> > +
> > +/* Visconti specific compound controls */
> > +#define V4L2_CID_VISCONTI_VIIF_BASE
> (V4L2_CID_USER_BASE + 0x1000)
> > +#define V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE
> (V4L2_CID_VISCONTI_VIIF_BASE + 1)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE
> (V4L2_CID_VISCONTI_VIIF_BASE + 2)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF
> (V4L2_CID_VISCONTI_VIIF_BASE + 3)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE
> (V4L2_CID_VISCONTI_VIIF_BASE + 4)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG
> (V4L2_CID_VISCONTI_VIIF_BASE + 5)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE
> (V4L2_CID_VISCONTI_VIIF_BASE + 6)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION
> (V4L2_CID_VISCONTI_VIIF_BASE + 7)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC
> (V4L2_CID_VISCONTI_VIIF_BASE + 8)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE
> (V4L2_CID_VISCONTI_VIIF_BASE + 9)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION
> \
> > + (V4L2_CID_VISCONTI_VIIF_BASE + 10)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS
> (V4L2_CID_VISCONTI_VIIF_BASE + 11)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION
> (V4L2_CID_VISCONTI_VIIF_BASE + 12)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC
> (V4L2_CID_VISCONTI_VIIF_BASE + 13)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS
> (V4L2_CID_VISCONTI_VIIF_BASE + 14)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB
> (V4L2_CID_VISCONTI_VIIF_BASE + 15)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN
> (V4L2_CID_VISCONTI_VIIF_BASE + 16)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC
> (V4L2_CID_VISCONTI_VIIF_BASE + 17)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM
> (V4L2_CID_VISCONTI_VIIF_BASE + 18)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA
> (V4L2_CID_VISCONTI_VIIF_BASE + 19)
> > +#define
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT
> (V4L2_CID_VISCONTI_VIIF_BASE + 20)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION
> (V4L2_CID_VISCONTI_VIIF_BASE + 21)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST
> (V4L2_CID_VISCONTI_VIIF_BASE + 22)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI
> (V4L2_CID_VISCONTI_VIIF_BASE + 23)
> > +#define V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA
> (V4L2_CID_VISCONTI_VIIF_BASE + 24)
> > +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS
> (V4L2_CID_VISCONTI_VIIF_BASE + 25)
> > +#define V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS
> (V4L2_CID_VISCONTI_VIIF_BASE + 26)
> > +#define V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS
> (V4L2_CID_VISCONTI_VIIF_BASE + 27)
> > +#define V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS
> (V4L2_CID_VISCONTI_VIIF_BASE + 28)
>
> First of all, thank you for taking the time to write all these, as well
> as the control documentation.
>
> This is a *lot* of controls, and each of them store a potentially large
> quantity of data. Unless I'm mistaken, the driver doesn't use the
> request API, which means that there's no synchronization between control
> values and frames. Isn't that a problem ? I'm wondering if a mechanism
> based on parameters buffers (like the rkisp1 driver for instance)
> wouldn't be a better fit.
Generally, Visconti5 ISPs capture register values at delayed-Vsync event.
Also, every function writing to registers is enclosed by hwd_viif_isp_guard_{start,end}() which disable the capture.
Therefore, we don't need a special care for setting control values.
There should have been a document about that. I'll add it.
The problem is that a register write just around delayed-Vsync event disturbs the capture. ISPs run with the configuration for the previous frame.
I assume that is not a big problem because most of the ISP control requests from userland will be issued just after delayed-VSync for typical usecase.
The driver enqueues a buffer at delayed-VSync event, and a userland waits for a new buffer with poll().
Hmm ... I should not make any assumption on the operations of userland?
As for introducing parameter buffers, a problem is increased latency of configuration change.
User requests are stored in parameter buffer, then set to registers at next delayed-VSync.
After that, ISP loads the configuration at next delayed-VSync. There's additional one frame for configuration.
I might need to turn on a currently unused interrupt to handle the parameter buffer earlier.
> > +/* Enable/Disable flag */
> > +#define VIIF_DISABLE (0U)
> > +#define VIIF_ENABLE (1U)
>
> No need for parentheses.
I'll fix them.
> [snip]
>
> > +#endif /* __UAPI_VISCONTI_VIIF_H_ */
>
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-11 2:24 [PATCH v5 0/6] Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
2023-01-11 2:24 ` [PATCH v5 1/6] dt-bindings: media: platform: visconti: Add Toshiba Visconti Video Input Interface bindings Yuji Ishikawa
2023-01-11 2:24 ` [PATCH v5 2/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
@ 2023-01-11 2:24 ` Yuji Ishikawa
2023-01-17 11:47 ` Hans Verkuil
2023-01-11 2:24 ` [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler Yuji Ishikawa
` (2 subsequent siblings)
5 siblings, 1 reply; 42+ messages in thread
From: Yuji Ishikawa @ 2023-01-11 2:24 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree, yuji2.ishikawa
Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
The interface device includes CSI2 Receiver,
frame grabber, video DMAC and image signal processor.
This patch provides the user interface layer.
A driver instance provides three /dev/videoX device files;
one for RGB image capture, another one for optional RGB capture
with different parameters and the last one for RAW capture.
Through the device files, the driver provides streaming (DMA-BUF) interface.
A userland application should feed DMA-BUF instances for capture buffers.
The driver is based on media controller framework.
Its operations are roughly mapped to two subdrivers;
one for ISP and CSI2 receiver (yields 1 instance),
the other for capture (yields 3 instances for each capture mode).
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
---
Changelog v2:
- Resend v1 because a patch exceeds size limit.
Changelog v3:
- Adapted to media control framework
- Introduced ISP subdevice, capture device
- Remove private IOCTLs and add vendor specific V4L2 controls
- Change function name avoiding camelcase and uppercase letters
Changelog v4:
- Split patches because the v3 patch exceeds size limit
- Stop using ID number to identify driver instance:
- Use dynamically allocated structure to hold HW specific context,
instead of static one.
- Call HW layer functions with the context structure instead of ID number
- Use pm_runtime to trigger initialization of HW
along with open/close of device files.
Changelog v5:
- Fix coding style problems in viif.c
---
drivers/media/platform/visconti/Makefile | 1 +
drivers/media/platform/visconti/viif.c | 545 ++++++++
drivers/media/platform/visconti/viif.h | 203 +++
.../media/platform/visconti/viif_capture.c | 1201 +++++++++++++++++
drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
5 files changed, 2796 insertions(+)
create mode 100644 drivers/media/platform/visconti/viif.c
create mode 100644 drivers/media/platform/visconti/viif.h
create mode 100644 drivers/media/platform/visconti/viif_capture.c
create mode 100644 drivers/media/platform/visconti/viif_isp.c
diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
index e14b904df75..d7a23c1f4e8 100644
--- a/drivers/media/platform/visconti/Makefile
+++ b/drivers/media/platform/visconti/Makefile
@@ -3,6 +3,7 @@
# Makefile for the Visconti video input device driver
#
+visconti-viif-objs = viif.o viif_capture.o viif_isp.o
visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
diff --git a/drivers/media/platform/visconti/viif.c b/drivers/media/platform/visconti/viif.c
new file mode 100644
index 00000000000..e29480dbb76
--- /dev/null
+++ b/drivers/media/platform/visconti/viif.c
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-fwnode.h>
+
+#include "viif.h"
+
+static inline struct viif_device *v4l2_to_viif(struct v4l2_device *v4l2_dev)
+{
+ return container_of(v4l2_dev, struct viif_device, v4l2_dev);
+}
+
+static struct viif_subdev *to_viif_subdev(struct v4l2_async_subdev *asd)
+{
+ return container_of(asd, struct viif_subdev, asd);
+}
+
+/* VSYNC mask setting of MAIN unit */
+#define INT_M_SYNC_MASK_VSYNC_INT BIT(0)
+#define INT_M_SYNC_MASK_LINES_DELAY_INT1 BIT(1)
+#define INT_M_SYNC_MASK_LINES_DELAY_INT2 BIT(2)
+#define INT_M_SYNC_MASK_SW_DELAY_INT0 BIT(16)
+#define INT_M_SYNC_MASK_SW_DELAY_INT1 BIT(17)
+#define INT_M_SYNC_MASK_SW_DELAY_INT2 BIT(18)
+
+/* STATUS error mask setting of MAIN unit */
+#define INT_M_MASK_L2ISP_SIZE_ERROR BIT(0)
+#define INT_M_MASK_CRGBF_INTCRGERR_WRSTART BIT(1)
+#define INT_M_MASK_CRGBF_INTCRGERR_RDSTART BIT(2)
+#define INT_M_MASK_EMBED_ERROR BIT(3)
+#define INT_M_MASK_USERDATA_ERROR BIT(4)
+#define INT_M_MASK_L2ISP_POST0_TABLE_TIMEOUT BIT(8)
+#define INT_M_MASK_L2ISP_POST1_TABLE_TIMEOUT BIT(9)
+#define INT_M_MASK_L2ISP_GRID_TABLE_TIMEOUT BIT(11)
+#define INT_M_MASK_L1ISP_SIZE_ERROR0 BIT(16)
+#define INT_M_MASK_L1ISP_SIZE_ERROR1 BIT(17)
+#define INT_M_MASK_L1ISP_SIZE_ERROR2 BIT(18)
+#define INT_M_MASK_L1ISP_SIZE_ERROR3 BIT(19)
+#define INT_M_MASK_L1ISP_SIZE_ERROR4 BIT(20)
+#define INT_M_MASK_L1ISP_INT_ERR_CRGWRSTART BIT(21)
+#define INT_M_MASK_L1ISP_INT_ERR_CRGRDSTART BIT(22)
+#define INT_M_MASK_DELAY_INT_ERROR BIT(24)
+
+/* VSYNC mask settings of SUB unit */
+#define INT_S_SYNC_MASK_VSYNC_INT BIT(0)
+#define INT_S_SYNC_MASK_LINES_DELAY_INT1 BIT(1)
+#define INT_S_SYNC_MASK_SW_DELAY_INT0 BIT(16)
+#define INT_S_SYNC_MASK_SW_DELAY_INT1 BIT(17)
+
+/* STATUS error mask setting of SUB unit */
+#define INT_S_MASK_SIZE_ERROR BIT(0)
+#define INT_S_MASK_EMBED_ERROR BIT(1)
+#define INT_S_MASK_USERDATA_ERROR BIT(2)
+#define INT_S_MASK_DELAY_INT_ERROR BIT(24)
+#define INT_S_MASK_RESERVED_SET (BIT(16) | BIT(28))
+
+static void viif_vsync_irq_handler_w_isp(struct viif_device *viif_dev)
+{
+ u32 event_main, event_sub, status_err, l2_transfer_status;
+ u64 ts;
+
+ ts = ktime_get_ns();
+ hwd_viif_vsync_irq_handler(viif_dev->hwd_res, &event_main, &event_sub);
+
+ /* Delayed Vsync of MAIN unit */
+ if (event_main & INT_M_SYNC_MASK_LINES_DELAY_INT2) {
+ /* unmask timeout error of gamma table */
+ hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res,
+ INT_M_MASK_DELAY_INT_ERROR);
+ viif_dev->masked_gamma_path = 0;
+
+ /* Get abort status of L2ISP */
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ hwd_viif_isp_get_info(viif_dev->hwd_res, NULL, &l2_transfer_status);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+
+ status_err = viif_dev->status_err;
+ viif_dev->status_err = 0;
+
+ visconti_viif_capture_switch_buffer(&viif_dev->cap_dev0, status_err,
+ l2_transfer_status, ts);
+ visconti_viif_capture_switch_buffer(&viif_dev->cap_dev1, status_err,
+ l2_transfer_status, ts);
+ }
+
+ /* Delayed Vsync of SUB unit */
+ if (event_sub & INT_S_SYNC_MASK_LINES_DELAY_INT1)
+ visconti_viif_capture_switch_buffer(&viif_dev->cap_dev2, 0, 0, ts);
+}
+
+#define MASK_M_GAMMATBL_TIMEOUT 0x0700U
+
+static void viif_status_err_irq_handler(struct viif_device *viif_dev)
+{
+ u32 event_main, event_sub, val, mask;
+
+ hwd_viif_status_err_irq_handler(viif_dev->hwd_res, &event_main, &event_sub);
+
+ if (event_main) {
+ /* mask for gamma table time out error which will be unmasked in the next Vsync */
+ val = FIELD_GET(MASK_M_GAMMATBL_TIMEOUT, event_main);
+ if (val) {
+ viif_dev->masked_gamma_path |= val;
+ mask = INT_M_MASK_DELAY_INT_ERROR |
+ FIELD_PREP(MASK_M_GAMMATBL_TIMEOUT, viif_dev->masked_gamma_path);
+ hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res, mask);
+ }
+
+ viif_dev->status_err = event_main;
+ }
+ viif_dev->reported_err_main |= event_main;
+ viif_dev->reported_err_sub |= event_sub;
+ dev_err(viif_dev->dev, "MAIN/SUB error 0x%x 0x%x.\n", event_main, event_sub);
+}
+
+static void viif_csi2rx_err_irq_handler(struct viif_device *viif_dev)
+{
+ u32 event;
+
+ event = hwd_viif_csi2rx_err_irq_handler(viif_dev->hwd_res);
+ viif_dev->reported_err_csi2rx |= event;
+ dev_err(viif_dev->dev, "CSI2RX error 0x%x.\n", event);
+}
+
+static irqreturn_t visconti_viif_irq(int irq, void *dev_id)
+{
+ struct viif_device *viif_dev = dev_id;
+ int irq_type = irq - viif_dev->irq[0];
+
+ spin_lock(&viif_dev->lock);
+
+ switch (irq_type) {
+ case 0:
+ viif_vsync_irq_handler_w_isp(viif_dev);
+ break;
+ case 1:
+ viif_status_err_irq_handler(viif_dev);
+ break;
+ case 2:
+ viif_csi2rx_err_irq_handler(viif_dev);
+ break;
+ }
+
+ spin_unlock(&viif_dev->lock);
+
+ return IRQ_HANDLED;
+}
+
+/* ----- Async Notifier Operations----- */
+static int visconti_viif_notify_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *v4l2_sd, struct v4l2_async_subdev *asd)
+{
+ struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
+ struct viif_device *viif_dev = v4l2_to_viif(v4l2_dev);
+ struct viif_subdev *viif_sd = to_viif_subdev(asd);
+
+ viif_sd->v4l2_sd = v4l2_sd;
+ viif_dev->num_sd++;
+
+ return 0;
+}
+
+static void visconti_viif_create_links(struct viif_device *viif_dev)
+{
+ unsigned int source_pad;
+ int ret;
+
+ /* camera subdev pad0 -> isp suddev pad0 */
+ ret = media_entity_get_fwnode_pad(&viif_dev->sd->v4l2_sd->entity,
+ viif_dev->sd->v4l2_sd->fwnode, MEDIA_PAD_FL_SOURCE);
+ if (ret < 0) {
+ dev_err(viif_dev->dev, "failed to find source pad\n");
+ return;
+ }
+ source_pad = ret;
+
+ ret = media_create_pad_link(&viif_dev->sd->v4l2_sd->entity, source_pad,
+ &viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED);
+ if (ret)
+ dev_err(viif_dev->dev, "failed create_pad_link (camera:src -> isp:sink)\n");
+
+ ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SRC_PATH0,
+ &viif_dev->cap_dev0.vdev.entity, VIIF_CAPTURE_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED);
+ if (ret)
+ dev_err(viif_dev->dev, "failed create_pad_link (isp:src -> capture0:sink)\n");
+
+ ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SRC_PATH1,
+ &viif_dev->cap_dev1.vdev.entity, VIIF_CAPTURE_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED);
+ if (ret)
+ dev_err(viif_dev->dev, "failed create_pad_link (isp:src -> capture1:sink)\n");
+
+ ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SRC_PATH2,
+ &viif_dev->cap_dev2.vdev.entity, VIIF_CAPTURE_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED);
+ if (ret)
+ dev_err(viif_dev->dev, "failed create_pad_link (isp:src -> capture2:sink)\n");
+}
+
+static void visconti_viif_notify_unbind(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *subdev, struct v4l2_async_subdev *asd)
+{
+ struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
+ struct viif_subdev *viif_sd = to_viif_subdev(asd);
+
+ v4l2_dev->ctrl_handler = NULL;
+ viif_sd->v4l2_sd = NULL;
+}
+
+static int visconti_viif_notify_complete(struct v4l2_async_notifier *notifier)
+{
+ struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
+ struct viif_device *viif_dev = v4l2_to_viif(v4l2_dev);
+ int ret;
+
+ ret = v4l2_device_register_subdev_nodes(v4l2_dev);
+ if (ret < 0) {
+ dev_err(v4l2_dev->dev, "Failed to register subdev nodes\n");
+ return ret;
+ }
+
+ /* Make sure at least one sensor is primary and use it to initialize */
+ if (!viif_dev->sd) {
+ viif_dev->sd = &viif_dev->subdevs[0];
+ viif_dev->sd_index = 0;
+ }
+
+ ret = visconti_viif_capture_register_ctrl_handlers(viif_dev);
+ if (ret)
+ return ret;
+
+ visconti_viif_create_links(viif_dev);
+
+ return 0;
+}
+
+static const struct v4l2_async_notifier_operations viif_notify_ops = {
+ .bound = visconti_viif_notify_bound,
+ .unbind = visconti_viif_notify_unbind,
+ .complete = visconti_viif_notify_complete,
+};
+
+/* ----- Probe and Remove ----- */
+static int visconti_viif_init_async_subdevs(struct viif_device *viif_dev, unsigned int n_sd)
+{
+ /* Reserve memory for 'n_sd' viif_subdev descriptors. */
+ viif_dev->subdevs =
+ devm_kcalloc(viif_dev->dev, n_sd, sizeof(*viif_dev->subdevs), GFP_KERNEL);
+ if (!viif_dev->subdevs)
+ return -ENOMEM;
+
+ /* Reserve memory for 'n_sd' pointers to async_subdevices.
+ * viif_dev->asds members will point to &viif_dev.asd
+ */
+ viif_dev->asds = devm_kcalloc(viif_dev->dev, n_sd, sizeof(*viif_dev->asds), GFP_KERNEL);
+ if (!viif_dev->asds)
+ return -ENOMEM;
+
+ viif_dev->sd = NULL;
+ viif_dev->sd_index = 0;
+ viif_dev->num_sd = 0;
+
+ return 0;
+}
+
+static int visconti_viif_parse_dt(struct viif_device *viif_dev)
+{
+ struct device_node *of = viif_dev->dev->of_node;
+ struct v4l2_fwnode_endpoint fw_ep;
+ struct viif_subdev *viif_sd;
+ struct device_node *ep;
+ unsigned int i;
+ int num_ep;
+ int ret;
+
+ memset(&fw_ep, 0, sizeof(struct v4l2_fwnode_endpoint));
+
+ num_ep = of_graph_get_endpoint_count(of);
+ if (!num_ep)
+ return -ENODEV;
+
+ ret = visconti_viif_init_async_subdevs(viif_dev, num_ep);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_ep; i++) {
+ ep = of_graph_get_endpoint_by_regs(of, 0, i);
+ if (!ep) {
+ dev_err(viif_dev->dev, "No subdevice connected on endpoint %u.\n", i);
+ ret = -ENODEV;
+ goto error_put_node;
+ }
+
+ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
+ if (ret) {
+ dev_err(viif_dev->dev, "Unable to parse endpoint #%u.\n", i);
+ goto error_put_node;
+ }
+
+ if (fw_ep.bus_type != V4L2_MBUS_CSI2_DPHY ||
+ fw_ep.bus.mipi_csi2.num_data_lanes == 0) {
+ dev_err(viif_dev->dev, "missing CSI-2 properties in endpoint\n");
+ ret = -EINVAL;
+ goto error_put_node;
+ }
+
+ /* Setup the ceu subdevice and the async subdevice. */
+ viif_sd = &viif_dev->subdevs[i];
+ INIT_LIST_HEAD(&viif_sd->asd.list);
+
+ viif_sd->mbus_flags = fw_ep.bus.mipi_csi2.flags;
+ viif_sd->num_lane = fw_ep.bus.mipi_csi2.num_data_lanes;
+ viif_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
+ viif_sd->asd.match.fwnode =
+ fwnode_graph_get_remote_port_parent(of_fwnode_handle(ep));
+
+ viif_dev->asds[i] = &viif_sd->asd;
+ of_node_put(ep);
+ }
+
+ return num_ep;
+
+error_put_node:
+ of_node_put(ep);
+ return ret;
+}
+
+static const struct of_device_id visconti_viif_of_table[] = {
+ {
+ .compatible = "toshiba,visconti-viif",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, visconti_viif_of_table);
+
+#define NUM_IRQS 3
+#define IRQ_ID_STR "viif"
+#define MEDIA_MODEL "visconti_viif"
+#define MEDIA_BUS_INFO "platform:visconti_viif"
+
+static int visconti_viif_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *of_id;
+ struct device *dev = &pdev->dev;
+ struct viif_device *viif_dev;
+ dma_addr_t table_paddr;
+ int ret, i, num_sd;
+
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
+ if (ret)
+ return ret;
+
+ viif_dev = devm_kzalloc(dev, sizeof(*viif_dev), GFP_KERNEL);
+ if (!viif_dev)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, viif_dev);
+ viif_dev->dev = dev;
+
+ spin_lock_init(&viif_dev->lock);
+ mutex_init(&viif_dev->pow_lock);
+
+ viif_dev->capture_reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(viif_dev->capture_reg))
+ return PTR_ERR(viif_dev->capture_reg);
+
+ viif_dev->csi2host_reg = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(viif_dev->csi2host_reg))
+ return PTR_ERR(viif_dev->csi2host_reg);
+
+ viif_dev->hwd_res = allocate_viif_res(dev, viif_dev->csi2host_reg, viif_dev->capture_reg);
+
+ for (i = 0; i < NUM_IRQS; i++) {
+ ret = platform_get_irq(pdev, i);
+ if (ret < 0) {
+ dev_err(dev, "failed to acquire irq resource\n");
+ return ret;
+ }
+ viif_dev->irq[i] = ret;
+ ret = devm_request_irq(dev, viif_dev->irq[i], visconti_viif_irq, 0, IRQ_ID_STR,
+ viif_dev);
+ if (ret) {
+ dev_err(dev, "irq request failed\n");
+ return ret;
+ }
+ }
+
+ viif_dev->table_vaddr =
+ dma_alloc_wc(dev, sizeof(struct viif_table_area), &table_paddr, GFP_KERNEL);
+ if (!viif_dev->table_vaddr) {
+ dev_err(dev, "dma_alloc_wc failed\n");
+ return -ENOMEM;
+ }
+ viif_dev->table_paddr = (struct viif_table_area *)table_paddr;
+
+ /* power control */
+ pm_runtime_enable(dev);
+
+ /* build media_dev */
+ viif_dev->media_dev.hw_revision = 0;
+ strscpy(viif_dev->media_dev.model, MEDIA_MODEL, sizeof(viif_dev->media_dev.model));
+ viif_dev->media_dev.dev = dev;
+ strscpy(viif_dev->media_dev.bus_info, MEDIA_BUS_INFO, sizeof(viif_dev->media_dev.bus_info));
+ media_device_init(&viif_dev->media_dev);
+
+ /* build v4l2_dev */
+ viif_dev->v4l2_dev.mdev = &viif_dev->media_dev;
+ ret = v4l2_device_register(dev, &viif_dev->v4l2_dev);
+ if (ret)
+ goto error_dma_free;
+
+ ret = media_device_register(&viif_dev->media_dev);
+ if (ret) {
+ dev_err(dev, "Failed to register media device: %d\n", ret);
+ goto error_v4l2_unregister;
+ }
+
+ ret = visconti_viif_isp_register(viif_dev);
+ if (ret) {
+ dev_err(dev, "failed to register isp sub node: %d\n", ret);
+ goto error_media_unregister;
+ }
+ ret = visconti_viif_capture_register(viif_dev);
+ if (ret) {
+ dev_err(dev, "failed to register capture node: %d\n", ret);
+ goto error_media_unregister;
+ }
+
+ /* check device type */
+ of_id = of_match_device(visconti_viif_of_table, dev);
+
+ num_sd = visconti_viif_parse_dt(viif_dev);
+ if (ret < 0) {
+ ret = num_sd;
+ goto error_media_unregister;
+ }
+
+ viif_dev->notifier.v4l2_dev = &viif_dev->v4l2_dev;
+ v4l2_async_nf_init(&viif_dev->notifier);
+ for (i = 0; i < num_sd; i++)
+ __v4l2_async_nf_add_subdev(&viif_dev->notifier, viif_dev->asds[i]);
+ viif_dev->notifier.ops = &viif_notify_ops;
+ ret = v4l2_async_nf_register(&viif_dev->v4l2_dev, &viif_dev->notifier);
+ if (ret)
+ goto error_media_unregister;
+
+ return 0;
+
+error_media_unregister:
+ media_device_unregister(&viif_dev->media_dev);
+error_v4l2_unregister:
+ v4l2_device_unregister(&viif_dev->v4l2_dev);
+error_dma_free:
+ pm_runtime_disable(dev);
+ dma_free_wc(&pdev->dev, sizeof(struct viif_table_area), viif_dev->table_vaddr,
+ (dma_addr_t)viif_dev->table_paddr);
+ return ret;
+}
+
+static int visconti_viif_remove(struct platform_device *pdev)
+{
+ struct viif_device *viif_dev = platform_get_drvdata(pdev);
+
+ visconti_viif_isp_unregister(viif_dev);
+ visconti_viif_capture_unregister(viif_dev);
+ v4l2_async_nf_unregister(&viif_dev->notifier);
+ media_device_unregister(&viif_dev->media_dev);
+ v4l2_device_unregister(&viif_dev->v4l2_dev);
+ pm_runtime_disable(&pdev->dev);
+ dma_free_wc(&pdev->dev, sizeof(struct viif_table_area), viif_dev->table_vaddr,
+ (dma_addr_t)viif_dev->table_paddr);
+
+ return 0;
+}
+
+static int visconti_viif_runtime_suspend(struct device *dev)
+{
+ /* This callback is kicked when the last device-file is closed */
+ return 0;
+}
+
+static int visconti_viif_runtime_resume(struct device *dev)
+{
+ /* This callback is kicked when the first device-file is opened */
+ struct viif_device *viif_dev = dev_get_drvdata(dev);
+
+ viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_DISABLE;
+
+ mutex_lock(&viif_dev->pow_lock);
+
+ /* VSYNC mask setting of MAIN unit */
+ hwd_viif_main_vsync_set_irq_mask(
+ viif_dev->hwd_res, INT_M_SYNC_MASK_VSYNC_INT | INT_M_SYNC_MASK_LINES_DELAY_INT1 |
+ INT_M_SYNC_MASK_SW_DELAY_INT0 |
+ INT_M_SYNC_MASK_SW_DELAY_INT2);
+
+ /* STATUS error mask setting of MAIN unit */
+ hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res, INT_M_MASK_DELAY_INT_ERROR);
+
+ /* VSYNC mask settings of SUB unit */
+ hwd_viif_sub_vsync_set_irq_mask(viif_dev->hwd_res, INT_S_SYNC_MASK_VSYNC_INT |
+ INT_S_SYNC_MASK_SW_DELAY_INT0 |
+ INT_S_SYNC_MASK_SW_DELAY_INT1);
+
+ /* STATUS error mask setting(unmask) of SUB unit */
+ hwd_viif_sub_status_err_set_irq_mask(viif_dev->hwd_res,
+ INT_S_MASK_RESERVED_SET | INT_S_MASK_DELAY_INT_ERROR);
+
+ mutex_unlock(&viif_dev->pow_lock);
+
+ return 0;
+}
+
+static const struct dev_pm_ops visconti_viif_pm_ops = { SET_RUNTIME_PM_OPS(
+ visconti_viif_runtime_suspend, visconti_viif_runtime_resume, NULL) };
+
+static struct platform_driver visconti_viif_driver = {
+ .probe = visconti_viif_probe,
+ .remove = visconti_viif_remove,
+ .driver = {
+ .name = "visconti_viif",
+ .of_match_table = visconti_viif_of_table,
+ .pm = &visconti_viif_pm_ops,
+ },
+};
+
+module_platform_driver(visconti_viif_driver);
+
+MODULE_AUTHOR("Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>");
+MODULE_DESCRIPTION("Toshiba Visconti Video Input driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/media/platform/visconti/viif.h b/drivers/media/platform/visconti/viif.h
new file mode 100644
index 00000000000..cd121ae3200
--- /dev/null
+++ b/drivers/media/platform/visconti/viif.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#ifndef VIIF_H
+#define VIIF_H
+
+#include <linux/visconti_viif.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mediabus.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "hwd_viif.h"
+
+#define VIIF_ISP_REGBUF_0 0
+#define VIIF_L2ISP_POST_0 0
+#define VIIF_L2ISP_POST_1 1
+
+#define VIIF_CAPTURE_PAD_SINK 0
+#define VIIF_ISP_PAD_SINK 0
+#define VIIF_ISP_PAD_SRC_PATH0 1
+#define VIIF_ISP_PAD_SRC_PATH1 2
+#define VIIF_ISP_PAD_SRC_PATH2 3
+#define VIIF_ISP_PAD_NUM 4
+
+#define CAPTURE_PATH_MAIN_POST0 0
+#define CAPTURE_PATH_MAIN_POST1 1
+#define CAPTURE_PATH_SUB 2
+
+#define VIIF_DPC_TABLE_BYTES 8192
+#define VIIF_LSC_TABLE_BYTES 1536
+#define VIIF_UNDIST_TABLE_BYTES 8192
+#define VIIF_L2_GAMMA_TABLE_BYTES 512
+
+#define VIIF_HW_AVAILABLE_IRQS 4
+
+struct viif_fmt {
+ u32 fourcc;
+ u8 bpp[3];
+ u8 num_planes;
+ u32 colorspace;
+ u32 pitch_align;
+};
+
+struct viif_subdev {
+ struct v4l2_subdev *v4l2_sd;
+ struct v4l2_async_subdev asd;
+
+ /* per-subdevice mbus configuration options */
+ unsigned int mbus_flags;
+ unsigned int mbus_code;
+ unsigned int num_lane;
+};
+
+struct viif_table_area {
+ /* viif_l1_dpc_config */
+ u32 dpc_table_h[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
+ u32 dpc_table_m[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
+ u32 dpc_table_l[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
+ /* viif_l1_lsc_config */
+ u16 lsc_table_gr[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
+ u16 lsc_table_r[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
+ u16 lsc_table_b[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
+ u16 lsc_table_gb[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
+ /* viif_l2_undist_config */
+ u32 undist_write_g[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
+ u32 undist_read_b[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
+ u32 undist_read_g[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
+ u32 undist_read_r[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
+ /* viif_l2_gamma_config */
+ u16 l2_gamma_table[2][6][VIIF_L2_GAMMA_TABLE_BYTES / sizeof(u16)];
+};
+
+/* capture device node information */
+struct cap_dev {
+ u32 pathid; /* 0 ... MAIN POST0, 1 ... MAIN POST1, 2 ... SUB */
+ struct video_device vdev;
+ struct media_pad capture_pad;
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct mutex vlock; /* serialize ioctl to vb2_queue and video_device */
+
+ /* vb2 queue, capture buffer list and active buffer pointer */
+ struct vb2_queue vb2_vq;
+ struct list_head buf_queue;
+ struct vb2_v4l2_buffer *active;
+ struct vb2_v4l2_buffer *dma_active;
+ int buf_cnt;
+ unsigned int sequence;
+
+ /* currently configured field and pixel format */
+ enum v4l2_field field;
+ struct v4l2_pix_format_mplane v4l2_pix;
+ unsigned int out_format;
+ struct hwd_viif_img_area img_area;
+ struct hwd_viif_out_process out_process;
+
+ struct viif_device *viif_dev;
+};
+
+struct isp_subdev {
+ struct v4l2_subdev sd;
+ struct media_pad pads[VIIF_ISP_PAD_NUM];
+ struct v4l2_subdev_pad_config pad_cfg[VIIF_ISP_PAD_NUM];
+ struct mutex ops_lock; /* serialize V4L2 query */
+ struct viif_device *viif_dev;
+ struct v4l2_ctrl_handler ctrl_handler;
+};
+
+struct hwd_viif_res;
+
+struct viif_device {
+ struct device *dev;
+ struct v4l2_device v4l2_dev;
+ struct media_device media_dev;
+ struct media_pipeline pipe;
+ u32 masked_gamma_path;
+ struct hwd_viif_func *func;
+
+ struct viif_subdev *subdevs;
+ struct v4l2_async_subdev **asds;
+ /* async subdev notification helpers */
+ struct v4l2_async_notifier notifier;
+
+ /* the subdevice currently in use */
+ struct viif_subdev *sd;
+ unsigned int sd_index;
+ unsigned int num_sd;
+
+ /* sub device node information */
+ struct cap_dev cap_dev0;
+ struct cap_dev cap_dev1;
+ struct cap_dev cap_dev2;
+ struct isp_subdev isp_subdev;
+
+ /* lock - serialize calls to low-level operations (hwd_xxxx) */
+ /* also, this serialize access to capture buffer queue and active buffer */
+ spinlock_t lock;
+
+ /* pow_lock - serialize power control*/
+ struct mutex pow_lock;
+
+ struct {
+ u32 clock_id;
+ u32 csi2_clock_id;
+ u32 csi2_reset_id;
+ } clk_compat;
+
+ /* hwd_res - context of low level implementation */
+ struct hwd_viif_res *hwd_res;
+
+ void __iomem *capture_reg;
+ void __iomem *csi2host_reg;
+ unsigned int irq[VIIF_HW_AVAILABLE_IRQS];
+
+ /* Un-cache table area */
+ struct viif_table_area *table_vaddr;
+ struct viif_table_area *table_paddr;
+
+ /* Rawpack mode */
+ u32 rawpack_mode;
+
+ /* Error flag checked at delayed vsync handler */
+ u32 status_err;
+
+ /* Error flag checked at compound control GET_REPORTED_ERRORS */
+ u32 reported_err_main;
+ u32 reported_err_sub;
+ u32 reported_err_csi2rx;
+};
+
+/* viif.c */
+void visconti_viif_hw_on(struct viif_device *viif_dev);
+void visconti_viif_hw_off(struct viif_device *viif_dev);
+
+/* viif_capture.c */
+int visconti_viif_capture_register(struct viif_device *viif_dev);
+void visconti_viif_capture_unregister(struct viif_device *viif_dev);
+int visconti_viif_capture_register_ctrl_handlers(struct viif_device *viif_dev);
+void visconti_viif_capture_switch_buffer(struct cap_dev *cap_dev, u32 status_err,
+ u32 l2_transfer_status, u64 timestamp);
+
+/* viif_isp.c */
+int visconti_viif_isp_register(struct viif_device *viif_dev);
+void visconti_viif_isp_unregister(struct viif_device *viif_dev);
+int visconti_viif_isp_main_set_unit(struct viif_device *viif_dev);
+int visconti_viif_isp_sub_set_unit(struct viif_device *viif_dev);
+void visconti_viif_isp_set_compose_rect(struct viif_device *viif_dev,
+ struct viif_l2_roi_config *roi);
+
+/* viif_controls.c */
+int visconti_viif_isp_init_controls(struct viif_device *viif_dev);
+
+#endif /* VIIF_H */
diff --git a/drivers/media/platform/visconti/viif_capture.c b/drivers/media/platform/visconti/viif_capture.c
new file mode 100644
index 00000000000..fa18aec4470
--- /dev/null
+++ b/drivers/media/platform/visconti/viif_capture.c
@@ -0,0 +1,1201 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-subdev.h>
+
+#include "viif.h"
+
+#define VIIF_CROP_MAX_X_ISP (8062U)
+#define VIIF_CROP_MAX_Y_ISP (3966U)
+#define VIIF_CROP_MIN_W (128U)
+#define VIIF_CROP_MAX_W_ISP (8190U)
+#define VIIF_CROP_MIN_H (128U)
+#define VIIF_CROP_MAX_H_ISP (4094U)
+
+struct viif_buffer {
+ struct vb2_v4l2_buffer vb;
+ struct list_head queue;
+};
+
+static inline struct viif_buffer *vb2_to_viif(struct vb2_v4l2_buffer *vbuf)
+{
+ return container_of(vbuf, struct viif_buffer, vb);
+}
+
+static inline struct cap_dev *video_drvdata_to_capdev(struct file *file)
+{
+ return (struct cap_dev *)video_drvdata(file);
+}
+
+static inline struct cap_dev *vb2queue_to_capdev(struct vb2_queue *vq)
+{
+ return (struct cap_dev *)vb2_get_drv_priv(vq);
+}
+
+/* ----- ISRs and VB2 Operations ----- */
+static int viif_set_img(struct cap_dev *cap_dev, struct vb2_buffer *vb)
+{
+ struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct hwd_viif_img next_out_img;
+ dma_addr_t phys_addr;
+ int i, ret = 0;
+
+ next_out_img.width = pix->width;
+ next_out_img.height = pix->height;
+ next_out_img.format = cap_dev->out_format;
+
+ for (i = 0; i < pix->num_planes; i++) {
+ next_out_img.pixelmap[i].pitch = pix->plane_fmt[i].bytesperline;
+ phys_addr = vb2_dma_contig_plane_dma_addr(vb, i);
+ next_out_img.pixelmap[i].pmap_paddr = phys_addr;
+ }
+
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l2_set_img_transmission(viif_dev->hwd_res, VIIF_L2ISP_POST_0,
+ HWD_VIIF_ENABLE, &cap_dev->img_area,
+ &cap_dev->out_process, &next_out_img);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ if (ret)
+ dev_err(viif_dev->dev, "set img error. %d\n", ret);
+ } else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1) {
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l2_set_img_transmission(viif_dev->hwd_res, VIIF_L2ISP_POST_1,
+ HWD_VIIF_ENABLE, &cap_dev->img_area,
+ &cap_dev->out_process, &next_out_img);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ if (ret)
+ dev_err(viif_dev->dev, "set img error. %d\n", ret);
+ } else if (cap_dev->pathid == CAPTURE_PATH_SUB) {
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_sub_set_img_transmission(viif_dev->hwd_res, &next_out_img);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ if (ret)
+ dev_err(viif_dev->dev, "set img error. %d\n", ret);
+ }
+
+ return ret;
+}
+
+/*
+ * viif_capture_switch_buffer() is called from interrupt service routine
+ * triggered by VSync with some fixed delay.
+ * The function may switch DMA target buffer by calling viif_set_img().
+ * The VIIF DMA HW captures the destination address at next VSync
+ * and completes transfer at one more after.
+ * Therefore, filled buffer is available at the one after next ISR.
+ *
+ * To avoid DMA HW getting stucked, we always need to set valid destination address.
+ * If a prepared buffer is not available, we reuse the buffer currently being transferred to.
+ *
+ * The cap_dev structure has two pointers and a queue to handle video buffers;
+ + Description of each item at the entry of this function:
+ * * buf_queue: holds prepared buffers, set by vb2_queue()
+ * * active: pointing at address captured (and to be filled) by DMA HW
+ * * dma_active: pointing at buffer filled by DMA HW
+ *
+ * Rules to update items:
+ * * when buf_queue is not empty, "active" buffer goes "dma_active"
+ * * when buf_queue is empty:
+ * * "active" buffer stays the same (DMA HW fills the same buffer for coming two frames)
+ * * "dma_active" gets NULL (filled buffer will be reused; should not go "DONE" at next ISR)
+ *
+ * Simulation:
+ * | buf_queue | active | dma_active | note |
+ * | X | NULL | NULL | |
+ * <QBUF BUF0>
+ * | X | BUF0 | NULL | BUF0 stays |
+ * | X | BUF0 | NULL | BUF0 stays |
+ * <QBUF BUF1>
+ * <QBUF BUF2>
+ * | BUF2 BUF1 | BUF0 | NULL | |
+ * | BUF2 | BUF1 | BUF0 | BUF0 goes DONE |
+ * | X | BUF2 | BUF1 | BUF1 goes DONE, BUF2 stays |
+ * | X | BUF2 | NULL | BUF2 stays |
+ */
+void visconti_viif_capture_switch_buffer(struct cap_dev *cap_dev, u32 status_err,
+ u32 l2_transfer_status, u64 timestamp)
+{
+ if (cap_dev->dma_active) {
+ /* DMA has completed and another framebuffer instance is set */
+ struct vb2_v4l2_buffer *vbuf = cap_dev->dma_active;
+ enum vb2_buffer_state state;
+
+ cap_dev->buf_cnt--;
+ vbuf->vb2_buf.timestamp = timestamp;
+ vbuf->sequence = cap_dev->sequence++;
+ vbuf->field = cap_dev->field;
+ if (status_err || l2_transfer_status)
+ state = VB2_BUF_STATE_ERROR;
+ else
+ state = VB2_BUF_STATE_DONE;
+
+ vb2_buffer_done(&vbuf->vb2_buf, state);
+ }
+
+ /* QUEUE pop to register an instance as next DMA target; if empty, reuse current instance */
+ if (!list_empty(&cap_dev->buf_queue)) {
+ struct viif_buffer *buf =
+ list_entry(cap_dev->buf_queue.next, struct viif_buffer, queue);
+ list_del_init(&buf->queue);
+ viif_set_img(cap_dev, &buf->vb.vb2_buf);
+ cap_dev->active = &buf->vb;
+ cap_dev->dma_active = cap_dev->active;
+ } else {
+ cap_dev->dma_active = NULL;
+ }
+}
+
+/* --- Capture buffer control --- */
+static int viif_vb2_setup(struct vb2_queue *vq, unsigned int *count, unsigned int *num_planes,
+ unsigned int sizes[], struct device *alloc_devs[])
+{
+ struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
+ struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
+ unsigned int i;
+
+ /* num_planes is set: just check plane sizes. */
+ if (*num_planes) {
+ for (i = 0; i < pix->num_planes; i++)
+ if (sizes[i] < pix->plane_fmt[i].sizeimage)
+ return -EINVAL;
+
+ return 0;
+ }
+
+ /* num_planes not set: called from REQBUFS, just set plane sizes. */
+ *num_planes = pix->num_planes;
+ for (i = 0; i < pix->num_planes; i++)
+ sizes[i] = pix->plane_fmt[i].sizeimage;
+
+ cap_dev->buf_cnt = 0;
+
+ return 0;
+}
+
+static void viif_vb2_queue(struct vb2_buffer *vb)
+{
+ struct cap_dev *cap_dev = vb2queue_to_capdev(vb->vb2_queue);
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct viif_buffer *buf = vb2_to_viif(vbuf);
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+
+ if (!cap_dev->active) {
+ cap_dev->active = vbuf;
+ viif_set_img(cap_dev, vb);
+ } else {
+ list_add_tail(&buf->queue, &cap_dev->buf_queue);
+ }
+ cap_dev->buf_cnt++;
+
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+}
+
+static int viif_vb2_prepare(struct vb2_buffer *vb)
+{
+ struct cap_dev *cap_dev = vb2queue_to_capdev(vb->vb2_queue);
+ struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ unsigned int i;
+
+ for (i = 0; i < pix->num_planes; i++) {
+ if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
+ dev_err(viif_dev->dev, "Plane size too small (%lu < %u)\n",
+ vb2_plane_size(vb, i), pix->plane_fmt[i].sizeimage);
+ return -EINVAL;
+ }
+
+ vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
+ }
+ return 0;
+}
+
+static int viif_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+
+ /* note that pipe is shared among paths; see pipe.streaming_count member variable */
+ ret = video_device_pipeline_start(&cap_dev->vdev, &viif_dev->pipe);
+ if (ret)
+ dev_err(viif_dev->dev, "start pipeline failed %d\n", ret);
+
+ /* Currently, only path0 (MAIN POST0) initializes ISP and Camera */
+ /* Possibly, initialization can be done when pipe.streaming_count==0 */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ /* CSI2RX start */
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, video, s_stream, true);
+ if (ret) {
+ dev_err(viif_dev->dev, "Start isp subdevice stream failed. %d\n", ret);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+ return ret;
+ }
+ }
+
+ /* buffer control */
+ cap_dev->sequence = 0;
+
+ /* finish critical section: some sensor driver (including imx219) calls schedule() */
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ /* Camera (CSI2 source) start streaming */
+ /* Currently, only path0 (MAIN POST0) initializes ISP and Camera */
+ /* Possibly, initialization can be done when pipe.streaming_count==0 */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, s_stream, true);
+ if (ret) {
+ dev_err(viif_dev->dev, "Start subdev stream failed. %d\n", ret);
+ (void)v4l2_subdev_call(&viif_dev->isp_subdev.sd, video, s_stream, false);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void viif_stop_streaming(struct vb2_queue *vq)
+{
+ struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ struct viif_buffer *buf;
+ unsigned long irqflags;
+ int ret;
+
+ /* Currently, only path0 (MAIN POST0) stops ISP and Camera */
+ /* Possibly, teardown can be done when pipe.streaming_count==0 */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, s_stream, false);
+ if (ret)
+ dev_err(viif_dev->dev, "Stop subdev stream failed. %d\n", ret);
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+
+ /* Currently, only path0 (MAIN POST0) stops ISP and Camera */
+ /* Possibly, teardown can be done when pipe.streaming_count==0 */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, video, s_stream, false);
+ if (ret)
+ dev_err(viif_dev->dev, "Stop isp subdevice stream failed %d\n", ret);
+ }
+
+ /* buffer control */
+ if (cap_dev->active) {
+ vb2_buffer_done(&cap_dev->active->vb2_buf, VB2_BUF_STATE_ERROR);
+ cap_dev->buf_cnt--;
+ cap_dev->active = NULL;
+ }
+ if (cap_dev->dma_active) {
+ vb2_buffer_done(&cap_dev->dma_active->vb2_buf, VB2_BUF_STATE_ERROR);
+ cap_dev->buf_cnt--;
+ cap_dev->dma_active = NULL;
+ }
+
+ /* Release all queued buffers. */
+ list_for_each_entry(buf, &cap_dev->buf_queue, queue) {
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+ cap_dev->buf_cnt--;
+ }
+ INIT_LIST_HEAD(&cap_dev->buf_queue);
+ if (cap_dev->buf_cnt)
+ dev_err(viif_dev->dev, "Buffer count error %d\n", cap_dev->buf_cnt);
+
+ video_device_pipeline_stop(&cap_dev->vdev);
+
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+}
+
+static const struct vb2_ops viif_vb2_ops = {
+ .queue_setup = viif_vb2_setup,
+ .buf_queue = viif_vb2_queue,
+ .buf_prepare = viif_vb2_prepare,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .start_streaming = viif_start_streaming,
+ .stop_streaming = viif_stop_streaming,
+};
+
+/* --- VIIF hardware settings --- */
+/* L2ISP output csc setting for YUV to RGB(ITU-R BT.709) */
+static const struct hwd_viif_csc_param viif_csc_yuv2rgb = {
+ .r_cr_in_offset = 0x18000,
+ .g_y_in_offset = 0x1f000,
+ .b_cb_in_offset = 0x18000,
+ .coef = {
+ [0] = 0x1000,
+ [1] = 0xfd12,
+ [2] = 0xf8ad,
+ [3] = 0x1000,
+ [4] = 0x1d07,
+ [5] = 0x0000,
+ [6] = 0x1000,
+ [7] = 0x0000,
+ [8] = 0x18a2,
+ },
+ .r_cr_out_offset = 0x1000,
+ .g_y_out_offset = 0x1000,
+ .b_cb_out_offset = 0x1000,
+};
+
+/* L2ISP output csc setting for RGB to YUV(ITU-R BT.709) */
+static const struct hwd_viif_csc_param viif_csc_rgb2yuv = {
+ .r_cr_in_offset = 0x1f000,
+ .g_y_in_offset = 0x1f000,
+ .b_cb_in_offset = 0x1f000,
+ .coef = {
+ [0] = 0x0b71,
+ [1] = 0x0128,
+ [2] = 0x0367,
+ [3] = 0xf9b1,
+ [4] = 0x082f,
+ [5] = 0xfe20,
+ [6] = 0xf891,
+ [7] = 0xff40,
+ [8] = 0x082f,
+ },
+ .r_cr_out_offset = 0x8000,
+ .g_y_out_offset = 0x1000,
+ .b_cb_out_offset = 0x8000,
+};
+
+static int viif_l2_set_format(struct cap_dev *cap_dev)
+{
+ struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ const struct hwd_viif_csc_param *csc_param = NULL;
+ struct v4l2_subdev_selection sel = {
+ .target = V4L2_SEL_TGT_CROP,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ struct v4l2_subdev_format fmt = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ bool inp_is_rgb = false;
+ bool out_is_rgb = false;
+ u32 postid;
+ int ret;
+
+ /* check path id */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ sel.pad = VIIF_ISP_PAD_SRC_PATH0;
+ fmt.pad = VIIF_ISP_PAD_SRC_PATH0;
+ postid = VIIF_L2ISP_POST_0;
+ } else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1) {
+ sel.pad = VIIF_ISP_PAD_SRC_PATH1;
+ fmt.pad = VIIF_ISP_PAD_SRC_PATH1;
+ postid = VIIF_L2ISP_POST_1;
+ } else {
+ return -EINVAL;
+ }
+
+ cap_dev->out_process.half_scale = HWD_VIIF_DISABLE;
+ cap_dev->out_process.select_color = HWD_VIIF_COLOR_YUV_RGB;
+ cap_dev->out_process.alpha = 0;
+
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection, NULL, &sel);
+ if (ret) {
+ cap_dev->img_area.x = 0;
+ cap_dev->img_area.y = 0;
+ cap_dev->img_area.w = pix->width;
+ cap_dev->img_area.h = pix->height;
+ } else {
+ cap_dev->img_area.x = sel.r.left;
+ cap_dev->img_area.y = sel.r.top;
+ cap_dev->img_area.w = sel.r.width;
+ cap_dev->img_area.h = sel.r.height;
+ }
+
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_fmt, NULL, &fmt);
+ if (!ret)
+ inp_is_rgb = (fmt.format.code == MEDIA_BUS_FMT_RGB888_1X24);
+
+ switch (pix->pixelformat) {
+ case V4L2_PIX_FMT_RGB24:
+ cap_dev->out_format = HWD_VIIF_RGB888_PACKED;
+ out_is_rgb = true;
+ break;
+ case V4L2_PIX_FMT_ABGR32:
+ cap_dev->out_format = HWD_VIIF_ARGB8888_PACKED;
+ cap_dev->out_process.alpha = 0xff;
+ out_is_rgb = true;
+ break;
+ case V4L2_PIX_FMT_YUV422M:
+ cap_dev->out_format = HWD_VIIF_YCBCR422_8_PLANAR;
+ break;
+ case V4L2_PIX_FMT_YUV444M:
+ cap_dev->out_format = HWD_VIIF_RGB888_YCBCR444_8_PLANAR;
+ break;
+ case V4L2_PIX_FMT_Y16:
+ cap_dev->out_format = HWD_VIIF_ONE_COLOR_16;
+ cap_dev->out_process.select_color = HWD_VIIF_COLOR_Y_G;
+ break;
+ }
+
+ if (!inp_is_rgb && out_is_rgb)
+ csc_param = &viif_csc_yuv2rgb; /* YUV -> RGB */
+ else if (inp_is_rgb && !out_is_rgb)
+ csc_param = &viif_csc_rgb2yuv; /* RGB -> YUV */
+
+ return hwd_viif_l2_set_output_csc(viif_dev->hwd_res, postid, csc_param);
+}
+
+/* --- IOCTL Operations --- */
+static const struct viif_fmt viif_fmt_list[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_RGB24,
+ .bpp = { 24, 0, 0 },
+ .num_planes = 1,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .pitch_align = 384,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_ABGR32,
+ .bpp = { 32, 0, 0 },
+ .num_planes = 1,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .pitch_align = 512,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUV422M,
+ .bpp = { 8, 4, 4 },
+ .num_planes = 3,
+ .colorspace = V4L2_COLORSPACE_REC709,
+ .pitch_align = 128,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUV444M,
+ .bpp = { 8, 8, 8 },
+ .num_planes = 3,
+ .colorspace = V4L2_COLORSPACE_REC709,
+ .pitch_align = 128,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_Y16,
+ .bpp = { 16, 0, 0 },
+ .num_planes = 1,
+ .colorspace = V4L2_COLORSPACE_REC709,
+ .pitch_align = 128,
+ },
+};
+
+static const struct viif_fmt viif_rawfmt_list[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB10,
+ .bpp = { 16, 0, 0 },
+ .num_planes = 1,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .pitch_align = 256,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB12,
+ .bpp = { 16, 0, 0 },
+ .num_planes = 1,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .pitch_align = 256,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB14,
+ .bpp = { 16, 0, 0 },
+ .num_planes = 1,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .pitch_align = 256,
+ },
+};
+
+static const struct viif_fmt *get_viif_fmt_from_fourcc(unsigned int fourcc)
+{
+ const struct viif_fmt *fmt = &viif_fmt_list[0];
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(viif_fmt_list); i++, fmt++)
+ if (fmt->fourcc == fourcc)
+ return fmt;
+
+ return NULL;
+}
+
+static void viif_update_plane_sizes(struct v4l2_plane_pix_format *plane, unsigned int bpl,
+ unsigned int szimage)
+{
+ memset(plane, 0, sizeof(*plane));
+
+ plane->sizeimage = szimage;
+ plane->bytesperline = bpl;
+}
+
+static void viif_calc_plane_sizes(const struct viif_fmt *viif_fmt,
+ struct v4l2_pix_format_mplane *pix)
+{
+ unsigned int i, bpl, szimage;
+
+ for (i = 0; i < viif_fmt->num_planes; i++) {
+ bpl = pix->width * viif_fmt->bpp[i] / 8;
+ /* round up ptch */
+ bpl = (bpl + (viif_fmt->pitch_align - 1)) / viif_fmt->pitch_align;
+ bpl *= viif_fmt->pitch_align;
+ szimage = pix->height * bpl;
+ viif_update_plane_sizes(&pix->plane_fmt[i], bpl, szimage);
+ }
+ pix->num_planes = viif_fmt->num_planes;
+}
+
+static int viif_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+
+ strscpy(cap->card, "Toshiba VIIF", sizeof(cap->card));
+ strscpy(cap->driver, "viif", sizeof(cap->driver));
+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:toshiba-viif-%s",
+ dev_name(viif_dev->dev));
+ return 0;
+}
+
+static int viif_enum_rawfmt(struct cap_dev *cap_dev, struct v4l2_fmtdesc *f)
+{
+ if (f->index >= ARRAY_SIZE(viif_rawfmt_list))
+ return -EINVAL;
+
+ f->pixelformat = viif_rawfmt_list[f->index].fourcc;
+
+ return 0;
+}
+
+static int viif_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *f)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+ const struct viif_fmt *fmt;
+
+ if (cap_dev->pathid == CAPTURE_PATH_SUB)
+ return viif_enum_rawfmt(cap_dev, f);
+
+ if (f->index >= ARRAY_SIZE(viif_fmt_list))
+ return -EINVAL;
+
+ fmt = &viif_fmt_list[f->index];
+ f->pixelformat = fmt->fourcc;
+
+ return 0;
+}
+
+/* size of minimum/maximum output image */
+#define VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
+#define VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
+#define VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
+
+#define VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
+#define VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
+#define VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
+
+static int viif_try_fmt(struct cap_dev *cap_dev, struct v4l2_format *v4l2_fmt)
+{
+ struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct v4l2_subdev_format format = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ const struct viif_fmt *viif_fmt;
+ int ret;
+
+ /* check path id */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
+ format.pad = VIIF_ISP_PAD_SRC_PATH0;
+ else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
+ format.pad = VIIF_ISP_PAD_SRC_PATH1;
+ else
+ format.pad = VIIF_ISP_PAD_SRC_PATH2;
+
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_fmt, NULL, &format);
+ if (ret)
+ return -EINVAL;
+
+ /* fourcc check */
+ if (cap_dev->pathid == CAPTURE_PATH_SUB) {
+ switch (format.format.code) {
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ viif_fmt = &viif_rawfmt_list[0]; /*V4L2_PIX_FMT_SRGGB10*/
+ pix->pixelformat = viif_fmt->fourcc;
+ break;
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ viif_fmt = &viif_rawfmt_list[1]; /*V4L2_PIX_FMT_SRGGB12*/
+ pix->pixelformat = viif_fmt->fourcc;
+ break;
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ viif_fmt = &viif_rawfmt_list[2]; /*V4L2_PIX_FMT_SRGGB14*/
+ pix->pixelformat = viif_fmt->fourcc;
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else {
+ viif_fmt = get_viif_fmt_from_fourcc(pix->pixelformat);
+ if (!viif_fmt)
+ return -EINVAL;
+ }
+
+ /* min/max width, height check */
+ if (pix->width < VIIF_MIN_OUTPUT_IMG_WIDTH)
+ pix->width = VIIF_MIN_OUTPUT_IMG_WIDTH;
+
+ if (pix->width > VIIF_MAX_OUTPUT_IMG_WIDTH_ISP)
+ pix->width = VIIF_MAX_OUTPUT_IMG_WIDTH_ISP;
+
+ if (pix->height < VIIF_MIN_OUTPUT_IMG_HEIGHT)
+ pix->height = VIIF_MIN_OUTPUT_IMG_HEIGHT;
+
+ if (pix->height > VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP)
+ pix->height = VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP;
+
+ /* consistency with isp::pad::src::fmt */
+ if (pix->width != format.format.width)
+ return -EINVAL;
+ if (pix->height != format.format.height)
+ return -EINVAL;
+
+ /* update derived parameters, such as bpp */
+ viif_calc_plane_sizes(viif_fmt, pix);
+
+ return 0;
+}
+
+static int viif_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+
+ return viif_try_fmt(cap_dev, f);
+}
+
+static int viif_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ int ret = 0;
+
+ if (vb2_is_streaming(&cap_dev->vb2_vq))
+ return -EBUSY;
+
+ if (f->type != cap_dev->vb2_vq.type)
+ return -EINVAL;
+
+ ret = viif_try_fmt(cap_dev, f);
+ if (ret)
+ return ret;
+
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
+ /*
+ * A call to main_set_unit() is currently at ioctl(VIDIOC_S_FMT) context.
+ * This call can be moved to viif_isp_s_stream(),
+ * if you don't want to check the given format is compatible to HW.
+ */
+ ret = visconti_viif_isp_main_set_unit(viif_dev);
+ if (ret)
+ return ret;
+ }
+
+ cap_dev->v4l2_pix = f->fmt.pix_mp;
+ cap_dev->field = V4L2_FIELD_NONE;
+
+ if (cap_dev->pathid == CAPTURE_PATH_SUB) {
+ cap_dev->out_format = HWD_VIIF_ONE_COLOR_16;
+ ret = visconti_viif_isp_sub_set_unit(viif_dev);
+ } else {
+ ret = viif_l2_set_format(cap_dev);
+ }
+
+ return ret;
+}
+
+static int viif_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+
+ f->fmt.pix_mp = cap_dev->v4l2_pix;
+
+ return 0;
+}
+
+static int viif_enum_input(struct file *file, void *priv, struct v4l2_input *inp)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd;
+ struct v4l2_subdev *v4l2_sd;
+ int ret;
+
+ if (inp->index >= viif_dev->num_sd)
+ return -EINVAL;
+
+ viif_sd = &viif_dev->subdevs[inp->index];
+ v4l2_sd = viif_sd->v4l2_sd;
+
+ ret = v4l2_subdev_call(v4l2_sd, video, g_input_status, &inp->status);
+ if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
+ return ret;
+ inp->type = V4L2_INPUT_TYPE_CAMERA;
+ inp->std = 0;
+ if (v4l2_subdev_has_op(v4l2_sd, pad, dv_timings_cap))
+ inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
+ else
+ inp->capabilities = V4L2_IN_CAP_STD;
+ snprintf(inp->name, sizeof(inp->name), "Camera%u: %s", inp->index, viif_sd->v4l2_sd->name);
+
+ return 0;
+}
+
+static int viif_g_input(struct file *file, void *priv, unsigned int *i)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+
+ *i = viif_dev->sd_index;
+
+ return 0;
+}
+
+static int viif_s_input(struct file *file, void *priv, unsigned int i)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+
+ if (i >= viif_dev->num_sd)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int viif_g_selection(struct file *file, void *priv, struct v4l2_selection *s)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct v4l2_subdev_selection sel = {
+ .target = V4L2_SEL_TGT_CROP,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ int ret;
+
+ /* check path id */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
+ sel.pad = VIIF_ISP_PAD_SRC_PATH0;
+ else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
+ sel.pad = VIIF_ISP_PAD_SRC_PATH1;
+ else
+ return -EINVAL;
+
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection, NULL, &sel);
+ s->r = sel.r;
+
+ return ret;
+}
+
+static int viif_s_selection(struct file *file, void *priv, struct v4l2_selection *s)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct v4l2_subdev_selection sel = {
+ .target = V4L2_SEL_TGT_CROP,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .r = s->r,
+ };
+ int ret;
+
+ /* check path id */
+ if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
+ sel.pad = VIIF_ISP_PAD_SRC_PATH0;
+ else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
+ sel.pad = VIIF_ISP_PAD_SRC_PATH1;
+ else
+ return -EINVAL;
+
+ if (s->r.left > VIIF_CROP_MAX_X_ISP || s->r.top > VIIF_CROP_MAX_Y_ISP ||
+ s->r.width < VIIF_CROP_MIN_W || s->r.width > VIIF_CROP_MAX_W_ISP ||
+ s->r.height < VIIF_CROP_MIN_H || s->r.height > VIIF_CROP_MAX_H_ISP) {
+ return -EINVAL;
+ }
+
+ ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, set_selection, NULL, &sel);
+ s->r = sel.r;
+
+ return ret;
+}
+
+static int viif_dv_timings_cap(struct file *file, void *priv_fh, struct v4l2_dv_timings_cap *cap)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, pad, dv_timings_cap, cap);
+}
+
+static int viif_enum_dv_timings(struct file *file, void *priv_fh,
+ struct v4l2_enum_dv_timings *timings)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, pad, enum_dv_timings, timings);
+}
+
+static int viif_g_dv_timings(struct file *file, void *priv_fh, struct v4l2_dv_timings *timings)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, video, g_dv_timings, timings);
+}
+
+static int viif_s_dv_timings(struct file *file, void *priv_fh, struct v4l2_dv_timings *timings)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, video, s_dv_timings, timings);
+}
+
+static int viif_query_dv_timings(struct file *file, void *priv_fh, struct v4l2_dv_timings *timings)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, video, query_dv_timings, timings);
+}
+
+static int viif_g_edid(struct file *file, void *fh, struct v4l2_edid *edid)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_edid, edid);
+}
+
+static int viif_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+
+ return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid, edid);
+}
+
+static int viif_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+
+ return v4l2_g_parm_cap(video_devdata(file), viif_dev->sd->v4l2_sd, a);
+}
+
+static int viif_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+
+ return v4l2_s_parm_cap(video_devdata(file), viif_dev->sd->v4l2_sd, a);
+}
+
+static int viif_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ struct v4l2_subdev *v4l2_sd = viif_sd->v4l2_sd;
+ struct v4l2_subdev_frame_size_enum fse = {
+ .code = viif_sd->mbus_code,
+ .index = fsize->index,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ int ret;
+
+ ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size, NULL, &fse);
+ if (ret)
+ return ret;
+
+ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+ fsize->discrete.width = fse.max_width;
+ fsize->discrete.height = fse.max_height;
+
+ return 0;
+}
+
+static int viif_enum_frameintervals(struct file *file, void *fh, struct v4l2_frmivalenum *fival)
+{
+ struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ struct v4l2_subdev *v4l2_sd = viif_sd->v4l2_sd;
+ struct v4l2_subdev_frame_interval_enum fie = {
+ .code = viif_sd->mbus_code,
+ .index = fival->index,
+ .width = fival->width,
+ .height = fival->height,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ int ret;
+
+ ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL, &fie);
+ if (ret)
+ return ret;
+
+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+ fival->discrete = fie.interval;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops viif_ioctl_ops = {
+ .vidioc_querycap = viif_querycap,
+
+ .vidioc_enum_fmt_vid_cap = viif_enum_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap_mplane = viif_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap_mplane = viif_s_fmt_vid_cap,
+ .vidioc_g_fmt_vid_cap_mplane = viif_g_fmt_vid_cap,
+
+ .vidioc_enum_input = viif_enum_input,
+ .vidioc_g_input = viif_g_input,
+ .vidioc_s_input = viif_s_input,
+
+ .vidioc_g_selection = viif_g_selection,
+ .vidioc_s_selection = viif_s_selection,
+
+ .vidioc_dv_timings_cap = viif_dv_timings_cap,
+ .vidioc_enum_dv_timings = viif_enum_dv_timings,
+ .vidioc_g_dv_timings = viif_g_dv_timings,
+ .vidioc_s_dv_timings = viif_s_dv_timings,
+ .vidioc_query_dv_timings = viif_query_dv_timings,
+
+ .vidioc_g_edid = viif_g_edid,
+ .vidioc_s_edid = viif_s_edid,
+
+ .vidioc_g_parm = viif_g_parm,
+ .vidioc_s_parm = viif_s_parm,
+
+ .vidioc_enum_framesizes = viif_enum_framesizes,
+ .vidioc_enum_frameintervals = viif_enum_frameintervals,
+
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+
+ .vidioc_log_status = v4l2_ctrl_log_status,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+/* --- File Operations --- */
+static int viif_capture_open(struct file *file)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ int ret;
+
+ ret = v4l2_fh_open(file);
+ if (ret)
+ return ret;
+
+ return pm_runtime_resume_and_get(viif_dev->dev);
+}
+
+static int viif_capture_release(struct file *file)
+{
+ struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+
+ vb2_fop_release(file);
+ pm_runtime_put(viif_dev->dev);
+
+ return 0;
+}
+
+static const struct v4l2_file_operations viif_fops = {
+ .owner = THIS_MODULE,
+ .open = viif_capture_open,
+ .release = viif_capture_release,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = vb2_fop_mmap,
+ .poll = vb2_fop_poll,
+};
+
+/* ----- media control callbacks ----- */
+static int viif_capture_link_validate(struct media_link *link)
+{
+ /* link validation at start-stream */
+ return 0;
+}
+
+static const struct media_entity_operations viif_media_ops = {
+ .link_validate = viif_capture_link_validate,
+};
+
+/* ----- attach ctrl callbacck handler ----- */
+int visconti_viif_capture_register_ctrl_handlers(struct viif_device *viif_dev)
+{
+ int ret;
+
+ /* MAIN POST0: merge controls of ISP and CAPTURE0 */
+ ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev0.ctrl_handler,
+ viif_dev->sd->v4l2_sd->ctrl_handler, NULL, true);
+ if (ret) {
+ dev_err(viif_dev->dev, "Failed to add sensor ctrl_handler");
+ return ret;
+ }
+ ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev0.ctrl_handler,
+ &viif_dev->isp_subdev.ctrl_handler, NULL, true);
+ if (ret) {
+ dev_err(viif_dev->dev, "Failed to add isp subdev ctrl_handler");
+ return ret;
+ }
+
+ /* MAIN POST1: merge controls of ISP and CAPTURE0 */
+ ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev1.ctrl_handler,
+ viif_dev->sd->v4l2_sd->ctrl_handler, NULL, true);
+ if (ret) {
+ dev_err(viif_dev->dev, "Failed to add sensor ctrl_handler");
+ return ret;
+ }
+ ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev1.ctrl_handler,
+ &viif_dev->isp_subdev.ctrl_handler, NULL, true);
+ if (ret) {
+ dev_err(viif_dev->dev, "Failed to add isp subdev ctrl_handler");
+ return ret;
+ }
+
+ /* SUB: no control is exported */
+
+ return 0;
+}
+
+/* ----- register/remove capture device node ----- */
+static int visconti_viif_capture_register_node(struct cap_dev *cap_dev)
+{
+ struct viif_device *viif_dev = cap_dev->viif_dev;
+ struct v4l2_device *v4l2_dev = &viif_dev->v4l2_dev;
+ struct video_device *vdev = &cap_dev->vdev;
+ struct vb2_queue *q = &cap_dev->vb2_vq;
+ static const char *const node_name[] = {
+ "viif_capture_post0",
+ "viif_capture_post1",
+ "viif_capture_sub",
+ };
+ int ret;
+
+ INIT_LIST_HEAD(&cap_dev->buf_queue);
+
+ mutex_init(&cap_dev->vlock);
+
+ /* Initialize vb2 queue. */
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ q->io_modes = VB2_DMABUF;
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->ops = &viif_vb2_ops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->drv_priv = cap_dev;
+ q->buf_struct_size = sizeof(struct viif_buffer);
+ q->min_buffers_needed = 2;
+ q->lock = &cap_dev->vlock;
+ q->dev = viif_dev->v4l2_dev.dev;
+
+ ret = vb2_queue_init(q);
+ if (ret)
+ return ret;
+
+ /* Register the video device. */
+ strscpy(vdev->name, node_name[cap_dev->pathid], sizeof(vdev->name));
+ vdev->v4l2_dev = v4l2_dev;
+ vdev->lock = &cap_dev->vlock;
+ vdev->queue = &cap_dev->vb2_vq;
+ vdev->ctrl_handler = NULL;
+ vdev->fops = &viif_fops;
+ vdev->ioctl_ops = &viif_ioctl_ops;
+ vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;
+ vdev->device_caps |= V4L2_CAP_IO_MC;
+ vdev->entity.ops = &viif_media_ops;
+ vdev->release = video_device_release_empty;
+ video_set_drvdata(vdev, cap_dev);
+ vdev->vfl_dir = VFL_DIR_RX;
+ cap_dev->capture_pad.flags = MEDIA_PAD_FL_SINK;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret < 0) {
+ dev_err(v4l2_dev->dev, "video_register_device failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = media_entity_pads_init(&vdev->entity, 1, &cap_dev->capture_pad);
+ if (ret) {
+ video_unregister_device(vdev);
+ return ret;
+ }
+
+ ret = v4l2_ctrl_handler_init(&cap_dev->ctrl_handler, 30);
+ if (ret)
+ return -ENOMEM;
+
+ cap_dev->vdev.ctrl_handler = &cap_dev->ctrl_handler;
+
+ return 0;
+}
+
+int visconti_viif_capture_register(struct viif_device *viif_dev)
+{
+ int ret;
+
+ /* register MAIN POST0 (primary RGB output)*/
+ viif_dev->cap_dev0.pathid = CAPTURE_PATH_MAIN_POST0;
+ viif_dev->cap_dev0.viif_dev = viif_dev;
+ ret = visconti_viif_capture_register_node(&viif_dev->cap_dev0);
+ if (ret)
+ return ret;
+
+ /* register MAIN POST1 (additional RGB output)*/
+ viif_dev->cap_dev1.pathid = CAPTURE_PATH_MAIN_POST1;
+ viif_dev->cap_dev1.viif_dev = viif_dev;
+ ret = visconti_viif_capture_register_node(&viif_dev->cap_dev1);
+ if (ret)
+ return ret;
+
+ /* register SUB (RAW output) */
+ viif_dev->cap_dev2.pathid = CAPTURE_PATH_SUB;
+ viif_dev->cap_dev2.viif_dev = viif_dev;
+ ret = visconti_viif_capture_register_node(&viif_dev->cap_dev2);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void visconti_viif_capture_unregister_node(struct cap_dev *cap_dev)
+{
+ media_entity_cleanup(&cap_dev->vdev.entity);
+ v4l2_ctrl_handler_free(&cap_dev->ctrl_handler);
+ vb2_video_unregister_device(&cap_dev->vdev);
+ mutex_destroy(&cap_dev->vlock);
+}
+
+void visconti_viif_capture_unregister(struct viif_device *viif_dev)
+{
+ visconti_viif_capture_unregister_node(&viif_dev->cap_dev0);
+ visconti_viif_capture_unregister_node(&viif_dev->cap_dev1);
+ visconti_viif_capture_unregister_node(&viif_dev->cap_dev2);
+}
diff --git a/drivers/media/platform/visconti/viif_isp.c b/drivers/media/platform/visconti/viif_isp.c
new file mode 100644
index 00000000000..9314e6e8661
--- /dev/null
+++ b/drivers/media/platform/visconti/viif_isp.c
@@ -0,0 +1,846 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/delay.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-subdev.h>
+
+#include "viif.h"
+
+/* ----- supported MBUS formats ----- */
+struct visconti_mbus_format {
+ unsigned int code;
+ unsigned int bpp;
+ int rgb_out;
+} static visconti_mbus_formats[] = {
+ { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .rgb_out = 1 },
+ { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_UYVY10_1X20, .bpp = 20, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, .rgb_out = 1 },
+ { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, .rgb_out = 0 },
+ { .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, .rgb_out = 0 },
+};
+
+static int viif_get_mbus_rgb_out(unsigned int mbus_code)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
+ if (visconti_mbus_formats[i].code == mbus_code)
+ return visconti_mbus_formats[i].rgb_out;
+
+ /* YUV intermediate code by default */
+ return 0;
+}
+
+static unsigned int viif_get_mbus_bpp(unsigned int mbus_code)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
+ if (visconti_mbus_formats[i].code == mbus_code)
+ return visconti_mbus_formats[i].bpp;
+
+ /* default bpp value */
+ return 24;
+}
+
+static bool viif_is_valid_mbus_code(unsigned int mbus_code)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
+ if (visconti_mbus_formats[i].code == mbus_code)
+ return true;
+ return false;
+}
+
+/* ----- handling main processing path ----- */
+static int viif_get_dv_timings(struct viif_device *viif_dev, struct v4l2_dv_timings *timings)
+{
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ struct v4l2_subdev_pad_config pad_cfg;
+ struct v4l2_subdev_state pad_state = {
+ .pads = &pad_cfg,
+ };
+ struct v4l2_subdev_format format = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = 0,
+ };
+ struct v4l2_ctrl *ctrl;
+ int ret;
+
+ /* some video I/F support dv_timings query */
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, g_dv_timings, timings);
+ if (ret == 0)
+ return 0;
+
+ /* others: call some discrete APIs */
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, &pad_state, &format);
+ if (ret != 0)
+ return ret;
+
+ timings->bt.width = format.format.width;
+ timings->bt.height = format.format.height;
+
+ ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler, V4L2_CID_HBLANK);
+ if (!ctrl) {
+ dev_err(viif_dev->dev, "subdev: V4L2_CID_VBLANK error.\n");
+ return -EINVAL;
+ }
+ timings->bt.hsync = v4l2_ctrl_g_ctrl(ctrl);
+
+ ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler, V4L2_CID_VBLANK);
+ if (!ctrl) {
+ dev_err(viif_dev->dev, "subdev: V4L2_CID_VBLANK error.\n");
+ return -EINVAL;
+ }
+ timings->bt.vsync = v4l2_ctrl_g_ctrl(ctrl);
+
+ ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler, V4L2_CID_PIXEL_RATE);
+ if (!ctrl) {
+ dev_err(viif_dev->dev, "subdev: V4L2_CID_PIXEL_RATE error.\n");
+ return -EINVAL;
+ }
+ timings->bt.pixelclock = v4l2_ctrl_g_ctrl_int64(ctrl);
+
+ return 0;
+}
+
+int visconti_viif_isp_main_set_unit(struct viif_device *viif_dev)
+{
+ unsigned int dt_image, color_type, rawpack, yuv_conv;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ struct hwd_viif_input_img in_img_main;
+ struct viif_l2_undist undist = { 0 };
+ struct v4l2_dv_timings timings;
+ struct v4l2_subdev_format fmt = {
+ .pad = 0,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ int mag_hactive = 1;
+ int ret = 0;
+
+ ret = viif_get_dv_timings(viif_dev, &timings);
+ if (ret) {
+ dev_err(viif_dev->dev, "could not get timing information of subdev");
+ return -EINVAL;
+ }
+
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, NULL, &fmt);
+ if (ret) {
+ dev_err(viif_dev->dev, "could not get pad information of subdev");
+ return -EINVAL;
+ }
+
+ switch (fmt.format.code) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ dt_image = VISCONTI_CSI2_DT_RGB888;
+ break;
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ dt_image = VISCONTI_CSI2_DT_YUV4228B;
+ break;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+ dt_image = VISCONTI_CSI2_DT_YUV42210B;
+ break;
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ dt_image = VISCONTI_CSI2_DT_RGB565;
+ break;
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ dt_image = VISCONTI_CSI2_DT_RAW8;
+ break;
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ dt_image = VISCONTI_CSI2_DT_RAW10;
+ break;
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ dt_image = VISCONTI_CSI2_DT_RAW12;
+ break;
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ dt_image = VISCONTI_CSI2_DT_RAW14;
+ break;
+ default:
+ dt_image = VISCONTI_CSI2_DT_RGB888;
+ break;
+ }
+
+ color_type = dt_image;
+
+ if (color_type == VISCONTI_CSI2_DT_RAW8 || color_type == VISCONTI_CSI2_DT_RAW10 ||
+ color_type == VISCONTI_CSI2_DT_RAW12) {
+ rawpack = viif_dev->rawpack_mode;
+ if (rawpack != HWD_VIIF_RAWPACK_DISABLE)
+ mag_hactive = 2;
+ } else {
+ rawpack = HWD_VIIF_RAWPACK_DISABLE;
+ }
+
+ if (color_type == VISCONTI_CSI2_DT_YUV4228B || color_type == VISCONTI_CSI2_DT_YUV42210B)
+ yuv_conv = HWD_VIIF_YUV_CONV_INTERPOLATION;
+ else
+ yuv_conv = HWD_VIIF_YUV_CONV_REPEAT;
+
+ in_img_main.hactive_size = timings.bt.width;
+ in_img_main.vactive_size = timings.bt.height;
+ in_img_main.htotal_size = timings.bt.width * mag_hactive + timings.bt.hsync;
+ in_img_main.vtotal_size = timings.bt.height + timings.bt.vsync;
+ in_img_main.pixel_clock = timings.bt.pixelclock / 1000;
+ in_img_main.vbp_size = timings.bt.vsync - 5;
+
+ in_img_main.interpolation_mode = HWD_VIIF_L1_INPUT_INTERPOLATION_LINE;
+ in_img_main.input_num = 1;
+ in_img_main.hobc_width = 0;
+ in_img_main.hobc_margin = 0;
+
+ /* configuration of MAIN unit */
+ ret = hwd_viif_main_set_unit(viif_dev->hwd_res, dt_image, &in_img_main, color_type, rawpack,
+ yuv_conv);
+ if (ret) {
+ dev_err(viif_dev->dev, "main_set_unit error. %d\n", ret);
+ return ret;
+ }
+
+ /* Enable regbuf */
+ hwd_viif_isp_set_regbuf_auto_transmission(viif_dev->hwd_res);
+
+ /* L2 UNDIST Enable through mode as default */
+ undist.through_mode = HWD_VIIF_ENABLE;
+ undist.sensor_crop_ofs_h = 1 - in_img_main.hactive_size;
+ undist.sensor_crop_ofs_v = 1 - in_img_main.vactive_size;
+ undist.grid_node_num_h = 16;
+ undist.grid_node_num_v = 16;
+ ret = hwd_viif_l2_set_undist(viif_dev->hwd_res, &undist);
+ if (ret)
+ dev_err(viif_dev->dev, "l2_set_undist error. %d\n", ret);
+ return ret;
+}
+
+static unsigned int dt_image_from_mbus_code(unsigned int mbus_code)
+{
+ switch (mbus_code) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ return VISCONTI_CSI2_DT_RGB888;
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ return VISCONTI_CSI2_DT_YUV4228B;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+ return VISCONTI_CSI2_DT_YUV42210B;
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ return VISCONTI_CSI2_DT_RGB565;
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ return VISCONTI_CSI2_DT_RAW8;
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ return VISCONTI_CSI2_DT_RAW10;
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ return VISCONTI_CSI2_DT_RAW12;
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ return VISCONTI_CSI2_DT_RAW14;
+ default:
+ return VISCONTI_CSI2_DT_RGB888;
+ }
+}
+
+int visconti_viif_isp_sub_set_unit(struct viif_device *viif_dev)
+{
+ struct hwd_viif_input_img in_img_sub;
+ struct v4l2_dv_timings timings;
+ struct v4l2_subdev_format fmt = {
+ .pad = 0,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ unsigned int dt_image;
+ int ret;
+
+ ret = viif_get_dv_timings(viif_dev, &timings);
+ if (ret)
+ return -EINVAL;
+
+ ret = v4l2_subdev_call(viif_dev->sd->v4l2_sd, pad, get_fmt, NULL, &fmt);
+ if (ret) {
+ dev_err(viif_dev->dev, "could not get pad information of subdev");
+ return -EINVAL;
+ }
+
+ dt_image = dt_image_from_mbus_code(fmt.format.code);
+
+ in_img_sub.hactive_size = 0;
+ in_img_sub.vactive_size = timings.bt.height;
+ in_img_sub.htotal_size = timings.bt.width + timings.bt.hsync;
+ in_img_sub.vtotal_size = timings.bt.height + timings.bt.vsync;
+ in_img_sub.pixel_clock = timings.bt.pixelclock / 1000;
+ in_img_sub.vbp_size = timings.bt.vsync - 5;
+ in_img_sub.interpolation_mode = HWD_VIIF_L1_INPUT_INTERPOLATION_LINE;
+ in_img_sub.input_num = 1;
+ in_img_sub.hobc_width = 0;
+ in_img_sub.hobc_margin = 0;
+
+ ret = hwd_viif_sub_set_unit(viif_dev->hwd_res, dt_image, &in_img_sub);
+ if (ret)
+ dev_err(viif_dev->dev, "sub_set_unit error. %d\n", ret);
+
+ return ret;
+};
+
+/* ----- handling CSI2RX hardware ----- */
+static int viif_csi2rx_initialize(struct viif_device *viif_dev)
+{
+ struct hwd_viif_csi2rx_line_err_target err_target = { 0 };
+ struct hwd_viif_csi2rx_irq_mask csi2rx_mask;
+ struct viif_subdev *viif_sd = viif_dev->sd;
+ struct v4l2_mbus_config cfg = { 0 };
+ struct v4l2_subdev_format fmt = {
+ .pad = 0,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ struct v4l2_dv_timings timings;
+ int num_lane, dphy_rate;
+ int ret;
+
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_mbus_config, 0, &cfg);
+ if (ret) {
+ dev_dbg(viif_dev->dev, "subdev: g_mbus_config error. %d\n", ret);
+ num_lane = viif_sd->num_lane;
+ } else {
+ if (cfg.type != V4L2_MBUS_CSI2_DPHY)
+ return -EINVAL;
+ num_lane = cfg.bus.mipi_csi2.num_data_lanes;
+ }
+
+ ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, 0, &fmt);
+ if (ret)
+ return -EINVAL;
+
+ ret = viif_get_dv_timings(viif_dev, &timings);
+ if (ret)
+ return -EINVAL;
+
+ dphy_rate = (timings.bt.pixelclock / 1000) * viif_get_mbus_bpp(fmt.format.code) / num_lane;
+ dphy_rate = dphy_rate / 1000;
+
+ /* check error for CH0: all supported DTs */
+ err_target.dt[0] = VISCONTI_CSI2_DT_RGB565;
+ err_target.dt[1] = VISCONTI_CSI2_DT_YUV4228B;
+ err_target.dt[2] = VISCONTI_CSI2_DT_YUV42210B;
+ err_target.dt[3] = VISCONTI_CSI2_DT_RGB888;
+ err_target.dt[4] = VISCONTI_CSI2_DT_RAW8;
+ err_target.dt[5] = VISCONTI_CSI2_DT_RAW10;
+ err_target.dt[6] = VISCONTI_CSI2_DT_RAW12;
+ err_target.dt[7] = VISCONTI_CSI2_DT_RAW14;
+
+ /* Define errors to be masked */
+ csi2rx_mask.mask[0] = 0x0000000F; /*check all for PHY_FATAL*/
+ csi2rx_mask.mask[1] = 0x0001000F; /*check all for PKT_FATAL*/
+ csi2rx_mask.mask[2] = 0x000F0F0F; /*check all for FRAME_FATAL*/
+ csi2rx_mask.mask[3] = 0x000F000F; /*check all for PHY*/
+ csi2rx_mask.mask[4] = 0x000F000F; /*check all for PKT*/
+ csi2rx_mask.mask[5] = 0x00FF00FF; /*check all for LINE*/
+
+ return hwd_viif_csi2rx_initialize(viif_dev->hwd_res, num_lane, HWD_VIIF_CSI2_DPHY_L0L1L2L3,
+ dphy_rate, HWD_VIIF_ENABLE, &err_target, &csi2rx_mask);
+}
+
+static int viif_csi2rx_start(struct viif_device *viif_dev)
+{
+ struct hwd_viif_csi2rx_packet packet = { 0 };
+ u32 vc_main = 0;
+ u32 vc_sub = 0;
+
+ viif_dev->masked_gamma_path = 0U;
+
+ return hwd_viif_csi2rx_start(viif_dev->hwd_res, vc_main, vc_sub, &packet);
+}
+
+static int viif_csi2rx_stop(struct viif_device *viif_dev)
+{
+ s32 ret;
+
+ ret = hwd_viif_csi2rx_stop(viif_dev->hwd_res);
+ if (ret)
+ dev_err(viif_dev->dev, "csi2rx_stop error. %d\n", ret);
+
+ hwd_viif_csi2rx_uninitialize(viif_dev->hwd_res);
+
+ return ret;
+}
+
+/* ----- subdevice video operations ----- */
+static int visconti_viif_isp_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ int ret;
+
+ if (enable) {
+ ret = viif_csi2rx_initialize(viif_dev);
+ if (ret)
+ return ret;
+ return viif_csi2rx_start(viif_dev);
+ } else {
+ return viif_csi2rx_stop(viif_dev);
+ }
+}
+
+/* ----- subdevice pad operations ----- */
+static int visconti_viif_isp_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->pad == 0) {
+ /* sink */
+ if (code->index > ARRAY_SIZE(visconti_mbus_formats) - 1)
+ return -EINVAL;
+ code->code = visconti_mbus_formats[code->index].code;
+ return 0;
+ }
+
+ /* source */
+ if (code->index > 0)
+ return -EINVAL;
+ code->code = MEDIA_BUS_FMT_YUV8_1X24;
+ return 0;
+}
+
+static struct v4l2_mbus_framefmt *visconti_viif_isp_get_pad_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ unsigned int pad, u32 which)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ struct v4l2_subdev_state state = {
+ .pads = viif_dev->isp_subdev.pad_cfg,
+ };
+
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state, pad);
+ else
+ return v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, &state, pad);
+}
+
+static struct v4l2_rect *visconti_viif_isp_get_pad_crop(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ unsigned int pad, u32 which)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ struct v4l2_subdev_state state = {
+ .pads = viif_dev->isp_subdev.pad_cfg,
+ };
+
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, sd_state, pad);
+ else
+ return v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, &state, pad);
+}
+
+static struct v4l2_rect *visconti_viif_isp_get_pad_compose(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ unsigned int pad, u32 which)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ struct v4l2_subdev_state state = {
+ .pads = viif_dev->isp_subdev.pad_cfg,
+ };
+
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, sd_state, pad);
+ else
+ return v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, &state, pad);
+}
+
+static int visconti_viif_isp_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+
+ mutex_lock(&viif_dev->isp_subdev.ops_lock);
+ fmt->format = *visconti_viif_isp_get_pad_fmt(sd, sd_state, fmt->pad, fmt->which);
+ mutex_unlock(&viif_dev->isp_subdev.ops_lock);
+
+ return 0;
+}
+
+static void visconti_viif_isp_set_sink_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *format, u32 which)
+{
+ struct v4l2_mbus_framefmt *sink_fmt, *src0_fmt, *src1_fmt, *src2_fmt;
+
+ sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK, which);
+ src0_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SRC_PATH0, which);
+ src1_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SRC_PATH1, which);
+ src2_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SRC_PATH2, which);
+
+ /* update mbus code only if it's available */
+ if (viif_is_valid_mbus_code(format->code))
+ sink_fmt->code = format->code;
+
+ /* sink::mbus_code is derived from src::mbus_code */
+ if (viif_get_mbus_rgb_out(sink_fmt->code)) {
+ src0_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
+ src1_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
+ } else {
+ src0_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
+ src1_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
+ }
+
+ /* SRC2 (RAW output) follows SINK format */
+ src2_fmt->code = format->code;
+ src2_fmt->width = format->width;
+ src2_fmt->height = format->height;
+
+ /* size check */
+ sink_fmt->width = format->width;
+ sink_fmt->height = format->height;
+
+ *format = *sink_fmt;
+}
+
+static void visconti_viif_isp_set_src_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *format, unsigned int pad,
+ u32 which)
+{
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ struct v4l2_rect *src_crop;
+
+ sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, pad, which);
+ src_crop = visconti_viif_isp_get_pad_crop(sd, sd_state, pad, which);
+
+ /* sink::mbus_code is derived from src::mbus_code */
+ if (viif_get_mbus_rgb_out(sink_fmt->code))
+ src_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
+ else
+ src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
+
+ /*size check*/
+ src_fmt->width = format->width;
+ src_fmt->height = format->height;
+
+ /*update crop*/
+ src_crop->width = format->width;
+ src_crop->height = format->height;
+
+ *format = *src_fmt;
+}
+
+static void visconti_viif_isp_set_src_fmt_rawpath(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *format,
+ unsigned int pad, u32 which)
+{
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+
+ sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, pad, which);
+
+ /* RAWPATH SRC pad has just the same configuration as SINK pad */
+ src_fmt->code = sink_fmt->code;
+ src_fmt->width = sink_fmt->width;
+ src_fmt->height = sink_fmt->height;
+
+ *format = *src_fmt;
+}
+
+static int visconti_viif_isp_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+
+ mutex_lock(&viif_dev->isp_subdev.ops_lock);
+
+ if (fmt->pad == VIIF_ISP_PAD_SINK)
+ visconti_viif_isp_set_sink_fmt(sd, sd_state, &fmt->format, fmt->which);
+ else if (fmt->pad == VIIF_ISP_PAD_SRC_PATH2)
+ visconti_viif_isp_set_src_fmt_rawpath(sd, sd_state, &fmt->format, fmt->pad,
+ fmt->which);
+ else
+ visconti_viif_isp_set_src_fmt(sd, sd_state, &fmt->format, fmt->pad, fmt->which);
+
+ mutex_unlock(&viif_dev->isp_subdev.ops_lock);
+
+ return 0;
+}
+
+#define VISCONTI_VIIF_ISP_DEFAULT_WIDTH 1920
+#define VISCONTI_VIIF_ISP_DEFAULT_HEIGHT 1080
+#define VISCONTI_VIIF_MAX_COMPOSED_WIDTH 8190
+#define VISCONTI_VIIF_MAX_COMPOSED_HEIGHT 4094
+
+static int visconti_viif_isp_init_config(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ struct v4l2_rect *src_crop, *sink_compose;
+
+ sink_fmt =
+ v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state, VIIF_ISP_PAD_SINK);
+ sink_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ sink_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+ sink_fmt->field = V4L2_FIELD_NONE;
+ sink_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
+
+ sink_compose =
+ v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, sd_state, VIIF_ISP_PAD_SINK);
+ sink_compose->top = 0;
+ sink_compose->left = 0;
+ sink_compose->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ sink_compose->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+
+ src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state,
+ VIIF_ISP_PAD_SRC_PATH0);
+ src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+ src_fmt->field = V4L2_FIELD_NONE;
+ src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
+
+ src_crop = v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, sd_state,
+ VIIF_ISP_PAD_SRC_PATH0);
+ src_crop->top = 0;
+ src_crop->left = 0;
+ src_crop->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ src_crop->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+
+ src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state,
+ VIIF_ISP_PAD_SRC_PATH1);
+ src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+ src_fmt->field = V4L2_FIELD_NONE;
+ src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
+
+ src_crop = v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, sd_state,
+ VIIF_ISP_PAD_SRC_PATH1);
+ src_crop->top = 0;
+ src_crop->left = 0;
+ src_crop->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ src_crop->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+
+ src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state,
+ VIIF_ISP_PAD_SRC_PATH2);
+ src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
+ src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
+ src_fmt->field = V4L2_FIELD_NONE;
+ src_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
+
+ return 0;
+}
+
+static int visconti_viif_isp_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ struct v4l2_mbus_framefmt *sink_fmt;
+ int ret = -EINVAL;
+
+ mutex_lock(&viif_dev->isp_subdev.ops_lock);
+ if (sel->pad == VIIF_ISP_PAD_SINK) {
+ /* SINK PAD */
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK,
+ sel->which);
+ sel->r.top = 0;
+ sel->r.left = 0;
+ sel->r.width = sink_fmt->width;
+ sel->r.height = sink_fmt->height;
+ ret = 0;
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ sel->r = *visconti_viif_isp_get_pad_compose(sd, sd_state, VIIF_ISP_PAD_SINK,
+ sel->which);
+ ret = 0;
+ break;
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ /* fixed value */
+ sel->r.top = 0;
+ sel->r.left = 0;
+ sel->r.width = VISCONTI_VIIF_MAX_COMPOSED_WIDTH;
+ sel->r.height = VISCONTI_VIIF_MAX_COMPOSED_HEIGHT;
+ ret = 0;
+ break;
+ }
+ } else if ((sel->pad == VIIF_ISP_PAD_SRC_PATH0) || (sel->pad == VIIF_ISP_PAD_SRC_PATH1)) {
+ /* SRC PAD */
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ sel->r =
+ *visconti_viif_isp_get_pad_crop(sd, sd_state, sel->pad, sel->which);
+ ret = 0;
+ break;
+ }
+ }
+ mutex_unlock(&viif_dev->isp_subdev.ops_lock);
+
+ return ret;
+}
+
+static int visconti_viif_isp_set_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
+ struct v4l2_mbus_framefmt *src_fmt;
+ struct v4l2_rect *rect, *rect_compose;
+ int ret = -EINVAL;
+
+ mutex_lock(&viif_dev->isp_subdev.ops_lock);
+ /* only source::selection::crop is writable */
+ if (sel->pad == VIIF_ISP_PAD_SRC_PATH0 || sel->pad == VIIF_ISP_PAD_SRC_PATH1) {
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP: {
+ /* check if new SRC::CROP is inside SINK::COMPOSE */
+ rect_compose = visconti_viif_isp_get_pad_compose(
+ sd, sd_state, VIIF_ISP_PAD_SINK, sel->which);
+ if (sel->r.top < rect_compose->top || sel->r.left < rect_compose->left ||
+ (sel->r.top + sel->r.height) >
+ (rect_compose->top + rect_compose->height) ||
+ (sel->r.left + sel->r.width) >
+ (rect_compose->left + rect_compose->width)) {
+ break;
+ }
+
+ rect = visconti_viif_isp_get_pad_crop(sd, sd_state, sel->pad, sel->which);
+ *rect = sel->r;
+
+ /* update SRC::FMT along with SRC::CROP */
+ src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, sel->pad, sel->which);
+ src_fmt->width = sel->r.width;
+ src_fmt->height = sel->r.height;
+ ret = 0;
+ break;
+ }
+ }
+ }
+ mutex_unlock(&viif_dev->isp_subdev.ops_lock);
+
+ return ret;
+}
+
+void visconti_viif_isp_set_compose_rect(struct viif_device *viif_dev,
+ struct viif_l2_roi_config *roi)
+{
+ struct v4l2_rect *rect;
+
+ rect = visconti_viif_isp_get_pad_compose(&viif_dev->isp_subdev.sd, NULL, VIIF_ISP_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ rect->top = 0;
+ rect->left = 0;
+ rect->width = roi->corrected_hsize[0];
+ rect->height = roi->corrected_vsize[0];
+}
+
+static const struct media_entity_operations visconti_viif_isp_media_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_pad_ops visconti_viif_isp_pad_ops = {
+ .enum_mbus_code = visconti_viif_isp_enum_mbus_code,
+ .get_selection = visconti_viif_isp_get_selection,
+ .set_selection = visconti_viif_isp_set_selection,
+ .init_cfg = visconti_viif_isp_init_config,
+ .get_fmt = visconti_viif_isp_get_fmt,
+ .set_fmt = visconti_viif_isp_set_fmt,
+ .link_validate = v4l2_subdev_link_validate_default,
+};
+
+static const struct v4l2_subdev_video_ops visconti_viif_isp_video_ops = {
+ .s_stream = visconti_viif_isp_s_stream,
+};
+
+static const struct v4l2_subdev_ops visconti_viif_isp_ops = {
+ .video = &visconti_viif_isp_video_ops,
+ .pad = &visconti_viif_isp_pad_ops,
+};
+
+/* ----- register/remove isp subdevice node ----- */
+int visconti_viif_isp_register(struct viif_device *viif_dev)
+{
+ struct v4l2_subdev_state state = {
+ .pads = viif_dev->isp_subdev.pad_cfg,
+ };
+ struct media_pad *pads = viif_dev->isp_subdev.pads;
+ struct v4l2_subdev *sd = &viif_dev->isp_subdev.sd;
+ int ret;
+
+ viif_dev->isp_subdev.viif_dev = viif_dev;
+
+ v4l2_subdev_init(sd, &visconti_viif_isp_ops);
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ sd->entity.ops = &visconti_viif_isp_media_ops;
+ sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
+ sd->owner = THIS_MODULE;
+ strscpy(sd->name, "visconti-viif:isp", sizeof(sd->name));
+
+ pads[0].flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
+ pads[1].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
+ pads[2].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
+ pads[3].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
+
+ mutex_init(&viif_dev->isp_subdev.ops_lock);
+
+ ret = media_entity_pads_init(&sd->entity, 4, pads);
+ if (ret) {
+ dev_err(viif_dev->dev, "Failed on media_entity_pads_init\n");
+ return ret;
+ }
+
+ ret = v4l2_device_register_subdev(&viif_dev->v4l2_dev, sd);
+ if (ret) {
+ dev_err(viif_dev->dev, "Failed to resize ISP subdev\n");
+ goto err_cleanup_media_entity;
+ }
+
+ visconti_viif_isp_init_config(sd, &state);
+
+ return 0;
+
+err_cleanup_media_entity:
+ media_entity_cleanup(&sd->entity);
+ return ret;
+}
+
+void visconti_viif_isp_unregister(struct viif_device *viif_dev)
+{
+ v4l2_device_unregister_subdev(&viif_dev->isp_subdev.sd);
+ media_entity_cleanup(&viif_dev->isp_subdev.sd.entity);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-11 2:24 ` [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace Yuji Ishikawa
@ 2023-01-17 11:47 ` Hans Verkuil
2023-01-18 1:04 ` Laurent Pinchart
2023-01-26 1:25 ` yuji2.ishikawa
0 siblings, 2 replies; 42+ messages in thread
From: Hans Verkuil @ 2023-01-17 11:47 UTC (permalink / raw)
To: Yuji Ishikawa, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
More comments below:
On 11/01/2023 03:24, Yuji Ishikawa wrote:
> Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> The interface device includes CSI2 Receiver,
> frame grabber, video DMAC and image signal processor.
> This patch provides the user interface layer.
>
> A driver instance provides three /dev/videoX device files;
> one for RGB image capture, another one for optional RGB capture
> with different parameters and the last one for RAW capture.
>
> Through the device files, the driver provides streaming (DMA-BUF) interface.
> A userland application should feed DMA-BUF instances for capture buffers.
>
> The driver is based on media controller framework.
> Its operations are roughly mapped to two subdrivers;
> one for ISP and CSI2 receiver (yields 1 instance),
> the other for capture (yields 3 instances for each capture mode).
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> ---
> Changelog v2:
> - Resend v1 because a patch exceeds size limit.
>
> Changelog v3:
> - Adapted to media control framework
> - Introduced ISP subdevice, capture device
> - Remove private IOCTLs and add vendor specific V4L2 controls
> - Change function name avoiding camelcase and uppercase letters
>
> Changelog v4:
> - Split patches because the v3 patch exceeds size limit
> - Stop using ID number to identify driver instance:
> - Use dynamically allocated structure to hold HW specific context,
> instead of static one.
> - Call HW layer functions with the context structure instead of ID number
> - Use pm_runtime to trigger initialization of HW
> along with open/close of device files.
>
> Changelog v5:
> - Fix coding style problems in viif.c
> ---
> drivers/media/platform/visconti/Makefile | 1 +
> drivers/media/platform/visconti/viif.c | 545 ++++++++
> drivers/media/platform/visconti/viif.h | 203 +++
> .../media/platform/visconti/viif_capture.c | 1201 +++++++++++++++++
> drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> 5 files changed, 2796 insertions(+)
> create mode 100644 drivers/media/platform/visconti/viif.c
> create mode 100644 drivers/media/platform/visconti/viif.h
> create mode 100644 drivers/media/platform/visconti/viif_capture.c
> create mode 100644 drivers/media/platform/visconti/viif_isp.c
>
> diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
> index e14b904df75..d7a23c1f4e8 100644
> --- a/drivers/media/platform/visconti/Makefile
> +++ b/drivers/media/platform/visconti/Makefile
> @@ -3,6 +3,7 @@
> # Makefile for the Visconti video input device driver
> #
>
> +visconti-viif-objs = viif.o viif_capture.o viif_isp.o
> visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
>
> obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> diff --git a/drivers/media/platform/visconti/viif.c b/drivers/media/platform/visconti/viif.c
> new file mode 100644
> index 00000000000..e29480dbb76
> --- /dev/null
> +++ b/drivers/media/platform/visconti/viif.c
> @@ -0,0 +1,545 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <media/v4l2-fwnode.h>
> +
> +#include "viif.h"
> +
> +static inline struct viif_device *v4l2_to_viif(struct v4l2_device *v4l2_dev)
> +{
> + return container_of(v4l2_dev, struct viif_device, v4l2_dev);
> +}
> +
> +static struct viif_subdev *to_viif_subdev(struct v4l2_async_subdev *asd)
> +{
> + return container_of(asd, struct viif_subdev, asd);
> +}
> +
> +/* VSYNC mask setting of MAIN unit */
> +#define INT_M_SYNC_MASK_VSYNC_INT BIT(0)
> +#define INT_M_SYNC_MASK_LINES_DELAY_INT1 BIT(1)
> +#define INT_M_SYNC_MASK_LINES_DELAY_INT2 BIT(2)
> +#define INT_M_SYNC_MASK_SW_DELAY_INT0 BIT(16)
> +#define INT_M_SYNC_MASK_SW_DELAY_INT1 BIT(17)
> +#define INT_M_SYNC_MASK_SW_DELAY_INT2 BIT(18)
> +
> +/* STATUS error mask setting of MAIN unit */
> +#define INT_M_MASK_L2ISP_SIZE_ERROR BIT(0)
> +#define INT_M_MASK_CRGBF_INTCRGERR_WRSTART BIT(1)
> +#define INT_M_MASK_CRGBF_INTCRGERR_RDSTART BIT(2)
> +#define INT_M_MASK_EMBED_ERROR BIT(3)
> +#define INT_M_MASK_USERDATA_ERROR BIT(4)
> +#define INT_M_MASK_L2ISP_POST0_TABLE_TIMEOUT BIT(8)
> +#define INT_M_MASK_L2ISP_POST1_TABLE_TIMEOUT BIT(9)
> +#define INT_M_MASK_L2ISP_GRID_TABLE_TIMEOUT BIT(11)
> +#define INT_M_MASK_L1ISP_SIZE_ERROR0 BIT(16)
> +#define INT_M_MASK_L1ISP_SIZE_ERROR1 BIT(17)
> +#define INT_M_MASK_L1ISP_SIZE_ERROR2 BIT(18)
> +#define INT_M_MASK_L1ISP_SIZE_ERROR3 BIT(19)
> +#define INT_M_MASK_L1ISP_SIZE_ERROR4 BIT(20)
> +#define INT_M_MASK_L1ISP_INT_ERR_CRGWRSTART BIT(21)
> +#define INT_M_MASK_L1ISP_INT_ERR_CRGRDSTART BIT(22)
> +#define INT_M_MASK_DELAY_INT_ERROR BIT(24)
> +
> +/* VSYNC mask settings of SUB unit */
> +#define INT_S_SYNC_MASK_VSYNC_INT BIT(0)
> +#define INT_S_SYNC_MASK_LINES_DELAY_INT1 BIT(1)
> +#define INT_S_SYNC_MASK_SW_DELAY_INT0 BIT(16)
> +#define INT_S_SYNC_MASK_SW_DELAY_INT1 BIT(17)
> +
> +/* STATUS error mask setting of SUB unit */
> +#define INT_S_MASK_SIZE_ERROR BIT(0)
> +#define INT_S_MASK_EMBED_ERROR BIT(1)
> +#define INT_S_MASK_USERDATA_ERROR BIT(2)
> +#define INT_S_MASK_DELAY_INT_ERROR BIT(24)
> +#define INT_S_MASK_RESERVED_SET (BIT(16) | BIT(28))
> +
> +static void viif_vsync_irq_handler_w_isp(struct viif_device *viif_dev)
> +{
> + u32 event_main, event_sub, status_err, l2_transfer_status;
> + u64 ts;
> +
> + ts = ktime_get_ns();
> + hwd_viif_vsync_irq_handler(viif_dev->hwd_res, &event_main, &event_sub);
> +
> + /* Delayed Vsync of MAIN unit */
> + if (event_main & INT_M_SYNC_MASK_LINES_DELAY_INT2) {
> + /* unmask timeout error of gamma table */
> + hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res,
> + INT_M_MASK_DELAY_INT_ERROR);
> + viif_dev->masked_gamma_path = 0;
> +
> + /* Get abort status of L2ISP */
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + hwd_viif_isp_get_info(viif_dev->hwd_res, NULL, &l2_transfer_status);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> +
> + status_err = viif_dev->status_err;
> + viif_dev->status_err = 0;
> +
> + visconti_viif_capture_switch_buffer(&viif_dev->cap_dev0, status_err,
> + l2_transfer_status, ts);
> + visconti_viif_capture_switch_buffer(&viif_dev->cap_dev1, status_err,
> + l2_transfer_status, ts);
> + }
> +
> + /* Delayed Vsync of SUB unit */
> + if (event_sub & INT_S_SYNC_MASK_LINES_DELAY_INT1)
> + visconti_viif_capture_switch_buffer(&viif_dev->cap_dev2, 0, 0, ts);
> +}
> +
> +#define MASK_M_GAMMATBL_TIMEOUT 0x0700U
> +
> +static void viif_status_err_irq_handler(struct viif_device *viif_dev)
> +{
> + u32 event_main, event_sub, val, mask;
> +
> + hwd_viif_status_err_irq_handler(viif_dev->hwd_res, &event_main, &event_sub);
> +
> + if (event_main) {
> + /* mask for gamma table time out error which will be unmasked in the next Vsync */
> + val = FIELD_GET(MASK_M_GAMMATBL_TIMEOUT, event_main);
> + if (val) {
> + viif_dev->masked_gamma_path |= val;
> + mask = INT_M_MASK_DELAY_INT_ERROR |
> + FIELD_PREP(MASK_M_GAMMATBL_TIMEOUT, viif_dev->masked_gamma_path);
> + hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res, mask);
> + }
> +
> + viif_dev->status_err = event_main;
> + }
> + viif_dev->reported_err_main |= event_main;
> + viif_dev->reported_err_sub |= event_sub;
> + dev_err(viif_dev->dev, "MAIN/SUB error 0x%x 0x%x.\n", event_main, event_sub);
> +}
> +
> +static void viif_csi2rx_err_irq_handler(struct viif_device *viif_dev)
> +{
> + u32 event;
> +
> + event = hwd_viif_csi2rx_err_irq_handler(viif_dev->hwd_res);
> + viif_dev->reported_err_csi2rx |= event;
> + dev_err(viif_dev->dev, "CSI2RX error 0x%x.\n", event);
> +}
> +
> +static irqreturn_t visconti_viif_irq(int irq, void *dev_id)
> +{
> + struct viif_device *viif_dev = dev_id;
> + int irq_type = irq - viif_dev->irq[0];
> +
> + spin_lock(&viif_dev->lock);
> +
> + switch (irq_type) {
> + case 0:
> + viif_vsync_irq_handler_w_isp(viif_dev);
> + break;
> + case 1:
> + viif_status_err_irq_handler(viif_dev);
> + break;
> + case 2:
> + viif_csi2rx_err_irq_handler(viif_dev);
> + break;
> + }
> +
> + spin_unlock(&viif_dev->lock);
> +
> + return IRQ_HANDLED;
> +}
> +
> +/* ----- Async Notifier Operations----- */
> +static int visconti_viif_notify_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *v4l2_sd, struct v4l2_async_subdev *asd)
> +{
> + struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
> + struct viif_device *viif_dev = v4l2_to_viif(v4l2_dev);
> + struct viif_subdev *viif_sd = to_viif_subdev(asd);
> +
> + viif_sd->v4l2_sd = v4l2_sd;
> + viif_dev->num_sd++;
> +
> + return 0;
> +}
> +
> +static void visconti_viif_create_links(struct viif_device *viif_dev)
> +{
> + unsigned int source_pad;
> + int ret;
> +
> + /* camera subdev pad0 -> isp suddev pad0 */
> + ret = media_entity_get_fwnode_pad(&viif_dev->sd->v4l2_sd->entity,
> + viif_dev->sd->v4l2_sd->fwnode, MEDIA_PAD_FL_SOURCE);
> + if (ret < 0) {
> + dev_err(viif_dev->dev, "failed to find source pad\n");
> + return;
> + }
> + source_pad = ret;
> +
> + ret = media_create_pad_link(&viif_dev->sd->v4l2_sd->entity, source_pad,
> + &viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SINK,
> + MEDIA_LNK_FL_ENABLED);
> + if (ret)
> + dev_err(viif_dev->dev, "failed create_pad_link (camera:src -> isp:sink)\n");
> +
> + ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SRC_PATH0,
> + &viif_dev->cap_dev0.vdev.entity, VIIF_CAPTURE_PAD_SINK,
> + MEDIA_LNK_FL_ENABLED);
> + if (ret)
> + dev_err(viif_dev->dev, "failed create_pad_link (isp:src -> capture0:sink)\n");
> +
> + ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SRC_PATH1,
> + &viif_dev->cap_dev1.vdev.entity, VIIF_CAPTURE_PAD_SINK,
> + MEDIA_LNK_FL_ENABLED);
> + if (ret)
> + dev_err(viif_dev->dev, "failed create_pad_link (isp:src -> capture1:sink)\n");
> +
> + ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity, VIIF_ISP_PAD_SRC_PATH2,
> + &viif_dev->cap_dev2.vdev.entity, VIIF_CAPTURE_PAD_SINK,
> + MEDIA_LNK_FL_ENABLED);
> + if (ret)
> + dev_err(viif_dev->dev, "failed create_pad_link (isp:src -> capture2:sink)\n");
> +}
> +
> +static void visconti_viif_notify_unbind(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev, struct v4l2_async_subdev *asd)
> +{
> + struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
> + struct viif_subdev *viif_sd = to_viif_subdev(asd);
> +
> + v4l2_dev->ctrl_handler = NULL;
> + viif_sd->v4l2_sd = NULL;
> +}
> +
> +static int visconti_viif_notify_complete(struct v4l2_async_notifier *notifier)
> +{
> + struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
> + struct viif_device *viif_dev = v4l2_to_viif(v4l2_dev);
> + int ret;
> +
> + ret = v4l2_device_register_subdev_nodes(v4l2_dev);
> + if (ret < 0) {
> + dev_err(v4l2_dev->dev, "Failed to register subdev nodes\n");
> + return ret;
> + }
> +
> + /* Make sure at least one sensor is primary and use it to initialize */
> + if (!viif_dev->sd) {
> + viif_dev->sd = &viif_dev->subdevs[0];
> + viif_dev->sd_index = 0;
> + }
> +
> + ret = visconti_viif_capture_register_ctrl_handlers(viif_dev);
> + if (ret)
> + return ret;
> +
> + visconti_viif_create_links(viif_dev);
> +
> + return 0;
> +}
> +
> +static const struct v4l2_async_notifier_operations viif_notify_ops = {
> + .bound = visconti_viif_notify_bound,
> + .unbind = visconti_viif_notify_unbind,
> + .complete = visconti_viif_notify_complete,
> +};
> +
> +/* ----- Probe and Remove ----- */
> +static int visconti_viif_init_async_subdevs(struct viif_device *viif_dev, unsigned int n_sd)
> +{
> + /* Reserve memory for 'n_sd' viif_subdev descriptors. */
> + viif_dev->subdevs =
> + devm_kcalloc(viif_dev->dev, n_sd, sizeof(*viif_dev->subdevs), GFP_KERNEL);
> + if (!viif_dev->subdevs)
> + return -ENOMEM;
> +
> + /* Reserve memory for 'n_sd' pointers to async_subdevices.
> + * viif_dev->asds members will point to &viif_dev.asd
> + */
> + viif_dev->asds = devm_kcalloc(viif_dev->dev, n_sd, sizeof(*viif_dev->asds), GFP_KERNEL);
> + if (!viif_dev->asds)
> + return -ENOMEM;
> +
> + viif_dev->sd = NULL;
> + viif_dev->sd_index = 0;
> + viif_dev->num_sd = 0;
> +
> + return 0;
> +}
> +
> +static int visconti_viif_parse_dt(struct viif_device *viif_dev)
> +{
> + struct device_node *of = viif_dev->dev->of_node;
> + struct v4l2_fwnode_endpoint fw_ep;
> + struct viif_subdev *viif_sd;
> + struct device_node *ep;
> + unsigned int i;
> + int num_ep;
> + int ret;
> +
> + memset(&fw_ep, 0, sizeof(struct v4l2_fwnode_endpoint));
> +
> + num_ep = of_graph_get_endpoint_count(of);
> + if (!num_ep)
> + return -ENODEV;
> +
> + ret = visconti_viif_init_async_subdevs(viif_dev, num_ep);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < num_ep; i++) {
> + ep = of_graph_get_endpoint_by_regs(of, 0, i);
> + if (!ep) {
> + dev_err(viif_dev->dev, "No subdevice connected on endpoint %u.\n", i);
> + ret = -ENODEV;
> + goto error_put_node;
> + }
> +
> + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep);
> + if (ret) {
> + dev_err(viif_dev->dev, "Unable to parse endpoint #%u.\n", i);
> + goto error_put_node;
> + }
> +
> + if (fw_ep.bus_type != V4L2_MBUS_CSI2_DPHY ||
> + fw_ep.bus.mipi_csi2.num_data_lanes == 0) {
> + dev_err(viif_dev->dev, "missing CSI-2 properties in endpoint\n");
> + ret = -EINVAL;
> + goto error_put_node;
> + }
> +
> + /* Setup the ceu subdevice and the async subdevice. */
> + viif_sd = &viif_dev->subdevs[i];
> + INIT_LIST_HEAD(&viif_sd->asd.list);
> +
> + viif_sd->mbus_flags = fw_ep.bus.mipi_csi2.flags;
> + viif_sd->num_lane = fw_ep.bus.mipi_csi2.num_data_lanes;
> + viif_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
> + viif_sd->asd.match.fwnode =
> + fwnode_graph_get_remote_port_parent(of_fwnode_handle(ep));
> +
> + viif_dev->asds[i] = &viif_sd->asd;
> + of_node_put(ep);
> + }
> +
> + return num_ep;
> +
> +error_put_node:
> + of_node_put(ep);
> + return ret;
> +}
> +
> +static const struct of_device_id visconti_viif_of_table[] = {
> + {
> + .compatible = "toshiba,visconti-viif",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, visconti_viif_of_table);
> +
> +#define NUM_IRQS 3
> +#define IRQ_ID_STR "viif"
> +#define MEDIA_MODEL "visconti_viif"
> +#define MEDIA_BUS_INFO "platform:visconti_viif"
> +
> +static int visconti_viif_probe(struct platform_device *pdev)
> +{
> + const struct of_device_id *of_id;
> + struct device *dev = &pdev->dev;
> + struct viif_device *viif_dev;
> + dma_addr_t table_paddr;
> + int ret, i, num_sd;
> +
> + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
> + if (ret)
> + return ret;
> +
> + viif_dev = devm_kzalloc(dev, sizeof(*viif_dev), GFP_KERNEL);
> + if (!viif_dev)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, viif_dev);
> + viif_dev->dev = dev;
> +
> + spin_lock_init(&viif_dev->lock);
> + mutex_init(&viif_dev->pow_lock);
> +
> + viif_dev->capture_reg = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(viif_dev->capture_reg))
> + return PTR_ERR(viif_dev->capture_reg);
> +
> + viif_dev->csi2host_reg = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(viif_dev->csi2host_reg))
> + return PTR_ERR(viif_dev->csi2host_reg);
> +
> + viif_dev->hwd_res = allocate_viif_res(dev, viif_dev->csi2host_reg, viif_dev->capture_reg);
> +
> + for (i = 0; i < NUM_IRQS; i++) {
> + ret = platform_get_irq(pdev, i);
> + if (ret < 0) {
> + dev_err(dev, "failed to acquire irq resource\n");
> + return ret;
> + }
> + viif_dev->irq[i] = ret;
> + ret = devm_request_irq(dev, viif_dev->irq[i], visconti_viif_irq, 0, IRQ_ID_STR,
> + viif_dev);
> + if (ret) {
> + dev_err(dev, "irq request failed\n");
> + return ret;
> + }
> + }
> +
> + viif_dev->table_vaddr =
> + dma_alloc_wc(dev, sizeof(struct viif_table_area), &table_paddr, GFP_KERNEL);
> + if (!viif_dev->table_vaddr) {
> + dev_err(dev, "dma_alloc_wc failed\n");
> + return -ENOMEM;
> + }
> + viif_dev->table_paddr = (struct viif_table_area *)table_paddr;
> +
> + /* power control */
> + pm_runtime_enable(dev);
> +
> + /* build media_dev */
> + viif_dev->media_dev.hw_revision = 0;
> + strscpy(viif_dev->media_dev.model, MEDIA_MODEL, sizeof(viif_dev->media_dev.model));
> + viif_dev->media_dev.dev = dev;
> + strscpy(viif_dev->media_dev.bus_info, MEDIA_BUS_INFO, sizeof(viif_dev->media_dev.bus_info));
> + media_device_init(&viif_dev->media_dev);
> +
> + /* build v4l2_dev */
> + viif_dev->v4l2_dev.mdev = &viif_dev->media_dev;
> + ret = v4l2_device_register(dev, &viif_dev->v4l2_dev);
> + if (ret)
> + goto error_dma_free;
> +
> + ret = media_device_register(&viif_dev->media_dev);
> + if (ret) {
> + dev_err(dev, "Failed to register media device: %d\n", ret);
> + goto error_v4l2_unregister;
> + }
> +
> + ret = visconti_viif_isp_register(viif_dev);
> + if (ret) {
> + dev_err(dev, "failed to register isp sub node: %d\n", ret);
> + goto error_media_unregister;
> + }
> + ret = visconti_viif_capture_register(viif_dev);
> + if (ret) {
> + dev_err(dev, "failed to register capture node: %d\n", ret);
> + goto error_media_unregister;
> + }
> +
> + /* check device type */
> + of_id = of_match_device(visconti_viif_of_table, dev);
> +
> + num_sd = visconti_viif_parse_dt(viif_dev);
> + if (ret < 0) {
> + ret = num_sd;
> + goto error_media_unregister;
> + }
> +
> + viif_dev->notifier.v4l2_dev = &viif_dev->v4l2_dev;
> + v4l2_async_nf_init(&viif_dev->notifier);
> + for (i = 0; i < num_sd; i++)
> + __v4l2_async_nf_add_subdev(&viif_dev->notifier, viif_dev->asds[i]);
> + viif_dev->notifier.ops = &viif_notify_ops;
> + ret = v4l2_async_nf_register(&viif_dev->v4l2_dev, &viif_dev->notifier);
> + if (ret)
> + goto error_media_unregister;
> +
> + return 0;
> +
> +error_media_unregister:
> + media_device_unregister(&viif_dev->media_dev);
> +error_v4l2_unregister:
> + v4l2_device_unregister(&viif_dev->v4l2_dev);
> +error_dma_free:
> + pm_runtime_disable(dev);
> + dma_free_wc(&pdev->dev, sizeof(struct viif_table_area), viif_dev->table_vaddr,
> + (dma_addr_t)viif_dev->table_paddr);
> + return ret;
> +}
> +
> +static int visconti_viif_remove(struct platform_device *pdev)
> +{
> + struct viif_device *viif_dev = platform_get_drvdata(pdev);
> +
> + visconti_viif_isp_unregister(viif_dev);
> + visconti_viif_capture_unregister(viif_dev);
> + v4l2_async_nf_unregister(&viif_dev->notifier);
> + media_device_unregister(&viif_dev->media_dev);
> + v4l2_device_unregister(&viif_dev->v4l2_dev);
> + pm_runtime_disable(&pdev->dev);
> + dma_free_wc(&pdev->dev, sizeof(struct viif_table_area), viif_dev->table_vaddr,
> + (dma_addr_t)viif_dev->table_paddr);
> +
> + return 0;
> +}
> +
> +static int visconti_viif_runtime_suspend(struct device *dev)
> +{
> + /* This callback is kicked when the last device-file is closed */
> + return 0;
> +}
> +
> +static int visconti_viif_runtime_resume(struct device *dev)
> +{
> + /* This callback is kicked when the first device-file is opened */
> + struct viif_device *viif_dev = dev_get_drvdata(dev);
> +
> + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_DISABLE;
> +
> + mutex_lock(&viif_dev->pow_lock);
> +
> + /* VSYNC mask setting of MAIN unit */
> + hwd_viif_main_vsync_set_irq_mask(
> + viif_dev->hwd_res, INT_M_SYNC_MASK_VSYNC_INT | INT_M_SYNC_MASK_LINES_DELAY_INT1 |
> + INT_M_SYNC_MASK_SW_DELAY_INT0 |
> + INT_M_SYNC_MASK_SW_DELAY_INT2);
> +
> + /* STATUS error mask setting of MAIN unit */
> + hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res, INT_M_MASK_DELAY_INT_ERROR);
> +
> + /* VSYNC mask settings of SUB unit */
> + hwd_viif_sub_vsync_set_irq_mask(viif_dev->hwd_res, INT_S_SYNC_MASK_VSYNC_INT |
> + INT_S_SYNC_MASK_SW_DELAY_INT0 |
> + INT_S_SYNC_MASK_SW_DELAY_INT1);
> +
> + /* STATUS error mask setting(unmask) of SUB unit */
> + hwd_viif_sub_status_err_set_irq_mask(viif_dev->hwd_res,
> + INT_S_MASK_RESERVED_SET | INT_S_MASK_DELAY_INT_ERROR);
> +
> + mutex_unlock(&viif_dev->pow_lock);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops visconti_viif_pm_ops = { SET_RUNTIME_PM_OPS(
> + visconti_viif_runtime_suspend, visconti_viif_runtime_resume, NULL) };
> +
> +static struct platform_driver visconti_viif_driver = {
> + .probe = visconti_viif_probe,
> + .remove = visconti_viif_remove,
> + .driver = {
> + .name = "visconti_viif",
> + .of_match_table = visconti_viif_of_table,
> + .pm = &visconti_viif_pm_ops,
> + },
> +};
> +
> +module_platform_driver(visconti_viif_driver);
> +
> +MODULE_AUTHOR("Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>");
> +MODULE_DESCRIPTION("Toshiba Visconti Video Input driver");
> +MODULE_LICENSE("Dual BSD/GPL");
> diff --git a/drivers/media/platform/visconti/viif.h b/drivers/media/platform/visconti/viif.h
> new file mode 100644
> index 00000000000..cd121ae3200
> --- /dev/null
> +++ b/drivers/media/platform/visconti/viif.h
> @@ -0,0 +1,203 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#ifndef VIIF_H
> +#define VIIF_H
> +
> +#include <linux/visconti_viif.h>
> +#include <media/v4l2-async.h>
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-dev.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-mediabus.h>
> +#include <media/v4l2-mem2mem.h>
> +#include <media/videobuf2-dma-contig.h>
> +
> +#include "hwd_viif.h"
> +
> +#define VIIF_ISP_REGBUF_0 0
> +#define VIIF_L2ISP_POST_0 0
> +#define VIIF_L2ISP_POST_1 1
> +
> +#define VIIF_CAPTURE_PAD_SINK 0
> +#define VIIF_ISP_PAD_SINK 0
> +#define VIIF_ISP_PAD_SRC_PATH0 1
> +#define VIIF_ISP_PAD_SRC_PATH1 2
> +#define VIIF_ISP_PAD_SRC_PATH2 3
> +#define VIIF_ISP_PAD_NUM 4
> +
> +#define CAPTURE_PATH_MAIN_POST0 0
> +#define CAPTURE_PATH_MAIN_POST1 1
> +#define CAPTURE_PATH_SUB 2
> +
> +#define VIIF_DPC_TABLE_BYTES 8192
> +#define VIIF_LSC_TABLE_BYTES 1536
> +#define VIIF_UNDIST_TABLE_BYTES 8192
> +#define VIIF_L2_GAMMA_TABLE_BYTES 512
> +
> +#define VIIF_HW_AVAILABLE_IRQS 4
> +
> +struct viif_fmt {
> + u32 fourcc;
> + u8 bpp[3];
> + u8 num_planes;
> + u32 colorspace;
> + u32 pitch_align;
> +};
> +
> +struct viif_subdev {
> + struct v4l2_subdev *v4l2_sd;
> + struct v4l2_async_subdev asd;
> +
> + /* per-subdevice mbus configuration options */
> + unsigned int mbus_flags;
> + unsigned int mbus_code;
> + unsigned int num_lane;
> +};
> +
> +struct viif_table_area {
> + /* viif_l1_dpc_config */
> + u32 dpc_table_h[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
> + u32 dpc_table_m[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
> + u32 dpc_table_l[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
> + /* viif_l1_lsc_config */
> + u16 lsc_table_gr[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> + u16 lsc_table_r[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> + u16 lsc_table_b[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> + u16 lsc_table_gb[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> + /* viif_l2_undist_config */
> + u32 undist_write_g[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> + u32 undist_read_b[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> + u32 undist_read_g[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> + u32 undist_read_r[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> + /* viif_l2_gamma_config */
> + u16 l2_gamma_table[2][6][VIIF_L2_GAMMA_TABLE_BYTES / sizeof(u16)];
> +};
> +
> +/* capture device node information */
> +struct cap_dev {
> + u32 pathid; /* 0 ... MAIN POST0, 1 ... MAIN POST1, 2 ... SUB */
> + struct video_device vdev;
> + struct media_pad capture_pad;
> + struct v4l2_ctrl_handler ctrl_handler;
> + struct mutex vlock; /* serialize ioctl to vb2_queue and video_device */
> +
> + /* vb2 queue, capture buffer list and active buffer pointer */
> + struct vb2_queue vb2_vq;
> + struct list_head buf_queue;
> + struct vb2_v4l2_buffer *active;
> + struct vb2_v4l2_buffer *dma_active;
> + int buf_cnt;
> + unsigned int sequence;
> +
> + /* currently configured field and pixel format */
> + enum v4l2_field field;
> + struct v4l2_pix_format_mplane v4l2_pix;
> + unsigned int out_format;
> + struct hwd_viif_img_area img_area;
> + struct hwd_viif_out_process out_process;
> +
> + struct viif_device *viif_dev;
> +};
> +
> +struct isp_subdev {
> + struct v4l2_subdev sd;
> + struct media_pad pads[VIIF_ISP_PAD_NUM];
> + struct v4l2_subdev_pad_config pad_cfg[VIIF_ISP_PAD_NUM];
> + struct mutex ops_lock; /* serialize V4L2 query */
> + struct viif_device *viif_dev;
> + struct v4l2_ctrl_handler ctrl_handler;
> +};
> +
> +struct hwd_viif_res;
> +
> +struct viif_device {
> + struct device *dev;
> + struct v4l2_device v4l2_dev;
> + struct media_device media_dev;
> + struct media_pipeline pipe;
> + u32 masked_gamma_path;
> + struct hwd_viif_func *func;
> +
> + struct viif_subdev *subdevs;
> + struct v4l2_async_subdev **asds;
> + /* async subdev notification helpers */
> + struct v4l2_async_notifier notifier;
> +
> + /* the subdevice currently in use */
> + struct viif_subdev *sd;
> + unsigned int sd_index;
> + unsigned int num_sd;
> +
> + /* sub device node information */
> + struct cap_dev cap_dev0;
> + struct cap_dev cap_dev1;
> + struct cap_dev cap_dev2;
> + struct isp_subdev isp_subdev;
> +
> + /* lock - serialize calls to low-level operations (hwd_xxxx) */
> + /* also, this serialize access to capture buffer queue and active buffer */
> + spinlock_t lock;
> +
> + /* pow_lock - serialize power control*/
> + struct mutex pow_lock;
> +
> + struct {
> + u32 clock_id;
> + u32 csi2_clock_id;
> + u32 csi2_reset_id;
> + } clk_compat;
> +
> + /* hwd_res - context of low level implementation */
> + struct hwd_viif_res *hwd_res;
> +
> + void __iomem *capture_reg;
> + void __iomem *csi2host_reg;
> + unsigned int irq[VIIF_HW_AVAILABLE_IRQS];
> +
> + /* Un-cache table area */
> + struct viif_table_area *table_vaddr;
> + struct viif_table_area *table_paddr;
> +
> + /* Rawpack mode */
> + u32 rawpack_mode;
> +
> + /* Error flag checked at delayed vsync handler */
> + u32 status_err;
> +
> + /* Error flag checked at compound control GET_REPORTED_ERRORS */
> + u32 reported_err_main;
> + u32 reported_err_sub;
> + u32 reported_err_csi2rx;
> +};
> +
> +/* viif.c */
> +void visconti_viif_hw_on(struct viif_device *viif_dev);
> +void visconti_viif_hw_off(struct viif_device *viif_dev);
> +
> +/* viif_capture.c */
> +int visconti_viif_capture_register(struct viif_device *viif_dev);
> +void visconti_viif_capture_unregister(struct viif_device *viif_dev);
> +int visconti_viif_capture_register_ctrl_handlers(struct viif_device *viif_dev);
> +void visconti_viif_capture_switch_buffer(struct cap_dev *cap_dev, u32 status_err,
> + u32 l2_transfer_status, u64 timestamp);
> +
> +/* viif_isp.c */
> +int visconti_viif_isp_register(struct viif_device *viif_dev);
> +void visconti_viif_isp_unregister(struct viif_device *viif_dev);
> +int visconti_viif_isp_main_set_unit(struct viif_device *viif_dev);
> +int visconti_viif_isp_sub_set_unit(struct viif_device *viif_dev);
> +void visconti_viif_isp_set_compose_rect(struct viif_device *viif_dev,
> + struct viif_l2_roi_config *roi);
> +
> +/* viif_controls.c */
> +int visconti_viif_isp_init_controls(struct viif_device *viif_dev);
> +
> +#endif /* VIIF_H */
> diff --git a/drivers/media/platform/visconti/viif_capture.c b/drivers/media/platform/visconti/viif_capture.c
> new file mode 100644
> index 00000000000..fa18aec4470
> --- /dev/null
> +++ b/drivers/media/platform/visconti/viif_capture.c
> @@ -0,0 +1,1201 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/pm_runtime.h>
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-subdev.h>
> +
> +#include "viif.h"
> +
> +#define VIIF_CROP_MAX_X_ISP (8062U)
> +#define VIIF_CROP_MAX_Y_ISP (3966U)
> +#define VIIF_CROP_MIN_W (128U)
> +#define VIIF_CROP_MAX_W_ISP (8190U)
> +#define VIIF_CROP_MIN_H (128U)
> +#define VIIF_CROP_MAX_H_ISP (4094U)
> +
> +struct viif_buffer {
> + struct vb2_v4l2_buffer vb;
> + struct list_head queue;
> +};
> +
> +static inline struct viif_buffer *vb2_to_viif(struct vb2_v4l2_buffer *vbuf)
> +{
> + return container_of(vbuf, struct viif_buffer, vb);
> +}
> +
> +static inline struct cap_dev *video_drvdata_to_capdev(struct file *file)
> +{
> + return (struct cap_dev *)video_drvdata(file);
> +}
> +
> +static inline struct cap_dev *vb2queue_to_capdev(struct vb2_queue *vq)
> +{
> + return (struct cap_dev *)vb2_get_drv_priv(vq);
> +}
> +
> +/* ----- ISRs and VB2 Operations ----- */
> +static int viif_set_img(struct cap_dev *cap_dev, struct vb2_buffer *vb)
> +{
> + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct hwd_viif_img next_out_img;
> + dma_addr_t phys_addr;
> + int i, ret = 0;
> +
> + next_out_img.width = pix->width;
> + next_out_img.height = pix->height;
> + next_out_img.format = cap_dev->out_format;
> +
> + for (i = 0; i < pix->num_planes; i++) {
> + next_out_img.pixelmap[i].pitch = pix->plane_fmt[i].bytesperline;
> + phys_addr = vb2_dma_contig_plane_dma_addr(vb, i);
> + next_out_img.pixelmap[i].pmap_paddr = phys_addr;
> + }
> +
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l2_set_img_transmission(viif_dev->hwd_res, VIIF_L2ISP_POST_0,
> + HWD_VIIF_ENABLE, &cap_dev->img_area,
> + &cap_dev->out_process, &next_out_img);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + if (ret)
> + dev_err(viif_dev->dev, "set img error. %d\n", ret);
> + } else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1) {
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l2_set_img_transmission(viif_dev->hwd_res, VIIF_L2ISP_POST_1,
> + HWD_VIIF_ENABLE, &cap_dev->img_area,
> + &cap_dev->out_process, &next_out_img);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + if (ret)
> + dev_err(viif_dev->dev, "set img error. %d\n", ret);
> + } else if (cap_dev->pathid == CAPTURE_PATH_SUB) {
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_sub_set_img_transmission(viif_dev->hwd_res, &next_out_img);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + if (ret)
> + dev_err(viif_dev->dev, "set img error. %d\n", ret);
> + }
> +
> + return ret;
> +}
> +
> +/*
> + * viif_capture_switch_buffer() is called from interrupt service routine
> + * triggered by VSync with some fixed delay.
> + * The function may switch DMA target buffer by calling viif_set_img().
> + * The VIIF DMA HW captures the destination address at next VSync
> + * and completes transfer at one more after.
> + * Therefore, filled buffer is available at the one after next ISR.
> + *
> + * To avoid DMA HW getting stucked, we always need to set valid destination address.
> + * If a prepared buffer is not available, we reuse the buffer currently being transferred to.
> + *
> + * The cap_dev structure has two pointers and a queue to handle video buffers;
> + + Description of each item at the entry of this function:
> + * * buf_queue: holds prepared buffers, set by vb2_queue()
> + * * active: pointing at address captured (and to be filled) by DMA HW
> + * * dma_active: pointing at buffer filled by DMA HW
> + *
> + * Rules to update items:
> + * * when buf_queue is not empty, "active" buffer goes "dma_active"
> + * * when buf_queue is empty:
> + * * "active" buffer stays the same (DMA HW fills the same buffer for coming two frames)
> + * * "dma_active" gets NULL (filled buffer will be reused; should not go "DONE" at next ISR)
> + *
> + * Simulation:
> + * | buf_queue | active | dma_active | note |
> + * | X | NULL | NULL | |
> + * <QBUF BUF0>
> + * | X | BUF0 | NULL | BUF0 stays |
> + * | X | BUF0 | NULL | BUF0 stays |
> + * <QBUF BUF1>
> + * <QBUF BUF2>
> + * | BUF2 BUF1 | BUF0 | NULL | |
> + * | BUF2 | BUF1 | BUF0 | BUF0 goes DONE |
> + * | X | BUF2 | BUF1 | BUF1 goes DONE, BUF2 stays |
> + * | X | BUF2 | NULL | BUF2 stays |
> + */
> +void visconti_viif_capture_switch_buffer(struct cap_dev *cap_dev, u32 status_err,
> + u32 l2_transfer_status, u64 timestamp)
> +{
> + if (cap_dev->dma_active) {
> + /* DMA has completed and another framebuffer instance is set */
> + struct vb2_v4l2_buffer *vbuf = cap_dev->dma_active;
> + enum vb2_buffer_state state;
> +
> + cap_dev->buf_cnt--;
> + vbuf->vb2_buf.timestamp = timestamp;
> + vbuf->sequence = cap_dev->sequence++;
> + vbuf->field = cap_dev->field;
> + if (status_err || l2_transfer_status)
> + state = VB2_BUF_STATE_ERROR;
> + else
> + state = VB2_BUF_STATE_DONE;
> +
> + vb2_buffer_done(&vbuf->vb2_buf, state);
> + }
> +
> + /* QUEUE pop to register an instance as next DMA target; if empty, reuse current instance */
> + if (!list_empty(&cap_dev->buf_queue)) {
> + struct viif_buffer *buf =
> + list_entry(cap_dev->buf_queue.next, struct viif_buffer, queue);
> + list_del_init(&buf->queue);
> + viif_set_img(cap_dev, &buf->vb.vb2_buf);
> + cap_dev->active = &buf->vb;
> + cap_dev->dma_active = cap_dev->active;
> + } else {
> + cap_dev->dma_active = NULL;
> + }
> +}
> +
> +/* --- Capture buffer control --- */
> +static int viif_vb2_setup(struct vb2_queue *vq, unsigned int *count, unsigned int *num_planes,
> + unsigned int sizes[], struct device *alloc_devs[])
> +{
> + struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
> + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> + unsigned int i;
> +
> + /* num_planes is set: just check plane sizes. */
> + if (*num_planes) {
> + for (i = 0; i < pix->num_planes; i++)
> + if (sizes[i] < pix->plane_fmt[i].sizeimage)
> + return -EINVAL;
> +
> + return 0;
> + }
> +
> + /* num_planes not set: called from REQBUFS, just set plane sizes. */
> + *num_planes = pix->num_planes;
> + for (i = 0; i < pix->num_planes; i++)
> + sizes[i] = pix->plane_fmt[i].sizeimage;
> +
> + cap_dev->buf_cnt = 0;
> +
> + return 0;
> +}
> +
> +static void viif_vb2_queue(struct vb2_buffer *vb)
> +{
> + struct cap_dev *cap_dev = vb2queue_to_capdev(vb->vb2_queue);
> + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct viif_buffer *buf = vb2_to_viif(vbuf);
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> +
> + if (!cap_dev->active) {
> + cap_dev->active = vbuf;
> + viif_set_img(cap_dev, vb);
> + } else {
> + list_add_tail(&buf->queue, &cap_dev->buf_queue);
> + }
> + cap_dev->buf_cnt++;
> +
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +}
> +
> +static int viif_vb2_prepare(struct vb2_buffer *vb)
> +{
> + struct cap_dev *cap_dev = vb2queue_to_capdev(vb->vb2_queue);
> + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + unsigned int i;
> +
> + for (i = 0; i < pix->num_planes; i++) {
> + if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
> + dev_err(viif_dev->dev, "Plane size too small (%lu < %u)\n",
> + vb2_plane_size(vb, i), pix->plane_fmt[i].sizeimage);
> + return -EINVAL;
> + }
> +
> + vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
> + }
> + return 0;
> +}
> +
> +static int viif_start_streaming(struct vb2_queue *vq, unsigned int count)
> +{
> + struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> +
> + /* note that pipe is shared among paths; see pipe.streaming_count member variable */
> + ret = video_device_pipeline_start(&cap_dev->vdev, &viif_dev->pipe);
> + if (ret)
> + dev_err(viif_dev->dev, "start pipeline failed %d\n", ret);
Huh, why do you ignore the error and continue?
> +
> + /* Currently, only path0 (MAIN POST0) initializes ISP and Camera */
> + /* Possibly, initialization can be done when pipe.streaming_count==0 */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + /* CSI2RX start */
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, video, s_stream, true);
> + if (ret) {
> + dev_err(viif_dev->dev, "Start isp subdevice stream failed. %d\n", ret);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
On error all queued buffers have to be returned to vb2 with status VB2_BUF_STATE_QUEUED.
Otherwise the vb2 internal status will get confused. Similar to stop_streaming, just
with a different status (QUEUED instead of ERROR).
> + return ret;
> + }
> + }
> +
> + /* buffer control */
> + cap_dev->sequence = 0;
> +
> + /* finish critical section: some sensor driver (including imx219) calls schedule() */
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + /* Camera (CSI2 source) start streaming */
> + /* Currently, only path0 (MAIN POST0) initializes ISP and Camera */
> + /* Possibly, initialization can be done when pipe.streaming_count==0 */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, s_stream, true);
> + if (ret) {
> + dev_err(viif_dev->dev, "Start subdev stream failed. %d\n", ret);
> + (void)v4l2_subdev_call(&viif_dev->isp_subdev.sd, video, s_stream, false);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void viif_stop_streaming(struct vb2_queue *vq)
> +{
> + struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + struct viif_buffer *buf;
> + unsigned long irqflags;
> + int ret;
> +
> + /* Currently, only path0 (MAIN POST0) stops ISP and Camera */
> + /* Possibly, teardown can be done when pipe.streaming_count==0 */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, s_stream, false);
> + if (ret)
> + dev_err(viif_dev->dev, "Stop subdev stream failed. %d\n", ret);
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> +
> + /* Currently, only path0 (MAIN POST0) stops ISP and Camera */
> + /* Possibly, teardown can be done when pipe.streaming_count==0 */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, video, s_stream, false);
> + if (ret)
> + dev_err(viif_dev->dev, "Stop isp subdevice stream failed %d\n", ret);
> + }
> +
> + /* buffer control */
> + if (cap_dev->active) {
> + vb2_buffer_done(&cap_dev->active->vb2_buf, VB2_BUF_STATE_ERROR);
> + cap_dev->buf_cnt--;
> + cap_dev->active = NULL;
> + }
> + if (cap_dev->dma_active) {
> + vb2_buffer_done(&cap_dev->dma_active->vb2_buf, VB2_BUF_STATE_ERROR);
> + cap_dev->buf_cnt--;
> + cap_dev->dma_active = NULL;
> + }
> +
> + /* Release all queued buffers. */
> + list_for_each_entry(buf, &cap_dev->buf_queue, queue) {
> + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> + cap_dev->buf_cnt--;
> + }
> + INIT_LIST_HEAD(&cap_dev->buf_queue);
> + if (cap_dev->buf_cnt)
> + dev_err(viif_dev->dev, "Buffer count error %d\n", cap_dev->buf_cnt);
> +
> + video_device_pipeline_stop(&cap_dev->vdev);
> +
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +}
> +
> +static const struct vb2_ops viif_vb2_ops = {
> + .queue_setup = viif_vb2_setup,
> + .buf_queue = viif_vb2_queue,
> + .buf_prepare = viif_vb2_prepare,
> + .wait_prepare = vb2_ops_wait_prepare,
> + .wait_finish = vb2_ops_wait_finish,
> + .start_streaming = viif_start_streaming,
> + .stop_streaming = viif_stop_streaming,
> +};
> +
> +/* --- VIIF hardware settings --- */
> +/* L2ISP output csc setting for YUV to RGB(ITU-R BT.709) */
> +static const struct hwd_viif_csc_param viif_csc_yuv2rgb = {
> + .r_cr_in_offset = 0x18000,
> + .g_y_in_offset = 0x1f000,
> + .b_cb_in_offset = 0x18000,
> + .coef = {
> + [0] = 0x1000,
> + [1] = 0xfd12,
> + [2] = 0xf8ad,
> + [3] = 0x1000,
> + [4] = 0x1d07,
> + [5] = 0x0000,
> + [6] = 0x1000,
> + [7] = 0x0000,
> + [8] = 0x18a2,
> + },
> + .r_cr_out_offset = 0x1000,
> + .g_y_out_offset = 0x1000,
> + .b_cb_out_offset = 0x1000,
> +};
> +
> +/* L2ISP output csc setting for RGB to YUV(ITU-R BT.709) */
> +static const struct hwd_viif_csc_param viif_csc_rgb2yuv = {
> + .r_cr_in_offset = 0x1f000,
> + .g_y_in_offset = 0x1f000,
> + .b_cb_in_offset = 0x1f000,
> + .coef = {
> + [0] = 0x0b71,
> + [1] = 0x0128,
> + [2] = 0x0367,
> + [3] = 0xf9b1,
> + [4] = 0x082f,
> + [5] = 0xfe20,
> + [6] = 0xf891,
> + [7] = 0xff40,
> + [8] = 0x082f,
> + },
> + .r_cr_out_offset = 0x8000,
> + .g_y_out_offset = 0x1000,
> + .b_cb_out_offset = 0x8000,
> +};
> +
> +static int viif_l2_set_format(struct cap_dev *cap_dev)
> +{
> + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + const struct hwd_viif_csc_param *csc_param = NULL;
> + struct v4l2_subdev_selection sel = {
> + .target = V4L2_SEL_TGT_CROP,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + struct v4l2_subdev_format fmt = {
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + bool inp_is_rgb = false;
> + bool out_is_rgb = false;
> + u32 postid;
> + int ret;
> +
> + /* check path id */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> + fmt.pad = VIIF_ISP_PAD_SRC_PATH0;
> + postid = VIIF_L2ISP_POST_0;
> + } else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1) {
> + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> + fmt.pad = VIIF_ISP_PAD_SRC_PATH1;
> + postid = VIIF_L2ISP_POST_1;
> + } else {
> + return -EINVAL;
> + }
> +
> + cap_dev->out_process.half_scale = HWD_VIIF_DISABLE;
> + cap_dev->out_process.select_color = HWD_VIIF_COLOR_YUV_RGB;
> + cap_dev->out_process.alpha = 0;
> +
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection, NULL, &sel);
> + if (ret) {
> + cap_dev->img_area.x = 0;
> + cap_dev->img_area.y = 0;
> + cap_dev->img_area.w = pix->width;
> + cap_dev->img_area.h = pix->height;
> + } else {
> + cap_dev->img_area.x = sel.r.left;
> + cap_dev->img_area.y = sel.r.top;
> + cap_dev->img_area.w = sel.r.width;
> + cap_dev->img_area.h = sel.r.height;
> + }
> +
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_fmt, NULL, &fmt);
> + if (!ret)
> + inp_is_rgb = (fmt.format.code == MEDIA_BUS_FMT_RGB888_1X24);
> +
> + switch (pix->pixelformat) {
> + case V4L2_PIX_FMT_RGB24:
> + cap_dev->out_format = HWD_VIIF_RGB888_PACKED;
> + out_is_rgb = true;
> + break;
> + case V4L2_PIX_FMT_ABGR32:
> + cap_dev->out_format = HWD_VIIF_ARGB8888_PACKED;
> + cap_dev->out_process.alpha = 0xff;
> + out_is_rgb = true;
> + break;
> + case V4L2_PIX_FMT_YUV422M:
> + cap_dev->out_format = HWD_VIIF_YCBCR422_8_PLANAR;
> + break;
> + case V4L2_PIX_FMT_YUV444M:
> + cap_dev->out_format = HWD_VIIF_RGB888_YCBCR444_8_PLANAR;
> + break;
> + case V4L2_PIX_FMT_Y16:
> + cap_dev->out_format = HWD_VIIF_ONE_COLOR_16;
> + cap_dev->out_process.select_color = HWD_VIIF_COLOR_Y_G;
> + break;
> + }
> +
> + if (!inp_is_rgb && out_is_rgb)
> + csc_param = &viif_csc_yuv2rgb; /* YUV -> RGB */
> + else if (inp_is_rgb && !out_is_rgb)
> + csc_param = &viif_csc_rgb2yuv; /* RGB -> YUV */
> +
> + return hwd_viif_l2_set_output_csc(viif_dev->hwd_res, postid, csc_param);
> +}
> +
> +/* --- IOCTL Operations --- */
> +static const struct viif_fmt viif_fmt_list[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_RGB24,
> + .bpp = { 24, 0, 0 },
> + .num_planes = 1,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .pitch_align = 384,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_ABGR32,
> + .bpp = { 32, 0, 0 },
> + .num_planes = 1,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .pitch_align = 512,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_YUV422M,
> + .bpp = { 8, 4, 4 },
> + .num_planes = 3,
> + .colorspace = V4L2_COLORSPACE_REC709,
> + .pitch_align = 128,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_YUV444M,
> + .bpp = { 8, 8, 8 },
> + .num_planes = 3,
> + .colorspace = V4L2_COLORSPACE_REC709,
> + .pitch_align = 128,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_Y16,
> + .bpp = { 16, 0, 0 },
> + .num_planes = 1,
> + .colorspace = V4L2_COLORSPACE_REC709,
> + .pitch_align = 128,
> + },
> +};
> +
> +static const struct viif_fmt viif_rawfmt_list[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_SRGGB10,
> + .bpp = { 16, 0, 0 },
> + .num_planes = 1,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .pitch_align = 256,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_SRGGB12,
> + .bpp = { 16, 0, 0 },
> + .num_planes = 1,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .pitch_align = 256,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_SRGGB14,
> + .bpp = { 16, 0, 0 },
> + .num_planes = 1,
> + .colorspace = V4L2_COLORSPACE_SRGB,
> + .pitch_align = 256,
> + },
> +};
> +
> +static const struct viif_fmt *get_viif_fmt_from_fourcc(unsigned int fourcc)
> +{
> + const struct viif_fmt *fmt = &viif_fmt_list[0];
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(viif_fmt_list); i++, fmt++)
> + if (fmt->fourcc == fourcc)
> + return fmt;
> +
> + return NULL;
> +}
> +
> +static void viif_update_plane_sizes(struct v4l2_plane_pix_format *plane, unsigned int bpl,
> + unsigned int szimage)
> +{
> + memset(plane, 0, sizeof(*plane));
> +
> + plane->sizeimage = szimage;
> + plane->bytesperline = bpl;
> +}
> +
> +static void viif_calc_plane_sizes(const struct viif_fmt *viif_fmt,
> + struct v4l2_pix_format_mplane *pix)
> +{
> + unsigned int i, bpl, szimage;
> +
> + for (i = 0; i < viif_fmt->num_planes; i++) {
> + bpl = pix->width * viif_fmt->bpp[i] / 8;
> + /* round up ptch */
> + bpl = (bpl + (viif_fmt->pitch_align - 1)) / viif_fmt->pitch_align;
> + bpl *= viif_fmt->pitch_align;
> + szimage = pix->height * bpl;
> + viif_update_plane_sizes(&pix->plane_fmt[i], bpl, szimage);
> + }
> + pix->num_planes = viif_fmt->num_planes;
> +}
> +
> +static int viif_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> +
> + strscpy(cap->card, "Toshiba VIIF", sizeof(cap->card));
> + strscpy(cap->driver, "viif", sizeof(cap->driver));
> + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:toshiba-viif-%s",
> + dev_name(viif_dev->dev));
> + return 0;
> +}
> +
> +static int viif_enum_rawfmt(struct cap_dev *cap_dev, struct v4l2_fmtdesc *f)
> +{
> + if (f->index >= ARRAY_SIZE(viif_rawfmt_list))
> + return -EINVAL;
> +
> + f->pixelformat = viif_rawfmt_list[f->index].fourcc;
> +
> + return 0;
> +}
> +
> +static int viif_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *f)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> + const struct viif_fmt *fmt;
> +
> + if (cap_dev->pathid == CAPTURE_PATH_SUB)
> + return viif_enum_rawfmt(cap_dev, f);
> +
> + if (f->index >= ARRAY_SIZE(viif_fmt_list))
> + return -EINVAL;
> +
> + fmt = &viif_fmt_list[f->index];
> + f->pixelformat = fmt->fourcc;
> +
> + return 0;
> +}
> +
> +/* size of minimum/maximum output image */
> +#define VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> +#define VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> +#define VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> +
> +#define VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> +#define VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> +#define VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> +
> +static int viif_try_fmt(struct cap_dev *cap_dev, struct v4l2_format *v4l2_fmt)
> +{
> + struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct v4l2_subdev_format format = {
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + const struct viif_fmt *viif_fmt;
> + int ret;
> +
> + /* check path id */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> + format.pad = VIIF_ISP_PAD_SRC_PATH0;
> + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> + format.pad = VIIF_ISP_PAD_SRC_PATH1;
> + else
> + format.pad = VIIF_ISP_PAD_SRC_PATH2;
> +
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_fmt, NULL, &format);
> + if (ret)
> + return -EINVAL;
> +
> + /* fourcc check */
> + if (cap_dev->pathid == CAPTURE_PATH_SUB) {
> + switch (format.format.code) {
> + case MEDIA_BUS_FMT_SRGGB10_1X10:
> + case MEDIA_BUS_FMT_SGRBG10_1X10:
> + case MEDIA_BUS_FMT_SGBRG10_1X10:
> + case MEDIA_BUS_FMT_SBGGR10_1X10:
> + viif_fmt = &viif_rawfmt_list[0]; /*V4L2_PIX_FMT_SRGGB10*/
> + pix->pixelformat = viif_fmt->fourcc;
> + break;
> + case MEDIA_BUS_FMT_SRGGB12_1X12:
> + case MEDIA_BUS_FMT_SGRBG12_1X12:
> + case MEDIA_BUS_FMT_SGBRG12_1X12:
> + case MEDIA_BUS_FMT_SBGGR12_1X12:
> + viif_fmt = &viif_rawfmt_list[1]; /*V4L2_PIX_FMT_SRGGB12*/
> + pix->pixelformat = viif_fmt->fourcc;
> + break;
> + case MEDIA_BUS_FMT_SRGGB14_1X14:
> + case MEDIA_BUS_FMT_SGRBG14_1X14:
> + case MEDIA_BUS_FMT_SGBRG14_1X14:
> + case MEDIA_BUS_FMT_SBGGR14_1X14:
> + viif_fmt = &viif_rawfmt_list[2]; /*V4L2_PIX_FMT_SRGGB14*/
> + pix->pixelformat = viif_fmt->fourcc;
> + break;
> + default:
> + return -EINVAL;
> + }
> + } else {
> + viif_fmt = get_viif_fmt_from_fourcc(pix->pixelformat);
> + if (!viif_fmt)
> + return -EINVAL;
> + }
> +
> + /* min/max width, height check */
> + if (pix->width < VIIF_MIN_OUTPUT_IMG_WIDTH)
> + pix->width = VIIF_MIN_OUTPUT_IMG_WIDTH;
> +
> + if (pix->width > VIIF_MAX_OUTPUT_IMG_WIDTH_ISP)
> + pix->width = VIIF_MAX_OUTPUT_IMG_WIDTH_ISP;
> +
> + if (pix->height < VIIF_MIN_OUTPUT_IMG_HEIGHT)
> + pix->height = VIIF_MIN_OUTPUT_IMG_HEIGHT;
> +
> + if (pix->height > VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP)
> + pix->height = VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP;
> +
> + /* consistency with isp::pad::src::fmt */
> + if (pix->width != format.format.width)
> + return -EINVAL;
> + if (pix->height != format.format.height)
> + return -EINVAL;
> +
> + /* update derived parameters, such as bpp */
> + viif_calc_plane_sizes(viif_fmt, pix);
> +
> + return 0;
> +}
> +
> +static int viif_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> +
> + return viif_try_fmt(cap_dev, f);
> +}
> +
> +static int viif_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + int ret = 0;
> +
> + if (vb2_is_streaming(&cap_dev->vb2_vq))
That should be vb2_is_busy(). Once buffers are allocated, you can no longer
change the format since that would change the buffer size as well.
> + return -EBUSY;
> +
> + if (f->type != cap_dev->vb2_vq.type)
> + return -EINVAL;
> +
> + ret = viif_try_fmt(cap_dev, f);
> + if (ret)
> + return ret;
> +
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> + /*
> + * A call to main_set_unit() is currently at ioctl(VIDIOC_S_FMT) context.
> + * This call can be moved to viif_isp_s_stream(),
> + * if you don't want to check the given format is compatible to HW.
> + */
> + ret = visconti_viif_isp_main_set_unit(viif_dev);
> + if (ret)
> + return ret;
> + }
> +
> + cap_dev->v4l2_pix = f->fmt.pix_mp;
> + cap_dev->field = V4L2_FIELD_NONE;
> +
> + if (cap_dev->pathid == CAPTURE_PATH_SUB) {
> + cap_dev->out_format = HWD_VIIF_ONE_COLOR_16;
> + ret = visconti_viif_isp_sub_set_unit(viif_dev);
> + } else {
> + ret = viif_l2_set_format(cap_dev);
> + }
> +
> + return ret;
> +}
> +
> +static int viif_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> +
> + f->fmt.pix_mp = cap_dev->v4l2_pix;
> +
> + return 0;
> +}
> +
> +static int viif_enum_input(struct file *file, void *priv, struct v4l2_input *inp)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd;
> + struct v4l2_subdev *v4l2_sd;
> + int ret;
> +
> + if (inp->index >= viif_dev->num_sd)
> + return -EINVAL;
> +
> + viif_sd = &viif_dev->subdevs[inp->index];
> + v4l2_sd = viif_sd->v4l2_sd;
> +
> + ret = v4l2_subdev_call(v4l2_sd, video, g_input_status, &inp->status);
> + if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
> + return ret;
> + inp->type = V4L2_INPUT_TYPE_CAMERA;
> + inp->std = 0;
> + if (v4l2_subdev_has_op(v4l2_sd, pad, dv_timings_cap))
> + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
> + else
> + inp->capabilities = V4L2_IN_CAP_STD;
> + snprintf(inp->name, sizeof(inp->name), "Camera%u: %s", inp->index, viif_sd->v4l2_sd->name);
> +
> + return 0;
> +}
> +
> +static int viif_g_input(struct file *file, void *priv, unsigned int *i)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> +
> + *i = viif_dev->sd_index;
> +
> + return 0;
> +}
> +
> +static int viif_s_input(struct file *file, void *priv, unsigned int i)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> +
> + if (i >= viif_dev->num_sd)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int viif_g_selection(struct file *file, void *priv, struct v4l2_selection *s)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct v4l2_subdev_selection sel = {
> + .target = V4L2_SEL_TGT_CROP,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + int ret;
> +
This is missing validation checks for s->type and s->target.
I've pretty sure you didn't run the v4l2-compliance utility: that would have
failed on this.
> + /* check path id */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> + else
> + return -EINVAL;
> +
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection, NULL, &sel);
> + s->r = sel.r;
> +
> + return ret;
> +}
> +
> +static int viif_s_selection(struct file *file, void *priv, struct v4l2_selection *s)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct v4l2_subdev_selection sel = {
> + .target = V4L2_SEL_TGT_CROP,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + .r = s->r,
> + };
> + int ret;
> +
Same as above.
> + /* check path id */
> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> + else
> + return -EINVAL;
> +
> + if (s->r.left > VIIF_CROP_MAX_X_ISP || s->r.top > VIIF_CROP_MAX_Y_ISP ||
> + s->r.width < VIIF_CROP_MIN_W || s->r.width > VIIF_CROP_MAX_W_ISP ||
> + s->r.height < VIIF_CROP_MIN_H || s->r.height > VIIF_CROP_MAX_H_ISP) {
> + return -EINVAL;
> + }
> +
> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, set_selection, NULL, &sel);
> + s->r = sel.r;
> +
> + return ret;
> +}
> +
> +static int viif_dv_timings_cap(struct file *file, void *priv_fh, struct v4l2_dv_timings_cap *cap)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, dv_timings_cap, cap);
> +}
> +
> +static int viif_enum_dv_timings(struct file *file, void *priv_fh,
> + struct v4l2_enum_dv_timings *timings)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, enum_dv_timings, timings);
> +}
> +
> +static int viif_g_dv_timings(struct file *file, void *priv_fh, struct v4l2_dv_timings *timings)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, video, g_dv_timings, timings);
> +}
> +
> +static int viif_s_dv_timings(struct file *file, void *priv_fh, struct v4l2_dv_timings *timings)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, video, s_dv_timings, timings);
> +}
> +
> +static int viif_query_dv_timings(struct file *file, void *priv_fh, struct v4l2_dv_timings *timings)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, video, query_dv_timings, timings);
> +}
> +
> +static int viif_g_edid(struct file *file, void *fh, struct v4l2_edid *edid)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_edid, edid);
> +}
> +
> +static int viif_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> +
> + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid, edid);
> +}
Has this driver been tested with an HDMI receiver? If not, then I would recommend
dropping support for it until you actually can test with such hardware.
The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces, it's not meant
for CSI and similar interfaces.
> +
> +static int viif_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> +
> + return v4l2_g_parm_cap(video_devdata(file), viif_dev->sd->v4l2_sd, a);
> +}
> +
> +static int viif_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> +
> + return v4l2_s_parm_cap(video_devdata(file), viif_dev->sd->v4l2_sd, a);
> +}
> +
> +static int viif_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + struct v4l2_subdev *v4l2_sd = viif_sd->v4l2_sd;
> + struct v4l2_subdev_frame_size_enum fse = {
> + .code = viif_sd->mbus_code,
> + .index = fsize->index,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + int ret;
> +
> + ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size, NULL, &fse);
> + if (ret)
> + return ret;
> +
> + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
> + fsize->discrete.width = fse.max_width;
> + fsize->discrete.height = fse.max_height;
> +
> + return 0;
> +}
> +
> +static int viif_enum_frameintervals(struct file *file, void *fh, struct v4l2_frmivalenum *fival)
> +{
> + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + struct v4l2_subdev *v4l2_sd = viif_sd->v4l2_sd;
> + struct v4l2_subdev_frame_interval_enum fie = {
> + .code = viif_sd->mbus_code,
> + .index = fival->index,
> + .width = fival->width,
> + .height = fival->height,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + int ret;
> +
> + ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL, &fie);
> + if (ret)
> + return ret;
> +
> + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
> + fival->discrete = fie.interval;
> +
> + return 0;
> +}
> +
> +static const struct v4l2_ioctl_ops viif_ioctl_ops = {
> + .vidioc_querycap = viif_querycap,
> +
> + .vidioc_enum_fmt_vid_cap = viif_enum_fmt_vid_cap,
> + .vidioc_try_fmt_vid_cap_mplane = viif_try_fmt_vid_cap,
> + .vidioc_s_fmt_vid_cap_mplane = viif_s_fmt_vid_cap,
> + .vidioc_g_fmt_vid_cap_mplane = viif_g_fmt_vid_cap,
> +
> + .vidioc_enum_input = viif_enum_input,
> + .vidioc_g_input = viif_g_input,
> + .vidioc_s_input = viif_s_input,
> +
> + .vidioc_g_selection = viif_g_selection,
> + .vidioc_s_selection = viif_s_selection,
> +
> + .vidioc_dv_timings_cap = viif_dv_timings_cap,
> + .vidioc_enum_dv_timings = viif_enum_dv_timings,
> + .vidioc_g_dv_timings = viif_g_dv_timings,
> + .vidioc_s_dv_timings = viif_s_dv_timings,
> + .vidioc_query_dv_timings = viif_query_dv_timings,
> +
> + .vidioc_g_edid = viif_g_edid,
> + .vidioc_s_edid = viif_s_edid,
> +
> + .vidioc_g_parm = viif_g_parm,
> + .vidioc_s_parm = viif_s_parm,
> +
> + .vidioc_enum_framesizes = viif_enum_framesizes,
> + .vidioc_enum_frameintervals = viif_enum_frameintervals,
> +
> + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> + .vidioc_querybuf = vb2_ioctl_querybuf,
> + .vidioc_qbuf = vb2_ioctl_qbuf,
> + .vidioc_expbuf = vb2_ioctl_expbuf,
> + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> + .vidioc_streamon = vb2_ioctl_streamon,
> + .vidioc_streamoff = vb2_ioctl_streamoff,
> +
> + .vidioc_log_status = v4l2_ctrl_log_status,
> + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
> + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
> +};
> +
> +/* --- File Operations --- */
> +static int viif_capture_open(struct file *file)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + int ret;
> +
> + ret = v4l2_fh_open(file);
> + if (ret)
> + return ret;
> +
> + return pm_runtime_resume_and_get(viif_dev->dev);
If pm_runtime_resume_and_get fails, then v4l2_fh_release needs
to be called.
> +}
> +
> +static int viif_capture_release(struct file *file)
> +{
> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> +
> + vb2_fop_release(file);
> + pm_runtime_put(viif_dev->dev);
> +
> + return 0;
> +}
> +
> +static const struct v4l2_file_operations viif_fops = {
> + .owner = THIS_MODULE,
> + .open = viif_capture_open,
> + .release = viif_capture_release,
> + .unlocked_ioctl = video_ioctl2,
> + .mmap = vb2_fop_mmap,
> + .poll = vb2_fop_poll,
> +};
> +
> +/* ----- media control callbacks ----- */
> +static int viif_capture_link_validate(struct media_link *link)
> +{
> + /* link validation at start-stream */
> + return 0;
> +}
> +
> +static const struct media_entity_operations viif_media_ops = {
> + .link_validate = viif_capture_link_validate,
> +};
> +
> +/* ----- attach ctrl callbacck handler ----- */
> +int visconti_viif_capture_register_ctrl_handlers(struct viif_device *viif_dev)
> +{
> + int ret;
> +
> + /* MAIN POST0: merge controls of ISP and CAPTURE0 */
> + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev0.ctrl_handler,
> + viif_dev->sd->v4l2_sd->ctrl_handler, NULL, true);
> + if (ret) {
> + dev_err(viif_dev->dev, "Failed to add sensor ctrl_handler");
> + return ret;
> + }
> + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev0.ctrl_handler,
> + &viif_dev->isp_subdev.ctrl_handler, NULL, true);
> + if (ret) {
> + dev_err(viif_dev->dev, "Failed to add isp subdev ctrl_handler");
> + return ret;
> + }
> +
> + /* MAIN POST1: merge controls of ISP and CAPTURE0 */
> + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev1.ctrl_handler,
> + viif_dev->sd->v4l2_sd->ctrl_handler, NULL, true);
> + if (ret) {
> + dev_err(viif_dev->dev, "Failed to add sensor ctrl_handler");
> + return ret;
> + }
> + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev1.ctrl_handler,
> + &viif_dev->isp_subdev.ctrl_handler, NULL, true);
> + if (ret) {
> + dev_err(viif_dev->dev, "Failed to add isp subdev ctrl_handler");
> + return ret;
> + }
> +
> + /* SUB: no control is exported */
> +
> + return 0;
> +}
> +
> +/* ----- register/remove capture device node ----- */
> +static int visconti_viif_capture_register_node(struct cap_dev *cap_dev)
> +{
> + struct viif_device *viif_dev = cap_dev->viif_dev;
> + struct v4l2_device *v4l2_dev = &viif_dev->v4l2_dev;
> + struct video_device *vdev = &cap_dev->vdev;
> + struct vb2_queue *q = &cap_dev->vb2_vq;
> + static const char *const node_name[] = {
> + "viif_capture_post0",
> + "viif_capture_post1",
> + "viif_capture_sub",
> + };
> + int ret;
> +
> + INIT_LIST_HEAD(&cap_dev->buf_queue);
> +
> + mutex_init(&cap_dev->vlock);
> +
> + /* Initialize vb2 queue. */
> + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
> + q->io_modes = VB2_DMABUF;
Why is there no VB2_MMAP?
> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> + q->ops = &viif_vb2_ops;
> + q->mem_ops = &vb2_dma_contig_memops;
> + q->drv_priv = cap_dev;
> + q->buf_struct_size = sizeof(struct viif_buffer);
> + q->min_buffers_needed = 2;
> + q->lock = &cap_dev->vlock;
> + q->dev = viif_dev->v4l2_dev.dev;
> +
> + ret = vb2_queue_init(q);
> + if (ret)
> + return ret;
> +
> + /* Register the video device. */
> + strscpy(vdev->name, node_name[cap_dev->pathid], sizeof(vdev->name));
> + vdev->v4l2_dev = v4l2_dev;
> + vdev->lock = &cap_dev->vlock;
> + vdev->queue = &cap_dev->vb2_vq;
> + vdev->ctrl_handler = NULL;
> + vdev->fops = &viif_fops;
> + vdev->ioctl_ops = &viif_ioctl_ops;
> + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;
> + vdev->device_caps |= V4L2_CAP_IO_MC;
> + vdev->entity.ops = &viif_media_ops;
> + vdev->release = video_device_release_empty;
> + video_set_drvdata(vdev, cap_dev);
> + vdev->vfl_dir = VFL_DIR_RX;
> + cap_dev->capture_pad.flags = MEDIA_PAD_FL_SINK;
> +
> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> + if (ret < 0) {
> + dev_err(v4l2_dev->dev, "video_register_device failed: %d\n", ret);
> + return ret;
> + }
> +
> + ret = media_entity_pads_init(&vdev->entity, 1, &cap_dev->capture_pad);
> + if (ret) {
> + video_unregister_device(vdev);
> + return ret;
> + }
> +
> + ret = v4l2_ctrl_handler_init(&cap_dev->ctrl_handler, 30);
> + if (ret)
> + return -ENOMEM;
> +
> + cap_dev->vdev.ctrl_handler = &cap_dev->ctrl_handler;
> +
> + return 0;
> +}
> +
> +int visconti_viif_capture_register(struct viif_device *viif_dev)
> +{
> + int ret;
> +
> + /* register MAIN POST0 (primary RGB output)*/
> + viif_dev->cap_dev0.pathid = CAPTURE_PATH_MAIN_POST0;
> + viif_dev->cap_dev0.viif_dev = viif_dev;
> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev0);
> + if (ret)
> + return ret;
> +
> + /* register MAIN POST1 (additional RGB output)*/
> + viif_dev->cap_dev1.pathid = CAPTURE_PATH_MAIN_POST1;
> + viif_dev->cap_dev1.viif_dev = viif_dev;
> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev1);
> + if (ret)
> + return ret;
> +
> + /* register SUB (RAW output) */
> + viif_dev->cap_dev2.pathid = CAPTURE_PATH_SUB;
> + viif_dev->cap_dev2.viif_dev = viif_dev;
> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev2);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void visconti_viif_capture_unregister_node(struct cap_dev *cap_dev)
> +{
> + media_entity_cleanup(&cap_dev->vdev.entity);
> + v4l2_ctrl_handler_free(&cap_dev->ctrl_handler);
> + vb2_video_unregister_device(&cap_dev->vdev);
> + mutex_destroy(&cap_dev->vlock);
> +}
> +
> +void visconti_viif_capture_unregister(struct viif_device *viif_dev)
> +{
> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev0);
> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev1);
> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev2);
> +}
> diff --git a/drivers/media/platform/visconti/viif_isp.c b/drivers/media/platform/visconti/viif_isp.c
> new file mode 100644
> index 00000000000..9314e6e8661
> --- /dev/null
> +++ b/drivers/media/platform/visconti/viif_isp.c
> @@ -0,0 +1,846 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-subdev.h>
> +
> +#include "viif.h"
> +
> +/* ----- supported MBUS formats ----- */
> +struct visconti_mbus_format {
> + unsigned int code;
> + unsigned int bpp;
> + int rgb_out;
> +} static visconti_mbus_formats[] = {
> + { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .rgb_out = 1 },
> + { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_UYVY10_1X20, .bpp = 20, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, .rgb_out = 1 },
> + { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, .rgb_out = 0 },
> + { .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, .rgb_out = 0 },
> +};
> +
> +static int viif_get_mbus_rgb_out(unsigned int mbus_code)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
> + if (visconti_mbus_formats[i].code == mbus_code)
> + return visconti_mbus_formats[i].rgb_out;
> +
> + /* YUV intermediate code by default */
> + return 0;
> +}
> +
> +static unsigned int viif_get_mbus_bpp(unsigned int mbus_code)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
> + if (visconti_mbus_formats[i].code == mbus_code)
> + return visconti_mbus_formats[i].bpp;
> +
> + /* default bpp value */
> + return 24;
> +}
> +
> +static bool viif_is_valid_mbus_code(unsigned int mbus_code)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
> + if (visconti_mbus_formats[i].code == mbus_code)
> + return true;
> + return false;
> +}
> +
> +/* ----- handling main processing path ----- */
> +static int viif_get_dv_timings(struct viif_device *viif_dev, struct v4l2_dv_timings *timings)
> +{
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + struct v4l2_subdev_pad_config pad_cfg;
> + struct v4l2_subdev_state pad_state = {
> + .pads = &pad_cfg,
> + };
> + struct v4l2_subdev_format format = {
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + .pad = 0,
> + };
> + struct v4l2_ctrl *ctrl;
> + int ret;
> +
> + /* some video I/F support dv_timings query */
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, g_dv_timings, timings);
> + if (ret == 0)
> + return 0;
> +
> + /* others: call some discrete APIs */
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, &pad_state, &format);
> + if (ret != 0)
> + return ret;
> +
> + timings->bt.width = format.format.width;
> + timings->bt.height = format.format.height;
> +
> + ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler, V4L2_CID_HBLANK);
> + if (!ctrl) {
> + dev_err(viif_dev->dev, "subdev: V4L2_CID_VBLANK error.\n");
> + return -EINVAL;
> + }
> + timings->bt.hsync = v4l2_ctrl_g_ctrl(ctrl);
> +
> + ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler, V4L2_CID_VBLANK);
> + if (!ctrl) {
> + dev_err(viif_dev->dev, "subdev: V4L2_CID_VBLANK error.\n");
> + return -EINVAL;
> + }
> + timings->bt.vsync = v4l2_ctrl_g_ctrl(ctrl);
> +
> + ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler, V4L2_CID_PIXEL_RATE);
> + if (!ctrl) {
> + dev_err(viif_dev->dev, "subdev: V4L2_CID_PIXEL_RATE error.\n");
> + return -EINVAL;
> + }
> + timings->bt.pixelclock = v4l2_ctrl_g_ctrl_int64(ctrl);
> +
> + return 0;
> +}
> +
> +int visconti_viif_isp_main_set_unit(struct viif_device *viif_dev)
> +{
> + unsigned int dt_image, color_type, rawpack, yuv_conv;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + struct hwd_viif_input_img in_img_main;
> + struct viif_l2_undist undist = { 0 };
> + struct v4l2_dv_timings timings;
> + struct v4l2_subdev_format fmt = {
> + .pad = 0,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + int mag_hactive = 1;
> + int ret = 0;
> +
> + ret = viif_get_dv_timings(viif_dev, &timings);
> + if (ret) {
> + dev_err(viif_dev->dev, "could not get timing information of subdev");
> + return -EINVAL;
> + }
> +
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, NULL, &fmt);
> + if (ret) {
> + dev_err(viif_dev->dev, "could not get pad information of subdev");
> + return -EINVAL;
> + }
> +
> + switch (fmt.format.code) {
> + case MEDIA_BUS_FMT_RGB888_1X24:
> + dt_image = VISCONTI_CSI2_DT_RGB888;
> + break;
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + dt_image = VISCONTI_CSI2_DT_YUV4228B;
> + break;
> + case MEDIA_BUS_FMT_UYVY10_1X20:
> + dt_image = VISCONTI_CSI2_DT_YUV42210B;
> + break;
> + case MEDIA_BUS_FMT_RGB565_1X16:
> + dt_image = VISCONTI_CSI2_DT_RGB565;
> + break;
> + case MEDIA_BUS_FMT_SBGGR8_1X8:
> + case MEDIA_BUS_FMT_SGBRG8_1X8:
> + case MEDIA_BUS_FMT_SGRBG8_1X8:
> + case MEDIA_BUS_FMT_SRGGB8_1X8:
> + dt_image = VISCONTI_CSI2_DT_RAW8;
> + break;
> + case MEDIA_BUS_FMT_SRGGB10_1X10:
> + case MEDIA_BUS_FMT_SGRBG10_1X10:
> + case MEDIA_BUS_FMT_SGBRG10_1X10:
> + case MEDIA_BUS_FMT_SBGGR10_1X10:
> + dt_image = VISCONTI_CSI2_DT_RAW10;
> + break;
> + case MEDIA_BUS_FMT_SRGGB12_1X12:
> + case MEDIA_BUS_FMT_SGRBG12_1X12:
> + case MEDIA_BUS_FMT_SGBRG12_1X12:
> + case MEDIA_BUS_FMT_SBGGR12_1X12:
> + dt_image = VISCONTI_CSI2_DT_RAW12;
> + break;
> + case MEDIA_BUS_FMT_SRGGB14_1X14:
> + case MEDIA_BUS_FMT_SGRBG14_1X14:
> + case MEDIA_BUS_FMT_SGBRG14_1X14:
> + case MEDIA_BUS_FMT_SBGGR14_1X14:
> + dt_image = VISCONTI_CSI2_DT_RAW14;
> + break;
> + default:
> + dt_image = VISCONTI_CSI2_DT_RGB888;
> + break;
> + }
> +
> + color_type = dt_image;
> +
> + if (color_type == VISCONTI_CSI2_DT_RAW8 || color_type == VISCONTI_CSI2_DT_RAW10 ||
> + color_type == VISCONTI_CSI2_DT_RAW12) {
> + rawpack = viif_dev->rawpack_mode;
> + if (rawpack != HWD_VIIF_RAWPACK_DISABLE)
> + mag_hactive = 2;
> + } else {
> + rawpack = HWD_VIIF_RAWPACK_DISABLE;
> + }
> +
> + if (color_type == VISCONTI_CSI2_DT_YUV4228B || color_type == VISCONTI_CSI2_DT_YUV42210B)
> + yuv_conv = HWD_VIIF_YUV_CONV_INTERPOLATION;
> + else
> + yuv_conv = HWD_VIIF_YUV_CONV_REPEAT;
> +
> + in_img_main.hactive_size = timings.bt.width;
> + in_img_main.vactive_size = timings.bt.height;
> + in_img_main.htotal_size = timings.bt.width * mag_hactive + timings.bt.hsync;
> + in_img_main.vtotal_size = timings.bt.height + timings.bt.vsync;
> + in_img_main.pixel_clock = timings.bt.pixelclock / 1000;
> + in_img_main.vbp_size = timings.bt.vsync - 5;
> +
> + in_img_main.interpolation_mode = HWD_VIIF_L1_INPUT_INTERPOLATION_LINE;
> + in_img_main.input_num = 1;
> + in_img_main.hobc_width = 0;
> + in_img_main.hobc_margin = 0;
> +
> + /* configuration of MAIN unit */
> + ret = hwd_viif_main_set_unit(viif_dev->hwd_res, dt_image, &in_img_main, color_type, rawpack,
> + yuv_conv);
> + if (ret) {
> + dev_err(viif_dev->dev, "main_set_unit error. %d\n", ret);
> + return ret;
> + }
> +
> + /* Enable regbuf */
> + hwd_viif_isp_set_regbuf_auto_transmission(viif_dev->hwd_res);
> +
> + /* L2 UNDIST Enable through mode as default */
> + undist.through_mode = HWD_VIIF_ENABLE;
> + undist.sensor_crop_ofs_h = 1 - in_img_main.hactive_size;
> + undist.sensor_crop_ofs_v = 1 - in_img_main.vactive_size;
> + undist.grid_node_num_h = 16;
> + undist.grid_node_num_v = 16;
> + ret = hwd_viif_l2_set_undist(viif_dev->hwd_res, &undist);
> + if (ret)
> + dev_err(viif_dev->dev, "l2_set_undist error. %d\n", ret);
> + return ret;
> +}
> +
> +static unsigned int dt_image_from_mbus_code(unsigned int mbus_code)
> +{
> + switch (mbus_code) {
> + case MEDIA_BUS_FMT_RGB888_1X24:
> + return VISCONTI_CSI2_DT_RGB888;
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + return VISCONTI_CSI2_DT_YUV4228B;
> + case MEDIA_BUS_FMT_UYVY10_1X20:
> + return VISCONTI_CSI2_DT_YUV42210B;
> + case MEDIA_BUS_FMT_RGB565_1X16:
> + return VISCONTI_CSI2_DT_RGB565;
> + case MEDIA_BUS_FMT_SBGGR8_1X8:
> + case MEDIA_BUS_FMT_SGBRG8_1X8:
> + case MEDIA_BUS_FMT_SGRBG8_1X8:
> + case MEDIA_BUS_FMT_SRGGB8_1X8:
> + return VISCONTI_CSI2_DT_RAW8;
> + case MEDIA_BUS_FMT_SRGGB10_1X10:
> + case MEDIA_BUS_FMT_SGRBG10_1X10:
> + case MEDIA_BUS_FMT_SGBRG10_1X10:
> + case MEDIA_BUS_FMT_SBGGR10_1X10:
> + return VISCONTI_CSI2_DT_RAW10;
> + case MEDIA_BUS_FMT_SRGGB12_1X12:
> + case MEDIA_BUS_FMT_SGRBG12_1X12:
> + case MEDIA_BUS_FMT_SGBRG12_1X12:
> + case MEDIA_BUS_FMT_SBGGR12_1X12:
> + return VISCONTI_CSI2_DT_RAW12;
> + case MEDIA_BUS_FMT_SRGGB14_1X14:
> + case MEDIA_BUS_FMT_SGRBG14_1X14:
> + case MEDIA_BUS_FMT_SGBRG14_1X14:
> + case MEDIA_BUS_FMT_SBGGR14_1X14:
> + return VISCONTI_CSI2_DT_RAW14;
> + default:
> + return VISCONTI_CSI2_DT_RGB888;
> + }
> +}
> +
> +int visconti_viif_isp_sub_set_unit(struct viif_device *viif_dev)
> +{
> + struct hwd_viif_input_img in_img_sub;
> + struct v4l2_dv_timings timings;
> + struct v4l2_subdev_format fmt = {
> + .pad = 0,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + unsigned int dt_image;
> + int ret;
> +
> + ret = viif_get_dv_timings(viif_dev, &timings);
> + if (ret)
> + return -EINVAL;
> +
> + ret = v4l2_subdev_call(viif_dev->sd->v4l2_sd, pad, get_fmt, NULL, &fmt);
> + if (ret) {
> + dev_err(viif_dev->dev, "could not get pad information of subdev");
> + return -EINVAL;
> + }
> +
> + dt_image = dt_image_from_mbus_code(fmt.format.code);
> +
> + in_img_sub.hactive_size = 0;
> + in_img_sub.vactive_size = timings.bt.height;
> + in_img_sub.htotal_size = timings.bt.width + timings.bt.hsync;
> + in_img_sub.vtotal_size = timings.bt.height + timings.bt.vsync;
> + in_img_sub.pixel_clock = timings.bt.pixelclock / 1000;
> + in_img_sub.vbp_size = timings.bt.vsync - 5;
> + in_img_sub.interpolation_mode = HWD_VIIF_L1_INPUT_INTERPOLATION_LINE;
> + in_img_sub.input_num = 1;
> + in_img_sub.hobc_width = 0;
> + in_img_sub.hobc_margin = 0;
> +
> + ret = hwd_viif_sub_set_unit(viif_dev->hwd_res, dt_image, &in_img_sub);
> + if (ret)
> + dev_err(viif_dev->dev, "sub_set_unit error. %d\n", ret);
> +
> + return ret;
> +};
> +
> +/* ----- handling CSI2RX hardware ----- */
> +static int viif_csi2rx_initialize(struct viif_device *viif_dev)
> +{
> + struct hwd_viif_csi2rx_line_err_target err_target = { 0 };
> + struct hwd_viif_csi2rx_irq_mask csi2rx_mask;
> + struct viif_subdev *viif_sd = viif_dev->sd;
> + struct v4l2_mbus_config cfg = { 0 };
> + struct v4l2_subdev_format fmt = {
> + .pad = 0,
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> + };
> + struct v4l2_dv_timings timings;
> + int num_lane, dphy_rate;
> + int ret;
> +
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_mbus_config, 0, &cfg);
> + if (ret) {
> + dev_dbg(viif_dev->dev, "subdev: g_mbus_config error. %d\n", ret);
> + num_lane = viif_sd->num_lane;
> + } else {
> + if (cfg.type != V4L2_MBUS_CSI2_DPHY)
> + return -EINVAL;
> + num_lane = cfg.bus.mipi_csi2.num_data_lanes;
> + }
> +
> + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, 0, &fmt);
> + if (ret)
> + return -EINVAL;
> +
> + ret = viif_get_dv_timings(viif_dev, &timings);
> + if (ret)
> + return -EINVAL;
> +
> + dphy_rate = (timings.bt.pixelclock / 1000) * viif_get_mbus_bpp(fmt.format.code) / num_lane;
> + dphy_rate = dphy_rate / 1000;
> +
> + /* check error for CH0: all supported DTs */
> + err_target.dt[0] = VISCONTI_CSI2_DT_RGB565;
> + err_target.dt[1] = VISCONTI_CSI2_DT_YUV4228B;
> + err_target.dt[2] = VISCONTI_CSI2_DT_YUV42210B;
> + err_target.dt[3] = VISCONTI_CSI2_DT_RGB888;
> + err_target.dt[4] = VISCONTI_CSI2_DT_RAW8;
> + err_target.dt[5] = VISCONTI_CSI2_DT_RAW10;
> + err_target.dt[6] = VISCONTI_CSI2_DT_RAW12;
> + err_target.dt[7] = VISCONTI_CSI2_DT_RAW14;
> +
> + /* Define errors to be masked */
> + csi2rx_mask.mask[0] = 0x0000000F; /*check all for PHY_FATAL*/
> + csi2rx_mask.mask[1] = 0x0001000F; /*check all for PKT_FATAL*/
> + csi2rx_mask.mask[2] = 0x000F0F0F; /*check all for FRAME_FATAL*/
> + csi2rx_mask.mask[3] = 0x000F000F; /*check all for PHY*/
> + csi2rx_mask.mask[4] = 0x000F000F; /*check all for PKT*/
> + csi2rx_mask.mask[5] = 0x00FF00FF; /*check all for LINE*/
> +
> + return hwd_viif_csi2rx_initialize(viif_dev->hwd_res, num_lane, HWD_VIIF_CSI2_DPHY_L0L1L2L3,
> + dphy_rate, HWD_VIIF_ENABLE, &err_target, &csi2rx_mask);
> +}
> +
> +static int viif_csi2rx_start(struct viif_device *viif_dev)
> +{
> + struct hwd_viif_csi2rx_packet packet = { 0 };
> + u32 vc_main = 0;
> + u32 vc_sub = 0;
> +
> + viif_dev->masked_gamma_path = 0U;
> +
> + return hwd_viif_csi2rx_start(viif_dev->hwd_res, vc_main, vc_sub, &packet);
> +}
> +
> +static int viif_csi2rx_stop(struct viif_device *viif_dev)
> +{
> + s32 ret;
> +
> + ret = hwd_viif_csi2rx_stop(viif_dev->hwd_res);
> + if (ret)
> + dev_err(viif_dev->dev, "csi2rx_stop error. %d\n", ret);
> +
> + hwd_viif_csi2rx_uninitialize(viif_dev->hwd_res);
> +
> + return ret;
> +}
> +
> +/* ----- subdevice video operations ----- */
> +static int visconti_viif_isp_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + int ret;
> +
> + if (enable) {
> + ret = viif_csi2rx_initialize(viif_dev);
> + if (ret)
> + return ret;
> + return viif_csi2rx_start(viif_dev);
> + } else {
> + return viif_csi2rx_stop(viif_dev);
> + }
> +}
> +
> +/* ----- subdevice pad operations ----- */
> +static int visconti_viif_isp_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + if (code->pad == 0) {
> + /* sink */
> + if (code->index > ARRAY_SIZE(visconti_mbus_formats) - 1)
> + return -EINVAL;
> + code->code = visconti_mbus_formats[code->index].code;
> + return 0;
> + }
> +
> + /* source */
> + if (code->index > 0)
> + return -EINVAL;
> + code->code = MEDIA_BUS_FMT_YUV8_1X24;
> + return 0;
> +}
> +
> +static struct v4l2_mbus_framefmt *visconti_viif_isp_get_pad_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + unsigned int pad, u32 which)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + struct v4l2_subdev_state state = {
> + .pads = viif_dev->isp_subdev.pad_cfg,
> + };
> +
> + if (which == V4L2_SUBDEV_FORMAT_TRY)
> + return v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state, pad);
> + else
> + return v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, &state, pad);
> +}
> +
> +static struct v4l2_rect *visconti_viif_isp_get_pad_crop(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + unsigned int pad, u32 which)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + struct v4l2_subdev_state state = {
> + .pads = viif_dev->isp_subdev.pad_cfg,
> + };
> +
> + if (which == V4L2_SUBDEV_FORMAT_TRY)
> + return v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, sd_state, pad);
> + else
> + return v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, &state, pad);
> +}
> +
> +static struct v4l2_rect *visconti_viif_isp_get_pad_compose(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + unsigned int pad, u32 which)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + struct v4l2_subdev_state state = {
> + .pads = viif_dev->isp_subdev.pad_cfg,
> + };
> +
> + if (which == V4L2_SUBDEV_FORMAT_TRY)
> + return v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, sd_state, pad);
> + else
> + return v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, &state, pad);
> +}
> +
> +static int visconti_viif_isp_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> +
> + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> + fmt->format = *visconti_viif_isp_get_pad_fmt(sd, sd_state, fmt->pad, fmt->which);
> + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> +
> + return 0;
> +}
> +
> +static void visconti_viif_isp_set_sink_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_mbus_framefmt *format, u32 which)
> +{
> + struct v4l2_mbus_framefmt *sink_fmt, *src0_fmt, *src1_fmt, *src2_fmt;
> +
> + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK, which);
> + src0_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SRC_PATH0, which);
> + src1_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SRC_PATH1, which);
> + src2_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SRC_PATH2, which);
> +
> + /* update mbus code only if it's available */
> + if (viif_is_valid_mbus_code(format->code))
> + sink_fmt->code = format->code;
> +
> + /* sink::mbus_code is derived from src::mbus_code */
> + if (viif_get_mbus_rgb_out(sink_fmt->code)) {
> + src0_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
> + src1_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
> + } else {
> + src0_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> + src1_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> + }
> +
> + /* SRC2 (RAW output) follows SINK format */
> + src2_fmt->code = format->code;
> + src2_fmt->width = format->width;
> + src2_fmt->height = format->height;
> +
> + /* size check */
> + sink_fmt->width = format->width;
> + sink_fmt->height = format->height;
> +
> + *format = *sink_fmt;
> +}
> +
> +static void visconti_viif_isp_set_src_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_mbus_framefmt *format, unsigned int pad,
> + u32 which)
> +{
> + struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
> + struct v4l2_rect *src_crop;
> +
> + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK,
> + V4L2_SUBDEV_FORMAT_ACTIVE);
> + src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, pad, which);
> + src_crop = visconti_viif_isp_get_pad_crop(sd, sd_state, pad, which);
> +
> + /* sink::mbus_code is derived from src::mbus_code */
> + if (viif_get_mbus_rgb_out(sink_fmt->code))
> + src_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
> + else
> + src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> +
> + /*size check*/
> + src_fmt->width = format->width;
> + src_fmt->height = format->height;
> +
> + /*update crop*/
> + src_crop->width = format->width;
> + src_crop->height = format->height;
> +
> + *format = *src_fmt;
> +}
> +
> +static void visconti_viif_isp_set_src_fmt_rawpath(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_mbus_framefmt *format,
> + unsigned int pad, u32 which)
> +{
> + struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
> +
> + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK,
> + V4L2_SUBDEV_FORMAT_ACTIVE);
> + src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, pad, which);
> +
> + /* RAWPATH SRC pad has just the same configuration as SINK pad */
> + src_fmt->code = sink_fmt->code;
> + src_fmt->width = sink_fmt->width;
> + src_fmt->height = sink_fmt->height;
> +
> + *format = *src_fmt;
> +}
> +
> +static int visconti_viif_isp_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_format *fmt)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> +
> + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> +
> + if (fmt->pad == VIIF_ISP_PAD_SINK)
> + visconti_viif_isp_set_sink_fmt(sd, sd_state, &fmt->format, fmt->which);
> + else if (fmt->pad == VIIF_ISP_PAD_SRC_PATH2)
> + visconti_viif_isp_set_src_fmt_rawpath(sd, sd_state, &fmt->format, fmt->pad,
> + fmt->which);
> + else
> + visconti_viif_isp_set_src_fmt(sd, sd_state, &fmt->format, fmt->pad, fmt->which);
> +
> + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> +
> + return 0;
> +}
> +
> +#define VISCONTI_VIIF_ISP_DEFAULT_WIDTH 1920
> +#define VISCONTI_VIIF_ISP_DEFAULT_HEIGHT 1080
> +#define VISCONTI_VIIF_MAX_COMPOSED_WIDTH 8190
> +#define VISCONTI_VIIF_MAX_COMPOSED_HEIGHT 4094
> +
> +static int visconti_viif_isp_init_config(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
> + struct v4l2_rect *src_crop, *sink_compose;
> +
> + sink_fmt =
> + v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state, VIIF_ISP_PAD_SINK);
> + sink_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + sink_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> + sink_fmt->field = V4L2_FIELD_NONE;
> + sink_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
> +
> + sink_compose =
> + v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, sd_state, VIIF_ISP_PAD_SINK);
> + sink_compose->top = 0;
> + sink_compose->left = 0;
> + sink_compose->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + sink_compose->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> +
> + src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state,
> + VIIF_ISP_PAD_SRC_PATH0);
> + src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> + src_fmt->field = V4L2_FIELD_NONE;
> + src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> +
> + src_crop = v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, sd_state,
> + VIIF_ISP_PAD_SRC_PATH0);
> + src_crop->top = 0;
> + src_crop->left = 0;
> + src_crop->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + src_crop->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> +
> + src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state,
> + VIIF_ISP_PAD_SRC_PATH1);
> + src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> + src_fmt->field = V4L2_FIELD_NONE;
> + src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> +
> + src_crop = v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd, sd_state,
> + VIIF_ISP_PAD_SRC_PATH1);
> + src_crop->top = 0;
> + src_crop->left = 0;
> + src_crop->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + src_crop->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> +
> + src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd, sd_state,
> + VIIF_ISP_PAD_SRC_PATH2);
> + src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> + src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> + src_fmt->field = V4L2_FIELD_NONE;
> + src_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
> +
> + return 0;
> +}
> +
> +static int visconti_viif_isp_get_selection(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_selection *sel)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + struct v4l2_mbus_framefmt *sink_fmt;
> + int ret = -EINVAL;
> +
> + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> + if (sel->pad == VIIF_ISP_PAD_SINK) {
> + /* SINK PAD */
> + switch (sel->target) {
> + case V4L2_SEL_TGT_CROP:
> + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, VIIF_ISP_PAD_SINK,
> + sel->which);
> + sel->r.top = 0;
> + sel->r.left = 0;
> + sel->r.width = sink_fmt->width;
> + sel->r.height = sink_fmt->height;
> + ret = 0;
> + break;
> + case V4L2_SEL_TGT_COMPOSE:
> + sel->r = *visconti_viif_isp_get_pad_compose(sd, sd_state, VIIF_ISP_PAD_SINK,
> + sel->which);
> + ret = 0;
> + break;
> + case V4L2_SEL_TGT_COMPOSE_BOUNDS:
> + /* fixed value */
> + sel->r.top = 0;
> + sel->r.left = 0;
> + sel->r.width = VISCONTI_VIIF_MAX_COMPOSED_WIDTH;
> + sel->r.height = VISCONTI_VIIF_MAX_COMPOSED_HEIGHT;
> + ret = 0;
> + break;
> + }
> + } else if ((sel->pad == VIIF_ISP_PAD_SRC_PATH0) || (sel->pad == VIIF_ISP_PAD_SRC_PATH1)) {
> + /* SRC PAD */
> + switch (sel->target) {
> + case V4L2_SEL_TGT_CROP:
> + sel->r =
> + *visconti_viif_isp_get_pad_crop(sd, sd_state, sel->pad, sel->which);
> + ret = 0;
> + break;
> + }
> + }
> + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> +
> + return ret;
> +}
> +
> +static int visconti_viif_isp_set_selection(struct v4l2_subdev *sd,
> + struct v4l2_subdev_state *sd_state,
> + struct v4l2_subdev_selection *sel)
> +{
> + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> + struct v4l2_mbus_framefmt *src_fmt;
> + struct v4l2_rect *rect, *rect_compose;
> + int ret = -EINVAL;
> +
> + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> + /* only source::selection::crop is writable */
> + if (sel->pad == VIIF_ISP_PAD_SRC_PATH0 || sel->pad == VIIF_ISP_PAD_SRC_PATH1) {
> + switch (sel->target) {
> + case V4L2_SEL_TGT_CROP: {
> + /* check if new SRC::CROP is inside SINK::COMPOSE */
> + rect_compose = visconti_viif_isp_get_pad_compose(
> + sd, sd_state, VIIF_ISP_PAD_SINK, sel->which);
> + if (sel->r.top < rect_compose->top || sel->r.left < rect_compose->left ||
> + (sel->r.top + sel->r.height) >
> + (rect_compose->top + rect_compose->height) ||
> + (sel->r.left + sel->r.width) >
> + (rect_compose->left + rect_compose->width)) {
> + break;
> + }
> +
> + rect = visconti_viif_isp_get_pad_crop(sd, sd_state, sel->pad, sel->which);
> + *rect = sel->r;
> +
> + /* update SRC::FMT along with SRC::CROP */
> + src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, sel->pad, sel->which);
> + src_fmt->width = sel->r.width;
> + src_fmt->height = sel->r.height;
> + ret = 0;
> + break;
> + }
> + }
> + }
> + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> +
> + return ret;
> +}
> +
> +void visconti_viif_isp_set_compose_rect(struct viif_device *viif_dev,
> + struct viif_l2_roi_config *roi)
> +{
> + struct v4l2_rect *rect;
> +
> + rect = visconti_viif_isp_get_pad_compose(&viif_dev->isp_subdev.sd, NULL, VIIF_ISP_PAD_SINK,
> + V4L2_SUBDEV_FORMAT_ACTIVE);
> + rect->top = 0;
> + rect->left = 0;
> + rect->width = roi->corrected_hsize[0];
> + rect->height = roi->corrected_vsize[0];
> +}
> +
> +static const struct media_entity_operations visconti_viif_isp_media_ops = {
> + .link_validate = v4l2_subdev_link_validate,
> +};
> +
> +static const struct v4l2_subdev_pad_ops visconti_viif_isp_pad_ops = {
> + .enum_mbus_code = visconti_viif_isp_enum_mbus_code,
> + .get_selection = visconti_viif_isp_get_selection,
> + .set_selection = visconti_viif_isp_set_selection,
> + .init_cfg = visconti_viif_isp_init_config,
> + .get_fmt = visconti_viif_isp_get_fmt,
> + .set_fmt = visconti_viif_isp_set_fmt,
> + .link_validate = v4l2_subdev_link_validate_default,
> +};
> +
> +static const struct v4l2_subdev_video_ops visconti_viif_isp_video_ops = {
> + .s_stream = visconti_viif_isp_s_stream,
> +};
> +
> +static const struct v4l2_subdev_ops visconti_viif_isp_ops = {
> + .video = &visconti_viif_isp_video_ops,
> + .pad = &visconti_viif_isp_pad_ops,
> +};
> +
> +/* ----- register/remove isp subdevice node ----- */
> +int visconti_viif_isp_register(struct viif_device *viif_dev)
> +{
> + struct v4l2_subdev_state state = {
> + .pads = viif_dev->isp_subdev.pad_cfg,
> + };
> + struct media_pad *pads = viif_dev->isp_subdev.pads;
> + struct v4l2_subdev *sd = &viif_dev->isp_subdev.sd;
> + int ret;
> +
> + viif_dev->isp_subdev.viif_dev = viif_dev;
> +
> + v4l2_subdev_init(sd, &visconti_viif_isp_ops);
> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> + sd->entity.ops = &visconti_viif_isp_media_ops;
> + sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
> + sd->owner = THIS_MODULE;
> + strscpy(sd->name, "visconti-viif:isp", sizeof(sd->name));
> +
> + pads[0].flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
> + pads[1].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
> + pads[2].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
> + pads[3].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
> +
> + mutex_init(&viif_dev->isp_subdev.ops_lock);
> +
> + ret = media_entity_pads_init(&sd->entity, 4, pads);
> + if (ret) {
> + dev_err(viif_dev->dev, "Failed on media_entity_pads_init\n");
> + return ret;
> + }
> +
> + ret = v4l2_device_register_subdev(&viif_dev->v4l2_dev, sd);
> + if (ret) {
> + dev_err(viif_dev->dev, "Failed to resize ISP subdev\n");
> + goto err_cleanup_media_entity;
> + }
> +
> + visconti_viif_isp_init_config(sd, &state);
> +
> + return 0;
> +
> +err_cleanup_media_entity:
> + media_entity_cleanup(&sd->entity);
> + return ret;
> +}
> +
> +void visconti_viif_isp_unregister(struct viif_device *viif_dev)
> +{
> + v4l2_device_unregister_subdev(&viif_dev->isp_subdev.sd);
> + media_entity_cleanup(&viif_dev->isp_subdev.sd.entity);
> +}
Regards,
Hans
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-17 11:47 ` Hans Verkuil
@ 2023-01-18 1:04 ` Laurent Pinchart
2023-01-25 10:20 ` yuji2.ishikawa
2023-01-26 1:25 ` yuji2.ishikawa
1 sibling, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-18 1:04 UTC (permalink / raw)
To: Hans Verkuil
Cc: Yuji Ishikawa, Mauro Carvalho Chehab, Nobuhiro Iwamatsu,
Rob Herring, Krzysztof Kozlowski, Rafael J . Wysocki, Mark Brown,
linux-media, linux-arm-kernel, linux-kernel, devicetree
Hello,
On Tue, Jan 17, 2023 at 12:47:10PM +0100, Hans Verkuil wrote:
> More comments below:
>
> On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > The interface device includes CSI2 Receiver,
> > frame grabber, video DMAC and image signal processor.
> > This patch provides the user interface layer.
> >
> > A driver instance provides three /dev/videoX device files;
> > one for RGB image capture, another one for optional RGB capture
> > with different parameters and the last one for RAW capture.
> >
> > Through the device files, the driver provides streaming (DMA-BUF) interface.
> > A userland application should feed DMA-BUF instances for capture buffers.
> >
> > The driver is based on media controller framework.
> > Its operations are roughly mapped to two subdrivers;
> > one for ISP and CSI2 receiver (yields 1 instance),
> > the other for capture (yields 3 instances for each capture mode).
> >
> > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > ---
> > Changelog v2:
> > - Resend v1 because a patch exceeds size limit.
> >
> > Changelog v3:
> > - Adapted to media control framework
> > - Introduced ISP subdevice, capture device
> > - Remove private IOCTLs and add vendor specific V4L2 controls
> > - Change function name avoiding camelcase and uppercase letters
> >
> > Changelog v4:
> > - Split patches because the v3 patch exceeds size limit
> > - Stop using ID number to identify driver instance:
> > - Use dynamically allocated structure to hold HW specific context,
> > instead of static one.
> > - Call HW layer functions with the context structure instead of ID number
> > - Use pm_runtime to trigger initialization of HW
> > along with open/close of device files.
> >
> > Changelog v5:
> > - Fix coding style problems in viif.c
> > ---
> > drivers/media/platform/visconti/Makefile | 1 +
> > drivers/media/platform/visconti/viif.c | 545 ++++++++
> > drivers/media/platform/visconti/viif.h | 203 +++
> > .../media/platform/visconti/viif_capture.c | 1201 +++++++++++++++++
> > drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> > 5 files changed, 2796 insertions(+)
> > create mode 100644 drivers/media/platform/visconti/viif.c
> > create mode 100644 drivers/media/platform/visconti/viif.h
> > create mode 100644 drivers/media/platform/visconti/viif_capture.c
> > create mode 100644 drivers/media/platform/visconti/viif_isp.c
[snip]
> > +static int viif_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid, edid);
> > +}
>
> Has this driver been tested with an HDMI receiver? If not, then I would recommend
> dropping support for it until you actually can test with such hardware.
>
> The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces, it's not meant
> for CSI and similar interfaces.
More than that, for MC-based drivers, the video node should *never*
forward ioctls to a connected subdev. The *only* valid calls to
v4l2_subdev_call() in this file are
- to video.s_stream() in the start and stop streaming handler
- to pad.g_fmt() when starting streaming to validate that the connected
subdev outputs a format compatible with the format set on the video
capture device
That's it, nothing else, all other calls to v4l2_subdev_call() must be
dropped from the implementation of the video_device.
[snip]
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-18 1:04 ` Laurent Pinchart
@ 2023-01-25 10:20 ` yuji2.ishikawa
2023-01-26 20:49 ` Laurent Pinchart
0 siblings, 1 reply; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-25 10:20 UTC (permalink / raw)
To: laurent.pinchart, hverkuil
Cc: mchehab, nobuhiro1.iwamatsu, robh+dt, krzysztof.kozlowski+dt,
rafael.j.wysocki, broonie, linux-media, linux-arm-kernel,
linux-kernel, devicetree
Hello,
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Wednesday, January 18, 2023 10:04 AM
> To: Hans Verkuil <hverkuil@xs4all.nl>
> Cc: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; Mauro Carvalho Chehab
> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>;
> linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver user interace
>
> Hello,
>
> On Tue, Jan 17, 2023 at 12:47:10PM +0100, Hans Verkuil wrote:
> > More comments below:
> >
> > On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > > The interface device includes CSI2 Receiver, frame grabber, video
> > > DMAC and image signal processor.
> > > This patch provides the user interface layer.
> > >
> > > A driver instance provides three /dev/videoX device files; one for
> > > RGB image capture, another one for optional RGB capture with
> > > different parameters and the last one for RAW capture.
> > >
> > > Through the device files, the driver provides streaming (DMA-BUF)
> interface.
> > > A userland application should feed DMA-BUF instances for capture buffers.
> > >
> > > The driver is based on media controller framework.
> > > Its operations are roughly mapped to two subdrivers; one for ISP and
> > > CSI2 receiver (yields 1 instance), the other for capture (yields 3
> > > instances for each capture mode).
> > >
> > > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > > ---
> > > Changelog v2:
> > > - Resend v1 because a patch exceeds size limit.
> > >
> > > Changelog v3:
> > > - Adapted to media control framework
> > > - Introduced ISP subdevice, capture device
> > > - Remove private IOCTLs and add vendor specific V4L2 controls
> > > - Change function name avoiding camelcase and uppercase letters
> > >
> > > Changelog v4:
> > > - Split patches because the v3 patch exceeds size limit
> > > - Stop using ID number to identify driver instance:
> > > - Use dynamically allocated structure to hold HW specific context,
> > > instead of static one.
> > > - Call HW layer functions with the context structure instead of ID
> > > number
> > > - Use pm_runtime to trigger initialization of HW
> > > along with open/close of device files.
> > >
> > > Changelog v5:
> > > - Fix coding style problems in viif.c
> > > ---
> > > drivers/media/platform/visconti/Makefile | 1 +
> > > drivers/media/platform/visconti/viif.c | 545 ++++++++
> > > drivers/media/platform/visconti/viif.h | 203 +++
> > > .../media/platform/visconti/viif_capture.c | 1201
> +++++++++++++++++
> > > drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> > > 5 files changed, 2796 insertions(+) create mode 100644
> > > drivers/media/platform/visconti/viif.c
> > > create mode 100644 drivers/media/platform/visconti/viif.h
> > > create mode 100644 drivers/media/platform/visconti/viif_capture.c
> > > create mode 100644 drivers/media/platform/visconti/viif_isp.c
>
> [snip]
>
> > > +static int viif_s_edid(struct file *file, void *fh, struct
> > > +v4l2_edid *edid) {
> > > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > > + struct viif_subdev *viif_sd = viif_dev->sd;
> > > +
> > > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid, edid); }
> >
> > Has this driver been tested with an HDMI receiver? If not, then I
> > would recommend dropping support for it until you actually can test with such
> hardware.
> >
> > The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces, it's
> > not meant for CSI and similar interfaces.
>
> More than that, for MC-based drivers, the video node should *never* forward
> ioctls to a connected subdev. The *only* valid calls to
> v4l2_subdev_call() in this file are
>
> - to video.s_stream() in the start and stop streaming handler
>
> - to pad.g_fmt() when starting streaming to validate that the connected
> subdev outputs a format compatible with the format set on the video
> capture device
>
> That's it, nothing else, all other calls to v4l2_subdev_call() must be dropped from
> the implementation of the video_device.
>
Thank you for your comment. I understand the restriction.
I'll remove following functions corresponding to ioctls.
* viif_enum_input
* viif_g_selection
* viif_s_selection
* viif_dv_timings_cap
* viif_enum_dv_timings
* viif_g_dv_timings
* viif_s_dv_timings
* viif_query_dv_timings
* viif_g_edid
* viif_s_edid
* viif_g_parm
* viif_s_parm
* viif_enum_framesizes
* viif_enum_frameintervals
I can call subdevices directly if I need. Is it a correct understanding?
As for viif_try_fmt_vid_cap and viif_s_fmt_vid_cap,
I'll remove pad.g_fmt() call which is for checking pixel format.
The check will be moved to viif_capture_link_validate() validation routine triggered by a start streaming event.
> [snip]
>
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-25 10:20 ` yuji2.ishikawa
@ 2023-01-26 20:49 ` Laurent Pinchart
2023-02-02 4:52 ` yuji2.ishikawa
0 siblings, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-26 20:49 UTC (permalink / raw)
To: yuji2.ishikawa
Cc: hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Ishikawa-san,
On Wed, Jan 25, 2023 at 10:20:27AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> On Wednesday, January 18, 2023 10:04 AM, Laurent Pinchart wrote:
> > On Tue, Jan 17, 2023 at 12:47:10PM +0100, Hans Verkuil wrote:
> > > On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > > > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > > > The interface device includes CSI2 Receiver, frame grabber, video
> > > > DMAC and image signal processor.
> > > > This patch provides the user interface layer.
> > > >
> > > > A driver instance provides three /dev/videoX device files; one for
> > > > RGB image capture, another one for optional RGB capture with
> > > > different parameters and the last one for RAW capture.
> > > >
> > > > Through the device files, the driver provides streaming (DMA-BUF) interface.
> > > > A userland application should feed DMA-BUF instances for capture buffers.
> > > >
> > > > The driver is based on media controller framework.
> > > > Its operations are roughly mapped to two subdrivers; one for ISP and
> > > > CSI2 receiver (yields 1 instance), the other for capture (yields 3
> > > > instances for each capture mode).
> > > >
> > > > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > > > ---
> > > > Changelog v2:
> > > > - Resend v1 because a patch exceeds size limit.
> > > >
> > > > Changelog v3:
> > > > - Adapted to media control framework
> > > > - Introduced ISP subdevice, capture device
> > > > - Remove private IOCTLs and add vendor specific V4L2 controls
> > > > - Change function name avoiding camelcase and uppercase letters
> > > >
> > > > Changelog v4:
> > > > - Split patches because the v3 patch exceeds size limit
> > > > - Stop using ID number to identify driver instance:
> > > > - Use dynamically allocated structure to hold HW specific context,
> > > > instead of static one.
> > > > - Call HW layer functions with the context structure instead of ID
> > > > number
> > > > - Use pm_runtime to trigger initialization of HW
> > > > along with open/close of device files.
> > > >
> > > > Changelog v5:
> > > > - Fix coding style problems in viif.c
> > > > ---
> > > > drivers/media/platform/visconti/Makefile | 1 +
> > > > drivers/media/platform/visconti/viif.c | 545 ++++++++
> > > > drivers/media/platform/visconti/viif.h | 203 +++
> > > > .../media/platform/visconti/viif_capture.c | 1201 +++++++++++++++++
> > > > drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> > > > 5 files changed, 2796 insertions(+) create mode 100644
> > > > drivers/media/platform/visconti/viif.c
> > > > create mode 100644 drivers/media/platform/visconti/viif.h
> > > > create mode 100644 drivers/media/platform/visconti/viif_capture.c
> > > > create mode 100644 drivers/media/platform/visconti/viif_isp.c
> >
> > [snip]
> >
> > > > +static int viif_s_edid(struct file *file, void *fh, struct
> > > > +v4l2_edid *edid) {
> > > > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > > > + struct viif_subdev *viif_sd = viif_dev->sd;
> > > > +
> > > > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid, edid); }
> > >
> > > Has this driver been tested with an HDMI receiver? If not, then I
> > > would recommend dropping support for it until you actually can
> > > test with such hardware.
> > >
> > > The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces, it's
> > > not meant for CSI and similar interfaces.
> >
> > More than that, for MC-based drivers, the video node should *never* forward
> > ioctls to a connected subdev. The *only* valid calls to
> > v4l2_subdev_call() in this file are
> >
> > - to video.s_stream() in the start and stop streaming handler
> >
> > - to pad.g_fmt() when starting streaming to validate that the connected
> > subdev outputs a format compatible with the format set on the video
> > capture device
> >
> > That's it, nothing else, all other calls to v4l2_subdev_call() must be dropped from
> > the implementation of the video_device.
>
> Thank you for your comment. I understand the restriction.
> I'll remove following functions corresponding to ioctls.
>
> * viif_enum_input
> * viif_g_selection
> * viif_s_selection
> * viif_dv_timings_cap
> * viif_enum_dv_timings
> * viif_g_dv_timings
> * viif_s_dv_timings
> * viif_query_dv_timings
> * viif_g_edid
> * viif_s_edid
> * viif_g_parm
> * viif_s_parm
> * viif_enum_framesizes
This one should stay, it should report the minimum and maximum sizes
supported by the video nodes, regardless of the configuration of the
connected subdev.
> * viif_enum_frameintervals
>
> I can call subdevices directly if I need. Is it a correct understanding?
what do you mean exactly by calling subdevices directly ?
> As for viif_try_fmt_vid_cap and viif_s_fmt_vid_cap,
> I'll remove pad.g_fmt() call which is for checking pixel format.
> The check will be moved to viif_capture_link_validate() validation
> routine triggered by a start streaming event.
>
> > [snip]
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-26 20:49 ` Laurent Pinchart
@ 2023-02-02 4:52 ` yuji2.ishikawa
2023-02-02 7:58 ` Laurent Pinchart
0 siblings, 1 reply; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-02 4:52 UTC (permalink / raw)
To: laurent.pinchart
Cc: hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Laurent,
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Friday, January 27, 2023 5:49 AM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>
> Cc: hverkuil@xs4all.nl; mchehab@kernel.org; iwamatsu nobuhiro(岩松 信洋 □
> ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; rafael.j.wysocki@intel.com;
> broonie@kernel.org; linux-media@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver user interace
>
> Hello Ishikawa-san,
>
> On Wed, Jan 25, 2023 at 10:20:27AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> > On Wednesday, January 18, 2023 10:04 AM, Laurent Pinchart wrote:
> > > On Tue, Jan 17, 2023 at 12:47:10PM +0100, Hans Verkuil wrote:
> > > > On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > > > > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > > > > The interface device includes CSI2 Receiver, frame grabber,
> > > > > video DMAC and image signal processor.
> > > > > This patch provides the user interface layer.
> > > > >
> > > > > A driver instance provides three /dev/videoX device files; one
> > > > > for RGB image capture, another one for optional RGB capture with
> > > > > different parameters and the last one for RAW capture.
> > > > >
> > > > > Through the device files, the driver provides streaming (DMA-BUF)
> interface.
> > > > > A userland application should feed DMA-BUF instances for capture
> buffers.
> > > > >
> > > > > The driver is based on media controller framework.
> > > > > Its operations are roughly mapped to two subdrivers; one for ISP
> > > > > and
> > > > > CSI2 receiver (yields 1 instance), the other for capture (yields
> > > > > 3 instances for each capture mode).
> > > > >
> > > > > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > > > > ---
> > > > > Changelog v2:
> > > > > - Resend v1 because a patch exceeds size limit.
> > > > >
> > > > > Changelog v3:
> > > > > - Adapted to media control framework
> > > > > - Introduced ISP subdevice, capture device
> > > > > - Remove private IOCTLs and add vendor specific V4L2 controls
> > > > > - Change function name avoiding camelcase and uppercase letters
> > > > >
> > > > > Changelog v4:
> > > > > - Split patches because the v3 patch exceeds size limit
> > > > > - Stop using ID number to identify driver instance:
> > > > > - Use dynamically allocated structure to hold HW specific context,
> > > > > instead of static one.
> > > > > - Call HW layer functions with the context structure instead
> > > > > of ID number
> > > > > - Use pm_runtime to trigger initialization of HW
> > > > > along with open/close of device files.
> > > > >
> > > > > Changelog v5:
> > > > > - Fix coding style problems in viif.c
> > > > > ---
> > > > > drivers/media/platform/visconti/Makefile | 1 +
> > > > > drivers/media/platform/visconti/viif.c | 545 ++++++++
> > > > > drivers/media/platform/visconti/viif.h | 203 +++
> > > > > .../media/platform/visconti/viif_capture.c | 1201
> +++++++++++++++++
> > > > > drivers/media/platform/visconti/viif_isp.c | 846
> ++++++++++++
> > > > > 5 files changed, 2796 insertions(+) create mode 100644
> > > > > drivers/media/platform/visconti/viif.c
> > > > > create mode 100644 drivers/media/platform/visconti/viif.h
> > > > > create mode 100644
> > > > > drivers/media/platform/visconti/viif_capture.c
> > > > > create mode 100644 drivers/media/platform/visconti/viif_isp.c
> > >
> > > [snip]
> > >
> > > > > +static int viif_s_edid(struct file *file, void *fh, struct
> > > > > +v4l2_edid *edid) {
> > > > > + struct viif_device *viif_dev =
> video_drvdata_to_capdev(file)->viif_dev;
> > > > > + struct viif_subdev *viif_sd = viif_dev->sd;
> > > > > +
> > > > > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid,
> > > > > +edid); }
> > > >
> > > > Has this driver been tested with an HDMI receiver? If not, then I
> > > > would recommend dropping support for it until you actually can
> > > > test with such hardware.
> > > >
> > > > The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces,
> > > > it's not meant for CSI and similar interfaces.
> > >
> > > More than that, for MC-based drivers, the video node should *never*
> > > forward ioctls to a connected subdev. The *only* valid calls to
> > > v4l2_subdev_call() in this file are
> > >
> > > - to video.s_stream() in the start and stop streaming handler
> > >
> > > - to pad.g_fmt() when starting streaming to validate that the connected
> > > subdev outputs a format compatible with the format set on the video
> > > capture device
> > >
> > > That's it, nothing else, all other calls to v4l2_subdev_call() must
> > > be dropped from the implementation of the video_device.
> >
> > Thank you for your comment. I understand the restriction.
> > I'll remove following functions corresponding to ioctls.
> >
> > * viif_enum_input
> > * viif_g_selection
> > * viif_s_selection
> > * viif_dv_timings_cap
> > * viif_enum_dv_timings
> > * viif_g_dv_timings
> > * viif_s_dv_timings
> > * viif_query_dv_timings
> > * viif_g_edid
> > * viif_s_edid
> > * viif_g_parm
> > * viif_s_parm
> > * viif_enum_framesizes
>
> This one should stay, it should report the minimum and maximum sizes
> supported by the video nodes, regardless of the configuration of the connected
> subdev.
I'll keep it.
> > * viif_enum_frameintervals
> >
> > I can call subdevices directly if I need. Is it a correct understanding?
>
> what do you mean exactly by calling subdevices directly ?
I meant userland can configure subdevices with /dev/v4l-subdev.
> > As for viif_try_fmt_vid_cap and viif_s_fmt_vid_cap, I'll remove
> > pad.g_fmt() call which is for checking pixel format.
> > The check will be moved to viif_capture_link_validate() validation
> > routine triggered by a start streaming event.
> >
> > > [snip]
>
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-02-02 4:52 ` yuji2.ishikawa
@ 2023-02-02 7:58 ` Laurent Pinchart
0 siblings, 0 replies; 42+ messages in thread
From: Laurent Pinchart @ 2023-02-02 7:58 UTC (permalink / raw)
To: yuji2.ishikawa
Cc: hverkuil, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
Hello Ishikawa-san,
On Thu, Feb 02, 2023 at 04:52:56AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> On Friday, January 27, 2023 5:49 AM, Laurent Pinchart wrote:
> > On Wed, Jan 25, 2023 at 10:20:27AM +0000, yuji2.ishikawa@toshiba.co.jp wrote:
> > > On Wednesday, January 18, 2023 10:04 AM, Laurent Pinchart wrote:
> > > > On Tue, Jan 17, 2023 at 12:47:10PM +0100, Hans Verkuil wrote:
> > > > > On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > > > > > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > > > > > The interface device includes CSI2 Receiver, frame grabber,
> > > > > > video DMAC and image signal processor.
> > > > > > This patch provides the user interface layer.
> > > > > >
> > > > > > A driver instance provides three /dev/videoX device files; one
> > > > > > for RGB image capture, another one for optional RGB capture with
> > > > > > different parameters and the last one for RAW capture.
> > > > > >
> > > > > > Through the device files, the driver provides streaming (DMA-BUF) interface.
> > > > > > A userland application should feed DMA-BUF instances for capture buffers.
> > > > > >
> > > > > > The driver is based on media controller framework.
> > > > > > Its operations are roughly mapped to two subdrivers; one for ISP
> > > > > > and
> > > > > > CSI2 receiver (yields 1 instance), the other for capture (yields
> > > > > > 3 instances for each capture mode).
> > > > > >
> > > > > > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > > > > > ---
> > > > > > Changelog v2:
> > > > > > - Resend v1 because a patch exceeds size limit.
> > > > > >
> > > > > > Changelog v3:
> > > > > > - Adapted to media control framework
> > > > > > - Introduced ISP subdevice, capture device
> > > > > > - Remove private IOCTLs and add vendor specific V4L2 controls
> > > > > > - Change function name avoiding camelcase and uppercase letters
> > > > > >
> > > > > > Changelog v4:
> > > > > > - Split patches because the v3 patch exceeds size limit
> > > > > > - Stop using ID number to identify driver instance:
> > > > > > - Use dynamically allocated structure to hold HW specific context,
> > > > > > instead of static one.
> > > > > > - Call HW layer functions with the context structure instead of ID number
> > > > > > - Use pm_runtime to trigger initialization of HW
> > > > > > along with open/close of device files.
> > > > > >
> > > > > > Changelog v5:
> > > > > > - Fix coding style problems in viif.c
> > > > > > ---
> > > > > > drivers/media/platform/visconti/Makefile | 1 +
> > > > > > drivers/media/platform/visconti/viif.c | 545 ++++++++
> > > > > > drivers/media/platform/visconti/viif.h | 203 +++
> > > > > > .../media/platform/visconti/viif_capture.c | 1201 +++++++++++++++++
> > > > > > drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> > > > > > 5 files changed, 2796 insertions(+) create mode 100644
> > > > > > drivers/media/platform/visconti/viif.c
> > > > > > create mode 100644 drivers/media/platform/visconti/viif.h
> > > > > > create mode 100644
> > > > > > drivers/media/platform/visconti/viif_capture.c
> > > > > > create mode 100644 drivers/media/platform/visconti/viif_isp.c
> > > >
> > > > [snip]
> > > >
> > > > > > +static int viif_s_edid(struct file *file, void *fh, struct
> > > > > > +v4l2_edid *edid) {
> > > > > > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > > > > > + struct viif_subdev *viif_sd = viif_dev->sd;
> > > > > > +
> > > > > > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid,
> > > > > > +edid); }
> > > > >
> > > > > Has this driver been tested with an HDMI receiver? If not, then I
> > > > > would recommend dropping support for it until you actually can
> > > > > test with such hardware.
> > > > >
> > > > > The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces,
> > > > > it's not meant for CSI and similar interfaces.
> > > >
> > > > More than that, for MC-based drivers, the video node should *never*
> > > > forward ioctls to a connected subdev. The *only* valid calls to
> > > > v4l2_subdev_call() in this file are
> > > >
> > > > - to video.s_stream() in the start and stop streaming handler
> > > >
> > > > - to pad.g_fmt() when starting streaming to validate that the connected
> > > > subdev outputs a format compatible with the format set on the video
> > > > capture device
> > > >
> > > > That's it, nothing else, all other calls to v4l2_subdev_call() must
> > > > be dropped from the implementation of the video_device.
> > >
> > > Thank you for your comment. I understand the restriction.
> > > I'll remove following functions corresponding to ioctls.
> > >
> > > * viif_enum_input
> > > * viif_g_selection
> > > * viif_s_selection
> > > * viif_dv_timings_cap
> > > * viif_enum_dv_timings
> > > * viif_g_dv_timings
> > > * viif_s_dv_timings
> > > * viif_query_dv_timings
> > > * viif_g_edid
> > > * viif_s_edid
> > > * viif_g_parm
> > > * viif_s_parm
> > > * viif_enum_framesizes
> >
> > This one should stay, it should report the minimum and maximum sizes
> > supported by the video nodes, regardless of the configuration of the connected
> > subdev.
>
> I'll keep it.
>
> > > * viif_enum_frameintervals
> > >
> > > I can call subdevices directly if I need. Is it a correct understanding?
> >
> > what do you mean exactly by calling subdevices directly ?
>
> I meant userland can configure subdevices with /dev/v4l-subdev.
Ah yes absolutely, userspace will configure the subdevs.
> > > As for viif_try_fmt_vid_cap and viif_s_fmt_vid_cap, I'll remove
> > > pad.g_fmt() call which is for checking pixel format.
> > > The check will be moved to viif_capture_link_validate() validation
> > > routine triggered by a start streaming event.
> > >
> > > > [snip]
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-17 11:47 ` Hans Verkuil
2023-01-18 1:04 ` Laurent Pinchart
@ 2023-01-26 1:25 ` yuji2.ishikawa
2023-01-26 8:01 ` Hans Verkuil
1 sibling, 1 reply; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-26 1:25 UTC (permalink / raw)
To: hverkuil, laurent.pinchart, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
Hello Hans,
Thank you for your comments.
> -----Original Message-----
> From: Hans Verkuil <hverkuil@xs4all.nl>
> Sent: Tuesday, January 17, 2023 8:47 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>; Mauro Carvalho Chehab
> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>
> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver user interace
>
> More comments below:
>
> On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> > The interface device includes CSI2 Receiver,
> > frame grabber, video DMAC and image signal processor.
> > This patch provides the user interface layer.
> >
> > A driver instance provides three /dev/videoX device files;
> > one for RGB image capture, another one for optional RGB capture
> > with different parameters and the last one for RAW capture.
> >
> > Through the device files, the driver provides streaming (DMA-BUF) interface.
> > A userland application should feed DMA-BUF instances for capture buffers.
> >
> > The driver is based on media controller framework.
> > Its operations are roughly mapped to two subdrivers;
> > one for ISP and CSI2 receiver (yields 1 instance),
> > the other for capture (yields 3 instances for each capture mode).
> >
> > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > ---
> > Changelog v2:
> > - Resend v1 because a patch exceeds size limit.
> >
> > Changelog v3:
> > - Adapted to media control framework
> > - Introduced ISP subdevice, capture device
> > - Remove private IOCTLs and add vendor specific V4L2 controls
> > - Change function name avoiding camelcase and uppercase letters
> >
> > Changelog v4:
> > - Split patches because the v3 patch exceeds size limit
> > - Stop using ID number to identify driver instance:
> > - Use dynamically allocated structure to hold HW specific context,
> > instead of static one.
> > - Call HW layer functions with the context structure instead of ID number
> > - Use pm_runtime to trigger initialization of HW
> > along with open/close of device files.
> >
> > Changelog v5:
> > - Fix coding style problems in viif.c
> > ---
> > drivers/media/platform/visconti/Makefile | 1 +
> > drivers/media/platform/visconti/viif.c | 545 ++++++++
> > drivers/media/platform/visconti/viif.h | 203 +++
> > .../media/platform/visconti/viif_capture.c | 1201
> +++++++++++++++++
> > drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> > 5 files changed, 2796 insertions(+)
> > create mode 100644 drivers/media/platform/visconti/viif.c
> > create mode 100644 drivers/media/platform/visconti/viif.h
> > create mode 100644 drivers/media/platform/visconti/viif_capture.c
> > create mode 100644 drivers/media/platform/visconti/viif_isp.c
> >
> > diff --git a/drivers/media/platform/visconti/Makefile
> b/drivers/media/platform/visconti/Makefile
> > index e14b904df75..d7a23c1f4e8 100644
> > --- a/drivers/media/platform/visconti/Makefile
> > +++ b/drivers/media/platform/visconti/Makefile
> > @@ -3,6 +3,7 @@
> > # Makefile for the Visconti video input device driver
> > #
> >
> > +visconti-viif-objs = viif.o viif_capture.o viif_isp.o
> > visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> >
> > obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> > diff --git a/drivers/media/platform/visconti/viif.c
> b/drivers/media/platform/visconti/viif.c
> > new file mode 100644
> > index 00000000000..e29480dbb76
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/viif.c
> > @@ -0,0 +1,545 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <media/v4l2-fwnode.h>
> > +
> > +#include "viif.h"
> > +
> > +static inline struct viif_device *v4l2_to_viif(struct v4l2_device *v4l2_dev)
> > +{
> > + return container_of(v4l2_dev, struct viif_device, v4l2_dev);
> > +}
> > +
> > +static struct viif_subdev *to_viif_subdev(struct v4l2_async_subdev *asd)
> > +{
> > + return container_of(asd, struct viif_subdev, asd);
> > +}
> > +
> > +/* VSYNC mask setting of MAIN unit */
> > +#define INT_M_SYNC_MASK_VSYNC_INT BIT(0)
> > +#define INT_M_SYNC_MASK_LINES_DELAY_INT1 BIT(1)
> > +#define INT_M_SYNC_MASK_LINES_DELAY_INT2 BIT(2)
> > +#define INT_M_SYNC_MASK_SW_DELAY_INT0 BIT(16)
> > +#define INT_M_SYNC_MASK_SW_DELAY_INT1 BIT(17)
> > +#define INT_M_SYNC_MASK_SW_DELAY_INT2 BIT(18)
> > +
> > +/* STATUS error mask setting of MAIN unit */
> > +#define INT_M_MASK_L2ISP_SIZE_ERROR BIT(0)
> > +#define INT_M_MASK_CRGBF_INTCRGERR_WRSTART BIT(1)
> > +#define INT_M_MASK_CRGBF_INTCRGERR_RDSTART BIT(2)
> > +#define INT_M_MASK_EMBED_ERROR BIT(3)
> > +#define INT_M_MASK_USERDATA_ERROR BIT(4)
> > +#define INT_M_MASK_L2ISP_POST0_TABLE_TIMEOUT BIT(8)
> > +#define INT_M_MASK_L2ISP_POST1_TABLE_TIMEOUT BIT(9)
> > +#define INT_M_MASK_L2ISP_GRID_TABLE_TIMEOUT BIT(11)
> > +#define INT_M_MASK_L1ISP_SIZE_ERROR0 BIT(16)
> > +#define INT_M_MASK_L1ISP_SIZE_ERROR1 BIT(17)
> > +#define INT_M_MASK_L1ISP_SIZE_ERROR2 BIT(18)
> > +#define INT_M_MASK_L1ISP_SIZE_ERROR3 BIT(19)
> > +#define INT_M_MASK_L1ISP_SIZE_ERROR4 BIT(20)
> > +#define INT_M_MASK_L1ISP_INT_ERR_CRGWRSTART BIT(21)
> > +#define INT_M_MASK_L1ISP_INT_ERR_CRGRDSTART BIT(22)
> > +#define INT_M_MASK_DELAY_INT_ERROR BIT(24)
> > +
> > +/* VSYNC mask settings of SUB unit */
> > +#define INT_S_SYNC_MASK_VSYNC_INT BIT(0)
> > +#define INT_S_SYNC_MASK_LINES_DELAY_INT1 BIT(1)
> > +#define INT_S_SYNC_MASK_SW_DELAY_INT0 BIT(16)
> > +#define INT_S_SYNC_MASK_SW_DELAY_INT1 BIT(17)
> > +
> > +/* STATUS error mask setting of SUB unit */
> > +#define INT_S_MASK_SIZE_ERROR BIT(0)
> > +#define INT_S_MASK_EMBED_ERROR BIT(1)
> > +#define INT_S_MASK_USERDATA_ERROR BIT(2)
> > +#define INT_S_MASK_DELAY_INT_ERROR BIT(24)
> > +#define INT_S_MASK_RESERVED_SET (BIT(16) | BIT(28))
> > +
> > +static void viif_vsync_irq_handler_w_isp(struct viif_device *viif_dev)
> > +{
> > + u32 event_main, event_sub, status_err, l2_transfer_status;
> > + u64 ts;
> > +
> > + ts = ktime_get_ns();
> > + hwd_viif_vsync_irq_handler(viif_dev->hwd_res, &event_main,
> &event_sub);
> > +
> > + /* Delayed Vsync of MAIN unit */
> > + if (event_main & INT_M_SYNC_MASK_LINES_DELAY_INT2) {
> > + /* unmask timeout error of gamma table */
> > + hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res,
> > +
> INT_M_MASK_DELAY_INT_ERROR);
> > + viif_dev->masked_gamma_path = 0;
> > +
> > + /* Get abort status of L2ISP */
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + hwd_viif_isp_get_info(viif_dev->hwd_res, NULL,
> &l2_transfer_status);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > +
> > + status_err = viif_dev->status_err;
> > + viif_dev->status_err = 0;
> > +
> > + visconti_viif_capture_switch_buffer(&viif_dev->cap_dev0,
> status_err,
> > + l2_transfer_status, ts);
> > + visconti_viif_capture_switch_buffer(&viif_dev->cap_dev1,
> status_err,
> > + l2_transfer_status, ts);
> > + }
> > +
> > + /* Delayed Vsync of SUB unit */
> > + if (event_sub & INT_S_SYNC_MASK_LINES_DELAY_INT1)
> > + visconti_viif_capture_switch_buffer(&viif_dev->cap_dev2, 0, 0,
> ts);
> > +}
> > +
> > +#define MASK_M_GAMMATBL_TIMEOUT 0x0700U
> > +
> > +static void viif_status_err_irq_handler(struct viif_device *viif_dev)
> > +{
> > + u32 event_main, event_sub, val, mask;
> > +
> > + hwd_viif_status_err_irq_handler(viif_dev->hwd_res, &event_main,
> &event_sub);
> > +
> > + if (event_main) {
> > + /* mask for gamma table time out error which will be
> unmasked in the next Vsync */
> > + val = FIELD_GET(MASK_M_GAMMATBL_TIMEOUT,
> event_main);
> > + if (val) {
> > + viif_dev->masked_gamma_path |= val;
> > + mask = INT_M_MASK_DELAY_INT_ERROR |
> > +
> FIELD_PREP(MASK_M_GAMMATBL_TIMEOUT,
> viif_dev->masked_gamma_path);
> > +
> hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res, mask);
> > + }
> > +
> > + viif_dev->status_err = event_main;
> > + }
> > + viif_dev->reported_err_main |= event_main;
> > + viif_dev->reported_err_sub |= event_sub;
> > + dev_err(viif_dev->dev, "MAIN/SUB error 0x%x 0x%x.\n", event_main,
> event_sub);
> > +}
> > +
> > +static void viif_csi2rx_err_irq_handler(struct viif_device *viif_dev)
> > +{
> > + u32 event;
> > +
> > + event = hwd_viif_csi2rx_err_irq_handler(viif_dev->hwd_res);
> > + viif_dev->reported_err_csi2rx |= event;
> > + dev_err(viif_dev->dev, "CSI2RX error 0x%x.\n", event);
> > +}
> > +
> > +static irqreturn_t visconti_viif_irq(int irq, void *dev_id)
> > +{
> > + struct viif_device *viif_dev = dev_id;
> > + int irq_type = irq - viif_dev->irq[0];
> > +
> > + spin_lock(&viif_dev->lock);
> > +
> > + switch (irq_type) {
> > + case 0:
> > + viif_vsync_irq_handler_w_isp(viif_dev);
> > + break;
> > + case 1:
> > + viif_status_err_irq_handler(viif_dev);
> > + break;
> > + case 2:
> > + viif_csi2rx_err_irq_handler(viif_dev);
> > + break;
> > + }
> > +
> > + spin_unlock(&viif_dev->lock);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +/* ----- Async Notifier Operations----- */
> > +static int visconti_viif_notify_bound(struct v4l2_async_notifier *notifier,
> > + struct v4l2_subdev *v4l2_sd, struct
> v4l2_async_subdev *asd)
> > +{
> > + struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
> > + struct viif_device *viif_dev = v4l2_to_viif(v4l2_dev);
> > + struct viif_subdev *viif_sd = to_viif_subdev(asd);
> > +
> > + viif_sd->v4l2_sd = v4l2_sd;
> > + viif_dev->num_sd++;
> > +
> > + return 0;
> > +}
> > +
> > +static void visconti_viif_create_links(struct viif_device *viif_dev)
> > +{
> > + unsigned int source_pad;
> > + int ret;
> > +
> > + /* camera subdev pad0 -> isp suddev pad0 */
> > + ret = media_entity_get_fwnode_pad(&viif_dev->sd->v4l2_sd->entity,
> > + viif_dev->sd->v4l2_sd->fwnode,
> MEDIA_PAD_FL_SOURCE);
> > + if (ret < 0) {
> > + dev_err(viif_dev->dev, "failed to find source pad\n");
> > + return;
> > + }
> > + source_pad = ret;
> > +
> > + ret = media_create_pad_link(&viif_dev->sd->v4l2_sd->entity,
> source_pad,
> > + &viif_dev->isp_subdev.sd.entity,
> VIIF_ISP_PAD_SINK,
> > + MEDIA_LNK_FL_ENABLED);
> > + if (ret)
> > + dev_err(viif_dev->dev, "failed create_pad_link (camera:src ->
> isp:sink)\n");
> > +
> > + ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity,
> VIIF_ISP_PAD_SRC_PATH0,
> > + &viif_dev->cap_dev0.vdev.entity,
> VIIF_CAPTURE_PAD_SINK,
> > + MEDIA_LNK_FL_ENABLED);
> > + if (ret)
> > + dev_err(viif_dev->dev, "failed create_pad_link (isp:src ->
> capture0:sink)\n");
> > +
> > + ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity,
> VIIF_ISP_PAD_SRC_PATH1,
> > + &viif_dev->cap_dev1.vdev.entity,
> VIIF_CAPTURE_PAD_SINK,
> > + MEDIA_LNK_FL_ENABLED);
> > + if (ret)
> > + dev_err(viif_dev->dev, "failed create_pad_link (isp:src ->
> capture1:sink)\n");
> > +
> > + ret = media_create_pad_link(&viif_dev->isp_subdev.sd.entity,
> VIIF_ISP_PAD_SRC_PATH2,
> > + &viif_dev->cap_dev2.vdev.entity,
> VIIF_CAPTURE_PAD_SINK,
> > + MEDIA_LNK_FL_ENABLED);
> > + if (ret)
> > + dev_err(viif_dev->dev, "failed create_pad_link (isp:src ->
> capture2:sink)\n");
> > +}
> > +
> > +static void visconti_viif_notify_unbind(struct v4l2_async_notifier *notifier,
> > + struct v4l2_subdev *subdev, struct
> v4l2_async_subdev *asd)
> > +{
> > + struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
> > + struct viif_subdev *viif_sd = to_viif_subdev(asd);
> > +
> > + v4l2_dev->ctrl_handler = NULL;
> > + viif_sd->v4l2_sd = NULL;
> > +}
> > +
> > +static int visconti_viif_notify_complete(struct v4l2_async_notifier *notifier)
> > +{
> > + struct v4l2_device *v4l2_dev = notifier->v4l2_dev;
> > + struct viif_device *viif_dev = v4l2_to_viif(v4l2_dev);
> > + int ret;
> > +
> > + ret = v4l2_device_register_subdev_nodes(v4l2_dev);
> > + if (ret < 0) {
> > + dev_err(v4l2_dev->dev, "Failed to register subdev nodes\n");
> > + return ret;
> > + }
> > +
> > + /* Make sure at least one sensor is primary and use it to initialize */
> > + if (!viif_dev->sd) {
> > + viif_dev->sd = &viif_dev->subdevs[0];
> > + viif_dev->sd_index = 0;
> > + }
> > +
> > + ret = visconti_viif_capture_register_ctrl_handlers(viif_dev);
> > + if (ret)
> > + return ret;
> > +
> > + visconti_viif_create_links(viif_dev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct v4l2_async_notifier_operations viif_notify_ops = {
> > + .bound = visconti_viif_notify_bound,
> > + .unbind = visconti_viif_notify_unbind,
> > + .complete = visconti_viif_notify_complete,
> > +};
> > +
> > +/* ----- Probe and Remove ----- */
> > +static int visconti_viif_init_async_subdevs(struct viif_device *viif_dev,
> unsigned int n_sd)
> > +{
> > + /* Reserve memory for 'n_sd' viif_subdev descriptors. */
> > + viif_dev->subdevs =
> > + devm_kcalloc(viif_dev->dev, n_sd, sizeof(*viif_dev->subdevs),
> GFP_KERNEL);
> > + if (!viif_dev->subdevs)
> > + return -ENOMEM;
> > +
> > + /* Reserve memory for 'n_sd' pointers to async_subdevices.
> > + * viif_dev->asds members will point to &viif_dev.asd
> > + */
> > + viif_dev->asds = devm_kcalloc(viif_dev->dev, n_sd,
> sizeof(*viif_dev->asds), GFP_KERNEL);
> > + if (!viif_dev->asds)
> > + return -ENOMEM;
> > +
> > + viif_dev->sd = NULL;
> > + viif_dev->sd_index = 0;
> > + viif_dev->num_sd = 0;
> > +
> > + return 0;
> > +}
> > +
> > +static int visconti_viif_parse_dt(struct viif_device *viif_dev)
> > +{
> > + struct device_node *of = viif_dev->dev->of_node;
> > + struct v4l2_fwnode_endpoint fw_ep;
> > + struct viif_subdev *viif_sd;
> > + struct device_node *ep;
> > + unsigned int i;
> > + int num_ep;
> > + int ret;
> > +
> > + memset(&fw_ep, 0, sizeof(struct v4l2_fwnode_endpoint));
> > +
> > + num_ep = of_graph_get_endpoint_count(of);
> > + if (!num_ep)
> > + return -ENODEV;
> > +
> > + ret = visconti_viif_init_async_subdevs(viif_dev, num_ep);
> > + if (ret)
> > + return ret;
> > +
> > + for (i = 0; i < num_ep; i++) {
> > + ep = of_graph_get_endpoint_by_regs(of, 0, i);
> > + if (!ep) {
> > + dev_err(viif_dev->dev, "No subdevice connected on
> endpoint %u.\n", i);
> > + ret = -ENODEV;
> > + goto error_put_node;
> > + }
> > +
> > + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep),
> &fw_ep);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Unable to parse endpoint
> #%u.\n", i);
> > + goto error_put_node;
> > + }
> > +
> > + if (fw_ep.bus_type != V4L2_MBUS_CSI2_DPHY ||
> > + fw_ep.bus.mipi_csi2.num_data_lanes == 0) {
> > + dev_err(viif_dev->dev, "missing CSI-2 properties in
> endpoint\n");
> > + ret = -EINVAL;
> > + goto error_put_node;
> > + }
> > +
> > + /* Setup the ceu subdevice and the async subdevice. */
> > + viif_sd = &viif_dev->subdevs[i];
> > + INIT_LIST_HEAD(&viif_sd->asd.list);
> > +
> > + viif_sd->mbus_flags = fw_ep.bus.mipi_csi2.flags;
> > + viif_sd->num_lane = fw_ep.bus.mipi_csi2.num_data_lanes;
> > + viif_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
> > + viif_sd->asd.match.fwnode =
> > +
> fwnode_graph_get_remote_port_parent(of_fwnode_handle(ep));
> > +
> > + viif_dev->asds[i] = &viif_sd->asd;
> > + of_node_put(ep);
> > + }
> > +
> > + return num_ep;
> > +
> > +error_put_node:
> > + of_node_put(ep);
> > + return ret;
> > +}
> > +
> > +static const struct of_device_id visconti_viif_of_table[] = {
> > + {
> > + .compatible = "toshiba,visconti-viif",
> > + },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, visconti_viif_of_table);
> > +
> > +#define NUM_IRQS 3
> > +#define IRQ_ID_STR "viif"
> > +#define MEDIA_MODEL "visconti_viif"
> > +#define MEDIA_BUS_INFO "platform:visconti_viif"
> > +
> > +static int visconti_viif_probe(struct platform_device *pdev)
> > +{
> > + const struct of_device_id *of_id;
> > + struct device *dev = &pdev->dev;
> > + struct viif_device *viif_dev;
> > + dma_addr_t table_paddr;
> > + int ret, i, num_sd;
> > +
> > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
> > + if (ret)
> > + return ret;
> > +
> > + viif_dev = devm_kzalloc(dev, sizeof(*viif_dev), GFP_KERNEL);
> > + if (!viif_dev)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, viif_dev);
> > + viif_dev->dev = dev;
> > +
> > + spin_lock_init(&viif_dev->lock);
> > + mutex_init(&viif_dev->pow_lock);
> > +
> > + viif_dev->capture_reg = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(viif_dev->capture_reg))
> > + return PTR_ERR(viif_dev->capture_reg);
> > +
> > + viif_dev->csi2host_reg = devm_platform_ioremap_resource(pdev, 1);
> > + if (IS_ERR(viif_dev->csi2host_reg))
> > + return PTR_ERR(viif_dev->csi2host_reg);
> > +
> > + viif_dev->hwd_res = allocate_viif_res(dev, viif_dev->csi2host_reg,
> viif_dev->capture_reg);
> > +
> > + for (i = 0; i < NUM_IRQS; i++) {
> > + ret = platform_get_irq(pdev, i);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to acquire irq resource\n");
> > + return ret;
> > + }
> > + viif_dev->irq[i] = ret;
> > + ret = devm_request_irq(dev, viif_dev->irq[i], visconti_viif_irq, 0,
> IRQ_ID_STR,
> > + viif_dev);
> > + if (ret) {
> > + dev_err(dev, "irq request failed\n");
> > + return ret;
> > + }
> > + }
> > +
> > + viif_dev->table_vaddr =
> > + dma_alloc_wc(dev, sizeof(struct viif_table_area), &table_paddr,
> GFP_KERNEL);
> > + if (!viif_dev->table_vaddr) {
> > + dev_err(dev, "dma_alloc_wc failed\n");
> > + return -ENOMEM;
> > + }
> > + viif_dev->table_paddr = (struct viif_table_area *)table_paddr;
> > +
> > + /* power control */
> > + pm_runtime_enable(dev);
> > +
> > + /* build media_dev */
> > + viif_dev->media_dev.hw_revision = 0;
> > + strscpy(viif_dev->media_dev.model, MEDIA_MODEL,
> sizeof(viif_dev->media_dev.model));
> > + viif_dev->media_dev.dev = dev;
> > + strscpy(viif_dev->media_dev.bus_info, MEDIA_BUS_INFO,
> sizeof(viif_dev->media_dev.bus_info));
> > + media_device_init(&viif_dev->media_dev);
> > +
> > + /* build v4l2_dev */
> > + viif_dev->v4l2_dev.mdev = &viif_dev->media_dev;
> > + ret = v4l2_device_register(dev, &viif_dev->v4l2_dev);
> > + if (ret)
> > + goto error_dma_free;
> > +
> > + ret = media_device_register(&viif_dev->media_dev);
> > + if (ret) {
> > + dev_err(dev, "Failed to register media device: %d\n", ret);
> > + goto error_v4l2_unregister;
> > + }
> > +
> > + ret = visconti_viif_isp_register(viif_dev);
> > + if (ret) {
> > + dev_err(dev, "failed to register isp sub node: %d\n", ret);
> > + goto error_media_unregister;
> > + }
> > + ret = visconti_viif_capture_register(viif_dev);
> > + if (ret) {
> > + dev_err(dev, "failed to register capture node: %d\n", ret);
> > + goto error_media_unregister;
> > + }
> > +
> > + /* check device type */
> > + of_id = of_match_device(visconti_viif_of_table, dev);
> > +
> > + num_sd = visconti_viif_parse_dt(viif_dev);
> > + if (ret < 0) {
> > + ret = num_sd;
> > + goto error_media_unregister;
> > + }
> > +
> > + viif_dev->notifier.v4l2_dev = &viif_dev->v4l2_dev;
> > + v4l2_async_nf_init(&viif_dev->notifier);
> > + for (i = 0; i < num_sd; i++)
> > + __v4l2_async_nf_add_subdev(&viif_dev->notifier,
> viif_dev->asds[i]);
> > + viif_dev->notifier.ops = &viif_notify_ops;
> > + ret = v4l2_async_nf_register(&viif_dev->v4l2_dev, &viif_dev->notifier);
> > + if (ret)
> > + goto error_media_unregister;
> > +
> > + return 0;
> > +
> > +error_media_unregister:
> > + media_device_unregister(&viif_dev->media_dev);
> > +error_v4l2_unregister:
> > + v4l2_device_unregister(&viif_dev->v4l2_dev);
> > +error_dma_free:
> > + pm_runtime_disable(dev);
> > + dma_free_wc(&pdev->dev, sizeof(struct viif_table_area),
> viif_dev->table_vaddr,
> > + (dma_addr_t)viif_dev->table_paddr);
> > + return ret;
> > +}
> > +
> > +static int visconti_viif_remove(struct platform_device *pdev)
> > +{
> > + struct viif_device *viif_dev = platform_get_drvdata(pdev);
> > +
> > + visconti_viif_isp_unregister(viif_dev);
> > + visconti_viif_capture_unregister(viif_dev);
> > + v4l2_async_nf_unregister(&viif_dev->notifier);
> > + media_device_unregister(&viif_dev->media_dev);
> > + v4l2_device_unregister(&viif_dev->v4l2_dev);
> > + pm_runtime_disable(&pdev->dev);
> > + dma_free_wc(&pdev->dev, sizeof(struct viif_table_area),
> viif_dev->table_vaddr,
> > + (dma_addr_t)viif_dev->table_paddr);
> > +
> > + return 0;
> > +}
> > +
> > +static int visconti_viif_runtime_suspend(struct device *dev)
> > +{
> > + /* This callback is kicked when the last device-file is closed */
> > + return 0;
> > +}
> > +
> > +static int visconti_viif_runtime_resume(struct device *dev)
> > +{
> > + /* This callback is kicked when the first device-file is opened */
> > + struct viif_device *viif_dev = dev_get_drvdata(dev);
> > +
> > + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_DISABLE;
> > +
> > + mutex_lock(&viif_dev->pow_lock);
> > +
> > + /* VSYNC mask setting of MAIN unit */
> > + hwd_viif_main_vsync_set_irq_mask(
> > + viif_dev->hwd_res, INT_M_SYNC_MASK_VSYNC_INT |
> INT_M_SYNC_MASK_LINES_DELAY_INT1 |
> > +
> INT_M_SYNC_MASK_SW_DELAY_INT0 |
> > +
> INT_M_SYNC_MASK_SW_DELAY_INT2);
> > +
> > + /* STATUS error mask setting of MAIN unit */
> > + hwd_viif_main_status_err_set_irq_mask(viif_dev->hwd_res,
> INT_M_MASK_DELAY_INT_ERROR);
> > +
> > + /* VSYNC mask settings of SUB unit */
> > + hwd_viif_sub_vsync_set_irq_mask(viif_dev->hwd_res,
> INT_S_SYNC_MASK_VSYNC_INT |
> > +
> INT_S_SYNC_MASK_SW_DELAY_INT0 |
> > +
> INT_S_SYNC_MASK_SW_DELAY_INT1);
> > +
> > + /* STATUS error mask setting(unmask) of SUB unit */
> > + hwd_viif_sub_status_err_set_irq_mask(viif_dev->hwd_res,
> > + INT_S_MASK_RESERVED_SET
> | INT_S_MASK_DELAY_INT_ERROR);
> > +
> > + mutex_unlock(&viif_dev->pow_lock);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dev_pm_ops visconti_viif_pm_ops =
> { SET_RUNTIME_PM_OPS(
> > + visconti_viif_runtime_suspend, visconti_viif_runtime_resume, NULL) };
> > +
> > +static struct platform_driver visconti_viif_driver = {
> > + .probe = visconti_viif_probe,
> > + .remove = visconti_viif_remove,
> > + .driver = {
> > + .name = "visconti_viif",
> > + .of_match_table = visconti_viif_of_table,
> > + .pm = &visconti_viif_pm_ops,
> > + },
> > +};
> > +
> > +module_platform_driver(visconti_viif_driver);
> > +
> > +MODULE_AUTHOR("Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>");
> > +MODULE_DESCRIPTION("Toshiba Visconti Video Input driver");
> > +MODULE_LICENSE("Dual BSD/GPL");
> > diff --git a/drivers/media/platform/visconti/viif.h
> b/drivers/media/platform/visconti/viif.h
> > new file mode 100644
> > index 00000000000..cd121ae3200
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/viif.h
> > @@ -0,0 +1,203 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#ifndef VIIF_H
> > +#define VIIF_H
> > +
> > +#include <linux/visconti_viif.h>
> > +#include <media/v4l2-async.h>
> > +#include <media/v4l2-common.h>
> > +#include <media/v4l2-ctrls.h>
> > +#include <media/v4l2-dev.h>
> > +#include <media/v4l2-device.h>
> > +#include <media/v4l2-event.h>
> > +#include <media/v4l2-ioctl.h>
> > +#include <media/v4l2-mediabus.h>
> > +#include <media/v4l2-mem2mem.h>
> > +#include <media/videobuf2-dma-contig.h>
> > +
> > +#include "hwd_viif.h"
> > +
> > +#define VIIF_ISP_REGBUF_0 0
> > +#define VIIF_L2ISP_POST_0 0
> > +#define VIIF_L2ISP_POST_1 1
> > +
> > +#define VIIF_CAPTURE_PAD_SINK 0
> > +#define VIIF_ISP_PAD_SINK 0
> > +#define VIIF_ISP_PAD_SRC_PATH0 1
> > +#define VIIF_ISP_PAD_SRC_PATH1 2
> > +#define VIIF_ISP_PAD_SRC_PATH2 3
> > +#define VIIF_ISP_PAD_NUM 4
> > +
> > +#define CAPTURE_PATH_MAIN_POST0 0
> > +#define CAPTURE_PATH_MAIN_POST1 1
> > +#define CAPTURE_PATH_SUB 2
> > +
> > +#define VIIF_DPC_TABLE_BYTES 8192
> > +#define VIIF_LSC_TABLE_BYTES 1536
> > +#define VIIF_UNDIST_TABLE_BYTES 8192
> > +#define VIIF_L2_GAMMA_TABLE_BYTES 512
> > +
> > +#define VIIF_HW_AVAILABLE_IRQS 4
> > +
> > +struct viif_fmt {
> > + u32 fourcc;
> > + u8 bpp[3];
> > + u8 num_planes;
> > + u32 colorspace;
> > + u32 pitch_align;
> > +};
> > +
> > +struct viif_subdev {
> > + struct v4l2_subdev *v4l2_sd;
> > + struct v4l2_async_subdev asd;
> > +
> > + /* per-subdevice mbus configuration options */
> > + unsigned int mbus_flags;
> > + unsigned int mbus_code;
> > + unsigned int num_lane;
> > +};
> > +
> > +struct viif_table_area {
> > + /* viif_l1_dpc_config */
> > + u32 dpc_table_h[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
> > + u32 dpc_table_m[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
> > + u32 dpc_table_l[VIIF_DPC_TABLE_BYTES / sizeof(u32)];
> > + /* viif_l1_lsc_config */
> > + u16 lsc_table_gr[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> > + u16 lsc_table_r[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> > + u16 lsc_table_b[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> > + u16 lsc_table_gb[VIIF_LSC_TABLE_BYTES / sizeof(u16)];
> > + /* viif_l2_undist_config */
> > + u32 undist_write_g[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> > + u32 undist_read_b[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> > + u32 undist_read_g[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> > + u32 undist_read_r[VIIF_UNDIST_TABLE_BYTES / sizeof(u32)];
> > + /* viif_l2_gamma_config */
> > + u16 l2_gamma_table[2][6][VIIF_L2_GAMMA_TABLE_BYTES /
> sizeof(u16)];
> > +};
> > +
> > +/* capture device node information */
> > +struct cap_dev {
> > + u32 pathid; /* 0 ... MAIN POST0, 1 ... MAIN POST1, 2 ... SUB */
> > + struct video_device vdev;
> > + struct media_pad capture_pad;
> > + struct v4l2_ctrl_handler ctrl_handler;
> > + struct mutex vlock; /* serialize ioctl to vb2_queue and video_device */
> > +
> > + /* vb2 queue, capture buffer list and active buffer pointer */
> > + struct vb2_queue vb2_vq;
> > + struct list_head buf_queue;
> > + struct vb2_v4l2_buffer *active;
> > + struct vb2_v4l2_buffer *dma_active;
> > + int buf_cnt;
> > + unsigned int sequence;
> > +
> > + /* currently configured field and pixel format */
> > + enum v4l2_field field;
> > + struct v4l2_pix_format_mplane v4l2_pix;
> > + unsigned int out_format;
> > + struct hwd_viif_img_area img_area;
> > + struct hwd_viif_out_process out_process;
> > +
> > + struct viif_device *viif_dev;
> > +};
> > +
> > +struct isp_subdev {
> > + struct v4l2_subdev sd;
> > + struct media_pad pads[VIIF_ISP_PAD_NUM];
> > + struct v4l2_subdev_pad_config pad_cfg[VIIF_ISP_PAD_NUM];
> > + struct mutex ops_lock; /* serialize V4L2 query */
> > + struct viif_device *viif_dev;
> > + struct v4l2_ctrl_handler ctrl_handler;
> > +};
> > +
> > +struct hwd_viif_res;
> > +
> > +struct viif_device {
> > + struct device *dev;
> > + struct v4l2_device v4l2_dev;
> > + struct media_device media_dev;
> > + struct media_pipeline pipe;
> > + u32 masked_gamma_path;
> > + struct hwd_viif_func *func;
> > +
> > + struct viif_subdev *subdevs;
> > + struct v4l2_async_subdev **asds;
> > + /* async subdev notification helpers */
> > + struct v4l2_async_notifier notifier;
> > +
> > + /* the subdevice currently in use */
> > + struct viif_subdev *sd;
> > + unsigned int sd_index;
> > + unsigned int num_sd;
> > +
> > + /* sub device node information */
> > + struct cap_dev cap_dev0;
> > + struct cap_dev cap_dev1;
> > + struct cap_dev cap_dev2;
> > + struct isp_subdev isp_subdev;
> > +
> > + /* lock - serialize calls to low-level operations (hwd_xxxx) */
> > + /* also, this serialize access to capture buffer queue and active buffer */
> > + spinlock_t lock;
> > +
> > + /* pow_lock - serialize power control*/
> > + struct mutex pow_lock;
> > +
> > + struct {
> > + u32 clock_id;
> > + u32 csi2_clock_id;
> > + u32 csi2_reset_id;
> > + } clk_compat;
> > +
> > + /* hwd_res - context of low level implementation */
> > + struct hwd_viif_res *hwd_res;
> > +
> > + void __iomem *capture_reg;
> > + void __iomem *csi2host_reg;
> > + unsigned int irq[VIIF_HW_AVAILABLE_IRQS];
> > +
> > + /* Un-cache table area */
> > + struct viif_table_area *table_vaddr;
> > + struct viif_table_area *table_paddr;
> > +
> > + /* Rawpack mode */
> > + u32 rawpack_mode;
> > +
> > + /* Error flag checked at delayed vsync handler */
> > + u32 status_err;
> > +
> > + /* Error flag checked at compound control GET_REPORTED_ERRORS
> */
> > + u32 reported_err_main;
> > + u32 reported_err_sub;
> > + u32 reported_err_csi2rx;
> > +};
> > +
> > +/* viif.c */
> > +void visconti_viif_hw_on(struct viif_device *viif_dev);
> > +void visconti_viif_hw_off(struct viif_device *viif_dev);
> > +
> > +/* viif_capture.c */
> > +int visconti_viif_capture_register(struct viif_device *viif_dev);
> > +void visconti_viif_capture_unregister(struct viif_device *viif_dev);
> > +int visconti_viif_capture_register_ctrl_handlers(struct viif_device *viif_dev);
> > +void visconti_viif_capture_switch_buffer(struct cap_dev *cap_dev, u32
> status_err,
> > + u32 l2_transfer_status, u64
> timestamp);
> > +
> > +/* viif_isp.c */
> > +int visconti_viif_isp_register(struct viif_device *viif_dev);
> > +void visconti_viif_isp_unregister(struct viif_device *viif_dev);
> > +int visconti_viif_isp_main_set_unit(struct viif_device *viif_dev);
> > +int visconti_viif_isp_sub_set_unit(struct viif_device *viif_dev);
> > +void visconti_viif_isp_set_compose_rect(struct viif_device *viif_dev,
> > + struct viif_l2_roi_config *roi);
> > +
> > +/* viif_controls.c */
> > +int visconti_viif_isp_init_controls(struct viif_device *viif_dev);
> > +
> > +#endif /* VIIF_H */
> > diff --git a/drivers/media/platform/visconti/viif_capture.c
> b/drivers/media/platform/visconti/viif_capture.c
> > new file mode 100644
> > index 00000000000..fa18aec4470
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/viif_capture.c
> > @@ -0,0 +1,1201 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/pm_runtime.h>
> > +#include <media/v4l2-common.h>
> > +#include <media/v4l2-subdev.h>
> > +
> > +#include "viif.h"
> > +
> > +#define VIIF_CROP_MAX_X_ISP (8062U)
> > +#define VIIF_CROP_MAX_Y_ISP (3966U)
> > +#define VIIF_CROP_MIN_W (128U)
> > +#define VIIF_CROP_MAX_W_ISP (8190U)
> > +#define VIIF_CROP_MIN_H (128U)
> > +#define VIIF_CROP_MAX_H_ISP (4094U)
> > +
> > +struct viif_buffer {
> > + struct vb2_v4l2_buffer vb;
> > + struct list_head queue;
> > +};
> > +
> > +static inline struct viif_buffer *vb2_to_viif(struct vb2_v4l2_buffer *vbuf)
> > +{
> > + return container_of(vbuf, struct viif_buffer, vb);
> > +}
> > +
> > +static inline struct cap_dev *video_drvdata_to_capdev(struct file *file)
> > +{
> > + return (struct cap_dev *)video_drvdata(file);
> > +}
> > +
> > +static inline struct cap_dev *vb2queue_to_capdev(struct vb2_queue *vq)
> > +{
> > + return (struct cap_dev *)vb2_get_drv_priv(vq);
> > +}
> > +
> > +/* ----- ISRs and VB2 Operations ----- */
> > +static int viif_set_img(struct cap_dev *cap_dev, struct vb2_buffer *vb)
> > +{
> > + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct hwd_viif_img next_out_img;
> > + dma_addr_t phys_addr;
> > + int i, ret = 0;
> > +
> > + next_out_img.width = pix->width;
> > + next_out_img.height = pix->height;
> > + next_out_img.format = cap_dev->out_format;
> > +
> > + for (i = 0; i < pix->num_planes; i++) {
> > + next_out_img.pixelmap[i].pitch =
> pix->plane_fmt[i].bytesperline;
> > + phys_addr = vb2_dma_contig_plane_dma_addr(vb, i);
> > + next_out_img.pixelmap[i].pmap_paddr = phys_addr;
> > + }
> > +
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l2_set_img_transmission(viif_dev->hwd_res,
> VIIF_L2ISP_POST_0,
> > + HWD_VIIF_ENABLE,
> &cap_dev->img_area,
> > +
> &cap_dev->out_process, &next_out_img);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + if (ret)
> > + dev_err(viif_dev->dev, "set img error. %d\n", ret);
> > + } else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1) {
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l2_set_img_transmission(viif_dev->hwd_res,
> VIIF_L2ISP_POST_1,
> > + HWD_VIIF_ENABLE,
> &cap_dev->img_area,
> > +
> &cap_dev->out_process, &next_out_img);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + if (ret)
> > + dev_err(viif_dev->dev, "set img error. %d\n", ret);
> > + } else if (cap_dev->pathid == CAPTURE_PATH_SUB) {
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_sub_set_img_transmission(viif_dev->hwd_res,
> &next_out_img);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + if (ret)
> > + dev_err(viif_dev->dev, "set img error. %d\n", ret);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +/*
> > + * viif_capture_switch_buffer() is called from interrupt service routine
> > + * triggered by VSync with some fixed delay.
> > + * The function may switch DMA target buffer by calling viif_set_img().
> > + * The VIIF DMA HW captures the destination address at next VSync
> > + * and completes transfer at one more after.
> > + * Therefore, filled buffer is available at the one after next ISR.
> > + *
> > + * To avoid DMA HW getting stucked, we always need to set valid destination
> address.
> > + * If a prepared buffer is not available, we reuse the buffer currently being
> transferred to.
> > + *
> > + * The cap_dev structure has two pointers and a queue to handle video
> buffers;
> > + + Description of each item at the entry of this function:
> > + * * buf_queue: holds prepared buffers, set by vb2_queue()
> > + * * active: pointing at address captured (and to be filled) by DMA HW
> > + * * dma_active: pointing at buffer filled by DMA HW
> > + *
> > + * Rules to update items:
> > + * * when buf_queue is not empty, "active" buffer goes "dma_active"
> > + * * when buf_queue is empty:
> > + * * "active" buffer stays the same (DMA HW fills the same buffer for
> coming two frames)
> > + * * "dma_active" gets NULL (filled buffer will be reused; should not go
> "DONE" at next ISR)
> > + *
> > + * Simulation:
> > + * | buf_queue | active | dma_active | note |
> > + * | X | NULL | NULL | |
> > + * <QBUF BUF0>
> > + * | X | BUF0 | NULL | BUF0 stays |
> > + * | X | BUF0 | NULL | BUF0 stays |
> > + * <QBUF BUF1>
> > + * <QBUF BUF2>
> > + * | BUF2 BUF1 | BUF0 | NULL | |
> > + * | BUF2 | BUF1 | BUF0 | BUF0 goes DONE |
> > + * | X | BUF2 | BUF1 | BUF1 goes DONE, BUF2 stays |
> > + * | X | BUF2 | NULL | BUF2 stays |
> > + */
> > +void visconti_viif_capture_switch_buffer(struct cap_dev *cap_dev, u32
> status_err,
> > + u32 l2_transfer_status, u64
> timestamp)
> > +{
> > + if (cap_dev->dma_active) {
> > + /* DMA has completed and another framebuffer instance is set
> */
> > + struct vb2_v4l2_buffer *vbuf = cap_dev->dma_active;
> > + enum vb2_buffer_state state;
> > +
> > + cap_dev->buf_cnt--;
> > + vbuf->vb2_buf.timestamp = timestamp;
> > + vbuf->sequence = cap_dev->sequence++;
> > + vbuf->field = cap_dev->field;
> > + if (status_err || l2_transfer_status)
> > + state = VB2_BUF_STATE_ERROR;
> > + else
> > + state = VB2_BUF_STATE_DONE;
> > +
> > + vb2_buffer_done(&vbuf->vb2_buf, state);
> > + }
> > +
> > + /* QUEUE pop to register an instance as next DMA target; if empty,
> reuse current instance */
> > + if (!list_empty(&cap_dev->buf_queue)) {
> > + struct viif_buffer *buf =
> > + list_entry(cap_dev->buf_queue.next, struct viif_buffer,
> queue);
> > + list_del_init(&buf->queue);
> > + viif_set_img(cap_dev, &buf->vb.vb2_buf);
> > + cap_dev->active = &buf->vb;
> > + cap_dev->dma_active = cap_dev->active;
> > + } else {
> > + cap_dev->dma_active = NULL;
> > + }
> > +}
> > +
> > +/* --- Capture buffer control --- */
> > +static int viif_vb2_setup(struct vb2_queue *vq, unsigned int *count, unsigned
> int *num_planes,
> > + unsigned int sizes[], struct device *alloc_devs[])
> > +{
> > + struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
> > + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> > + unsigned int i;
> > +
> > + /* num_planes is set: just check plane sizes. */
> > + if (*num_planes) {
> > + for (i = 0; i < pix->num_planes; i++)
> > + if (sizes[i] < pix->plane_fmt[i].sizeimage)
> > + return -EINVAL;
> > +
> > + return 0;
> > + }
> > +
> > + /* num_planes not set: called from REQBUFS, just set plane sizes. */
> > + *num_planes = pix->num_planes;
> > + for (i = 0; i < pix->num_planes; i++)
> > + sizes[i] = pix->plane_fmt[i].sizeimage;
> > +
> > + cap_dev->buf_cnt = 0;
> > +
> > + return 0;
> > +}
> > +
> > +static void viif_vb2_queue(struct vb2_buffer *vb)
> > +{
> > + struct cap_dev *cap_dev = vb2queue_to_capdev(vb->vb2_queue);
> > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct viif_buffer *buf = vb2_to_viif(vbuf);
> > + unsigned long irqflags;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > +
> > + if (!cap_dev->active) {
> > + cap_dev->active = vbuf;
> > + viif_set_img(cap_dev, vb);
> > + } else {
> > + list_add_tail(&buf->queue, &cap_dev->buf_queue);
> > + }
> > + cap_dev->buf_cnt++;
> > +
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +}
> > +
> > +static int viif_vb2_prepare(struct vb2_buffer *vb)
> > +{
> > + struct cap_dev *cap_dev = vb2queue_to_capdev(vb->vb2_queue);
> > + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + unsigned int i;
> > +
> > + for (i = 0; i < pix->num_planes; i++) {
> > + if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) {
> > + dev_err(viif_dev->dev, "Plane size too small (%lu
> < %u)\n",
> > + vb2_plane_size(vb, i),
> pix->plane_fmt[i].sizeimage);
> > + return -EINVAL;
> > + }
> > +
> > + vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage);
> > + }
> > + return 0;
> > +}
> > +
> > +static int viif_start_streaming(struct vb2_queue *vq, unsigned int count)
> > +{
> > + struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > +
> > + /* note that pipe is shared among paths; see pipe.streaming_count
> member variable */
> > + ret = video_device_pipeline_start(&cap_dev->vdev, &viif_dev->pipe);
> > + if (ret)
> > + dev_err(viif_dev->dev, "start pipeline failed %d\n", ret);
>
> Huh, why do you ignore the error and continue?
This error should have been cared.
I'll fix it.
> > +
> > + /* Currently, only path0 (MAIN POST0) initializes ISP and Camera */
> > + /* Possibly, initialization can be done when pipe.streaming_count==0 */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + /* CSI2RX start */
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, video,
> s_stream, true);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Start isp subdevice stream
> failed. %d\n", ret);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
>
> On error all queued buffers have to be returned to vb2 with status
> VB2_BUF_STATE_QUEUED.
> Otherwise the vb2 internal status will get confused. Similar to stop_streaming,
> just
> with a different status (QUEUED instead of ERROR).
I'll fix them. I'll add cares for vb2 at start/stop streaming.
> > + return ret;
> > + }
> > + }
> > +
> > + /* buffer control */
> > + cap_dev->sequence = 0;
> > +
> > + /* finish critical section: some sensor driver (including imx219) calls
> schedule() */
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + /* Camera (CSI2 source) start streaming */
> > + /* Currently, only path0 (MAIN POST0) initializes ISP and Camera */
> > + /* Possibly, initialization can be done when pipe.streaming_count==0 */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, s_stream, true);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Start subdev stream
> failed. %d\n", ret);
> > + (void)v4l2_subdev_call(&viif_dev->isp_subdev.sd,
> video, s_stream, false);
> > + return ret;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void viif_stop_streaming(struct vb2_queue *vq)
> > +{
> > + struct cap_dev *cap_dev = vb2queue_to_capdev(vq);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + struct viif_buffer *buf;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + /* Currently, only path0 (MAIN POST0) stops ISP and Camera */
> > + /* Possibly, teardown can be done when pipe.streaming_count==0 */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, s_stream,
> false);
> > + if (ret)
> > + dev_err(viif_dev->dev, "Stop subdev stream
> failed. %d\n", ret);
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > +
> > + /* Currently, only path0 (MAIN POST0) stops ISP and Camera */
> > + /* Possibly, teardown can be done when pipe.streaming_count==0 */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, video,
> s_stream, false);
> > + if (ret)
> > + dev_err(viif_dev->dev, "Stop isp subdevice stream
> failed %d\n", ret);
> > + }
> > +
> > + /* buffer control */
> > + if (cap_dev->active) {
> > + vb2_buffer_done(&cap_dev->active->vb2_buf,
> VB2_BUF_STATE_ERROR);
> > + cap_dev->buf_cnt--;
> > + cap_dev->active = NULL;
> > + }
> > + if (cap_dev->dma_active) {
> > + vb2_buffer_done(&cap_dev->dma_active->vb2_buf,
> VB2_BUF_STATE_ERROR);
> > + cap_dev->buf_cnt--;
> > + cap_dev->dma_active = NULL;
> > + }
> > +
> > + /* Release all queued buffers. */
> > + list_for_each_entry(buf, &cap_dev->buf_queue, queue) {
> > + vb2_buffer_done(&buf->vb.vb2_buf,
> VB2_BUF_STATE_ERROR);
> > + cap_dev->buf_cnt--;
> > + }
> > + INIT_LIST_HEAD(&cap_dev->buf_queue);
> > + if (cap_dev->buf_cnt)
> > + dev_err(viif_dev->dev, "Buffer count error %d\n",
> cap_dev->buf_cnt);
> > +
> > + video_device_pipeline_stop(&cap_dev->vdev);
> > +
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +}
> > +
> > +static const struct vb2_ops viif_vb2_ops = {
> > + .queue_setup = viif_vb2_setup,
> > + .buf_queue = viif_vb2_queue,
> > + .buf_prepare = viif_vb2_prepare,
> > + .wait_prepare = vb2_ops_wait_prepare,
> > + .wait_finish = vb2_ops_wait_finish,
> > + .start_streaming = viif_start_streaming,
> > + .stop_streaming = viif_stop_streaming,
> > +};
> > +
> > +/* --- VIIF hardware settings --- */
> > +/* L2ISP output csc setting for YUV to RGB(ITU-R BT.709) */
> > +static const struct hwd_viif_csc_param viif_csc_yuv2rgb = {
> > + .r_cr_in_offset = 0x18000,
> > + .g_y_in_offset = 0x1f000,
> > + .b_cb_in_offset = 0x18000,
> > + .coef = {
> > + [0] = 0x1000,
> > + [1] = 0xfd12,
> > + [2] = 0xf8ad,
> > + [3] = 0x1000,
> > + [4] = 0x1d07,
> > + [5] = 0x0000,
> > + [6] = 0x1000,
> > + [7] = 0x0000,
> > + [8] = 0x18a2,
> > + },
> > + .r_cr_out_offset = 0x1000,
> > + .g_y_out_offset = 0x1000,
> > + .b_cb_out_offset = 0x1000,
> > +};
> > +
> > +/* L2ISP output csc setting for RGB to YUV(ITU-R BT.709) */
> > +static const struct hwd_viif_csc_param viif_csc_rgb2yuv = {
> > + .r_cr_in_offset = 0x1f000,
> > + .g_y_in_offset = 0x1f000,
> > + .b_cb_in_offset = 0x1f000,
> > + .coef = {
> > + [0] = 0x0b71,
> > + [1] = 0x0128,
> > + [2] = 0x0367,
> > + [3] = 0xf9b1,
> > + [4] = 0x082f,
> > + [5] = 0xfe20,
> > + [6] = 0xf891,
> > + [7] = 0xff40,
> > + [8] = 0x082f,
> > + },
> > + .r_cr_out_offset = 0x8000,
> > + .g_y_out_offset = 0x1000,
> > + .b_cb_out_offset = 0x8000,
> > +};
> > +
> > +static int viif_l2_set_format(struct cap_dev *cap_dev)
> > +{
> > + struct v4l2_pix_format_mplane *pix = &cap_dev->v4l2_pix;
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + const struct hwd_viif_csc_param *csc_param = NULL;
> > + struct v4l2_subdev_selection sel = {
> > + .target = V4L2_SEL_TGT_CROP,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + struct v4l2_subdev_format fmt = {
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + bool inp_is_rgb = false;
> > + bool out_is_rgb = false;
> > + u32 postid;
> > + int ret;
> > +
> > + /* check path id */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> > + fmt.pad = VIIF_ISP_PAD_SRC_PATH0;
> > + postid = VIIF_L2ISP_POST_0;
> > + } else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1) {
> > + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> > + fmt.pad = VIIF_ISP_PAD_SRC_PATH1;
> > + postid = VIIF_L2ISP_POST_1;
> > + } else {
> > + return -EINVAL;
> > + }
> > +
> > + cap_dev->out_process.half_scale = HWD_VIIF_DISABLE;
> > + cap_dev->out_process.select_color = HWD_VIIF_COLOR_YUV_RGB;
> > + cap_dev->out_process.alpha = 0;
> > +
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection,
> NULL, &sel);
> > + if (ret) {
> > + cap_dev->img_area.x = 0;
> > + cap_dev->img_area.y = 0;
> > + cap_dev->img_area.w = pix->width;
> > + cap_dev->img_area.h = pix->height;
> > + } else {
> > + cap_dev->img_area.x = sel.r.left;
> > + cap_dev->img_area.y = sel.r.top;
> > + cap_dev->img_area.w = sel.r.width;
> > + cap_dev->img_area.h = sel.r.height;
> > + }
> > +
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_fmt, NULL,
> &fmt);
> > + if (!ret)
> > + inp_is_rgb = (fmt.format.code ==
> MEDIA_BUS_FMT_RGB888_1X24);
> > +
> > + switch (pix->pixelformat) {
> > + case V4L2_PIX_FMT_RGB24:
> > + cap_dev->out_format = HWD_VIIF_RGB888_PACKED;
> > + out_is_rgb = true;
> > + break;
> > + case V4L2_PIX_FMT_ABGR32:
> > + cap_dev->out_format = HWD_VIIF_ARGB8888_PACKED;
> > + cap_dev->out_process.alpha = 0xff;
> > + out_is_rgb = true;
> > + break;
> > + case V4L2_PIX_FMT_YUV422M:
> > + cap_dev->out_format = HWD_VIIF_YCBCR422_8_PLANAR;
> > + break;
> > + case V4L2_PIX_FMT_YUV444M:
> > + cap_dev->out_format =
> HWD_VIIF_RGB888_YCBCR444_8_PLANAR;
> > + break;
> > + case V4L2_PIX_FMT_Y16:
> > + cap_dev->out_format = HWD_VIIF_ONE_COLOR_16;
> > + cap_dev->out_process.select_color = HWD_VIIF_COLOR_Y_G;
> > + break;
> > + }
> > +
> > + if (!inp_is_rgb && out_is_rgb)
> > + csc_param = &viif_csc_yuv2rgb; /* YUV -> RGB */
> > + else if (inp_is_rgb && !out_is_rgb)
> > + csc_param = &viif_csc_rgb2yuv; /* RGB -> YUV */
> > +
> > + return hwd_viif_l2_set_output_csc(viif_dev->hwd_res, postid,
> csc_param);
> > +}
> > +
> > +/* --- IOCTL Operations --- */
> > +static const struct viif_fmt viif_fmt_list[] = {
> > + {
> > + .fourcc = V4L2_PIX_FMT_RGB24,
> > + .bpp = { 24, 0, 0 },
> > + .num_planes = 1,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .pitch_align = 384,
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_ABGR32,
> > + .bpp = { 32, 0, 0 },
> > + .num_planes = 1,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .pitch_align = 512,
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_YUV422M,
> > + .bpp = { 8, 4, 4 },
> > + .num_planes = 3,
> > + .colorspace = V4L2_COLORSPACE_REC709,
> > + .pitch_align = 128,
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_YUV444M,
> > + .bpp = { 8, 8, 8 },
> > + .num_planes = 3,
> > + .colorspace = V4L2_COLORSPACE_REC709,
> > + .pitch_align = 128,
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_Y16,
> > + .bpp = { 16, 0, 0 },
> > + .num_planes = 1,
> > + .colorspace = V4L2_COLORSPACE_REC709,
> > + .pitch_align = 128,
> > + },
> > +};
> > +
> > +static const struct viif_fmt viif_rawfmt_list[] = {
> > + {
> > + .fourcc = V4L2_PIX_FMT_SRGGB10,
> > + .bpp = { 16, 0, 0 },
> > + .num_planes = 1,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .pitch_align = 256,
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_SRGGB12,
> > + .bpp = { 16, 0, 0 },
> > + .num_planes = 1,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .pitch_align = 256,
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_SRGGB14,
> > + .bpp = { 16, 0, 0 },
> > + .num_planes = 1,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .pitch_align = 256,
> > + },
> > +};
> > +
> > +static const struct viif_fmt *get_viif_fmt_from_fourcc(unsigned int fourcc)
> > +{
> > + const struct viif_fmt *fmt = &viif_fmt_list[0];
> > + unsigned int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(viif_fmt_list); i++, fmt++)
> > + if (fmt->fourcc == fourcc)
> > + return fmt;
> > +
> > + return NULL;
> > +}
> > +
> > +static void viif_update_plane_sizes(struct v4l2_plane_pix_format *plane,
> unsigned int bpl,
> > + unsigned int szimage)
> > +{
> > + memset(plane, 0, sizeof(*plane));
> > +
> > + plane->sizeimage = szimage;
> > + plane->bytesperline = bpl;
> > +}
> > +
> > +static void viif_calc_plane_sizes(const struct viif_fmt *viif_fmt,
> > + struct v4l2_pix_format_mplane *pix)
> > +{
> > + unsigned int i, bpl, szimage;
> > +
> > + for (i = 0; i < viif_fmt->num_planes; i++) {
> > + bpl = pix->width * viif_fmt->bpp[i] / 8;
> > + /* round up ptch */
> > + bpl = (bpl + (viif_fmt->pitch_align - 1)) / viif_fmt->pitch_align;
> > + bpl *= viif_fmt->pitch_align;
> > + szimage = pix->height * bpl;
> > + viif_update_plane_sizes(&pix->plane_fmt[i], bpl, szimage);
> > + }
> > + pix->num_planes = viif_fmt->num_planes;
> > +}
> > +
> > +static int viif_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > +
> > + strscpy(cap->card, "Toshiba VIIF", sizeof(cap->card));
> > + strscpy(cap->driver, "viif", sizeof(cap->driver));
> > + snprintf(cap->bus_info, sizeof(cap->bus_info),
> "platform:toshiba-viif-%s",
> > + dev_name(viif_dev->dev));
> > + return 0;
> > +}
> > +
> > +static int viif_enum_rawfmt(struct cap_dev *cap_dev, struct v4l2_fmtdesc *f)
> > +{
> > + if (f->index >= ARRAY_SIZE(viif_rawfmt_list))
> > + return -EINVAL;
> > +
> > + f->pixelformat = viif_rawfmt_list[f->index].fourcc;
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_enum_fmt_vid_cap(struct file *file, void *priv, struct
> v4l2_fmtdesc *f)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > + const struct viif_fmt *fmt;
> > +
> > + if (cap_dev->pathid == CAPTURE_PATH_SUB)
> > + return viif_enum_rawfmt(cap_dev, f);
> > +
> > + if (f->index >= ARRAY_SIZE(viif_fmt_list))
> > + return -EINVAL;
> > +
> > + fmt = &viif_fmt_list[f->index];
> > + f->pixelformat = fmt->fourcc;
> > +
> > + return 0;
> > +}
> > +
> > +/* size of minimum/maximum output image */
> > +#define VIIF_MIN_OUTPUT_IMG_WIDTH (128U)
> > +#define VIIF_MAX_OUTPUT_IMG_WIDTH_ISP (5760U)
> > +#define VIIF_MAX_OUTPUT_IMG_WIDTH_SUB (4096U)
> > +
> > +#define VIIF_MIN_OUTPUT_IMG_HEIGHT (128U)
> > +#define VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP (3240U)
> > +#define VIIF_MAX_OUTPUT_IMG_HEIGHT_SUB (2160U)
> > +
> > +static int viif_try_fmt(struct cap_dev *cap_dev, struct v4l2_format *v4l2_fmt)
> > +{
> > + struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp;
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct v4l2_subdev_format format = {
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + const struct viif_fmt *viif_fmt;
> > + int ret;
> > +
> > + /* check path id */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> > + format.pad = VIIF_ISP_PAD_SRC_PATH0;
> > + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> > + format.pad = VIIF_ISP_PAD_SRC_PATH1;
> > + else
> > + format.pad = VIIF_ISP_PAD_SRC_PATH2;
> > +
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_fmt, NULL,
> &format);
> > + if (ret)
> > + return -EINVAL;
> > +
> > + /* fourcc check */
> > + if (cap_dev->pathid == CAPTURE_PATH_SUB) {
> > + switch (format.format.code) {
> > + case MEDIA_BUS_FMT_SRGGB10_1X10:
> > + case MEDIA_BUS_FMT_SGRBG10_1X10:
> > + case MEDIA_BUS_FMT_SGBRG10_1X10:
> > + case MEDIA_BUS_FMT_SBGGR10_1X10:
> > + viif_fmt = &viif_rawfmt_list[0];
> /*V4L2_PIX_FMT_SRGGB10*/
> > + pix->pixelformat = viif_fmt->fourcc;
> > + break;
> > + case MEDIA_BUS_FMT_SRGGB12_1X12:
> > + case MEDIA_BUS_FMT_SGRBG12_1X12:
> > + case MEDIA_BUS_FMT_SGBRG12_1X12:
> > + case MEDIA_BUS_FMT_SBGGR12_1X12:
> > + viif_fmt = &viif_rawfmt_list[1];
> /*V4L2_PIX_FMT_SRGGB12*/
> > + pix->pixelformat = viif_fmt->fourcc;
> > + break;
> > + case MEDIA_BUS_FMT_SRGGB14_1X14:
> > + case MEDIA_BUS_FMT_SGRBG14_1X14:
> > + case MEDIA_BUS_FMT_SGBRG14_1X14:
> > + case MEDIA_BUS_FMT_SBGGR14_1X14:
> > + viif_fmt = &viif_rawfmt_list[2];
> /*V4L2_PIX_FMT_SRGGB14*/
> > + pix->pixelformat = viif_fmt->fourcc;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > + } else {
> > + viif_fmt = get_viif_fmt_from_fourcc(pix->pixelformat);
> > + if (!viif_fmt)
> > + return -EINVAL;
> > + }
> > +
> > + /* min/max width, height check */
> > + if (pix->width < VIIF_MIN_OUTPUT_IMG_WIDTH)
> > + pix->width = VIIF_MIN_OUTPUT_IMG_WIDTH;
> > +
> > + if (pix->width > VIIF_MAX_OUTPUT_IMG_WIDTH_ISP)
> > + pix->width = VIIF_MAX_OUTPUT_IMG_WIDTH_ISP;
> > +
> > + if (pix->height < VIIF_MIN_OUTPUT_IMG_HEIGHT)
> > + pix->height = VIIF_MIN_OUTPUT_IMG_HEIGHT;
> > +
> > + if (pix->height > VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP)
> > + pix->height = VIIF_MAX_OUTPUT_IMG_HEIGHT_ISP;
> > +
> > + /* consistency with isp::pad::src::fmt */
> > + if (pix->width != format.format.width)
> > + return -EINVAL;
> > + if (pix->height != format.format.height)
> > + return -EINVAL;
> > +
> > + /* update derived parameters, such as bpp */
> > + viif_calc_plane_sizes(viif_fmt, pix);
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > +
> > + return viif_try_fmt(cap_dev, f);
> > +}
> > +
> > +static int viif_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + int ret = 0;
> > +
> > + if (vb2_is_streaming(&cap_dev->vb2_vq))
>
> That should be vb2_is_busy(). Once buffers are allocated, you can no longer
> change the format since that would change the buffer size as well.
I'll use vb2_is_busy.
> > + return -EBUSY;
> > +
> > + if (f->type != cap_dev->vb2_vq.type)
> > + return -EINVAL;
> > +
> > + ret = viif_try_fmt(cap_dev, f);
> > + if (ret)
> > + return ret;
> > +
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0) {
> > + /*
> > + * A call to main_set_unit() is currently at ioctl(VIDIOC_S_FMT)
> context.
> > + * This call can be moved to viif_isp_s_stream(),
> > + * if you don't want to check the given format is compatible to
> HW.
> > + */
> > + ret = visconti_viif_isp_main_set_unit(viif_dev);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + cap_dev->v4l2_pix = f->fmt.pix_mp;
> > + cap_dev->field = V4L2_FIELD_NONE;
> > +
> > + if (cap_dev->pathid == CAPTURE_PATH_SUB) {
> > + cap_dev->out_format = HWD_VIIF_ONE_COLOR_16;
> > + ret = visconti_viif_isp_sub_set_unit(viif_dev);
> > + } else {
> > + ret = viif_l2_set_format(cap_dev);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > +
> > + f->fmt.pix_mp = cap_dev->v4l2_pix;
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_enum_input(struct file *file, void *priv, struct v4l2_input *inp)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd;
> > + struct v4l2_subdev *v4l2_sd;
> > + int ret;
> > +
> > + if (inp->index >= viif_dev->num_sd)
> > + return -EINVAL;
> > +
> > + viif_sd = &viif_dev->subdevs[inp->index];
> > + v4l2_sd = viif_sd->v4l2_sd;
> > +
> > + ret = v4l2_subdev_call(v4l2_sd, video, g_input_status, &inp->status);
> > + if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
> > + return ret;
> > + inp->type = V4L2_INPUT_TYPE_CAMERA;
> > + inp->std = 0;
> > + if (v4l2_subdev_has_op(v4l2_sd, pad, dv_timings_cap))
> > + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
> > + else
> > + inp->capabilities = V4L2_IN_CAP_STD;
> > + snprintf(inp->name, sizeof(inp->name), "Camera%u: %s", inp->index,
> viif_sd->v4l2_sd->name);
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_g_input(struct file *file, void *priv, unsigned int *i)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > +
> > + *i = viif_dev->sd_index;
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_s_input(struct file *file, void *priv, unsigned int i)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > +
> > + if (i >= viif_dev->num_sd)
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_g_selection(struct file *file, void *priv, struct v4l2_selection *s)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct v4l2_subdev_selection sel = {
> > + .target = V4L2_SEL_TGT_CROP,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + int ret;
> > +
>
> This is missing validation checks for s->type and s->target.
I'll add validation code.
> I've pretty sure you didn't run the v4l2-compliance utility: that would have
> failed on this.
Sorry I didn't know the utility.
I'll apply it.
> > + /* check path id */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> > + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> > + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> > + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> > + else
> > + return -EINVAL;
> > +
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection,
> NULL, &sel);
> > + s->r = sel.r;
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_s_selection(struct file *file, void *priv, struct v4l2_selection *s)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct v4l2_subdev_selection sel = {
> > + .target = V4L2_SEL_TGT_CROP,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + .r = s->r,
> > + };
> > + int ret;
> > +
>
> Same as above.
I'll add validation code.
> > + /* check path id */
> > + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> > + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> > + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> > + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> > + else
> > + return -EINVAL;
> > +
> > + if (s->r.left > VIIF_CROP_MAX_X_ISP || s->r.top >
> VIIF_CROP_MAX_Y_ISP ||
> > + s->r.width < VIIF_CROP_MIN_W || s->r.width >
> VIIF_CROP_MAX_W_ISP ||
> > + s->r.height < VIIF_CROP_MIN_H || s->r.height >
> VIIF_CROP_MAX_H_ISP) {
> > + return -EINVAL;
> > + }
> > +
> > + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, set_selection,
> NULL, &sel);
> > + s->r = sel.r;
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_dv_timings_cap(struct file *file, void *priv_fh, struct
> v4l2_dv_timings_cap *cap)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, dv_timings_cap, cap);
> > +}
> > +
> > +static int viif_enum_dv_timings(struct file *file, void *priv_fh,
> > + struct v4l2_enum_dv_timings *timings)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, enum_dv_timings,
> timings);
> > +}
> > +
> > +static int viif_g_dv_timings(struct file *file, void *priv_fh, struct
> v4l2_dv_timings *timings)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, video, g_dv_timings, timings);
> > +}
> > +
> > +static int viif_s_dv_timings(struct file *file, void *priv_fh, struct
> v4l2_dv_timings *timings)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, video, s_dv_timings, timings);
> > +}
> > +
> > +static int viif_query_dv_timings(struct file *file, void *priv_fh, struct
> v4l2_dv_timings *timings)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, video, query_dv_timings,
> timings);
> > +}
> > +
> > +static int viif_g_edid(struct file *file, void *fh, struct v4l2_edid *edid)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_edid, edid);
> > +}
> > +
> > +static int viif_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > +
> > + return v4l2_subdev_call(viif_sd->v4l2_sd, pad, set_edid, edid);
> > +}
>
> Has this driver been tested with an HDMI receiver? If not, then I would
> recommend
> dropping support for it until you actually can test with such hardware.
>
> The DV_TIMINGS API is for HDMI/DVI/DisplayPort etc. interfaces, it's not
> meant
> for CSI and similar interfaces.
As in my previous reply (for comments from Laurent) for patch 4/5,
these ioctl functions will be removed (because v4l2_subdev_call should not be used in this context).
Currently, this driver is not tested with HDMI receiver
although an evaluation board has a circuit.
I'll remove HDMI support for this patch submission.
> > +
> > +static int viif_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > +
> > + return v4l2_g_parm_cap(video_devdata(file), viif_dev->sd->v4l2_sd, a);
> > +}
> > +
> > +static int viif_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > +
> > + return v4l2_s_parm_cap(video_devdata(file), viif_dev->sd->v4l2_sd, a);
> > +}
> > +
> > +static int viif_enum_framesizes(struct file *file, void *fh, struct
> v4l2_frmsizeenum *fsize)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + struct v4l2_subdev *v4l2_sd = viif_sd->v4l2_sd;
> > + struct v4l2_subdev_frame_size_enum fse = {
> > + .code = viif_sd->mbus_code,
> > + .index = fsize->index,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + int ret;
> > +
> > + ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size, NULL, &fse);
> > + if (ret)
> > + return ret;
> > +
> > + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
> > + fsize->discrete.width = fse.max_width;
> > + fsize->discrete.height = fse.max_height;
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_enum_frameintervals(struct file *file, void *fh, struct
> v4l2_frmivalenum *fival)
> > +{
> > + struct viif_device *viif_dev = video_drvdata_to_capdev(file)->viif_dev;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + struct v4l2_subdev *v4l2_sd = viif_sd->v4l2_sd;
> > + struct v4l2_subdev_frame_interval_enum fie = {
> > + .code = viif_sd->mbus_code,
> > + .index = fival->index,
> > + .width = fival->width,
> > + .height = fival->height,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + int ret;
> > +
> > + ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL, &fie);
> > + if (ret)
> > + return ret;
> > +
> > + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
> > + fival->discrete = fie.interval;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct v4l2_ioctl_ops viif_ioctl_ops = {
> > + .vidioc_querycap = viif_querycap,
> > +
> > + .vidioc_enum_fmt_vid_cap = viif_enum_fmt_vid_cap,
> > + .vidioc_try_fmt_vid_cap_mplane = viif_try_fmt_vid_cap,
> > + .vidioc_s_fmt_vid_cap_mplane = viif_s_fmt_vid_cap,
> > + .vidioc_g_fmt_vid_cap_mplane = viif_g_fmt_vid_cap,
> > +
> > + .vidioc_enum_input = viif_enum_input,
> > + .vidioc_g_input = viif_g_input,
> > + .vidioc_s_input = viif_s_input,
> > +
> > + .vidioc_g_selection = viif_g_selection,
> > + .vidioc_s_selection = viif_s_selection,
> > +
> > + .vidioc_dv_timings_cap = viif_dv_timings_cap,
> > + .vidioc_enum_dv_timings = viif_enum_dv_timings,
> > + .vidioc_g_dv_timings = viif_g_dv_timings,
> > + .vidioc_s_dv_timings = viif_s_dv_timings,
> > + .vidioc_query_dv_timings = viif_query_dv_timings,
> > +
> > + .vidioc_g_edid = viif_g_edid,
> > + .vidioc_s_edid = viif_s_edid,
> > +
> > + .vidioc_g_parm = viif_g_parm,
> > + .vidioc_s_parm = viif_s_parm,
> > +
> > + .vidioc_enum_framesizes = viif_enum_framesizes,
> > + .vidioc_enum_frameintervals = viif_enum_frameintervals,
> > +
> > + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> > + .vidioc_querybuf = vb2_ioctl_querybuf,
> > + .vidioc_qbuf = vb2_ioctl_qbuf,
> > + .vidioc_expbuf = vb2_ioctl_expbuf,
> > + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> > + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> > + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> > + .vidioc_streamon = vb2_ioctl_streamon,
> > + .vidioc_streamoff = vb2_ioctl_streamoff,
> > +
> > + .vidioc_log_status = v4l2_ctrl_log_status,
> > + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
> > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
> > +};
> > +
> > +/* --- File Operations --- */
> > +static int viif_capture_open(struct file *file)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + int ret;
> > +
> > + ret = v4l2_fh_open(file);
> > + if (ret)
> > + return ret;
> > +
> > + return pm_runtime_resume_and_get(viif_dev->dev);
>
> If pm_runtime_resume_and_get fails, then v4l2_fh_release needs
> to be called.
I'll fix it.
> > +}
> > +
> > +static int viif_capture_release(struct file *file)
> > +{
> > + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > +
> > + vb2_fop_release(file);
> > + pm_runtime_put(viif_dev->dev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct v4l2_file_operations viif_fops = {
> > + .owner = THIS_MODULE,
> > + .open = viif_capture_open,
> > + .release = viif_capture_release,
> > + .unlocked_ioctl = video_ioctl2,
> > + .mmap = vb2_fop_mmap,
> > + .poll = vb2_fop_poll,
> > +};
> > +
> > +/* ----- media control callbacks ----- */
> > +static int viif_capture_link_validate(struct media_link *link)
> > +{
> > + /* link validation at start-stream */
> > + return 0;
> > +}
> > +
> > +static const struct media_entity_operations viif_media_ops = {
> > + .link_validate = viif_capture_link_validate,
> > +};
> > +
> > +/* ----- attach ctrl callbacck handler ----- */
> > +int visconti_viif_capture_register_ctrl_handlers(struct viif_device *viif_dev)
> > +{
> > + int ret;
> > +
> > + /* MAIN POST0: merge controls of ISP and CAPTURE0 */
> > + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev0.ctrl_handler,
> > + viif_dev->sd->v4l2_sd->ctrl_handler,
> NULL, true);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Failed to add sensor ctrl_handler");
> > + return ret;
> > + }
> > + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev0.ctrl_handler,
> > + &viif_dev->isp_subdev.ctrl_handler,
> NULL, true);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Failed to add isp subdev ctrl_handler");
> > + return ret;
> > + }
> > +
> > + /* MAIN POST1: merge controls of ISP and CAPTURE0 */
> > + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev1.ctrl_handler,
> > + viif_dev->sd->v4l2_sd->ctrl_handler,
> NULL, true);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Failed to add sensor ctrl_handler");
> > + return ret;
> > + }
> > + ret = v4l2_ctrl_add_handler(&viif_dev->cap_dev1.ctrl_handler,
> > + &viif_dev->isp_subdev.ctrl_handler,
> NULL, true);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Failed to add isp subdev ctrl_handler");
> > + return ret;
> > + }
> > +
> > + /* SUB: no control is exported */
> > +
> > + return 0;
> > +}
> > +
> > +/* ----- register/remove capture device node ----- */
> > +static int visconti_viif_capture_register_node(struct cap_dev *cap_dev)
> > +{
> > + struct viif_device *viif_dev = cap_dev->viif_dev;
> > + struct v4l2_device *v4l2_dev = &viif_dev->v4l2_dev;
> > + struct video_device *vdev = &cap_dev->vdev;
> > + struct vb2_queue *q = &cap_dev->vb2_vq;
> > + static const char *const node_name[] = {
> > + "viif_capture_post0",
> > + "viif_capture_post1",
> > + "viif_capture_sub",
> > + };
> > + int ret;
> > +
> > + INIT_LIST_HEAD(&cap_dev->buf_queue);
> > +
> > + mutex_init(&cap_dev->vlock);
> > +
> > + /* Initialize vb2 queue. */
> > + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
> > + q->io_modes = VB2_DMABUF;
>
> Why is there no VB2_MMAP?
The hardware requests physically contiguous memory for frame buffer.
I'm not sure if memory allocation in VB2_MMAP mode satisfies this restriction.
> > + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> > + q->ops = &viif_vb2_ops;
> > + q->mem_ops = &vb2_dma_contig_memops;
> > + q->drv_priv = cap_dev;
> > + q->buf_struct_size = sizeof(struct viif_buffer);
> > + q->min_buffers_needed = 2;
> > + q->lock = &cap_dev->vlock;
> > + q->dev = viif_dev->v4l2_dev.dev;
> > +
> > + ret = vb2_queue_init(q);
> > + if (ret)
> > + return ret;
> > +
> > + /* Register the video device. */
> > + strscpy(vdev->name, node_name[cap_dev->pathid],
> sizeof(vdev->name));
> > + vdev->v4l2_dev = v4l2_dev;
> > + vdev->lock = &cap_dev->vlock;
> > + vdev->queue = &cap_dev->vb2_vq;
> > + vdev->ctrl_handler = NULL;
> > + vdev->fops = &viif_fops;
> > + vdev->ioctl_ops = &viif_ioctl_ops;
> > + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
> V4L2_CAP_STREAMING;
> > + vdev->device_caps |= V4L2_CAP_IO_MC;
> > + vdev->entity.ops = &viif_media_ops;
> > + vdev->release = video_device_release_empty;
> > + video_set_drvdata(vdev, cap_dev);
> > + vdev->vfl_dir = VFL_DIR_RX;
> > + cap_dev->capture_pad.flags = MEDIA_PAD_FL_SINK;
> > +
> > + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> > + if (ret < 0) {
> > + dev_err(v4l2_dev->dev, "video_register_device failed: %d\n",
> ret);
> > + return ret;
> > + }
> > +
> > + ret = media_entity_pads_init(&vdev->entity, 1,
> &cap_dev->capture_pad);
> > + if (ret) {
> > + video_unregister_device(vdev);
> > + return ret;
> > + }
> > +
> > + ret = v4l2_ctrl_handler_init(&cap_dev->ctrl_handler, 30);
> > + if (ret)
> > + return -ENOMEM;
> > +
> > + cap_dev->vdev.ctrl_handler = &cap_dev->ctrl_handler;
> > +
> > + return 0;
> > +}
> > +
> > +int visconti_viif_capture_register(struct viif_device *viif_dev)
> > +{
> > + int ret;
> > +
> > + /* register MAIN POST0 (primary RGB output)*/
> > + viif_dev->cap_dev0.pathid = CAPTURE_PATH_MAIN_POST0;
> > + viif_dev->cap_dev0.viif_dev = viif_dev;
> > + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev0);
> > + if (ret)
> > + return ret;
> > +
> > + /* register MAIN POST1 (additional RGB output)*/
> > + viif_dev->cap_dev1.pathid = CAPTURE_PATH_MAIN_POST1;
> > + viif_dev->cap_dev1.viif_dev = viif_dev;
> > + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev1);
> > + if (ret)
> > + return ret;
> > +
> > + /* register SUB (RAW output) */
> > + viif_dev->cap_dev2.pathid = CAPTURE_PATH_SUB;
> > + viif_dev->cap_dev2.viif_dev = viif_dev;
> > + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev2);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static void visconti_viif_capture_unregister_node(struct cap_dev *cap_dev)
> > +{
> > + media_entity_cleanup(&cap_dev->vdev.entity);
> > + v4l2_ctrl_handler_free(&cap_dev->ctrl_handler);
> > + vb2_video_unregister_device(&cap_dev->vdev);
> > + mutex_destroy(&cap_dev->vlock);
> > +}
> > +
> > +void visconti_viif_capture_unregister(struct viif_device *viif_dev)
> > +{
> > + visconti_viif_capture_unregister_node(&viif_dev->cap_dev0);
> > + visconti_viif_capture_unregister_node(&viif_dev->cap_dev1);
> > + visconti_viif_capture_unregister_node(&viif_dev->cap_dev2);
> > +}
> > diff --git a/drivers/media/platform/visconti/viif_isp.c
> b/drivers/media/platform/visconti/viif_isp.c
> > new file mode 100644
> > index 00000000000..9314e6e8661
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/viif_isp.c
> > @@ -0,0 +1,846 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <media/v4l2-common.h>
> > +#include <media/v4l2-subdev.h>
> > +
> > +#include "viif.h"
> > +
> > +/* ----- supported MBUS formats ----- */
> > +struct visconti_mbus_format {
> > + unsigned int code;
> > + unsigned int bpp;
> > + int rgb_out;
> > +} static visconti_mbus_formats[] = {
> > + { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .rgb_out = 1 },
> > + { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_UYVY10_1X20, .bpp = 20, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, .rgb_out = 1 },
> > + { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, .rgb_out = 0 },
> > + { .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, .rgb_out = 0 },
> > +};
> > +
> > +static int viif_get_mbus_rgb_out(unsigned int mbus_code)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
> > + if (visconti_mbus_formats[i].code == mbus_code)
> > + return visconti_mbus_formats[i].rgb_out;
> > +
> > + /* YUV intermediate code by default */
> > + return 0;
> > +}
> > +
> > +static unsigned int viif_get_mbus_bpp(unsigned int mbus_code)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
> > + if (visconti_mbus_formats[i].code == mbus_code)
> > + return visconti_mbus_formats[i].bpp;
> > +
> > + /* default bpp value */
> > + return 24;
> > +}
> > +
> > +static bool viif_is_valid_mbus_code(unsigned int mbus_code)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(visconti_mbus_formats); i++)
> > + if (visconti_mbus_formats[i].code == mbus_code)
> > + return true;
> > + return false;
> > +}
> > +
> > +/* ----- handling main processing path ----- */
> > +static int viif_get_dv_timings(struct viif_device *viif_dev, struct
> v4l2_dv_timings *timings)
> > +{
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + struct v4l2_subdev_pad_config pad_cfg;
> > + struct v4l2_subdev_state pad_state = {
> > + .pads = &pad_cfg,
> > + };
> > + struct v4l2_subdev_format format = {
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + .pad = 0,
> > + };
> > + struct v4l2_ctrl *ctrl;
> > + int ret;
> > +
> > + /* some video I/F support dv_timings query */
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, video, g_dv_timings, timings);
> > + if (ret == 0)
> > + return 0;
> > +
> > + /* others: call some discrete APIs */
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, &pad_state,
> &format);
> > + if (ret != 0)
> > + return ret;
> > +
> > + timings->bt.width = format.format.width;
> > + timings->bt.height = format.format.height;
> > +
> > + ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler,
> V4L2_CID_HBLANK);
> > + if (!ctrl) {
> > + dev_err(viif_dev->dev, "subdev: V4L2_CID_VBLANK error.\n");
> > + return -EINVAL;
> > + }
> > + timings->bt.hsync = v4l2_ctrl_g_ctrl(ctrl);
> > +
> > + ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler,
> V4L2_CID_VBLANK);
> > + if (!ctrl) {
> > + dev_err(viif_dev->dev, "subdev: V4L2_CID_VBLANK error.\n");
> > + return -EINVAL;
> > + }
> > + timings->bt.vsync = v4l2_ctrl_g_ctrl(ctrl);
> > +
> > + ctrl = v4l2_ctrl_find(viif_sd->v4l2_sd->ctrl_handler,
> V4L2_CID_PIXEL_RATE);
> > + if (!ctrl) {
> > + dev_err(viif_dev->dev, "subdev: V4L2_CID_PIXEL_RATE
> error.\n");
> > + return -EINVAL;
> > + }
> > + timings->bt.pixelclock = v4l2_ctrl_g_ctrl_int64(ctrl);
> > +
> > + return 0;
> > +}
> > +
> > +int visconti_viif_isp_main_set_unit(struct viif_device *viif_dev)
> > +{
> > + unsigned int dt_image, color_type, rawpack, yuv_conv;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + struct hwd_viif_input_img in_img_main;
> > + struct viif_l2_undist undist = { 0 };
> > + struct v4l2_dv_timings timings;
> > + struct v4l2_subdev_format fmt = {
> > + .pad = 0,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + int mag_hactive = 1;
> > + int ret = 0;
> > +
> > + ret = viif_get_dv_timings(viif_dev, &timings);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "could not get timing information of
> subdev");
> > + return -EINVAL;
> > + }
> > +
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, NULL, &fmt);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "could not get pad information of
> subdev");
> > + return -EINVAL;
> > + }
> > +
> > + switch (fmt.format.code) {
> > + case MEDIA_BUS_FMT_RGB888_1X24:
> > + dt_image = VISCONTI_CSI2_DT_RGB888;
> > + break;
> > + case MEDIA_BUS_FMT_UYVY8_1X16:
> > + dt_image = VISCONTI_CSI2_DT_YUV4228B;
> > + break;
> > + case MEDIA_BUS_FMT_UYVY10_1X20:
> > + dt_image = VISCONTI_CSI2_DT_YUV42210B;
> > + break;
> > + case MEDIA_BUS_FMT_RGB565_1X16:
> > + dt_image = VISCONTI_CSI2_DT_RGB565;
> > + break;
> > + case MEDIA_BUS_FMT_SBGGR8_1X8:
> > + case MEDIA_BUS_FMT_SGBRG8_1X8:
> > + case MEDIA_BUS_FMT_SGRBG8_1X8:
> > + case MEDIA_BUS_FMT_SRGGB8_1X8:
> > + dt_image = VISCONTI_CSI2_DT_RAW8;
> > + break;
> > + case MEDIA_BUS_FMT_SRGGB10_1X10:
> > + case MEDIA_BUS_FMT_SGRBG10_1X10:
> > + case MEDIA_BUS_FMT_SGBRG10_1X10:
> > + case MEDIA_BUS_FMT_SBGGR10_1X10:
> > + dt_image = VISCONTI_CSI2_DT_RAW10;
> > + break;
> > + case MEDIA_BUS_FMT_SRGGB12_1X12:
> > + case MEDIA_BUS_FMT_SGRBG12_1X12:
> > + case MEDIA_BUS_FMT_SGBRG12_1X12:
> > + case MEDIA_BUS_FMT_SBGGR12_1X12:
> > + dt_image = VISCONTI_CSI2_DT_RAW12;
> > + break;
> > + case MEDIA_BUS_FMT_SRGGB14_1X14:
> > + case MEDIA_BUS_FMT_SGRBG14_1X14:
> > + case MEDIA_BUS_FMT_SGBRG14_1X14:
> > + case MEDIA_BUS_FMT_SBGGR14_1X14:
> > + dt_image = VISCONTI_CSI2_DT_RAW14;
> > + break;
> > + default:
> > + dt_image = VISCONTI_CSI2_DT_RGB888;
> > + break;
> > + }
> > +
> > + color_type = dt_image;
> > +
> > + if (color_type == VISCONTI_CSI2_DT_RAW8 || color_type ==
> VISCONTI_CSI2_DT_RAW10 ||
> > + color_type == VISCONTI_CSI2_DT_RAW12) {
> > + rawpack = viif_dev->rawpack_mode;
> > + if (rawpack != HWD_VIIF_RAWPACK_DISABLE)
> > + mag_hactive = 2;
> > + } else {
> > + rawpack = HWD_VIIF_RAWPACK_DISABLE;
> > + }
> > +
> > + if (color_type == VISCONTI_CSI2_DT_YUV4228B || color_type ==
> VISCONTI_CSI2_DT_YUV42210B)
> > + yuv_conv = HWD_VIIF_YUV_CONV_INTERPOLATION;
> > + else
> > + yuv_conv = HWD_VIIF_YUV_CONV_REPEAT;
> > +
> > + in_img_main.hactive_size = timings.bt.width;
> > + in_img_main.vactive_size = timings.bt.height;
> > + in_img_main.htotal_size = timings.bt.width * mag_hactive +
> timings.bt.hsync;
> > + in_img_main.vtotal_size = timings.bt.height + timings.bt.vsync;
> > + in_img_main.pixel_clock = timings.bt.pixelclock / 1000;
> > + in_img_main.vbp_size = timings.bt.vsync - 5;
> > +
> > + in_img_main.interpolation_mode =
> HWD_VIIF_L1_INPUT_INTERPOLATION_LINE;
> > + in_img_main.input_num = 1;
> > + in_img_main.hobc_width = 0;
> > + in_img_main.hobc_margin = 0;
> > +
> > + /* configuration of MAIN unit */
> > + ret = hwd_viif_main_set_unit(viif_dev->hwd_res, dt_image,
> &in_img_main, color_type, rawpack,
> > + yuv_conv);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "main_set_unit error. %d\n", ret);
> > + return ret;
> > + }
> > +
> > + /* Enable regbuf */
> > + hwd_viif_isp_set_regbuf_auto_transmission(viif_dev->hwd_res);
> > +
> > + /* L2 UNDIST Enable through mode as default */
> > + undist.through_mode = HWD_VIIF_ENABLE;
> > + undist.sensor_crop_ofs_h = 1 - in_img_main.hactive_size;
> > + undist.sensor_crop_ofs_v = 1 - in_img_main.vactive_size;
> > + undist.grid_node_num_h = 16;
> > + undist.grid_node_num_v = 16;
> > + ret = hwd_viif_l2_set_undist(viif_dev->hwd_res, &undist);
> > + if (ret)
> > + dev_err(viif_dev->dev, "l2_set_undist error. %d\n", ret);
> > + return ret;
> > +}
> > +
> > +static unsigned int dt_image_from_mbus_code(unsigned int mbus_code)
> > +{
> > + switch (mbus_code) {
> > + case MEDIA_BUS_FMT_RGB888_1X24:
> > + return VISCONTI_CSI2_DT_RGB888;
> > + case MEDIA_BUS_FMT_UYVY8_1X16:
> > + return VISCONTI_CSI2_DT_YUV4228B;
> > + case MEDIA_BUS_FMT_UYVY10_1X20:
> > + return VISCONTI_CSI2_DT_YUV42210B;
> > + case MEDIA_BUS_FMT_RGB565_1X16:
> > + return VISCONTI_CSI2_DT_RGB565;
> > + case MEDIA_BUS_FMT_SBGGR8_1X8:
> > + case MEDIA_BUS_FMT_SGBRG8_1X8:
> > + case MEDIA_BUS_FMT_SGRBG8_1X8:
> > + case MEDIA_BUS_FMT_SRGGB8_1X8:
> > + return VISCONTI_CSI2_DT_RAW8;
> > + case MEDIA_BUS_FMT_SRGGB10_1X10:
> > + case MEDIA_BUS_FMT_SGRBG10_1X10:
> > + case MEDIA_BUS_FMT_SGBRG10_1X10:
> > + case MEDIA_BUS_FMT_SBGGR10_1X10:
> > + return VISCONTI_CSI2_DT_RAW10;
> > + case MEDIA_BUS_FMT_SRGGB12_1X12:
> > + case MEDIA_BUS_FMT_SGRBG12_1X12:
> > + case MEDIA_BUS_FMT_SGBRG12_1X12:
> > + case MEDIA_BUS_FMT_SBGGR12_1X12:
> > + return VISCONTI_CSI2_DT_RAW12;
> > + case MEDIA_BUS_FMT_SRGGB14_1X14:
> > + case MEDIA_BUS_FMT_SGRBG14_1X14:
> > + case MEDIA_BUS_FMT_SGBRG14_1X14:
> > + case MEDIA_BUS_FMT_SBGGR14_1X14:
> > + return VISCONTI_CSI2_DT_RAW14;
> > + default:
> > + return VISCONTI_CSI2_DT_RGB888;
> > + }
> > +}
> > +
> > +int visconti_viif_isp_sub_set_unit(struct viif_device *viif_dev)
> > +{
> > + struct hwd_viif_input_img in_img_sub;
> > + struct v4l2_dv_timings timings;
> > + struct v4l2_subdev_format fmt = {
> > + .pad = 0,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + unsigned int dt_image;
> > + int ret;
> > +
> > + ret = viif_get_dv_timings(viif_dev, &timings);
> > + if (ret)
> > + return -EINVAL;
> > +
> > + ret = v4l2_subdev_call(viif_dev->sd->v4l2_sd, pad, get_fmt, NULL,
> &fmt);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "could not get pad information of
> subdev");
> > + return -EINVAL;
> > + }
> > +
> > + dt_image = dt_image_from_mbus_code(fmt.format.code);
> > +
> > + in_img_sub.hactive_size = 0;
> > + in_img_sub.vactive_size = timings.bt.height;
> > + in_img_sub.htotal_size = timings.bt.width + timings.bt.hsync;
> > + in_img_sub.vtotal_size = timings.bt.height + timings.bt.vsync;
> > + in_img_sub.pixel_clock = timings.bt.pixelclock / 1000;
> > + in_img_sub.vbp_size = timings.bt.vsync - 5;
> > + in_img_sub.interpolation_mode =
> HWD_VIIF_L1_INPUT_INTERPOLATION_LINE;
> > + in_img_sub.input_num = 1;
> > + in_img_sub.hobc_width = 0;
> > + in_img_sub.hobc_margin = 0;
> > +
> > + ret = hwd_viif_sub_set_unit(viif_dev->hwd_res, dt_image,
> &in_img_sub);
> > + if (ret)
> > + dev_err(viif_dev->dev, "sub_set_unit error. %d\n", ret);
> > +
> > + return ret;
> > +};
> > +
> > +/* ----- handling CSI2RX hardware ----- */
> > +static int viif_csi2rx_initialize(struct viif_device *viif_dev)
> > +{
> > + struct hwd_viif_csi2rx_line_err_target err_target = { 0 };
> > + struct hwd_viif_csi2rx_irq_mask csi2rx_mask;
> > + struct viif_subdev *viif_sd = viif_dev->sd;
> > + struct v4l2_mbus_config cfg = { 0 };
> > + struct v4l2_subdev_format fmt = {
> > + .pad = 0,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + struct v4l2_dv_timings timings;
> > + int num_lane, dphy_rate;
> > + int ret;
> > +
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_mbus_config, 0,
> &cfg);
> > + if (ret) {
> > + dev_dbg(viif_dev->dev, "subdev: g_mbus_config error. %d\n",
> ret);
> > + num_lane = viif_sd->num_lane;
> > + } else {
> > + if (cfg.type != V4L2_MBUS_CSI2_DPHY)
> > + return -EINVAL;
> > + num_lane = cfg.bus.mipi_csi2.num_data_lanes;
> > + }
> > +
> > + ret = v4l2_subdev_call(viif_sd->v4l2_sd, pad, get_fmt, 0, &fmt);
> > + if (ret)
> > + return -EINVAL;
> > +
> > + ret = viif_get_dv_timings(viif_dev, &timings);
> > + if (ret)
> > + return -EINVAL;
> > +
> > + dphy_rate = (timings.bt.pixelclock / 1000) *
> viif_get_mbus_bpp(fmt.format.code) / num_lane;
> > + dphy_rate = dphy_rate / 1000;
> > +
> > + /* check error for CH0: all supported DTs */
> > + err_target.dt[0] = VISCONTI_CSI2_DT_RGB565;
> > + err_target.dt[1] = VISCONTI_CSI2_DT_YUV4228B;
> > + err_target.dt[2] = VISCONTI_CSI2_DT_YUV42210B;
> > + err_target.dt[3] = VISCONTI_CSI2_DT_RGB888;
> > + err_target.dt[4] = VISCONTI_CSI2_DT_RAW8;
> > + err_target.dt[5] = VISCONTI_CSI2_DT_RAW10;
> > + err_target.dt[6] = VISCONTI_CSI2_DT_RAW12;
> > + err_target.dt[7] = VISCONTI_CSI2_DT_RAW14;
> > +
> > + /* Define errors to be masked */
> > + csi2rx_mask.mask[0] = 0x0000000F; /*check all for PHY_FATAL*/
> > + csi2rx_mask.mask[1] = 0x0001000F; /*check all for PKT_FATAL*/
> > + csi2rx_mask.mask[2] = 0x000F0F0F; /*check all for FRAME_FATAL*/
> > + csi2rx_mask.mask[3] = 0x000F000F; /*check all for PHY*/
> > + csi2rx_mask.mask[4] = 0x000F000F; /*check all for PKT*/
> > + csi2rx_mask.mask[5] = 0x00FF00FF; /*check all for LINE*/
> > +
> > + return hwd_viif_csi2rx_initialize(viif_dev->hwd_res, num_lane,
> HWD_VIIF_CSI2_DPHY_L0L1L2L3,
> > + dphy_rate, HWD_VIIF_ENABLE,
> &err_target, &csi2rx_mask);
> > +}
> > +
> > +static int viif_csi2rx_start(struct viif_device *viif_dev)
> > +{
> > + struct hwd_viif_csi2rx_packet packet = { 0 };
> > + u32 vc_main = 0;
> > + u32 vc_sub = 0;
> > +
> > + viif_dev->masked_gamma_path = 0U;
> > +
> > + return hwd_viif_csi2rx_start(viif_dev->hwd_res, vc_main, vc_sub,
> &packet);
> > +}
> > +
> > +static int viif_csi2rx_stop(struct viif_device *viif_dev)
> > +{
> > + s32 ret;
> > +
> > + ret = hwd_viif_csi2rx_stop(viif_dev->hwd_res);
> > + if (ret)
> > + dev_err(viif_dev->dev, "csi2rx_stop error. %d\n", ret);
> > +
> > + hwd_viif_csi2rx_uninitialize(viif_dev->hwd_res);
> > +
> > + return ret;
> > +}
> > +
> > +/* ----- subdevice video operations ----- */
> > +static int visconti_viif_isp_s_stream(struct v4l2_subdev *sd, int enable)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + int ret;
> > +
> > + if (enable) {
> > + ret = viif_csi2rx_initialize(viif_dev);
> > + if (ret)
> > + return ret;
> > + return viif_csi2rx_start(viif_dev);
> > + } else {
> > + return viif_csi2rx_stop(viif_dev);
> > + }
> > +}
> > +
> > +/* ----- subdevice pad operations ----- */
> > +static int visconti_viif_isp_enum_mbus_code(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_state
> *sd_state,
> > + struct
> v4l2_subdev_mbus_code_enum *code)
> > +{
> > + if (code->pad == 0) {
> > + /* sink */
> > + if (code->index > ARRAY_SIZE(visconti_mbus_formats) - 1)
> > + return -EINVAL;
> > + code->code = visconti_mbus_formats[code->index].code;
> > + return 0;
> > + }
> > +
> > + /* source */
> > + if (code->index > 0)
> > + return -EINVAL;
> > + code->code = MEDIA_BUS_FMT_YUV8_1X24;
> > + return 0;
> > +}
> > +
> > +static struct v4l2_mbus_framefmt *visconti_viif_isp_get_pad_fmt(struct
> v4l2_subdev *sd,
> > + struct
> v4l2_subdev_state *sd_state,
> > + unsigned int
> pad, u32 which)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + struct v4l2_subdev_state state = {
> > + .pads = viif_dev->isp_subdev.pad_cfg,
> > + };
> > +
> > + if (which == V4L2_SUBDEV_FORMAT_TRY)
> > + return v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd,
> sd_state, pad);
> > + else
> > + return v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd,
> &state, pad);
> > +}
> > +
> > +static struct v4l2_rect *visconti_viif_isp_get_pad_crop(struct v4l2_subdev
> *sd,
> > + struct
> v4l2_subdev_state *sd_state,
> > + unsigned int pad,
> u32 which)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + struct v4l2_subdev_state state = {
> > + .pads = viif_dev->isp_subdev.pad_cfg,
> > + };
> > +
> > + if (which == V4L2_SUBDEV_FORMAT_TRY)
> > + return v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd,
> sd_state, pad);
> > + else
> > + return v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd,
> &state, pad);
> > +}
> > +
> > +static struct v4l2_rect *visconti_viif_isp_get_pad_compose(struct
> v4l2_subdev *sd,
> > + struct
> v4l2_subdev_state *sd_state,
> > + unsigned int pad,
> u32 which)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + struct v4l2_subdev_state state = {
> > + .pads = viif_dev->isp_subdev.pad_cfg,
> > + };
> > +
> > + if (which == V4L2_SUBDEV_FORMAT_TRY)
> > + return
> v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, sd_state, pad);
> > + else
> > + return
> v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd, &state, pad);
> > +}
> > +
> > +static int visconti_viif_isp_get_fmt(struct v4l2_subdev *sd, struct
> v4l2_subdev_state *sd_state,
> > + struct v4l2_subdev_format *fmt)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > +
> > + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> > + fmt->format = *visconti_viif_isp_get_pad_fmt(sd, sd_state, fmt->pad,
> fmt->which);
> > + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> > +
> > + return 0;
> > +}
> > +
> > +static void visconti_viif_isp_set_sink_fmt(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_state
> *sd_state,
> > + struct v4l2_mbus_framefmt
> *format, u32 which)
> > +{
> > + struct v4l2_mbus_framefmt *sink_fmt, *src0_fmt, *src1_fmt, *src2_fmt;
> > +
> > + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SINK, which);
> > + src0_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SRC_PATH0, which);
> > + src1_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SRC_PATH1, which);
> > + src2_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SRC_PATH2, which);
> > +
> > + /* update mbus code only if it's available */
> > + if (viif_is_valid_mbus_code(format->code))
> > + sink_fmt->code = format->code;
> > +
> > + /* sink::mbus_code is derived from src::mbus_code */
> > + if (viif_get_mbus_rgb_out(sink_fmt->code)) {
> > + src0_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
> > + src1_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
> > + } else {
> > + src0_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> > + src1_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> > + }
> > +
> > + /* SRC2 (RAW output) follows SINK format */
> > + src2_fmt->code = format->code;
> > + src2_fmt->width = format->width;
> > + src2_fmt->height = format->height;
> > +
> > + /* size check */
> > + sink_fmt->width = format->width;
> > + sink_fmt->height = format->height;
> > +
> > + *format = *sink_fmt;
> > +}
> > +
> > +static void visconti_viif_isp_set_src_fmt(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_state *sd_state,
> > + struct v4l2_mbus_framefmt *format,
> unsigned int pad,
> > + u32 which)
> > +{
> > + struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
> > + struct v4l2_rect *src_crop;
> > +
> > + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SINK,
> > +
> V4L2_SUBDEV_FORMAT_ACTIVE);
> > + src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, pad, which);
> > + src_crop = visconti_viif_isp_get_pad_crop(sd, sd_state, pad, which);
> > +
> > + /* sink::mbus_code is derived from src::mbus_code */
> > + if (viif_get_mbus_rgb_out(sink_fmt->code))
> > + src_fmt->code = MEDIA_BUS_FMT_RGB888_1X24;
> > + else
> > + src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> > +
> > + /*size check*/
> > + src_fmt->width = format->width;
> > + src_fmt->height = format->height;
> > +
> > + /*update crop*/
> > + src_crop->width = format->width;
> > + src_crop->height = format->height;
> > +
> > + *format = *src_fmt;
> > +}
> > +
> > +static void visconti_viif_isp_set_src_fmt_rawpath(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_state
> *sd_state,
> > + struct
> v4l2_mbus_framefmt *format,
> > + unsigned int pad, u32
> which)
> > +{
> > + struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
> > +
> > + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SINK,
> > +
> V4L2_SUBDEV_FORMAT_ACTIVE);
> > + src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state, pad, which);
> > +
> > + /* RAWPATH SRC pad has just the same configuration as SINK pad */
> > + src_fmt->code = sink_fmt->code;
> > + src_fmt->width = sink_fmt->width;
> > + src_fmt->height = sink_fmt->height;
> > +
> > + *format = *src_fmt;
> > +}
> > +
> > +static int visconti_viif_isp_set_fmt(struct v4l2_subdev *sd, struct
> v4l2_subdev_state *sd_state,
> > + struct v4l2_subdev_format *fmt)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > +
> > + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> > +
> > + if (fmt->pad == VIIF_ISP_PAD_SINK)
> > + visconti_viif_isp_set_sink_fmt(sd, sd_state, &fmt->format,
> fmt->which);
> > + else if (fmt->pad == VIIF_ISP_PAD_SRC_PATH2)
> > + visconti_viif_isp_set_src_fmt_rawpath(sd, sd_state,
> &fmt->format, fmt->pad,
> > + fmt->which);
> > + else
> > + visconti_viif_isp_set_src_fmt(sd, sd_state, &fmt->format,
> fmt->pad, fmt->which);
> > +
> > + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> > +
> > + return 0;
> > +}
> > +
> > +#define VISCONTI_VIIF_ISP_DEFAULT_WIDTH 1920
> > +#define VISCONTI_VIIF_ISP_DEFAULT_HEIGHT 1080
> > +#define VISCONTI_VIIF_MAX_COMPOSED_WIDTH 8190
> > +#define VISCONTI_VIIF_MAX_COMPOSED_HEIGHT 4094
> > +
> > +static int visconti_viif_isp_init_config(struct v4l2_subdev *sd, struct
> v4l2_subdev_state *sd_state)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
> > + struct v4l2_rect *src_crop, *sink_compose;
> > +
> > + sink_fmt =
> > + v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd,
> sd_state, VIIF_ISP_PAD_SINK);
> > + sink_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + sink_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > + sink_fmt->field = V4L2_FIELD_NONE;
> > + sink_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
> > +
> > + sink_compose =
> > + v4l2_subdev_get_try_compose(&viif_dev->isp_subdev.sd,
> sd_state, VIIF_ISP_PAD_SINK);
> > + sink_compose->top = 0;
> > + sink_compose->left = 0;
> > + sink_compose->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + sink_compose->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > +
> > + src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd,
> sd_state,
> > + VIIF_ISP_PAD_SRC_PATH0);
> > + src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > + src_fmt->field = V4L2_FIELD_NONE;
> > + src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> > +
> > + src_crop = v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd,
> sd_state,
> > + VIIF_ISP_PAD_SRC_PATH0);
> > + src_crop->top = 0;
> > + src_crop->left = 0;
> > + src_crop->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + src_crop->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > +
> > + src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd,
> sd_state,
> > + VIIF_ISP_PAD_SRC_PATH1);
> > + src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > + src_fmt->field = V4L2_FIELD_NONE;
> > + src_fmt->code = MEDIA_BUS_FMT_YUV8_1X24;
> > +
> > + src_crop = v4l2_subdev_get_try_crop(&viif_dev->isp_subdev.sd,
> sd_state,
> > + VIIF_ISP_PAD_SRC_PATH1);
> > + src_crop->top = 0;
> > + src_crop->left = 0;
> > + src_crop->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + src_crop->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > +
> > + src_fmt = v4l2_subdev_get_try_format(&viif_dev->isp_subdev.sd,
> sd_state,
> > + VIIF_ISP_PAD_SRC_PATH2);
> > + src_fmt->width = VISCONTI_VIIF_ISP_DEFAULT_WIDTH;
> > + src_fmt->height = VISCONTI_VIIF_ISP_DEFAULT_HEIGHT;
> > + src_fmt->field = V4L2_FIELD_NONE;
> > + src_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
> > +
> > + return 0;
> > +}
> > +
> > +static int visconti_viif_isp_get_selection(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_state
> *sd_state,
> > + struct v4l2_subdev_selection *sel)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + struct v4l2_mbus_framefmt *sink_fmt;
> > + int ret = -EINVAL;
> > +
> > + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> > + if (sel->pad == VIIF_ISP_PAD_SINK) {
> > + /* SINK PAD */
> > + switch (sel->target) {
> > + case V4L2_SEL_TGT_CROP:
> > + sink_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> VIIF_ISP_PAD_SINK,
> > +
> sel->which);
> > + sel->r.top = 0;
> > + sel->r.left = 0;
> > + sel->r.width = sink_fmt->width;
> > + sel->r.height = sink_fmt->height;
> > + ret = 0;
> > + break;
> > + case V4L2_SEL_TGT_COMPOSE:
> > + sel->r = *visconti_viif_isp_get_pad_compose(sd,
> sd_state, VIIF_ISP_PAD_SINK,
> > +
> sel->which);
> > + ret = 0;
> > + break;
> > + case V4L2_SEL_TGT_COMPOSE_BOUNDS:
> > + /* fixed value */
> > + sel->r.top = 0;
> > + sel->r.left = 0;
> > + sel->r.width =
> VISCONTI_VIIF_MAX_COMPOSED_WIDTH;
> > + sel->r.height =
> VISCONTI_VIIF_MAX_COMPOSED_HEIGHT;
> > + ret = 0;
> > + break;
> > + }
> > + } else if ((sel->pad == VIIF_ISP_PAD_SRC_PATH0) || (sel->pad ==
> VIIF_ISP_PAD_SRC_PATH1)) {
> > + /* SRC PAD */
> > + switch (sel->target) {
> > + case V4L2_SEL_TGT_CROP:
> > + sel->r =
> > + *visconti_viif_isp_get_pad_crop(sd, sd_state,
> sel->pad, sel->which);
> > + ret = 0;
> > + break;
> > + }
> > + }
> > + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> > +
> > + return ret;
> > +}
> > +
> > +static int visconti_viif_isp_set_selection(struct v4l2_subdev *sd,
> > + struct v4l2_subdev_state
> *sd_state,
> > + struct v4l2_subdev_selection *sel)
> > +{
> > + struct viif_device *viif_dev = ((struct isp_subdev *)sd)->viif_dev;
> > + struct v4l2_mbus_framefmt *src_fmt;
> > + struct v4l2_rect *rect, *rect_compose;
> > + int ret = -EINVAL;
> > +
> > + mutex_lock(&viif_dev->isp_subdev.ops_lock);
> > + /* only source::selection::crop is writable */
> > + if (sel->pad == VIIF_ISP_PAD_SRC_PATH0 || sel->pad ==
> VIIF_ISP_PAD_SRC_PATH1) {
> > + switch (sel->target) {
> > + case V4L2_SEL_TGT_CROP: {
> > + /* check if new SRC::CROP is inside SINK::COMPOSE
> */
> > + rect_compose = visconti_viif_isp_get_pad_compose(
> > + sd, sd_state, VIIF_ISP_PAD_SINK,
> sel->which);
> > + if (sel->r.top < rect_compose->top || sel->r.left <
> rect_compose->left ||
> > + (sel->r.top + sel->r.height) >
> > + (rect_compose->top +
> rect_compose->height) ||
> > + (sel->r.left + sel->r.width) >
> > + (rect_compose->left +
> rect_compose->width)) {
> > + break;
> > + }
> > +
> > + rect = visconti_viif_isp_get_pad_crop(sd, sd_state,
> sel->pad, sel->which);
> > + *rect = sel->r;
> > +
> > + /* update SRC::FMT along with SRC::CROP */
> > + src_fmt = visconti_viif_isp_get_pad_fmt(sd, sd_state,
> sel->pad, sel->which);
> > + src_fmt->width = sel->r.width;
> > + src_fmt->height = sel->r.height;
> > + ret = 0;
> > + break;
> > + }
> > + }
> > + }
> > + mutex_unlock(&viif_dev->isp_subdev.ops_lock);
> > +
> > + return ret;
> > +}
> > +
> > +void visconti_viif_isp_set_compose_rect(struct viif_device *viif_dev,
> > + struct viif_l2_roi_config *roi)
> > +{
> > + struct v4l2_rect *rect;
> > +
> > + rect = visconti_viif_isp_get_pad_compose(&viif_dev->isp_subdev.sd,
> NULL, VIIF_ISP_PAD_SINK,
> > +
> V4L2_SUBDEV_FORMAT_ACTIVE);
> > + rect->top = 0;
> > + rect->left = 0;
> > + rect->width = roi->corrected_hsize[0];
> > + rect->height = roi->corrected_vsize[0];
> > +}
> > +
> > +static const struct media_entity_operations visconti_viif_isp_media_ops = {
> > + .link_validate = v4l2_subdev_link_validate,
> > +};
> > +
> > +static const struct v4l2_subdev_pad_ops visconti_viif_isp_pad_ops = {
> > + .enum_mbus_code = visconti_viif_isp_enum_mbus_code,
> > + .get_selection = visconti_viif_isp_get_selection,
> > + .set_selection = visconti_viif_isp_set_selection,
> > + .init_cfg = visconti_viif_isp_init_config,
> > + .get_fmt = visconti_viif_isp_get_fmt,
> > + .set_fmt = visconti_viif_isp_set_fmt,
> > + .link_validate = v4l2_subdev_link_validate_default,
> > +};
> > +
> > +static const struct v4l2_subdev_video_ops visconti_viif_isp_video_ops = {
> > + .s_stream = visconti_viif_isp_s_stream,
> > +};
> > +
> > +static const struct v4l2_subdev_ops visconti_viif_isp_ops = {
> > + .video = &visconti_viif_isp_video_ops,
> > + .pad = &visconti_viif_isp_pad_ops,
> > +};
> > +
> > +/* ----- register/remove isp subdevice node ----- */
> > +int visconti_viif_isp_register(struct viif_device *viif_dev)
> > +{
> > + struct v4l2_subdev_state state = {
> > + .pads = viif_dev->isp_subdev.pad_cfg,
> > + };
> > + struct media_pad *pads = viif_dev->isp_subdev.pads;
> > + struct v4l2_subdev *sd = &viif_dev->isp_subdev.sd;
> > + int ret;
> > +
> > + viif_dev->isp_subdev.viif_dev = viif_dev;
> > +
> > + v4l2_subdev_init(sd, &visconti_viif_isp_ops);
> > + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> > + sd->entity.ops = &visconti_viif_isp_media_ops;
> > + sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
> > + sd->owner = THIS_MODULE;
> > + strscpy(sd->name, "visconti-viif:isp", sizeof(sd->name));
> > +
> > + pads[0].flags = MEDIA_PAD_FL_SINK |
> MEDIA_PAD_FL_MUST_CONNECT;
> > + pads[1].flags = MEDIA_PAD_FL_SOURCE |
> MEDIA_PAD_FL_MUST_CONNECT;
> > + pads[2].flags = MEDIA_PAD_FL_SOURCE |
> MEDIA_PAD_FL_MUST_CONNECT;
> > + pads[3].flags = MEDIA_PAD_FL_SOURCE |
> MEDIA_PAD_FL_MUST_CONNECT;
> > +
> > + mutex_init(&viif_dev->isp_subdev.ops_lock);
> > +
> > + ret = media_entity_pads_init(&sd->entity, 4, pads);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Failed on media_entity_pads_init\n");
> > + return ret;
> > + }
> > +
> > + ret = v4l2_device_register_subdev(&viif_dev->v4l2_dev, sd);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "Failed to resize ISP subdev\n");
> > + goto err_cleanup_media_entity;
> > + }
> > +
> > + visconti_viif_isp_init_config(sd, &state);
> > +
> > + return 0;
> > +
> > +err_cleanup_media_entity:
> > + media_entity_cleanup(&sd->entity);
> > + return ret;
> > +}
> > +
> > +void visconti_viif_isp_unregister(struct viif_device *viif_dev)
> > +{
> > + v4l2_device_unregister_subdev(&viif_dev->isp_subdev.sd);
> > + media_entity_cleanup(&viif_dev->isp_subdev.sd.entity);
> > +}
>
> Regards,
>
> Hans
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-26 1:25 ` yuji2.ishikawa
@ 2023-01-26 8:01 ` Hans Verkuil
2023-01-27 12:47 ` yuji2.ishikawa
0 siblings, 1 reply; 42+ messages in thread
From: Hans Verkuil @ 2023-01-26 8:01 UTC (permalink / raw)
To: yuji2.ishikawa, laurent.pinchart, mchehab, nobuhiro1.iwamatsu,
robh+dt, krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
On 26/01/2023 02:25, yuji2.ishikawa@toshiba.co.jp wrote:
> Hello Hans,
>
> Thank you for your comments.
>
>> -----Original Message-----
>> From: Hans Verkuil <hverkuil@xs4all.nl>
>> Sent: Tuesday, January 17, 2023 8:47 PM
>> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
>> <yuji2.ishikawa@toshiba.co.jp>; Laurent Pinchart
>> <laurent.pinchart@ideasonboard.com>; Mauro Carvalho Chehab
>> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
>> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
>> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
>> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>
>> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
>> Subject: Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti
>> Video Input Interface driver user interace
>>
>> More comments below:
>>
>> On 11/01/2023 03:24, Yuji Ishikawa wrote:
>>> Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
>>> The interface device includes CSI2 Receiver,
>>> frame grabber, video DMAC and image signal processor.
>>> This patch provides the user interface layer.
>>>
>>> A driver instance provides three /dev/videoX device files;
>>> one for RGB image capture, another one for optional RGB capture
>>> with different parameters and the last one for RAW capture.
>>>
>>> Through the device files, the driver provides streaming (DMA-BUF) interface.
>>> A userland application should feed DMA-BUF instances for capture buffers.
>>>
>>> The driver is based on media controller framework.
>>> Its operations are roughly mapped to two subdrivers;
>>> one for ISP and CSI2 receiver (yields 1 instance),
>>> the other for capture (yields 3 instances for each capture mode).
>>>
>>> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
>>> ---
>>> Changelog v2:
>>> - Resend v1 because a patch exceeds size limit.
>>>
>>> Changelog v3:
>>> - Adapted to media control framework
>>> - Introduced ISP subdevice, capture device
>>> - Remove private IOCTLs and add vendor specific V4L2 controls
>>> - Change function name avoiding camelcase and uppercase letters
>>>
>>> Changelog v4:
>>> - Split patches because the v3 patch exceeds size limit
>>> - Stop using ID number to identify driver instance:
>>> - Use dynamically allocated structure to hold HW specific context,
>>> instead of static one.
>>> - Call HW layer functions with the context structure instead of ID number
>>> - Use pm_runtime to trigger initialization of HW
>>> along with open/close of device files.
>>>
>>> Changelog v5:
>>> - Fix coding style problems in viif.c
>>> ---
>>> drivers/media/platform/visconti/Makefile | 1 +
>>> drivers/media/platform/visconti/viif.c | 545 ++++++++
>>> drivers/media/platform/visconti/viif.h | 203 +++
>>> .../media/platform/visconti/viif_capture.c | 1201
>> +++++++++++++++++
>>> drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
>>> 5 files changed, 2796 insertions(+)
>>> create mode 100644 drivers/media/platform/visconti/viif.c
>>> create mode 100644 drivers/media/platform/visconti/viif.h
>>> create mode 100644 drivers/media/platform/visconti/viif_capture.c
>>> create mode 100644 drivers/media/platform/visconti/viif_isp.c
>>>
<snip>
>>> +static int viif_g_selection(struct file *file, void *priv, struct v4l2_selection *s)
>>> +{
>>> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
>>> + struct viif_device *viif_dev = cap_dev->viif_dev;
>>> + struct v4l2_subdev_selection sel = {
>>> + .target = V4L2_SEL_TGT_CROP,
>>> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
>>> + };
>>> + int ret;
>>> +
>>
>> This is missing validation checks for s->type and s->target.
>
> I'll add validation code.
>
>> I've pretty sure you didn't run the v4l2-compliance utility: that would have
>> failed on this.
>
> Sorry I didn't know the utility.
> I'll apply it.
FYI: v4l2-compliance is part of the v4l-utils git repo.
Build it from scratch:
git clone git://linuxtv.org/v4l-utils.git
cd v4l-utils
./bootstrap.sh
./configure
make
sudo make install
>
>>> + /* check path id */
>>> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
>>> + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
>>> + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
>>> + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
>>> + else
>>> + return -EINVAL;
>>> +
>>> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad, get_selection,
>> NULL, &sel);
>>> + s->r = sel.r;
>>> +
>>> + return ret;
>>> +}
<snip>
>>> +/* ----- register/remove capture device node ----- */
>>> +static int visconti_viif_capture_register_node(struct cap_dev *cap_dev)
>>> +{
>>> + struct viif_device *viif_dev = cap_dev->viif_dev;
>>> + struct v4l2_device *v4l2_dev = &viif_dev->v4l2_dev;
>>> + struct video_device *vdev = &cap_dev->vdev;
>>> + struct vb2_queue *q = &cap_dev->vb2_vq;
>>> + static const char *const node_name[] = {
>>> + "viif_capture_post0",
>>> + "viif_capture_post1",
>>> + "viif_capture_sub",
>>> + };
>>> + int ret;
>>> +
>>> + INIT_LIST_HEAD(&cap_dev->buf_queue);
>>> +
>>> + mutex_init(&cap_dev->vlock);
>>> +
>>> + /* Initialize vb2 queue. */
>>> + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
>>> + q->io_modes = VB2_DMABUF;
>>
>> Why is there no VB2_MMAP?
>
> The hardware requests physically contiguous memory for frame buffer.
> I'm not sure if memory allocation in VB2_MMAP mode satisfies this restriction.
Yes, it does.
>
>>> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
>>> + q->ops = &viif_vb2_ops;
>>> + q->mem_ops = &vb2_dma_contig_memops;
The use of vb2_dma_contig_memops is what enforces physically contiguous memory.
It works fine with VB2_MMAP.
>>> + q->drv_priv = cap_dev;
>>> + q->buf_struct_size = sizeof(struct viif_buffer);
>>> + q->min_buffers_needed = 2;
>>> + q->lock = &cap_dev->vlock;
>>> + q->dev = viif_dev->v4l2_dev.dev;
>>> +
>>> + ret = vb2_queue_init(q);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + /* Register the video device. */
>>> + strscpy(vdev->name, node_name[cap_dev->pathid],
>> sizeof(vdev->name));
>>> + vdev->v4l2_dev = v4l2_dev;
>>> + vdev->lock = &cap_dev->vlock;
>>> + vdev->queue = &cap_dev->vb2_vq;
>>> + vdev->ctrl_handler = NULL;
>>> + vdev->fops = &viif_fops;
>>> + vdev->ioctl_ops = &viif_ioctl_ops;
>>> + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
>> V4L2_CAP_STREAMING;
>>> + vdev->device_caps |= V4L2_CAP_IO_MC;
>>> + vdev->entity.ops = &viif_media_ops;
>>> + vdev->release = video_device_release_empty;
>>> + video_set_drvdata(vdev, cap_dev);
>>> + vdev->vfl_dir = VFL_DIR_RX;
>>> + cap_dev->capture_pad.flags = MEDIA_PAD_FL_SINK;
>>> +
>>> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
>>> + if (ret < 0) {
>>> + dev_err(v4l2_dev->dev, "video_register_device failed: %d\n",
>> ret);
>>> + return ret;
>>> + }
>>> +
>>> + ret = media_entity_pads_init(&vdev->entity, 1,
>> &cap_dev->capture_pad);
>>> + if (ret) {
>>> + video_unregister_device(vdev);
>>> + return ret;
>>> + }
>>> +
>>> + ret = v4l2_ctrl_handler_init(&cap_dev->ctrl_handler, 30);
>>> + if (ret)
>>> + return -ENOMEM;
>>> +
>>> + cap_dev->vdev.ctrl_handler = &cap_dev->ctrl_handler;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int visconti_viif_capture_register(struct viif_device *viif_dev)
>>> +{
>>> + int ret;
>>> +
>>> + /* register MAIN POST0 (primary RGB output)*/
>>> + viif_dev->cap_dev0.pathid = CAPTURE_PATH_MAIN_POST0;
>>> + viif_dev->cap_dev0.viif_dev = viif_dev;
>>> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev0);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + /* register MAIN POST1 (additional RGB output)*/
>>> + viif_dev->cap_dev1.pathid = CAPTURE_PATH_MAIN_POST1;
>>> + viif_dev->cap_dev1.viif_dev = viif_dev;
>>> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev1);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + /* register SUB (RAW output) */
>>> + viif_dev->cap_dev2.pathid = CAPTURE_PATH_SUB;
>>> + viif_dev->cap_dev2.viif_dev = viif_dev;
>>> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev2);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void visconti_viif_capture_unregister_node(struct cap_dev *cap_dev)
>>> +{
>>> + media_entity_cleanup(&cap_dev->vdev.entity);
>>> + v4l2_ctrl_handler_free(&cap_dev->ctrl_handler);
>>> + vb2_video_unregister_device(&cap_dev->vdev);
>>> + mutex_destroy(&cap_dev->vlock);
>>> +}
>>> +
>>> +void visconti_viif_capture_unregister(struct viif_device *viif_dev)
>>> +{
>>> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev0);
>>> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev1);
>>> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev2);
>>> +}
Regards,
Hans
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace
2023-01-26 8:01 ` Hans Verkuil
@ 2023-01-27 12:47 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-27 12:47 UTC (permalink / raw)
To: hverkuil, laurent.pinchart, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
> -----Original Message-----
> From: Hans Verkuil <hverkuil@xs4all.nl>
> Sent: Thursday, January 26, 2023 5:02 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; laurent.pinchart@ideasonboard.com;
> mchehab@kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; rafael.j.wysocki@intel.com;
> broonie@kernel.org
> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver user interace
>
> On 26/01/2023 02:25, yuji2.ishikawa@toshiba.co.jp wrote:
> > Hello Hans,
> >
> > Thank you for your comments.
> >
> >> -----Original Message-----
> >> From: Hans Verkuil <hverkuil@xs4all.nl>
> >> Sent: Tuesday, January 17, 2023 8:47 PM
> >> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> >> <yuji2.ishikawa@toshiba.co.jp>; Laurent Pinchart
> >> <laurent.pinchart@ideasonboard.com>; Mauro Carvalho Chehab
> >> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> >> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> >> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J .
> >> Wysocki <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>
> >> Cc: linux-media@vger.kernel.org;
> >> linux-arm-kernel@lists.infradead.org;
> >> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> >> Subject: Re: [PATCH v5 3/6] media: platform: visconti: Add Toshiba
> >> Visconti Video Input Interface driver user interace
> >>
> >> More comments below:
> >>
> >> On 11/01/2023 03:24, Yuji Ishikawa wrote:
> >>> Add support to Video Input Interface on Toshiba Visconti ARM SoCs.
> >>> The interface device includes CSI2 Receiver, frame grabber, video
> >>> DMAC and image signal processor.
> >>> This patch provides the user interface layer.
> >>>
> >>> A driver instance provides three /dev/videoX device files; one for
> >>> RGB image capture, another one for optional RGB capture with
> >>> different parameters and the last one for RAW capture.
> >>>
> >>> Through the device files, the driver provides streaming (DMA-BUF)
> interface.
> >>> A userland application should feed DMA-BUF instances for capture
> buffers.
> >>>
> >>> The driver is based on media controller framework.
> >>> Its operations are roughly mapped to two subdrivers; one for ISP and
> >>> CSI2 receiver (yields 1 instance), the other for capture (yields 3
> >>> instances for each capture mode).
> >>>
> >>> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> >>> ---
> >>> Changelog v2:
> >>> - Resend v1 because a patch exceeds size limit.
> >>>
> >>> Changelog v3:
> >>> - Adapted to media control framework
> >>> - Introduced ISP subdevice, capture device
> >>> - Remove private IOCTLs and add vendor specific V4L2 controls
> >>> - Change function name avoiding camelcase and uppercase letters
> >>>
> >>> Changelog v4:
> >>> - Split patches because the v3 patch exceeds size limit
> >>> - Stop using ID number to identify driver instance:
> >>> - Use dynamically allocated structure to hold HW specific context,
> >>> instead of static one.
> >>> - Call HW layer functions with the context structure instead of ID
> >>> number
> >>> - Use pm_runtime to trigger initialization of HW
> >>> along with open/close of device files.
> >>>
> >>> Changelog v5:
> >>> - Fix coding style problems in viif.c
> >>> ---
> >>> drivers/media/platform/visconti/Makefile | 1 +
> >>> drivers/media/platform/visconti/viif.c | 545 ++++++++
> >>> drivers/media/platform/visconti/viif.h | 203 +++
> >>> .../media/platform/visconti/viif_capture.c | 1201
> >> +++++++++++++++++
> >>> drivers/media/platform/visconti/viif_isp.c | 846 ++++++++++++
> >>> 5 files changed, 2796 insertions(+) create mode 100644
> >>> drivers/media/platform/visconti/viif.c
> >>> create mode 100644 drivers/media/platform/visconti/viif.h
> >>> create mode 100644 drivers/media/platform/visconti/viif_capture.c
> >>> create mode 100644 drivers/media/platform/visconti/viif_isp.c
> >>>
>
> <snip>
>
> >>> +static int viif_g_selection(struct file *file, void *priv, struct
> >>> +v4l2_selection *s) {
> >>> + struct cap_dev *cap_dev = video_drvdata_to_capdev(file);
> >>> + struct viif_device *viif_dev = cap_dev->viif_dev;
> >>> + struct v4l2_subdev_selection sel = {
> >>> + .target = V4L2_SEL_TGT_CROP,
> >>> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> >>> + };
> >>> + int ret;
> >>> +
> >>
> >> This is missing validation checks for s->type and s->target.
> >
> > I'll add validation code.
> >
> >> I've pretty sure you didn't run the v4l2-compliance utility: that
> >> would have failed on this.
> >
> > Sorry I didn't know the utility.
> > I'll apply it.
>
> FYI: v4l2-compliance is part of the v4l-utils git repo.
>
> Build it from scratch:
>
> git clone git://linuxtv.org/v4l-utils.git cd v4l-utils ./bootstrap.sh ./configure
> make sudo make install
>
Thank you for information.
I'll run v4l2-compliance tool.
> >
> >>> + /* check path id */
> >>> + if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST0)
> >>> + sel.pad = VIIF_ISP_PAD_SRC_PATH0;
> >>> + else if (cap_dev->pathid == CAPTURE_PATH_MAIN_POST1)
> >>> + sel.pad = VIIF_ISP_PAD_SRC_PATH1;
> >>> + else
> >>> + return -EINVAL;
> >>> +
> >>> + ret = v4l2_subdev_call(&viif_dev->isp_subdev.sd, pad,
> >>> +get_selection,
> >> NULL, &sel);
> >>> + s->r = sel.r;
> >>> +
> >>> + return ret;
> >>> +}
>
> <snip>
>
> >>> +/* ----- register/remove capture device node ----- */ static int
> >>> +visconti_viif_capture_register_node(struct cap_dev *cap_dev) {
> >>> + struct viif_device *viif_dev = cap_dev->viif_dev;
> >>> + struct v4l2_device *v4l2_dev = &viif_dev->v4l2_dev;
> >>> + struct video_device *vdev = &cap_dev->vdev;
> >>> + struct vb2_queue *q = &cap_dev->vb2_vq;
> >>> + static const char *const node_name[] = {
> >>> + "viif_capture_post0",
> >>> + "viif_capture_post1",
> >>> + "viif_capture_sub",
> >>> + };
> >>> + int ret;
> >>> +
> >>> + INIT_LIST_HEAD(&cap_dev->buf_queue);
> >>> +
> >>> + mutex_init(&cap_dev->vlock);
> >>> +
> >>> + /* Initialize vb2 queue. */
> >>> + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
> >>> + q->io_modes = VB2_DMABUF;
> >>
> >> Why is there no VB2_MMAP?
> >
> > The hardware requests physically contiguous memory for frame buffer.
> > I'm not sure if memory allocation in VB2_MMAP mode satisfies this restriction.
>
> Yes, it does.
>
> >
> >>> + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> >>> + q->ops = &viif_vb2_ops;
> >>> + q->mem_ops = &vb2_dma_contig_memops;
>
> The use of vb2_dma_contig_memops is what enforces physically contiguous
> memory.
> It works fine with VB2_MMAP.
>
Thank you. I will add VB2_MMAP support.
> >>> + q->drv_priv = cap_dev;
> >>> + q->buf_struct_size = sizeof(struct viif_buffer);
> >>> + q->min_buffers_needed = 2;
> >>> + q->lock = &cap_dev->vlock;
> >>> + q->dev = viif_dev->v4l2_dev.dev;
> >>> +
> >>> + ret = vb2_queue_init(q);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + /* Register the video device. */
> >>> + strscpy(vdev->name, node_name[cap_dev->pathid],
> >> sizeof(vdev->name));
> >>> + vdev->v4l2_dev = v4l2_dev;
> >>> + vdev->lock = &cap_dev->vlock;
> >>> + vdev->queue = &cap_dev->vb2_vq;
> >>> + vdev->ctrl_handler = NULL;
> >>> + vdev->fops = &viif_fops;
> >>> + vdev->ioctl_ops = &viif_ioctl_ops;
> >>> + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
> >> V4L2_CAP_STREAMING;
> >>> + vdev->device_caps |= V4L2_CAP_IO_MC;
> >>> + vdev->entity.ops = &viif_media_ops;
> >>> + vdev->release = video_device_release_empty;
> >>> + video_set_drvdata(vdev, cap_dev);
> >>> + vdev->vfl_dir = VFL_DIR_RX;
> >>> + cap_dev->capture_pad.flags = MEDIA_PAD_FL_SINK;
> >>> +
> >>> + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> >>> + if (ret < 0) {
> >>> + dev_err(v4l2_dev->dev, "video_register_device failed: %d\n",
> >> ret);
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = media_entity_pads_init(&vdev->entity, 1,
> >> &cap_dev->capture_pad);
> >>> + if (ret) {
> >>> + video_unregister_device(vdev);
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = v4l2_ctrl_handler_init(&cap_dev->ctrl_handler, 30);
> >>> + if (ret)
> >>> + return -ENOMEM;
> >>> +
> >>> + cap_dev->vdev.ctrl_handler = &cap_dev->ctrl_handler;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +int visconti_viif_capture_register(struct viif_device *viif_dev) {
> >>> + int ret;
> >>> +
> >>> + /* register MAIN POST0 (primary RGB output)*/
> >>> + viif_dev->cap_dev0.pathid = CAPTURE_PATH_MAIN_POST0;
> >>> + viif_dev->cap_dev0.viif_dev = viif_dev;
> >>> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev0);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + /* register MAIN POST1 (additional RGB output)*/
> >>> + viif_dev->cap_dev1.pathid = CAPTURE_PATH_MAIN_POST1;
> >>> + viif_dev->cap_dev1.viif_dev = viif_dev;
> >>> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev1);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + /* register SUB (RAW output) */
> >>> + viif_dev->cap_dev2.pathid = CAPTURE_PATH_SUB;
> >>> + viif_dev->cap_dev2.viif_dev = viif_dev;
> >>> + ret = visconti_viif_capture_register_node(&viif_dev->cap_dev2);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static void visconti_viif_capture_unregister_node(struct cap_dev
> >>> +*cap_dev) {
> >>> + media_entity_cleanup(&cap_dev->vdev.entity);
> >>> + v4l2_ctrl_handler_free(&cap_dev->ctrl_handler);
> >>> + vb2_video_unregister_device(&cap_dev->vdev);
> >>> + mutex_destroy(&cap_dev->vlock);
> >>> +}
> >>> +
> >>> +void visconti_viif_capture_unregister(struct viif_device *viif_dev)
> >>> +{
> >>> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev0);
> >>> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev1);
> >>> + visconti_viif_capture_unregister_node(&viif_dev->cap_dev2);
> >>> +}
>
> Regards,
>
> Hans
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-11 2:24 [PATCH v5 0/6] Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
` (2 preceding siblings ...)
2023-01-11 2:24 ` [PATCH v5 3/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver user interace Yuji Ishikawa
@ 2023-01-11 2:24 ` Yuji Ishikawa
2023-01-17 11:19 ` Hans Verkuil
2023-01-11 2:24 ` [PATCH v5 5/6] documentation: media: add documentation for Toshiba Visconti Video Input Interface driver Yuji Ishikawa
2023-01-11 2:24 ` [PATCH v5 6/6] MAINTAINERS: Add entries for Toshiba Visconti Video Input Interface Yuji Ishikawa
5 siblings, 1 reply; 42+ messages in thread
From: Yuji Ishikawa @ 2023-01-11 2:24 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree, yuji2.ishikawa
Add support to Image Signal Processors of Visconti's Video Input Interface.
This patch adds vendor specific compound controls
to configure the image signal processor.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
---
Changelog v2:
- Resend v1 because a patch exceeds size limit.
Changelog v3:
- Adapted to media control framework
- Introduced ISP subdevice, capture device
- Remove private IOCTLs and add vendor specific V4L2 controls
- Change function name avoiding camelcase and uppercase letters
Changelog v4:
- Split patches because the v3 patch exceeds size limit
- Stop using ID number to identify driver instance:
- Use dynamically allocated structure to hold HW specific context,
instead of static one.
- Call HW layer functions with the context structure instead of ID number
Changelog v5:
- no change
---
drivers/media/platform/visconti/Makefile | 4 +-
.../media/platform/visconti/hwd_viif_l1isp.c | 2674 +++++++++++++++++
.../media/platform/visconti/viif_controls.c | 1153 +++++++
drivers/media/platform/visconti/viif_isp.c | 2 +
4 files changed, 3831 insertions(+), 2 deletions(-)
create mode 100644 drivers/media/platform/visconti/hwd_viif_l1isp.c
create mode 100644 drivers/media/platform/visconti/viif_controls.c
diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
index d7a23c1f4e8..13cf70ce309 100644
--- a/drivers/media/platform/visconti/Makefile
+++ b/drivers/media/platform/visconti/Makefile
@@ -3,7 +3,7 @@
# Makefile for the Visconti video input device driver
#
-visconti-viif-objs = viif.o viif_capture.o viif_isp.o
-visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
+visconti-viif-objs = viif.o viif_capture.o viif_controls.o viif_isp.o
+visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o hwd_viif_l1isp.o
obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
diff --git a/drivers/media/platform/visconti/hwd_viif_l1isp.c b/drivers/media/platform/visconti/hwd_viif_l1isp.c
new file mode 100644
index 00000000000..882eea92205
--- /dev/null
+++ b/drivers/media/platform/visconti/hwd_viif_l1isp.c
@@ -0,0 +1,2674 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/io.h>
+#include "hwd_viif.h"
+#include "hwd_viif_internal.h"
+
+/**
+ * hwd_viif_l1_set_input_mode() - Configure L1ISP input mode.
+ *
+ * @mode: L1ISP preprocessing mode @ref hwd_viif_l1_input_mode
+ * @depth: input color depth (even only)
+ * - [8..24] in case of mode = #HWD_VIIF_L1_INPUT_HDR or #HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT
+ * - [8..14] in case of mode = #HWD_VIIF_L1_INPUT_PWL or #HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT
+ * - [8..12] in case of mode = #HWD_VIIF_L1_INPUT_SDR
+ * @raw_color_filter: RAW color filter array @ref hwd_viif_l1_raw_color_filter_mode
+ * @interpolation_order: interpolation order for input image
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "mode" is out of range
+ * - "depth" is out of range
+ * - "raw_color_filter" is out of range
+ * - "interpolation_order" is NULL in case of "mode" == #HWD_VIIF_L1_INPUT_SDR
+ * - "interpolation_order" is not NULL in case of "mode" != #HWD_VIIF_L1_INPUT_SDR
+ *
+ * Note that if 'mode' is not HWD_VIIF_L1_INPUT_SDR, NULL shall be set to 'interpolation_order'.
+ */
+s32 hwd_viif_l1_set_input_mode(struct hwd_viif_res *res, u32 mode, u32 depth, u32 raw_color_filter)
+{
+ u32 depth_max;
+
+ if (mode >= HWD_VIIF_L1_INPUT_MODE_NUM || mode == HWD_VIIF_L1_INPUT_SDR)
+ return -EINVAL;
+
+ if (mode == HWD_VIIF_L1_INPUT_PWL || mode == HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT)
+ depth_max = HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX;
+ else
+ depth_max = HWD_VIIF_L1_INPUT_DEPTH_MAX;
+
+ if (depth < HWD_VIIF_L1_INPUT_DEPTH_MIN || depth > depth_max || ((depth % 2U) != 0U) ||
+ raw_color_filter >= HWD_VIIF_L1_RAW_MODE_NUM) {
+ return -EINVAL;
+ }
+
+ writel(mode, &res->capture_reg->l1isp.L1_SYSM_INPUT_MODE);
+ writel(depth, &res->capture_reg->l1isp.L1_IBUF_DEPTH);
+ writel(raw_color_filter, &res->capture_reg->l1isp.L1_SYSM_START_COLOR);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_rgb_to_y_coef() - Configure L1ISP RGB coefficients to calculate Y.
+ *
+ * @coef_r: R coefficient to calculate Y [256..65024] accuracy: 1/65536
+ * @coef_g: G coefficient to calculate Y [256..65024] accuracy: 1/65536
+ * @coef_b: B coefficient to calculate Y [256..65024] accuracy: 1/65536
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "coef_r" is out of range
+ * - "coef_g" is out of range
+ * - "coef_b" is out of range
+ *
+ * Note that it is possible that coef_r/g/b has rounding error when the value is set to HW register
+ */
+s32 hwd_viif_l1_set_rgb_to_y_coef(struct hwd_viif_res *res, u16 coef_r, u16 coef_g, u16 coef_b)
+{
+ if (coef_r < HWD_VIIF_L1_COEF_MIN || coef_r > HWD_VIIF_L1_COEF_MAX ||
+ coef_g < HWD_VIIF_L1_COEF_MIN || coef_g > HWD_VIIF_L1_COEF_MAX ||
+ coef_b < HWD_VIIF_L1_COEF_MIN || coef_b > HWD_VIIF_L1_COEF_MAX) {
+ return -EINVAL;
+ }
+
+ writel((u32)coef_r, &res->capture_reg->l1isp.L1_SYSM_YCOEF_R);
+ writel((u32)coef_g, &res->capture_reg->l1isp.L1_SYSM_YCOEF_G);
+ writel((u32)coef_b, &res->capture_reg->l1isp.L1_SYSM_YCOEF_B);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_ag_mode() - Configure L1ISP AG mode.
+ *
+ * @param: pointer to struct hwd_viif_l1_ag_mode
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "param" is NULL
+ * - each member of "param" is invalid
+ */
+s32 hwd_viif_l1_set_ag_mode(struct hwd_viif_res *res, const struct viif_l1_ag_mode_config *param)
+{
+ u32 val;
+
+ if (!param || param->sysm_ag_psel_hobc_high >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_hobc_middle_led >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_hobc_low >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_abpc_high >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_abpc_middle_led >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_abpc_low >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_rcnr_high >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_rcnr_middle_led >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_psel_rcnr_low >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_ssel_lssc >= HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
+ param->sysm_ag_psel_lssc >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_ssel_mpro >= HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
+ param->sysm_ag_psel_mpro >= HWD_VIIF_L1_AG_ID_NUM ||
+ param->sysm_ag_ssel_vpro >= HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
+ param->sysm_ag_psel_vpro >= HWD_VIIF_L1_AG_ID_NUM ||
+ (param->sysm_ag_cont_hobc_en_high != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_hobc_en_high != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_hobc_en_middle_led != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_hobc_en_middle_led != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_hobc_en_low != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_hobc_en_low != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_rcnr_en_high != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_rcnr_en_high != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_rcnr_en_middle_led != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_rcnr_en_middle_led != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_rcnr_en_low != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_rcnr_en_low != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_lssc_en != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_lssc_en != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_mpro_en != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_mpro_en != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_vpro_en != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_vpro_en != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_abpc_en_middle_led != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_abpc_en_middle_led != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_abpc_en_high != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_abpc_en_high != HWD_VIIF_DISABLE) ||
+ (param->sysm_ag_cont_abpc_en_low != HWD_VIIF_ENABLE &&
+ param->sysm_ag_cont_abpc_en_low != HWD_VIIF_DISABLE)) {
+ return -EINVAL;
+ }
+
+ /* SYSM_AG_PARAM */
+ val = ((u32)param->sysm_ag_grad[0] << 16U) | ((u32)param->sysm_ag_ofst[0]);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_A);
+ val = ((u32)param->sysm_ag_grad[1] << 16U) | ((u32)param->sysm_ag_ofst[1]);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_B);
+ val = ((u32)param->sysm_ag_grad[2] << 16U) | ((u32)param->sysm_ag_ofst[2]);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_C);
+ val = ((u32)param->sysm_ag_grad[3] << 16U) | ((u32)param->sysm_ag_ofst[3]);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_D);
+
+ /* SYSM_AG_SEL */
+ val = ((u32)param->sysm_ag_psel_hobc_high << 6U) |
+ ((u32)param->sysm_ag_psel_hobc_middle_led << 4U) |
+ ((u32)param->sysm_ag_psel_hobc_low << 2U);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_HOBC);
+
+ val = ((u32)param->sysm_ag_psel_abpc_high << 6U) |
+ ((u32)param->sysm_ag_psel_abpc_middle_led << 4U) |
+ ((u32)param->sysm_ag_psel_abpc_low << 2U);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_ABPC);
+
+ val = ((u32)param->sysm_ag_psel_rcnr_high << 6U) |
+ ((u32)param->sysm_ag_psel_rcnr_middle_led << 4U) |
+ ((u32)param->sysm_ag_psel_rcnr_low << 2U);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_RCNR);
+
+ val = ((u32)param->sysm_ag_ssel_lssc << 2U) | ((u32)param->sysm_ag_psel_lssc);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_LSSC);
+
+ val = ((u32)param->sysm_ag_ssel_mpro << 2U) | ((u32)param->sysm_ag_psel_mpro);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_MPRO);
+
+ val = ((u32)param->sysm_ag_ssel_vpro << 2U) | ((u32)param->sysm_ag_psel_vpro);
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_VPRO);
+
+ /* SYSM_AG_CONT */
+ val = (param->sysm_ag_cont_hobc_en_middle_led << 24U) |
+ ((u32)(param->sysm_ag_cont_hobc_test_middle_led) << 16U) |
+ (param->sysm_ag_cont_hobc_en_high << 8U) | (u32)param->sysm_ag_cont_hobc_test_high;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_HOBC01_EN);
+ val = (param->sysm_ag_cont_hobc_en_low << 8U) | (u32)param->sysm_ag_cont_hobc_test_low;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_HOBC2_EN);
+
+ val = (param->sysm_ag_cont_abpc_en_middle_led << 24U) |
+ ((u32)(param->sysm_ag_cont_abpc_test_middle_led) << 16U) |
+ (param->sysm_ag_cont_abpc_en_high << 8U) | (u32)param->sysm_ag_cont_abpc_test_high;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_ABPC01_EN);
+ val = (param->sysm_ag_cont_abpc_en_low << 8U) | (u32)param->sysm_ag_cont_abpc_test_low;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_ABPC2_EN);
+
+ val = (param->sysm_ag_cont_rcnr_en_middle_led << 24U) |
+ ((u32)(param->sysm_ag_cont_rcnr_test_middle_led) << 16U) |
+ (param->sysm_ag_cont_rcnr_en_high << 8U) | (u32)param->sysm_ag_cont_rcnr_test_high;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_RCNR01_EN);
+ val = (param->sysm_ag_cont_rcnr_en_low << 8U) | (u32)param->sysm_ag_cont_rcnr_test_low;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_RCNR2_EN);
+
+ val = (param->sysm_ag_cont_lssc_en << 8U) | (u32)param->sysm_ag_cont_lssc_test;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_LSSC_EN);
+
+ val = (param->sysm_ag_cont_mpro_en << 8U) | (u32)param->sysm_ag_cont_mpro_test;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_MPRO_EN);
+
+ val = (param->sysm_ag_cont_vpro_en << 8U) | (u32)param->sysm_ag_cont_vpro_test;
+ writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_VPRO_EN);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_ag() - Configure L1ISP analog gain.
+ *
+ * @gain_h: analog gain value for high sensitivity image [0..65535]
+ * @gain_m: analog gain value for middle sensitivity or led image [0..65535]
+ * @gain_l: analog gain value for low sensitivity image [0..65535]
+ * Return: 0 operation completed successfully
+ */
+s32 hwd_viif_l1_set_ag(struct hwd_viif_res *res, u16 gain_h, u16 gain_m, u16 gain_l)
+{
+ writel((u32)gain_h, &res->capture_reg->l1isp.L1_SYSM_AG_H);
+ writel((u32)gain_m, &res->capture_reg->l1isp.L1_SYSM_AG_M);
+ writel((u32)gain_l, &res->capture_reg->l1isp.L1_SYSM_AG_L);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_hdre() - Configure L1ISP HDR extension parameters.
+ *
+ * @param: pointer to struct hwd_viif_l1_hdre
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "param" is NULL
+ * - each member of "param" is invalid
+ */
+s32 hwd_viif_l1_set_hdre(struct hwd_viif_res *res, const struct viif_l1_hdre_config *param)
+{
+ u32 idx;
+
+ if (!param)
+ return -EINVAL;
+
+ for (idx = 0; idx < 16U; idx++) {
+ if (param->hdre_src_point[idx] > HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL)
+ return -EINVAL;
+ }
+
+ for (idx = 0; idx < 17U; idx++) {
+ if (param->hdre_dst_base[idx] > HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL ||
+ param->hdre_ratio[idx] >= HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO) {
+ return -EINVAL;
+ }
+ }
+
+ if (param->hdre_dst_max_val > HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL)
+ return -EINVAL;
+
+ writel(param->hdre_src_point[0], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT00);
+ writel(param->hdre_src_point[1], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT01);
+ writel(param->hdre_src_point[2], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT02);
+ writel(param->hdre_src_point[3], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT03);
+ writel(param->hdre_src_point[4], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT04);
+ writel(param->hdre_src_point[5], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT05);
+ writel(param->hdre_src_point[6], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT06);
+ writel(param->hdre_src_point[7], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT07);
+ writel(param->hdre_src_point[8], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT08);
+ writel(param->hdre_src_point[9], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT09);
+ writel(param->hdre_src_point[10], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT10);
+ writel(param->hdre_src_point[11], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT11);
+ writel(param->hdre_src_point[12], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT12);
+ writel(param->hdre_src_point[13], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT13);
+ writel(param->hdre_src_point[14], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT14);
+ writel(param->hdre_src_point[15], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT15);
+
+ writel(0, &res->capture_reg->l1isp.L1_HDRE_SRCBASE00);
+ writel(param->hdre_src_point[0], &res->capture_reg->l1isp.L1_HDRE_SRCBASE01);
+ writel(param->hdre_src_point[1], &res->capture_reg->l1isp.L1_HDRE_SRCBASE02);
+ writel(param->hdre_src_point[2], &res->capture_reg->l1isp.L1_HDRE_SRCBASE03);
+ writel(param->hdre_src_point[3], &res->capture_reg->l1isp.L1_HDRE_SRCBASE04);
+ writel(param->hdre_src_point[4], &res->capture_reg->l1isp.L1_HDRE_SRCBASE05);
+ writel(param->hdre_src_point[5], &res->capture_reg->l1isp.L1_HDRE_SRCBASE06);
+ writel(param->hdre_src_point[6], &res->capture_reg->l1isp.L1_HDRE_SRCBASE07);
+ writel(param->hdre_src_point[7], &res->capture_reg->l1isp.L1_HDRE_SRCBASE08);
+ writel(param->hdre_src_point[8], &res->capture_reg->l1isp.L1_HDRE_SRCBASE09);
+ writel(param->hdre_src_point[9], &res->capture_reg->l1isp.L1_HDRE_SRCBASE10);
+ writel(param->hdre_src_point[10], &res->capture_reg->l1isp.L1_HDRE_SRCBASE11);
+ writel(param->hdre_src_point[11], &res->capture_reg->l1isp.L1_HDRE_SRCBASE12);
+ writel(param->hdre_src_point[12], &res->capture_reg->l1isp.L1_HDRE_SRCBASE13);
+ writel(param->hdre_src_point[13], &res->capture_reg->l1isp.L1_HDRE_SRCBASE14);
+ writel(param->hdre_src_point[14], &res->capture_reg->l1isp.L1_HDRE_SRCBASE15);
+ writel(param->hdre_src_point[15], &res->capture_reg->l1isp.L1_HDRE_SRCBASE16);
+
+ writel(param->hdre_dst_base[0], &res->capture_reg->l1isp.L1_HDRE_DSTBASE00);
+ writel(param->hdre_dst_base[1], &res->capture_reg->l1isp.L1_HDRE_DSTBASE01);
+ writel(param->hdre_dst_base[2], &res->capture_reg->l1isp.L1_HDRE_DSTBASE02);
+ writel(param->hdre_dst_base[3], &res->capture_reg->l1isp.L1_HDRE_DSTBASE03);
+ writel(param->hdre_dst_base[4], &res->capture_reg->l1isp.L1_HDRE_DSTBASE04);
+ writel(param->hdre_dst_base[5], &res->capture_reg->l1isp.L1_HDRE_DSTBASE05);
+ writel(param->hdre_dst_base[6], &res->capture_reg->l1isp.L1_HDRE_DSTBASE06);
+ writel(param->hdre_dst_base[7], &res->capture_reg->l1isp.L1_HDRE_DSTBASE07);
+ writel(param->hdre_dst_base[8], &res->capture_reg->l1isp.L1_HDRE_DSTBASE08);
+ writel(param->hdre_dst_base[9], &res->capture_reg->l1isp.L1_HDRE_DSTBASE09);
+ writel(param->hdre_dst_base[10], &res->capture_reg->l1isp.L1_HDRE_DSTBASE10);
+ writel(param->hdre_dst_base[11], &res->capture_reg->l1isp.L1_HDRE_DSTBASE11);
+ writel(param->hdre_dst_base[12], &res->capture_reg->l1isp.L1_HDRE_DSTBASE12);
+ writel(param->hdre_dst_base[13], &res->capture_reg->l1isp.L1_HDRE_DSTBASE13);
+ writel(param->hdre_dst_base[14], &res->capture_reg->l1isp.L1_HDRE_DSTBASE14);
+ writel(param->hdre_dst_base[15], &res->capture_reg->l1isp.L1_HDRE_DSTBASE15);
+ writel(param->hdre_dst_base[16], &res->capture_reg->l1isp.L1_HDRE_DSTBASE16);
+
+ writel(param->hdre_ratio[0], &res->capture_reg->l1isp.L1_HDRE_RATIO00);
+ writel(param->hdre_ratio[1], &res->capture_reg->l1isp.L1_HDRE_RATIO01);
+ writel(param->hdre_ratio[2], &res->capture_reg->l1isp.L1_HDRE_RATIO02);
+ writel(param->hdre_ratio[3], &res->capture_reg->l1isp.L1_HDRE_RATIO03);
+ writel(param->hdre_ratio[4], &res->capture_reg->l1isp.L1_HDRE_RATIO04);
+ writel(param->hdre_ratio[5], &res->capture_reg->l1isp.L1_HDRE_RATIO05);
+ writel(param->hdre_ratio[6], &res->capture_reg->l1isp.L1_HDRE_RATIO06);
+ writel(param->hdre_ratio[7], &res->capture_reg->l1isp.L1_HDRE_RATIO07);
+ writel(param->hdre_ratio[8], &res->capture_reg->l1isp.L1_HDRE_RATIO08);
+ writel(param->hdre_ratio[9], &res->capture_reg->l1isp.L1_HDRE_RATIO09);
+ writel(param->hdre_ratio[10], &res->capture_reg->l1isp.L1_HDRE_RATIO10);
+ writel(param->hdre_ratio[11], &res->capture_reg->l1isp.L1_HDRE_RATIO11);
+ writel(param->hdre_ratio[12], &res->capture_reg->l1isp.L1_HDRE_RATIO12);
+ writel(param->hdre_ratio[13], &res->capture_reg->l1isp.L1_HDRE_RATIO13);
+ writel(param->hdre_ratio[14], &res->capture_reg->l1isp.L1_HDRE_RATIO14);
+ writel(param->hdre_ratio[15], &res->capture_reg->l1isp.L1_HDRE_RATIO15);
+ writel(param->hdre_ratio[16], &res->capture_reg->l1isp.L1_HDRE_RATIO16);
+
+ writel(param->hdre_dst_max_val, &res->capture_reg->l1isp.L1_HDRE_DSTMAXVAL);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_img_extraction() - Configure L1ISP image extraction parameters.
+ *
+ * @input_black_gr: black level of Gr input pixel [0x0..0xffffff]
+ * @input_black_r: black level of R input pixel [0x0..0xffffff]
+ * @input_black_b: black level of B input pixel [0x0..0xffffff]
+ * @input_black_gb: black level of Gb input pixel [0x0..0xffffff]
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "input_black_gr" is out of range
+ * - "input_black_r" is out of range
+ * - "input_black_b" is out of range
+ * - "input_black_gb" is out of range
+ */
+s32 hwd_viif_l1_set_img_extraction(struct hwd_viif_res *res, u32 input_black_gr, u32 input_black_r,
+ u32 input_black_b, u32 input_black_gb)
+{
+ if (input_black_gr > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
+ input_black_r > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
+ input_black_b > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
+ input_black_gb > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL) {
+ return -EINVAL;
+ }
+
+ writel(input_black_gr, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_GR);
+ writel(input_black_r, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_R);
+ writel(input_black_b, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_B);
+ writel(input_black_gb, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_GB);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_dpc() - Configure L1ISP defect pixel correction parameters.
+ *
+ * @param_h: pointer to defect pixel correction parameters for high sensitivity image
+ * @param_m: pointer to defect pixel correction parameters for middle sensitivity or led image
+ * @param_l: pointer to defect pixel correction parameters for low sensitivity image
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "param_h", "param_m" and "param_l" are NULL
+ * - each member of "param_h" is invalid
+ * - each member of "param_m" is invalid
+ * - each member of "param_l" is invalid
+ */
+s32 hwd_viif_l1_set_dpc(struct hwd_viif_res *res, const struct viif_l1_dpc *param_h,
+ const struct viif_l1_dpc *param_m, const struct viif_l1_dpc *param_l)
+{
+ const struct viif_l1_dpc *param;
+ u32 idx;
+ u32 val;
+
+ if (!param_h && !param_m && !param_l)
+ return -EINVAL;
+
+ for (idx = 0U; idx < 3U; idx++) {
+ if (idx == 0U)
+ param = param_h;
+ else if (idx == 1U)
+ param = param_m;
+ else
+ param = param_l;
+
+ if (!param)
+ continue;
+
+ if ((param->abpc_sta_en != HWD_VIIF_ENABLE &&
+ param->abpc_sta_en != HWD_VIIF_DISABLE) ||
+ (param->abpc_dyn_en != HWD_VIIF_ENABLE &&
+ param->abpc_dyn_en != HWD_VIIF_DISABLE)) {
+ return -EINVAL;
+ }
+
+ if (param->abpc_dyn_en != HWD_VIIF_ENABLE)
+ continue;
+
+ if ((param->abpc_dyn_mode != HWD_VIIF_L1_DPC_1PIXEL &&
+ param->abpc_dyn_mode != HWD_VIIF_L1_DPC_2PIXEL) ||
+ param->abpc_ratio_limit > HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL ||
+ param->abpc_dark_limit > HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL ||
+ param->abpc_sn_coef_w_ag_min < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_w_ag_min > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_w_ag_mid < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_w_ag_mid > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_w_ag_max < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_w_ag_max > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_b_ag_min < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_b_ag_min > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_b_ag_mid < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_b_ag_mid > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_b_ag_max < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_b_ag_max > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
+ param->abpc_sn_coef_w_th_min >= param->abpc_sn_coef_w_th_max ||
+ param->abpc_sn_coef_b_th_min >= param->abpc_sn_coef_b_th_max) {
+ return -EINVAL;
+ }
+ }
+
+ val = 0;
+ if (param_h)
+ val |= param_h->abpc_sta_en << 24U;
+
+ if (param_m)
+ val |= param_m->abpc_sta_en << 16U;
+
+ if (param_l)
+ val |= param_l->abpc_sta_en << 8U;
+
+ writel(val, &res->capture_reg->l1isp.L1_ABPC012_STA_EN);
+
+ val = 0;
+ if (param_h)
+ val |= param_h->abpc_dyn_en << 24U;
+
+ if (param_m)
+ val |= param_m->abpc_dyn_en << 16U;
+
+ if (param_l)
+ val |= param_l->abpc_dyn_en << 8U;
+
+ writel(val, &res->capture_reg->l1isp.L1_ABPC012_DYN_EN);
+
+ val = 0;
+ if (param_h)
+ val |= param_h->abpc_dyn_mode << 24U;
+
+ if (param_m)
+ val |= param_m->abpc_dyn_mode << 16U;
+
+ if (param_l)
+ val |= param_l->abpc_dyn_mode << 8U;
+
+ writel(val, &res->capture_reg->l1isp.L1_ABPC012_DYN_MODE);
+
+ if (param_h) {
+ writel(param_h->abpc_ratio_limit, &res->capture_reg->l1isp.L1_ABPC0_RATIO_LIMIT);
+ writel(param_h->abpc_dark_limit, &res->capture_reg->l1isp.L1_ABPC0_DARK_LIMIT);
+ writel(param_h->abpc_sn_coef_w_ag_min,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MIN);
+ writel(param_h->abpc_sn_coef_w_ag_mid,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MID);
+ writel(param_h->abpc_sn_coef_w_ag_max,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MAX);
+ writel(param_h->abpc_sn_coef_b_ag_min,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MIN);
+ writel(param_h->abpc_sn_coef_b_ag_mid,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MID);
+ writel(param_h->abpc_sn_coef_b_ag_max,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MAX);
+ writel((u32)param_h->abpc_sn_coef_w_th_min,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_TH_MIN);
+ writel((u32)param_h->abpc_sn_coef_w_th_max,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_TH_MAX);
+ writel((u32)param_h->abpc_sn_coef_b_th_min,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_TH_MIN);
+ writel((u32)param_h->abpc_sn_coef_b_th_max,
+ &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_TH_MAX);
+ }
+
+ if (param_m) {
+ writel(param_m->abpc_ratio_limit, &res->capture_reg->l1isp.L1_ABPC1_RATIO_LIMIT);
+ writel(param_m->abpc_dark_limit, &res->capture_reg->l1isp.L1_ABPC1_DARK_LIMIT);
+ writel(param_m->abpc_sn_coef_w_ag_min,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MIN);
+ writel(param_m->abpc_sn_coef_w_ag_mid,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MID);
+ writel(param_m->abpc_sn_coef_w_ag_max,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MAX);
+ writel(param_m->abpc_sn_coef_b_ag_min,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MIN);
+ writel(param_m->abpc_sn_coef_b_ag_mid,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MID);
+ writel(param_m->abpc_sn_coef_b_ag_max,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MAX);
+ writel((u32)param_m->abpc_sn_coef_w_th_min,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_TH_MIN);
+ writel((u32)param_m->abpc_sn_coef_w_th_max,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_TH_MAX);
+ writel((u32)param_m->abpc_sn_coef_b_th_min,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_TH_MIN);
+ writel((u32)param_m->abpc_sn_coef_b_th_max,
+ &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_TH_MAX);
+ }
+
+ if (param_l) {
+ writel(param_l->abpc_ratio_limit, &res->capture_reg->l1isp.L1_ABPC2_RATIO_LIMIT);
+ writel(param_l->abpc_dark_limit, &res->capture_reg->l1isp.L1_ABPC2_DARK_LIMIT);
+ writel(param_l->abpc_sn_coef_w_ag_min,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MIN);
+ writel(param_l->abpc_sn_coef_w_ag_mid,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MID);
+ writel(param_l->abpc_sn_coef_w_ag_max,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MAX);
+ writel(param_l->abpc_sn_coef_b_ag_min,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MIN);
+ writel(param_l->abpc_sn_coef_b_ag_mid,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MID);
+ writel(param_l->abpc_sn_coef_b_ag_max,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MAX);
+ writel((u32)param_l->abpc_sn_coef_w_th_min,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_TH_MIN);
+ writel((u32)param_l->abpc_sn_coef_w_th_max,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_TH_MAX);
+ writel((u32)param_l->abpc_sn_coef_b_th_min,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_TH_MIN);
+ writel((u32)param_l->abpc_sn_coef_b_th_max,
+ &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_TH_MAX);
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_dpc_table_transmission() -
+ * Configure L1ISP transferring defect pixel correction table.
+ *
+ * @table_h: defect pixel correction table for high sensitivity image(physical address)
+ * @table_m: defect pixel correction table for middle sensitivity or led image(physical address)
+ * @table_l: defect pixel correction table for low sensitivity image(physical address)
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "table_h", "table_m" or "table_l" is not 8byte alignment
+ *
+ * Note that when 0 is set to table address, table transfer of the table is disabled.
+ */
+s32 hwd_viif_l1_set_dpc_table_transmission(struct hwd_viif_res *res, uintptr_t table_h,
+ uintptr_t table_m, uintptr_t table_l)
+{
+ u32 val = 0x0U;
+
+ if (((table_h % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
+ ((table_m % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
+ ((table_l % HWD_VIIF_L1_VDM_ALIGN) != 0U)) {
+ return -EINVAL;
+ }
+
+ /* VDM common settings */
+
+ writel(HWD_VIIF_L1_VDM_CFG_PARAM, &res->capture_reg->vdm.t_group[0].VDM_T_CFG);
+ writel(HWD_VIIF_L1_VDM_SRAM_BASE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_BASE);
+ writel(HWD_VIIF_L1_VDM_SRAM_SIZE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_SIZE);
+
+ if (table_h != 0U) {
+ writel((u32)table_h, &res->capture_reg->vdm.t_port[0].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE, &res->capture_reg->vdm.t_port[0].VDM_T_SIZE);
+ val |= 0x1U;
+ }
+
+ if (table_m != 0U) {
+ writel((u32)table_m, &res->capture_reg->vdm.t_port[1].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE, &res->capture_reg->vdm.t_port[1].VDM_T_SIZE);
+ val |= 0x2U;
+ }
+
+ if (table_l != 0U) {
+ writel((u32)table_l, &res->capture_reg->vdm.t_port[2].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE, &res->capture_reg->vdm.t_port[2].VDM_T_SIZE);
+ val |= 0x4U;
+ }
+
+ val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) & 0xfffffff8U);
+ writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_preset_white_balance() - Configure L1ISP preset white balance parameters.
+ *
+ * @dstmaxval: maximum output pixel value [0..4095]
+ * @param_h: pointer to preset white balance parameters for high sensitivity image
+ * @param_m: pointer to preset white balance parameters for middle sensitivity or led image
+ * @param_l: pointer to preset white balance parameters for low sensitivity image
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "dstmaxval" is out of range
+ * - "param_h", "param_m", and "param_l" are NULL
+ * - each parameter of "param_h" is out of range
+ * - each parameter of "param_m" is out of range
+ * - each parameter of "param_l" is out of range
+ * Note that when NULL is set to "param_{h/m/l}", the corresponding parameters are not set to HW.
+ */
+s32 hwd_viif_l1_set_preset_white_balance(struct hwd_viif_res *res, u32 dstmaxval,
+ const struct viif_l1_preset_wb *param_h,
+ const struct viif_l1_preset_wb *param_m,
+ const struct viif_l1_preset_wb *param_l)
+{
+ if (dstmaxval > HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL || (!param_h && !param_m && !param_l))
+ return -EINVAL;
+
+ if (param_h) {
+ if (param_h->gain_gr >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_h->gain_r >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_h->gain_b >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_h->gain_gb >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
+ return -EINVAL;
+ }
+ }
+
+ if (param_m) {
+ if (param_m->gain_gr >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_m->gain_r >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_m->gain_b >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_m->gain_gb >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
+ return -EINVAL;
+ }
+ }
+
+ if (param_l) {
+ if (param_l->gain_gr >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_l->gain_r >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_l->gain_b >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
+ param_l->gain_gb >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
+ return -EINVAL;
+ }
+ }
+
+ writel(dstmaxval, &res->capture_reg->l1isp.L1_PWHB_DSTMAXVAL);
+
+ if (param_h) {
+ writel(param_h->gain_gr, &res->capture_reg->l1isp.L1_PWHB_H_GR);
+ writel(param_h->gain_r, &res->capture_reg->l1isp.L1_PWHB_HR);
+ writel(param_h->gain_b, &res->capture_reg->l1isp.L1_PWHB_HB);
+ writel(param_h->gain_gb, &res->capture_reg->l1isp.L1_PWHB_H_GB);
+ }
+
+ if (param_m) {
+ writel(param_m->gain_gr, &res->capture_reg->l1isp.L1_PWHB_M_GR);
+ writel(param_m->gain_r, &res->capture_reg->l1isp.L1_PWHB_MR);
+ writel(param_m->gain_b, &res->capture_reg->l1isp.L1_PWHB_MB);
+ writel(param_m->gain_gb, &res->capture_reg->l1isp.L1_PWHB_M_GB);
+ }
+
+ if (param_l) {
+ writel(param_l->gain_gr, &res->capture_reg->l1isp.L1_PWHB_L_GR);
+ writel(param_l->gain_r, &res->capture_reg->l1isp.L1_PWHB_LR);
+ writel(param_l->gain_b, &res->capture_reg->l1isp.L1_PWHB_LB);
+ writel(param_l->gain_gb, &res->capture_reg->l1isp.L1_PWHB_L_GB);
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_raw_color_noise_reduction() -
+ * Configure L1ISP raw color noise reduction parameters.
+ *
+ * @param_h: pointer to raw color noise reduction parameters for high sensitivity image
+ * @param_m: pointer to raw color noise reduction parameters for middle sensitivity or led image
+ * @param_l: pointer to raw color noise reduction parameters for low sensitivity image
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "param_h", "param_m", and "param_l" are NULL
+ * - each parameter of "param_h" is out of range
+ * - each parameter of "param_m" is out of range
+ * - each parameter of "param_l" is out of range
+ * Note that when NULL is set to "param_{h/m/l}", the corresponding parameters are not set to HW.
+ */
+s32 hwd_viif_l1_set_raw_color_noise_reduction(
+ struct hwd_viif_res *res, const struct viif_l1_raw_color_noise_reduction *param_h,
+ const struct viif_l1_raw_color_noise_reduction *param_m,
+ const struct viif_l1_raw_color_noise_reduction *param_l)
+{
+ const struct viif_l1_raw_color_noise_reduction *param;
+ u32 idx;
+
+ if (!param_h && !param_m && !param_l)
+ return -EINVAL;
+
+ for (idx = 0; idx < 3U; idx++) {
+ if (idx == 0U)
+ param = param_h;
+ else if (idx == 1U)
+ param = param_m;
+ else
+ param = param_l;
+
+ if (!param)
+ continue;
+
+ if (param->rcnr_sw != HWD_VIIF_ENABLE && param->rcnr_sw != HWD_VIIF_DISABLE)
+ return -EINVAL;
+
+ if (param->rcnr_cnf_dark_ag0 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
+ param->rcnr_cnf_dark_ag1 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
+ param->rcnr_cnf_dark_ag2 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
+ param->rcnr_cnf_ratio_ag0 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
+ param->rcnr_cnf_ratio_ag1 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
+ param->rcnr_cnf_ratio_ag2 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
+ param->rcnr_cnf_clip_gain_r > HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
+ param->rcnr_cnf_clip_gain_g > HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
+ param->rcnr_cnf_clip_gain_b > HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
+ param->rcnr_a1l_dark_ag0 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
+ param->rcnr_a1l_dark_ag1 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
+ param->rcnr_a1l_dark_ag2 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
+ param->rcnr_a1l_ratio_ag0 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
+ param->rcnr_a1l_ratio_ag1 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
+ param->rcnr_a1l_ratio_ag2 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
+ param->rcnr_inf_zero_clip > HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL ||
+ param->rcnr_merge_d2blend_ag0 > HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
+ param->rcnr_merge_d2blend_ag1 > HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
+ param->rcnr_merge_d2blend_ag2 > HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
+ param->rcnr_merge_black > HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL ||
+ param->rcnr_merge_mindiv < HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL ||
+ param->rcnr_merge_mindiv > HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL) {
+ return -EINVAL;
+ }
+
+ switch (param->rcnr_hry_type) {
+ case HWD_VIIF_L1_RCNR_LOW_RESOLUTION:
+ case HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION:
+ case HWD_VIIF_L1_RCNR_HIGH_RESOLUTION:
+ case HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (param->rcnr_anf_blend_ag0 != HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
+ param->rcnr_anf_blend_ag0 != HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
+ param->rcnr_anf_blend_ag0 != HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
+ return -EINVAL;
+ }
+ if (param->rcnr_anf_blend_ag1 != HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
+ param->rcnr_anf_blend_ag1 != HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
+ param->rcnr_anf_blend_ag1 != HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
+ return -EINVAL;
+ }
+ if (param->rcnr_anf_blend_ag2 != HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
+ param->rcnr_anf_blend_ag2 != HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
+ param->rcnr_anf_blend_ag2 != HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
+ return -EINVAL;
+ }
+
+ if (param->rcnr_lpf_threshold >= HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL ||
+ param->rcnr_merge_hlblend_ag0 > HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
+ param->rcnr_merge_hlblend_ag1 > HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
+ param->rcnr_merge_hlblend_ag2 > HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
+ (param->rcnr_gnr_sw != HWD_VIIF_DISABLE &&
+ param->rcnr_gnr_sw != HWD_VIIF_ENABLE)) {
+ return -EINVAL;
+ }
+
+ if (param->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
+ if (param->rcnr_gnr_ratio > HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO)
+ return -EINVAL;
+ if (param->rcnr_gnr_wide_en != HWD_VIIF_DISABLE &&
+ param->rcnr_gnr_wide_en != HWD_VIIF_ENABLE) {
+ return -EINVAL;
+ }
+ }
+ }
+
+ if (param_h) {
+ writel(param_h->rcnr_sw, &res->capture_reg->l1isp.L1_RCNR0_SW);
+
+ writel(param_h->rcnr_cnf_dark_ag0, &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG0);
+ writel(param_h->rcnr_cnf_dark_ag1, &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG1);
+ writel(param_h->rcnr_cnf_dark_ag2, &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG2);
+
+ writel(param_h->rcnr_cnf_ratio_ag0,
+ &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG0);
+ writel(param_h->rcnr_cnf_ratio_ag1,
+ &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG1);
+ writel(param_h->rcnr_cnf_ratio_ag2,
+ &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG2);
+
+ writel(param_h->rcnr_cnf_clip_gain_r,
+ &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_R);
+ writel(param_h->rcnr_cnf_clip_gain_g,
+ &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_G);
+ writel(param_h->rcnr_cnf_clip_gain_b,
+ &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_B);
+
+ writel(param_h->rcnr_a1l_dark_ag0, &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG0);
+ writel(param_h->rcnr_a1l_dark_ag1, &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG1);
+ writel(param_h->rcnr_a1l_dark_ag2, &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG2);
+
+ writel(param_h->rcnr_a1l_ratio_ag0,
+ &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG0);
+ writel(param_h->rcnr_a1l_ratio_ag1,
+ &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG1);
+ writel(param_h->rcnr_a1l_ratio_ag2,
+ &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG2);
+
+ writel(param_h->rcnr_inf_zero_clip,
+ &res->capture_reg->l1isp.L1_RCNR0_INF_ZERO_CLIP);
+
+ writel(param_h->rcnr_merge_d2blend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG0);
+ writel(param_h->rcnr_merge_d2blend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG1);
+ writel(param_h->rcnr_merge_d2blend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG2);
+ writel(param_h->rcnr_merge_black, &res->capture_reg->l1isp.L1_RCNR0_MERGE_BLACK);
+ writel(param_h->rcnr_merge_mindiv, &res->capture_reg->l1isp.L1_RCNR0_MERGE_MINDIV);
+
+ writel(param_h->rcnr_hry_type, &res->capture_reg->l1isp.L1_RCNR0_HRY_TYPE);
+
+ writel(param_h->rcnr_anf_blend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG0);
+ writel(param_h->rcnr_anf_blend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG1);
+ writel(param_h->rcnr_anf_blend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG2);
+
+ writel(param_h->rcnr_lpf_threshold,
+ &res->capture_reg->l1isp.L1_RCNR0_LPF_THRESHOLD);
+
+ writel(param_h->rcnr_merge_hlblend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG0);
+ writel(param_h->rcnr_merge_hlblend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG1);
+ writel(param_h->rcnr_merge_hlblend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG2);
+
+ writel(param_h->rcnr_gnr_sw, &res->capture_reg->l1isp.L1_RCNR0_GNR_SW);
+
+ if (param_h->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
+ writel(param_h->rcnr_gnr_ratio,
+ &res->capture_reg->l1isp.L1_RCNR0_GNR_RATIO);
+ writel(param_h->rcnr_gnr_wide_en,
+ &res->capture_reg->l1isp.L1_RCNR0_GNR_WIDE_EN);
+ }
+ }
+
+ if (param_m) {
+ writel(param_m->rcnr_sw, &res->capture_reg->l1isp.L1_RCNR1_SW);
+
+ writel(param_m->rcnr_cnf_dark_ag0, &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG0);
+ writel(param_m->rcnr_cnf_dark_ag1, &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG1);
+ writel(param_m->rcnr_cnf_dark_ag2, &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG2);
+
+ writel(param_m->rcnr_cnf_ratio_ag0,
+ &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG0);
+ writel(param_m->rcnr_cnf_ratio_ag1,
+ &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG1);
+ writel(param_m->rcnr_cnf_ratio_ag2,
+ &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG2);
+
+ writel(param_m->rcnr_cnf_clip_gain_r,
+ &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_R);
+ writel(param_m->rcnr_cnf_clip_gain_g,
+ &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_G);
+ writel(param_m->rcnr_cnf_clip_gain_b,
+ &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_B);
+
+ writel(param_m->rcnr_a1l_dark_ag0, &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG0);
+ writel(param_m->rcnr_a1l_dark_ag1, &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG1);
+ writel(param_m->rcnr_a1l_dark_ag2, &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG2);
+
+ writel(param_m->rcnr_a1l_ratio_ag0,
+ &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG0);
+ writel(param_m->rcnr_a1l_ratio_ag1,
+ &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG1);
+ writel(param_m->rcnr_a1l_ratio_ag2,
+ &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG2);
+
+ writel(param_m->rcnr_inf_zero_clip,
+ &res->capture_reg->l1isp.L1_RCNR1_INF_ZERO_CLIP);
+
+ writel(param_m->rcnr_merge_d2blend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG0);
+ writel(param_m->rcnr_merge_d2blend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG1);
+ writel(param_m->rcnr_merge_d2blend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG2);
+ writel(param_m->rcnr_merge_black, &res->capture_reg->l1isp.L1_RCNR1_MERGE_BLACK);
+ writel(param_m->rcnr_merge_mindiv, &res->capture_reg->l1isp.L1_RCNR1_MERGE_MINDIV);
+
+ writel(param_m->rcnr_hry_type, &res->capture_reg->l1isp.L1_RCNR1_HRY_TYPE);
+
+ writel(param_m->rcnr_anf_blend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG0);
+ writel(param_m->rcnr_anf_blend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG1);
+ writel(param_m->rcnr_anf_blend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG2);
+
+ writel(param_m->rcnr_lpf_threshold,
+ &res->capture_reg->l1isp.L1_RCNR1_LPF_THRESHOLD);
+
+ writel(param_m->rcnr_merge_hlblend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG0);
+ writel(param_m->rcnr_merge_hlblend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG1);
+ writel(param_m->rcnr_merge_hlblend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG2);
+
+ writel(param_m->rcnr_gnr_sw, &res->capture_reg->l1isp.L1_RCNR1_GNR_SW);
+
+ if (param_m->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
+ writel(param_m->rcnr_gnr_ratio,
+ &res->capture_reg->l1isp.L1_RCNR1_GNR_RATIO);
+ writel(param_m->rcnr_gnr_wide_en,
+ &res->capture_reg->l1isp.L1_RCNR1_GNR_WIDE_EN);
+ }
+ }
+
+ if (param_l) {
+ writel(param_l->rcnr_sw, &res->capture_reg->l1isp.L1_RCNR2_SW);
+
+ writel(param_l->rcnr_cnf_dark_ag0, &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG0);
+ writel(param_l->rcnr_cnf_dark_ag1, &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG1);
+ writel(param_l->rcnr_cnf_dark_ag2, &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG2);
+
+ writel(param_l->rcnr_cnf_ratio_ag0,
+ &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG0);
+ writel(param_l->rcnr_cnf_ratio_ag1,
+ &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG1);
+ writel(param_l->rcnr_cnf_ratio_ag2,
+ &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG2);
+
+ writel(param_l->rcnr_cnf_clip_gain_r,
+ &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_R);
+ writel(param_l->rcnr_cnf_clip_gain_g,
+ &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_G);
+ writel(param_l->rcnr_cnf_clip_gain_b,
+ &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_B);
+
+ writel(param_l->rcnr_a1l_dark_ag0, &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG0);
+ writel(param_l->rcnr_a1l_dark_ag1, &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG1);
+ writel(param_l->rcnr_a1l_dark_ag2, &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG2);
+
+ writel(param_l->rcnr_a1l_ratio_ag0,
+ &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG0);
+ writel(param_l->rcnr_a1l_ratio_ag1,
+ &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG1);
+ writel(param_l->rcnr_a1l_ratio_ag2,
+ &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG2);
+
+ writel(param_l->rcnr_inf_zero_clip,
+ &res->capture_reg->l1isp.L1_RCNR2_INF_ZERO_CLIP);
+
+ writel(param_l->rcnr_merge_d2blend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG0);
+ writel(param_l->rcnr_merge_d2blend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG1);
+ writel(param_l->rcnr_merge_d2blend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG2);
+ writel(param_l->rcnr_merge_black, &res->capture_reg->l1isp.L1_RCNR2_MERGE_BLACK);
+ writel(param_l->rcnr_merge_mindiv, &res->capture_reg->l1isp.L1_RCNR2_MERGE_MINDIV);
+
+ writel(param_l->rcnr_hry_type, &res->capture_reg->l1isp.L1_RCNR2_HRY_TYPE);
+
+ writel(param_l->rcnr_anf_blend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG0);
+ writel(param_l->rcnr_anf_blend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG1);
+ writel(param_l->rcnr_anf_blend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG2);
+
+ writel(param_l->rcnr_lpf_threshold,
+ &res->capture_reg->l1isp.L1_RCNR2_LPF_THRESHOLD);
+
+ writel(param_l->rcnr_merge_hlblend_ag0,
+ &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG0);
+ writel(param_l->rcnr_merge_hlblend_ag1,
+ &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG1);
+ writel(param_l->rcnr_merge_hlblend_ag2,
+ &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG2);
+
+ writel(param_l->rcnr_gnr_sw, &res->capture_reg->l1isp.L1_RCNR2_GNR_SW);
+
+ if (param_l->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
+ writel(param_l->rcnr_gnr_ratio,
+ &res->capture_reg->l1isp.L1_RCNR2_GNR_RATIO);
+ writel(param_l->rcnr_gnr_wide_en,
+ &res->capture_reg->l1isp.L1_RCNR2_GNR_WIDE_EN);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_hdrs() - Configure L1ISP HDR synthesis parameters.
+ *
+ * @param: pointer to HDR synthesis parameters
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "param" is NULL
+ * - each parameter of "param" is out of range
+ */
+s32 hwd_viif_l1_set_hdrs(struct hwd_viif_res *res, const struct viif_l1_hdrs_config *param)
+{
+ if (!param ||
+ (param->hdrs_hdr_mode != HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE &&
+ param->hdrs_hdr_mode != HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) ||
+ param->hdrs_hdr_ratio_m < HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
+ param->hdrs_hdr_ratio_m > HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
+ param->hdrs_hdr_ratio_l < HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
+ param->hdrs_hdr_ratio_l > HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
+ param->hdrs_hdr_ratio_e < HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
+ param->hdrs_hdr_ratio_e > HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
+ param->hdrs_dg_h >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
+ param->hdrs_dg_m >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
+ param->hdrs_dg_l >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
+ param->hdrs_dg_e >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
+ param->hdrs_blendend_h > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
+ param->hdrs_blendend_m > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
+ param->hdrs_blendend_e > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
+ param->hdrs_blendbeg_h > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
+ param->hdrs_blendbeg_m > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
+ param->hdrs_blendbeg_e > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
+ (param->hdrs_led_mode_on != HWD_VIIF_ENABLE &&
+ param->hdrs_led_mode_on != HWD_VIIF_DISABLE) ||
+ param->hdrs_dst_max_val > HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL) {
+ return -EINVAL;
+ }
+
+ writel(param->hdrs_hdr_mode, &res->capture_reg->l1isp.L1_HDRS_HDRMODE);
+
+ writel(param->hdrs_hdr_ratio_m, &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_M);
+ writel(param->hdrs_hdr_ratio_l, &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_L);
+ writel(param->hdrs_hdr_ratio_e, &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_E);
+
+ writel(param->hdrs_dg_h, &res->capture_reg->l1isp.L1_HDRS_DG_H);
+ writel(param->hdrs_dg_m, &res->capture_reg->l1isp.L1_HDRS_DG_M);
+ writel(param->hdrs_dg_l, &res->capture_reg->l1isp.L1_HDRS_DG_L);
+ writel(param->hdrs_dg_e, &res->capture_reg->l1isp.L1_HDRS_DG_E);
+
+ writel(param->hdrs_blendend_h, &res->capture_reg->l1isp.L1_HDRS_BLENDEND_H);
+ writel(param->hdrs_blendend_m, &res->capture_reg->l1isp.L1_HDRS_BLENDEND_M);
+ writel(param->hdrs_blendend_e, &res->capture_reg->l1isp.L1_HDRS_BLENDEND_E);
+
+ writel(param->hdrs_blendbeg_h, &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_H);
+ writel(param->hdrs_blendbeg_m, &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_M);
+ writel(param->hdrs_blendbeg_e, &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_E);
+
+ writel(param->hdrs_led_mode_on, &res->capture_reg->l1isp.L1_HDRS_LEDMODE_ON);
+ writel(param->hdrs_dst_max_val, &res->capture_reg->l1isp.L1_HDRS_DSTMAXVAL);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_black_level_correction() - Configure L1ISP black level correction parameters.
+ *
+ * @param: pointer to black level correction parameters
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "param" is NULL
+ * - each parameter of "param" is out of range
+ */
+s32 hwd_viif_l1_set_black_level_correction(
+ struct hwd_viif_res *res, const struct viif_l1_black_level_correction_config *param)
+{
+ if (!param || param->srcblacklevel_gr > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
+ param->srcblacklevel_r > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
+ param->srcblacklevel_b > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
+ param->srcblacklevel_gb > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
+ param->mulval_gr >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
+ param->mulval_r >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
+ param->mulval_b >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
+ param->mulval_gb >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
+ param->dstmaxval > HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL) {
+ return -EINVAL;
+ }
+
+ writel(param->srcblacklevel_gr, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_GR);
+ writel(param->srcblacklevel_r, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_R);
+ writel(param->srcblacklevel_b, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_B);
+ writel(param->srcblacklevel_gb, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVELGB);
+
+ writel(param->mulval_gr, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_GR);
+ writel(param->mulval_r, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_R);
+ writel(param->mulval_b, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_B);
+ writel(param->mulval_gb, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_GB);
+
+ writel(param->dstmaxval, &res->capture_reg->l1isp.L1_BLVC_DSTMAXVAL);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_lsc() - Configure L1ISP lens shading correction parameters.
+ *
+ * @param: pointer to lens shading correction parameters
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - each parameter of "param" is out of range
+ * @note when NULL is set to "param"
+ */
+s32 hwd_viif_l1_set_lsc(struct hwd_viif_res *res, const struct hwd_viif_l1_lsc *param)
+{
+ u32 sysm_width, sysm_height;
+ u32 grid_h_size = 0U;
+ u32 grid_v_size = 0U;
+ s32 ret = 0;
+ u32 idx;
+ u32 val;
+ u32 tmp;
+
+ if (!param) {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_LSSC_EN);
+ return 0;
+ }
+
+ sysm_width = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
+ sysm_height = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
+
+ if (param->lssc_parabola_param) {
+ if (param->lssc_parabola_param->lssc_para_h_center >= sysm_width ||
+ param->lssc_parabola_param->lssc_para_v_center >= sysm_height ||
+ param->lssc_parabola_param->lssc_para_h_gain >= HWD_VIIF_LSC_MAX_GAIN ||
+ param->lssc_parabola_param->lssc_para_v_gain >= HWD_VIIF_LSC_MAX_GAIN) {
+ return -EINVAL;
+ }
+
+ switch (param->lssc_parabola_param->lssc_para_mgsel2) {
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH:
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH:
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND:
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (param->lssc_parabola_param->lssc_para_mgsel4) {
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH:
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH:
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND:
+ case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (idx = 0U; idx < 8U; idx++) {
+ const struct viif_l1_lsc_parabola_ag_param *ag_param;
+
+ switch (idx) {
+ case 0U:
+ ag_param = ¶m->lssc_parabola_param->r_2d;
+ break;
+ case 1U:
+ ag_param = ¶m->lssc_parabola_param->r_4d;
+ break;
+ case 2U:
+ ag_param = ¶m->lssc_parabola_param->gr_2d;
+ break;
+ case 3U:
+ ag_param = ¶m->lssc_parabola_param->gr_4d;
+ break;
+ case 4U:
+ ag_param = ¶m->lssc_parabola_param->gb_2d;
+ break;
+ case 5U:
+ ag_param = ¶m->lssc_parabola_param->gb_4d;
+ break;
+ case 6U:
+ ag_param = ¶m->lssc_parabola_param->b_2d;
+ break;
+ default:
+ ag_param = ¶m->lssc_parabola_param->b_4d;
+ break;
+ }
+
+ if (!ag_param || ag_param->lssc_paracoef_h_l_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_h_l_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_h_l_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_h_l_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_h_l_min > ag_param->lssc_paracoef_h_l_max ||
+ ag_param->lssc_paracoef_h_r_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_h_r_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_h_r_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_h_r_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_h_r_min > ag_param->lssc_paracoef_h_r_max ||
+ ag_param->lssc_paracoef_v_u_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_v_u_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_v_u_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_v_u_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_v_u_min > ag_param->lssc_paracoef_v_u_max ||
+ ag_param->lssc_paracoef_v_d_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_v_d_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_v_d_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_v_d_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_v_d_min > ag_param->lssc_paracoef_v_d_max ||
+ ag_param->lssc_paracoef_hv_lu_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_lu_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_lu_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_lu_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_lu_min > ag_param->lssc_paracoef_hv_lu_max ||
+ ag_param->lssc_paracoef_hv_ru_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_ru_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_ru_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_ru_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_ru_min > ag_param->lssc_paracoef_hv_ru_max ||
+ ag_param->lssc_paracoef_hv_ld_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_ld_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_ld_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_ld_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_ld_min > ag_param->lssc_paracoef_hv_ld_max ||
+ ag_param->lssc_paracoef_hv_rd_max < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_rd_max >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_rd_min < HWD_VIIF_LSC_MIN_GAIN ||
+ ag_param->lssc_paracoef_hv_rd_min >= HWD_VIIF_LSC_MAX_GAIN ||
+ ag_param->lssc_paracoef_hv_rd_min > ag_param->lssc_paracoef_hv_rd_max) {
+ return -EINVAL;
+ }
+ }
+ }
+
+ if (param->lssc_grid_param) {
+ switch (param->lssc_grid_param->lssc_grid_h_size) {
+ case 32U:
+ grid_h_size = 5U;
+ break;
+ case 64U:
+ grid_h_size = 6U;
+ break;
+ case 128U:
+ grid_h_size = 7U;
+ break;
+ case 256U:
+ grid_h_size = 8U;
+ break;
+ case 512U:
+ grid_h_size = 9U;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret != 0)
+ return ret;
+
+ switch (param->lssc_grid_param->lssc_grid_v_size) {
+ case 32U:
+ grid_v_size = 5U;
+ break;
+ case 64U:
+ grid_v_size = 6U;
+ break;
+ case 128U:
+ grid_v_size = 7U;
+ break;
+ case 256U:
+ grid_v_size = 8U;
+ break;
+ case 512U:
+ grid_v_size = 9U;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret != 0)
+ return ret;
+
+ if (param->lssc_grid_param->lssc_grid_h_center < HWD_VIIF_LSC_GRID_MIN_COORDINATE ||
+ param->lssc_grid_param->lssc_grid_h_center >
+ param->lssc_grid_param->lssc_grid_h_size) {
+ return -EINVAL;
+ }
+
+ if (sysm_width > (param->lssc_grid_param->lssc_grid_h_center +
+ (param->lssc_grid_param->lssc_grid_h_size * 31U))) {
+ return -EINVAL;
+ }
+
+ if (param->lssc_grid_param->lssc_grid_v_center < HWD_VIIF_LSC_GRID_MIN_COORDINATE ||
+ param->lssc_grid_param->lssc_grid_v_center >
+ param->lssc_grid_param->lssc_grid_v_size) {
+ return -EINVAL;
+ }
+
+ if (sysm_height > (param->lssc_grid_param->lssc_grid_v_center +
+ (param->lssc_grid_param->lssc_grid_v_size * 23U))) {
+ return -EINVAL;
+ }
+
+ if (param->lssc_grid_param->lssc_grid_mgsel != HWD_VIIF_L1_GRID_COEF_GAIN_X1 &&
+ param->lssc_grid_param->lssc_grid_mgsel != HWD_VIIF_L1_GRID_COEF_GAIN_X2) {
+ return -EINVAL;
+ }
+ }
+
+ if (param->lssc_pwhb_r_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_r_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_r_gain_min > param->lssc_pwhb_r_gain_max ||
+ param->lssc_pwhb_gr_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_gr_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_gr_gain_min > param->lssc_pwhb_gr_gain_max ||
+ param->lssc_pwhb_gb_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_gb_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_gb_gain_min > param->lssc_pwhb_gb_gain_max ||
+ param->lssc_pwhb_b_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_b_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
+ param->lssc_pwhb_b_gain_min > param->lssc_pwhb_b_gain_max) {
+ return -EINVAL;
+ }
+
+ /* parabola shading */
+ if (param->lssc_parabola_param) {
+ struct viif_l1_lsc_parabola_ag_param *r_2d;
+ struct viif_l1_lsc_parabola_ag_param *r_4d;
+ struct viif_l1_lsc_parabola_ag_param *gr_2d;
+ struct viif_l1_lsc_parabola_ag_param *gr_4d;
+ struct viif_l1_lsc_parabola_ag_param *gb_2d;
+ struct viif_l1_lsc_parabola_ag_param *gb_4d;
+ struct viif_l1_lsc_parabola_ag_param *b_2d;
+ struct viif_l1_lsc_parabola_ag_param *b_4d;
+
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_PARA_EN);
+
+ writel(param->lssc_parabola_param->lssc_para_h_center,
+ &res->capture_reg->l1isp.L1_LSSC_PARA_H_CENTER);
+ writel(param->lssc_parabola_param->lssc_para_v_center,
+ &res->capture_reg->l1isp.L1_LSSC_PARA_V_CENTER);
+
+ writel(param->lssc_parabola_param->lssc_para_h_gain,
+ &res->capture_reg->l1isp.L1_LSSC_PARA_H_GAIN);
+ writel(param->lssc_parabola_param->lssc_para_v_gain,
+ &res->capture_reg->l1isp.L1_LSSC_PARA_V_GAIN);
+
+ writel(param->lssc_parabola_param->lssc_para_mgsel2,
+ &res->capture_reg->l1isp.L1_LSSC_PARA_MGSEL2);
+ writel(param->lssc_parabola_param->lssc_para_mgsel4,
+ &res->capture_reg->l1isp.L1_LSSC_PARA_MGSEL4);
+
+ /* R 2D */
+ r_2d = ¶m->lssc_parabola_param->r_2d;
+ tmp = (u32)r_2d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_H_L);
+
+ tmp = (u32)r_2d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_H_R);
+
+ tmp = (u32)r_2d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_V_U);
+
+ tmp = (u32)r_2d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_V_D);
+
+ tmp = (u32)r_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_LU);
+
+ tmp = (u32)r_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_RU);
+
+ tmp = (u32)r_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_LD);
+
+ tmp = (u32)r_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_RD);
+
+ /* R 4D */
+ r_4d = ¶m->lssc_parabola_param->r_4d;
+ tmp = (u32)r_4d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_H_L);
+
+ tmp = (u32)r_4d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_H_R);
+
+ tmp = (u32)r_4d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_V_U);
+
+ tmp = (u32)r_4d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_V_D);
+
+ tmp = (u32)r_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_LU);
+
+ tmp = (u32)r_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_RU);
+
+ tmp = (u32)r_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_LD);
+
+ tmp = (u32)r_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_RD);
+
+ /* GR 2D */
+ gr_2d = ¶m->lssc_parabola_param->gr_2d;
+ tmp = (u32)gr_2d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_H_L);
+
+ tmp = (u32)gr_2d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_H_R);
+
+ tmp = (u32)gr_2d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_V_U);
+
+ tmp = (u32)gr_2d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_V_D);
+
+ tmp = (u32)gr_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_LU);
+
+ tmp = (u32)gr_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_RU);
+
+ tmp = (u32)gr_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_LD);
+
+ tmp = (u32)gr_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_RD);
+
+ /* GR 4D */
+ gr_4d = ¶m->lssc_parabola_param->gr_4d;
+ tmp = (u32)gr_4d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_H_L);
+
+ tmp = (u32)gr_4d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_H_R);
+
+ tmp = (u32)gr_4d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_V_U);
+
+ tmp = (u32)gr_4d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_V_D);
+
+ tmp = (u32)gr_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_LU);
+
+ tmp = (u32)gr_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_RU);
+
+ tmp = (u32)gr_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_LD);
+
+ tmp = (u32)gr_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_RD);
+
+ /* GB 2D */
+ gb_2d = ¶m->lssc_parabola_param->gb_2d;
+ tmp = (u32)gb_2d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_H_L);
+
+ tmp = (u32)gb_2d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_H_R);
+
+ tmp = (u32)gb_2d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_V_U);
+
+ tmp = (u32)gb_2d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_V_D);
+
+ tmp = (u32)gb_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_LU);
+
+ tmp = (u32)gb_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_RU);
+
+ tmp = (u32)gb_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_LD);
+
+ tmp = (u32)gb_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_RD);
+
+ /* GB 4D */
+ gb_4d = ¶m->lssc_parabola_param->gb_4d;
+ tmp = (u32)gb_4d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_H_L);
+
+ tmp = (u32)gb_4d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_H_R);
+
+ tmp = (u32)gb_4d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_V_U);
+
+ tmp = (u32)gb_4d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_V_D);
+
+ tmp = (u32)gb_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_LU);
+
+ tmp = (u32)gb_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_RU);
+
+ tmp = (u32)gb_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_LD);
+
+ tmp = (u32)gb_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_RD);
+
+ /* B 2D */
+ b_2d = ¶m->lssc_parabola_param->b_2d;
+ tmp = (u32)b_2d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_H_L);
+
+ tmp = (u32)b_2d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_H_R);
+
+ tmp = (u32)b_2d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_V_U);
+
+ tmp = (u32)b_2d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_V_D);
+
+ tmp = (u32)b_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_LU);
+
+ tmp = (u32)b_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_RU);
+
+ tmp = (u32)b_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_LD);
+
+ tmp = (u32)b_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_RD);
+
+ /* B 4D */
+ b_4d = ¶m->lssc_parabola_param->b_4d;
+ tmp = (u32)b_4d->lssc_paracoef_h_l_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_h_l_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_H_L);
+
+ tmp = (u32)b_4d->lssc_paracoef_h_r_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_h_r_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_H_R);
+
+ tmp = (u32)b_4d->lssc_paracoef_v_u_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_v_u_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_V_U);
+
+ tmp = (u32)b_4d->lssc_paracoef_v_d_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_v_d_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_V_D);
+
+ tmp = (u32)b_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_LU);
+
+ tmp = (u32)b_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_RU);
+
+ tmp = (u32)b_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_LD);
+
+ tmp = (u32)b_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
+ val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_RD);
+
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_LSSC_PARA_EN);
+ }
+
+ /* grid shading */
+ if (param->lssc_grid_param) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_GRID_EN);
+ writel(grid_h_size, &res->capture_reg->l1isp.L1_LSSC_GRID_H_SIZE);
+ writel(grid_v_size, &res->capture_reg->l1isp.L1_LSSC_GRID_V_SIZE);
+ writel(param->lssc_grid_param->lssc_grid_h_center,
+ &res->capture_reg->l1isp.L1_LSSC_GRID_H_CENTER);
+ writel(param->lssc_grid_param->lssc_grid_v_center,
+ &res->capture_reg->l1isp.L1_LSSC_GRID_V_CENTER);
+ writel(param->lssc_grid_param->lssc_grid_mgsel,
+ &res->capture_reg->l1isp.L1_LSSC_GRID_MGSEL);
+
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_LSSC_GRID_EN);
+ }
+
+ /* preset white balance */
+ val = (param->lssc_pwhb_r_gain_max << 16U) | (param->lssc_pwhb_r_gain_min);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_R_GAIN);
+
+ val = (param->lssc_pwhb_gr_gain_max << 16U) | (param->lssc_pwhb_gr_gain_min);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_GR_GAIN);
+
+ val = (param->lssc_pwhb_gb_gain_max << 16U) | (param->lssc_pwhb_gb_gain_min);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_GB_GAIN);
+
+ val = (param->lssc_pwhb_b_gain_max << 16U) | (param->lssc_pwhb_b_gain_min);
+ writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_B_GAIN);
+
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_EN);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_lsc_table_transmission() - Configure L1ISP transferring lens shading grid table.
+ *
+ * @table_gr: grid shading table for Gr(physical address)
+ * @table_r: grid shading table for R(physical address)
+ * @table_b: grid shading table for B(physical address)
+ * @table_gb: grid shading table for Gb(physical address)
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "table_h", "table_m" or "table_l" is not 8byte alignment
+ *
+ * Note that when 0 is set to table address, table transfer of the table is disabled.
+ */
+s32 hwd_viif_l1_set_lsc_table_transmission(struct hwd_viif_res *res, uintptr_t table_gr,
+ uintptr_t table_r, uintptr_t table_b, uintptr_t table_gb)
+{
+ u32 val = 0x0U;
+
+ if (((table_gr % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
+ ((table_r % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
+ ((table_b % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
+ ((table_gb % HWD_VIIF_L1_VDM_ALIGN) != 0U)) {
+ return -EINVAL;
+ }
+ /* VDM common settings */
+ writel(HWD_VIIF_L1_VDM_CFG_PARAM, &res->capture_reg->vdm.t_group[0].VDM_T_CFG);
+ writel(HWD_VIIF_L1_VDM_SRAM_BASE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_BASE);
+ writel(HWD_VIIF_L1_VDM_SRAM_SIZE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_SIZE);
+
+ if (table_gr != 0U) {
+ writel((u32)table_gr, &res->capture_reg->vdm.t_port[4].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[4].VDM_T_SIZE);
+ val |= 0x10U;
+ }
+
+ if (table_r != 0U) {
+ writel((u32)table_r, &res->capture_reg->vdm.t_port[5].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[5].VDM_T_SIZE);
+ val |= 0x20U;
+ }
+
+ if (table_b != 0U) {
+ writel((u32)table_b, &res->capture_reg->vdm.t_port[6].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[6].VDM_T_SIZE);
+ val |= 0x40U;
+ }
+
+ if (table_gb != 0U) {
+ writel((u32)table_gb, &res->capture_reg->vdm.t_port[7].VDM_T_STADR);
+ writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[7].VDM_T_SIZE);
+ val |= 0x80U;
+ }
+
+ val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) & 0xffffff0fU);
+ writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_main_process() - Configure L1ISP main process.
+ *
+ * @demosaic_mode: demosaic mode @ref hwd_viif_l1_demosaic
+ * @damp_lsbsel: output pixel clip range for auto white balance [0..15]
+ * @color_matrix: pointer to color matrix correction parameters
+ * @dst_maxval: output pixel maximum value [0x0..0xffffff]
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * main process means digital amp, demosaic, and color matrix correction
+ * NULL means disabling color matrix correction
+ * - "demosaic_mode" is neither HWD_VIIF_L1_DEMOSAIC_ACPI nor HWD_VIIF_L1_DEMOSAIC_DMG
+ * - "damp_lsbsel" is out of range
+ * - each parameter of "color_matrix" is out of range
+ * - "dst_maxval" is out of range
+ */
+s32 hwd_viif_l1_set_main_process(struct hwd_viif_res *res, u32 demosaic_mode, u32 damp_lsbsel,
+ const struct viif_l1_color_matrix_correction *color_matrix,
+ u32 dst_maxval)
+{
+ u32 val;
+
+ if (demosaic_mode != HWD_VIIF_L1_DEMOSAIC_ACPI &&
+ demosaic_mode != HWD_VIIF_L1_DEMOSAIC_DMG) {
+ return -EINVAL;
+ }
+
+ if (damp_lsbsel > HWD_VIIF_DAMP_MAX_LSBSEL)
+ return -EINVAL;
+
+ if (color_matrix) {
+ if (color_matrix->coef_rmg_min > color_matrix->coef_rmg_max ||
+ color_matrix->coef_rmb_min > color_matrix->coef_rmb_max ||
+ color_matrix->coef_gmr_min > color_matrix->coef_gmr_max ||
+ color_matrix->coef_gmb_min > color_matrix->coef_gmb_max ||
+ color_matrix->coef_bmr_min > color_matrix->coef_bmr_max ||
+ color_matrix->coef_bmg_min > color_matrix->coef_bmg_max ||
+ (u32)color_matrix->dst_minval > dst_maxval)
+ return -EINVAL;
+ }
+
+ if (dst_maxval > HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL)
+ return -EINVAL;
+
+ val = damp_lsbsel << 4U;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_CONF);
+
+ writel(demosaic_mode, &res->capture_reg->l1isp.L1_MPRO_LCS_MODE);
+
+ if (color_matrix) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_MPRO_SW);
+
+ val = (u32)color_matrix->coef_rmg_min & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMG_MIN);
+
+ val = (u32)color_matrix->coef_rmg_max & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMG_MAX);
+
+ val = (u32)color_matrix->coef_rmb_min & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMB_MIN);
+
+ val = (u32)color_matrix->coef_rmb_max & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMB_MAX);
+
+ val = (u32)color_matrix->coef_gmr_min & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMR_MIN);
+
+ val = (u32)color_matrix->coef_gmr_max & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMR_MAX);
+
+ val = (u32)color_matrix->coef_gmb_min & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMB_MIN);
+
+ val = (u32)color_matrix->coef_gmb_max & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMB_MAX);
+
+ val = (u32)color_matrix->coef_bmr_min & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMR_MIN);
+
+ val = (u32)color_matrix->coef_bmr_max & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMR_MAX);
+
+ val = (u32)color_matrix->coef_bmg_min & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMG_MIN);
+
+ val = (u32)color_matrix->coef_bmg_max & 0xffffU;
+ writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMG_MAX);
+
+ writel((u32)color_matrix->dst_minval, &res->capture_reg->l1isp.L1_MPRO_DST_MINVAL);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_MPRO_SW);
+ }
+
+ writel(dst_maxval, &res->capture_reg->l1isp.L1_MPRO_DST_MAXVAL);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_awb() - Configure L1ISP auto white balance parameters.
+ *
+ * @param: pointer to auto white balance parameters; NULL means disabling auto white balance
+ * @awhb_wbmrg: R gain of white balance adjustment [0x40..0x3FF] accuracy: 1/256
+ * @awhb_wbmgg: G gain of white balance adjustment [0x40..0x3FF] accuracy: 1/256
+ * @awhb_wbmbg: B gain of white balance adjustment [0x40..0x3FF] accuracy: 1/256
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL
+ * - each parameter of "param" is out of range
+ * - awhb_wbm*g is out of range
+ */
+s32 hwd_viif_l1_set_awb(struct hwd_viif_res *res, const struct viif_l1_awb *param, u32 awhb_wbmrg,
+ u32 awhb_wbmgg, u32 awhb_wbmbg)
+{
+ u32 val, ygate_data;
+
+ if (awhb_wbmrg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmrg >= HWD_VIIF_AWB_MAX_GAIN ||
+ awhb_wbmgg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmgg >= HWD_VIIF_AWB_MAX_GAIN ||
+ awhb_wbmbg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmbg >= HWD_VIIF_AWB_MAX_GAIN) {
+ return -EINVAL;
+ }
+
+ if (param) {
+ if (param->awhb_ygate_sel != HWD_VIIF_ENABLE &&
+ param->awhb_ygate_sel != HWD_VIIF_DISABLE) {
+ return -EINVAL;
+ }
+
+ if (param->awhb_ygate_data != 64U && param->awhb_ygate_data != 128U &&
+ param->awhb_ygate_data != 256U && param->awhb_ygate_data != 512U) {
+ return -EINVAL;
+ }
+
+ if (param->awhb_cgrange != HWD_VIIF_L1_AWB_ONE_SECOND &&
+ param->awhb_cgrange != HWD_VIIF_L1_AWB_X1 &&
+ param->awhb_cgrange != HWD_VIIF_L1_AWB_X2 &&
+ param->awhb_cgrange != HWD_VIIF_L1_AWB_X4) {
+ return -EINVAL;
+ }
+
+ if (param->awhb_ygatesw != HWD_VIIF_ENABLE &&
+ param->awhb_ygatesw != HWD_VIIF_DISABLE) {
+ return -EINVAL;
+ }
+
+ if (param->awhb_hexsw != HWD_VIIF_ENABLE && param->awhb_hexsw != HWD_VIIF_DISABLE)
+ return -EINVAL;
+
+ if (param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE0 &&
+ param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE1 &&
+ param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE2 &&
+ param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE3) {
+ return -EINVAL;
+ }
+
+ val = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
+ if (param->awhb_area_hsize < 1U || (param->awhb_area_hsize > ((val - 8U) / 8U)) ||
+ param->awhb_area_hofs > (val - 9U)) {
+ return -EINVAL;
+ }
+
+ val = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
+ if (param->awhb_area_vsize < 1U || (param->awhb_area_vsize > ((val - 4U) / 8U)) ||
+ param->awhb_area_vofs > (val - 5U)) {
+ return -EINVAL;
+ }
+
+ if ((param->awhb_sq_sw[0] != HWD_VIIF_ENABLE &&
+ param->awhb_sq_sw[0] != HWD_VIIF_DISABLE) ||
+ (param->awhb_sq_sw[1] != HWD_VIIF_ENABLE &&
+ param->awhb_sq_sw[1] != HWD_VIIF_DISABLE) ||
+ (param->awhb_sq_sw[2] != HWD_VIIF_ENABLE &&
+ param->awhb_sq_sw[2] != HWD_VIIF_DISABLE) ||
+ (param->awhb_sq_pol[0] != HWD_VIIF_ENABLE &&
+ param->awhb_sq_pol[0] != HWD_VIIF_DISABLE) ||
+ (param->awhb_sq_pol[1] != HWD_VIIF_ENABLE &&
+ param->awhb_sq_pol[1] != HWD_VIIF_DISABLE) ||
+ (param->awhb_sq_pol[2] != HWD_VIIF_ENABLE &&
+ param->awhb_sq_pol[2] != HWD_VIIF_DISABLE)) {
+ return -EINVAL;
+ }
+
+ if (param->awhb_bycut0p > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_bycut0n > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_rycut0p > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_rycut0n > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_rbcut0h < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_rbcut0h > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_rbcut0l < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_rbcut0l > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_bycut_h[0] < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_bycut_h[0] > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_bycut_h[1] < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_bycut_h[1] > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_bycut_h[2] < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_bycut_h[2] > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_bycut_l[0] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_bycut_l[1] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_bycut_l[2] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_rycut_h[0] < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_rycut_h[0] > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_rycut_h[1] < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_rycut_h[1] > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_rycut_h[2] < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_rycut_h[2] > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_rycut_l[0] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_rycut_l[1] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_rycut_l[2] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
+ param->awhb_awbsftu < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_awbsftu > HWD_VIIF_AWB_GATE_UPPER ||
+ param->awhb_awbsftv < HWD_VIIF_AWB_GATE_LOWER ||
+ param->awhb_awbsftv > HWD_VIIF_AWB_GATE_UPPER ||
+ (param->awhb_awbhuecor != HWD_VIIF_ENABLE &&
+ param->awhb_awbhuecor != HWD_VIIF_DISABLE)) {
+ return -EINVAL;
+ }
+
+ if (param->awhb_awbspd > HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED ||
+ param->awhb_awbulv > HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL ||
+ param->awhb_awbvlv > HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL ||
+ param->awhb_awbondot > HWD_VIIF_AWB_INTEGRATION_STOP_TH) {
+ return -EINVAL;
+ }
+
+ switch (param->awhb_awbfztim) {
+ case HWD_VIIF_L1_AWB_RESTART_NO:
+ case HWD_VIIF_L1_AWB_RESTART_128FRAME:
+ case HWD_VIIF_L1_AWB_RESTART_64FRAME:
+ case HWD_VIIF_L1_AWB_RESTART_32FRAME:
+ case HWD_VIIF_L1_AWB_RESTART_16FRAME:
+ case HWD_VIIF_L1_AWB_RESTART_8FRAME:
+ case HWD_VIIF_L1_AWB_RESTART_4FRAME:
+ case HWD_VIIF_L1_AWB_RESTART_2FRAME:
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ writel(awhb_wbmrg, &res->capture_reg->l1isp.L1_AWHB_WBMRG);
+ writel(awhb_wbmgg, &res->capture_reg->l1isp.L1_AWHB_WBMGG);
+ writel(awhb_wbmbg, &res->capture_reg->l1isp.L1_AWHB_WBMBG);
+
+ val = readl(&res->capture_reg->l1isp.L1_AWHB_SW) & 0xffffff7fU;
+
+ if (param) {
+ val |= (HWD_VIIF_ENABLE << 7U);
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
+
+ if (param->awhb_ygate_data == 64U)
+ ygate_data = 0U;
+ else if (param->awhb_ygate_data == 128U)
+ ygate_data = 1U;
+ else if (param->awhb_ygate_data == 256U)
+ ygate_data = 2U;
+ else
+ ygate_data = 3U;
+
+ val = (param->awhb_ygate_sel << 7U) | (ygate_data << 5U) | (param->awhb_cgrange);
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_GATE_CONF0);
+
+ val = (param->awhb_ygatesw << 5U) | (param->awhb_hexsw << 4U) |
+ (param->awhb_areamode);
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_GATE_CONF1);
+
+ writel(param->awhb_area_hsize, &res->capture_reg->l1isp.L1_AWHB_AREA_HSIZE);
+ writel(param->awhb_area_vsize, &res->capture_reg->l1isp.L1_AWHB_AREA_VSIZE);
+ writel(param->awhb_area_hofs, &res->capture_reg->l1isp.L1_AWHB_AREA_HOFS);
+ writel(param->awhb_area_vofs, &res->capture_reg->l1isp.L1_AWHB_AREA_VOFS);
+
+ writel(param->awhb_area_maskh, &res->capture_reg->l1isp.L1_AWHB_AREA_MASKH);
+ writel(param->awhb_area_maskl, &res->capture_reg->l1isp.L1_AWHB_AREA_MASKL);
+
+ val = (param->awhb_sq_sw[0] << 7U) | (param->awhb_sq_pol[0] << 6U) |
+ (param->awhb_sq_sw[1] << 5U) | (param->awhb_sq_pol[1] << 4U) |
+ (param->awhb_sq_sw[2] << 3U) | (param->awhb_sq_pol[2] << 2U);
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_SQ_CONF);
+
+ writel((u32)param->awhb_ygateh, &res->capture_reg->l1isp.L1_AWHB_YGATEH);
+ writel((u32)param->awhb_ygatel, &res->capture_reg->l1isp.L1_AWHB_YGATEL);
+
+ writel(param->awhb_bycut0p, &res->capture_reg->l1isp.L1_AWHB_BYCUT0P);
+ writel(param->awhb_bycut0n, &res->capture_reg->l1isp.L1_AWHB_BYCUT0N);
+ writel(param->awhb_rycut0p, &res->capture_reg->l1isp.L1_AWHB_RYCUT0P);
+ writel(param->awhb_rycut0n, &res->capture_reg->l1isp.L1_AWHB_RYCUT0N);
+
+ val = (u32)param->awhb_rbcut0h & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_RBCUT0H);
+ val = (u32)param->awhb_rbcut0l & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_RBCUT0L);
+
+ val = (u32)param->awhb_bycut_h[0] & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT1H);
+ writel(param->awhb_bycut_l[0], &res->capture_reg->l1isp.L1_AWHB_BYCUT1L);
+ val = (u32)param->awhb_bycut_h[1] & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT2H);
+ writel(param->awhb_bycut_l[1], &res->capture_reg->l1isp.L1_AWHB_BYCUT2L);
+ val = (u32)param->awhb_bycut_h[2] & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT3H);
+ writel(param->awhb_bycut_l[2], &res->capture_reg->l1isp.L1_AWHB_BYCUT3L);
+
+ val = (u32)param->awhb_rycut_h[0] & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT1H);
+ writel(param->awhb_rycut_l[0], &res->capture_reg->l1isp.L1_AWHB_RYCUT1L);
+ val = (u32)param->awhb_rycut_h[1] & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT2H);
+ writel(param->awhb_rycut_l[1], &res->capture_reg->l1isp.L1_AWHB_RYCUT2L);
+ val = (u32)param->awhb_rycut_h[2] & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT3H);
+ writel(param->awhb_rycut_l[2], &res->capture_reg->l1isp.L1_AWHB_RYCUT3L);
+
+ val = (u32)param->awhb_awbsftu & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSFTU);
+ val = (u32)param->awhb_awbsftv & 0xffU;
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSFTV);
+
+ val = (param->awhb_awbhuecor << 4U) | (param->awhb_awbspd);
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSPD);
+
+ writel(param->awhb_awbulv, &res->capture_reg->l1isp.L1_AWHB_AWBULV);
+ writel(param->awhb_awbvlv, &res->capture_reg->l1isp.L1_AWHB_AWBVLV);
+ writel((u32)param->awhb_awbwait, &res->capture_reg->l1isp.L1_AWHB_AWBWAIT);
+
+ writel(param->awhb_awbondot, &res->capture_reg->l1isp.L1_AWHB_AWBONDOT);
+ writel(param->awhb_awbfztim, &res->capture_reg->l1isp.L1_AWHB_AWBFZTIM);
+
+ writel((u32)param->awhb_wbgrmax, &res->capture_reg->l1isp.L1_AWHB_WBGRMAX);
+ writel((u32)param->awhb_wbgbmax, &res->capture_reg->l1isp.L1_AWHB_WBGBMAX);
+ writel((u32)param->awhb_wbgrmin, &res->capture_reg->l1isp.L1_AWHB_WBGRMIN);
+ writel((u32)param->awhb_wbgbmin, &res->capture_reg->l1isp.L1_AWHB_WBGBMIN);
+
+ } else {
+ /* disable awb */
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_lock_awb_gain() - Configure L1ISP lock auto white balance gain.
+ *
+ * @enable: enable/disable lock AWB gain
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - "enable" is neither HWD_VIIF_ENABLE nor HWD_VIIF_DISABLE
+ */
+s32 hwd_viif_l1_lock_awb_gain(struct hwd_viif_res *res, u32 enable)
+{
+ u32 val;
+
+ if (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
+ return -EINVAL;
+
+ val = readl(&res->capture_reg->l1isp.L1_AWHB_SW) & 0xffffffdfU;
+ val |= (enable << 5U);
+ writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_hdrc() - Configure L1ISP HDR compression parameters.
+ *
+ * @param: pointer to HDR compression parameters
+ * @hdrc_thr_sft_amt: shift value in case of through mode [0..8]
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - each parameter of "param" is out of range
+ * - hdrc_thr_sft_amt is out of range when param is NULL
+ * - hdrc_thr_sft_amt is not 0 when param is not NULL
+ */
+s32 hwd_viif_l1_set_hdrc(struct hwd_viif_res *res, const struct viif_l1_hdrc *param,
+ u32 hdrc_thr_sft_amt)
+{
+ u32 val, sw_delay1;
+
+ if (!param) {
+ if (hdrc_thr_sft_amt > HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL)
+ return -EINVAL;
+
+ writel(hdrc_thr_sft_amt, &res->capture_reg->l1isp.L1_HDRC_THR_SFT_AMT);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_HDRC_EN);
+
+ return 0;
+ }
+
+ if (hdrc_thr_sft_amt != 0U || param->hdrc_ratio < HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH ||
+ param->hdrc_ratio > HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH ||
+ param->hdrc_pt_ratio > HWD_VIIF_L1_HDRC_MAX_PT_SLOPE ||
+ param->hdrc_pt_blend > HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
+ param->hdrc_pt_blend2 > HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
+ (param->hdrc_pt_blend + param->hdrc_pt_blend2) > HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
+ (param->hdrc_tn_type != HWD_VIIF_L1_HDRC_TONE_USER &&
+ param->hdrc_tn_type != HWD_VIIF_L1_HDRC_TONE_PRESET) ||
+ param->hdrc_flr_val > HWD_VIIF_L1_HDRC_MAX_FLARE_VAL ||
+ (param->hdrc_flr_adp != HWD_VIIF_ENABLE && param->hdrc_flr_adp != HWD_VIIF_DISABLE) ||
+ (param->hdrc_ybr_off != HWD_VIIF_ENABLE && param->hdrc_ybr_off != HWD_VIIF_DISABLE) ||
+ param->hdrc_orgy_blend > HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA) {
+ return -EINVAL;
+ }
+
+ writel((param->hdrc_ratio - HWD_VIIF_L1_HDRC_RATIO_OFFSET),
+ &res->capture_reg->l1isp.L1_HDRC_RATIO);
+ writel(param->hdrc_pt_ratio, &res->capture_reg->l1isp.L1_HDRC_PT_RATIO);
+
+ writel(param->hdrc_pt_blend, &res->capture_reg->l1isp.L1_HDRC_PT_BLEND);
+ writel(param->hdrc_pt_blend2, &res->capture_reg->l1isp.L1_HDRC_PT_BLEND2);
+
+ writel(param->hdrc_pt_sat, &res->capture_reg->l1isp.L1_HDRC_PT_SAT);
+ writel(param->hdrc_tn_type, &res->capture_reg->l1isp.L1_HDRC_TN_TYPE);
+
+ writel(param->hdrc_utn_tbl[0], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL0);
+ writel(param->hdrc_utn_tbl[1], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL1);
+ writel(param->hdrc_utn_tbl[2], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL2);
+ writel(param->hdrc_utn_tbl[3], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL3);
+ writel(param->hdrc_utn_tbl[4], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL4);
+ writel(param->hdrc_utn_tbl[5], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL5);
+ writel(param->hdrc_utn_tbl[6], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL6);
+ writel(param->hdrc_utn_tbl[7], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL7);
+ writel(param->hdrc_utn_tbl[8], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL8);
+ writel(param->hdrc_utn_tbl[9], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL9);
+ writel(param->hdrc_utn_tbl[10], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL10);
+ writel(param->hdrc_utn_tbl[11], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL11);
+ writel(param->hdrc_utn_tbl[12], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL12);
+ writel(param->hdrc_utn_tbl[13], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL13);
+ writel(param->hdrc_utn_tbl[14], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL14);
+ writel(param->hdrc_utn_tbl[15], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL15);
+ writel(param->hdrc_utn_tbl[16], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL16);
+ writel(param->hdrc_utn_tbl[17], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL17);
+ writel(param->hdrc_utn_tbl[18], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL18);
+ writel(param->hdrc_utn_tbl[19], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL19);
+
+ writel(param->hdrc_flr_val, &res->capture_reg->l1isp.L1_HDRC_FLR_VAL);
+ writel(param->hdrc_flr_adp, &res->capture_reg->l1isp.L1_HDRC_FLR_ADP);
+
+ writel(param->hdrc_ybr_off, &res->capture_reg->l1isp.L1_HDRC_YBR_OFF);
+ writel(param->hdrc_orgy_blend, &res->capture_reg->l1isp.L1_HDRC_ORGY_BLEND);
+
+ val = ((readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT)) % 64U) / 2U;
+ writel(val, &res->capture_reg->l1isp.L1_HDRC_MAR_TOP);
+ val = ((readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH)) % 64U) / 2U;
+ writel(val, &res->capture_reg->l1isp.L1_HDRC_MAR_LEFT);
+
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_HDRC_EN);
+
+ /* update of sw_delay1 must be done when MAIN unit is NOT running. */
+ if (!res->run_flag_main) {
+ sw_delay1 = (u32)((HWD_VIIF_REGBUF_ACCESS_TIME * (u64)res->pixel_clock) /
+ ((u64)res->htotal_size * HWD_VIIF_SYS_CLK)) +
+ HWD_VIIF_L1_DELAY_W_HDRC + 1U;
+ val = readl(&res->capture_reg->sys.INT_M1_LINE) & 0xffffU;
+ val |= (sw_delay1 << 16U);
+ writel(val, &res->capture_reg->sys.INT_M1_LINE);
+ /* M2_LINE is the same condition as M1_LINE */
+ writel(val, &res->capture_reg->sys.INT_M2_LINE);
+ }
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_hdrc_ltm() - Configure L1ISP HDR compression local tone mapping parameters.
+ *
+ * @param: pointer to HDR compression local tone mapping parameters
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL
+ * - "param" is NULL
+ * - each parameter of "param" is out of range
+ */
+s32 hwd_viif_l1_set_hdrc_ltm(struct hwd_viif_res *res, const struct viif_l1_hdrc_ltm_config *param)
+{
+ u32 val;
+ u32 idx;
+
+ if (!param || param->tnp_max >= HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO ||
+ param->tnp_mag >= HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION) {
+ return -EINVAL;
+ }
+
+ val = (u32)param->tnp_fil[0];
+ for (idx = 1; idx < 5U; idx++)
+ val += (u32)param->tnp_fil[idx] * 2U;
+
+ if (val != 1024U)
+ return -EINVAL;
+
+ writel(param->tnp_max, &res->capture_reg->l1isp.L1_HDRC_TNP_MAX);
+
+ writel(param->tnp_mag, &res->capture_reg->l1isp.L1_HDRC_TNP_MAG);
+
+ writel((u32)param->tnp_fil[0], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL0);
+ writel((u32)param->tnp_fil[1], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL1);
+ writel((u32)param->tnp_fil[2], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL2);
+ writel((u32)param->tnp_fil[3], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL3);
+ writel((u32)param->tnp_fil[4], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL4);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_gamma() - Configure L1ISP gamma correction parameters.
+ *
+ * @param: pointer to gamma correction parameters
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - each parameter of "param" is out of range
+ */
+s32 hwd_viif_l1_set_gamma(struct hwd_viif_res *res, const struct viif_l1_gamma *param)
+{
+ u32 idx;
+
+ if (!param) {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_PGC_SW);
+ return 0;
+ }
+
+ for (idx = 0; idx < 44U; idx++) {
+ if (param->gam_p[idx] > HWD_VIIF_L1_GAMMA_MAX_VAL)
+ return -EINVAL;
+ }
+
+ writel(param->gam_p[0], &res->capture_reg->l1isp.L1_VPRO_GAM01P);
+ writel(param->gam_p[1], &res->capture_reg->l1isp.L1_VPRO_GAM02P);
+ writel(param->gam_p[2], &res->capture_reg->l1isp.L1_VPRO_GAM03P);
+ writel(param->gam_p[3], &res->capture_reg->l1isp.L1_VPRO_GAM04P);
+ writel(param->gam_p[4], &res->capture_reg->l1isp.L1_VPRO_GAM05P);
+ writel(param->gam_p[5], &res->capture_reg->l1isp.L1_VPRO_GAM06P);
+ writel(param->gam_p[6], &res->capture_reg->l1isp.L1_VPRO_GAM07P);
+ writel(param->gam_p[7], &res->capture_reg->l1isp.L1_VPRO_GAM08P);
+ writel(param->gam_p[8], &res->capture_reg->l1isp.L1_VPRO_GAM09P);
+ writel(param->gam_p[9], &res->capture_reg->l1isp.L1_VPRO_GAM10P);
+ writel(param->gam_p[10], &res->capture_reg->l1isp.L1_VPRO_GAM11P);
+ writel(param->gam_p[11], &res->capture_reg->l1isp.L1_VPRO_GAM12P);
+ writel(param->gam_p[12], &res->capture_reg->l1isp.L1_VPRO_GAM13P);
+ writel(param->gam_p[13], &res->capture_reg->l1isp.L1_VPRO_GAM14P);
+ writel(param->gam_p[14], &res->capture_reg->l1isp.L1_VPRO_GAM15P);
+ writel(param->gam_p[15], &res->capture_reg->l1isp.L1_VPRO_GAM16P);
+ writel(param->gam_p[16], &res->capture_reg->l1isp.L1_VPRO_GAM17P);
+ writel(param->gam_p[17], &res->capture_reg->l1isp.L1_VPRO_GAM18P);
+ writel(param->gam_p[18], &res->capture_reg->l1isp.L1_VPRO_GAM19P);
+ writel(param->gam_p[19], &res->capture_reg->l1isp.L1_VPRO_GAM20P);
+ writel(param->gam_p[20], &res->capture_reg->l1isp.L1_VPRO_GAM21P);
+ writel(param->gam_p[21], &res->capture_reg->l1isp.L1_VPRO_GAM22P);
+ writel(param->gam_p[22], &res->capture_reg->l1isp.L1_VPRO_GAM23P);
+ writel(param->gam_p[23], &res->capture_reg->l1isp.L1_VPRO_GAM24P);
+ writel(param->gam_p[24], &res->capture_reg->l1isp.L1_VPRO_GAM25P);
+ writel(param->gam_p[25], &res->capture_reg->l1isp.L1_VPRO_GAM26P);
+ writel(param->gam_p[26], &res->capture_reg->l1isp.L1_VPRO_GAM27P);
+ writel(param->gam_p[27], &res->capture_reg->l1isp.L1_VPRO_GAM28P);
+ writel(param->gam_p[28], &res->capture_reg->l1isp.L1_VPRO_GAM29P);
+ writel(param->gam_p[29], &res->capture_reg->l1isp.L1_VPRO_GAM30P);
+ writel(param->gam_p[30], &res->capture_reg->l1isp.L1_VPRO_GAM31P);
+ writel(param->gam_p[31], &res->capture_reg->l1isp.L1_VPRO_GAM32P);
+ writel(param->gam_p[32], &res->capture_reg->l1isp.L1_VPRO_GAM33P);
+ writel(param->gam_p[33], &res->capture_reg->l1isp.L1_VPRO_GAM34P);
+ writel(param->gam_p[34], &res->capture_reg->l1isp.L1_VPRO_GAM35P);
+ writel(param->gam_p[35], &res->capture_reg->l1isp.L1_VPRO_GAM36P);
+ writel(param->gam_p[36], &res->capture_reg->l1isp.L1_VPRO_GAM37P);
+ writel(param->gam_p[37], &res->capture_reg->l1isp.L1_VPRO_GAM38P);
+ writel(param->gam_p[38], &res->capture_reg->l1isp.L1_VPRO_GAM39P);
+ writel(param->gam_p[39], &res->capture_reg->l1isp.L1_VPRO_GAM40P);
+ writel(param->gam_p[40], &res->capture_reg->l1isp.L1_VPRO_GAM41P);
+ writel(param->gam_p[41], &res->capture_reg->l1isp.L1_VPRO_GAM42P);
+ writel(param->gam_p[42], &res->capture_reg->l1isp.L1_VPRO_GAM43P);
+ writel(param->gam_p[43], &res->capture_reg->l1isp.L1_VPRO_GAM44P);
+ writel(param->blkadj, &res->capture_reg->l1isp.L1_VPRO_BLKADJ);
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_PGC_SW);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_img_quality_adjustment() - Configure L1ISP image quality adjustment.
+ *
+ * @param: pointer to image quality adjustment parameters; NULL means disabling
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - each parameter of "param" is out of range
+ */
+s32 hwd_viif_l1_set_img_quality_adjustment(struct hwd_viif_res *res,
+ const struct hwd_viif_l1_img_quality_adjustment *param)
+{
+ u32 val;
+
+ if (!param) {
+ /* disable all features when param is absent */
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_YUVC_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
+ writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
+ writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
+ writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CNR_SW);
+
+ return 0;
+ }
+
+ if (param->lum_noise_reduction) {
+ if (param->lum_noise_reduction->gain_min > param->lum_noise_reduction->gain_max ||
+ param->lum_noise_reduction->lim_min > param->lum_noise_reduction->lim_max) {
+ return -EINVAL;
+ }
+ }
+
+ if (param->edge_enhancement) {
+ if (param->edge_enhancement->gain_min > param->edge_enhancement->gain_max ||
+ param->edge_enhancement->lim_min > param->edge_enhancement->lim_max ||
+ param->edge_enhancement->coring_min > param->edge_enhancement->coring_max) {
+ return -EINVAL;
+ }
+ }
+
+ if (param->uv_suppression) {
+ if (param->uv_suppression->bk_mp >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
+ param->uv_suppression->black >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
+ param->uv_suppression->wh_mp >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
+ param->uv_suppression->white >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
+ param->uv_suppression->bk_slv >= param->uv_suppression->wh_slv)
+ return -EINVAL;
+ }
+
+ if (param->coring_suppression) {
+ if (param->coring_suppression->gain_min > param->coring_suppression->gain_max ||
+ param->coring_suppression->lv_min > param->coring_suppression->lv_max)
+ return -EINVAL;
+ }
+
+ if (param->edge_suppression) {
+ if (param->edge_suppression->lim > HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT)
+ return -EINVAL;
+ }
+
+ if (param->color_level) {
+ if (param->color_level->cb_gain >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
+ param->color_level->cr_gain >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
+ param->color_level->cbr_mgain_min >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
+ param->color_level->cbp_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
+ param->color_level->cbm_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
+ param->color_level->crp_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
+ param->color_level->crm_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN) {
+ return -EINVAL;
+ }
+ }
+
+ if (param->color_noise_reduction_enable != HWD_VIIF_ENABLE &&
+ param->color_noise_reduction_enable != HWD_VIIF_DISABLE) {
+ return -EINVAL;
+ }
+
+ /* RGB to YUV */
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_YUVC_SW);
+ writel((u32)param->coef_cb, &res->capture_reg->l1isp.L1_VPRO_CB_MAT);
+ writel((u32)param->coef_cr, &res->capture_reg->l1isp.L1_VPRO_CR_MAT);
+
+ /* brightness */
+ val = (u32)param->brightness & 0xffffU;
+ if (val != 0U) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
+ writel(val, &res->capture_reg->l1isp.L1_VPRO_BRIGHT);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
+ }
+
+ /* linear contrast */
+ if ((u32)param->linear_contrast != 128U) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
+ writel((u32)param->linear_contrast, &res->capture_reg->l1isp.L1_VPRO_LCONT_LEV);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
+ }
+
+ /* nonlinear contrast */
+ if (param->nonlinear_contrast) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
+ writel((u32)param->nonlinear_contrast->blk_knee,
+ &res->capture_reg->l1isp.L1_VPRO_BLK_KNEE);
+ writel((u32)param->nonlinear_contrast->wht_knee,
+ &res->capture_reg->l1isp.L1_VPRO_WHT_KNEE);
+
+ writel((u32)param->nonlinear_contrast->blk_cont[0],
+ &res->capture_reg->l1isp.L1_VPRO_BLK_CONT0);
+ writel((u32)param->nonlinear_contrast->blk_cont[1],
+ &res->capture_reg->l1isp.L1_VPRO_BLK_CONT1);
+ writel((u32)param->nonlinear_contrast->blk_cont[2],
+ &res->capture_reg->l1isp.L1_VPRO_BLK_CONT2);
+
+ writel((u32)param->nonlinear_contrast->wht_cont[0],
+ &res->capture_reg->l1isp.L1_VPRO_WHT_CONT0);
+ writel((u32)param->nonlinear_contrast->wht_cont[1],
+ &res->capture_reg->l1isp.L1_VPRO_WHT_CONT1);
+ writel((u32)param->nonlinear_contrast->wht_cont[2],
+ &res->capture_reg->l1isp.L1_VPRO_WHT_CONT2);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
+ }
+
+ /* luminance noise reduction */
+ if (param->lum_noise_reduction) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
+ writel((u32)param->lum_noise_reduction->gain_min,
+ &res->capture_reg->l1isp.L1_VPRO_YNR_GAIN_MIN);
+ writel((u32)param->lum_noise_reduction->gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_YNR_GAIN_MAX);
+ writel((u32)param->lum_noise_reduction->lim_min,
+ &res->capture_reg->l1isp.L1_VPRO_YNR_LIM_MIN);
+ writel((u32)param->lum_noise_reduction->lim_max,
+ &res->capture_reg->l1isp.L1_VPRO_YNR_LIM_MAX);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
+ }
+
+ /* edge enhancement */
+ if (param->edge_enhancement) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
+ writel((u32)param->edge_enhancement->gain_min,
+ &res->capture_reg->l1isp.L1_VPRO_ETE_GAIN_MIN);
+ writel((u32)param->edge_enhancement->gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_ETE_GAIN_MAX);
+ writel((u32)param->edge_enhancement->lim_min,
+ &res->capture_reg->l1isp.L1_VPRO_ETE_LIM_MIN);
+ writel((u32)param->edge_enhancement->lim_max,
+ &res->capture_reg->l1isp.L1_VPRO_ETE_LIM_MAX);
+ writel((u32)param->edge_enhancement->coring_min,
+ &res->capture_reg->l1isp.L1_VPRO_ETE_CORING_MIN);
+ writel((u32)param->edge_enhancement->coring_max,
+ &res->capture_reg->l1isp.L1_VPRO_ETE_CORING_MAX);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
+ }
+
+ /* UV suppression */
+ if (param->uv_suppression) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
+ writel((u32)param->uv_suppression->bk_slv,
+ &res->capture_reg->l1isp.L1_VPRO_CSUP_BK_SLV);
+ writel(param->uv_suppression->bk_mp, &res->capture_reg->l1isp.L1_VPRO_CSUP_BK_MP);
+ writel(param->uv_suppression->black, &res->capture_reg->l1isp.L1_VPRO_CSUP_BLACK);
+
+ writel((u32)param->uv_suppression->wh_slv,
+ &res->capture_reg->l1isp.L1_VPRO_CSUP_WH_SLV);
+ writel(param->uv_suppression->wh_mp, &res->capture_reg->l1isp.L1_VPRO_CSUP_WH_MP);
+ writel(param->uv_suppression->white, &res->capture_reg->l1isp.L1_VPRO_CSUP_WHITE);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
+ }
+
+ /* coring suppression */
+ if (param->coring_suppression) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
+ writel((u32)param->coring_suppression->lv_min,
+ &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_LV_MIN);
+ writel((u32)param->coring_suppression->lv_max,
+ &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_LV_MAX);
+ writel((u32)param->coring_suppression->gain_min,
+ &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_GAIN_MIN);
+ writel((u32)param->coring_suppression->gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_GAIN_MAX);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
+ }
+
+ /* edge suppression */
+ if (param->edge_suppression) {
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
+ writel((u32)param->edge_suppression->gain,
+ &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_GAIN);
+ writel((u32)param->edge_suppression->lim,
+ &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_LIM);
+ } else {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
+ }
+
+ /* color level */
+ if (param->color_level) {
+ writel(param->color_level->cb_gain, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
+ writel(param->color_level->cr_gain, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
+ writel(param->color_level->cbr_mgain_min,
+ &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
+ writel(param->color_level->cbp_gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
+ writel(param->color_level->cbm_gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
+ writel(param->color_level->crp_gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
+ writel(param->color_level->crm_gain_max,
+ &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
+ } else {
+ /* disable */
+ writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
+ writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
+ writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
+ writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
+ }
+
+ /* color noise reduction */
+ writel(param->color_noise_reduction_enable, &res->capture_reg->l1isp.L1_VPRO_CNR_SW);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_avg_lum_generation() - Configure L1ISP average luminance generation parameters.
+ *
+ * @param: pointer to auto exposure parameters
+ * Return: 0 operation completed successfully
+ * Return: -EINVAL Parameter error
+ * - each parameter of "param" is out of range
+ */
+s32 hwd_viif_l1_set_avg_lum_generation(struct hwd_viif_res *res,
+ const struct viif_l1_avg_lum_generation_config *param)
+{
+ u32 idx, j;
+ u32 val;
+
+ if (!param) {
+ writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_AEXP_ON);
+ return 0;
+ }
+
+ val = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
+ if (param->aexp_start_x > (val - 1U))
+ return -EINVAL;
+
+ if (param->aexp_block_width < HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH ||
+ param->aexp_block_width > val) {
+ return -EINVAL;
+ }
+ if (param->aexp_block_width % 64U)
+ return -EINVAL;
+
+ val = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
+ if (param->aexp_start_y > (val - 1U))
+ return -EINVAL;
+
+ if (param->aexp_block_height < HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT ||
+ param->aexp_block_height > val) {
+ return -EINVAL;
+ }
+ if (param->aexp_block_height % 64U)
+ return -EINVAL;
+
+ for (idx = 0; idx < 8U; idx++) {
+ for (j = 0; j < 8U; j++) {
+ if (param->aexp_weight[idx][j] > HWD_VIIF_L1_AEXP_MAX_WEIGHT)
+ return -EINVAL;
+ }
+ }
+
+ if (param->aexp_satur_ratio > HWD_VIIF_L1_AEXP_MAX_BLOCK_TH ||
+ param->aexp_black_ratio > HWD_VIIF_L1_AEXP_MAX_BLOCK_TH ||
+ param->aexp_satur_level > HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH) {
+ return -EINVAL;
+ }
+
+ for (idx = 0; idx < 4U; idx++) {
+ if (param->aexp_ave4linesy[idx] > (val - 4U))
+ return -EINVAL;
+ }
+
+ writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_AEXP_ON);
+ writel(param->aexp_start_x, &res->capture_reg->l1isp.L1_AEXP_START_X);
+ writel(param->aexp_start_y, &res->capture_reg->l1isp.L1_AEXP_START_Y);
+ writel(param->aexp_block_width, &res->capture_reg->l1isp.L1_AEXP_BLOCK_WIDTH);
+ writel(param->aexp_block_height, &res->capture_reg->l1isp.L1_AEXP_BLOCK_HEIGHT);
+
+ val = (param->aexp_weight[0][0] << 14U) | (param->aexp_weight[0][1] << 12U) |
+ (param->aexp_weight[0][2] << 10U) | (param->aexp_weight[0][3] << 8U) |
+ (param->aexp_weight[0][4] << 6U) | (param->aexp_weight[0][5] << 4U) |
+ (param->aexp_weight[0][6] << 2U) | (param->aexp_weight[0][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_0);
+
+ val = (param->aexp_weight[1][0] << 14U) | (param->aexp_weight[1][1] << 12U) |
+ (param->aexp_weight[1][2] << 10U) | (param->aexp_weight[1][3] << 8U) |
+ (param->aexp_weight[1][4] << 6U) | (param->aexp_weight[1][5] << 4U) |
+ (param->aexp_weight[1][6] << 2U) | (param->aexp_weight[1][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_1);
+
+ val = (param->aexp_weight[2][0] << 14U) | (param->aexp_weight[2][1] << 12U) |
+ (param->aexp_weight[2][2] << 10U) | (param->aexp_weight[2][3] << 8U) |
+ (param->aexp_weight[2][4] << 6U) | (param->aexp_weight[2][5] << 4U) |
+ (param->aexp_weight[2][6] << 2U) | (param->aexp_weight[2][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_2);
+
+ val = (param->aexp_weight[3][0] << 14U) | (param->aexp_weight[3][1] << 12U) |
+ (param->aexp_weight[3][2] << 10U) | (param->aexp_weight[3][3] << 8U) |
+ (param->aexp_weight[3][4] << 6U) | (param->aexp_weight[3][5] << 4U) |
+ (param->aexp_weight[3][6] << 2U) | (param->aexp_weight[3][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_3);
+
+ val = (param->aexp_weight[4][0] << 14U) | (param->aexp_weight[4][1] << 12U) |
+ (param->aexp_weight[4][2] << 10U) | (param->aexp_weight[4][3] << 8U) |
+ (param->aexp_weight[4][4] << 6U) | (param->aexp_weight[4][5] << 4U) |
+ (param->aexp_weight[4][6] << 2U) | (param->aexp_weight[4][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_4);
+
+ val = (param->aexp_weight[5][0] << 14U) | (param->aexp_weight[5][1] << 12U) |
+ (param->aexp_weight[5][2] << 10U) | (param->aexp_weight[5][3] << 8U) |
+ (param->aexp_weight[5][4] << 6U) | (param->aexp_weight[5][5] << 4U) |
+ (param->aexp_weight[5][6] << 2U) | (param->aexp_weight[5][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_5);
+
+ val = (param->aexp_weight[6][0] << 14U) | (param->aexp_weight[6][1] << 12U) |
+ (param->aexp_weight[6][2] << 10U) | (param->aexp_weight[6][3] << 8U) |
+ (param->aexp_weight[6][4] << 6U) | (param->aexp_weight[6][5] << 4U) |
+ (param->aexp_weight[6][6] << 2U) | (param->aexp_weight[6][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_6);
+
+ val = (param->aexp_weight[7][0] << 14U) | (param->aexp_weight[7][1] << 12U) |
+ (param->aexp_weight[7][2] << 10U) | (param->aexp_weight[7][3] << 8U) |
+ (param->aexp_weight[7][4] << 6U) | (param->aexp_weight[7][5] << 4U) |
+ (param->aexp_weight[7][6] << 2U) | (param->aexp_weight[7][7]);
+ writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_7);
+
+ writel(param->aexp_satur_ratio, &res->capture_reg->l1isp.L1_AEXP_SATUR_RATIO);
+ writel(param->aexp_black_ratio, &res->capture_reg->l1isp.L1_AEXP_BLACK_RATIO);
+ writel(param->aexp_satur_level, &res->capture_reg->l1isp.L1_AEXP_SATUR_LEVEL);
+
+ writel(param->aexp_ave4linesy[0], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY0);
+ writel(param->aexp_ave4linesy[1], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY1);
+ writel(param->aexp_ave4linesy[2], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY2);
+ writel(param->aexp_ave4linesy[3], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY3);
+
+ return 0;
+}
+
+/**
+ * hwd_viif_l1_set_irq_mask() - Set L1ISP interruption mask.
+ *
+ * @mask: mask setting
+ * Return: None
+ */
+void hwd_viif_l1_set_irq_mask(struct hwd_viif_res *res, u32 mask)
+{
+ writel(mask, &res->capture_reg->l1isp.L1_CRGBF_ISP_INT_MASK);
+}
diff --git a/drivers/media/platform/visconti/viif_controls.c b/drivers/media/platform/visconti/viif_controls.c
new file mode 100644
index 00000000000..2793fb0a807
--- /dev/null
+++ b/drivers/media/platform/visconti/viif_controls.c
@@ -0,0 +1,1153 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+/* Toshiba Visconti Video Capture Support
+ *
+ * (C) Copyright 2022 TOSHIBA CORPORATION
+ * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-subdev.h>
+
+#include "viif.h"
+
+static int viif_main_set_rawpack_mode(struct viif_device *viif_dev, u32 *rawpack)
+{
+ if (vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
+ return -EBUSY;
+
+ if (*rawpack == VIIF_RAWPACK_DISABLE) {
+ viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_DISABLE;
+ return 0;
+ }
+ if (*rawpack == VIIF_RAWPACK_MSBFIRST) {
+ viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_MSBFIRST;
+ return 0;
+ }
+ if (*rawpack == VIIF_RAWPACK_LSBFIRST) {
+ viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_LSBFIRST;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int viif_l1_set_input_mode(struct viif_device *viif_dev,
+ struct viif_l1_input_mode_config *input_mode)
+{
+ u32 mode, raw_color_filter;
+ unsigned long irqflags;
+ int ret;
+
+ /* SDR input is not supported */
+ if (input_mode->mode == VIIF_L1_INPUT_HDR)
+ mode = HWD_VIIF_L1_INPUT_HDR;
+ else if (input_mode->mode == VIIF_L1_INPUT_PWL)
+ mode = HWD_VIIF_L1_INPUT_PWL;
+ else if (input_mode->mode == VIIF_L1_INPUT_HDR_IMG_CORRECT)
+ mode = HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT;
+ else if (input_mode->mode == VIIF_L1_INPUT_PWL_IMG_CORRECT)
+ mode = HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT;
+ else
+ return -EINVAL;
+
+ if (input_mode->raw_color_filter == VIIF_L1_RAW_GR_R_B_GB)
+ raw_color_filter = HWD_VIIF_L1_RAW_GR_R_B_GB;
+ else if (input_mode->raw_color_filter == VIIF_L1_RAW_R_GR_GB_B)
+ raw_color_filter = HWD_VIIF_L1_RAW_R_GR_GB_B;
+ else if (input_mode->raw_color_filter == VIIF_L1_RAW_B_GB_GR_R)
+ raw_color_filter = HWD_VIIF_L1_RAW_B_GB_GR_R;
+ else if (input_mode->raw_color_filter == VIIF_L1_RAW_GB_B_R_GR)
+ raw_color_filter = HWD_VIIF_L1_RAW_GB_B_R_GR;
+ else
+ return -EINVAL;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_input_mode(viif_dev->hwd_res, mode, input_mode->depth,
+ raw_color_filter);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_rgb_to_y_coef(struct viif_device *viif_dev,
+ struct viif_l1_rgb_to_y_coef_config *l1_rgb_to_y_coef)
+{
+ int ret;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_rgb_to_y_coef(viif_dev->hwd_res, l1_rgb_to_y_coef->coef_r,
+ l1_rgb_to_y_coef->coef_g, l1_rgb_to_y_coef->coef_b);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_ag_mode(struct viif_device *viif_dev,
+ struct viif_l1_ag_mode_config *l1_ag_mode)
+{
+ int ret;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_ag_mode(viif_dev->hwd_res, l1_ag_mode);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_ag(struct viif_device *viif_dev, struct viif_l1_ag_config *l1_ag)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_ag(viif_dev->hwd_res, l1_ag->gain_h, l1_ag->gain_m, l1_ag->gain_l);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_hdre(struct viif_device *viif_dev, struct viif_l1_hdre_config *l1_hdre)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_hdre(viif_dev->hwd_res, l1_hdre);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_img_extraction(struct viif_device *viif_dev,
+ struct viif_l1_img_extraction_config *img_extract)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_img_extraction(viif_dev->hwd_res, img_extract->input_black_gr,
+ img_extract->input_black_r, img_extract->input_black_b,
+ img_extract->input_black_gb);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192
+static int viif_l1_set_dpc(struct viif_device *viif_dev, struct viif_l1_dpc_config *l1_dpc)
+{
+ uintptr_t table_h_paddr = 0;
+ uintptr_t table_m_paddr = 0;
+ uintptr_t table_l_paddr = 0;
+ unsigned long irqflags;
+ int ret;
+
+ if (l1_dpc->table_h_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
+ u64_to_user_ptr(l1_dpc->table_h_addr),
+ VISCONTI_VIIF_DPC_TABLE_SIZE))
+ return -EFAULT;
+ table_h_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_h;
+ }
+ if (l1_dpc->table_m_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->dpc_table_m,
+ u64_to_user_ptr(l1_dpc->table_m_addr),
+ VISCONTI_VIIF_DPC_TABLE_SIZE))
+ return -EFAULT;
+ table_m_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_m;
+ }
+ if (l1_dpc->table_l_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->dpc_table_l,
+ u64_to_user_ptr(l1_dpc->table_l_addr),
+ VISCONTI_VIIF_DPC_TABLE_SIZE))
+ return -EFAULT;
+ table_l_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_l;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_dpc_table_transmission(viif_dev->hwd_res, table_h_paddr,
+ table_m_paddr, table_l_paddr);
+ if (ret)
+ goto err;
+
+ ret = hwd_viif_l1_set_dpc(viif_dev->hwd_res, &l1_dpc->param_h, &l1_dpc->param_m,
+ &l1_dpc->param_l);
+
+err:
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+ return ret;
+}
+
+static int
+viif_l1_set_preset_white_balance(struct viif_device *viif_dev,
+ struct viif_l1_preset_white_balance_config *l1_preset_wb)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_preset_white_balance(viif_dev->hwd_res, l1_preset_wb->dstmaxval,
+ &l1_preset_wb->param_h, &l1_preset_wb->param_m,
+ &l1_preset_wb->param_l);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int
+viif_l1_set_raw_color_noise_reduction(struct viif_device *viif_dev,
+ struct viif_l1_raw_color_noise_reduction_config *raw_color)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_raw_color_noise_reduction(viif_dev->hwd_res, &raw_color->param_h,
+ &raw_color->param_m, &raw_color->param_l);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_hdrs(struct viif_device *viif_dev, struct viif_l1_hdrs_config *hdrs)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_hdrs(viif_dev->hwd_res, hdrs);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_black_level_correction(struct viif_device *viif_dev,
+ struct viif_l1_black_level_correction_config *blc)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_black_level_correction(viif_dev->hwd_res, blc);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+#define VISCONTI_VIIF_LSC_TABLE_BYTES 1536
+
+static int viif_l1_set_lsc(struct viif_device *viif_dev, struct viif_l1_lsc_config *l1_lsc)
+{
+ struct viif_l1_lsc_parabola_param lsc_para;
+ struct viif_l1_lsc_grid_param lsc_grid;
+ struct hwd_viif_l1_lsc hwd_params;
+ struct viif_l1_lsc lsc_params;
+ uintptr_t table_gr_paddr = 0;
+ uintptr_t table_gb_paddr = 0;
+ uintptr_t table_r_paddr = 0;
+ uintptr_t table_b_paddr = 0;
+ unsigned long irqflags;
+ int ret;
+
+ if (!l1_lsc->param_addr) {
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_lsc(viif_dev->hwd_res, NULL);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+ return ret;
+ }
+
+ if (l1_lsc->table_gr_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->lsc_table_gr,
+ u64_to_user_ptr(l1_lsc->table_gr_addr),
+ VISCONTI_VIIF_LSC_TABLE_BYTES))
+ return -EFAULT;
+ table_gr_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_gr;
+ }
+ if (l1_lsc->table_r_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->lsc_table_r,
+ u64_to_user_ptr(l1_lsc->table_r_addr),
+ VISCONTI_VIIF_LSC_TABLE_BYTES))
+ return -EFAULT;
+ table_r_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_r;
+ }
+ if (l1_lsc->table_b_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->lsc_table_b,
+ u64_to_user_ptr(l1_lsc->table_b_addr),
+ VISCONTI_VIIF_LSC_TABLE_BYTES))
+ return -EFAULT;
+ table_b_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_b;
+ }
+ if (l1_lsc->table_gb_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->lsc_table_gb,
+ u64_to_user_ptr(l1_lsc->table_gb_addr),
+ VISCONTI_VIIF_LSC_TABLE_BYTES))
+ return -EFAULT;
+ table_gb_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_gb;
+ }
+
+ if (copy_from_user(&lsc_params, u64_to_user_ptr(l1_lsc->param_addr),
+ sizeof(struct viif_l1_lsc)))
+ return -EFAULT;
+
+ hwd_params.lssc_parabola_param = NULL;
+ hwd_params.lssc_grid_param = NULL;
+
+ if (lsc_params.lssc_parabola_param_addr) {
+ if (copy_from_user(&lsc_para, u64_to_user_ptr(lsc_params.lssc_parabola_param_addr),
+ sizeof(struct viif_l1_lsc_parabola_param)))
+ return -EFAULT;
+ hwd_params.lssc_parabola_param = &lsc_para;
+ }
+
+ if (lsc_params.lssc_grid_param_addr) {
+ if (copy_from_user(&lsc_grid, u64_to_user_ptr(lsc_params.lssc_grid_param_addr),
+ sizeof(struct viif_l1_lsc_grid_param)))
+ return -EFAULT;
+ hwd_params.lssc_grid_param = &lsc_grid;
+ }
+
+ hwd_params.lssc_pwhb_r_gain_max = lsc_params.lssc_pwhb_r_gain_max;
+ hwd_params.lssc_pwhb_r_gain_min = lsc_params.lssc_pwhb_r_gain_min;
+ hwd_params.lssc_pwhb_gr_gain_max = lsc_params.lssc_pwhb_gr_gain_max;
+ hwd_params.lssc_pwhb_gr_gain_min = lsc_params.lssc_pwhb_gr_gain_min;
+ hwd_params.lssc_pwhb_gb_gain_max = lsc_params.lssc_pwhb_gb_gain_max;
+ hwd_params.lssc_pwhb_gb_gain_min = lsc_params.lssc_pwhb_gb_gain_min;
+ hwd_params.lssc_pwhb_b_gain_max = lsc_params.lssc_pwhb_b_gain_max;
+ hwd_params.lssc_pwhb_b_gain_min = lsc_params.lssc_pwhb_b_gain_min;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_lsc_table_transmission(viif_dev->hwd_res, table_gr_paddr,
+ table_r_paddr, table_b_paddr, table_gb_paddr);
+ if (ret)
+ goto err;
+
+ ret = hwd_viif_l1_set_lsc(viif_dev->hwd_res, &hwd_params);
+err:
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_main_process(struct viif_device *viif_dev,
+ struct viif_l1_main_process_config *mpro)
+{
+ struct viif_l1_color_matrix_correction color_matrix;
+ unsigned long irqflags;
+ int ret;
+
+ if (mpro->param_addr) {
+ if (copy_from_user(&color_matrix, u64_to_user_ptr(mpro->param_addr),
+ sizeof(struct viif_l1_color_matrix_correction)))
+ return -EFAULT;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_main_process(viif_dev->hwd_res, mpro->demosaic_mode,
+ mpro->damp_lsbsel,
+ mpro->param_addr ? &color_matrix : NULL,
+ mpro->dst_maxval);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_awb(struct viif_device *viif_dev, struct viif_l1_awb_config *l1_awb)
+{
+ struct viif_l1_awb param;
+ unsigned long irqflags;
+ int ret;
+
+ if (l1_awb->param_addr) {
+ if (copy_from_user(¶m, u64_to_user_ptr(l1_awb->param_addr),
+ sizeof(struct viif_l1_awb)))
+ return -EFAULT;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_awb(viif_dev->hwd_res, l1_awb->param_addr ? ¶m : NULL,
+ l1_awb->awhb_wbmrg, l1_awb->awhb_wbmgg, l1_awb->awhb_wbmbg);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_lock_awb_gain(struct viif_device *viif_dev, u32 *enable)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_lock_awb_gain(viif_dev->hwd_res, *enable);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_hdrc(struct viif_device *viif_dev, struct viif_l1_hdrc_config *hdrc)
+{
+ struct viif_l1_hdrc param;
+ unsigned long irqflags;
+ int ret;
+
+ if (hdrc->param_addr) {
+ if (copy_from_user(¶m, u64_to_user_ptr(hdrc->param_addr),
+ sizeof(struct viif_l1_hdrc)))
+ return -EFAULT;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_hdrc(viif_dev->hwd_res, hdrc->param_addr ? ¶m : NULL,
+ hdrc->hdrc_thr_sft_amt);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_hdrc_ltm(struct viif_device *viif_dev,
+ struct viif_l1_hdrc_ltm_config *l1_hdrc_ltm)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_hdrc_ltm(viif_dev->hwd_res, l1_hdrc_ltm);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_gamma(struct viif_device *viif_dev, struct viif_l1_gamma_config *l1_gamma)
+{
+ struct viif_l1_gamma param;
+ unsigned long irqflags;
+ int ret;
+
+ if (l1_gamma->param_addr) {
+ if (copy_from_user(¶m, u64_to_user_ptr(l1_gamma->param_addr),
+ sizeof(struct viif_l1_gamma)))
+ return -EFAULT;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_gamma(viif_dev->hwd_res, l1_gamma->param_addr ? ¶m : NULL);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int
+viif_l1_set_img_quality_adjustment(struct viif_device *viif_dev,
+ struct viif_l1_img_quality_adjustment_config *img_quality)
+{
+ struct hwd_viif_l1_img_quality_adjustment hwd_img_quality;
+ struct viif_l1_lum_noise_reduction lum_noise;
+ struct viif_l1_nonlinear_contrast nonlinear;
+ struct viif_l1_coring_suppression coring;
+ struct viif_l1_edge_enhancement edge_enh;
+ struct viif_l1_edge_suppression edge_sup;
+ struct viif_l1_uv_suppression uv;
+ struct viif_l1_color_level color;
+ unsigned long irqflags;
+ int ret;
+
+ hwd_img_quality.coef_cb = img_quality->coef_cb;
+ hwd_img_quality.coef_cr = img_quality->coef_cr;
+ hwd_img_quality.brightness = img_quality->brightness;
+ hwd_img_quality.linear_contrast = img_quality->linear_contrast;
+ hwd_img_quality.color_noise_reduction_enable = img_quality->color_noise_reduction_enable;
+
+ if (img_quality->nonlinear_contrast_addr) {
+ if (copy_from_user(&nonlinear,
+ u64_to_user_ptr(img_quality->nonlinear_contrast_addr),
+ sizeof(struct viif_l1_nonlinear_contrast)))
+ return -EFAULT;
+ hwd_img_quality.nonlinear_contrast = &nonlinear;
+ } else {
+ hwd_img_quality.nonlinear_contrast = NULL;
+ }
+ if (img_quality->lum_noise_reduction_addr) {
+ if (copy_from_user(&lum_noise,
+ u64_to_user_ptr(img_quality->lum_noise_reduction_addr),
+ sizeof(struct viif_l1_lum_noise_reduction)))
+ return -EFAULT;
+ hwd_img_quality.lum_noise_reduction = &lum_noise;
+ } else {
+ hwd_img_quality.lum_noise_reduction = NULL;
+ }
+ if (img_quality->edge_enhancement_addr) {
+ if (copy_from_user(&edge_enh, u64_to_user_ptr(img_quality->edge_enhancement_addr),
+ sizeof(struct viif_l1_edge_enhancement)))
+ return -EFAULT;
+ hwd_img_quality.edge_enhancement = &edge_enh;
+ } else {
+ hwd_img_quality.edge_enhancement = NULL;
+ }
+ if (img_quality->uv_suppression_addr) {
+ if (copy_from_user(&uv, u64_to_user_ptr(img_quality->uv_suppression_addr),
+ sizeof(struct viif_l1_uv_suppression)))
+ return -EFAULT;
+ hwd_img_quality.uv_suppression = &uv;
+ } else {
+ hwd_img_quality.uv_suppression = NULL;
+ }
+ if (img_quality->coring_suppression_addr) {
+ if (copy_from_user(&coring, u64_to_user_ptr(img_quality->coring_suppression_addr),
+ sizeof(struct viif_l1_coring_suppression)))
+ return -EFAULT;
+ hwd_img_quality.coring_suppression = &coring;
+ } else {
+ hwd_img_quality.coring_suppression = NULL;
+ }
+ if (img_quality->edge_suppression_addr) {
+ if (copy_from_user(&edge_sup, u64_to_user_ptr(img_quality->edge_suppression_addr),
+ sizeof(struct viif_l1_edge_suppression)))
+ return -EFAULT;
+ hwd_img_quality.edge_suppression = &edge_sup;
+ } else {
+ hwd_img_quality.edge_suppression = NULL;
+ }
+ if (img_quality->color_level_addr) {
+ if (copy_from_user(&color, u64_to_user_ptr(img_quality->color_level_addr),
+ sizeof(struct viif_l1_color_level)))
+ return -EFAULT;
+ hwd_img_quality.color_level = &color;
+ } else {
+ hwd_img_quality.color_level = NULL;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_img_quality_adjustment(viif_dev->hwd_res, &hwd_img_quality);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+static int viif_l1_set_avg_lum_generation(struct viif_device *viif_dev,
+ struct viif_l1_avg_lum_generation_config *l1_avg_lum)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l1_set_avg_lum_generation(viif_dev->hwd_res, l1_avg_lum);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ return ret;
+}
+
+#define VISCONTI_VIIF_DPC_TABLE_SIZE_MIN 1024
+#define VISCONTI_VIIF_DPC_TABLE_SIZE_MAX 8192
+static int viif_l2_set_undist(struct viif_device *viif_dev, struct viif_l2_undist_config *undist)
+{
+ uintptr_t table_write_g_paddr = 0;
+ uintptr_t table_read_b_paddr = 0;
+ uintptr_t table_read_g_paddr = 0;
+ uintptr_t table_read_r_paddr = 0;
+ unsigned long irqflags;
+ int ret;
+
+ if ((undist->size && undist->size < VISCONTI_VIIF_DPC_TABLE_SIZE_MIN) ||
+ undist->size > VISCONTI_VIIF_DPC_TABLE_SIZE_MAX)
+ return -EINVAL;
+
+ if (undist->write_g_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->undist_write_g,
+ u64_to_user_ptr(undist->write_g_addr), undist->size))
+ return -EFAULT;
+ table_write_g_paddr = (uintptr_t)viif_dev->table_paddr->undist_write_g;
+ }
+ if (undist->read_b_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->undist_read_b,
+ u64_to_user_ptr(undist->read_b_addr), undist->size))
+ return -EFAULT;
+ table_read_b_paddr = (uintptr_t)viif_dev->table_paddr->undist_read_b;
+ }
+ if (undist->read_g_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->undist_read_g,
+ u64_to_user_ptr(undist->read_g_addr), undist->size))
+ return -EFAULT;
+ table_read_g_paddr = (uintptr_t)viif_dev->table_paddr->undist_read_g;
+ }
+ if (undist->read_r_addr) {
+ if (copy_from_user(viif_dev->table_vaddr->undist_read_r,
+ u64_to_user_ptr(undist->read_r_addr), undist->size))
+ return -EFAULT;
+ table_read_r_paddr = (uintptr_t)viif_dev->table_paddr->undist_read_r;
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l2_set_undist_table_transmission(viif_dev->hwd_res, table_write_g_paddr,
+ table_read_b_paddr, table_read_g_paddr,
+ table_read_r_paddr, undist->size);
+ if (ret) {
+ dev_err(viif_dev->dev, "l2_set_undist_table_transmission error. %d\n", ret);
+ goto err;
+ }
+
+ ret = hwd_viif_l2_set_undist(viif_dev->hwd_res, &undist->param);
+
+err:
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+ return ret;
+}
+
+static int viif_l2_set_roi(struct viif_device *viif_dev, struct viif_l2_roi_config *roi)
+{
+ unsigned long irqflags;
+ int ret;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l2_set_roi(viif_dev->hwd_res, roi);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+ return ret;
+}
+
+static int viif_l2_set_roi_wrap(struct viif_device *viif_dev, struct viif_l2_roi_config *roi)
+{
+ int ret;
+
+ ret = viif_l2_set_roi(viif_dev, roi);
+ if (!ret)
+ visconti_viif_isp_set_compose_rect(viif_dev, roi);
+
+ return ret;
+}
+
+#define VISCONTI_VIIF_GANMMA_TABLE_SIZE 512
+static int viif_l2_set_gamma(struct viif_device *viif_dev, struct viif_l2_gamma_config *l2_gamma)
+{
+ struct hwd_viif_l2_gamma_table hwd_table = { 0 };
+ int pathid = l2_gamma->pathid;
+ unsigned long irqflags;
+ int postid;
+ int ret;
+ u32 i;
+
+ if (pathid == CAPTURE_PATH_MAIN_POST0)
+ postid = VIIF_L2ISP_POST_0;
+ else if (pathid == CAPTURE_PATH_MAIN_POST1)
+ postid = VIIF_L2ISP_POST_1;
+ else
+ return -EINVAL;
+
+ for (i = 0; i < 6; i++) {
+ if (l2_gamma->table_addr[i]) {
+ if (copy_from_user(viif_dev->table_vaddr->l2_gamma_table[pathid][i],
+ u64_to_user_ptr(l2_gamma->table_addr[i]),
+ VISCONTI_VIIF_GANMMA_TABLE_SIZE))
+ return -EFAULT;
+ hwd_table.table[i] =
+ (uintptr_t)viif_dev->table_paddr->l2_gamma_table[pathid][i];
+ }
+ }
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ ret = hwd_viif_l2_set_gamma_table_transmission(viif_dev->hwd_res, postid, &hwd_table);
+ if (ret)
+ goto err;
+
+ ret = hwd_viif_l2_set_gamma(viif_dev->hwd_res, postid, l2_gamma->enable, l2_gamma->vsplit,
+ l2_gamma->mode);
+err:
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+ return ret;
+}
+
+static int
+viif_csi2rx_get_calibration_status(struct viif_device *viif_dev,
+ struct viif_csi2rx_dphy_calibration_status *calibration_status)
+{
+ int ret;
+
+ if (!vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
+ return -EIO;
+
+ ret = hwd_viif_csi2rx_get_calibration_status(viif_dev->hwd_res, calibration_status);
+
+ return ret;
+}
+
+static int viif_csi2rx_get_err_status(struct viif_device *viif_dev,
+ struct viif_csi2rx_err_status *csi_err)
+{
+ int ret;
+
+ if (!vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
+ return -EIO;
+
+ ret = hwd_viif_csi2rx_get_err_status(viif_dev->hwd_res, &csi_err->err_phy_fatal,
+ &csi_err->err_pkt_fatal, &csi_err->err_frame_fatal,
+ &csi_err->err_phy, &csi_err->err_pkt,
+ &csi_err->err_line);
+
+ return ret;
+}
+
+static int viif_isp_get_last_capture_status(struct viif_device *viif_dev,
+ struct viif_isp_capture_status *status)
+{
+ struct hwd_viif_l1_info l1_info;
+ unsigned long irqflags;
+ int i, j;
+
+ spin_lock_irqsave(&viif_dev->lock, irqflags);
+ hwd_viif_isp_guard_start(viif_dev->hwd_res);
+ hwd_viif_isp_get_info(viif_dev->hwd_res, &l1_info, NULL);
+ hwd_viif_isp_guard_end(viif_dev->hwd_res);
+ spin_unlock_irqrestore(&viif_dev->lock, irqflags);
+
+ status->l1_info.avg_lum_weight = l1_info.avg_lum_weight;
+ for (i = 0; i < 8; i++) {
+ for (j = 0; j < 8; j++)
+ status->l1_info.avg_lum_block[i][j] = l1_info.avg_lum_block[i][j];
+ }
+ for (i = 0; i < 4; i++)
+ status->l1_info.avg_lum_four_line_lum[i] = l1_info.avg_lum_four_line_lum[i];
+
+ status->l1_info.avg_satur_pixnum = l1_info.avg_satur_pixnum;
+ status->l1_info.avg_black_pixnum = l1_info.avg_black_pixnum;
+ status->l1_info.awb_ave_u = l1_info.awb_ave_u;
+ status->l1_info.awb_ave_v = l1_info.awb_ave_v;
+ status->l1_info.awb_accumulated_pixel = l1_info.awb_accumulated_pixel;
+ status->l1_info.awb_gain_r = l1_info.awb_gain_r;
+ status->l1_info.awb_gain_g = l1_info.awb_gain_g;
+ status->l1_info.awb_gain_b = l1_info.awb_gain_b;
+ status->l1_info.awb_status_u = l1_info.awb_status_u;
+ status->l1_info.awb_status_v = l1_info.awb_status_v;
+
+ return 0;
+}
+
+static int viif_isp_get_reported_errors(struct viif_device *viif_dev,
+ struct viif_reported_errors *status)
+{
+ status->main = viif_dev->reported_err_main;
+ status->sub = viif_dev->reported_err_sub;
+ status->csi2rx = viif_dev->reported_err_csi2rx;
+ viif_dev->reported_err_main = 0;
+ viif_dev->reported_err_sub = 0;
+ viif_dev->reported_err_csi2rx = 0;
+
+ return 0;
+}
+
+/* ===== v4l2 subdevice control handlers ===== */
+#define COMPOUND_TYPE_SAMPLE01 0x0280
+
+static int visconti_viif_isp_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct viif_device *viif_dev = ctrl->priv;
+
+ pr_info("isp_set_ctrl: %s", ctrl->name);
+ if (pm_runtime_status_suspended(viif_dev->dev)) {
+ pr_info("warning: visconti viif HW is not powered");
+ return 0;
+ }
+
+ switch (ctrl->id) {
+ case V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE:
+ return viif_main_set_rawpack_mode(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE:
+ return viif_l1_set_input_mode(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF:
+ return viif_l1_set_rgb_to_y_coef(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE:
+ return viif_l1_set_ag_mode(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG:
+ return viif_l1_set_ag(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE:
+ return viif_l1_set_hdre(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION:
+ return viif_l1_set_img_extraction(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC:
+ return viif_l1_set_dpc(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE:
+ return viif_l1_set_preset_white_balance(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION:
+ return viif_l1_set_raw_color_noise_reduction(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS:
+ return viif_l1_set_hdrs(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION:
+ return viif_l1_set_black_level_correction(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC:
+ return viif_l1_set_lsc(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS:
+ return viif_l1_set_main_process(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB:
+ return viif_l1_set_awb(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN:
+ return viif_l1_lock_awb_gain(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC:
+ return viif_l1_set_hdrc(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM:
+ return viif_l1_set_hdrc_ltm(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA:
+ return viif_l1_set_gamma(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT:
+ return viif_l1_set_img_quality_adjustment(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION:
+ return viif_l1_set_avg_lum_generation(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST:
+ return viif_l2_set_undist(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI:
+ return viif_l2_set_roi_wrap(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA:
+ return viif_l2_set_gamma(viif_dev, ctrl->p_new.p);
+ default:
+ pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
+ break;
+ }
+ return 0;
+}
+
+static int visconti_viif_isp_get_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct viif_device *viif_dev = ctrl->priv;
+
+ pr_info("isp_get_ctrl: %s", ctrl->name);
+ if (pm_runtime_status_suspended(viif_dev->dev)) {
+ pr_info("warning: visconti viif HW is not powered");
+ return 0;
+ }
+
+ switch (ctrl->id) {
+ case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
+ return viif_csi2rx_get_calibration_status(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
+ return viif_csi2rx_get_err_status(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
+ return viif_isp_get_last_capture_status(viif_dev, ctrl->p_new.p);
+ case V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
+ return viif_isp_get_reported_errors(viif_dev, ctrl->p_new.p);
+ default:
+ pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
+ break;
+ }
+ return 0;
+}
+
+/* ===== register v4l2 subdevice controls ===== */
+static bool visconti_viif_isp_custom_ctrl_equal(const struct v4l2_ctrl *ctrl,
+ union v4l2_ctrl_ptr ptr1, union v4l2_ctrl_ptr ptr2)
+{
+ return !memcmp(ptr1.p_const, ptr2.p_const, ctrl->elem_size);
+}
+
+static void visconti_viif_isp_custom_ctrl_init(const struct v4l2_ctrl *ctrl, u32 idx,
+ union v4l2_ctrl_ptr ptr)
+{
+ if (ctrl->p_def.p_const)
+ memcpy(ptr.p, ctrl->p_def.p_const, ctrl->elem_size);
+ else
+ memset(ptr.p, 0, ctrl->elem_size);
+}
+
+static void visconti_viif_isp_custom_ctrl_log(const struct v4l2_ctrl *ctrl)
+{
+}
+
+static int visconti_viif_isp_custom_ctrl_validate(const struct v4l2_ctrl *ctrl,
+ union v4l2_ctrl_ptr ptr)
+{
+ pr_info("std_validate: %s", ctrl->name);
+ return 0;
+}
+
+static const struct v4l2_ctrl_type_ops custom_type_ops = {
+ .equal = visconti_viif_isp_custom_ctrl_equal,
+ .init = visconti_viif_isp_custom_ctrl_init,
+ .log = visconti_viif_isp_custom_ctrl_log,
+ .validate = visconti_viif_isp_custom_ctrl_validate,
+};
+
+static const struct v4l2_ctrl_ops visconti_viif_isp_ctrl_ops = {
+ .g_volatile_ctrl = visconti_viif_isp_get_ctrl,
+ .s_ctrl = visconti_viif_isp_set_ctrl,
+};
+
+/* ----- control handler ----- */
+#define CTRL_CONFIG_DEFAULT_ENTRY \
+ .ops = &visconti_viif_isp_ctrl_ops, .type_ops = &custom_type_ops, \
+ .type = COMPOUND_TYPE_SAMPLE01, .flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE
+
+#define CTRL_CONFIG_RDONLY_ENTRY \
+ .ops = &visconti_viif_isp_ctrl_ops, .type_ops = &custom_type_ops, \
+ .type = COMPOUND_TYPE_SAMPLE01, .flags = V4L2_CTRL_FLAG_VOLATILE
+
+static const struct v4l2_ctrl_config visconti_viif_isp_ctrl_config[] = {
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE,
+ .name = "rawpack_mode",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(u32),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE,
+ .name = "l1_input_mode",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_input_mode_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF,
+ .name = "l1_rgb_to_y_coef",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_rgb_to_y_coef_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE,
+ .name = "l1_ag_mode",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_ag_mode_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG,
+ .name = "l1_ag",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_ag_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE,
+ .name = "l1_hdre",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_hdre_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION,
+ .name = "l1_img_extraction",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_img_extraction_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC,
+ .name = "l1_dpc",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_dpc_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE,
+ .name = "l1_preset_white_balance",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_preset_white_balance_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION,
+ .name = "l1_raw_color_noise_reduction",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_raw_color_noise_reduction_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS,
+ .name = "l1_set_hdrs",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_hdrs_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION,
+ .name = "l1_black_level_correction",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_black_level_correction_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC,
+ .name = "l1_lsc",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_lsc_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS,
+ .name = "l1_main_process",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_main_process_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB,
+ .name = "l1_awb",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_awb_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN,
+ .name = "l1_lock_awb_gain",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(u32),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC,
+ .name = "l1_hdrc",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_hdrc_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM,
+ .name = "l1_hdrc_ltm",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_hdrc_ltm_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA,
+ .name = "l1_gamma",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_gamma_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT,
+ .name = "l1_img_quality_adjustment",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_img_quality_adjustment_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION,
+ .name = "l1_avg_lum",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l1_avg_lum_generation_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST,
+ .name = "l2_undist",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l2_undist_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI,
+ .name = "l2_roi",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l2_roi_config),
+ },
+ {
+ CTRL_CONFIG_DEFAULT_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA,
+ .name = "l2_gamma",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_l2_gamma_config),
+ },
+ {
+ CTRL_CONFIG_RDONLY_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS,
+ .name = "csi2rx_calibration_status",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_csi2rx_dphy_calibration_status),
+ },
+ {
+ CTRL_CONFIG_RDONLY_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS,
+ .name = "csi2rx_err_status",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_csi2rx_err_status),
+ },
+ {
+ CTRL_CONFIG_RDONLY_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS,
+ .name = "last_capture_status",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_isp_capture_status),
+ },
+ {
+ CTRL_CONFIG_RDONLY_ENTRY,
+ .id = V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS,
+ .name = "reported errors",
+ .p_def = { .p_const = NULL },
+ .elem_size = sizeof(struct viif_reported_errors),
+ },
+};
+
+int visconti_viif_isp_init_controls(struct viif_device *viif_dev)
+{
+ struct v4l2_ctrl_handler *ctrl_handler = &viif_dev->isp_subdev.ctrl_handler;
+ int ret;
+ int i;
+
+ ret = v4l2_ctrl_handler_init(ctrl_handler, 10);
+ if (ret) {
+ dev_err(viif_dev->dev, "failed on v4l2_ctrl_handler_init");
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(visconti_viif_isp_ctrl_config); i++) {
+ struct v4l2_ctrl *ctrl;
+
+ ctrl = v4l2_ctrl_new_custom(ctrl_handler, &visconti_viif_isp_ctrl_config[i],
+ viif_dev);
+ if (!ctrl) {
+ dev_err(viif_dev->dev, "failed to add ctrl crop: %d", ctrl_handler->error);
+ return ctrl_handler->error;
+ }
+ }
+
+ viif_dev->isp_subdev.sd.ctrl_handler = &viif_dev->isp_subdev.ctrl_handler;
+ return 0;
+}
diff --git a/drivers/media/platform/visconti/viif_isp.c b/drivers/media/platform/visconti/viif_isp.c
index 9314e6e8661..9aeb8bcab9b 100644
--- a/drivers/media/platform/visconti/viif_isp.c
+++ b/drivers/media/platform/visconti/viif_isp.c
@@ -818,6 +818,8 @@ int visconti_viif_isp_register(struct viif_device *viif_dev)
mutex_init(&viif_dev->isp_subdev.ops_lock);
+ visconti_viif_isp_init_controls(viif_dev);
+
ret = media_entity_pads_init(&sd->entity, 4, pads);
if (ret) {
dev_err(viif_dev->dev, "Failed on media_entity_pads_init\n");
--
2.25.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-11 2:24 ` [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler Yuji Ishikawa
@ 2023-01-17 11:19 ` Hans Verkuil
2023-01-26 0:38 ` yuji2.ishikawa
0 siblings, 1 reply; 42+ messages in thread
From: Hans Verkuil @ 2023-01-17 11:19 UTC (permalink / raw)
To: Yuji Ishikawa, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
Some review comments below:
On 11/01/2023 03:24, Yuji Ishikawa wrote:
> Add support to Image Signal Processors of Visconti's Video Input Interface.
> This patch adds vendor specific compound controls
> to configure the image signal processor.
>
> Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> ---
> Changelog v2:
> - Resend v1 because a patch exceeds size limit.
>
> Changelog v3:
> - Adapted to media control framework
> - Introduced ISP subdevice, capture device
> - Remove private IOCTLs and add vendor specific V4L2 controls
> - Change function name avoiding camelcase and uppercase letters
>
> Changelog v4:
> - Split patches because the v3 patch exceeds size limit
> - Stop using ID number to identify driver instance:
> - Use dynamically allocated structure to hold HW specific context,
> instead of static one.
> - Call HW layer functions with the context structure instead of ID number
>
> Changelog v5:
> - no change
> ---
> drivers/media/platform/visconti/Makefile | 4 +-
> .../media/platform/visconti/hwd_viif_l1isp.c | 2674 +++++++++++++++++
> .../media/platform/visconti/viif_controls.c | 1153 +++++++
> drivers/media/platform/visconti/viif_isp.c | 2 +
> 4 files changed, 3831 insertions(+), 2 deletions(-)
> create mode 100644 drivers/media/platform/visconti/hwd_viif_l1isp.c
> create mode 100644 drivers/media/platform/visconti/viif_controls.c
>
> diff --git a/drivers/media/platform/visconti/Makefile b/drivers/media/platform/visconti/Makefile
> index d7a23c1f4e8..13cf70ce309 100644
> --- a/drivers/media/platform/visconti/Makefile
> +++ b/drivers/media/platform/visconti/Makefile
> @@ -3,7 +3,7 @@
> # Makefile for the Visconti video input device driver
> #
>
> -visconti-viif-objs = viif.o viif_capture.o viif_isp.o
> -visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> +visconti-viif-objs = viif.o viif_capture.o viif_controls.o viif_isp.o
> +visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o hwd_viif_l1isp.o
>
> obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> diff --git a/drivers/media/platform/visconti/hwd_viif_l1isp.c b/drivers/media/platform/visconti/hwd_viif_l1isp.c
> new file mode 100644
> index 00000000000..882eea92205
> --- /dev/null
> +++ b/drivers/media/platform/visconti/hwd_viif_l1isp.c
> @@ -0,0 +1,2674 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/io.h>
> +#include "hwd_viif.h"
> +#include "hwd_viif_internal.h"
> +
> +/**
> + * hwd_viif_l1_set_input_mode() - Configure L1ISP input mode.
> + *
> + * @mode: L1ISP preprocessing mode @ref hwd_viif_l1_input_mode
> + * @depth: input color depth (even only)
> + * - [8..24] in case of mode = #HWD_VIIF_L1_INPUT_HDR or #HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT
> + * - [8..14] in case of mode = #HWD_VIIF_L1_INPUT_PWL or #HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT
> + * - [8..12] in case of mode = #HWD_VIIF_L1_INPUT_SDR
> + * @raw_color_filter: RAW color filter array @ref hwd_viif_l1_raw_color_filter_mode
> + * @interpolation_order: interpolation order for input image
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "mode" is out of range
> + * - "depth" is out of range
> + * - "raw_color_filter" is out of range
> + * - "interpolation_order" is NULL in case of "mode" == #HWD_VIIF_L1_INPUT_SDR
> + * - "interpolation_order" is not NULL in case of "mode" != #HWD_VIIF_L1_INPUT_SDR
> + *
> + * Note that if 'mode' is not HWD_VIIF_L1_INPUT_SDR, NULL shall be set to 'interpolation_order'.
> + */
> +s32 hwd_viif_l1_set_input_mode(struct hwd_viif_res *res, u32 mode, u32 depth, u32 raw_color_filter)
> +{
> + u32 depth_max;
> +
> + if (mode >= HWD_VIIF_L1_INPUT_MODE_NUM || mode == HWD_VIIF_L1_INPUT_SDR)
> + return -EINVAL;
> +
> + if (mode == HWD_VIIF_L1_INPUT_PWL || mode == HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT)
> + depth_max = HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX;
> + else
> + depth_max = HWD_VIIF_L1_INPUT_DEPTH_MAX;
> +
> + if (depth < HWD_VIIF_L1_INPUT_DEPTH_MIN || depth > depth_max || ((depth % 2U) != 0U) ||
> + raw_color_filter >= HWD_VIIF_L1_RAW_MODE_NUM) {
> + return -EINVAL;
> + }
> +
> + writel(mode, &res->capture_reg->l1isp.L1_SYSM_INPUT_MODE);
> + writel(depth, &res->capture_reg->l1isp.L1_IBUF_DEPTH);
> + writel(raw_color_filter, &res->capture_reg->l1isp.L1_SYSM_START_COLOR);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_rgb_to_y_coef() - Configure L1ISP RGB coefficients to calculate Y.
> + *
> + * @coef_r: R coefficient to calculate Y [256..65024] accuracy: 1/65536
> + * @coef_g: G coefficient to calculate Y [256..65024] accuracy: 1/65536
> + * @coef_b: B coefficient to calculate Y [256..65024] accuracy: 1/65536
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "coef_r" is out of range
> + * - "coef_g" is out of range
> + * - "coef_b" is out of range
> + *
> + * Note that it is possible that coef_r/g/b has rounding error when the value is set to HW register
> + */
> +s32 hwd_viif_l1_set_rgb_to_y_coef(struct hwd_viif_res *res, u16 coef_r, u16 coef_g, u16 coef_b)
> +{
> + if (coef_r < HWD_VIIF_L1_COEF_MIN || coef_r > HWD_VIIF_L1_COEF_MAX ||
> + coef_g < HWD_VIIF_L1_COEF_MIN || coef_g > HWD_VIIF_L1_COEF_MAX ||
> + coef_b < HWD_VIIF_L1_COEF_MIN || coef_b > HWD_VIIF_L1_COEF_MAX) {
> + return -EINVAL;
> + }
> +
> + writel((u32)coef_r, &res->capture_reg->l1isp.L1_SYSM_YCOEF_R);
> + writel((u32)coef_g, &res->capture_reg->l1isp.L1_SYSM_YCOEF_G);
> + writel((u32)coef_b, &res->capture_reg->l1isp.L1_SYSM_YCOEF_B);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_ag_mode() - Configure L1ISP AG mode.
> + *
> + * @param: pointer to struct hwd_viif_l1_ag_mode
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "param" is NULL
> + * - each member of "param" is invalid
> + */
> +s32 hwd_viif_l1_set_ag_mode(struct hwd_viif_res *res, const struct viif_l1_ag_mode_config *param)
> +{
> + u32 val;
> +
> + if (!param || param->sysm_ag_psel_hobc_high >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_hobc_middle_led >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_hobc_low >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_abpc_high >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_abpc_middle_led >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_abpc_low >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_rcnr_high >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_rcnr_middle_led >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_psel_rcnr_low >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_ssel_lssc >= HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
> + param->sysm_ag_psel_lssc >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_ssel_mpro >= HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
> + param->sysm_ag_psel_mpro >= HWD_VIIF_L1_AG_ID_NUM ||
> + param->sysm_ag_ssel_vpro >= HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
> + param->sysm_ag_psel_vpro >= HWD_VIIF_L1_AG_ID_NUM ||
> + (param->sysm_ag_cont_hobc_en_high != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_hobc_en_high != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_hobc_en_middle_led != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_hobc_en_middle_led != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_hobc_en_low != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_hobc_en_low != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_rcnr_en_high != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_rcnr_en_high != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_rcnr_en_middle_led != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_rcnr_en_middle_led != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_rcnr_en_low != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_rcnr_en_low != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_lssc_en != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_lssc_en != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_mpro_en != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_mpro_en != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_vpro_en != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_vpro_en != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_abpc_en_middle_led != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_abpc_en_middle_led != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_abpc_en_high != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_abpc_en_high != HWD_VIIF_DISABLE) ||
> + (param->sysm_ag_cont_abpc_en_low != HWD_VIIF_ENABLE &&
> + param->sysm_ag_cont_abpc_en_low != HWD_VIIF_DISABLE)) {
> + return -EINVAL;
> + }
You should split off the validation code into a separate function
(e.g. hwd_viif_l1_try_ag_mode) and add support for the try_ctrl op
where you call these 'try' functions.
The advantage is that applications can use VIDIOC_TRY_EXT_CTRLS to
check if the controls are valid, it's really where the checks should
be done.
> +
> + /* SYSM_AG_PARAM */
> + val = ((u32)param->sysm_ag_grad[0] << 16U) | ((u32)param->sysm_ag_ofst[0]);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_A);
> + val = ((u32)param->sysm_ag_grad[1] << 16U) | ((u32)param->sysm_ag_ofst[1]);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_B);
> + val = ((u32)param->sysm_ag_grad[2] << 16U) | ((u32)param->sysm_ag_ofst[2]);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_C);
> + val = ((u32)param->sysm_ag_grad[3] << 16U) | ((u32)param->sysm_ag_ofst[3]);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_D);
> +
> + /* SYSM_AG_SEL */
> + val = ((u32)param->sysm_ag_psel_hobc_high << 6U) |
> + ((u32)param->sysm_ag_psel_hobc_middle_led << 4U) |
> + ((u32)param->sysm_ag_psel_hobc_low << 2U);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_HOBC);
> +
> + val = ((u32)param->sysm_ag_psel_abpc_high << 6U) |
> + ((u32)param->sysm_ag_psel_abpc_middle_led << 4U) |
> + ((u32)param->sysm_ag_psel_abpc_low << 2U);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_ABPC);
> +
> + val = ((u32)param->sysm_ag_psel_rcnr_high << 6U) |
> + ((u32)param->sysm_ag_psel_rcnr_middle_led << 4U) |
> + ((u32)param->sysm_ag_psel_rcnr_low << 2U);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_RCNR);
> +
> + val = ((u32)param->sysm_ag_ssel_lssc << 2U) | ((u32)param->sysm_ag_psel_lssc);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_LSSC);
> +
> + val = ((u32)param->sysm_ag_ssel_mpro << 2U) | ((u32)param->sysm_ag_psel_mpro);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_MPRO);
> +
> + val = ((u32)param->sysm_ag_ssel_vpro << 2U) | ((u32)param->sysm_ag_psel_vpro);
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_VPRO);
> +
> + /* SYSM_AG_CONT */
> + val = (param->sysm_ag_cont_hobc_en_middle_led << 24U) |
> + ((u32)(param->sysm_ag_cont_hobc_test_middle_led) << 16U) |
> + (param->sysm_ag_cont_hobc_en_high << 8U) | (u32)param->sysm_ag_cont_hobc_test_high;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_HOBC01_EN);
> + val = (param->sysm_ag_cont_hobc_en_low << 8U) | (u32)param->sysm_ag_cont_hobc_test_low;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_HOBC2_EN);
> +
> + val = (param->sysm_ag_cont_abpc_en_middle_led << 24U) |
> + ((u32)(param->sysm_ag_cont_abpc_test_middle_led) << 16U) |
> + (param->sysm_ag_cont_abpc_en_high << 8U) | (u32)param->sysm_ag_cont_abpc_test_high;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_ABPC01_EN);
> + val = (param->sysm_ag_cont_abpc_en_low << 8U) | (u32)param->sysm_ag_cont_abpc_test_low;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_ABPC2_EN);
> +
> + val = (param->sysm_ag_cont_rcnr_en_middle_led << 24U) |
> + ((u32)(param->sysm_ag_cont_rcnr_test_middle_led) << 16U) |
> + (param->sysm_ag_cont_rcnr_en_high << 8U) | (u32)param->sysm_ag_cont_rcnr_test_high;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_RCNR01_EN);
> + val = (param->sysm_ag_cont_rcnr_en_low << 8U) | (u32)param->sysm_ag_cont_rcnr_test_low;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_RCNR2_EN);
> +
> + val = (param->sysm_ag_cont_lssc_en << 8U) | (u32)param->sysm_ag_cont_lssc_test;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_LSSC_EN);
> +
> + val = (param->sysm_ag_cont_mpro_en << 8U) | (u32)param->sysm_ag_cont_mpro_test;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_MPRO_EN);
> +
> + val = (param->sysm_ag_cont_vpro_en << 8U) | (u32)param->sysm_ag_cont_vpro_test;
> + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_VPRO_EN);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_ag() - Configure L1ISP analog gain.
> + *
> + * @gain_h: analog gain value for high sensitivity image [0..65535]
> + * @gain_m: analog gain value for middle sensitivity or led image [0..65535]
> + * @gain_l: analog gain value for low sensitivity image [0..65535]
> + * Return: 0 operation completed successfully
> + */
> +s32 hwd_viif_l1_set_ag(struct hwd_viif_res *res, u16 gain_h, u16 gain_m, u16 gain_l)
> +{
> + writel((u32)gain_h, &res->capture_reg->l1isp.L1_SYSM_AG_H);
> + writel((u32)gain_m, &res->capture_reg->l1isp.L1_SYSM_AG_M);
> + writel((u32)gain_l, &res->capture_reg->l1isp.L1_SYSM_AG_L);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_hdre() - Configure L1ISP HDR extension parameters.
> + *
> + * @param: pointer to struct hwd_viif_l1_hdre
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "param" is NULL
> + * - each member of "param" is invalid
> + */
> +s32 hwd_viif_l1_set_hdre(struct hwd_viif_res *res, const struct viif_l1_hdre_config *param)
> +{
> + u32 idx;
> +
> + if (!param)
> + return -EINVAL;
> +
> + for (idx = 0; idx < 16U; idx++) {
> + if (param->hdre_src_point[idx] > HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL)
> + return -EINVAL;
> + }
> +
> + for (idx = 0; idx < 17U; idx++) {
> + if (param->hdre_dst_base[idx] > HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL ||
> + param->hdre_ratio[idx] >= HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param->hdre_dst_max_val > HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL)
> + return -EINVAL;
> +
> + writel(param->hdre_src_point[0], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT00);
> + writel(param->hdre_src_point[1], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT01);
> + writel(param->hdre_src_point[2], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT02);
> + writel(param->hdre_src_point[3], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT03);
> + writel(param->hdre_src_point[4], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT04);
> + writel(param->hdre_src_point[5], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT05);
> + writel(param->hdre_src_point[6], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT06);
> + writel(param->hdre_src_point[7], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT07);
> + writel(param->hdre_src_point[8], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT08);
> + writel(param->hdre_src_point[9], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT09);
> + writel(param->hdre_src_point[10], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT10);
> + writel(param->hdre_src_point[11], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT11);
> + writel(param->hdre_src_point[12], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT12);
> + writel(param->hdre_src_point[13], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT13);
> + writel(param->hdre_src_point[14], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT14);
> + writel(param->hdre_src_point[15], &res->capture_reg->l1isp.L1_HDRE_SRCPOINT15);
> +
> + writel(0, &res->capture_reg->l1isp.L1_HDRE_SRCBASE00);
> + writel(param->hdre_src_point[0], &res->capture_reg->l1isp.L1_HDRE_SRCBASE01);
> + writel(param->hdre_src_point[1], &res->capture_reg->l1isp.L1_HDRE_SRCBASE02);
> + writel(param->hdre_src_point[2], &res->capture_reg->l1isp.L1_HDRE_SRCBASE03);
> + writel(param->hdre_src_point[3], &res->capture_reg->l1isp.L1_HDRE_SRCBASE04);
> + writel(param->hdre_src_point[4], &res->capture_reg->l1isp.L1_HDRE_SRCBASE05);
> + writel(param->hdre_src_point[5], &res->capture_reg->l1isp.L1_HDRE_SRCBASE06);
> + writel(param->hdre_src_point[6], &res->capture_reg->l1isp.L1_HDRE_SRCBASE07);
> + writel(param->hdre_src_point[7], &res->capture_reg->l1isp.L1_HDRE_SRCBASE08);
> + writel(param->hdre_src_point[8], &res->capture_reg->l1isp.L1_HDRE_SRCBASE09);
> + writel(param->hdre_src_point[9], &res->capture_reg->l1isp.L1_HDRE_SRCBASE10);
> + writel(param->hdre_src_point[10], &res->capture_reg->l1isp.L1_HDRE_SRCBASE11);
> + writel(param->hdre_src_point[11], &res->capture_reg->l1isp.L1_HDRE_SRCBASE12);
> + writel(param->hdre_src_point[12], &res->capture_reg->l1isp.L1_HDRE_SRCBASE13);
> + writel(param->hdre_src_point[13], &res->capture_reg->l1isp.L1_HDRE_SRCBASE14);
> + writel(param->hdre_src_point[14], &res->capture_reg->l1isp.L1_HDRE_SRCBASE15);
> + writel(param->hdre_src_point[15], &res->capture_reg->l1isp.L1_HDRE_SRCBASE16);
> +
> + writel(param->hdre_dst_base[0], &res->capture_reg->l1isp.L1_HDRE_DSTBASE00);
> + writel(param->hdre_dst_base[1], &res->capture_reg->l1isp.L1_HDRE_DSTBASE01);
> + writel(param->hdre_dst_base[2], &res->capture_reg->l1isp.L1_HDRE_DSTBASE02);
> + writel(param->hdre_dst_base[3], &res->capture_reg->l1isp.L1_HDRE_DSTBASE03);
> + writel(param->hdre_dst_base[4], &res->capture_reg->l1isp.L1_HDRE_DSTBASE04);
> + writel(param->hdre_dst_base[5], &res->capture_reg->l1isp.L1_HDRE_DSTBASE05);
> + writel(param->hdre_dst_base[6], &res->capture_reg->l1isp.L1_HDRE_DSTBASE06);
> + writel(param->hdre_dst_base[7], &res->capture_reg->l1isp.L1_HDRE_DSTBASE07);
> + writel(param->hdre_dst_base[8], &res->capture_reg->l1isp.L1_HDRE_DSTBASE08);
> + writel(param->hdre_dst_base[9], &res->capture_reg->l1isp.L1_HDRE_DSTBASE09);
> + writel(param->hdre_dst_base[10], &res->capture_reg->l1isp.L1_HDRE_DSTBASE10);
> + writel(param->hdre_dst_base[11], &res->capture_reg->l1isp.L1_HDRE_DSTBASE11);
> + writel(param->hdre_dst_base[12], &res->capture_reg->l1isp.L1_HDRE_DSTBASE12);
> + writel(param->hdre_dst_base[13], &res->capture_reg->l1isp.L1_HDRE_DSTBASE13);
> + writel(param->hdre_dst_base[14], &res->capture_reg->l1isp.L1_HDRE_DSTBASE14);
> + writel(param->hdre_dst_base[15], &res->capture_reg->l1isp.L1_HDRE_DSTBASE15);
> + writel(param->hdre_dst_base[16], &res->capture_reg->l1isp.L1_HDRE_DSTBASE16);
> +
> + writel(param->hdre_ratio[0], &res->capture_reg->l1isp.L1_HDRE_RATIO00);
> + writel(param->hdre_ratio[1], &res->capture_reg->l1isp.L1_HDRE_RATIO01);
> + writel(param->hdre_ratio[2], &res->capture_reg->l1isp.L1_HDRE_RATIO02);
> + writel(param->hdre_ratio[3], &res->capture_reg->l1isp.L1_HDRE_RATIO03);
> + writel(param->hdre_ratio[4], &res->capture_reg->l1isp.L1_HDRE_RATIO04);
> + writel(param->hdre_ratio[5], &res->capture_reg->l1isp.L1_HDRE_RATIO05);
> + writel(param->hdre_ratio[6], &res->capture_reg->l1isp.L1_HDRE_RATIO06);
> + writel(param->hdre_ratio[7], &res->capture_reg->l1isp.L1_HDRE_RATIO07);
> + writel(param->hdre_ratio[8], &res->capture_reg->l1isp.L1_HDRE_RATIO08);
> + writel(param->hdre_ratio[9], &res->capture_reg->l1isp.L1_HDRE_RATIO09);
> + writel(param->hdre_ratio[10], &res->capture_reg->l1isp.L1_HDRE_RATIO10);
> + writel(param->hdre_ratio[11], &res->capture_reg->l1isp.L1_HDRE_RATIO11);
> + writel(param->hdre_ratio[12], &res->capture_reg->l1isp.L1_HDRE_RATIO12);
> + writel(param->hdre_ratio[13], &res->capture_reg->l1isp.L1_HDRE_RATIO13);
> + writel(param->hdre_ratio[14], &res->capture_reg->l1isp.L1_HDRE_RATIO14);
> + writel(param->hdre_ratio[15], &res->capture_reg->l1isp.L1_HDRE_RATIO15);
> + writel(param->hdre_ratio[16], &res->capture_reg->l1isp.L1_HDRE_RATIO16);
> +
> + writel(param->hdre_dst_max_val, &res->capture_reg->l1isp.L1_HDRE_DSTMAXVAL);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_img_extraction() - Configure L1ISP image extraction parameters.
> + *
> + * @input_black_gr: black level of Gr input pixel [0x0..0xffffff]
> + * @input_black_r: black level of R input pixel [0x0..0xffffff]
> + * @input_black_b: black level of B input pixel [0x0..0xffffff]
> + * @input_black_gb: black level of Gb input pixel [0x0..0xffffff]
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "input_black_gr" is out of range
> + * - "input_black_r" is out of range
> + * - "input_black_b" is out of range
> + * - "input_black_gb" is out of range
> + */
> +s32 hwd_viif_l1_set_img_extraction(struct hwd_viif_res *res, u32 input_black_gr, u32 input_black_r,
> + u32 input_black_b, u32 input_black_gb)
> +{
> + if (input_black_gr > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
> + input_black_r > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
> + input_black_b > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
> + input_black_gb > HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL) {
> + return -EINVAL;
> + }
> +
> + writel(input_black_gr, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_GR);
> + writel(input_black_r, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_R);
> + writel(input_black_b, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_B);
> + writel(input_black_gb, &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_GB);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_dpc() - Configure L1ISP defect pixel correction parameters.
> + *
> + * @param_h: pointer to defect pixel correction parameters for high sensitivity image
> + * @param_m: pointer to defect pixel correction parameters for middle sensitivity or led image
> + * @param_l: pointer to defect pixel correction parameters for low sensitivity image
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "param_h", "param_m" and "param_l" are NULL
> + * - each member of "param_h" is invalid
> + * - each member of "param_m" is invalid
> + * - each member of "param_l" is invalid
> + */
> +s32 hwd_viif_l1_set_dpc(struct hwd_viif_res *res, const struct viif_l1_dpc *param_h,
> + const struct viif_l1_dpc *param_m, const struct viif_l1_dpc *param_l)
> +{
> + const struct viif_l1_dpc *param;
> + u32 idx;
> + u32 val;
> +
> + if (!param_h && !param_m && !param_l)
> + return -EINVAL;
> +
> + for (idx = 0U; idx < 3U; idx++) {
> + if (idx == 0U)
> + param = param_h;
> + else if (idx == 1U)
> + param = param_m;
> + else
> + param = param_l;
> +
> + if (!param)
> + continue;
> +
> + if ((param->abpc_sta_en != HWD_VIIF_ENABLE &&
> + param->abpc_sta_en != HWD_VIIF_DISABLE) ||
> + (param->abpc_dyn_en != HWD_VIIF_ENABLE &&
> + param->abpc_dyn_en != HWD_VIIF_DISABLE)) {
> + return -EINVAL;
> + }
> +
> + if (param->abpc_dyn_en != HWD_VIIF_ENABLE)
> + continue;
> +
> + if ((param->abpc_dyn_mode != HWD_VIIF_L1_DPC_1PIXEL &&
> + param->abpc_dyn_mode != HWD_VIIF_L1_DPC_2PIXEL) ||
> + param->abpc_ratio_limit > HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL ||
> + param->abpc_dark_limit > HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL ||
> + param->abpc_sn_coef_w_ag_min < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_w_ag_min > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_w_ag_mid < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_w_ag_mid > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_w_ag_max < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_w_ag_max > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_b_ag_min < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_b_ag_min > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_b_ag_mid < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_b_ag_mid > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_b_ag_max < HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_b_ag_max > HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> + param->abpc_sn_coef_w_th_min >= param->abpc_sn_coef_w_th_max ||
> + param->abpc_sn_coef_b_th_min >= param->abpc_sn_coef_b_th_max) {
> + return -EINVAL;
> + }
> + }
> +
> + val = 0;
> + if (param_h)
> + val |= param_h->abpc_sta_en << 24U;
> +
> + if (param_m)
> + val |= param_m->abpc_sta_en << 16U;
> +
> + if (param_l)
> + val |= param_l->abpc_sta_en << 8U;
> +
> + writel(val, &res->capture_reg->l1isp.L1_ABPC012_STA_EN);
> +
> + val = 0;
> + if (param_h)
> + val |= param_h->abpc_dyn_en << 24U;
> +
> + if (param_m)
> + val |= param_m->abpc_dyn_en << 16U;
> +
> + if (param_l)
> + val |= param_l->abpc_dyn_en << 8U;
> +
> + writel(val, &res->capture_reg->l1isp.L1_ABPC012_DYN_EN);
> +
> + val = 0;
> + if (param_h)
> + val |= param_h->abpc_dyn_mode << 24U;
> +
> + if (param_m)
> + val |= param_m->abpc_dyn_mode << 16U;
> +
> + if (param_l)
> + val |= param_l->abpc_dyn_mode << 8U;
> +
> + writel(val, &res->capture_reg->l1isp.L1_ABPC012_DYN_MODE);
> +
> + if (param_h) {
> + writel(param_h->abpc_ratio_limit, &res->capture_reg->l1isp.L1_ABPC0_RATIO_LIMIT);
> + writel(param_h->abpc_dark_limit, &res->capture_reg->l1isp.L1_ABPC0_DARK_LIMIT);
> + writel(param_h->abpc_sn_coef_w_ag_min,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MIN);
> + writel(param_h->abpc_sn_coef_w_ag_mid,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MID);
> + writel(param_h->abpc_sn_coef_w_ag_max,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MAX);
> + writel(param_h->abpc_sn_coef_b_ag_min,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MIN);
> + writel(param_h->abpc_sn_coef_b_ag_mid,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MID);
> + writel(param_h->abpc_sn_coef_b_ag_max,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MAX);
> + writel((u32)param_h->abpc_sn_coef_w_th_min,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_TH_MIN);
> + writel((u32)param_h->abpc_sn_coef_w_th_max,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_TH_MAX);
> + writel((u32)param_h->abpc_sn_coef_b_th_min,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_TH_MIN);
> + writel((u32)param_h->abpc_sn_coef_b_th_max,
> + &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_TH_MAX);
> + }
> +
> + if (param_m) {
> + writel(param_m->abpc_ratio_limit, &res->capture_reg->l1isp.L1_ABPC1_RATIO_LIMIT);
> + writel(param_m->abpc_dark_limit, &res->capture_reg->l1isp.L1_ABPC1_DARK_LIMIT);
> + writel(param_m->abpc_sn_coef_w_ag_min,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MIN);
> + writel(param_m->abpc_sn_coef_w_ag_mid,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MID);
> + writel(param_m->abpc_sn_coef_w_ag_max,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MAX);
> + writel(param_m->abpc_sn_coef_b_ag_min,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MIN);
> + writel(param_m->abpc_sn_coef_b_ag_mid,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MID);
> + writel(param_m->abpc_sn_coef_b_ag_max,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MAX);
> + writel((u32)param_m->abpc_sn_coef_w_th_min,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_TH_MIN);
> + writel((u32)param_m->abpc_sn_coef_w_th_max,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_TH_MAX);
> + writel((u32)param_m->abpc_sn_coef_b_th_min,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_TH_MIN);
> + writel((u32)param_m->abpc_sn_coef_b_th_max,
> + &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_TH_MAX);
> + }
> +
> + if (param_l) {
> + writel(param_l->abpc_ratio_limit, &res->capture_reg->l1isp.L1_ABPC2_RATIO_LIMIT);
> + writel(param_l->abpc_dark_limit, &res->capture_reg->l1isp.L1_ABPC2_DARK_LIMIT);
> + writel(param_l->abpc_sn_coef_w_ag_min,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MIN);
> + writel(param_l->abpc_sn_coef_w_ag_mid,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MID);
> + writel(param_l->abpc_sn_coef_w_ag_max,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MAX);
> + writel(param_l->abpc_sn_coef_b_ag_min,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MIN);
> + writel(param_l->abpc_sn_coef_b_ag_mid,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MID);
> + writel(param_l->abpc_sn_coef_b_ag_max,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MAX);
> + writel((u32)param_l->abpc_sn_coef_w_th_min,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_TH_MIN);
> + writel((u32)param_l->abpc_sn_coef_w_th_max,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_TH_MAX);
> + writel((u32)param_l->abpc_sn_coef_b_th_min,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_TH_MIN);
> + writel((u32)param_l->abpc_sn_coef_b_th_max,
> + &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_TH_MAX);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_dpc_table_transmission() -
> + * Configure L1ISP transferring defect pixel correction table.
> + *
> + * @table_h: defect pixel correction table for high sensitivity image(physical address)
> + * @table_m: defect pixel correction table for middle sensitivity or led image(physical address)
> + * @table_l: defect pixel correction table for low sensitivity image(physical address)
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "table_h", "table_m" or "table_l" is not 8byte alignment
> + *
> + * Note that when 0 is set to table address, table transfer of the table is disabled.
> + */
> +s32 hwd_viif_l1_set_dpc_table_transmission(struct hwd_viif_res *res, uintptr_t table_h,
> + uintptr_t table_m, uintptr_t table_l)
> +{
> + u32 val = 0x0U;
> +
> + if (((table_h % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> + ((table_m % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> + ((table_l % HWD_VIIF_L1_VDM_ALIGN) != 0U)) {
> + return -EINVAL;
> + }
> +
> + /* VDM common settings */
> +
> + writel(HWD_VIIF_L1_VDM_CFG_PARAM, &res->capture_reg->vdm.t_group[0].VDM_T_CFG);
> + writel(HWD_VIIF_L1_VDM_SRAM_BASE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_BASE);
> + writel(HWD_VIIF_L1_VDM_SRAM_SIZE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_SIZE);
> +
> + if (table_h != 0U) {
> + writel((u32)table_h, &res->capture_reg->vdm.t_port[0].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE, &res->capture_reg->vdm.t_port[0].VDM_T_SIZE);
> + val |= 0x1U;
> + }
> +
> + if (table_m != 0U) {
> + writel((u32)table_m, &res->capture_reg->vdm.t_port[1].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE, &res->capture_reg->vdm.t_port[1].VDM_T_SIZE);
> + val |= 0x2U;
> + }
> +
> + if (table_l != 0U) {
> + writel((u32)table_l, &res->capture_reg->vdm.t_port[2].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE, &res->capture_reg->vdm.t_port[2].VDM_T_SIZE);
> + val |= 0x4U;
> + }
> +
> + val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) & 0xfffffff8U);
> + writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_preset_white_balance() - Configure L1ISP preset white balance parameters.
> + *
> + * @dstmaxval: maximum output pixel value [0..4095]
> + * @param_h: pointer to preset white balance parameters for high sensitivity image
> + * @param_m: pointer to preset white balance parameters for middle sensitivity or led image
> + * @param_l: pointer to preset white balance parameters for low sensitivity image
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "dstmaxval" is out of range
> + * - "param_h", "param_m", and "param_l" are NULL
> + * - each parameter of "param_h" is out of range
> + * - each parameter of "param_m" is out of range
> + * - each parameter of "param_l" is out of range
> + * Note that when NULL is set to "param_{h/m/l}", the corresponding parameters are not set to HW.
> + */
> +s32 hwd_viif_l1_set_preset_white_balance(struct hwd_viif_res *res, u32 dstmaxval,
> + const struct viif_l1_preset_wb *param_h,
> + const struct viif_l1_preset_wb *param_m,
> + const struct viif_l1_preset_wb *param_l)
> +{
> + if (dstmaxval > HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL || (!param_h && !param_m && !param_l))
> + return -EINVAL;
> +
> + if (param_h) {
> + if (param_h->gain_gr >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_h->gain_r >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_h->gain_b >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_h->gain_gb >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param_m) {
> + if (param_m->gain_gr >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_m->gain_r >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_m->gain_b >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_m->gain_gb >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param_l) {
> + if (param_l->gain_gr >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_l->gain_r >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_l->gain_b >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> + param_l->gain_gb >= HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
> + return -EINVAL;
> + }
> + }
> +
> + writel(dstmaxval, &res->capture_reg->l1isp.L1_PWHB_DSTMAXVAL);
> +
> + if (param_h) {
> + writel(param_h->gain_gr, &res->capture_reg->l1isp.L1_PWHB_H_GR);
> + writel(param_h->gain_r, &res->capture_reg->l1isp.L1_PWHB_HR);
> + writel(param_h->gain_b, &res->capture_reg->l1isp.L1_PWHB_HB);
> + writel(param_h->gain_gb, &res->capture_reg->l1isp.L1_PWHB_H_GB);
> + }
> +
> + if (param_m) {
> + writel(param_m->gain_gr, &res->capture_reg->l1isp.L1_PWHB_M_GR);
> + writel(param_m->gain_r, &res->capture_reg->l1isp.L1_PWHB_MR);
> + writel(param_m->gain_b, &res->capture_reg->l1isp.L1_PWHB_MB);
> + writel(param_m->gain_gb, &res->capture_reg->l1isp.L1_PWHB_M_GB);
> + }
> +
> + if (param_l) {
> + writel(param_l->gain_gr, &res->capture_reg->l1isp.L1_PWHB_L_GR);
> + writel(param_l->gain_r, &res->capture_reg->l1isp.L1_PWHB_LR);
> + writel(param_l->gain_b, &res->capture_reg->l1isp.L1_PWHB_LB);
> + writel(param_l->gain_gb, &res->capture_reg->l1isp.L1_PWHB_L_GB);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_raw_color_noise_reduction() -
> + * Configure L1ISP raw color noise reduction parameters.
> + *
> + * @param_h: pointer to raw color noise reduction parameters for high sensitivity image
> + * @param_m: pointer to raw color noise reduction parameters for middle sensitivity or led image
> + * @param_l: pointer to raw color noise reduction parameters for low sensitivity image
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "param_h", "param_m", and "param_l" are NULL
> + * - each parameter of "param_h" is out of range
> + * - each parameter of "param_m" is out of range
> + * - each parameter of "param_l" is out of range
> + * Note that when NULL is set to "param_{h/m/l}", the corresponding parameters are not set to HW.
> + */
> +s32 hwd_viif_l1_set_raw_color_noise_reduction(
> + struct hwd_viif_res *res, const struct viif_l1_raw_color_noise_reduction *param_h,
> + const struct viif_l1_raw_color_noise_reduction *param_m,
> + const struct viif_l1_raw_color_noise_reduction *param_l)
> +{
> + const struct viif_l1_raw_color_noise_reduction *param;
> + u32 idx;
> +
> + if (!param_h && !param_m && !param_l)
> + return -EINVAL;
> +
> + for (idx = 0; idx < 3U; idx++) {
> + if (idx == 0U)
> + param = param_h;
> + else if (idx == 1U)
> + param = param_m;
> + else
> + param = param_l;
> +
> + if (!param)
> + continue;
> +
> + if (param->rcnr_sw != HWD_VIIF_ENABLE && param->rcnr_sw != HWD_VIIF_DISABLE)
> + return -EINVAL;
> +
> + if (param->rcnr_cnf_dark_ag0 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> + param->rcnr_cnf_dark_ag1 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> + param->rcnr_cnf_dark_ag2 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> + param->rcnr_cnf_ratio_ag0 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> + param->rcnr_cnf_ratio_ag1 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> + param->rcnr_cnf_ratio_ag2 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> + param->rcnr_cnf_clip_gain_r > HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
> + param->rcnr_cnf_clip_gain_g > HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
> + param->rcnr_cnf_clip_gain_b > HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
> + param->rcnr_a1l_dark_ag0 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> + param->rcnr_a1l_dark_ag1 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> + param->rcnr_a1l_dark_ag2 > HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> + param->rcnr_a1l_ratio_ag0 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> + param->rcnr_a1l_ratio_ag1 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> + param->rcnr_a1l_ratio_ag2 > HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> + param->rcnr_inf_zero_clip > HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL ||
> + param->rcnr_merge_d2blend_ag0 > HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
> + param->rcnr_merge_d2blend_ag1 > HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
> + param->rcnr_merge_d2blend_ag2 > HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
> + param->rcnr_merge_black > HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL ||
> + param->rcnr_merge_mindiv < HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL ||
> + param->rcnr_merge_mindiv > HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL) {
> + return -EINVAL;
> + }
> +
> + switch (param->rcnr_hry_type) {
> + case HWD_VIIF_L1_RCNR_LOW_RESOLUTION:
> + case HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION:
> + case HWD_VIIF_L1_RCNR_HIGH_RESOLUTION:
> + case HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION:
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + if (param->rcnr_anf_blend_ag0 != HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
> + param->rcnr_anf_blend_ag0 != HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
> + param->rcnr_anf_blend_ag0 != HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
> + return -EINVAL;
> + }
> + if (param->rcnr_anf_blend_ag1 != HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
> + param->rcnr_anf_blend_ag1 != HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
> + param->rcnr_anf_blend_ag1 != HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
> + return -EINVAL;
> + }
> + if (param->rcnr_anf_blend_ag2 != HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
> + param->rcnr_anf_blend_ag2 != HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
> + param->rcnr_anf_blend_ag2 != HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
> + return -EINVAL;
> + }
> +
> + if (param->rcnr_lpf_threshold >= HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL ||
> + param->rcnr_merge_hlblend_ag0 > HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
> + param->rcnr_merge_hlblend_ag1 > HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
> + param->rcnr_merge_hlblend_ag2 > HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
> + (param->rcnr_gnr_sw != HWD_VIIF_DISABLE &&
> + param->rcnr_gnr_sw != HWD_VIIF_ENABLE)) {
> + return -EINVAL;
> + }
> +
> + if (param->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> + if (param->rcnr_gnr_ratio > HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO)
> + return -EINVAL;
> + if (param->rcnr_gnr_wide_en != HWD_VIIF_DISABLE &&
> + param->rcnr_gnr_wide_en != HWD_VIIF_ENABLE) {
> + return -EINVAL;
> + }
> + }
> + }
> +
> + if (param_h) {
> + writel(param_h->rcnr_sw, &res->capture_reg->l1isp.L1_RCNR0_SW);
> +
> + writel(param_h->rcnr_cnf_dark_ag0, &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG0);
> + writel(param_h->rcnr_cnf_dark_ag1, &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG1);
> + writel(param_h->rcnr_cnf_dark_ag2, &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG2);
> +
> + writel(param_h->rcnr_cnf_ratio_ag0,
> + &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG0);
> + writel(param_h->rcnr_cnf_ratio_ag1,
> + &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG1);
> + writel(param_h->rcnr_cnf_ratio_ag2,
> + &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG2);
> +
> + writel(param_h->rcnr_cnf_clip_gain_r,
> + &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_R);
> + writel(param_h->rcnr_cnf_clip_gain_g,
> + &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_G);
> + writel(param_h->rcnr_cnf_clip_gain_b,
> + &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_B);
> +
> + writel(param_h->rcnr_a1l_dark_ag0, &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG0);
> + writel(param_h->rcnr_a1l_dark_ag1, &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG1);
> + writel(param_h->rcnr_a1l_dark_ag2, &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG2);
> +
> + writel(param_h->rcnr_a1l_ratio_ag0,
> + &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG0);
> + writel(param_h->rcnr_a1l_ratio_ag1,
> + &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG1);
> + writel(param_h->rcnr_a1l_ratio_ag2,
> + &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG2);
> +
> + writel(param_h->rcnr_inf_zero_clip,
> + &res->capture_reg->l1isp.L1_RCNR0_INF_ZERO_CLIP);
> +
> + writel(param_h->rcnr_merge_d2blend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG0);
> + writel(param_h->rcnr_merge_d2blend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG1);
> + writel(param_h->rcnr_merge_d2blend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG2);
> + writel(param_h->rcnr_merge_black, &res->capture_reg->l1isp.L1_RCNR0_MERGE_BLACK);
> + writel(param_h->rcnr_merge_mindiv, &res->capture_reg->l1isp.L1_RCNR0_MERGE_MINDIV);
> +
> + writel(param_h->rcnr_hry_type, &res->capture_reg->l1isp.L1_RCNR0_HRY_TYPE);
> +
> + writel(param_h->rcnr_anf_blend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG0);
> + writel(param_h->rcnr_anf_blend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG1);
> + writel(param_h->rcnr_anf_blend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG2);
> +
> + writel(param_h->rcnr_lpf_threshold,
> + &res->capture_reg->l1isp.L1_RCNR0_LPF_THRESHOLD);
> +
> + writel(param_h->rcnr_merge_hlblend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG0);
> + writel(param_h->rcnr_merge_hlblend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG1);
> + writel(param_h->rcnr_merge_hlblend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG2);
> +
> + writel(param_h->rcnr_gnr_sw, &res->capture_reg->l1isp.L1_RCNR0_GNR_SW);
> +
> + if (param_h->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> + writel(param_h->rcnr_gnr_ratio,
> + &res->capture_reg->l1isp.L1_RCNR0_GNR_RATIO);
> + writel(param_h->rcnr_gnr_wide_en,
> + &res->capture_reg->l1isp.L1_RCNR0_GNR_WIDE_EN);
> + }
> + }
> +
> + if (param_m) {
> + writel(param_m->rcnr_sw, &res->capture_reg->l1isp.L1_RCNR1_SW);
> +
> + writel(param_m->rcnr_cnf_dark_ag0, &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG0);
> + writel(param_m->rcnr_cnf_dark_ag1, &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG1);
> + writel(param_m->rcnr_cnf_dark_ag2, &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG2);
> +
> + writel(param_m->rcnr_cnf_ratio_ag0,
> + &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG0);
> + writel(param_m->rcnr_cnf_ratio_ag1,
> + &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG1);
> + writel(param_m->rcnr_cnf_ratio_ag2,
> + &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG2);
> +
> + writel(param_m->rcnr_cnf_clip_gain_r,
> + &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_R);
> + writel(param_m->rcnr_cnf_clip_gain_g,
> + &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_G);
> + writel(param_m->rcnr_cnf_clip_gain_b,
> + &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_B);
> +
> + writel(param_m->rcnr_a1l_dark_ag0, &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG0);
> + writel(param_m->rcnr_a1l_dark_ag1, &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG1);
> + writel(param_m->rcnr_a1l_dark_ag2, &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG2);
> +
> + writel(param_m->rcnr_a1l_ratio_ag0,
> + &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG0);
> + writel(param_m->rcnr_a1l_ratio_ag1,
> + &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG1);
> + writel(param_m->rcnr_a1l_ratio_ag2,
> + &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG2);
> +
> + writel(param_m->rcnr_inf_zero_clip,
> + &res->capture_reg->l1isp.L1_RCNR1_INF_ZERO_CLIP);
> +
> + writel(param_m->rcnr_merge_d2blend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG0);
> + writel(param_m->rcnr_merge_d2blend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG1);
> + writel(param_m->rcnr_merge_d2blend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG2);
> + writel(param_m->rcnr_merge_black, &res->capture_reg->l1isp.L1_RCNR1_MERGE_BLACK);
> + writel(param_m->rcnr_merge_mindiv, &res->capture_reg->l1isp.L1_RCNR1_MERGE_MINDIV);
> +
> + writel(param_m->rcnr_hry_type, &res->capture_reg->l1isp.L1_RCNR1_HRY_TYPE);
> +
> + writel(param_m->rcnr_anf_blend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG0);
> + writel(param_m->rcnr_anf_blend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG1);
> + writel(param_m->rcnr_anf_blend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG2);
> +
> + writel(param_m->rcnr_lpf_threshold,
> + &res->capture_reg->l1isp.L1_RCNR1_LPF_THRESHOLD);
> +
> + writel(param_m->rcnr_merge_hlblend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG0);
> + writel(param_m->rcnr_merge_hlblend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG1);
> + writel(param_m->rcnr_merge_hlblend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG2);
> +
> + writel(param_m->rcnr_gnr_sw, &res->capture_reg->l1isp.L1_RCNR1_GNR_SW);
> +
> + if (param_m->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> + writel(param_m->rcnr_gnr_ratio,
> + &res->capture_reg->l1isp.L1_RCNR1_GNR_RATIO);
> + writel(param_m->rcnr_gnr_wide_en,
> + &res->capture_reg->l1isp.L1_RCNR1_GNR_WIDE_EN);
> + }
> + }
> +
> + if (param_l) {
> + writel(param_l->rcnr_sw, &res->capture_reg->l1isp.L1_RCNR2_SW);
> +
> + writel(param_l->rcnr_cnf_dark_ag0, &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG0);
> + writel(param_l->rcnr_cnf_dark_ag1, &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG1);
> + writel(param_l->rcnr_cnf_dark_ag2, &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG2);
> +
> + writel(param_l->rcnr_cnf_ratio_ag0,
> + &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG0);
> + writel(param_l->rcnr_cnf_ratio_ag1,
> + &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG1);
> + writel(param_l->rcnr_cnf_ratio_ag2,
> + &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG2);
> +
> + writel(param_l->rcnr_cnf_clip_gain_r,
> + &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_R);
> + writel(param_l->rcnr_cnf_clip_gain_g,
> + &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_G);
> + writel(param_l->rcnr_cnf_clip_gain_b,
> + &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_B);
> +
> + writel(param_l->rcnr_a1l_dark_ag0, &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG0);
> + writel(param_l->rcnr_a1l_dark_ag1, &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG1);
> + writel(param_l->rcnr_a1l_dark_ag2, &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG2);
> +
> + writel(param_l->rcnr_a1l_ratio_ag0,
> + &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG0);
> + writel(param_l->rcnr_a1l_ratio_ag1,
> + &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG1);
> + writel(param_l->rcnr_a1l_ratio_ag2,
> + &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG2);
> +
> + writel(param_l->rcnr_inf_zero_clip,
> + &res->capture_reg->l1isp.L1_RCNR2_INF_ZERO_CLIP);
> +
> + writel(param_l->rcnr_merge_d2blend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG0);
> + writel(param_l->rcnr_merge_d2blend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG1);
> + writel(param_l->rcnr_merge_d2blend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG2);
> + writel(param_l->rcnr_merge_black, &res->capture_reg->l1isp.L1_RCNR2_MERGE_BLACK);
> + writel(param_l->rcnr_merge_mindiv, &res->capture_reg->l1isp.L1_RCNR2_MERGE_MINDIV);
> +
> + writel(param_l->rcnr_hry_type, &res->capture_reg->l1isp.L1_RCNR2_HRY_TYPE);
> +
> + writel(param_l->rcnr_anf_blend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG0);
> + writel(param_l->rcnr_anf_blend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG1);
> + writel(param_l->rcnr_anf_blend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG2);
> +
> + writel(param_l->rcnr_lpf_threshold,
> + &res->capture_reg->l1isp.L1_RCNR2_LPF_THRESHOLD);
> +
> + writel(param_l->rcnr_merge_hlblend_ag0,
> + &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG0);
> + writel(param_l->rcnr_merge_hlblend_ag1,
> + &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG1);
> + writel(param_l->rcnr_merge_hlblend_ag2,
> + &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG2);
> +
> + writel(param_l->rcnr_gnr_sw, &res->capture_reg->l1isp.L1_RCNR2_GNR_SW);
> +
> + if (param_l->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> + writel(param_l->rcnr_gnr_ratio,
> + &res->capture_reg->l1isp.L1_RCNR2_GNR_RATIO);
> + writel(param_l->rcnr_gnr_wide_en,
> + &res->capture_reg->l1isp.L1_RCNR2_GNR_WIDE_EN);
> + }
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_hdrs() - Configure L1ISP HDR synthesis parameters.
> + *
> + * @param: pointer to HDR synthesis parameters
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "param" is NULL
> + * - each parameter of "param" is out of range
> + */
> +s32 hwd_viif_l1_set_hdrs(struct hwd_viif_res *res, const struct viif_l1_hdrs_config *param)
> +{
> + if (!param ||
> + (param->hdrs_hdr_mode != HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE &&
> + param->hdrs_hdr_mode != HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) ||
> + param->hdrs_hdr_ratio_m < HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
> + param->hdrs_hdr_ratio_m > HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
> + param->hdrs_hdr_ratio_l < HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
> + param->hdrs_hdr_ratio_l > HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
> + param->hdrs_hdr_ratio_e < HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
> + param->hdrs_hdr_ratio_e > HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
> + param->hdrs_dg_h >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> + param->hdrs_dg_m >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> + param->hdrs_dg_l >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> + param->hdrs_dg_e >= HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> + param->hdrs_blendend_h > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> + param->hdrs_blendend_m > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> + param->hdrs_blendend_e > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> + param->hdrs_blendbeg_h > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> + param->hdrs_blendbeg_m > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> + param->hdrs_blendbeg_e > HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> + (param->hdrs_led_mode_on != HWD_VIIF_ENABLE &&
> + param->hdrs_led_mode_on != HWD_VIIF_DISABLE) ||
> + param->hdrs_dst_max_val > HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL) {
> + return -EINVAL;
> + }
> +
> + writel(param->hdrs_hdr_mode, &res->capture_reg->l1isp.L1_HDRS_HDRMODE);
> +
> + writel(param->hdrs_hdr_ratio_m, &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_M);
> + writel(param->hdrs_hdr_ratio_l, &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_L);
> + writel(param->hdrs_hdr_ratio_e, &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_E);
> +
> + writel(param->hdrs_dg_h, &res->capture_reg->l1isp.L1_HDRS_DG_H);
> + writel(param->hdrs_dg_m, &res->capture_reg->l1isp.L1_HDRS_DG_M);
> + writel(param->hdrs_dg_l, &res->capture_reg->l1isp.L1_HDRS_DG_L);
> + writel(param->hdrs_dg_e, &res->capture_reg->l1isp.L1_HDRS_DG_E);
> +
> + writel(param->hdrs_blendend_h, &res->capture_reg->l1isp.L1_HDRS_BLENDEND_H);
> + writel(param->hdrs_blendend_m, &res->capture_reg->l1isp.L1_HDRS_BLENDEND_M);
> + writel(param->hdrs_blendend_e, &res->capture_reg->l1isp.L1_HDRS_BLENDEND_E);
> +
> + writel(param->hdrs_blendbeg_h, &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_H);
> + writel(param->hdrs_blendbeg_m, &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_M);
> + writel(param->hdrs_blendbeg_e, &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_E);
> +
> + writel(param->hdrs_led_mode_on, &res->capture_reg->l1isp.L1_HDRS_LEDMODE_ON);
> + writel(param->hdrs_dst_max_val, &res->capture_reg->l1isp.L1_HDRS_DSTMAXVAL);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_black_level_correction() - Configure L1ISP black level correction parameters.
> + *
> + * @param: pointer to black level correction parameters
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "param" is NULL
> + * - each parameter of "param" is out of range
> + */
> +s32 hwd_viif_l1_set_black_level_correction(
> + struct hwd_viif_res *res, const struct viif_l1_black_level_correction_config *param)
> +{
> + if (!param || param->srcblacklevel_gr > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> + param->srcblacklevel_r > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> + param->srcblacklevel_b > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> + param->srcblacklevel_gb > HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> + param->mulval_gr >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> + param->mulval_r >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> + param->mulval_b >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> + param->mulval_gb >= HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> + param->dstmaxval > HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL) {
> + return -EINVAL;
> + }
> +
> + writel(param->srcblacklevel_gr, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_GR);
> + writel(param->srcblacklevel_r, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_R);
> + writel(param->srcblacklevel_b, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_B);
> + writel(param->srcblacklevel_gb, &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVELGB);
> +
> + writel(param->mulval_gr, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_GR);
> + writel(param->mulval_r, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_R);
> + writel(param->mulval_b, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_B);
> + writel(param->mulval_gb, &res->capture_reg->l1isp.L1_BLVC_MULTVAL_GB);
> +
> + writel(param->dstmaxval, &res->capture_reg->l1isp.L1_BLVC_DSTMAXVAL);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_lsc() - Configure L1ISP lens shading correction parameters.
> + *
> + * @param: pointer to lens shading correction parameters
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - each parameter of "param" is out of range
> + * @note when NULL is set to "param"
> + */
> +s32 hwd_viif_l1_set_lsc(struct hwd_viif_res *res, const struct hwd_viif_l1_lsc *param)
> +{
> + u32 sysm_width, sysm_height;
> + u32 grid_h_size = 0U;
> + u32 grid_v_size = 0U;
> + s32 ret = 0;
> + u32 idx;
> + u32 val;
> + u32 tmp;
> +
> + if (!param) {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_LSSC_EN);
> + return 0;
> + }
> +
> + sysm_width = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
> + sysm_height = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> +
> + if (param->lssc_parabola_param) {
> + if (param->lssc_parabola_param->lssc_para_h_center >= sysm_width ||
> + param->lssc_parabola_param->lssc_para_v_center >= sysm_height ||
> + param->lssc_parabola_param->lssc_para_h_gain >= HWD_VIIF_LSC_MAX_GAIN ||
> + param->lssc_parabola_param->lssc_para_v_gain >= HWD_VIIF_LSC_MAX_GAIN) {
> + return -EINVAL;
> + }
> +
> + switch (param->lssc_parabola_param->lssc_para_mgsel2) {
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH:
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH:
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND:
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST:
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + switch (param->lssc_parabola_param->lssc_para_mgsel4) {
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH:
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH:
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND:
> + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST:
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + for (idx = 0U; idx < 8U; idx++) {
> + const struct viif_l1_lsc_parabola_ag_param *ag_param;
> +
> + switch (idx) {
> + case 0U:
> + ag_param = ¶m->lssc_parabola_param->r_2d;
> + break;
> + case 1U:
> + ag_param = ¶m->lssc_parabola_param->r_4d;
> + break;
> + case 2U:
> + ag_param = ¶m->lssc_parabola_param->gr_2d;
> + break;
> + case 3U:
> + ag_param = ¶m->lssc_parabola_param->gr_4d;
> + break;
> + case 4U:
> + ag_param = ¶m->lssc_parabola_param->gb_2d;
> + break;
> + case 5U:
> + ag_param = ¶m->lssc_parabola_param->gb_4d;
> + break;
> + case 6U:
> + ag_param = ¶m->lssc_parabola_param->b_2d;
> + break;
> + default:
> + ag_param = ¶m->lssc_parabola_param->b_4d;
> + break;
> + }
> +
> + if (!ag_param || ag_param->lssc_paracoef_h_l_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_h_l_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_h_l_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_h_l_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_h_l_min > ag_param->lssc_paracoef_h_l_max ||
> + ag_param->lssc_paracoef_h_r_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_h_r_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_h_r_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_h_r_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_h_r_min > ag_param->lssc_paracoef_h_r_max ||
> + ag_param->lssc_paracoef_v_u_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_v_u_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_v_u_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_v_u_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_v_u_min > ag_param->lssc_paracoef_v_u_max ||
> + ag_param->lssc_paracoef_v_d_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_v_d_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_v_d_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_v_d_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_v_d_min > ag_param->lssc_paracoef_v_d_max ||
> + ag_param->lssc_paracoef_hv_lu_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_lu_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_lu_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_lu_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_lu_min > ag_param->lssc_paracoef_hv_lu_max ||
> + ag_param->lssc_paracoef_hv_ru_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_ru_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_ru_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_ru_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_ru_min > ag_param->lssc_paracoef_hv_ru_max ||
> + ag_param->lssc_paracoef_hv_ld_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_ld_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_ld_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_ld_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_ld_min > ag_param->lssc_paracoef_hv_ld_max ||
> + ag_param->lssc_paracoef_hv_rd_max < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_rd_max >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_rd_min < HWD_VIIF_LSC_MIN_GAIN ||
> + ag_param->lssc_paracoef_hv_rd_min >= HWD_VIIF_LSC_MAX_GAIN ||
> + ag_param->lssc_paracoef_hv_rd_min > ag_param->lssc_paracoef_hv_rd_max) {
> + return -EINVAL;
> + }
> + }
> + }
> +
> + if (param->lssc_grid_param) {
> + switch (param->lssc_grid_param->lssc_grid_h_size) {
> + case 32U:
> + grid_h_size = 5U;
> + break;
> + case 64U:
> + grid_h_size = 6U;
> + break;
> + case 128U:
> + grid_h_size = 7U;
> + break;
> + case 256U:
> + grid_h_size = 8U;
> + break;
> + case 512U:
> + grid_h_size = 9U;
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (ret != 0)
> + return ret;
> +
> + switch (param->lssc_grid_param->lssc_grid_v_size) {
> + case 32U:
> + grid_v_size = 5U;
> + break;
> + case 64U:
> + grid_v_size = 6U;
> + break;
> + case 128U:
> + grid_v_size = 7U;
> + break;
> + case 256U:
> + grid_v_size = 8U;
> + break;
> + case 512U:
> + grid_v_size = 9U;
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (ret != 0)
> + return ret;
> +
> + if (param->lssc_grid_param->lssc_grid_h_center < HWD_VIIF_LSC_GRID_MIN_COORDINATE ||
> + param->lssc_grid_param->lssc_grid_h_center >
> + param->lssc_grid_param->lssc_grid_h_size) {
> + return -EINVAL;
> + }
> +
> + if (sysm_width > (param->lssc_grid_param->lssc_grid_h_center +
> + (param->lssc_grid_param->lssc_grid_h_size * 31U))) {
> + return -EINVAL;
> + }
> +
> + if (param->lssc_grid_param->lssc_grid_v_center < HWD_VIIF_LSC_GRID_MIN_COORDINATE ||
> + param->lssc_grid_param->lssc_grid_v_center >
> + param->lssc_grid_param->lssc_grid_v_size) {
> + return -EINVAL;
> + }
> +
> + if (sysm_height > (param->lssc_grid_param->lssc_grid_v_center +
> + (param->lssc_grid_param->lssc_grid_v_size * 23U))) {
> + return -EINVAL;
> + }
> +
> + if (param->lssc_grid_param->lssc_grid_mgsel != HWD_VIIF_L1_GRID_COEF_GAIN_X1 &&
> + param->lssc_grid_param->lssc_grid_mgsel != HWD_VIIF_L1_GRID_COEF_GAIN_X2) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param->lssc_pwhb_r_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_r_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_r_gain_min > param->lssc_pwhb_r_gain_max ||
> + param->lssc_pwhb_gr_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_gr_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_gr_gain_min > param->lssc_pwhb_gr_gain_max ||
> + param->lssc_pwhb_gb_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_gb_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_gb_gain_min > param->lssc_pwhb_gb_gain_max ||
> + param->lssc_pwhb_b_gain_max >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_b_gain_min >= HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> + param->lssc_pwhb_b_gain_min > param->lssc_pwhb_b_gain_max) {
> + return -EINVAL;
> + }
> +
> + /* parabola shading */
> + if (param->lssc_parabola_param) {
> + struct viif_l1_lsc_parabola_ag_param *r_2d;
> + struct viif_l1_lsc_parabola_ag_param *r_4d;
> + struct viif_l1_lsc_parabola_ag_param *gr_2d;
> + struct viif_l1_lsc_parabola_ag_param *gr_4d;
> + struct viif_l1_lsc_parabola_ag_param *gb_2d;
> + struct viif_l1_lsc_parabola_ag_param *gb_4d;
> + struct viif_l1_lsc_parabola_ag_param *b_2d;
> + struct viif_l1_lsc_parabola_ag_param *b_4d;
> +
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_PARA_EN);
> +
> + writel(param->lssc_parabola_param->lssc_para_h_center,
> + &res->capture_reg->l1isp.L1_LSSC_PARA_H_CENTER);
> + writel(param->lssc_parabola_param->lssc_para_v_center,
> + &res->capture_reg->l1isp.L1_LSSC_PARA_V_CENTER);
> +
> + writel(param->lssc_parabola_param->lssc_para_h_gain,
> + &res->capture_reg->l1isp.L1_LSSC_PARA_H_GAIN);
> + writel(param->lssc_parabola_param->lssc_para_v_gain,
> + &res->capture_reg->l1isp.L1_LSSC_PARA_V_GAIN);
> +
> + writel(param->lssc_parabola_param->lssc_para_mgsel2,
> + &res->capture_reg->l1isp.L1_LSSC_PARA_MGSEL2);
> + writel(param->lssc_parabola_param->lssc_para_mgsel4,
> + &res->capture_reg->l1isp.L1_LSSC_PARA_MGSEL4);
> +
> + /* R 2D */
> + r_2d = ¶m->lssc_parabola_param->r_2d;
> + tmp = (u32)r_2d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_H_L);
> +
> + tmp = (u32)r_2d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_H_R);
> +
> + tmp = (u32)r_2d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_V_U);
> +
> + tmp = (u32)r_2d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_V_D);
> +
> + tmp = (u32)r_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_LU);
> +
> + tmp = (u32)r_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_RU);
> +
> + tmp = (u32)r_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_LD);
> +
> + tmp = (u32)r_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_RD);
> +
> + /* R 4D */
> + r_4d = ¶m->lssc_parabola_param->r_4d;
> + tmp = (u32)r_4d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_H_L);
> +
> + tmp = (u32)r_4d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_H_R);
> +
> + tmp = (u32)r_4d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_V_U);
> +
> + tmp = (u32)r_4d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_V_D);
> +
> + tmp = (u32)r_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_LU);
> +
> + tmp = (u32)r_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_RU);
> +
> + tmp = (u32)r_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_LD);
> +
> + tmp = (u32)r_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_RD);
> +
> + /* GR 2D */
> + gr_2d = ¶m->lssc_parabola_param->gr_2d;
> + tmp = (u32)gr_2d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_H_L);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_H_R);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_V_U);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_V_D);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_LU);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_RU);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_LD);
> +
> + tmp = (u32)gr_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_RD);
> +
> + /* GR 4D */
> + gr_4d = ¶m->lssc_parabola_param->gr_4d;
> + tmp = (u32)gr_4d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_H_L);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_H_R);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_V_U);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_V_D);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_LU);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_RU);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_LD);
> +
> + tmp = (u32)gr_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_RD);
> +
> + /* GB 2D */
> + gb_2d = ¶m->lssc_parabola_param->gb_2d;
> + tmp = (u32)gb_2d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_H_L);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_H_R);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_V_U);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_V_D);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_LU);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_RU);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_LD);
> +
> + tmp = (u32)gb_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_RD);
> +
> + /* GB 4D */
> + gb_4d = ¶m->lssc_parabola_param->gb_4d;
> + tmp = (u32)gb_4d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_H_L);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_H_R);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_V_U);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_V_D);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_LU);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_RU);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_LD);
> +
> + tmp = (u32)gb_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_RD);
> +
> + /* B 2D */
> + b_2d = ¶m->lssc_parabola_param->b_2d;
> + tmp = (u32)b_2d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_H_L);
> +
> + tmp = (u32)b_2d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_H_R);
> +
> + tmp = (u32)b_2d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_V_U);
> +
> + tmp = (u32)b_2d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_V_D);
> +
> + tmp = (u32)b_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_LU);
> +
> + tmp = (u32)b_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_RU);
> +
> + tmp = (u32)b_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_LD);
> +
> + tmp = (u32)b_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_RD);
> +
> + /* B 4D */
> + b_4d = ¶m->lssc_parabola_param->b_4d;
> + tmp = (u32)b_4d->lssc_paracoef_h_l_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_h_l_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_H_L);
> +
> + tmp = (u32)b_4d->lssc_paracoef_h_r_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_h_r_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_H_R);
> +
> + tmp = (u32)b_4d->lssc_paracoef_v_u_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_v_u_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_V_U);
> +
> + tmp = (u32)b_4d->lssc_paracoef_v_d_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_v_d_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_V_D);
> +
> + tmp = (u32)b_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_lu_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_LU);
> +
> + tmp = (u32)b_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_ru_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_RU);
> +
> + tmp = (u32)b_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_ld_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_LD);
> +
> + tmp = (u32)b_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_rd_min & 0x1fffU);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_RD);
> +
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_LSSC_PARA_EN);
> + }
> +
> + /* grid shading */
> + if (param->lssc_grid_param) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_GRID_EN);
> + writel(grid_h_size, &res->capture_reg->l1isp.L1_LSSC_GRID_H_SIZE);
> + writel(grid_v_size, &res->capture_reg->l1isp.L1_LSSC_GRID_V_SIZE);
> + writel(param->lssc_grid_param->lssc_grid_h_center,
> + &res->capture_reg->l1isp.L1_LSSC_GRID_H_CENTER);
> + writel(param->lssc_grid_param->lssc_grid_v_center,
> + &res->capture_reg->l1isp.L1_LSSC_GRID_V_CENTER);
> + writel(param->lssc_grid_param->lssc_grid_mgsel,
> + &res->capture_reg->l1isp.L1_LSSC_GRID_MGSEL);
> +
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_LSSC_GRID_EN);
> + }
> +
> + /* preset white balance */
> + val = (param->lssc_pwhb_r_gain_max << 16U) | (param->lssc_pwhb_r_gain_min);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_R_GAIN);
> +
> + val = (param->lssc_pwhb_gr_gain_max << 16U) | (param->lssc_pwhb_gr_gain_min);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_GR_GAIN);
> +
> + val = (param->lssc_pwhb_gb_gain_max << 16U) | (param->lssc_pwhb_gb_gain_min);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_GB_GAIN);
> +
> + val = (param->lssc_pwhb_b_gain_max << 16U) | (param->lssc_pwhb_b_gain_min);
> + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_B_GAIN);
> +
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_EN);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_lsc_table_transmission() - Configure L1ISP transferring lens shading grid table.
> + *
> + * @table_gr: grid shading table for Gr(physical address)
> + * @table_r: grid shading table for R(physical address)
> + * @table_b: grid shading table for B(physical address)
> + * @table_gb: grid shading table for Gb(physical address)
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "table_h", "table_m" or "table_l" is not 8byte alignment
> + *
> + * Note that when 0 is set to table address, table transfer of the table is disabled.
> + */
> +s32 hwd_viif_l1_set_lsc_table_transmission(struct hwd_viif_res *res, uintptr_t table_gr,
> + uintptr_t table_r, uintptr_t table_b, uintptr_t table_gb)
> +{
> + u32 val = 0x0U;
> +
> + if (((table_gr % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> + ((table_r % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> + ((table_b % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> + ((table_gb % HWD_VIIF_L1_VDM_ALIGN) != 0U)) {
> + return -EINVAL;
> + }
> + /* VDM common settings */
> + writel(HWD_VIIF_L1_VDM_CFG_PARAM, &res->capture_reg->vdm.t_group[0].VDM_T_CFG);
> + writel(HWD_VIIF_L1_VDM_SRAM_BASE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_BASE);
> + writel(HWD_VIIF_L1_VDM_SRAM_SIZE, &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_SIZE);
> +
> + if (table_gr != 0U) {
> + writel((u32)table_gr, &res->capture_reg->vdm.t_port[4].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[4].VDM_T_SIZE);
> + val |= 0x10U;
> + }
> +
> + if (table_r != 0U) {
> + writel((u32)table_r, &res->capture_reg->vdm.t_port[5].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[5].VDM_T_SIZE);
> + val |= 0x20U;
> + }
> +
> + if (table_b != 0U) {
> + writel((u32)table_b, &res->capture_reg->vdm.t_port[6].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[6].VDM_T_SIZE);
> + val |= 0x40U;
> + }
> +
> + if (table_gb != 0U) {
> + writel((u32)table_gb, &res->capture_reg->vdm.t_port[7].VDM_T_STADR);
> + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE, &res->capture_reg->vdm.t_port[7].VDM_T_SIZE);
> + val |= 0x80U;
> + }
> +
> + val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) & 0xffffff0fU);
> + writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_main_process() - Configure L1ISP main process.
> + *
> + * @demosaic_mode: demosaic mode @ref hwd_viif_l1_demosaic
> + * @damp_lsbsel: output pixel clip range for auto white balance [0..15]
> + * @color_matrix: pointer to color matrix correction parameters
> + * @dst_maxval: output pixel maximum value [0x0..0xffffff]
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * main process means digital amp, demosaic, and color matrix correction
> + * NULL means disabling color matrix correction
> + * - "demosaic_mode" is neither HWD_VIIF_L1_DEMOSAIC_ACPI nor HWD_VIIF_L1_DEMOSAIC_DMG
> + * - "damp_lsbsel" is out of range
> + * - each parameter of "color_matrix" is out of range
> + * - "dst_maxval" is out of range
> + */
> +s32 hwd_viif_l1_set_main_process(struct hwd_viif_res *res, u32 demosaic_mode, u32 damp_lsbsel,
> + const struct viif_l1_color_matrix_correction *color_matrix,
> + u32 dst_maxval)
> +{
> + u32 val;
> +
> + if (demosaic_mode != HWD_VIIF_L1_DEMOSAIC_ACPI &&
> + demosaic_mode != HWD_VIIF_L1_DEMOSAIC_DMG) {
> + return -EINVAL;
> + }
> +
> + if (damp_lsbsel > HWD_VIIF_DAMP_MAX_LSBSEL)
> + return -EINVAL;
> +
> + if (color_matrix) {
> + if (color_matrix->coef_rmg_min > color_matrix->coef_rmg_max ||
> + color_matrix->coef_rmb_min > color_matrix->coef_rmb_max ||
> + color_matrix->coef_gmr_min > color_matrix->coef_gmr_max ||
> + color_matrix->coef_gmb_min > color_matrix->coef_gmb_max ||
> + color_matrix->coef_bmr_min > color_matrix->coef_bmr_max ||
> + color_matrix->coef_bmg_min > color_matrix->coef_bmg_max ||
> + (u32)color_matrix->dst_minval > dst_maxval)
> + return -EINVAL;
> + }
> +
> + if (dst_maxval > HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL)
> + return -EINVAL;
> +
> + val = damp_lsbsel << 4U;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_CONF);
> +
> + writel(demosaic_mode, &res->capture_reg->l1isp.L1_MPRO_LCS_MODE);
> +
> + if (color_matrix) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_MPRO_SW);
> +
> + val = (u32)color_matrix->coef_rmg_min & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMG_MIN);
> +
> + val = (u32)color_matrix->coef_rmg_max & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMG_MAX);
> +
> + val = (u32)color_matrix->coef_rmb_min & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMB_MIN);
> +
> + val = (u32)color_matrix->coef_rmb_max & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_RMB_MAX);
> +
> + val = (u32)color_matrix->coef_gmr_min & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMR_MIN);
> +
> + val = (u32)color_matrix->coef_gmr_max & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMR_MAX);
> +
> + val = (u32)color_matrix->coef_gmb_min & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMB_MIN);
> +
> + val = (u32)color_matrix->coef_gmb_max & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_GMB_MAX);
> +
> + val = (u32)color_matrix->coef_bmr_min & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMR_MIN);
> +
> + val = (u32)color_matrix->coef_bmr_max & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMR_MAX);
> +
> + val = (u32)color_matrix->coef_bmg_min & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMG_MIN);
> +
> + val = (u32)color_matrix->coef_bmg_max & 0xffffU;
> + writel(val, &res->capture_reg->l1isp.L1_MPRO_LM0_BMG_MAX);
> +
> + writel((u32)color_matrix->dst_minval, &res->capture_reg->l1isp.L1_MPRO_DST_MINVAL);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_MPRO_SW);
> + }
> +
> + writel(dst_maxval, &res->capture_reg->l1isp.L1_MPRO_DST_MAXVAL);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_awb() - Configure L1ISP auto white balance parameters.
> + *
> + * @param: pointer to auto white balance parameters; NULL means disabling auto white balance
> + * @awhb_wbmrg: R gain of white balance adjustment [0x40..0x3FF] accuracy: 1/256
> + * @awhb_wbmgg: G gain of white balance adjustment [0x40..0x3FF] accuracy: 1/256
> + * @awhb_wbmbg: B gain of white balance adjustment [0x40..0x3FF] accuracy: 1/256
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL
> + * - each parameter of "param" is out of range
> + * - awhb_wbm*g is out of range
> + */
> +s32 hwd_viif_l1_set_awb(struct hwd_viif_res *res, const struct viif_l1_awb *param, u32 awhb_wbmrg,
> + u32 awhb_wbmgg, u32 awhb_wbmbg)
> +{
> + u32 val, ygate_data;
> +
> + if (awhb_wbmrg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmrg >= HWD_VIIF_AWB_MAX_GAIN ||
> + awhb_wbmgg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmgg >= HWD_VIIF_AWB_MAX_GAIN ||
> + awhb_wbmbg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmbg >= HWD_VIIF_AWB_MAX_GAIN) {
> + return -EINVAL;
> + }
> +
> + if (param) {
> + if (param->awhb_ygate_sel != HWD_VIIF_ENABLE &&
> + param->awhb_ygate_sel != HWD_VIIF_DISABLE) {
> + return -EINVAL;
> + }
> +
> + if (param->awhb_ygate_data != 64U && param->awhb_ygate_data != 128U &&
> + param->awhb_ygate_data != 256U && param->awhb_ygate_data != 512U) {
> + return -EINVAL;
> + }
> +
> + if (param->awhb_cgrange != HWD_VIIF_L1_AWB_ONE_SECOND &&
> + param->awhb_cgrange != HWD_VIIF_L1_AWB_X1 &&
> + param->awhb_cgrange != HWD_VIIF_L1_AWB_X2 &&
> + param->awhb_cgrange != HWD_VIIF_L1_AWB_X4) {
> + return -EINVAL;
> + }
> +
> + if (param->awhb_ygatesw != HWD_VIIF_ENABLE &&
> + param->awhb_ygatesw != HWD_VIIF_DISABLE) {
> + return -EINVAL;
> + }
> +
> + if (param->awhb_hexsw != HWD_VIIF_ENABLE && param->awhb_hexsw != HWD_VIIF_DISABLE)
> + return -EINVAL;
> +
> + if (param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE0 &&
> + param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE1 &&
> + param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE2 &&
> + param->awhb_areamode != HWD_VIIF_L1_AWB_AREA_MODE3) {
> + return -EINVAL;
> + }
> +
> + val = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
> + if (param->awhb_area_hsize < 1U || (param->awhb_area_hsize > ((val - 8U) / 8U)) ||
> + param->awhb_area_hofs > (val - 9U)) {
> + return -EINVAL;
> + }
> +
> + val = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> + if (param->awhb_area_vsize < 1U || (param->awhb_area_vsize > ((val - 4U) / 8U)) ||
> + param->awhb_area_vofs > (val - 5U)) {
> + return -EINVAL;
> + }
> +
> + if ((param->awhb_sq_sw[0] != HWD_VIIF_ENABLE &&
> + param->awhb_sq_sw[0] != HWD_VIIF_DISABLE) ||
> + (param->awhb_sq_sw[1] != HWD_VIIF_ENABLE &&
> + param->awhb_sq_sw[1] != HWD_VIIF_DISABLE) ||
> + (param->awhb_sq_sw[2] != HWD_VIIF_ENABLE &&
> + param->awhb_sq_sw[2] != HWD_VIIF_DISABLE) ||
> + (param->awhb_sq_pol[0] != HWD_VIIF_ENABLE &&
> + param->awhb_sq_pol[0] != HWD_VIIF_DISABLE) ||
> + (param->awhb_sq_pol[1] != HWD_VIIF_ENABLE &&
> + param->awhb_sq_pol[1] != HWD_VIIF_DISABLE) ||
> + (param->awhb_sq_pol[2] != HWD_VIIF_ENABLE &&
> + param->awhb_sq_pol[2] != HWD_VIIF_DISABLE)) {
> + return -EINVAL;
> + }
> +
> + if (param->awhb_bycut0p > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_bycut0n > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_rycut0p > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_rycut0n > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_rbcut0h < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_rbcut0h > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_rbcut0l < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_rbcut0l > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_bycut_h[0] < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_bycut_h[0] > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_bycut_h[1] < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_bycut_h[1] > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_bycut_h[2] < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_bycut_h[2] > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_bycut_l[0] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_bycut_l[1] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_bycut_l[2] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_rycut_h[0] < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_rycut_h[0] > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_rycut_h[1] < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_rycut_h[1] > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_rycut_h[2] < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_rycut_h[2] > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_rycut_l[0] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_rycut_l[1] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_rycut_l[2] > HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> + param->awhb_awbsftu < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_awbsftu > HWD_VIIF_AWB_GATE_UPPER ||
> + param->awhb_awbsftv < HWD_VIIF_AWB_GATE_LOWER ||
> + param->awhb_awbsftv > HWD_VIIF_AWB_GATE_UPPER ||
> + (param->awhb_awbhuecor != HWD_VIIF_ENABLE &&
> + param->awhb_awbhuecor != HWD_VIIF_DISABLE)) {
> + return -EINVAL;
> + }
> +
> + if (param->awhb_awbspd > HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED ||
> + param->awhb_awbulv > HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL ||
> + param->awhb_awbvlv > HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL ||
> + param->awhb_awbondot > HWD_VIIF_AWB_INTEGRATION_STOP_TH) {
> + return -EINVAL;
> + }
> +
> + switch (param->awhb_awbfztim) {
> + case HWD_VIIF_L1_AWB_RESTART_NO:
> + case HWD_VIIF_L1_AWB_RESTART_128FRAME:
> + case HWD_VIIF_L1_AWB_RESTART_64FRAME:
> + case HWD_VIIF_L1_AWB_RESTART_32FRAME:
> + case HWD_VIIF_L1_AWB_RESTART_16FRAME:
> + case HWD_VIIF_L1_AWB_RESTART_8FRAME:
> + case HWD_VIIF_L1_AWB_RESTART_4FRAME:
> + case HWD_VIIF_L1_AWB_RESTART_2FRAME:
> + break;
> + default:
> + return -EINVAL;
> + }
> + }
> +
> + writel(awhb_wbmrg, &res->capture_reg->l1isp.L1_AWHB_WBMRG);
> + writel(awhb_wbmgg, &res->capture_reg->l1isp.L1_AWHB_WBMGG);
> + writel(awhb_wbmbg, &res->capture_reg->l1isp.L1_AWHB_WBMBG);
> +
> + val = readl(&res->capture_reg->l1isp.L1_AWHB_SW) & 0xffffff7fU;
> +
> + if (param) {
> + val |= (HWD_VIIF_ENABLE << 7U);
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
> +
> + if (param->awhb_ygate_data == 64U)
> + ygate_data = 0U;
> + else if (param->awhb_ygate_data == 128U)
> + ygate_data = 1U;
> + else if (param->awhb_ygate_data == 256U)
> + ygate_data = 2U;
> + else
> + ygate_data = 3U;
> +
> + val = (param->awhb_ygate_sel << 7U) | (ygate_data << 5U) | (param->awhb_cgrange);
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_GATE_CONF0);
> +
> + val = (param->awhb_ygatesw << 5U) | (param->awhb_hexsw << 4U) |
> + (param->awhb_areamode);
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_GATE_CONF1);
> +
> + writel(param->awhb_area_hsize, &res->capture_reg->l1isp.L1_AWHB_AREA_HSIZE);
> + writel(param->awhb_area_vsize, &res->capture_reg->l1isp.L1_AWHB_AREA_VSIZE);
> + writel(param->awhb_area_hofs, &res->capture_reg->l1isp.L1_AWHB_AREA_HOFS);
> + writel(param->awhb_area_vofs, &res->capture_reg->l1isp.L1_AWHB_AREA_VOFS);
> +
> + writel(param->awhb_area_maskh, &res->capture_reg->l1isp.L1_AWHB_AREA_MASKH);
> + writel(param->awhb_area_maskl, &res->capture_reg->l1isp.L1_AWHB_AREA_MASKL);
> +
> + val = (param->awhb_sq_sw[0] << 7U) | (param->awhb_sq_pol[0] << 6U) |
> + (param->awhb_sq_sw[1] << 5U) | (param->awhb_sq_pol[1] << 4U) |
> + (param->awhb_sq_sw[2] << 3U) | (param->awhb_sq_pol[2] << 2U);
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_SQ_CONF);
> +
> + writel((u32)param->awhb_ygateh, &res->capture_reg->l1isp.L1_AWHB_YGATEH);
> + writel((u32)param->awhb_ygatel, &res->capture_reg->l1isp.L1_AWHB_YGATEL);
> +
> + writel(param->awhb_bycut0p, &res->capture_reg->l1isp.L1_AWHB_BYCUT0P);
> + writel(param->awhb_bycut0n, &res->capture_reg->l1isp.L1_AWHB_BYCUT0N);
> + writel(param->awhb_rycut0p, &res->capture_reg->l1isp.L1_AWHB_RYCUT0P);
> + writel(param->awhb_rycut0n, &res->capture_reg->l1isp.L1_AWHB_RYCUT0N);
> +
> + val = (u32)param->awhb_rbcut0h & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_RBCUT0H);
> + val = (u32)param->awhb_rbcut0l & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_RBCUT0L);
> +
> + val = (u32)param->awhb_bycut_h[0] & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT1H);
> + writel(param->awhb_bycut_l[0], &res->capture_reg->l1isp.L1_AWHB_BYCUT1L);
> + val = (u32)param->awhb_bycut_h[1] & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT2H);
> + writel(param->awhb_bycut_l[1], &res->capture_reg->l1isp.L1_AWHB_BYCUT2L);
> + val = (u32)param->awhb_bycut_h[2] & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT3H);
> + writel(param->awhb_bycut_l[2], &res->capture_reg->l1isp.L1_AWHB_BYCUT3L);
> +
> + val = (u32)param->awhb_rycut_h[0] & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT1H);
> + writel(param->awhb_rycut_l[0], &res->capture_reg->l1isp.L1_AWHB_RYCUT1L);
> + val = (u32)param->awhb_rycut_h[1] & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT2H);
> + writel(param->awhb_rycut_l[1], &res->capture_reg->l1isp.L1_AWHB_RYCUT2L);
> + val = (u32)param->awhb_rycut_h[2] & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT3H);
> + writel(param->awhb_rycut_l[2], &res->capture_reg->l1isp.L1_AWHB_RYCUT3L);
> +
> + val = (u32)param->awhb_awbsftu & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSFTU);
> + val = (u32)param->awhb_awbsftv & 0xffU;
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSFTV);
> +
> + val = (param->awhb_awbhuecor << 4U) | (param->awhb_awbspd);
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSPD);
> +
> + writel(param->awhb_awbulv, &res->capture_reg->l1isp.L1_AWHB_AWBULV);
> + writel(param->awhb_awbvlv, &res->capture_reg->l1isp.L1_AWHB_AWBVLV);
> + writel((u32)param->awhb_awbwait, &res->capture_reg->l1isp.L1_AWHB_AWBWAIT);
> +
> + writel(param->awhb_awbondot, &res->capture_reg->l1isp.L1_AWHB_AWBONDOT);
> + writel(param->awhb_awbfztim, &res->capture_reg->l1isp.L1_AWHB_AWBFZTIM);
> +
> + writel((u32)param->awhb_wbgrmax, &res->capture_reg->l1isp.L1_AWHB_WBGRMAX);
> + writel((u32)param->awhb_wbgbmax, &res->capture_reg->l1isp.L1_AWHB_WBGBMAX);
> + writel((u32)param->awhb_wbgrmin, &res->capture_reg->l1isp.L1_AWHB_WBGRMIN);
> + writel((u32)param->awhb_wbgbmin, &res->capture_reg->l1isp.L1_AWHB_WBGBMIN);
> +
> + } else {
> + /* disable awb */
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_lock_awb_gain() - Configure L1ISP lock auto white balance gain.
> + *
> + * @enable: enable/disable lock AWB gain
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - "enable" is neither HWD_VIIF_ENABLE nor HWD_VIIF_DISABLE
> + */
> +s32 hwd_viif_l1_lock_awb_gain(struct hwd_viif_res *res, u32 enable)
> +{
> + u32 val;
> +
> + if (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
> + return -EINVAL;
> +
> + val = readl(&res->capture_reg->l1isp.L1_AWHB_SW) & 0xffffffdfU;
> + val |= (enable << 5U);
> + writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_hdrc() - Configure L1ISP HDR compression parameters.
> + *
> + * @param: pointer to HDR compression parameters
> + * @hdrc_thr_sft_amt: shift value in case of through mode [0..8]
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - each parameter of "param" is out of range
> + * - hdrc_thr_sft_amt is out of range when param is NULL
> + * - hdrc_thr_sft_amt is not 0 when param is not NULL
> + */
> +s32 hwd_viif_l1_set_hdrc(struct hwd_viif_res *res, const struct viif_l1_hdrc *param,
> + u32 hdrc_thr_sft_amt)
> +{
> + u32 val, sw_delay1;
> +
> + if (!param) {
> + if (hdrc_thr_sft_amt > HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL)
> + return -EINVAL;
> +
> + writel(hdrc_thr_sft_amt, &res->capture_reg->l1isp.L1_HDRC_THR_SFT_AMT);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_HDRC_EN);
> +
> + return 0;
> + }
> +
> + if (hdrc_thr_sft_amt != 0U || param->hdrc_ratio < HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH ||
> + param->hdrc_ratio > HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH ||
> + param->hdrc_pt_ratio > HWD_VIIF_L1_HDRC_MAX_PT_SLOPE ||
> + param->hdrc_pt_blend > HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
> + param->hdrc_pt_blend2 > HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
> + (param->hdrc_pt_blend + param->hdrc_pt_blend2) > HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
> + (param->hdrc_tn_type != HWD_VIIF_L1_HDRC_TONE_USER &&
> + param->hdrc_tn_type != HWD_VIIF_L1_HDRC_TONE_PRESET) ||
> + param->hdrc_flr_val > HWD_VIIF_L1_HDRC_MAX_FLARE_VAL ||
> + (param->hdrc_flr_adp != HWD_VIIF_ENABLE && param->hdrc_flr_adp != HWD_VIIF_DISABLE) ||
> + (param->hdrc_ybr_off != HWD_VIIF_ENABLE && param->hdrc_ybr_off != HWD_VIIF_DISABLE) ||
> + param->hdrc_orgy_blend > HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA) {
> + return -EINVAL;
> + }
> +
> + writel((param->hdrc_ratio - HWD_VIIF_L1_HDRC_RATIO_OFFSET),
> + &res->capture_reg->l1isp.L1_HDRC_RATIO);
> + writel(param->hdrc_pt_ratio, &res->capture_reg->l1isp.L1_HDRC_PT_RATIO);
> +
> + writel(param->hdrc_pt_blend, &res->capture_reg->l1isp.L1_HDRC_PT_BLEND);
> + writel(param->hdrc_pt_blend2, &res->capture_reg->l1isp.L1_HDRC_PT_BLEND2);
> +
> + writel(param->hdrc_pt_sat, &res->capture_reg->l1isp.L1_HDRC_PT_SAT);
> + writel(param->hdrc_tn_type, &res->capture_reg->l1isp.L1_HDRC_TN_TYPE);
> +
> + writel(param->hdrc_utn_tbl[0], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL0);
> + writel(param->hdrc_utn_tbl[1], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL1);
> + writel(param->hdrc_utn_tbl[2], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL2);
> + writel(param->hdrc_utn_tbl[3], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL3);
> + writel(param->hdrc_utn_tbl[4], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL4);
> + writel(param->hdrc_utn_tbl[5], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL5);
> + writel(param->hdrc_utn_tbl[6], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL6);
> + writel(param->hdrc_utn_tbl[7], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL7);
> + writel(param->hdrc_utn_tbl[8], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL8);
> + writel(param->hdrc_utn_tbl[9], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL9);
> + writel(param->hdrc_utn_tbl[10], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL10);
> + writel(param->hdrc_utn_tbl[11], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL11);
> + writel(param->hdrc_utn_tbl[12], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL12);
> + writel(param->hdrc_utn_tbl[13], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL13);
> + writel(param->hdrc_utn_tbl[14], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL14);
> + writel(param->hdrc_utn_tbl[15], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL15);
> + writel(param->hdrc_utn_tbl[16], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL16);
> + writel(param->hdrc_utn_tbl[17], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL17);
> + writel(param->hdrc_utn_tbl[18], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL18);
> + writel(param->hdrc_utn_tbl[19], &res->capture_reg->l1isp.L1_HDRC_UTN_TBL19);
> +
> + writel(param->hdrc_flr_val, &res->capture_reg->l1isp.L1_HDRC_FLR_VAL);
> + writel(param->hdrc_flr_adp, &res->capture_reg->l1isp.L1_HDRC_FLR_ADP);
> +
> + writel(param->hdrc_ybr_off, &res->capture_reg->l1isp.L1_HDRC_YBR_OFF);
> + writel(param->hdrc_orgy_blend, &res->capture_reg->l1isp.L1_HDRC_ORGY_BLEND);
> +
> + val = ((readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT)) % 64U) / 2U;
> + writel(val, &res->capture_reg->l1isp.L1_HDRC_MAR_TOP);
> + val = ((readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH)) % 64U) / 2U;
> + writel(val, &res->capture_reg->l1isp.L1_HDRC_MAR_LEFT);
> +
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_HDRC_EN);
> +
> + /* update of sw_delay1 must be done when MAIN unit is NOT running. */
> + if (!res->run_flag_main) {
> + sw_delay1 = (u32)((HWD_VIIF_REGBUF_ACCESS_TIME * (u64)res->pixel_clock) /
> + ((u64)res->htotal_size * HWD_VIIF_SYS_CLK)) +
> + HWD_VIIF_L1_DELAY_W_HDRC + 1U;
> + val = readl(&res->capture_reg->sys.INT_M1_LINE) & 0xffffU;
> + val |= (sw_delay1 << 16U);
> + writel(val, &res->capture_reg->sys.INT_M1_LINE);
> + /* M2_LINE is the same condition as M1_LINE */
> + writel(val, &res->capture_reg->sys.INT_M2_LINE);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_hdrc_ltm() - Configure L1ISP HDR compression local tone mapping parameters.
> + *
> + * @param: pointer to HDR compression local tone mapping parameters
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL
> + * - "param" is NULL
> + * - each parameter of "param" is out of range
> + */
> +s32 hwd_viif_l1_set_hdrc_ltm(struct hwd_viif_res *res, const struct viif_l1_hdrc_ltm_config *param)
> +{
> + u32 val;
> + u32 idx;
> +
> + if (!param || param->tnp_max >= HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO ||
> + param->tnp_mag >= HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION) {
> + return -EINVAL;
> + }
> +
> + val = (u32)param->tnp_fil[0];
> + for (idx = 1; idx < 5U; idx++)
> + val += (u32)param->tnp_fil[idx] * 2U;
> +
> + if (val != 1024U)
> + return -EINVAL;
> +
> + writel(param->tnp_max, &res->capture_reg->l1isp.L1_HDRC_TNP_MAX);
> +
> + writel(param->tnp_mag, &res->capture_reg->l1isp.L1_HDRC_TNP_MAG);
> +
> + writel((u32)param->tnp_fil[0], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL0);
> + writel((u32)param->tnp_fil[1], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL1);
> + writel((u32)param->tnp_fil[2], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL2);
> + writel((u32)param->tnp_fil[3], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL3);
> + writel((u32)param->tnp_fil[4], &res->capture_reg->l1isp.L1_HDRC_TNP_FIL4);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_gamma() - Configure L1ISP gamma correction parameters.
> + *
> + * @param: pointer to gamma correction parameters
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - each parameter of "param" is out of range
> + */
> +s32 hwd_viif_l1_set_gamma(struct hwd_viif_res *res, const struct viif_l1_gamma *param)
> +{
> + u32 idx;
> +
> + if (!param) {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_PGC_SW);
> + return 0;
> + }
> +
> + for (idx = 0; idx < 44U; idx++) {
> + if (param->gam_p[idx] > HWD_VIIF_L1_GAMMA_MAX_VAL)
> + return -EINVAL;
> + }
> +
> + writel(param->gam_p[0], &res->capture_reg->l1isp.L1_VPRO_GAM01P);
> + writel(param->gam_p[1], &res->capture_reg->l1isp.L1_VPRO_GAM02P);
> + writel(param->gam_p[2], &res->capture_reg->l1isp.L1_VPRO_GAM03P);
> + writel(param->gam_p[3], &res->capture_reg->l1isp.L1_VPRO_GAM04P);
> + writel(param->gam_p[4], &res->capture_reg->l1isp.L1_VPRO_GAM05P);
> + writel(param->gam_p[5], &res->capture_reg->l1isp.L1_VPRO_GAM06P);
> + writel(param->gam_p[6], &res->capture_reg->l1isp.L1_VPRO_GAM07P);
> + writel(param->gam_p[7], &res->capture_reg->l1isp.L1_VPRO_GAM08P);
> + writel(param->gam_p[8], &res->capture_reg->l1isp.L1_VPRO_GAM09P);
> + writel(param->gam_p[9], &res->capture_reg->l1isp.L1_VPRO_GAM10P);
> + writel(param->gam_p[10], &res->capture_reg->l1isp.L1_VPRO_GAM11P);
> + writel(param->gam_p[11], &res->capture_reg->l1isp.L1_VPRO_GAM12P);
> + writel(param->gam_p[12], &res->capture_reg->l1isp.L1_VPRO_GAM13P);
> + writel(param->gam_p[13], &res->capture_reg->l1isp.L1_VPRO_GAM14P);
> + writel(param->gam_p[14], &res->capture_reg->l1isp.L1_VPRO_GAM15P);
> + writel(param->gam_p[15], &res->capture_reg->l1isp.L1_VPRO_GAM16P);
> + writel(param->gam_p[16], &res->capture_reg->l1isp.L1_VPRO_GAM17P);
> + writel(param->gam_p[17], &res->capture_reg->l1isp.L1_VPRO_GAM18P);
> + writel(param->gam_p[18], &res->capture_reg->l1isp.L1_VPRO_GAM19P);
> + writel(param->gam_p[19], &res->capture_reg->l1isp.L1_VPRO_GAM20P);
> + writel(param->gam_p[20], &res->capture_reg->l1isp.L1_VPRO_GAM21P);
> + writel(param->gam_p[21], &res->capture_reg->l1isp.L1_VPRO_GAM22P);
> + writel(param->gam_p[22], &res->capture_reg->l1isp.L1_VPRO_GAM23P);
> + writel(param->gam_p[23], &res->capture_reg->l1isp.L1_VPRO_GAM24P);
> + writel(param->gam_p[24], &res->capture_reg->l1isp.L1_VPRO_GAM25P);
> + writel(param->gam_p[25], &res->capture_reg->l1isp.L1_VPRO_GAM26P);
> + writel(param->gam_p[26], &res->capture_reg->l1isp.L1_VPRO_GAM27P);
> + writel(param->gam_p[27], &res->capture_reg->l1isp.L1_VPRO_GAM28P);
> + writel(param->gam_p[28], &res->capture_reg->l1isp.L1_VPRO_GAM29P);
> + writel(param->gam_p[29], &res->capture_reg->l1isp.L1_VPRO_GAM30P);
> + writel(param->gam_p[30], &res->capture_reg->l1isp.L1_VPRO_GAM31P);
> + writel(param->gam_p[31], &res->capture_reg->l1isp.L1_VPRO_GAM32P);
> + writel(param->gam_p[32], &res->capture_reg->l1isp.L1_VPRO_GAM33P);
> + writel(param->gam_p[33], &res->capture_reg->l1isp.L1_VPRO_GAM34P);
> + writel(param->gam_p[34], &res->capture_reg->l1isp.L1_VPRO_GAM35P);
> + writel(param->gam_p[35], &res->capture_reg->l1isp.L1_VPRO_GAM36P);
> + writel(param->gam_p[36], &res->capture_reg->l1isp.L1_VPRO_GAM37P);
> + writel(param->gam_p[37], &res->capture_reg->l1isp.L1_VPRO_GAM38P);
> + writel(param->gam_p[38], &res->capture_reg->l1isp.L1_VPRO_GAM39P);
> + writel(param->gam_p[39], &res->capture_reg->l1isp.L1_VPRO_GAM40P);
> + writel(param->gam_p[40], &res->capture_reg->l1isp.L1_VPRO_GAM41P);
> + writel(param->gam_p[41], &res->capture_reg->l1isp.L1_VPRO_GAM42P);
> + writel(param->gam_p[42], &res->capture_reg->l1isp.L1_VPRO_GAM43P);
> + writel(param->gam_p[43], &res->capture_reg->l1isp.L1_VPRO_GAM44P);
> + writel(param->blkadj, &res->capture_reg->l1isp.L1_VPRO_BLKADJ);
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_PGC_SW);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_img_quality_adjustment() - Configure L1ISP image quality adjustment.
> + *
> + * @param: pointer to image quality adjustment parameters; NULL means disabling
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - each parameter of "param" is out of range
> + */
> +s32 hwd_viif_l1_set_img_quality_adjustment(struct hwd_viif_res *res,
> + const struct hwd_viif_l1_img_quality_adjustment *param)
> +{
> + u32 val;
> +
> + if (!param) {
> + /* disable all features when param is absent */
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_YUVC_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
> + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
> + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
> + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CNR_SW);
> +
> + return 0;
> + }
> +
> + if (param->lum_noise_reduction) {
> + if (param->lum_noise_reduction->gain_min > param->lum_noise_reduction->gain_max ||
> + param->lum_noise_reduction->lim_min > param->lum_noise_reduction->lim_max) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param->edge_enhancement) {
> + if (param->edge_enhancement->gain_min > param->edge_enhancement->gain_max ||
> + param->edge_enhancement->lim_min > param->edge_enhancement->lim_max ||
> + param->edge_enhancement->coring_min > param->edge_enhancement->coring_max) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param->uv_suppression) {
> + if (param->uv_suppression->bk_mp >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> + param->uv_suppression->black >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> + param->uv_suppression->wh_mp >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> + param->uv_suppression->white >= HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> + param->uv_suppression->bk_slv >= param->uv_suppression->wh_slv)
> + return -EINVAL;
> + }
> +
> + if (param->coring_suppression) {
> + if (param->coring_suppression->gain_min > param->coring_suppression->gain_max ||
> + param->coring_suppression->lv_min > param->coring_suppression->lv_max)
> + return -EINVAL;
> + }
> +
> + if (param->edge_suppression) {
> + if (param->edge_suppression->lim > HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT)
> + return -EINVAL;
> + }
> +
> + if (param->color_level) {
> + if (param->color_level->cb_gain >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> + param->color_level->cr_gain >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> + param->color_level->cbr_mgain_min >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> + param->color_level->cbp_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> + param->color_level->cbm_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> + param->color_level->crp_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> + param->color_level->crm_gain_max >= HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN) {
> + return -EINVAL;
> + }
> + }
> +
> + if (param->color_noise_reduction_enable != HWD_VIIF_ENABLE &&
> + param->color_noise_reduction_enable != HWD_VIIF_DISABLE) {
> + return -EINVAL;
> + }
> +
> + /* RGB to YUV */
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_YUVC_SW);
> + writel((u32)param->coef_cb, &res->capture_reg->l1isp.L1_VPRO_CB_MAT);
> + writel((u32)param->coef_cr, &res->capture_reg->l1isp.L1_VPRO_CR_MAT);
> +
> + /* brightness */
> + val = (u32)param->brightness & 0xffffU;
> + if (val != 0U) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
> + writel(val, &res->capture_reg->l1isp.L1_VPRO_BRIGHT);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
> + }
> +
> + /* linear contrast */
> + if ((u32)param->linear_contrast != 128U) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
> + writel((u32)param->linear_contrast, &res->capture_reg->l1isp.L1_VPRO_LCONT_LEV);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
> + }
> +
> + /* nonlinear contrast */
> + if (param->nonlinear_contrast) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
> + writel((u32)param->nonlinear_contrast->blk_knee,
> + &res->capture_reg->l1isp.L1_VPRO_BLK_KNEE);
> + writel((u32)param->nonlinear_contrast->wht_knee,
> + &res->capture_reg->l1isp.L1_VPRO_WHT_KNEE);
> +
> + writel((u32)param->nonlinear_contrast->blk_cont[0],
> + &res->capture_reg->l1isp.L1_VPRO_BLK_CONT0);
> + writel((u32)param->nonlinear_contrast->blk_cont[1],
> + &res->capture_reg->l1isp.L1_VPRO_BLK_CONT1);
> + writel((u32)param->nonlinear_contrast->blk_cont[2],
> + &res->capture_reg->l1isp.L1_VPRO_BLK_CONT2);
> +
> + writel((u32)param->nonlinear_contrast->wht_cont[0],
> + &res->capture_reg->l1isp.L1_VPRO_WHT_CONT0);
> + writel((u32)param->nonlinear_contrast->wht_cont[1],
> + &res->capture_reg->l1isp.L1_VPRO_WHT_CONT1);
> + writel((u32)param->nonlinear_contrast->wht_cont[2],
> + &res->capture_reg->l1isp.L1_VPRO_WHT_CONT2);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
> + }
> +
> + /* luminance noise reduction */
> + if (param->lum_noise_reduction) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
> + writel((u32)param->lum_noise_reduction->gain_min,
> + &res->capture_reg->l1isp.L1_VPRO_YNR_GAIN_MIN);
> + writel((u32)param->lum_noise_reduction->gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_YNR_GAIN_MAX);
> + writel((u32)param->lum_noise_reduction->lim_min,
> + &res->capture_reg->l1isp.L1_VPRO_YNR_LIM_MIN);
> + writel((u32)param->lum_noise_reduction->lim_max,
> + &res->capture_reg->l1isp.L1_VPRO_YNR_LIM_MAX);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
> + }
> +
> + /* edge enhancement */
> + if (param->edge_enhancement) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
> + writel((u32)param->edge_enhancement->gain_min,
> + &res->capture_reg->l1isp.L1_VPRO_ETE_GAIN_MIN);
> + writel((u32)param->edge_enhancement->gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_ETE_GAIN_MAX);
> + writel((u32)param->edge_enhancement->lim_min,
> + &res->capture_reg->l1isp.L1_VPRO_ETE_LIM_MIN);
> + writel((u32)param->edge_enhancement->lim_max,
> + &res->capture_reg->l1isp.L1_VPRO_ETE_LIM_MAX);
> + writel((u32)param->edge_enhancement->coring_min,
> + &res->capture_reg->l1isp.L1_VPRO_ETE_CORING_MIN);
> + writel((u32)param->edge_enhancement->coring_max,
> + &res->capture_reg->l1isp.L1_VPRO_ETE_CORING_MAX);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
> + }
> +
> + /* UV suppression */
> + if (param->uv_suppression) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
> + writel((u32)param->uv_suppression->bk_slv,
> + &res->capture_reg->l1isp.L1_VPRO_CSUP_BK_SLV);
> + writel(param->uv_suppression->bk_mp, &res->capture_reg->l1isp.L1_VPRO_CSUP_BK_MP);
> + writel(param->uv_suppression->black, &res->capture_reg->l1isp.L1_VPRO_CSUP_BLACK);
> +
> + writel((u32)param->uv_suppression->wh_slv,
> + &res->capture_reg->l1isp.L1_VPRO_CSUP_WH_SLV);
> + writel(param->uv_suppression->wh_mp, &res->capture_reg->l1isp.L1_VPRO_CSUP_WH_MP);
> + writel(param->uv_suppression->white, &res->capture_reg->l1isp.L1_VPRO_CSUP_WHITE);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
> + }
> +
> + /* coring suppression */
> + if (param->coring_suppression) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
> + writel((u32)param->coring_suppression->lv_min,
> + &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_LV_MIN);
> + writel((u32)param->coring_suppression->lv_max,
> + &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_LV_MAX);
> + writel((u32)param->coring_suppression->gain_min,
> + &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_GAIN_MIN);
> + writel((u32)param->coring_suppression->gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_GAIN_MAX);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
> + }
> +
> + /* edge suppression */
> + if (param->edge_suppression) {
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
> + writel((u32)param->edge_suppression->gain,
> + &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_GAIN);
> + writel((u32)param->edge_suppression->lim,
> + &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_LIM);
> + } else {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
> + }
> +
> + /* color level */
> + if (param->color_level) {
> + writel(param->color_level->cb_gain, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
> + writel(param->color_level->cr_gain, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
> + writel(param->color_level->cbr_mgain_min,
> + &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
> + writel(param->color_level->cbp_gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
> + writel(param->color_level->cbm_gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
> + writel(param->color_level->crp_gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
> + writel(param->color_level->crm_gain_max,
> + &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
> + } else {
> + /* disable */
> + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
> + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
> + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
> + writel(0U, &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
> + }
> +
> + /* color noise reduction */
> + writel(param->color_noise_reduction_enable, &res->capture_reg->l1isp.L1_VPRO_CNR_SW);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_avg_lum_generation() - Configure L1ISP average luminance generation parameters.
> + *
> + * @param: pointer to auto exposure parameters
> + * Return: 0 operation completed successfully
> + * Return: -EINVAL Parameter error
> + * - each parameter of "param" is out of range
> + */
> +s32 hwd_viif_l1_set_avg_lum_generation(struct hwd_viif_res *res,
> + const struct viif_l1_avg_lum_generation_config *param)
> +{
> + u32 idx, j;
> + u32 val;
> +
> + if (!param) {
> + writel(HWD_VIIF_DISABLE, &res->capture_reg->l1isp.L1_AEXP_ON);
> + return 0;
> + }
> +
> + val = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
> + if (param->aexp_start_x > (val - 1U))
> + return -EINVAL;
> +
> + if (param->aexp_block_width < HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH ||
> + param->aexp_block_width > val) {
> + return -EINVAL;
> + }
> + if (param->aexp_block_width % 64U)
> + return -EINVAL;
> +
> + val = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> + if (param->aexp_start_y > (val - 1U))
> + return -EINVAL;
> +
> + if (param->aexp_block_height < HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT ||
> + param->aexp_block_height > val) {
> + return -EINVAL;
> + }
> + if (param->aexp_block_height % 64U)
> + return -EINVAL;
> +
> + for (idx = 0; idx < 8U; idx++) {
> + for (j = 0; j < 8U; j++) {
> + if (param->aexp_weight[idx][j] > HWD_VIIF_L1_AEXP_MAX_WEIGHT)
> + return -EINVAL;
> + }
> + }
> +
> + if (param->aexp_satur_ratio > HWD_VIIF_L1_AEXP_MAX_BLOCK_TH ||
> + param->aexp_black_ratio > HWD_VIIF_L1_AEXP_MAX_BLOCK_TH ||
> + param->aexp_satur_level > HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH) {
> + return -EINVAL;
> + }
> +
> + for (idx = 0; idx < 4U; idx++) {
> + if (param->aexp_ave4linesy[idx] > (val - 4U))
> + return -EINVAL;
> + }
> +
> + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_AEXP_ON);
> + writel(param->aexp_start_x, &res->capture_reg->l1isp.L1_AEXP_START_X);
> + writel(param->aexp_start_y, &res->capture_reg->l1isp.L1_AEXP_START_Y);
> + writel(param->aexp_block_width, &res->capture_reg->l1isp.L1_AEXP_BLOCK_WIDTH);
> + writel(param->aexp_block_height, &res->capture_reg->l1isp.L1_AEXP_BLOCK_HEIGHT);
> +
> + val = (param->aexp_weight[0][0] << 14U) | (param->aexp_weight[0][1] << 12U) |
> + (param->aexp_weight[0][2] << 10U) | (param->aexp_weight[0][3] << 8U) |
> + (param->aexp_weight[0][4] << 6U) | (param->aexp_weight[0][5] << 4U) |
> + (param->aexp_weight[0][6] << 2U) | (param->aexp_weight[0][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_0);
> +
> + val = (param->aexp_weight[1][0] << 14U) | (param->aexp_weight[1][1] << 12U) |
> + (param->aexp_weight[1][2] << 10U) | (param->aexp_weight[1][3] << 8U) |
> + (param->aexp_weight[1][4] << 6U) | (param->aexp_weight[1][5] << 4U) |
> + (param->aexp_weight[1][6] << 2U) | (param->aexp_weight[1][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_1);
> +
> + val = (param->aexp_weight[2][0] << 14U) | (param->aexp_weight[2][1] << 12U) |
> + (param->aexp_weight[2][2] << 10U) | (param->aexp_weight[2][3] << 8U) |
> + (param->aexp_weight[2][4] << 6U) | (param->aexp_weight[2][5] << 4U) |
> + (param->aexp_weight[2][6] << 2U) | (param->aexp_weight[2][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_2);
> +
> + val = (param->aexp_weight[3][0] << 14U) | (param->aexp_weight[3][1] << 12U) |
> + (param->aexp_weight[3][2] << 10U) | (param->aexp_weight[3][3] << 8U) |
> + (param->aexp_weight[3][4] << 6U) | (param->aexp_weight[3][5] << 4U) |
> + (param->aexp_weight[3][6] << 2U) | (param->aexp_weight[3][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_3);
> +
> + val = (param->aexp_weight[4][0] << 14U) | (param->aexp_weight[4][1] << 12U) |
> + (param->aexp_weight[4][2] << 10U) | (param->aexp_weight[4][3] << 8U) |
> + (param->aexp_weight[4][4] << 6U) | (param->aexp_weight[4][5] << 4U) |
> + (param->aexp_weight[4][6] << 2U) | (param->aexp_weight[4][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_4);
> +
> + val = (param->aexp_weight[5][0] << 14U) | (param->aexp_weight[5][1] << 12U) |
> + (param->aexp_weight[5][2] << 10U) | (param->aexp_weight[5][3] << 8U) |
> + (param->aexp_weight[5][4] << 6U) | (param->aexp_weight[5][5] << 4U) |
> + (param->aexp_weight[5][6] << 2U) | (param->aexp_weight[5][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_5);
> +
> + val = (param->aexp_weight[6][0] << 14U) | (param->aexp_weight[6][1] << 12U) |
> + (param->aexp_weight[6][2] << 10U) | (param->aexp_weight[6][3] << 8U) |
> + (param->aexp_weight[6][4] << 6U) | (param->aexp_weight[6][5] << 4U) |
> + (param->aexp_weight[6][6] << 2U) | (param->aexp_weight[6][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_6);
> +
> + val = (param->aexp_weight[7][0] << 14U) | (param->aexp_weight[7][1] << 12U) |
> + (param->aexp_weight[7][2] << 10U) | (param->aexp_weight[7][3] << 8U) |
> + (param->aexp_weight[7][4] << 6U) | (param->aexp_weight[7][5] << 4U) |
> + (param->aexp_weight[7][6] << 2U) | (param->aexp_weight[7][7]);
> + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_7);
> +
> + writel(param->aexp_satur_ratio, &res->capture_reg->l1isp.L1_AEXP_SATUR_RATIO);
> + writel(param->aexp_black_ratio, &res->capture_reg->l1isp.L1_AEXP_BLACK_RATIO);
> + writel(param->aexp_satur_level, &res->capture_reg->l1isp.L1_AEXP_SATUR_LEVEL);
> +
> + writel(param->aexp_ave4linesy[0], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY0);
> + writel(param->aexp_ave4linesy[1], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY1);
> + writel(param->aexp_ave4linesy[2], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY2);
> + writel(param->aexp_ave4linesy[3], &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY3);
> +
> + return 0;
> +}
> +
> +/**
> + * hwd_viif_l1_set_irq_mask() - Set L1ISP interruption mask.
> + *
> + * @mask: mask setting
> + * Return: None
> + */
> +void hwd_viif_l1_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> +{
> + writel(mask, &res->capture_reg->l1isp.L1_CRGBF_ISP_INT_MASK);
> +}
> diff --git a/drivers/media/platform/visconti/viif_controls.c b/drivers/media/platform/visconti/viif_controls.c
> new file mode 100644
> index 00000000000..2793fb0a807
> --- /dev/null
> +++ b/drivers/media/platform/visconti/viif_controls.c
> @@ -0,0 +1,1153 @@
> +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +/* Toshiba Visconti Video Capture Support
> + *
> + * (C) Copyright 2022 TOSHIBA CORPORATION
> + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/pm_runtime.h>
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-subdev.h>
> +
> +#include "viif.h"
> +
> +static int viif_main_set_rawpack_mode(struct viif_device *viif_dev, u32 *rawpack)
> +{
> + if (vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
> + return -EBUSY;
> +
> + if (*rawpack == VIIF_RAWPACK_DISABLE) {
> + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_DISABLE;
> + return 0;
> + }
> + if (*rawpack == VIIF_RAWPACK_MSBFIRST) {
> + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_MSBFIRST;
> + return 0;
> + }
> + if (*rawpack == VIIF_RAWPACK_LSBFIRST) {
> + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_LSBFIRST;
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int viif_l1_set_input_mode(struct viif_device *viif_dev,
> + struct viif_l1_input_mode_config *input_mode)
> +{
> + u32 mode, raw_color_filter;
> + unsigned long irqflags;
> + int ret;
> +
> + /* SDR input is not supported */
> + if (input_mode->mode == VIIF_L1_INPUT_HDR)
> + mode = HWD_VIIF_L1_INPUT_HDR;
> + else if (input_mode->mode == VIIF_L1_INPUT_PWL)
> + mode = HWD_VIIF_L1_INPUT_PWL;
> + else if (input_mode->mode == VIIF_L1_INPUT_HDR_IMG_CORRECT)
> + mode = HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT;
> + else if (input_mode->mode == VIIF_L1_INPUT_PWL_IMG_CORRECT)
> + mode = HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT;
> + else
> + return -EINVAL;
> +
> + if (input_mode->raw_color_filter == VIIF_L1_RAW_GR_R_B_GB)
> + raw_color_filter = HWD_VIIF_L1_RAW_GR_R_B_GB;
> + else if (input_mode->raw_color_filter == VIIF_L1_RAW_R_GR_GB_B)
> + raw_color_filter = HWD_VIIF_L1_RAW_R_GR_GB_B;
> + else if (input_mode->raw_color_filter == VIIF_L1_RAW_B_GB_GR_R)
> + raw_color_filter = HWD_VIIF_L1_RAW_B_GB_GR_R;
> + else if (input_mode->raw_color_filter == VIIF_L1_RAW_GB_B_R_GR)
> + raw_color_filter = HWD_VIIF_L1_RAW_GB_B_R_GR;
> + else
> + return -EINVAL;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_input_mode(viif_dev->hwd_res, mode, input_mode->depth,
> + raw_color_filter);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_rgb_to_y_coef(struct viif_device *viif_dev,
> + struct viif_l1_rgb_to_y_coef_config *l1_rgb_to_y_coef)
> +{
> + int ret;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_rgb_to_y_coef(viif_dev->hwd_res, l1_rgb_to_y_coef->coef_r,
> + l1_rgb_to_y_coef->coef_g, l1_rgb_to_y_coef->coef_b);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_ag_mode(struct viif_device *viif_dev,
> + struct viif_l1_ag_mode_config *l1_ag_mode)
> +{
> + int ret;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_ag_mode(viif_dev->hwd_res, l1_ag_mode);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_ag(struct viif_device *viif_dev, struct viif_l1_ag_config *l1_ag)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_ag(viif_dev->hwd_res, l1_ag->gain_h, l1_ag->gain_m, l1_ag->gain_l);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_hdre(struct viif_device *viif_dev, struct viif_l1_hdre_config *l1_hdre)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_hdre(viif_dev->hwd_res, l1_hdre);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_img_extraction(struct viif_device *viif_dev,
> + struct viif_l1_img_extraction_config *img_extract)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_img_extraction(viif_dev->hwd_res, img_extract->input_black_gr,
> + img_extract->input_black_r, img_extract->input_black_b,
> + img_extract->input_black_gb);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192
> +static int viif_l1_set_dpc(struct viif_device *viif_dev, struct viif_l1_dpc_config *l1_dpc)
> +{
> + uintptr_t table_h_paddr = 0;
> + uintptr_t table_m_paddr = 0;
> + uintptr_t table_l_paddr = 0;
> + unsigned long irqflags;
> + int ret;
> +
> + if (l1_dpc->table_h_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
> + u64_to_user_ptr(l1_dpc->table_h_addr),
> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> + return -EFAULT;
NACK!
I thought those addresses in a struct were iffy. This is not supported, it
basically bypasses the whole control framework.
The way to do this is to create separate array controls for these tables.
And table_h_addr becomes a simple 0 or 1 value, indicating whether to use
the table set by that control. For small arrays it is also an option to
embed them in the control structure.
Are these l, h and m tables independent from one another? I.e. is it possible
to set l but not h and m? I suspect it is all or nothing, and in that case you
need only a single control to set all three tables (a two dimensional array).
Anyway, the same issue applies to all the controls were you pass addresses for
tables, that all needs to change.
> + table_h_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_h;
> + }
> + if (l1_dpc->table_m_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_m,
> + u64_to_user_ptr(l1_dpc->table_m_addr),
> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> + return -EFAULT;
> + table_m_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_m;
> + }
> + if (l1_dpc->table_l_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_l,
> + u64_to_user_ptr(l1_dpc->table_l_addr),
> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> + return -EFAULT;
> + table_l_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_l;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_dpc_table_transmission(viif_dev->hwd_res, table_h_paddr,
> + table_m_paddr, table_l_paddr);
> + if (ret)
> + goto err;
> +
> + ret = hwd_viif_l1_set_dpc(viif_dev->hwd_res, &l1_dpc->param_h, &l1_dpc->param_m,
> + &l1_dpc->param_l);
> +
> +err:
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> + return ret;
> +}
> +
> +static int
> +viif_l1_set_preset_white_balance(struct viif_device *viif_dev,
> + struct viif_l1_preset_white_balance_config *l1_preset_wb)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_preset_white_balance(viif_dev->hwd_res, l1_preset_wb->dstmaxval,
> + &l1_preset_wb->param_h, &l1_preset_wb->param_m,
> + &l1_preset_wb->param_l);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int
> +viif_l1_set_raw_color_noise_reduction(struct viif_device *viif_dev,
> + struct viif_l1_raw_color_noise_reduction_config *raw_color)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_raw_color_noise_reduction(viif_dev->hwd_res, &raw_color->param_h,
> + &raw_color->param_m, &raw_color->param_l);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_hdrs(struct viif_device *viif_dev, struct viif_l1_hdrs_config *hdrs)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_hdrs(viif_dev->hwd_res, hdrs);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_black_level_correction(struct viif_device *viif_dev,
> + struct viif_l1_black_level_correction_config *blc)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_black_level_correction(viif_dev->hwd_res, blc);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +#define VISCONTI_VIIF_LSC_TABLE_BYTES 1536
> +
> +static int viif_l1_set_lsc(struct viif_device *viif_dev, struct viif_l1_lsc_config *l1_lsc)
> +{
> + struct viif_l1_lsc_parabola_param lsc_para;
> + struct viif_l1_lsc_grid_param lsc_grid;
> + struct hwd_viif_l1_lsc hwd_params;
> + struct viif_l1_lsc lsc_params;
> + uintptr_t table_gr_paddr = 0;
> + uintptr_t table_gb_paddr = 0;
> + uintptr_t table_r_paddr = 0;
> + uintptr_t table_b_paddr = 0;
> + unsigned long irqflags;
> + int ret;
> +
> + if (!l1_lsc->param_addr) {
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_lsc(viif_dev->hwd_res, NULL);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> + return ret;
> + }
> +
> + if (l1_lsc->table_gr_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->lsc_table_gr,
> + u64_to_user_ptr(l1_lsc->table_gr_addr),
> + VISCONTI_VIIF_LSC_TABLE_BYTES))
> + return -EFAULT;
> + table_gr_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_gr;
> + }
> + if (l1_lsc->table_r_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->lsc_table_r,
> + u64_to_user_ptr(l1_lsc->table_r_addr),
> + VISCONTI_VIIF_LSC_TABLE_BYTES))
> + return -EFAULT;
> + table_r_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_r;
> + }
> + if (l1_lsc->table_b_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->lsc_table_b,
> + u64_to_user_ptr(l1_lsc->table_b_addr),
> + VISCONTI_VIIF_LSC_TABLE_BYTES))
> + return -EFAULT;
> + table_b_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_b;
> + }
> + if (l1_lsc->table_gb_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->lsc_table_gb,
> + u64_to_user_ptr(l1_lsc->table_gb_addr),
> + VISCONTI_VIIF_LSC_TABLE_BYTES))
> + return -EFAULT;
> + table_gb_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_gb;
> + }
> +
> + if (copy_from_user(&lsc_params, u64_to_user_ptr(l1_lsc->param_addr),
> + sizeof(struct viif_l1_lsc)))
> + return -EFAULT;
> +
> + hwd_params.lssc_parabola_param = NULL;
> + hwd_params.lssc_grid_param = NULL;
> +
> + if (lsc_params.lssc_parabola_param_addr) {
> + if (copy_from_user(&lsc_para, u64_to_user_ptr(lsc_params.lssc_parabola_param_addr),
> + sizeof(struct viif_l1_lsc_parabola_param)))
> + return -EFAULT;
> + hwd_params.lssc_parabola_param = &lsc_para;
> + }
> +
> + if (lsc_params.lssc_grid_param_addr) {
> + if (copy_from_user(&lsc_grid, u64_to_user_ptr(lsc_params.lssc_grid_param_addr),
> + sizeof(struct viif_l1_lsc_grid_param)))
> + return -EFAULT;
> + hwd_params.lssc_grid_param = &lsc_grid;
> + }
> +
> + hwd_params.lssc_pwhb_r_gain_max = lsc_params.lssc_pwhb_r_gain_max;
> + hwd_params.lssc_pwhb_r_gain_min = lsc_params.lssc_pwhb_r_gain_min;
> + hwd_params.lssc_pwhb_gr_gain_max = lsc_params.lssc_pwhb_gr_gain_max;
> + hwd_params.lssc_pwhb_gr_gain_min = lsc_params.lssc_pwhb_gr_gain_min;
> + hwd_params.lssc_pwhb_gb_gain_max = lsc_params.lssc_pwhb_gb_gain_max;
> + hwd_params.lssc_pwhb_gb_gain_min = lsc_params.lssc_pwhb_gb_gain_min;
> + hwd_params.lssc_pwhb_b_gain_max = lsc_params.lssc_pwhb_b_gain_max;
> + hwd_params.lssc_pwhb_b_gain_min = lsc_params.lssc_pwhb_b_gain_min;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_lsc_table_transmission(viif_dev->hwd_res, table_gr_paddr,
> + table_r_paddr, table_b_paddr, table_gb_paddr);
> + if (ret)
> + goto err;
> +
> + ret = hwd_viif_l1_set_lsc(viif_dev->hwd_res, &hwd_params);
> +err:
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_main_process(struct viif_device *viif_dev,
> + struct viif_l1_main_process_config *mpro)
> +{
> + struct viif_l1_color_matrix_correction color_matrix;
> + unsigned long irqflags;
> + int ret;
> +
> + if (mpro->param_addr) {
> + if (copy_from_user(&color_matrix, u64_to_user_ptr(mpro->param_addr),
> + sizeof(struct viif_l1_color_matrix_correction)))
> + return -EFAULT;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_main_process(viif_dev->hwd_res, mpro->demosaic_mode,
> + mpro->damp_lsbsel,
> + mpro->param_addr ? &color_matrix : NULL,
> + mpro->dst_maxval);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_awb(struct viif_device *viif_dev, struct viif_l1_awb_config *l1_awb)
> +{
> + struct viif_l1_awb param;
> + unsigned long irqflags;
> + int ret;
> +
> + if (l1_awb->param_addr) {
> + if (copy_from_user(¶m, u64_to_user_ptr(l1_awb->param_addr),
> + sizeof(struct viif_l1_awb)))
> + return -EFAULT;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_awb(viif_dev->hwd_res, l1_awb->param_addr ? ¶m : NULL,
> + l1_awb->awhb_wbmrg, l1_awb->awhb_wbmgg, l1_awb->awhb_wbmbg);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_lock_awb_gain(struct viif_device *viif_dev, u32 *enable)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_lock_awb_gain(viif_dev->hwd_res, *enable);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_hdrc(struct viif_device *viif_dev, struct viif_l1_hdrc_config *hdrc)
> +{
> + struct viif_l1_hdrc param;
> + unsigned long irqflags;
> + int ret;
> +
> + if (hdrc->param_addr) {
> + if (copy_from_user(¶m, u64_to_user_ptr(hdrc->param_addr),
> + sizeof(struct viif_l1_hdrc)))
> + return -EFAULT;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_hdrc(viif_dev->hwd_res, hdrc->param_addr ? ¶m : NULL,
> + hdrc->hdrc_thr_sft_amt);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_hdrc_ltm(struct viif_device *viif_dev,
> + struct viif_l1_hdrc_ltm_config *l1_hdrc_ltm)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_hdrc_ltm(viif_dev->hwd_res, l1_hdrc_ltm);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_gamma(struct viif_device *viif_dev, struct viif_l1_gamma_config *l1_gamma)
> +{
> + struct viif_l1_gamma param;
> + unsigned long irqflags;
> + int ret;
> +
> + if (l1_gamma->param_addr) {
> + if (copy_from_user(¶m, u64_to_user_ptr(l1_gamma->param_addr),
> + sizeof(struct viif_l1_gamma)))
> + return -EFAULT;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_gamma(viif_dev->hwd_res, l1_gamma->param_addr ? ¶m : NULL);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int
> +viif_l1_set_img_quality_adjustment(struct viif_device *viif_dev,
> + struct viif_l1_img_quality_adjustment_config *img_quality)
> +{
> + struct hwd_viif_l1_img_quality_adjustment hwd_img_quality;
> + struct viif_l1_lum_noise_reduction lum_noise;
> + struct viif_l1_nonlinear_contrast nonlinear;
> + struct viif_l1_coring_suppression coring;
> + struct viif_l1_edge_enhancement edge_enh;
> + struct viif_l1_edge_suppression edge_sup;
> + struct viif_l1_uv_suppression uv;
> + struct viif_l1_color_level color;
> + unsigned long irqflags;
> + int ret;
> +
> + hwd_img_quality.coef_cb = img_quality->coef_cb;
> + hwd_img_quality.coef_cr = img_quality->coef_cr;
> + hwd_img_quality.brightness = img_quality->brightness;
> + hwd_img_quality.linear_contrast = img_quality->linear_contrast;
> + hwd_img_quality.color_noise_reduction_enable = img_quality->color_noise_reduction_enable;
> +
> + if (img_quality->nonlinear_contrast_addr) {
> + if (copy_from_user(&nonlinear,
> + u64_to_user_ptr(img_quality->nonlinear_contrast_addr),
> + sizeof(struct viif_l1_nonlinear_contrast)))
> + return -EFAULT;
> + hwd_img_quality.nonlinear_contrast = &nonlinear;
> + } else {
> + hwd_img_quality.nonlinear_contrast = NULL;
> + }
> + if (img_quality->lum_noise_reduction_addr) {
> + if (copy_from_user(&lum_noise,
> + u64_to_user_ptr(img_quality->lum_noise_reduction_addr),
> + sizeof(struct viif_l1_lum_noise_reduction)))
> + return -EFAULT;
> + hwd_img_quality.lum_noise_reduction = &lum_noise;
> + } else {
> + hwd_img_quality.lum_noise_reduction = NULL;
> + }
> + if (img_quality->edge_enhancement_addr) {
> + if (copy_from_user(&edge_enh, u64_to_user_ptr(img_quality->edge_enhancement_addr),
> + sizeof(struct viif_l1_edge_enhancement)))
> + return -EFAULT;
> + hwd_img_quality.edge_enhancement = &edge_enh;
> + } else {
> + hwd_img_quality.edge_enhancement = NULL;
> + }
> + if (img_quality->uv_suppression_addr) {
> + if (copy_from_user(&uv, u64_to_user_ptr(img_quality->uv_suppression_addr),
> + sizeof(struct viif_l1_uv_suppression)))
> + return -EFAULT;
> + hwd_img_quality.uv_suppression = &uv;
> + } else {
> + hwd_img_quality.uv_suppression = NULL;
> + }
> + if (img_quality->coring_suppression_addr) {
> + if (copy_from_user(&coring, u64_to_user_ptr(img_quality->coring_suppression_addr),
> + sizeof(struct viif_l1_coring_suppression)))
> + return -EFAULT;
> + hwd_img_quality.coring_suppression = &coring;
> + } else {
> + hwd_img_quality.coring_suppression = NULL;
> + }
> + if (img_quality->edge_suppression_addr) {
> + if (copy_from_user(&edge_sup, u64_to_user_ptr(img_quality->edge_suppression_addr),
> + sizeof(struct viif_l1_edge_suppression)))
> + return -EFAULT;
> + hwd_img_quality.edge_suppression = &edge_sup;
> + } else {
> + hwd_img_quality.edge_suppression = NULL;
> + }
> + if (img_quality->color_level_addr) {
> + if (copy_from_user(&color, u64_to_user_ptr(img_quality->color_level_addr),
> + sizeof(struct viif_l1_color_level)))
> + return -EFAULT;
> + hwd_img_quality.color_level = &color;
> + } else {
> + hwd_img_quality.color_level = NULL;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_img_quality_adjustment(viif_dev->hwd_res, &hwd_img_quality);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +static int viif_l1_set_avg_lum_generation(struct viif_device *viif_dev,
> + struct viif_l1_avg_lum_generation_config *l1_avg_lum)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l1_set_avg_lum_generation(viif_dev->hwd_res, l1_avg_lum);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + return ret;
> +}
> +
> +#define VISCONTI_VIIF_DPC_TABLE_SIZE_MIN 1024
> +#define VISCONTI_VIIF_DPC_TABLE_SIZE_MAX 8192
> +static int viif_l2_set_undist(struct viif_device *viif_dev, struct viif_l2_undist_config *undist)
> +{
> + uintptr_t table_write_g_paddr = 0;
> + uintptr_t table_read_b_paddr = 0;
> + uintptr_t table_read_g_paddr = 0;
> + uintptr_t table_read_r_paddr = 0;
> + unsigned long irqflags;
> + int ret;
> +
> + if ((undist->size && undist->size < VISCONTI_VIIF_DPC_TABLE_SIZE_MIN) ||
> + undist->size > VISCONTI_VIIF_DPC_TABLE_SIZE_MAX)
> + return -EINVAL;
> +
> + if (undist->write_g_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->undist_write_g,
> + u64_to_user_ptr(undist->write_g_addr), undist->size))
> + return -EFAULT;
> + table_write_g_paddr = (uintptr_t)viif_dev->table_paddr->undist_write_g;
> + }
> + if (undist->read_b_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->undist_read_b,
> + u64_to_user_ptr(undist->read_b_addr), undist->size))
> + return -EFAULT;
> + table_read_b_paddr = (uintptr_t)viif_dev->table_paddr->undist_read_b;
> + }
> + if (undist->read_g_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->undist_read_g,
> + u64_to_user_ptr(undist->read_g_addr), undist->size))
> + return -EFAULT;
> + table_read_g_paddr = (uintptr_t)viif_dev->table_paddr->undist_read_g;
> + }
> + if (undist->read_r_addr) {
> + if (copy_from_user(viif_dev->table_vaddr->undist_read_r,
> + u64_to_user_ptr(undist->read_r_addr), undist->size))
> + return -EFAULT;
> + table_read_r_paddr = (uintptr_t)viif_dev->table_paddr->undist_read_r;
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l2_set_undist_table_transmission(viif_dev->hwd_res, table_write_g_paddr,
> + table_read_b_paddr, table_read_g_paddr,
> + table_read_r_paddr, undist->size);
> + if (ret) {
> + dev_err(viif_dev->dev, "l2_set_undist_table_transmission error. %d\n", ret);
> + goto err;
> + }
> +
> + ret = hwd_viif_l2_set_undist(viif_dev->hwd_res, &undist->param);
> +
> +err:
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> + return ret;
> +}
> +
> +static int viif_l2_set_roi(struct viif_device *viif_dev, struct viif_l2_roi_config *roi)
> +{
> + unsigned long irqflags;
> + int ret;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l2_set_roi(viif_dev->hwd_res, roi);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> + return ret;
> +}
> +
> +static int viif_l2_set_roi_wrap(struct viif_device *viif_dev, struct viif_l2_roi_config *roi)
> +{
> + int ret;
> +
> + ret = viif_l2_set_roi(viif_dev, roi);
> + if (!ret)
> + visconti_viif_isp_set_compose_rect(viif_dev, roi);
> +
> + return ret;
> +}
> +
> +#define VISCONTI_VIIF_GANMMA_TABLE_SIZE 512
> +static int viif_l2_set_gamma(struct viif_device *viif_dev, struct viif_l2_gamma_config *l2_gamma)
> +{
> + struct hwd_viif_l2_gamma_table hwd_table = { 0 };
> + int pathid = l2_gamma->pathid;
> + unsigned long irqflags;
> + int postid;
> + int ret;
> + u32 i;
> +
> + if (pathid == CAPTURE_PATH_MAIN_POST0)
> + postid = VIIF_L2ISP_POST_0;
> + else if (pathid == CAPTURE_PATH_MAIN_POST1)
> + postid = VIIF_L2ISP_POST_1;
> + else
> + return -EINVAL;
> +
> + for (i = 0; i < 6; i++) {
> + if (l2_gamma->table_addr[i]) {
> + if (copy_from_user(viif_dev->table_vaddr->l2_gamma_table[pathid][i],
> + u64_to_user_ptr(l2_gamma->table_addr[i]),
> + VISCONTI_VIIF_GANMMA_TABLE_SIZE))
> + return -EFAULT;
> + hwd_table.table[i] =
> + (uintptr_t)viif_dev->table_paddr->l2_gamma_table[pathid][i];
> + }
> + }
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + ret = hwd_viif_l2_set_gamma_table_transmission(viif_dev->hwd_res, postid, &hwd_table);
> + if (ret)
> + goto err;
> +
> + ret = hwd_viif_l2_set_gamma(viif_dev->hwd_res, postid, l2_gamma->enable, l2_gamma->vsplit,
> + l2_gamma->mode);
> +err:
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> + return ret;
> +}
> +
> +static int
> +viif_csi2rx_get_calibration_status(struct viif_device *viif_dev,
> + struct viif_csi2rx_dphy_calibration_status *calibration_status)
> +{
> + int ret;
> +
> + if (!vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
> + return -EIO;
EIO is definitely the wrong error code since that indicates a HW issue, and
that's not the case. Do you need to return an error here? Is there a reasonable
calibration status that you can return instead?
Presumably if it is not streaming, then that means 'uncalibrated', so perhaps
returning an 'uncalibrated' status here makes the more sense.
Also, I suspect you actually mean vb2_start_streaming_called() here. I assume
that the calibration step happens in start_streaming() which can be called later
than VIDIOC_STREAMON (which is the ioctl that sets 'is streaming' to true).
> +
> + ret = hwd_viif_csi2rx_get_calibration_status(viif_dev->hwd_res, calibration_status);
> +
> + return ret;
> +}
> +
> +static int viif_csi2rx_get_err_status(struct viif_device *viif_dev,
> + struct viif_csi2rx_err_status *csi_err)
> +{
> + int ret;
> +
> + if (!vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
> + return -EIO;
> +
> + ret = hwd_viif_csi2rx_get_err_status(viif_dev->hwd_res, &csi_err->err_phy_fatal,
> + &csi_err->err_pkt_fatal, &csi_err->err_frame_fatal,
> + &csi_err->err_phy, &csi_err->err_pkt,
> + &csi_err->err_line);
> +
> + return ret;
> +}
> +
> +static int viif_isp_get_last_capture_status(struct viif_device *viif_dev,
> + struct viif_isp_capture_status *status)
> +{
> + struct hwd_viif_l1_info l1_info;
> + unsigned long irqflags;
> + int i, j;
> +
> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> + hwd_viif_isp_get_info(viif_dev->hwd_res, &l1_info, NULL);
> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> +
> + status->l1_info.avg_lum_weight = l1_info.avg_lum_weight;
> + for (i = 0; i < 8; i++) {
> + for (j = 0; j < 8; j++)
> + status->l1_info.avg_lum_block[i][j] = l1_info.avg_lum_block[i][j];
> + }
> + for (i = 0; i < 4; i++)
> + status->l1_info.avg_lum_four_line_lum[i] = l1_info.avg_lum_four_line_lum[i];
> +
> + status->l1_info.avg_satur_pixnum = l1_info.avg_satur_pixnum;
> + status->l1_info.avg_black_pixnum = l1_info.avg_black_pixnum;
> + status->l1_info.awb_ave_u = l1_info.awb_ave_u;
> + status->l1_info.awb_ave_v = l1_info.awb_ave_v;
> + status->l1_info.awb_accumulated_pixel = l1_info.awb_accumulated_pixel;
> + status->l1_info.awb_gain_r = l1_info.awb_gain_r;
> + status->l1_info.awb_gain_g = l1_info.awb_gain_g;
> + status->l1_info.awb_gain_b = l1_info.awb_gain_b;
> + status->l1_info.awb_status_u = l1_info.awb_status_u;
> + status->l1_info.awb_status_v = l1_info.awb_status_v;
> +
> + return 0;
> +}
> +
> +static int viif_isp_get_reported_errors(struct viif_device *viif_dev,
> + struct viif_reported_errors *status)
> +{
> + status->main = viif_dev->reported_err_main;
> + status->sub = viif_dev->reported_err_sub;
> + status->csi2rx = viif_dev->reported_err_csi2rx;
> + viif_dev->reported_err_main = 0;
> + viif_dev->reported_err_sub = 0;
> + viif_dev->reported_err_csi2rx = 0;
> +
> + return 0;
> +}
> +
> +/* ===== v4l2 subdevice control handlers ===== */
> +#define COMPOUND_TYPE_SAMPLE01 0x0280
> +
> +static int visconti_viif_isp_set_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + struct viif_device *viif_dev = ctrl->priv;
> +
> + pr_info("isp_set_ctrl: %s", ctrl->name);
> + if (pm_runtime_status_suspended(viif_dev->dev)) {
> + pr_info("warning: visconti viif HW is not powered");
> + return 0;
> + }
> +
> + switch (ctrl->id) {
> + case V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE:
> + return viif_main_set_rawpack_mode(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE:
> + return viif_l1_set_input_mode(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF:
> + return viif_l1_set_rgb_to_y_coef(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE:
> + return viif_l1_set_ag_mode(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG:
> + return viif_l1_set_ag(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE:
> + return viif_l1_set_hdre(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION:
> + return viif_l1_set_img_extraction(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC:
> + return viif_l1_set_dpc(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE:
> + return viif_l1_set_preset_white_balance(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION:
> + return viif_l1_set_raw_color_noise_reduction(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS:
> + return viif_l1_set_hdrs(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION:
> + return viif_l1_set_black_level_correction(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC:
> + return viif_l1_set_lsc(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS:
> + return viif_l1_set_main_process(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB:
> + return viif_l1_set_awb(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN:
> + return viif_l1_lock_awb_gain(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC:
> + return viif_l1_set_hdrc(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM:
> + return viif_l1_set_hdrc_ltm(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA:
> + return viif_l1_set_gamma(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT:
> + return viif_l1_set_img_quality_adjustment(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION:
> + return viif_l1_set_avg_lum_generation(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST:
> + return viif_l2_set_undist(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI:
> + return viif_l2_set_roi_wrap(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA:
> + return viif_l2_set_gamma(viif_dev, ctrl->p_new.p);
> + default:
> + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
> + break;
> + }
> + return 0;
> +}
> +
> +static int visconti_viif_isp_get_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + struct viif_device *viif_dev = ctrl->priv;
> +
> + pr_info("isp_get_ctrl: %s", ctrl->name);
> + if (pm_runtime_status_suspended(viif_dev->dev)) {
> + pr_info("warning: visconti viif HW is not powered");
> + return 0;
> + }
> +
> + switch (ctrl->id) {
> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
> + return viif_csi2rx_get_calibration_status(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
> + return viif_csi2rx_get_err_status(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
> + return viif_isp_get_last_capture_status(viif_dev, ctrl->p_new.p);
> + case V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
> + return viif_isp_get_reported_errors(viif_dev, ctrl->p_new.p);
My question for these four controls is: are these really volatile controls?
A volatile control means that the hardware can change the registers at any
time without telling the CPU about it via an interrupt or some similar mechanism.
If there *is* such a mechanism, then it is not a volatile control, instead the
driver has to update the control value whenever the HW informs it about the
new value.
I can't tell, so that's why I ask here to double check.
> + default:
> + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
> + break;
> + }
> + return 0;
> +}
> +
> +/* ===== register v4l2 subdevice controls ===== */
> +static bool visconti_viif_isp_custom_ctrl_equal(const struct v4l2_ctrl *ctrl,
> + union v4l2_ctrl_ptr ptr1, union v4l2_ctrl_ptr ptr2)
> +{
> + return !memcmp(ptr1.p_const, ptr2.p_const, ctrl->elem_size);
> +}
> +
> +static void visconti_viif_isp_custom_ctrl_init(const struct v4l2_ctrl *ctrl, u32 idx,
> + union v4l2_ctrl_ptr ptr)
> +{
> + if (ctrl->p_def.p_const)
> + memcpy(ptr.p, ctrl->p_def.p_const, ctrl->elem_size);
> + else
> + memset(ptr.p, 0, ctrl->elem_size);
> +}
> +
> +static void visconti_viif_isp_custom_ctrl_log(const struct v4l2_ctrl *ctrl)
> +{
> +}
> +
> +static int visconti_viif_isp_custom_ctrl_validate(const struct v4l2_ctrl *ctrl,
> + union v4l2_ctrl_ptr ptr)
> +{
> + pr_info("std_validate: %s", ctrl->name);
> + return 0;
> +}
> +
> +static const struct v4l2_ctrl_type_ops custom_type_ops = {
> + .equal = visconti_viif_isp_custom_ctrl_equal,
> + .init = visconti_viif_isp_custom_ctrl_init,
> + .log = visconti_viif_isp_custom_ctrl_log,
> + .validate = visconti_viif_isp_custom_ctrl_validate,
> +};
This is not needed, it's not doing anything that the control framework already
does by default.
> +
> +static const struct v4l2_ctrl_ops visconti_viif_isp_ctrl_ops = {
> + .g_volatile_ctrl = visconti_viif_isp_get_ctrl,
> + .s_ctrl = visconti_viif_isp_set_ctrl,
As mentioned above, you should add a try_ctrl callback as well to do the
validation. Note that if there is a try_ctrl callback, then set_ctrl doesn't
need to do the validation anymore since try_ctrl will be called before set_ctrl.
> +};
> +
> +/* ----- control handler ----- */
> +#define CTRL_CONFIG_DEFAULT_ENTRY \
> + .ops = &visconti_viif_isp_ctrl_ops, .type_ops = &custom_type_ops, \
> + .type = COMPOUND_TYPE_SAMPLE01, .flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE
Why is V4L2_CTRL_FLAG_EXECUTE_ON_WRITE needed?
> +
> +#define CTRL_CONFIG_RDONLY_ENTRY \
> + .ops = &visconti_viif_isp_ctrl_ops, .type_ops = &custom_type_ops, \
> + .type = COMPOUND_TYPE_SAMPLE01, .flags = V4L2_CTRL_FLAG_VOLATILE
Shouldn't the READ_ONLY flag be set as well?
> +
> +static const struct v4l2_ctrl_config visconti_viif_isp_ctrl_config[] = {
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE,
> + .name = "rawpack_mode",
These strings appear as the name of the control and are supposed to be
human readable. So I would write this as: "Rawpack Mode", and (for the
next control): "L1 Input Mode", etc.
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(u32),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE,
> + .name = "l1_input_mode",
> + .p_def = { .p_const = NULL },
Just drop this, no need to initialize fields to 0.
> + .elem_size = sizeof(struct viif_l1_input_mode_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF,
> + .name = "l1_rgb_to_y_coef",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_rgb_to_y_coef_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE,
> + .name = "l1_ag_mode",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_ag_mode_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG,
> + .name = "l1_ag",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_ag_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE,
> + .name = "l1_hdre",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_hdre_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION,
> + .name = "l1_img_extraction",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_img_extraction_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC,
> + .name = "l1_dpc",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_dpc_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE,
> + .name = "l1_preset_white_balance",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_preset_white_balance_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION,
> + .name = "l1_raw_color_noise_reduction",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_raw_color_noise_reduction_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS,
> + .name = "l1_set_hdrs",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_hdrs_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION,
> + .name = "l1_black_level_correction",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_black_level_correction_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC,
> + .name = "l1_lsc",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_lsc_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS,
> + .name = "l1_main_process",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_main_process_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB,
> + .name = "l1_awb",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_awb_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN,
> + .name = "l1_lock_awb_gain",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(u32),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC,
> + .name = "l1_hdrc",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_hdrc_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM,
> + .name = "l1_hdrc_ltm",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_hdrc_ltm_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA,
> + .name = "l1_gamma",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_gamma_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT,
> + .name = "l1_img_quality_adjustment",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_img_quality_adjustment_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION,
> + .name = "l1_avg_lum",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l1_avg_lum_generation_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST,
> + .name = "l2_undist",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l2_undist_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI,
> + .name = "l2_roi",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l2_roi_config),
> + },
> + {
> + CTRL_CONFIG_DEFAULT_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA,
> + .name = "l2_gamma",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_l2_gamma_config),
> + },
> + {
> + CTRL_CONFIG_RDONLY_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS,
> + .name = "csi2rx_calibration_status",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_csi2rx_dphy_calibration_status),
> + },
> + {
> + CTRL_CONFIG_RDONLY_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS,
> + .name = "csi2rx_err_status",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_csi2rx_err_status),
> + },
> + {
> + CTRL_CONFIG_RDONLY_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS,
> + .name = "last_capture_status",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_isp_capture_status),
> + },
> + {
> + CTRL_CONFIG_RDONLY_ENTRY,
> + .id = V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS,
> + .name = "reported errors",
> + .p_def = { .p_const = NULL },
> + .elem_size = sizeof(struct viif_reported_errors),
> + },
> +};
> +
> +int visconti_viif_isp_init_controls(struct viif_device *viif_dev)
> +{
> + struct v4l2_ctrl_handler *ctrl_handler = &viif_dev->isp_subdev.ctrl_handler;
> + int ret;
> + int i;
> +
> + ret = v4l2_ctrl_handler_init(ctrl_handler, 10);
Replace 10 by ARRAY_SIZE(visconti_viif_isp_ctrl_config), that way the
control handler has the right hint about the number of controls.
> + if (ret) {
> + dev_err(viif_dev->dev, "failed on v4l2_ctrl_handler_init");
> + return ret;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(visconti_viif_isp_ctrl_config); i++) {
> + struct v4l2_ctrl *ctrl;
> +
> + ctrl = v4l2_ctrl_new_custom(ctrl_handler, &visconti_viif_isp_ctrl_config[i],
> + viif_dev);
> + if (!ctrl) {
> + dev_err(viif_dev->dev, "failed to add ctrl crop: %d", ctrl_handler->error);
> + return ctrl_handler->error;
> + }
> + }
> +
> + viif_dev->isp_subdev.sd.ctrl_handler = &viif_dev->isp_subdev.ctrl_handler;
> + return 0;
> +}
> diff --git a/drivers/media/platform/visconti/viif_isp.c b/drivers/media/platform/visconti/viif_isp.c
> index 9314e6e8661..9aeb8bcab9b 100644
> --- a/drivers/media/platform/visconti/viif_isp.c
> +++ b/drivers/media/platform/visconti/viif_isp.c
> @@ -818,6 +818,8 @@ int visconti_viif_isp_register(struct viif_device *viif_dev)
>
> mutex_init(&viif_dev->isp_subdev.ops_lock);
>
> + visconti_viif_isp_init_controls(viif_dev);
> +
> ret = media_entity_pads_init(&sd->entity, 4, pads);
> if (ret) {
> dev_err(viif_dev->dev, "Failed on media_entity_pads_init\n");
Regards,
Hans
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-17 11:19 ` Hans Verkuil
@ 2023-01-26 0:38 ` yuji2.ishikawa
2023-01-26 8:39 ` Hans Verkuil
0 siblings, 1 reply; 42+ messages in thread
From: yuji2.ishikawa @ 2023-01-26 0:38 UTC (permalink / raw)
To: hverkuil, laurent.pinchart, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
Hello Hans,
Thank you for your comments.
> -----Original Message-----
> From: Hans Verkuil <hverkuil@xs4all.nl>
> Sent: Tuesday, January 17, 2023 8:20 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>; Mauro Carvalho Chehab
> <mchehab@kernel.org>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Rafael J . Wysocki
> <rafael.j.wysocki@intel.com>; Mark Brown <broonie@kernel.org>
> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver v4l2 controls handler
>
> Some review comments below:
>
> On 11/01/2023 03:24, Yuji Ishikawa wrote:
> > Add support to Image Signal Processors of Visconti's Video Input Interface.
> > This patch adds vendor specific compound controls
> > to configure the image signal processor.
> >
> > Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
> > ---
> > Changelog v2:
> > - Resend v1 because a patch exceeds size limit.
> >
> > Changelog v3:
> > - Adapted to media control framework
> > - Introduced ISP subdevice, capture device
> > - Remove private IOCTLs and add vendor specific V4L2 controls
> > - Change function name avoiding camelcase and uppercase letters
> >
> > Changelog v4:
> > - Split patches because the v3 patch exceeds size limit
> > - Stop using ID number to identify driver instance:
> > - Use dynamically allocated structure to hold HW specific context,
> > instead of static one.
> > - Call HW layer functions with the context structure instead of ID number
> >
> > Changelog v5:
> > - no change
> > ---
> > drivers/media/platform/visconti/Makefile | 4 +-
> > .../media/platform/visconti/hwd_viif_l1isp.c | 2674
> +++++++++++++++++
> > .../media/platform/visconti/viif_controls.c | 1153 +++++++
> > drivers/media/platform/visconti/viif_isp.c | 2 +
> > 4 files changed, 3831 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/media/platform/visconti/hwd_viif_l1isp.c
> > create mode 100644 drivers/media/platform/visconti/viif_controls.c
> >
> > diff --git a/drivers/media/platform/visconti/Makefile
> b/drivers/media/platform/visconti/Makefile
> > index d7a23c1f4e8..13cf70ce309 100644
> > --- a/drivers/media/platform/visconti/Makefile
> > +++ b/drivers/media/platform/visconti/Makefile
> > @@ -3,7 +3,7 @@
> > # Makefile for the Visconti video input device driver
> > #
> >
> > -visconti-viif-objs = viif.o viif_capture.o viif_isp.o
> > -visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o
> > +visconti-viif-objs = viif.o viif_capture.o viif_controls.o viif_isp.o
> > +visconti-viif-objs += hwd_viif_csi2rx.o hwd_viif.o hwd_viif_l1isp.o
> >
> > obj-$(CONFIG_VIDEO_VISCONTI_VIIF) += visconti-viif.o
> > diff --git a/drivers/media/platform/visconti/hwd_viif_l1isp.c
> b/drivers/media/platform/visconti/hwd_viif_l1isp.c
> > new file mode 100644
> > index 00000000000..882eea92205
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/hwd_viif_l1isp.c
> > @@ -0,0 +1,2674 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/io.h>
> > +#include "hwd_viif.h"
> > +#include "hwd_viif_internal.h"
> > +
> > +/**
> > + * hwd_viif_l1_set_input_mode() - Configure L1ISP input mode.
> > + *
> > + * @mode: L1ISP preprocessing mode @ref hwd_viif_l1_input_mode
> > + * @depth: input color depth (even only)
> > + * - [8..24] in case of mode = #HWD_VIIF_L1_INPUT_HDR or
> #HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT
> > + * - [8..14] in case of mode = #HWD_VIIF_L1_INPUT_PWL or
> #HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT
> > + * - [8..12] in case of mode = #HWD_VIIF_L1_INPUT_SDR
> > + * @raw_color_filter: RAW color filter array @ref
> hwd_viif_l1_raw_color_filter_mode
> > + * @interpolation_order: interpolation order for input image
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "mode" is out of range
> > + * - "depth" is out of range
> > + * - "raw_color_filter" is out of range
> > + * - "interpolation_order" is NULL in case of "mode" ==
> #HWD_VIIF_L1_INPUT_SDR
> > + * - "interpolation_order" is not NULL in case of "mode" !=
> #HWD_VIIF_L1_INPUT_SDR
> > + *
> > + * Note that if 'mode' is not HWD_VIIF_L1_INPUT_SDR, NULL shall be set to
> 'interpolation_order'.
> > + */
> > +s32 hwd_viif_l1_set_input_mode(struct hwd_viif_res *res, u32 mode, u32
> depth, u32 raw_color_filter)
> > +{
> > + u32 depth_max;
> > +
> > + if (mode >= HWD_VIIF_L1_INPUT_MODE_NUM || mode ==
> HWD_VIIF_L1_INPUT_SDR)
> > + return -EINVAL;
> > +
> > + if (mode == HWD_VIIF_L1_INPUT_PWL || mode ==
> HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT)
> > + depth_max = HWD_VIIF_L1_INPUT_DEPTH_PWL_MAX;
> > + else
> > + depth_max = HWD_VIIF_L1_INPUT_DEPTH_MAX;
> > +
> > + if (depth < HWD_VIIF_L1_INPUT_DEPTH_MIN || depth > depth_max ||
> ((depth % 2U) != 0U) ||
> > + raw_color_filter >= HWD_VIIF_L1_RAW_MODE_NUM) {
> > + return -EINVAL;
> > + }
> > +
> > + writel(mode, &res->capture_reg->l1isp.L1_SYSM_INPUT_MODE);
> > + writel(depth, &res->capture_reg->l1isp.L1_IBUF_DEPTH);
> > + writel(raw_color_filter,
> &res->capture_reg->l1isp.L1_SYSM_START_COLOR);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_rgb_to_y_coef() - Configure L1ISP RGB coefficients to
> calculate Y.
> > + *
> > + * @coef_r: R coefficient to calculate Y [256..65024] accuracy: 1/65536
> > + * @coef_g: G coefficient to calculate Y [256..65024] accuracy: 1/65536
> > + * @coef_b: B coefficient to calculate Y [256..65024] accuracy: 1/65536
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "coef_r" is out of range
> > + * - "coef_g" is out of range
> > + * - "coef_b" is out of range
> > + *
> > + * Note that it is possible that coef_r/g/b has rounding error when the value
> is set to HW register
> > + */
> > +s32 hwd_viif_l1_set_rgb_to_y_coef(struct hwd_viif_res *res, u16 coef_r, u16
> coef_g, u16 coef_b)
> > +{
> > + if (coef_r < HWD_VIIF_L1_COEF_MIN || coef_r >
> HWD_VIIF_L1_COEF_MAX ||
> > + coef_g < HWD_VIIF_L1_COEF_MIN || coef_g >
> HWD_VIIF_L1_COEF_MAX ||
> > + coef_b < HWD_VIIF_L1_COEF_MIN || coef_b >
> HWD_VIIF_L1_COEF_MAX) {
> > + return -EINVAL;
> > + }
> > +
> > + writel((u32)coef_r, &res->capture_reg->l1isp.L1_SYSM_YCOEF_R);
> > + writel((u32)coef_g, &res->capture_reg->l1isp.L1_SYSM_YCOEF_G);
> > + writel((u32)coef_b, &res->capture_reg->l1isp.L1_SYSM_YCOEF_B);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_ag_mode() - Configure L1ISP AG mode.
> > + *
> > + * @param: pointer to struct hwd_viif_l1_ag_mode
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "param" is NULL
> > + * - each member of "param" is invalid
> > + */
> > +s32 hwd_viif_l1_set_ag_mode(struct hwd_viif_res *res, const struct
> viif_l1_ag_mode_config *param)
> > +{
> > + u32 val;
> > +
> > + if (!param || param->sysm_ag_psel_hobc_high >=
> HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_psel_hobc_middle_led >=
> HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_psel_hobc_low >= HWD_VIIF_L1_AG_ID_NUM
> ||
> > + param->sysm_ag_psel_abpc_high >= HWD_VIIF_L1_AG_ID_NUM
> ||
> > + param->sysm_ag_psel_abpc_middle_led >=
> HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_psel_abpc_low >= HWD_VIIF_L1_AG_ID_NUM
> ||
> > + param->sysm_ag_psel_rcnr_high >= HWD_VIIF_L1_AG_ID_NUM
> ||
> > + param->sysm_ag_psel_rcnr_middle_led >=
> HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_psel_rcnr_low >= HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_ssel_lssc >=
> HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
> > + param->sysm_ag_psel_lssc >= HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_ssel_mpro >=
> HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
> > + param->sysm_ag_psel_mpro >= HWD_VIIF_L1_AG_ID_NUM ||
> > + param->sysm_ag_ssel_vpro >=
> HWD_VIIF_L1_SENSITIVITY_IMAGE_NUM ||
> > + param->sysm_ag_psel_vpro >= HWD_VIIF_L1_AG_ID_NUM ||
> > + (param->sysm_ag_cont_hobc_en_high != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_hobc_en_high != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_hobc_en_middle_led !=
> HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_hobc_en_middle_led !=
> HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_hobc_en_low != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_hobc_en_low != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_rcnr_en_high != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_rcnr_en_high != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_rcnr_en_middle_led !=
> HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_rcnr_en_middle_led !=
> HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_rcnr_en_low != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_rcnr_en_low != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_lssc_en != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_lssc_en != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_mpro_en != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_mpro_en != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_vpro_en != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_vpro_en != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_abpc_en_middle_led !=
> HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_abpc_en_middle_led !=
> HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_abpc_en_high != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_abpc_en_high != HWD_VIIF_DISABLE) ||
> > + (param->sysm_ag_cont_abpc_en_low != HWD_VIIF_ENABLE &&
> > + param->sysm_ag_cont_abpc_en_low != HWD_VIIF_DISABLE)) {
> > + return -EINVAL;
> > + }
>
> You should split off the validation code into a separate function
> (e.g. hwd_viif_l1_try_ag_mode) and add support for the try_ctrl op
> where you call these 'try' functions.
>
> The advantage is that applications can use VIDIOC_TRY_EXT_CTRLS to
> check if the controls are valid, it's really where the checks should
> be done.
That's nice.
I'll split off the validation code.
> > +
> > + /* SYSM_AG_PARAM */
> > + val = ((u32)param->sysm_ag_grad[0] << 16U) |
> ((u32)param->sysm_ag_ofst[0]);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_A);
> > + val = ((u32)param->sysm_ag_grad[1] << 16U) |
> ((u32)param->sysm_ag_ofst[1]);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_B);
> > + val = ((u32)param->sysm_ag_grad[2] << 16U) |
> ((u32)param->sysm_ag_ofst[2]);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_C);
> > + val = ((u32)param->sysm_ag_grad[3] << 16U) |
> ((u32)param->sysm_ag_ofst[3]);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_PARAM_D);
> > +
> > + /* SYSM_AG_SEL */
> > + val = ((u32)param->sysm_ag_psel_hobc_high << 6U) |
> > + ((u32)param->sysm_ag_psel_hobc_middle_led << 4U) |
> > + ((u32)param->sysm_ag_psel_hobc_low << 2U);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_HOBC);
> > +
> > + val = ((u32)param->sysm_ag_psel_abpc_high << 6U) |
> > + ((u32)param->sysm_ag_psel_abpc_middle_led << 4U) |
> > + ((u32)param->sysm_ag_psel_abpc_low << 2U);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_ABPC);
> > +
> > + val = ((u32)param->sysm_ag_psel_rcnr_high << 6U) |
> > + ((u32)param->sysm_ag_psel_rcnr_middle_led << 4U) |
> > + ((u32)param->sysm_ag_psel_rcnr_low << 2U);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_RCNR);
> > +
> > + val = ((u32)param->sysm_ag_ssel_lssc << 2U) |
> ((u32)param->sysm_ag_psel_lssc);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_LSSC);
> > +
> > + val = ((u32)param->sysm_ag_ssel_mpro << 2U) |
> ((u32)param->sysm_ag_psel_mpro);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_MPRO);
> > +
> > + val = ((u32)param->sysm_ag_ssel_vpro << 2U) |
> ((u32)param->sysm_ag_psel_vpro);
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_SEL_VPRO);
> > +
> > + /* SYSM_AG_CONT */
> > + val = (param->sysm_ag_cont_hobc_en_middle_led << 24U) |
> > + ((u32)(param->sysm_ag_cont_hobc_test_middle_led) << 16U) |
> > + (param->sysm_ag_cont_hobc_en_high << 8U) |
> (u32)param->sysm_ag_cont_hobc_test_high;
> > + writel(val,
> &res->capture_reg->l1isp.L1_SYSM_AG_CONT_HOBC01_EN);
> > + val = (param->sysm_ag_cont_hobc_en_low << 8U) |
> (u32)param->sysm_ag_cont_hobc_test_low;
> > + writel(val,
> &res->capture_reg->l1isp.L1_SYSM_AG_CONT_HOBC2_EN);
> > +
> > + val = (param->sysm_ag_cont_abpc_en_middle_led << 24U) |
> > + ((u32)(param->sysm_ag_cont_abpc_test_middle_led) << 16U) |
> > + (param->sysm_ag_cont_abpc_en_high << 8U) |
> (u32)param->sysm_ag_cont_abpc_test_high;
> > + writel(val,
> &res->capture_reg->l1isp.L1_SYSM_AG_CONT_ABPC01_EN);
> > + val = (param->sysm_ag_cont_abpc_en_low << 8U) |
> (u32)param->sysm_ag_cont_abpc_test_low;
> > + writel(val,
> &res->capture_reg->l1isp.L1_SYSM_AG_CONT_ABPC2_EN);
> > +
> > + val = (param->sysm_ag_cont_rcnr_en_middle_led << 24U) |
> > + ((u32)(param->sysm_ag_cont_rcnr_test_middle_led) << 16U) |
> > + (param->sysm_ag_cont_rcnr_en_high << 8U) |
> (u32)param->sysm_ag_cont_rcnr_test_high;
> > + writel(val,
> &res->capture_reg->l1isp.L1_SYSM_AG_CONT_RCNR01_EN);
> > + val = (param->sysm_ag_cont_rcnr_en_low << 8U) |
> (u32)param->sysm_ag_cont_rcnr_test_low;
> > + writel(val,
> &res->capture_reg->l1isp.L1_SYSM_AG_CONT_RCNR2_EN);
> > +
> > + val = (param->sysm_ag_cont_lssc_en << 8U) |
> (u32)param->sysm_ag_cont_lssc_test;
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_LSSC_EN);
> > +
> > + val = (param->sysm_ag_cont_mpro_en << 8U) |
> (u32)param->sysm_ag_cont_mpro_test;
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_MPRO_EN);
> > +
> > + val = (param->sysm_ag_cont_vpro_en << 8U) |
> (u32)param->sysm_ag_cont_vpro_test;
> > + writel(val, &res->capture_reg->l1isp.L1_SYSM_AG_CONT_VPRO_EN);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_ag() - Configure L1ISP analog gain.
> > + *
> > + * @gain_h: analog gain value for high sensitivity image [0..65535]
> > + * @gain_m: analog gain value for middle sensitivity or led image [0..65535]
> > + * @gain_l: analog gain value for low sensitivity image [0..65535]
> > + * Return: 0 operation completed successfully
> > + */
> > +s32 hwd_viif_l1_set_ag(struct hwd_viif_res *res, u16 gain_h, u16 gain_m,
> u16 gain_l)
> > +{
> > + writel((u32)gain_h, &res->capture_reg->l1isp.L1_SYSM_AG_H);
> > + writel((u32)gain_m, &res->capture_reg->l1isp.L1_SYSM_AG_M);
> > + writel((u32)gain_l, &res->capture_reg->l1isp.L1_SYSM_AG_L);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_hdre() - Configure L1ISP HDR extension parameters.
> > + *
> > + * @param: pointer to struct hwd_viif_l1_hdre
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "param" is NULL
> > + * - each member of "param" is invalid
> > + */
> > +s32 hwd_viif_l1_set_hdre(struct hwd_viif_res *res, const struct
> viif_l1_hdre_config *param)
> > +{
> > + u32 idx;
> > +
> > + if (!param)
> > + return -EINVAL;
> > +
> > + for (idx = 0; idx < 16U; idx++) {
> > + if (param->hdre_src_point[idx] >
> HWD_VIIF_L1_HDRE_MAX_KNEEPOINT_VAL)
> > + return -EINVAL;
> > + }
> > +
> > + for (idx = 0; idx < 17U; idx++) {
> > + if (param->hdre_dst_base[idx] >
> HWD_VIIF_L1_HDRE_MAX_HDRE_SIG_VAL ||
> > + param->hdre_ratio[idx] >=
> HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_RATIO) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->hdre_dst_max_val >
> HWD_VIIF_L1_HDRE_MAX_OUT_PIXEL_VAL)
> > + return -EINVAL;
> > +
> > + writel(param->hdre_src_point[0],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT00);
> > + writel(param->hdre_src_point[1],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT01);
> > + writel(param->hdre_src_point[2],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT02);
> > + writel(param->hdre_src_point[3],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT03);
> > + writel(param->hdre_src_point[4],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT04);
> > + writel(param->hdre_src_point[5],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT05);
> > + writel(param->hdre_src_point[6],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT06);
> > + writel(param->hdre_src_point[7],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT07);
> > + writel(param->hdre_src_point[8],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT08);
> > + writel(param->hdre_src_point[9],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT09);
> > + writel(param->hdre_src_point[10],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT10);
> > + writel(param->hdre_src_point[11],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT11);
> > + writel(param->hdre_src_point[12],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT12);
> > + writel(param->hdre_src_point[13],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT13);
> > + writel(param->hdre_src_point[14],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT14);
> > + writel(param->hdre_src_point[15],
> &res->capture_reg->l1isp.L1_HDRE_SRCPOINT15);
> > +
> > + writel(0, &res->capture_reg->l1isp.L1_HDRE_SRCBASE00);
> > + writel(param->hdre_src_point[0],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE01);
> > + writel(param->hdre_src_point[1],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE02);
> > + writel(param->hdre_src_point[2],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE03);
> > + writel(param->hdre_src_point[3],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE04);
> > + writel(param->hdre_src_point[4],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE05);
> > + writel(param->hdre_src_point[5],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE06);
> > + writel(param->hdre_src_point[6],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE07);
> > + writel(param->hdre_src_point[7],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE08);
> > + writel(param->hdre_src_point[8],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE09);
> > + writel(param->hdre_src_point[9],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE10);
> > + writel(param->hdre_src_point[10],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE11);
> > + writel(param->hdre_src_point[11],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE12);
> > + writel(param->hdre_src_point[12],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE13);
> > + writel(param->hdre_src_point[13],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE14);
> > + writel(param->hdre_src_point[14],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE15);
> > + writel(param->hdre_src_point[15],
> &res->capture_reg->l1isp.L1_HDRE_SRCBASE16);
> > +
> > + writel(param->hdre_dst_base[0],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE00);
> > + writel(param->hdre_dst_base[1],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE01);
> > + writel(param->hdre_dst_base[2],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE02);
> > + writel(param->hdre_dst_base[3],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE03);
> > + writel(param->hdre_dst_base[4],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE04);
> > + writel(param->hdre_dst_base[5],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE05);
> > + writel(param->hdre_dst_base[6],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE06);
> > + writel(param->hdre_dst_base[7],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE07);
> > + writel(param->hdre_dst_base[8],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE08);
> > + writel(param->hdre_dst_base[9],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE09);
> > + writel(param->hdre_dst_base[10],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE10);
> > + writel(param->hdre_dst_base[11],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE11);
> > + writel(param->hdre_dst_base[12],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE12);
> > + writel(param->hdre_dst_base[13],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE13);
> > + writel(param->hdre_dst_base[14],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE14);
> > + writel(param->hdre_dst_base[15],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE15);
> > + writel(param->hdre_dst_base[16],
> &res->capture_reg->l1isp.L1_HDRE_DSTBASE16);
> > +
> > + writel(param->hdre_ratio[0],
> &res->capture_reg->l1isp.L1_HDRE_RATIO00);
> > + writel(param->hdre_ratio[1],
> &res->capture_reg->l1isp.L1_HDRE_RATIO01);
> > + writel(param->hdre_ratio[2],
> &res->capture_reg->l1isp.L1_HDRE_RATIO02);
> > + writel(param->hdre_ratio[3],
> &res->capture_reg->l1isp.L1_HDRE_RATIO03);
> > + writel(param->hdre_ratio[4],
> &res->capture_reg->l1isp.L1_HDRE_RATIO04);
> > + writel(param->hdre_ratio[5],
> &res->capture_reg->l1isp.L1_HDRE_RATIO05);
> > + writel(param->hdre_ratio[6],
> &res->capture_reg->l1isp.L1_HDRE_RATIO06);
> > + writel(param->hdre_ratio[7],
> &res->capture_reg->l1isp.L1_HDRE_RATIO07);
> > + writel(param->hdre_ratio[8],
> &res->capture_reg->l1isp.L1_HDRE_RATIO08);
> > + writel(param->hdre_ratio[9],
> &res->capture_reg->l1isp.L1_HDRE_RATIO09);
> > + writel(param->hdre_ratio[10],
> &res->capture_reg->l1isp.L1_HDRE_RATIO10);
> > + writel(param->hdre_ratio[11],
> &res->capture_reg->l1isp.L1_HDRE_RATIO11);
> > + writel(param->hdre_ratio[12],
> &res->capture_reg->l1isp.L1_HDRE_RATIO12);
> > + writel(param->hdre_ratio[13],
> &res->capture_reg->l1isp.L1_HDRE_RATIO13);
> > + writel(param->hdre_ratio[14],
> &res->capture_reg->l1isp.L1_HDRE_RATIO14);
> > + writel(param->hdre_ratio[15],
> &res->capture_reg->l1isp.L1_HDRE_RATIO15);
> > + writel(param->hdre_ratio[16],
> &res->capture_reg->l1isp.L1_HDRE_RATIO16);
> > +
> > + writel(param->hdre_dst_max_val,
> &res->capture_reg->l1isp.L1_HDRE_DSTMAXVAL);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_img_extraction() - Configure L1ISP image extraction
> parameters.
> > + *
> > + * @input_black_gr: black level of Gr input pixel [0x0..0xffffff]
> > + * @input_black_r: black level of R input pixel [0x0..0xffffff]
> > + * @input_black_b: black level of B input pixel [0x0..0xffffff]
> > + * @input_black_gb: black level of Gb input pixel [0x0..0xffffff]
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "input_black_gr" is out of range
> > + * - "input_black_r" is out of range
> > + * - "input_black_b" is out of range
> > + * - "input_black_gb" is out of range
> > + */
> > +s32 hwd_viif_l1_set_img_extraction(struct hwd_viif_res *res, u32
> input_black_gr, u32 input_black_r,
> > + u32 input_black_b, u32 input_black_gb)
> > +{
> > + if (input_black_gr >
> HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
> > + input_black_r >
> HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
> > + input_black_b >
> HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL ||
> > + input_black_gb >
> HWD_VIIF_L1_IMG_EXTRACT_MAX_BLACK_LEVEL_VAL) {
> > + return -EINVAL;
> > + }
> > +
> > + writel(input_black_gr,
> &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_GR);
> > + writel(input_black_r,
> &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_R);
> > + writel(input_black_b,
> &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_B);
> > + writel(input_black_gb,
> &res->capture_reg->l1isp.L1_SLIC_SRCBLACKLEVEL_GB);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_dpc() - Configure L1ISP defect pixel correction
> parameters.
> > + *
> > + * @param_h: pointer to defect pixel correction parameters for high
> sensitivity image
> > + * @param_m: pointer to defect pixel correction parameters for middle
> sensitivity or led image
> > + * @param_l: pointer to defect pixel correction parameters for low sensitivity
> image
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "param_h", "param_m" and "param_l" are NULL
> > + * - each member of "param_h" is invalid
> > + * - each member of "param_m" is invalid
> > + * - each member of "param_l" is invalid
> > + */
> > +s32 hwd_viif_l1_set_dpc(struct hwd_viif_res *res, const struct viif_l1_dpc
> *param_h,
> > + const struct viif_l1_dpc *param_m, const struct
> viif_l1_dpc *param_l)
> > +{
> > + const struct viif_l1_dpc *param;
> > + u32 idx;
> > + u32 val;
> > +
> > + if (!param_h && !param_m && !param_l)
> > + return -EINVAL;
> > +
> > + for (idx = 0U; idx < 3U; idx++) {
> > + if (idx == 0U)
> > + param = param_h;
> > + else if (idx == 1U)
> > + param = param_m;
> > + else
> > + param = param_l;
> > +
> > + if (!param)
> > + continue;
> > +
> > + if ((param->abpc_sta_en != HWD_VIIF_ENABLE &&
> > + param->abpc_sta_en != HWD_VIIF_DISABLE) ||
> > + (param->abpc_dyn_en != HWD_VIIF_ENABLE &&
> > + param->abpc_dyn_en != HWD_VIIF_DISABLE)) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->abpc_dyn_en != HWD_VIIF_ENABLE)
> > + continue;
> > +
> > + if ((param->abpc_dyn_mode != HWD_VIIF_L1_DPC_1PIXEL
> &&
> > + param->abpc_dyn_mode !=
> HWD_VIIF_L1_DPC_2PIXEL) ||
> > + param->abpc_ratio_limit >
> HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL ||
> > + param->abpc_dark_limit >
> HWD_VIIF_L1_DPC_MAX_RATIO_LIMIT_VAL ||
> > + param->abpc_sn_coef_w_ag_min <
> HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_w_ag_min >
> HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_w_ag_mid <
> HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_w_ag_mid >
> HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_w_ag_max <
> HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_w_ag_max >
> HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_b_ag_min <
> HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_b_ag_min >
> HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_b_ag_mid <
> HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_b_ag_mid >
> HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_b_ag_max <
> HWD_VIIF_L1_DPC_MIN_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_b_ag_max >
> HWD_VIIF_L1_DPC_MAX_LUMA_ADJ_VAL ||
> > + param->abpc_sn_coef_w_th_min >=
> param->abpc_sn_coef_w_th_max ||
> > + param->abpc_sn_coef_b_th_min >=
> param->abpc_sn_coef_b_th_max) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + val = 0;
> > + if (param_h)
> > + val |= param_h->abpc_sta_en << 24U;
> > +
> > + if (param_m)
> > + val |= param_m->abpc_sta_en << 16U;
> > +
> > + if (param_l)
> > + val |= param_l->abpc_sta_en << 8U;
> > +
> > + writel(val, &res->capture_reg->l1isp.L1_ABPC012_STA_EN);
> > +
> > + val = 0;
> > + if (param_h)
> > + val |= param_h->abpc_dyn_en << 24U;
> > +
> > + if (param_m)
> > + val |= param_m->abpc_dyn_en << 16U;
> > +
> > + if (param_l)
> > + val |= param_l->abpc_dyn_en << 8U;
> > +
> > + writel(val, &res->capture_reg->l1isp.L1_ABPC012_DYN_EN);
> > +
> > + val = 0;
> > + if (param_h)
> > + val |= param_h->abpc_dyn_mode << 24U;
> > +
> > + if (param_m)
> > + val |= param_m->abpc_dyn_mode << 16U;
> > +
> > + if (param_l)
> > + val |= param_l->abpc_dyn_mode << 8U;
> > +
> > + writel(val, &res->capture_reg->l1isp.L1_ABPC012_DYN_MODE);
> > +
> > + if (param_h) {
> > + writel(param_h->abpc_ratio_limit,
> &res->capture_reg->l1isp.L1_ABPC0_RATIO_LIMIT);
> > + writel(param_h->abpc_dark_limit,
> &res->capture_reg->l1isp.L1_ABPC0_DARK_LIMIT);
> > + writel(param_h->abpc_sn_coef_w_ag_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MIN);
> > + writel(param_h->abpc_sn_coef_w_ag_mid,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MID);
> > + writel(param_h->abpc_sn_coef_w_ag_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_AG_MAX);
> > + writel(param_h->abpc_sn_coef_b_ag_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MIN);
> > + writel(param_h->abpc_sn_coef_b_ag_mid,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MID);
> > + writel(param_h->abpc_sn_coef_b_ag_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_AG_MAX);
> > + writel((u32)param_h->abpc_sn_coef_w_th_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_TH_MIN);
> > + writel((u32)param_h->abpc_sn_coef_w_th_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_W_TH_MAX);
> > + writel((u32)param_h->abpc_sn_coef_b_th_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_TH_MIN);
> > + writel((u32)param_h->abpc_sn_coef_b_th_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC0_SN_COEF_B_TH_MAX);
> > + }
> > +
> > + if (param_m) {
> > + writel(param_m->abpc_ratio_limit,
> &res->capture_reg->l1isp.L1_ABPC1_RATIO_LIMIT);
> > + writel(param_m->abpc_dark_limit,
> &res->capture_reg->l1isp.L1_ABPC1_DARK_LIMIT);
> > + writel(param_m->abpc_sn_coef_w_ag_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MIN);
> > + writel(param_m->abpc_sn_coef_w_ag_mid,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MID);
> > + writel(param_m->abpc_sn_coef_w_ag_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_AG_MAX);
> > + writel(param_m->abpc_sn_coef_b_ag_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MIN);
> > + writel(param_m->abpc_sn_coef_b_ag_mid,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MID);
> > + writel(param_m->abpc_sn_coef_b_ag_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_AG_MAX);
> > + writel((u32)param_m->abpc_sn_coef_w_th_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_TH_MIN);
> > + writel((u32)param_m->abpc_sn_coef_w_th_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_W_TH_MAX);
> > + writel((u32)param_m->abpc_sn_coef_b_th_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_TH_MIN);
> > + writel((u32)param_m->abpc_sn_coef_b_th_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC1_SN_COEF_B_TH_MAX);
> > + }
> > +
> > + if (param_l) {
> > + writel(param_l->abpc_ratio_limit,
> &res->capture_reg->l1isp.L1_ABPC2_RATIO_LIMIT);
> > + writel(param_l->abpc_dark_limit,
> &res->capture_reg->l1isp.L1_ABPC2_DARK_LIMIT);
> > + writel(param_l->abpc_sn_coef_w_ag_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MIN);
> > + writel(param_l->abpc_sn_coef_w_ag_mid,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MID);
> > + writel(param_l->abpc_sn_coef_w_ag_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_AG_MAX);
> > + writel(param_l->abpc_sn_coef_b_ag_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MIN);
> > + writel(param_l->abpc_sn_coef_b_ag_mid,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MID);
> > + writel(param_l->abpc_sn_coef_b_ag_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_AG_MAX);
> > + writel((u32)param_l->abpc_sn_coef_w_th_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_TH_MIN);
> > + writel((u32)param_l->abpc_sn_coef_w_th_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_W_TH_MAX);
> > + writel((u32)param_l->abpc_sn_coef_b_th_min,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_TH_MIN);
> > + writel((u32)param_l->abpc_sn_coef_b_th_max,
> > +
> &res->capture_reg->l1isp.L1_ABPC2_SN_COEF_B_TH_MAX);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_dpc_table_transmission() -
> > + * Configure L1ISP transferring defect pixel correction table.
> > + *
> > + * @table_h: defect pixel correction table for high sensitivity image(physical
> address)
> > + * @table_m: defect pixel correction table for middle sensitivity or led
> image(physical address)
> > + * @table_l: defect pixel correction table for low sensitivity image(physical
> address)
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "table_h", "table_m" or "table_l" is not 8byte alignment
> > + *
> > + * Note that when 0 is set to table address, table transfer of the table is
> disabled.
> > + */
> > +s32 hwd_viif_l1_set_dpc_table_transmission(struct hwd_viif_res *res,
> uintptr_t table_h,
> > + uintptr_t table_m, uintptr_t
> table_l)
> > +{
> > + u32 val = 0x0U;
> > +
> > + if (((table_h % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> > + ((table_m % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> > + ((table_l % HWD_VIIF_L1_VDM_ALIGN) != 0U)) {
> > + return -EINVAL;
> > + }
> > +
> > + /* VDM common settings */
> > +
> > + writel(HWD_VIIF_L1_VDM_CFG_PARAM,
> &res->capture_reg->vdm.t_group[0].VDM_T_CFG);
> > + writel(HWD_VIIF_L1_VDM_SRAM_BASE,
> &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_BASE);
> > + writel(HWD_VIIF_L1_VDM_SRAM_SIZE,
> &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_SIZE);
> > +
> > + if (table_h != 0U) {
> > + writel((u32)table_h,
> &res->capture_reg->vdm.t_port[0].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[0].VDM_T_SIZE);
> > + val |= 0x1U;
> > + }
> > +
> > + if (table_m != 0U) {
> > + writel((u32)table_m,
> &res->capture_reg->vdm.t_port[1].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[1].VDM_T_SIZE);
> > + val |= 0x2U;
> > + }
> > +
> > + if (table_l != 0U) {
> > + writel((u32)table_l,
> &res->capture_reg->vdm.t_port[2].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_DPC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[2].VDM_T_SIZE);
> > + val |= 0x4U;
> > + }
> > +
> > + val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) &
> 0xfffffff8U);
> > + writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_preset_white_balance() - Configure L1ISP preset white
> balance parameters.
> > + *
> > + * @dstmaxval: maximum output pixel value [0..4095]
> > + * @param_h: pointer to preset white balance parameters for high sensitivity
> image
> > + * @param_m: pointer to preset white balance parameters for middle
> sensitivity or led image
> > + * @param_l: pointer to preset white balance parameters for low sensitivity
> image
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "dstmaxval" is out of range
> > + * - "param_h", "param_m", and "param_l" are NULL
> > + * - each parameter of "param_h" is out of range
> > + * - each parameter of "param_m" is out of range
> > + * - each parameter of "param_l" is out of range
> > + * Note that when NULL is set to "param_{h/m/l}", the corresponding
> parameters are not set to HW.
> > + */
> > +s32 hwd_viif_l1_set_preset_white_balance(struct hwd_viif_res *res, u32
> dstmaxval,
> > + const struct viif_l1_preset_wb
> *param_h,
> > + const struct viif_l1_preset_wb
> *param_m,
> > + const struct viif_l1_preset_wb
> *param_l)
> > +{
> > + if (dstmaxval > HWD_VIIF_L1_PWHB_MAX_OUT_PIXEL_VAL ||
> (!param_h && !param_m && !param_l))
> > + return -EINVAL;
> > +
> > + if (param_h) {
> > + if (param_h->gain_gr >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_h->gain_r >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_h->gain_b >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_h->gain_gb >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param_m) {
> > + if (param_m->gain_gr >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_m->gain_r >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_m->gain_b >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_m->gain_gb >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param_l) {
> > + if (param_l->gain_gr >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_l->gain_r >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_l->gain_b >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL ||
> > + param_l->gain_gb >=
> HWD_VIIF_L1_PWHB_MAX_GAIN_VAL) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + writel(dstmaxval, &res->capture_reg->l1isp.L1_PWHB_DSTMAXVAL);
> > +
> > + if (param_h) {
> > + writel(param_h->gain_gr,
> &res->capture_reg->l1isp.L1_PWHB_H_GR);
> > + writel(param_h->gain_r,
> &res->capture_reg->l1isp.L1_PWHB_HR);
> > + writel(param_h->gain_b,
> &res->capture_reg->l1isp.L1_PWHB_HB);
> > + writel(param_h->gain_gb,
> &res->capture_reg->l1isp.L1_PWHB_H_GB);
> > + }
> > +
> > + if (param_m) {
> > + writel(param_m->gain_gr,
> &res->capture_reg->l1isp.L1_PWHB_M_GR);
> > + writel(param_m->gain_r,
> &res->capture_reg->l1isp.L1_PWHB_MR);
> > + writel(param_m->gain_b,
> &res->capture_reg->l1isp.L1_PWHB_MB);
> > + writel(param_m->gain_gb,
> &res->capture_reg->l1isp.L1_PWHB_M_GB);
> > + }
> > +
> > + if (param_l) {
> > + writel(param_l->gain_gr,
> &res->capture_reg->l1isp.L1_PWHB_L_GR);
> > + writel(param_l->gain_r,
> &res->capture_reg->l1isp.L1_PWHB_LR);
> > + writel(param_l->gain_b,
> &res->capture_reg->l1isp.L1_PWHB_LB);
> > + writel(param_l->gain_gb,
> &res->capture_reg->l1isp.L1_PWHB_L_GB);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_raw_color_noise_reduction() -
> > + * Configure L1ISP raw color noise reduction parameters.
> > + *
> > + * @param_h: pointer to raw color noise reduction parameters for high
> sensitivity image
> > + * @param_m: pointer to raw color noise reduction parameters for middle
> sensitivity or led image
> > + * @param_l: pointer to raw color noise reduction parameters for low
> sensitivity image
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "param_h", "param_m", and "param_l" are NULL
> > + * - each parameter of "param_h" is out of range
> > + * - each parameter of "param_m" is out of range
> > + * - each parameter of "param_l" is out of range
> > + * Note that when NULL is set to "param_{h/m/l}", the corresponding
> parameters are not set to HW.
> > + */
> > +s32 hwd_viif_l1_set_raw_color_noise_reduction(
> > + struct hwd_viif_res *res, const struct viif_l1_raw_color_noise_reduction
> *param_h,
> > + const struct viif_l1_raw_color_noise_reduction *param_m,
> > + const struct viif_l1_raw_color_noise_reduction *param_l)
> > +{
> > + const struct viif_l1_raw_color_noise_reduction *param;
> > + u32 idx;
> > +
> > + if (!param_h && !param_m && !param_l)
> > + return -EINVAL;
> > +
> > + for (idx = 0; idx < 3U; idx++) {
> > + if (idx == 0U)
> > + param = param_h;
> > + else if (idx == 1U)
> > + param = param_m;
> > + else
> > + param = param_l;
> > +
> > + if (!param)
> > + continue;
> > +
> > + if (param->rcnr_sw != HWD_VIIF_ENABLE &&
> param->rcnr_sw != HWD_VIIF_DISABLE)
> > + return -EINVAL;
> > +
> > + if (param->rcnr_cnf_dark_ag0 >
> HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> > + param->rcnr_cnf_dark_ag1 >
> HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> > + param->rcnr_cnf_dark_ag2 >
> HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> > + param->rcnr_cnf_ratio_ag0 >
> HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> > + param->rcnr_cnf_ratio_ag1 >
> HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> > + param->rcnr_cnf_ratio_ag2 >
> HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> > + param->rcnr_cnf_clip_gain_r >
> HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
> > + param->rcnr_cnf_clip_gain_g >
> HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
> > + param->rcnr_cnf_clip_gain_b >
> HWD_VIIF_L1_RCNR_MAX_ADJUSTMENT_GAIN_VAL ||
> > + param->rcnr_a1l_dark_ag0 >
> HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> > + param->rcnr_a1l_dark_ag1 >
> HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> > + param->rcnr_a1l_dark_ag2 >
> HWD_VIIF_L1_RCNR_MAX_DARK_ADJUSTMENT_VAL ||
> > + param->rcnr_a1l_ratio_ag0 >
> HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> > + param->rcnr_a1l_ratio_ag1 >
> HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> > + param->rcnr_a1l_ratio_ag2 >
> HWD_VIIF_L1_RCNR_MAX_LUMA_LINKAGE_ADJUSTMENT_VAL ||
> > + param->rcnr_inf_zero_clip >
> HWD_VIIF_L1_RCNR_MAX_ZERO_CLIP_VAL ||
> > + param->rcnr_merge_d2blend_ag0 >
> HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
> > + param->rcnr_merge_d2blend_ag1 >
> HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
> > + param->rcnr_merge_d2blend_ag2 >
> HWD_VIIF_L1_RCNR_MAX_BLEND_VAL ||
> > + param->rcnr_merge_black >
> HWD_VIIF_L1_RCNR_MAX_BLACK_LEVEL_VAL ||
> > + param->rcnr_merge_mindiv <
> HWD_VIIF_L1_RCNR_MIN_0DIV_GUARD_VAL ||
> > + param->rcnr_merge_mindiv >
> HWD_VIIF_L1_RCNR_MAX_0DIV_GUARD_VAL) {
> > + return -EINVAL;
> > + }
> > +
> > + switch (param->rcnr_hry_type) {
> > + case HWD_VIIF_L1_RCNR_LOW_RESOLUTION:
> > + case HWD_VIIF_L1_RCNR_MIDDLE_RESOLUTION:
> > + case HWD_VIIF_L1_RCNR_HIGH_RESOLUTION:
> > + case HWD_VIIF_L1_RCNR_ULTRA_HIGH_RESOLUTION:
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + if (param->rcnr_anf_blend_ag0 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
> > + param->rcnr_anf_blend_ag0 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
> > + param->rcnr_anf_blend_ag0 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
> > + return -EINVAL;
> > + }
> > + if (param->rcnr_anf_blend_ag1 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
> > + param->rcnr_anf_blend_ag1 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
> > + param->rcnr_anf_blend_ag1 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
> > + return -EINVAL;
> > + }
> > + if (param->rcnr_anf_blend_ag2 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_0_DIV_64 &&
> > + param->rcnr_anf_blend_ag2 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_1_DIV_64 &&
> > + param->rcnr_anf_blend_ag2 !=
> HWD_VIIF_L1_MSF_BLEND_RATIO_2_DIV_64) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->rcnr_lpf_threshold >=
> HWD_VIIF_L1_RCNR_MAX_CALC_MSF_NOISE_MULTI_VAL ||
> > + param->rcnr_merge_hlblend_ag0 >
> HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
> > + param->rcnr_merge_hlblend_ag1 >
> HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
> > + param->rcnr_merge_hlblend_ag2 >
> HWD_VIIF_L1_RCNR_MAX_GEN_LUMA_SIG_BLEND_VAL ||
> > + (param->rcnr_gnr_sw != HWD_VIIF_DISABLE &&
> > + param->rcnr_gnr_sw != HWD_VIIF_ENABLE)) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> > + if (param->rcnr_gnr_ratio >
> HWD_VIIF_L1_RCNR_MAX_UP_LIMIT_GRGB_SENS_RATIO)
> > + return -EINVAL;
> > + if (param->rcnr_gnr_wide_en != HWD_VIIF_DISABLE
> &&
> > + param->rcnr_gnr_wide_en !=
> HWD_VIIF_ENABLE) {
> > + return -EINVAL;
> > + }
> > + }
> > + }
> > +
> > + if (param_h) {
> > + writel(param_h->rcnr_sw,
> &res->capture_reg->l1isp.L1_RCNR0_SW);
> > +
> > + writel(param_h->rcnr_cnf_dark_ag0,
> &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG0);
> > + writel(param_h->rcnr_cnf_dark_ag1,
> &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG1);
> > + writel(param_h->rcnr_cnf_dark_ag2,
> &res->capture_reg->l1isp.L1_RCNR0_CNF_DARK_AG2);
> > +
> > + writel(param_h->rcnr_cnf_ratio_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG0);
> > + writel(param_h->rcnr_cnf_ratio_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG1);
> > + writel(param_h->rcnr_cnf_ratio_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_CNF_RATIO_AG2);
> > +
> > + writel(param_h->rcnr_cnf_clip_gain_r,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_R);
> > + writel(param_h->rcnr_cnf_clip_gain_g,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_G);
> > + writel(param_h->rcnr_cnf_clip_gain_b,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_CNF_CLIP_GAIN_B);
> > +
> > + writel(param_h->rcnr_a1l_dark_ag0,
> &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG0);
> > + writel(param_h->rcnr_a1l_dark_ag1,
> &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG1);
> > + writel(param_h->rcnr_a1l_dark_ag2,
> &res->capture_reg->l1isp.L1_RCNR0_A1L_DARK_AG2);
> > +
> > + writel(param_h->rcnr_a1l_ratio_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG0);
> > + writel(param_h->rcnr_a1l_ratio_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG1);
> > + writel(param_h->rcnr_a1l_ratio_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_A1L_RATIO_AG2);
> > +
> > + writel(param_h->rcnr_inf_zero_clip,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_INF_ZERO_CLIP);
> > +
> > + writel(param_h->rcnr_merge_d2blend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG0);
> > + writel(param_h->rcnr_merge_d2blend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG1);
> > + writel(param_h->rcnr_merge_d2blend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_D2BLEND_AG2);
> > + writel(param_h->rcnr_merge_black,
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_BLACK);
> > + writel(param_h->rcnr_merge_mindiv,
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_MINDIV);
> > +
> > + writel(param_h->rcnr_hry_type,
> &res->capture_reg->l1isp.L1_RCNR0_HRY_TYPE);
> > +
> > + writel(param_h->rcnr_anf_blend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG0);
> > + writel(param_h->rcnr_anf_blend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG1);
> > + writel(param_h->rcnr_anf_blend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_ANF_BLEND_AG2);
> > +
> > + writel(param_h->rcnr_lpf_threshold,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_LPF_THRESHOLD);
> > +
> > + writel(param_h->rcnr_merge_hlblend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG0);
> > + writel(param_h->rcnr_merge_hlblend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG1);
> > + writel(param_h->rcnr_merge_hlblend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_MERGE_HLBLEND_AG2);
> > +
> > + writel(param_h->rcnr_gnr_sw,
> &res->capture_reg->l1isp.L1_RCNR0_GNR_SW);
> > +
> > + if (param_h->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> > + writel(param_h->rcnr_gnr_ratio,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_GNR_RATIO);
> > + writel(param_h->rcnr_gnr_wide_en,
> > +
> &res->capture_reg->l1isp.L1_RCNR0_GNR_WIDE_EN);
> > + }
> > + }
> > +
> > + if (param_m) {
> > + writel(param_m->rcnr_sw,
> &res->capture_reg->l1isp.L1_RCNR1_SW);
> > +
> > + writel(param_m->rcnr_cnf_dark_ag0,
> &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG0);
> > + writel(param_m->rcnr_cnf_dark_ag1,
> &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG1);
> > + writel(param_m->rcnr_cnf_dark_ag2,
> &res->capture_reg->l1isp.L1_RCNR1_CNF_DARK_AG2);
> > +
> > + writel(param_m->rcnr_cnf_ratio_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG0);
> > + writel(param_m->rcnr_cnf_ratio_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG1);
> > + writel(param_m->rcnr_cnf_ratio_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_CNF_RATIO_AG2);
> > +
> > + writel(param_m->rcnr_cnf_clip_gain_r,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_R);
> > + writel(param_m->rcnr_cnf_clip_gain_g,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_G);
> > + writel(param_m->rcnr_cnf_clip_gain_b,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_CNF_CLIP_GAIN_B);
> > +
> > + writel(param_m->rcnr_a1l_dark_ag0,
> &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG0);
> > + writel(param_m->rcnr_a1l_dark_ag1,
> &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG1);
> > + writel(param_m->rcnr_a1l_dark_ag2,
> &res->capture_reg->l1isp.L1_RCNR1_A1L_DARK_AG2);
> > +
> > + writel(param_m->rcnr_a1l_ratio_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG0);
> > + writel(param_m->rcnr_a1l_ratio_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG1);
> > + writel(param_m->rcnr_a1l_ratio_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_A1L_RATIO_AG2);
> > +
> > + writel(param_m->rcnr_inf_zero_clip,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_INF_ZERO_CLIP);
> > +
> > + writel(param_m->rcnr_merge_d2blend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG0);
> > + writel(param_m->rcnr_merge_d2blend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG1);
> > + writel(param_m->rcnr_merge_d2blend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_D2BLEND_AG2);
> > + writel(param_m->rcnr_merge_black,
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_BLACK);
> > + writel(param_m->rcnr_merge_mindiv,
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_MINDIV);
> > +
> > + writel(param_m->rcnr_hry_type,
> &res->capture_reg->l1isp.L1_RCNR1_HRY_TYPE);
> > +
> > + writel(param_m->rcnr_anf_blend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG0);
> > + writel(param_m->rcnr_anf_blend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG1);
> > + writel(param_m->rcnr_anf_blend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_ANF_BLEND_AG2);
> > +
> > + writel(param_m->rcnr_lpf_threshold,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_LPF_THRESHOLD);
> > +
> > + writel(param_m->rcnr_merge_hlblend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG0);
> > + writel(param_m->rcnr_merge_hlblend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG1);
> > + writel(param_m->rcnr_merge_hlblend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_MERGE_HLBLEND_AG2);
> > +
> > + writel(param_m->rcnr_gnr_sw,
> &res->capture_reg->l1isp.L1_RCNR1_GNR_SW);
> > +
> > + if (param_m->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> > + writel(param_m->rcnr_gnr_ratio,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_GNR_RATIO);
> > + writel(param_m->rcnr_gnr_wide_en,
> > +
> &res->capture_reg->l1isp.L1_RCNR1_GNR_WIDE_EN);
> > + }
> > + }
> > +
> > + if (param_l) {
> > + writel(param_l->rcnr_sw,
> &res->capture_reg->l1isp.L1_RCNR2_SW);
> > +
> > + writel(param_l->rcnr_cnf_dark_ag0,
> &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG0);
> > + writel(param_l->rcnr_cnf_dark_ag1,
> &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG1);
> > + writel(param_l->rcnr_cnf_dark_ag2,
> &res->capture_reg->l1isp.L1_RCNR2_CNF_DARK_AG2);
> > +
> > + writel(param_l->rcnr_cnf_ratio_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG0);
> > + writel(param_l->rcnr_cnf_ratio_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG1);
> > + writel(param_l->rcnr_cnf_ratio_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_CNF_RATIO_AG2);
> > +
> > + writel(param_l->rcnr_cnf_clip_gain_r,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_R);
> > + writel(param_l->rcnr_cnf_clip_gain_g,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_G);
> > + writel(param_l->rcnr_cnf_clip_gain_b,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_CNF_CLIP_GAIN_B);
> > +
> > + writel(param_l->rcnr_a1l_dark_ag0,
> &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG0);
> > + writel(param_l->rcnr_a1l_dark_ag1,
> &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG1);
> > + writel(param_l->rcnr_a1l_dark_ag2,
> &res->capture_reg->l1isp.L1_RCNR2_A1L_DARK_AG2);
> > +
> > + writel(param_l->rcnr_a1l_ratio_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG0);
> > + writel(param_l->rcnr_a1l_ratio_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG1);
> > + writel(param_l->rcnr_a1l_ratio_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_A1L_RATIO_AG2);
> > +
> > + writel(param_l->rcnr_inf_zero_clip,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_INF_ZERO_CLIP);
> > +
> > + writel(param_l->rcnr_merge_d2blend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG0);
> > + writel(param_l->rcnr_merge_d2blend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG1);
> > + writel(param_l->rcnr_merge_d2blend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_D2BLEND_AG2);
> > + writel(param_l->rcnr_merge_black,
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_BLACK);
> > + writel(param_l->rcnr_merge_mindiv,
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_MINDIV);
> > +
> > + writel(param_l->rcnr_hry_type,
> &res->capture_reg->l1isp.L1_RCNR2_HRY_TYPE);
> > +
> > + writel(param_l->rcnr_anf_blend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG0);
> > + writel(param_l->rcnr_anf_blend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG1);
> > + writel(param_l->rcnr_anf_blend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_ANF_BLEND_AG2);
> > +
> > + writel(param_l->rcnr_lpf_threshold,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_LPF_THRESHOLD);
> > +
> > + writel(param_l->rcnr_merge_hlblend_ag0,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG0);
> > + writel(param_l->rcnr_merge_hlblend_ag1,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG1);
> > + writel(param_l->rcnr_merge_hlblend_ag2,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_MERGE_HLBLEND_AG2);
> > +
> > + writel(param_l->rcnr_gnr_sw,
> &res->capture_reg->l1isp.L1_RCNR2_GNR_SW);
> > +
> > + if (param_l->rcnr_gnr_sw == HWD_VIIF_ENABLE) {
> > + writel(param_l->rcnr_gnr_ratio,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_GNR_RATIO);
> > + writel(param_l->rcnr_gnr_wide_en,
> > +
> &res->capture_reg->l1isp.L1_RCNR2_GNR_WIDE_EN);
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_hdrs() - Configure L1ISP HDR synthesis parameters.
> > + *
> > + * @param: pointer to HDR synthesis parameters
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "param" is NULL
> > + * - each parameter of "param" is out of range
> > + */
> > +s32 hwd_viif_l1_set_hdrs(struct hwd_viif_res *res, const struct
> viif_l1_hdrs_config *param)
> > +{
> > + if (!param ||
> > + (param->hdrs_hdr_mode !=
> HWD_VIIF_L1_HDRS_NOT_USE_MIDDLE_SENS_IMAGE &&
> > + param->hdrs_hdr_mode !=
> HWD_VIIF_L1_HDRS_USE_MIDDLE_SENS_IMAGE) ||
> > + param->hdrs_hdr_ratio_m <
> HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
> > + param->hdrs_hdr_ratio_m >
> HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
> > + param->hdrs_hdr_ratio_l <
> HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
> > + param->hdrs_hdr_ratio_l >
> HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
> > + param->hdrs_hdr_ratio_e <
> HWD_VIIF_L1_HDRS_MIN_BLEND_RATIO ||
> > + param->hdrs_hdr_ratio_e >
> HWD_VIIF_L1_HDRS_MAX_BLEND_RATIO ||
> > + param->hdrs_dg_h >=
> HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> > + param->hdrs_dg_m >=
> HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> > + param->hdrs_dg_l >=
> HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> > + param->hdrs_dg_e >=
> HWD_VIIF_L1_HDRS_MAX_DIGITAL_GAIN_VAL ||
> > + param->hdrs_blendend_h >
> HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> > + param->hdrs_blendend_m >
> HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> > + param->hdrs_blendend_e >
> HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> > + param->hdrs_blendbeg_h >
> HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> > + param->hdrs_blendbeg_m >
> HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> > + param->hdrs_blendbeg_e >
> HWD_VIIF_L1_HDRS_MAX_BLEND_PIX_VAL ||
> > + (param->hdrs_led_mode_on != HWD_VIIF_ENABLE &&
> > + param->hdrs_led_mode_on != HWD_VIIF_DISABLE) ||
> > + param->hdrs_dst_max_val >
> HWD_VIIF_L1_HDRS_MAX_DST_MAX_VAL) {
> > + return -EINVAL;
> > + }
> > +
> > + writel(param->hdrs_hdr_mode,
> &res->capture_reg->l1isp.L1_HDRS_HDRMODE);
> > +
> > + writel(param->hdrs_hdr_ratio_m,
> &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_M);
> > + writel(param->hdrs_hdr_ratio_l,
> &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_L);
> > + writel(param->hdrs_hdr_ratio_e,
> &res->capture_reg->l1isp.L1_HDRS_HDRRATIO_E);
> > +
> > + writel(param->hdrs_dg_h,
> &res->capture_reg->l1isp.L1_HDRS_DG_H);
> > + writel(param->hdrs_dg_m,
> &res->capture_reg->l1isp.L1_HDRS_DG_M);
> > + writel(param->hdrs_dg_l, &res->capture_reg->l1isp.L1_HDRS_DG_L);
> > + writel(param->hdrs_dg_e, &res->capture_reg->l1isp.L1_HDRS_DG_E);
> > +
> > + writel(param->hdrs_blendend_h,
> &res->capture_reg->l1isp.L1_HDRS_BLENDEND_H);
> > + writel(param->hdrs_blendend_m,
> &res->capture_reg->l1isp.L1_HDRS_BLENDEND_M);
> > + writel(param->hdrs_blendend_e,
> &res->capture_reg->l1isp.L1_HDRS_BLENDEND_E);
> > +
> > + writel(param->hdrs_blendbeg_h,
> &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_H);
> > + writel(param->hdrs_blendbeg_m,
> &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_M);
> > + writel(param->hdrs_blendbeg_e,
> &res->capture_reg->l1isp.L1_HDRS_BLENDBEG_E);
> > +
> > + writel(param->hdrs_led_mode_on,
> &res->capture_reg->l1isp.L1_HDRS_LEDMODE_ON);
> > + writel(param->hdrs_dst_max_val,
> &res->capture_reg->l1isp.L1_HDRS_DSTMAXVAL);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_black_level_correction() - Configure L1ISP black level
> correction parameters.
> > + *
> > + * @param: pointer to black level correction parameters
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "param" is NULL
> > + * - each parameter of "param" is out of range
> > + */
> > +s32 hwd_viif_l1_set_black_level_correction(
> > + struct hwd_viif_res *res, const struct
> viif_l1_black_level_correction_config *param)
> > +{
> > + if (!param || param->srcblacklevel_gr >
> HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> > + param->srcblacklevel_r >
> HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> > + param->srcblacklevel_b >
> HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> > + param->srcblacklevel_gb >
> HWD_VIIF_L1_BLACK_LEVEL_MAX_VAL ||
> > + param->mulval_gr >=
> HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> > + param->mulval_r >=
> HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> > + param->mulval_b >=
> HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> > + param->mulval_gb >=
> HWD_VIIF_L1_BLACK_LEVEL_MAX_GAIN_VAL ||
> > + param->dstmaxval >
> HWD_VIIF_L1_BLACK_LEVEL_MAX_DST_VAL) {
> > + return -EINVAL;
> > + }
> > +
> > + writel(param->srcblacklevel_gr,
> &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_GR);
> > + writel(param->srcblacklevel_r,
> &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_R);
> > + writel(param->srcblacklevel_b,
> &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVEL_B);
> > + writel(param->srcblacklevel_gb,
> &res->capture_reg->l1isp.L1_BLVC_SRCBLACKLEVELGB);
> > +
> > + writel(param->mulval_gr,
> &res->capture_reg->l1isp.L1_BLVC_MULTVAL_GR);
> > + writel(param->mulval_r,
> &res->capture_reg->l1isp.L1_BLVC_MULTVAL_R);
> > + writel(param->mulval_b,
> &res->capture_reg->l1isp.L1_BLVC_MULTVAL_B);
> > + writel(param->mulval_gb,
> &res->capture_reg->l1isp.L1_BLVC_MULTVAL_GB);
> > +
> > + writel(param->dstmaxval,
> &res->capture_reg->l1isp.L1_BLVC_DSTMAXVAL);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_lsc() - Configure L1ISP lens shading correction
> parameters.
> > + *
> > + * @param: pointer to lens shading correction parameters
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - each parameter of "param" is out of range
> > + * @note when NULL is set to "param"
> > + */
> > +s32 hwd_viif_l1_set_lsc(struct hwd_viif_res *res, const struct hwd_viif_l1_lsc
> *param)
> > +{
> > + u32 sysm_width, sysm_height;
> > + u32 grid_h_size = 0U;
> > + u32 grid_v_size = 0U;
> > + s32 ret = 0;
> > + u32 idx;
> > + u32 val;
> > + u32 tmp;
> > +
> > + if (!param) {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_LSSC_EN);
> > + return 0;
> > + }
> > +
> > + sysm_width = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
> > + sysm_height = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> > +
> > + if (param->lssc_parabola_param) {
> > + if (param->lssc_parabola_param->lssc_para_h_center >=
> sysm_width ||
> > + param->lssc_parabola_param->lssc_para_v_center >=
> sysm_height ||
> > + param->lssc_parabola_param->lssc_para_h_gain >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + param->lssc_parabola_param->lssc_para_v_gain >=
> HWD_VIIF_LSC_MAX_GAIN) {
> > + return -EINVAL;
> > + }
> > +
> > + switch (param->lssc_parabola_param->lssc_para_mgsel2) {
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH:
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH:
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND:
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST:
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + switch (param->lssc_parabola_param->lssc_para_mgsel4) {
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_EIGHTH:
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FOURTH:
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_SECOND:
> > + case HWD_VIIF_L1_PARA_COEF_GAIN_ONE_FIRST:
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + for (idx = 0U; idx < 8U; idx++) {
> > + const struct viif_l1_lsc_parabola_ag_param
> *ag_param;
> > +
> > + switch (idx) {
> > + case 0U:
> > + ag_param =
> ¶m->lssc_parabola_param->r_2d;
> > + break;
> > + case 1U:
> > + ag_param =
> ¶m->lssc_parabola_param->r_4d;
> > + break;
> > + case 2U:
> > + ag_param =
> ¶m->lssc_parabola_param->gr_2d;
> > + break;
> > + case 3U:
> > + ag_param =
> ¶m->lssc_parabola_param->gr_4d;
> > + break;
> > + case 4U:
> > + ag_param =
> ¶m->lssc_parabola_param->gb_2d;
> > + break;
> > + case 5U:
> > + ag_param =
> ¶m->lssc_parabola_param->gb_4d;
> > + break;
> > + case 6U:
> > + ag_param =
> ¶m->lssc_parabola_param->b_2d;
> > + break;
> > + default:
> > + ag_param =
> ¶m->lssc_parabola_param->b_4d;
> > + break;
> > + }
> > +
> > + if (!ag_param || ag_param->lssc_paracoef_h_l_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_h_l_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_h_l_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_h_l_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_h_l_min >
> ag_param->lssc_paracoef_h_l_max ||
> > + ag_param->lssc_paracoef_h_r_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_h_r_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_h_r_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_h_r_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_h_r_min >
> ag_param->lssc_paracoef_h_r_max ||
> > + ag_param->lssc_paracoef_v_u_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_v_u_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_v_u_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_v_u_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_v_u_min >
> ag_param->lssc_paracoef_v_u_max ||
> > + ag_param->lssc_paracoef_v_d_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_v_d_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_v_d_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_v_d_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_v_d_min >
> ag_param->lssc_paracoef_v_d_max ||
> > + ag_param->lssc_paracoef_hv_lu_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_lu_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_lu_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_lu_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_lu_min >
> ag_param->lssc_paracoef_hv_lu_max ||
> > + ag_param->lssc_paracoef_hv_ru_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_ru_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_ru_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_ru_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_ru_min >
> ag_param->lssc_paracoef_hv_ru_max ||
> > + ag_param->lssc_paracoef_hv_ld_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_ld_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_ld_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_ld_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_ld_min >
> ag_param->lssc_paracoef_hv_ld_max ||
> > + ag_param->lssc_paracoef_hv_rd_max <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_rd_max >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_rd_min <
> HWD_VIIF_LSC_MIN_GAIN ||
> > + ag_param->lssc_paracoef_hv_rd_min >=
> HWD_VIIF_LSC_MAX_GAIN ||
> > + ag_param->lssc_paracoef_hv_rd_min >
> ag_param->lssc_paracoef_hv_rd_max) {
> > + return -EINVAL;
> > + }
> > + }
> > + }
> > +
> > + if (param->lssc_grid_param) {
> > + switch (param->lssc_grid_param->lssc_grid_h_size) {
> > + case 32U:
> > + grid_h_size = 5U;
> > + break;
> > + case 64U:
> > + grid_h_size = 6U;
> > + break;
> > + case 128U:
> > + grid_h_size = 7U;
> > + break;
> > + case 256U:
> > + grid_h_size = 8U;
> > + break;
> > + case 512U:
> > + grid_h_size = 9U;
> > + break;
> > + default:
> > + ret = -EINVAL;
> > + break;
> > + }
> > +
> > + if (ret != 0)
> > + return ret;
> > +
> > + switch (param->lssc_grid_param->lssc_grid_v_size) {
> > + case 32U:
> > + grid_v_size = 5U;
> > + break;
> > + case 64U:
> > + grid_v_size = 6U;
> > + break;
> > + case 128U:
> > + grid_v_size = 7U;
> > + break;
> > + case 256U:
> > + grid_v_size = 8U;
> > + break;
> > + case 512U:
> > + grid_v_size = 9U;
> > + break;
> > + default:
> > + ret = -EINVAL;
> > + break;
> > + }
> > +
> > + if (ret != 0)
> > + return ret;
> > +
> > + if (param->lssc_grid_param->lssc_grid_h_center <
> HWD_VIIF_LSC_GRID_MIN_COORDINATE ||
> > + param->lssc_grid_param->lssc_grid_h_center >
> > + param->lssc_grid_param->lssc_grid_h_size) {
> > + return -EINVAL;
> > + }
> > +
> > + if (sysm_width >
> (param->lssc_grid_param->lssc_grid_h_center +
> > +
> (param->lssc_grid_param->lssc_grid_h_size * 31U))) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->lssc_grid_param->lssc_grid_v_center <
> HWD_VIIF_LSC_GRID_MIN_COORDINATE ||
> > + param->lssc_grid_param->lssc_grid_v_center >
> > + param->lssc_grid_param->lssc_grid_v_size) {
> > + return -EINVAL;
> > + }
> > +
> > + if (sysm_height >
> (param->lssc_grid_param->lssc_grid_v_center +
> > +
> (param->lssc_grid_param->lssc_grid_v_size * 23U))) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->lssc_grid_param->lssc_grid_mgsel !=
> HWD_VIIF_L1_GRID_COEF_GAIN_X1 &&
> > + param->lssc_grid_param->lssc_grid_mgsel !=
> HWD_VIIF_L1_GRID_COEF_GAIN_X2) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->lssc_pwhb_r_gain_max >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_r_gain_min >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_r_gain_min > param->lssc_pwhb_r_gain_max
> ||
> > + param->lssc_pwhb_gr_gain_max >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_gr_gain_min >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_gr_gain_min >
> param->lssc_pwhb_gr_gain_max ||
> > + param->lssc_pwhb_gb_gain_max >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_gb_gain_min >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_gb_gain_min >
> param->lssc_pwhb_gb_gain_max ||
> > + param->lssc_pwhb_b_gain_max >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_b_gain_min >=
> HWD_VIIF_LSC_PWB_MAX_COEF_VAL ||
> > + param->lssc_pwhb_b_gain_min >
> param->lssc_pwhb_b_gain_max) {
> > + return -EINVAL;
> > + }
> > +
> > + /* parabola shading */
> > + if (param->lssc_parabola_param) {
> > + struct viif_l1_lsc_parabola_ag_param *r_2d;
> > + struct viif_l1_lsc_parabola_ag_param *r_4d;
> > + struct viif_l1_lsc_parabola_ag_param *gr_2d;
> > + struct viif_l1_lsc_parabola_ag_param *gr_4d;
> > + struct viif_l1_lsc_parabola_ag_param *gb_2d;
> > + struct viif_l1_lsc_parabola_ag_param *gb_4d;
> > + struct viif_l1_lsc_parabola_ag_param *b_2d;
> > + struct viif_l1_lsc_parabola_ag_param *b_4d;
> > +
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_LSSC_PARA_EN);
> > +
> > + writel(param->lssc_parabola_param->lssc_para_h_center,
> > +
> &res->capture_reg->l1isp.L1_LSSC_PARA_H_CENTER);
> > + writel(param->lssc_parabola_param->lssc_para_v_center,
> > +
> &res->capture_reg->l1isp.L1_LSSC_PARA_V_CENTER);
> > +
> > + writel(param->lssc_parabola_param->lssc_para_h_gain,
> > + &res->capture_reg->l1isp.L1_LSSC_PARA_H_GAIN);
> > + writel(param->lssc_parabola_param->lssc_para_v_gain,
> > + &res->capture_reg->l1isp.L1_LSSC_PARA_V_GAIN);
> > +
> > + writel(param->lssc_parabola_param->lssc_para_mgsel2,
> > + &res->capture_reg->l1isp.L1_LSSC_PARA_MGSEL2);
> > + writel(param->lssc_parabola_param->lssc_para_mgsel4,
> > + &res->capture_reg->l1isp.L1_LSSC_PARA_MGSEL4);
> > +
> > + /* R 2D */
> > + r_2d = ¶m->lssc_parabola_param->r_2d;
> > + tmp = (u32)r_2d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_H_L);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_H_R);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_V_U);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_V_D);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_LU);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_ru_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_RU);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_LD);
> > +
> > + tmp = (u32)r_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_2d->lssc_paracoef_hv_rd_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_2D_HV_RD);
> > +
> > + /* R 4D */
> > + r_4d = ¶m->lssc_parabola_param->r_4d;
> > + tmp = (u32)r_4d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_H_L);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_H_R);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_V_U);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_V_D);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_LU);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_ru_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_RU);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_LD);
> > +
> > + tmp = (u32)r_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(r_4d->lssc_paracoef_hv_rd_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_R_COEF_4D_HV_RD);
> > +
> > + /* GR 2D */
> > + gr_2d = ¶m->lssc_parabola_param->gr_2d;
> > + tmp = (u32)gr_2d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_H_L);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_H_R);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_V_U);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_V_D);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_LU);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_ru_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_RU);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_LD);
> > +
> > + tmp = (u32)gr_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_2d->lssc_paracoef_hv_rd_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_2D_HV_RD);
> > +
> > + /* GR 4D */
> > + gr_4d = ¶m->lssc_parabola_param->gr_4d;
> > + tmp = (u32)gr_4d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_H_L);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_H_R);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_V_U);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_V_D);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_LU);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_ru_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_RU);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_LD);
> > +
> > + tmp = (u32)gr_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gr_4d->lssc_paracoef_hv_rd_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GR_COEF_4D_HV_RD);
> > +
> > + /* GB 2D */
> > + gb_2d = ¶m->lssc_parabola_param->gb_2d;
> > + tmp = (u32)gb_2d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_H_L);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_H_R);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_V_U);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_V_D);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_LU);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_ru_min
> & 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_RU);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_LD);
> > +
> > + tmp = (u32)gb_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_2d->lssc_paracoef_hv_rd_min
> & 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_2D_HV_RD);
> > +
> > + /* GB 4D */
> > + gb_4d = ¶m->lssc_parabola_param->gb_4d;
> > + tmp = (u32)gb_4d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_H_L);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_H_R);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_V_U);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_V_D);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_LU);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_ru_min
> & 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_RU);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_LD);
> > +
> > + tmp = (u32)gb_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(gb_4d->lssc_paracoef_hv_rd_min
> & 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_GB_COEF_4D_HV_RD);
> > +
> > + /* B 2D */
> > + b_2d = ¶m->lssc_parabola_param->b_2d;
> > + tmp = (u32)b_2d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_H_L);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_H_R);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_V_U);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_V_D);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_LU);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_ru_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_RU);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_LD);
> > +
> > + tmp = (u32)b_2d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_2d->lssc_paracoef_hv_rd_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_2D_HV_RD);
> > +
> > + /* B 4D */
> > + b_4d = ¶m->lssc_parabola_param->b_4d;
> > + tmp = (u32)b_4d->lssc_paracoef_h_l_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_h_l_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_H_L);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_h_r_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_h_r_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_H_R);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_v_u_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_v_u_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_V_U);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_v_d_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_v_d_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_V_D);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_hv_lu_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_lu_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_LU);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_hv_ru_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_ru_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_RU);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_hv_ld_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_ld_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_LD);
> > +
> > + tmp = (u32)b_4d->lssc_paracoef_hv_rd_max & 0x1fffU;
> > + val = (tmp << 16U) | (u32)(b_4d->lssc_paracoef_hv_rd_min &
> 0x1fffU);
> > + writel(val,
> &res->capture_reg->l1isp.L1_LSSC_PARA_B_COEF_4D_HV_RD);
> > +
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_LSSC_PARA_EN);
> > + }
> > +
> > + /* grid shading */
> > + if (param->lssc_grid_param) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_LSSC_GRID_EN);
> > + writel(grid_h_size,
> &res->capture_reg->l1isp.L1_LSSC_GRID_H_SIZE);
> > + writel(grid_v_size,
> &res->capture_reg->l1isp.L1_LSSC_GRID_V_SIZE);
> > + writel(param->lssc_grid_param->lssc_grid_h_center,
> > +
> &res->capture_reg->l1isp.L1_LSSC_GRID_H_CENTER);
> > + writel(param->lssc_grid_param->lssc_grid_v_center,
> > +
> &res->capture_reg->l1isp.L1_LSSC_GRID_V_CENTER);
> > + writel(param->lssc_grid_param->lssc_grid_mgsel,
> > + &res->capture_reg->l1isp.L1_LSSC_GRID_MGSEL);
> > +
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_LSSC_GRID_EN);
> > + }
> > +
> > + /* preset white balance */
> > + val = (param->lssc_pwhb_r_gain_max << 16U) |
> (param->lssc_pwhb_r_gain_min);
> > + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_R_GAIN);
> > +
> > + val = (param->lssc_pwhb_gr_gain_max << 16U) |
> (param->lssc_pwhb_gr_gain_min);
> > + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_GR_GAIN);
> > +
> > + val = (param->lssc_pwhb_gb_gain_max << 16U) |
> (param->lssc_pwhb_gb_gain_min);
> > + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_GB_GAIN);
> > +
> > + val = (param->lssc_pwhb_b_gain_max << 16U) |
> (param->lssc_pwhb_b_gain_min);
> > + writel(val, &res->capture_reg->l1isp.L1_LSSC_PWHB_B_GAIN);
> > +
> > + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_LSSC_EN);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_lsc_table_transmission() - Configure L1ISP transferring
> lens shading grid table.
> > + *
> > + * @table_gr: grid shading table for Gr(physical address)
> > + * @table_r: grid shading table for R(physical address)
> > + * @table_b: grid shading table for B(physical address)
> > + * @table_gb: grid shading table for Gb(physical address)
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "table_h", "table_m" or "table_l" is not 8byte alignment
> > + *
> > + * Note that when 0 is set to table address, table transfer of the table is
> disabled.
> > + */
> > +s32 hwd_viif_l1_set_lsc_table_transmission(struct hwd_viif_res *res,
> uintptr_t table_gr,
> > + uintptr_t table_r, uintptr_t table_b,
> uintptr_t table_gb)
> > +{
> > + u32 val = 0x0U;
> > +
> > + if (((table_gr % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> > + ((table_r % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> > + ((table_b % HWD_VIIF_L1_VDM_ALIGN) != 0U) ||
> > + ((table_gb % HWD_VIIF_L1_VDM_ALIGN) != 0U)) {
> > + return -EINVAL;
> > + }
> > + /* VDM common settings */
> > + writel(HWD_VIIF_L1_VDM_CFG_PARAM,
> &res->capture_reg->vdm.t_group[0].VDM_T_CFG);
> > + writel(HWD_VIIF_L1_VDM_SRAM_BASE,
> &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_BASE);
> > + writel(HWD_VIIF_L1_VDM_SRAM_SIZE,
> &res->capture_reg->vdm.t_group[0].VDM_T_SRAM_SIZE);
> > +
> > + if (table_gr != 0U) {
> > + writel((u32)table_gr,
> &res->capture_reg->vdm.t_port[4].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[4].VDM_T_SIZE);
> > + val |= 0x10U;
> > + }
> > +
> > + if (table_r != 0U) {
> > + writel((u32)table_r,
> &res->capture_reg->vdm.t_port[5].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[5].VDM_T_SIZE);
> > + val |= 0x20U;
> > + }
> > +
> > + if (table_b != 0U) {
> > + writel((u32)table_b,
> &res->capture_reg->vdm.t_port[6].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[6].VDM_T_SIZE);
> > + val |= 0x40U;
> > + }
> > +
> > + if (table_gb != 0U) {
> > + writel((u32)table_gb,
> &res->capture_reg->vdm.t_port[7].VDM_T_STADR);
> > + writel(HWD_VIIF_L1_VDM_LSC_TABLE_SIZE,
> &res->capture_reg->vdm.t_port[7].VDM_T_SIZE);
> > + val |= 0x80U;
> > + }
> > +
> > + val |= (readl(&res->capture_reg->vdm.VDM_T_ENABLE) &
> 0xffffff0fU);
> > + writel(val, &res->capture_reg->vdm.VDM_T_ENABLE);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_main_process() - Configure L1ISP main process.
> > + *
> > + * @demosaic_mode: demosaic mode @ref hwd_viif_l1_demosaic
> > + * @damp_lsbsel: output pixel clip range for auto white balance [0..15]
> > + * @color_matrix: pointer to color matrix correction parameters
> > + * @dst_maxval: output pixel maximum value [0x0..0xffffff]
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * main process means digital amp, demosaic, and color matrix correction
> > + * NULL means disabling color matrix correction
> > + * - "demosaic_mode" is neither HWD_VIIF_L1_DEMOSAIC_ACPI nor
> HWD_VIIF_L1_DEMOSAIC_DMG
> > + * - "damp_lsbsel" is out of range
> > + * - each parameter of "color_matrix" is out of range
> > + * - "dst_maxval" is out of range
> > + */
> > +s32 hwd_viif_l1_set_main_process(struct hwd_viif_res *res, u32
> demosaic_mode, u32 damp_lsbsel,
> > + const struct viif_l1_color_matrix_correction
> *color_matrix,
> > + u32 dst_maxval)
> > +{
> > + u32 val;
> > +
> > + if (demosaic_mode != HWD_VIIF_L1_DEMOSAIC_ACPI &&
> > + demosaic_mode != HWD_VIIF_L1_DEMOSAIC_DMG) {
> > + return -EINVAL;
> > + }
> > +
> > + if (damp_lsbsel > HWD_VIIF_DAMP_MAX_LSBSEL)
> > + return -EINVAL;
> > +
> > + if (color_matrix) {
> > + if (color_matrix->coef_rmg_min >
> color_matrix->coef_rmg_max ||
> > + color_matrix->coef_rmb_min >
> color_matrix->coef_rmb_max ||
> > + color_matrix->coef_gmr_min >
> color_matrix->coef_gmr_max ||
> > + color_matrix->coef_gmb_min >
> color_matrix->coef_gmb_max ||
> > + color_matrix->coef_bmr_min >
> color_matrix->coef_bmr_max ||
> > + color_matrix->coef_bmg_min >
> color_matrix->coef_bmg_max ||
> > + (u32)color_matrix->dst_minval > dst_maxval)
> > + return -EINVAL;
> > + }
> > +
> > + if (dst_maxval > HWD_VIIF_MAIN_PROCESS_MAX_OUT_PIXEL_VAL)
> > + return -EINVAL;
> > +
> > + val = damp_lsbsel << 4U;
> > + writel(val, &res->capture_reg->l1isp.L1_MPRO_CONF);
> > +
> > + writel(demosaic_mode,
> &res->capture_reg->l1isp.L1_MPRO_LCS_MODE);
> > +
> > + if (color_matrix) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_MPRO_SW);
> > +
> > + val = (u32)color_matrix->coef_rmg_min & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_RMG_MIN);
> > +
> > + val = (u32)color_matrix->coef_rmg_max & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_RMG_MAX);
> > +
> > + val = (u32)color_matrix->coef_rmb_min & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_RMB_MIN);
> > +
> > + val = (u32)color_matrix->coef_rmb_max & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_RMB_MAX);
> > +
> > + val = (u32)color_matrix->coef_gmr_min & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_GMR_MIN);
> > +
> > + val = (u32)color_matrix->coef_gmr_max & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_GMR_MAX);
> > +
> > + val = (u32)color_matrix->coef_gmb_min & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_GMB_MIN);
> > +
> > + val = (u32)color_matrix->coef_gmb_max & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_GMB_MAX);
> > +
> > + val = (u32)color_matrix->coef_bmr_min & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_BMR_MIN);
> > +
> > + val = (u32)color_matrix->coef_bmr_max & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_BMR_MAX);
> > +
> > + val = (u32)color_matrix->coef_bmg_min & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_BMG_MIN);
> > +
> > + val = (u32)color_matrix->coef_bmg_max & 0xffffU;
> > + writel(val,
> &res->capture_reg->l1isp.L1_MPRO_LM0_BMG_MAX);
> > +
> > + writel((u32)color_matrix->dst_minval,
> &res->capture_reg->l1isp.L1_MPRO_DST_MINVAL);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_MPRO_SW);
> > + }
> > +
> > + writel(dst_maxval,
> &res->capture_reg->l1isp.L1_MPRO_DST_MAXVAL);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_awb() - Configure L1ISP auto white balance parameters.
> > + *
> > + * @param: pointer to auto white balance parameters; NULL means disabling
> auto white balance
> > + * @awhb_wbmrg: R gain of white balance adjustment [0x40..0x3FF]
> accuracy: 1/256
> > + * @awhb_wbmgg: G gain of white balance adjustment [0x40..0x3FF]
> accuracy: 1/256
> > + * @awhb_wbmbg: B gain of white balance adjustment [0x40..0x3FF]
> accuracy: 1/256
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL
> > + * - each parameter of "param" is out of range
> > + * - awhb_wbm*g is out of range
> > + */
> > +s32 hwd_viif_l1_set_awb(struct hwd_viif_res *res, const struct viif_l1_awb
> *param, u32 awhb_wbmrg,
> > + u32 awhb_wbmgg, u32 awhb_wbmbg)
> > +{
> > + u32 val, ygate_data;
> > +
> > + if (awhb_wbmrg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmrg >=
> HWD_VIIF_AWB_MAX_GAIN ||
> > + awhb_wbmgg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmgg >=
> HWD_VIIF_AWB_MAX_GAIN ||
> > + awhb_wbmbg < HWD_VIIF_AWB_MIN_GAIN || awhb_wbmbg >=
> HWD_VIIF_AWB_MAX_GAIN) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param) {
> > + if (param->awhb_ygate_sel != HWD_VIIF_ENABLE &&
> > + param->awhb_ygate_sel != HWD_VIIF_DISABLE) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->awhb_ygate_data != 64U &&
> param->awhb_ygate_data != 128U &&
> > + param->awhb_ygate_data != 256U &&
> param->awhb_ygate_data != 512U) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->awhb_cgrange !=
> HWD_VIIF_L1_AWB_ONE_SECOND &&
> > + param->awhb_cgrange != HWD_VIIF_L1_AWB_X1 &&
> > + param->awhb_cgrange != HWD_VIIF_L1_AWB_X2 &&
> > + param->awhb_cgrange != HWD_VIIF_L1_AWB_X4) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->awhb_ygatesw != HWD_VIIF_ENABLE &&
> > + param->awhb_ygatesw != HWD_VIIF_DISABLE) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->awhb_hexsw != HWD_VIIF_ENABLE &&
> param->awhb_hexsw != HWD_VIIF_DISABLE)
> > + return -EINVAL;
> > +
> > + if (param->awhb_areamode !=
> HWD_VIIF_L1_AWB_AREA_MODE0 &&
> > + param->awhb_areamode !=
> HWD_VIIF_L1_AWB_AREA_MODE1 &&
> > + param->awhb_areamode !=
> HWD_VIIF_L1_AWB_AREA_MODE2 &&
> > + param->awhb_areamode !=
> HWD_VIIF_L1_AWB_AREA_MODE3) {
> > + return -EINVAL;
> > + }
> > +
> > + val = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
> > + if (param->awhb_area_hsize < 1U ||
> (param->awhb_area_hsize > ((val - 8U) / 8U)) ||
> > + param->awhb_area_hofs > (val - 9U)) {
> > + return -EINVAL;
> > + }
> > +
> > + val = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> > + if (param->awhb_area_vsize < 1U ||
> (param->awhb_area_vsize > ((val - 4U) / 8U)) ||
> > + param->awhb_area_vofs > (val - 5U)) {
> > + return -EINVAL;
> > + }
> > +
> > + if ((param->awhb_sq_sw[0] != HWD_VIIF_ENABLE &&
> > + param->awhb_sq_sw[0] != HWD_VIIF_DISABLE) ||
> > + (param->awhb_sq_sw[1] != HWD_VIIF_ENABLE &&
> > + param->awhb_sq_sw[1] != HWD_VIIF_DISABLE) ||
> > + (param->awhb_sq_sw[2] != HWD_VIIF_ENABLE &&
> > + param->awhb_sq_sw[2] != HWD_VIIF_DISABLE) ||
> > + (param->awhb_sq_pol[0] != HWD_VIIF_ENABLE &&
> > + param->awhb_sq_pol[0] != HWD_VIIF_DISABLE) ||
> > + (param->awhb_sq_pol[1] != HWD_VIIF_ENABLE &&
> > + param->awhb_sq_pol[1] != HWD_VIIF_DISABLE) ||
> > + (param->awhb_sq_pol[2] != HWD_VIIF_ENABLE &&
> > + param->awhb_sq_pol[2] != HWD_VIIF_DISABLE)) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->awhb_bycut0p >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_bycut0n >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_rycut0p >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_rycut0n >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_rbcut0h < HWD_VIIF_AWB_GATE_LOWER
> ||
> > + param->awhb_rbcut0h > HWD_VIIF_AWB_GATE_UPPER
> ||
> > + param->awhb_rbcut0l < HWD_VIIF_AWB_GATE_LOWER
> ||
> > + param->awhb_rbcut0l > HWD_VIIF_AWB_GATE_UPPER
> ||
> > + param->awhb_bycut_h[0] <
> HWD_VIIF_AWB_GATE_LOWER ||
> > + param->awhb_bycut_h[0] >
> HWD_VIIF_AWB_GATE_UPPER ||
> > + param->awhb_bycut_h[1] <
> HWD_VIIF_AWB_GATE_LOWER ||
> > + param->awhb_bycut_h[1] >
> HWD_VIIF_AWB_GATE_UPPER ||
> > + param->awhb_bycut_h[2] <
> HWD_VIIF_AWB_GATE_LOWER ||
> > + param->awhb_bycut_h[2] >
> HWD_VIIF_AWB_GATE_UPPER ||
> > + param->awhb_bycut_l[0] >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_bycut_l[1] >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_bycut_l[2] >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_rycut_h[0] <
> HWD_VIIF_AWB_GATE_LOWER ||
> > + param->awhb_rycut_h[0] >
> HWD_VIIF_AWB_GATE_UPPER ||
> > + param->awhb_rycut_h[1] <
> HWD_VIIF_AWB_GATE_LOWER ||
> > + param->awhb_rycut_h[1] >
> HWD_VIIF_AWB_GATE_UPPER ||
> > + param->awhb_rycut_h[2] <
> HWD_VIIF_AWB_GATE_LOWER ||
> > + param->awhb_rycut_h[2] >
> HWD_VIIF_AWB_GATE_UPPER ||
> > + param->awhb_rycut_l[0] >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_rycut_l[1] >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_rycut_l[2] >
> HWD_VIIF_AWB_UNSIGNED_GATE_UPPER ||
> > + param->awhb_awbsftu < HWD_VIIF_AWB_GATE_LOWER
> ||
> > + param->awhb_awbsftu > HWD_VIIF_AWB_GATE_UPPER
> ||
> > + param->awhb_awbsftv < HWD_VIIF_AWB_GATE_LOWER
> ||
> > + param->awhb_awbsftv > HWD_VIIF_AWB_GATE_UPPER
> ||
> > + (param->awhb_awbhuecor != HWD_VIIF_ENABLE &&
> > + param->awhb_awbhuecor != HWD_VIIF_DISABLE)) {
> > + return -EINVAL;
> > + }
> > +
> > + if (param->awhb_awbspd >
> HWD_VIIF_AWB_MAX_UV_CONVERGENCE_SPEED ||
> > + param->awhb_awbulv >
> HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL ||
> > + param->awhb_awbvlv >
> HWD_VIIF_AWB_MAX_UV_CONVERGENCE_LEVEL ||
> > + param->awhb_awbondot >
> HWD_VIIF_AWB_INTEGRATION_STOP_TH) {
> > + return -EINVAL;
> > + }
> > +
> > + switch (param->awhb_awbfztim) {
> > + case HWD_VIIF_L1_AWB_RESTART_NO:
> > + case HWD_VIIF_L1_AWB_RESTART_128FRAME:
> > + case HWD_VIIF_L1_AWB_RESTART_64FRAME:
> > + case HWD_VIIF_L1_AWB_RESTART_32FRAME:
> > + case HWD_VIIF_L1_AWB_RESTART_16FRAME:
> > + case HWD_VIIF_L1_AWB_RESTART_8FRAME:
> > + case HWD_VIIF_L1_AWB_RESTART_4FRAME:
> > + case HWD_VIIF_L1_AWB_RESTART_2FRAME:
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + writel(awhb_wbmrg, &res->capture_reg->l1isp.L1_AWHB_WBMRG);
> > + writel(awhb_wbmgg, &res->capture_reg->l1isp.L1_AWHB_WBMGG);
> > + writel(awhb_wbmbg, &res->capture_reg->l1isp.L1_AWHB_WBMBG);
> > +
> > + val = readl(&res->capture_reg->l1isp.L1_AWHB_SW) & 0xffffff7fU;
> > +
> > + if (param) {
> > + val |= (HWD_VIIF_ENABLE << 7U);
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
> > +
> > + if (param->awhb_ygate_data == 64U)
> > + ygate_data = 0U;
> > + else if (param->awhb_ygate_data == 128U)
> > + ygate_data = 1U;
> > + else if (param->awhb_ygate_data == 256U)
> > + ygate_data = 2U;
> > + else
> > + ygate_data = 3U;
> > +
> > + val = (param->awhb_ygate_sel << 7U) | (ygate_data << 5U) |
> (param->awhb_cgrange);
> > + writel(val,
> &res->capture_reg->l1isp.L1_AWHB_GATE_CONF0);
> > +
> > + val = (param->awhb_ygatesw << 5U) | (param->awhb_hexsw
> << 4U) |
> > + (param->awhb_areamode);
> > + writel(val,
> &res->capture_reg->l1isp.L1_AWHB_GATE_CONF1);
> > +
> > + writel(param->awhb_area_hsize,
> &res->capture_reg->l1isp.L1_AWHB_AREA_HSIZE);
> > + writel(param->awhb_area_vsize,
> &res->capture_reg->l1isp.L1_AWHB_AREA_VSIZE);
> > + writel(param->awhb_area_hofs,
> &res->capture_reg->l1isp.L1_AWHB_AREA_HOFS);
> > + writel(param->awhb_area_vofs,
> &res->capture_reg->l1isp.L1_AWHB_AREA_VOFS);
> > +
> > + writel(param->awhb_area_maskh,
> &res->capture_reg->l1isp.L1_AWHB_AREA_MASKH);
> > + writel(param->awhb_area_maskl,
> &res->capture_reg->l1isp.L1_AWHB_AREA_MASKL);
> > +
> > + val = (param->awhb_sq_sw[0] << 7U) |
> (param->awhb_sq_pol[0] << 6U) |
> > + (param->awhb_sq_sw[1] << 5U) |
> (param->awhb_sq_pol[1] << 4U) |
> > + (param->awhb_sq_sw[2] << 3U) |
> (param->awhb_sq_pol[2] << 2U);
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_SQ_CONF);
> > +
> > + writel((u32)param->awhb_ygateh,
> &res->capture_reg->l1isp.L1_AWHB_YGATEH);
> > + writel((u32)param->awhb_ygatel,
> &res->capture_reg->l1isp.L1_AWHB_YGATEL);
> > +
> > + writel(param->awhb_bycut0p,
> &res->capture_reg->l1isp.L1_AWHB_BYCUT0P);
> > + writel(param->awhb_bycut0n,
> &res->capture_reg->l1isp.L1_AWHB_BYCUT0N);
> > + writel(param->awhb_rycut0p,
> &res->capture_reg->l1isp.L1_AWHB_RYCUT0P);
> > + writel(param->awhb_rycut0n,
> &res->capture_reg->l1isp.L1_AWHB_RYCUT0N);
> > +
> > + val = (u32)param->awhb_rbcut0h & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_RBCUT0H);
> > + val = (u32)param->awhb_rbcut0l & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_RBCUT0L);
> > +
> > + val = (u32)param->awhb_bycut_h[0] & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT1H);
> > + writel(param->awhb_bycut_l[0],
> &res->capture_reg->l1isp.L1_AWHB_BYCUT1L);
> > + val = (u32)param->awhb_bycut_h[1] & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT2H);
> > + writel(param->awhb_bycut_l[1],
> &res->capture_reg->l1isp.L1_AWHB_BYCUT2L);
> > + val = (u32)param->awhb_bycut_h[2] & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_BYCUT3H);
> > + writel(param->awhb_bycut_l[2],
> &res->capture_reg->l1isp.L1_AWHB_BYCUT3L);
> > +
> > + val = (u32)param->awhb_rycut_h[0] & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT1H);
> > + writel(param->awhb_rycut_l[0],
> &res->capture_reg->l1isp.L1_AWHB_RYCUT1L);
> > + val = (u32)param->awhb_rycut_h[1] & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT2H);
> > + writel(param->awhb_rycut_l[1],
> &res->capture_reg->l1isp.L1_AWHB_RYCUT2L);
> > + val = (u32)param->awhb_rycut_h[2] & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_RYCUT3H);
> > + writel(param->awhb_rycut_l[2],
> &res->capture_reg->l1isp.L1_AWHB_RYCUT3L);
> > +
> > + val = (u32)param->awhb_awbsftu & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSFTU);
> > + val = (u32)param->awhb_awbsftv & 0xffU;
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSFTV);
> > +
> > + val = (param->awhb_awbhuecor << 4U) |
> (param->awhb_awbspd);
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_AWBSPD);
> > +
> > + writel(param->awhb_awbulv,
> &res->capture_reg->l1isp.L1_AWHB_AWBULV);
> > + writel(param->awhb_awbvlv,
> &res->capture_reg->l1isp.L1_AWHB_AWBVLV);
> > + writel((u32)param->awhb_awbwait,
> &res->capture_reg->l1isp.L1_AWHB_AWBWAIT);
> > +
> > + writel(param->awhb_awbondot,
> &res->capture_reg->l1isp.L1_AWHB_AWBONDOT);
> > + writel(param->awhb_awbfztim,
> &res->capture_reg->l1isp.L1_AWHB_AWBFZTIM);
> > +
> > + writel((u32)param->awhb_wbgrmax,
> &res->capture_reg->l1isp.L1_AWHB_WBGRMAX);
> > + writel((u32)param->awhb_wbgbmax,
> &res->capture_reg->l1isp.L1_AWHB_WBGBMAX);
> > + writel((u32)param->awhb_wbgrmin,
> &res->capture_reg->l1isp.L1_AWHB_WBGRMIN);
> > + writel((u32)param->awhb_wbgbmin,
> &res->capture_reg->l1isp.L1_AWHB_WBGBMIN);
> > +
> > + } else {
> > + /* disable awb */
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_lock_awb_gain() - Configure L1ISP lock auto white balance
> gain.
> > + *
> > + * @enable: enable/disable lock AWB gain
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - "enable" is neither HWD_VIIF_ENABLE nor HWD_VIIF_DISABLE
> > + */
> > +s32 hwd_viif_l1_lock_awb_gain(struct hwd_viif_res *res, u32 enable)
> > +{
> > + u32 val;
> > +
> > + if (enable != HWD_VIIF_ENABLE && enable != HWD_VIIF_DISABLE)
> > + return -EINVAL;
> > +
> > + val = readl(&res->capture_reg->l1isp.L1_AWHB_SW) & 0xffffffdfU;
> > + val |= (enable << 5U);
> > + writel(val, &res->capture_reg->l1isp.L1_AWHB_SW);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_hdrc() - Configure L1ISP HDR compression parameters.
> > + *
> > + * @param: pointer to HDR compression parameters
> > + * @hdrc_thr_sft_amt: shift value in case of through mode [0..8]
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - each parameter of "param" is out of range
> > + * - hdrc_thr_sft_amt is out of range when param is NULL
> > + * - hdrc_thr_sft_amt is not 0 when param is not NULL
> > + */
> > +s32 hwd_viif_l1_set_hdrc(struct hwd_viif_res *res, const struct viif_l1_hdrc
> *param,
> > + u32 hdrc_thr_sft_amt)
> > +{
> > + u32 val, sw_delay1;
> > +
> > + if (!param) {
> > + if (hdrc_thr_sft_amt >
> HWD_VIIF_L1_HDRC_MAX_THROUGH_SHIFT_VAL)
> > + return -EINVAL;
> > +
> > + writel(hdrc_thr_sft_amt,
> &res->capture_reg->l1isp.L1_HDRC_THR_SFT_AMT);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_HDRC_EN);
> > +
> > + return 0;
> > + }
> > +
> > + if (hdrc_thr_sft_amt != 0U || param->hdrc_ratio <
> HWD_VIIF_L1_HDRC_MIN_INPUT_DATA_WIDTH ||
> > + param->hdrc_ratio >
> HWD_VIIF_L1_HDRC_MAX_INPUT_DATA_WIDTH ||
> > + param->hdrc_pt_ratio > HWD_VIIF_L1_HDRC_MAX_PT_SLOPE ||
> > + param->hdrc_pt_blend >
> HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
> > + param->hdrc_pt_blend2 >
> HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
> > + (param->hdrc_pt_blend + param->hdrc_pt_blend2) >
> HWD_VIIF_L1_HDRC_MAX_BLEND_RATIO ||
> > + (param->hdrc_tn_type != HWD_VIIF_L1_HDRC_TONE_USER &&
> > + param->hdrc_tn_type != HWD_VIIF_L1_HDRC_TONE_PRESET)
> ||
> > + param->hdrc_flr_val > HWD_VIIF_L1_HDRC_MAX_FLARE_VAL ||
> > + (param->hdrc_flr_adp != HWD_VIIF_ENABLE &&
> param->hdrc_flr_adp != HWD_VIIF_DISABLE) ||
> > + (param->hdrc_ybr_off != HWD_VIIF_ENABLE &&
> param->hdrc_ybr_off != HWD_VIIF_DISABLE) ||
> > + param->hdrc_orgy_blend >
> HWD_VIIF_L1_HDRC_MAX_BLEND_LUMA) {
> > + return -EINVAL;
> > + }
> > +
> > + writel((param->hdrc_ratio - HWD_VIIF_L1_HDRC_RATIO_OFFSET),
> > + &res->capture_reg->l1isp.L1_HDRC_RATIO);
> > + writel(param->hdrc_pt_ratio,
> &res->capture_reg->l1isp.L1_HDRC_PT_RATIO);
> > +
> > + writel(param->hdrc_pt_blend,
> &res->capture_reg->l1isp.L1_HDRC_PT_BLEND);
> > + writel(param->hdrc_pt_blend2,
> &res->capture_reg->l1isp.L1_HDRC_PT_BLEND2);
> > +
> > + writel(param->hdrc_pt_sat,
> &res->capture_reg->l1isp.L1_HDRC_PT_SAT);
> > + writel(param->hdrc_tn_type,
> &res->capture_reg->l1isp.L1_HDRC_TN_TYPE);
> > +
> > + writel(param->hdrc_utn_tbl[0],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL0);
> > + writel(param->hdrc_utn_tbl[1],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL1);
> > + writel(param->hdrc_utn_tbl[2],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL2);
> > + writel(param->hdrc_utn_tbl[3],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL3);
> > + writel(param->hdrc_utn_tbl[4],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL4);
> > + writel(param->hdrc_utn_tbl[5],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL5);
> > + writel(param->hdrc_utn_tbl[6],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL6);
> > + writel(param->hdrc_utn_tbl[7],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL7);
> > + writel(param->hdrc_utn_tbl[8],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL8);
> > + writel(param->hdrc_utn_tbl[9],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL9);
> > + writel(param->hdrc_utn_tbl[10],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL10);
> > + writel(param->hdrc_utn_tbl[11],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL11);
> > + writel(param->hdrc_utn_tbl[12],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL12);
> > + writel(param->hdrc_utn_tbl[13],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL13);
> > + writel(param->hdrc_utn_tbl[14],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL14);
> > + writel(param->hdrc_utn_tbl[15],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL15);
> > + writel(param->hdrc_utn_tbl[16],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL16);
> > + writel(param->hdrc_utn_tbl[17],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL17);
> > + writel(param->hdrc_utn_tbl[18],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL18);
> > + writel(param->hdrc_utn_tbl[19],
> &res->capture_reg->l1isp.L1_HDRC_UTN_TBL19);
> > +
> > + writel(param->hdrc_flr_val,
> &res->capture_reg->l1isp.L1_HDRC_FLR_VAL);
> > + writel(param->hdrc_flr_adp,
> &res->capture_reg->l1isp.L1_HDRC_FLR_ADP);
> > +
> > + writel(param->hdrc_ybr_off,
> &res->capture_reg->l1isp.L1_HDRC_YBR_OFF);
> > + writel(param->hdrc_orgy_blend,
> &res->capture_reg->l1isp.L1_HDRC_ORGY_BLEND);
> > +
> > + val = ((readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT)) % 64U) /
> 2U;
> > + writel(val, &res->capture_reg->l1isp.L1_HDRC_MAR_TOP);
> > + val = ((readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH)) % 64U) /
> 2U;
> > + writel(val, &res->capture_reg->l1isp.L1_HDRC_MAR_LEFT);
> > +
> > + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_HDRC_EN);
> > +
> > + /* update of sw_delay1 must be done when MAIN unit is NOT running.
> */
> > + if (!res->run_flag_main) {
> > + sw_delay1 = (u32)((HWD_VIIF_REGBUF_ACCESS_TIME *
> (u64)res->pixel_clock) /
> > + ((u64)res->htotal_size *
> HWD_VIIF_SYS_CLK)) +
> > + HWD_VIIF_L1_DELAY_W_HDRC + 1U;
> > + val = readl(&res->capture_reg->sys.INT_M1_LINE) & 0xffffU;
> > + val |= (sw_delay1 << 16U);
> > + writel(val, &res->capture_reg->sys.INT_M1_LINE);
> > + /* M2_LINE is the same condition as M1_LINE */
> > + writel(val, &res->capture_reg->sys.INT_M2_LINE);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_hdrc_ltm() - Configure L1ISP HDR compression local tone
> mapping parameters.
> > + *
> > + * @param: pointer to HDR compression local tone mapping parameters
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL
> > + * - "param" is NULL
> > + * - each parameter of "param" is out of range
> > + */
> > +s32 hwd_viif_l1_set_hdrc_ltm(struct hwd_viif_res *res, const struct
> viif_l1_hdrc_ltm_config *param)
> > +{
> > + u32 val;
> > + u32 idx;
> > +
> > + if (!param || param->tnp_max >=
> HWD_VIIF_L1_HDRC_MAX_LTM_TONE_BLEND_RATIO ||
> > + param->tnp_mag >=
> HWD_VIIF_L1_HDRC_MAX_LTM_MAGNIFICATION) {
> > + return -EINVAL;
> > + }
> > +
> > + val = (u32)param->tnp_fil[0];
> > + for (idx = 1; idx < 5U; idx++)
> > + val += (u32)param->tnp_fil[idx] * 2U;
> > +
> > + if (val != 1024U)
> > + return -EINVAL;
> > +
> > + writel(param->tnp_max,
> &res->capture_reg->l1isp.L1_HDRC_TNP_MAX);
> > +
> > + writel(param->tnp_mag,
> &res->capture_reg->l1isp.L1_HDRC_TNP_MAG);
> > +
> > + writel((u32)param->tnp_fil[0],
> &res->capture_reg->l1isp.L1_HDRC_TNP_FIL0);
> > + writel((u32)param->tnp_fil[1],
> &res->capture_reg->l1isp.L1_HDRC_TNP_FIL1);
> > + writel((u32)param->tnp_fil[2],
> &res->capture_reg->l1isp.L1_HDRC_TNP_FIL2);
> > + writel((u32)param->tnp_fil[3],
> &res->capture_reg->l1isp.L1_HDRC_TNP_FIL3);
> > + writel((u32)param->tnp_fil[4],
> &res->capture_reg->l1isp.L1_HDRC_TNP_FIL4);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_gamma() - Configure L1ISP gamma correction
> parameters.
> > + *
> > + * @param: pointer to gamma correction parameters
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - each parameter of "param" is out of range
> > + */
> > +s32 hwd_viif_l1_set_gamma(struct hwd_viif_res *res, const struct
> viif_l1_gamma *param)
> > +{
> > + u32 idx;
> > +
> > + if (!param) {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_PGC_SW);
> > + return 0;
> > + }
> > +
> > + for (idx = 0; idx < 44U; idx++) {
> > + if (param->gam_p[idx] > HWD_VIIF_L1_GAMMA_MAX_VAL)
> > + return -EINVAL;
> > + }
> > +
> > + writel(param->gam_p[0],
> &res->capture_reg->l1isp.L1_VPRO_GAM01P);
> > + writel(param->gam_p[1],
> &res->capture_reg->l1isp.L1_VPRO_GAM02P);
> > + writel(param->gam_p[2],
> &res->capture_reg->l1isp.L1_VPRO_GAM03P);
> > + writel(param->gam_p[3],
> &res->capture_reg->l1isp.L1_VPRO_GAM04P);
> > + writel(param->gam_p[4],
> &res->capture_reg->l1isp.L1_VPRO_GAM05P);
> > + writel(param->gam_p[5],
> &res->capture_reg->l1isp.L1_VPRO_GAM06P);
> > + writel(param->gam_p[6],
> &res->capture_reg->l1isp.L1_VPRO_GAM07P);
> > + writel(param->gam_p[7],
> &res->capture_reg->l1isp.L1_VPRO_GAM08P);
> > + writel(param->gam_p[8],
> &res->capture_reg->l1isp.L1_VPRO_GAM09P);
> > + writel(param->gam_p[9],
> &res->capture_reg->l1isp.L1_VPRO_GAM10P);
> > + writel(param->gam_p[10],
> &res->capture_reg->l1isp.L1_VPRO_GAM11P);
> > + writel(param->gam_p[11],
> &res->capture_reg->l1isp.L1_VPRO_GAM12P);
> > + writel(param->gam_p[12],
> &res->capture_reg->l1isp.L1_VPRO_GAM13P);
> > + writel(param->gam_p[13],
> &res->capture_reg->l1isp.L1_VPRO_GAM14P);
> > + writel(param->gam_p[14],
> &res->capture_reg->l1isp.L1_VPRO_GAM15P);
> > + writel(param->gam_p[15],
> &res->capture_reg->l1isp.L1_VPRO_GAM16P);
> > + writel(param->gam_p[16],
> &res->capture_reg->l1isp.L1_VPRO_GAM17P);
> > + writel(param->gam_p[17],
> &res->capture_reg->l1isp.L1_VPRO_GAM18P);
> > + writel(param->gam_p[18],
> &res->capture_reg->l1isp.L1_VPRO_GAM19P);
> > + writel(param->gam_p[19],
> &res->capture_reg->l1isp.L1_VPRO_GAM20P);
> > + writel(param->gam_p[20],
> &res->capture_reg->l1isp.L1_VPRO_GAM21P);
> > + writel(param->gam_p[21],
> &res->capture_reg->l1isp.L1_VPRO_GAM22P);
> > + writel(param->gam_p[22],
> &res->capture_reg->l1isp.L1_VPRO_GAM23P);
> > + writel(param->gam_p[23],
> &res->capture_reg->l1isp.L1_VPRO_GAM24P);
> > + writel(param->gam_p[24],
> &res->capture_reg->l1isp.L1_VPRO_GAM25P);
> > + writel(param->gam_p[25],
> &res->capture_reg->l1isp.L1_VPRO_GAM26P);
> > + writel(param->gam_p[26],
> &res->capture_reg->l1isp.L1_VPRO_GAM27P);
> > + writel(param->gam_p[27],
> &res->capture_reg->l1isp.L1_VPRO_GAM28P);
> > + writel(param->gam_p[28],
> &res->capture_reg->l1isp.L1_VPRO_GAM29P);
> > + writel(param->gam_p[29],
> &res->capture_reg->l1isp.L1_VPRO_GAM30P);
> > + writel(param->gam_p[30],
> &res->capture_reg->l1isp.L1_VPRO_GAM31P);
> > + writel(param->gam_p[31],
> &res->capture_reg->l1isp.L1_VPRO_GAM32P);
> > + writel(param->gam_p[32],
> &res->capture_reg->l1isp.L1_VPRO_GAM33P);
> > + writel(param->gam_p[33],
> &res->capture_reg->l1isp.L1_VPRO_GAM34P);
> > + writel(param->gam_p[34],
> &res->capture_reg->l1isp.L1_VPRO_GAM35P);
> > + writel(param->gam_p[35],
> &res->capture_reg->l1isp.L1_VPRO_GAM36P);
> > + writel(param->gam_p[36],
> &res->capture_reg->l1isp.L1_VPRO_GAM37P);
> > + writel(param->gam_p[37],
> &res->capture_reg->l1isp.L1_VPRO_GAM38P);
> > + writel(param->gam_p[38],
> &res->capture_reg->l1isp.L1_VPRO_GAM39P);
> > + writel(param->gam_p[39],
> &res->capture_reg->l1isp.L1_VPRO_GAM40P);
> > + writel(param->gam_p[40],
> &res->capture_reg->l1isp.L1_VPRO_GAM41P);
> > + writel(param->gam_p[41],
> &res->capture_reg->l1isp.L1_VPRO_GAM42P);
> > + writel(param->gam_p[42],
> &res->capture_reg->l1isp.L1_VPRO_GAM43P);
> > + writel(param->gam_p[43],
> &res->capture_reg->l1isp.L1_VPRO_GAM44P);
> > + writel(param->blkadj, &res->capture_reg->l1isp.L1_VPRO_BLKADJ);
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_PGC_SW);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_img_quality_adjustment() - Configure L1ISP image quality
> adjustment.
> > + *
> > + * @param: pointer to image quality adjustment parameters; NULL means
> disabling
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - each parameter of "param" is out of range
> > + */
> > +s32 hwd_viif_l1_set_img_quality_adjustment(struct hwd_viif_res *res,
> > + const struct
> hwd_viif_l1_img_quality_adjustment *param)
> > +{
> > + u32 val;
> > +
> > + if (!param) {
> > + /* disable all features when param is absent */
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_YUVC_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
> > + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
> > + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
> > + writel(1024U,
> &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_CNR_SW);
> > +
> > + return 0;
> > + }
> > +
> > + if (param->lum_noise_reduction) {
> > + if (param->lum_noise_reduction->gain_min >
> param->lum_noise_reduction->gain_max ||
> > + param->lum_noise_reduction->lim_min >
> param->lum_noise_reduction->lim_max) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->edge_enhancement) {
> > + if (param->edge_enhancement->gain_min >
> param->edge_enhancement->gain_max ||
> > + param->edge_enhancement->lim_min >
> param->edge_enhancement->lim_max ||
> > + param->edge_enhancement->coring_min >
> param->edge_enhancement->coring_max) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->uv_suppression) {
> > + if (param->uv_suppression->bk_mp >=
> HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> > + param->uv_suppression->black >=
> HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> > + param->uv_suppression->wh_mp >=
> HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> > + param->uv_suppression->white >=
> HWD_VIIF_L1_SUPPRESSION_MAX_VAL ||
> > + param->uv_suppression->bk_slv >=
> param->uv_suppression->wh_slv)
> > + return -EINVAL;
> > + }
> > +
> > + if (param->coring_suppression) {
> > + if (param->coring_suppression->gain_min >
> param->coring_suppression->gain_max ||
> > + param->coring_suppression->lv_min >
> param->coring_suppression->lv_max)
> > + return -EINVAL;
> > + }
> > +
> > + if (param->edge_suppression) {
> > + if (param->edge_suppression->lim >
> HWD_VIIF_L1_EDGE_SUPPRESSION_MAX_LIMIT)
> > + return -EINVAL;
> > + }
> > +
> > + if (param->color_level) {
> > + if (param->color_level->cb_gain >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> > + param->color_level->cr_gain >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> > + param->color_level->cbr_mgain_min >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> > + param->color_level->cbp_gain_max >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> > + param->color_level->cbm_gain_max >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> > + param->color_level->crp_gain_max >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN ||
> > + param->color_level->crm_gain_max >=
> HWD_VIIF_L1_COLOR_LEVEL_MAX_GAIN) {
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->color_noise_reduction_enable != HWD_VIIF_ENABLE &&
> > + param->color_noise_reduction_enable != HWD_VIIF_DISABLE) {
> > + return -EINVAL;
> > + }
> > +
> > + /* RGB to YUV */
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_YUVC_SW);
> > + writel((u32)param->coef_cb,
> &res->capture_reg->l1isp.L1_VPRO_CB_MAT);
> > + writel((u32)param->coef_cr,
> &res->capture_reg->l1isp.L1_VPRO_CR_MAT);
> > +
> > + /* brightness */
> > + val = (u32)param->brightness & 0xffffU;
> > + if (val != 0U) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
> > + writel(val, &res->capture_reg->l1isp.L1_VPRO_BRIGHT);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_BRIGHT_SW);
> > + }
> > +
> > + /* linear contrast */
> > + if ((u32)param->linear_contrast != 128U) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
> > + writel((u32)param->linear_contrast,
> &res->capture_reg->l1isp.L1_VPRO_LCONT_LEV);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_LCNT_SW);
> > + }
> > +
> > + /* nonlinear contrast */
> > + if (param->nonlinear_contrast) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
> > + writel((u32)param->nonlinear_contrast->blk_knee,
> > + &res->capture_reg->l1isp.L1_VPRO_BLK_KNEE);
> > + writel((u32)param->nonlinear_contrast->wht_knee,
> > + &res->capture_reg->l1isp.L1_VPRO_WHT_KNEE);
> > +
> > + writel((u32)param->nonlinear_contrast->blk_cont[0],
> > + &res->capture_reg->l1isp.L1_VPRO_BLK_CONT0);
> > + writel((u32)param->nonlinear_contrast->blk_cont[1],
> > + &res->capture_reg->l1isp.L1_VPRO_BLK_CONT1);
> > + writel((u32)param->nonlinear_contrast->blk_cont[2],
> > + &res->capture_reg->l1isp.L1_VPRO_BLK_CONT2);
> > +
> > + writel((u32)param->nonlinear_contrast->wht_cont[0],
> > + &res->capture_reg->l1isp.L1_VPRO_WHT_CONT0);
> > + writel((u32)param->nonlinear_contrast->wht_cont[1],
> > + &res->capture_reg->l1isp.L1_VPRO_WHT_CONT1);
> > + writel((u32)param->nonlinear_contrast->wht_cont[2],
> > + &res->capture_reg->l1isp.L1_VPRO_WHT_CONT2);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_NLCNT_SW);
> > + }
> > +
> > + /* luminance noise reduction */
> > + if (param->lum_noise_reduction) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
> > + writel((u32)param->lum_noise_reduction->gain_min,
> > + &res->capture_reg->l1isp.L1_VPRO_YNR_GAIN_MIN);
> > + writel((u32)param->lum_noise_reduction->gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_YNR_GAIN_MAX);
> > + writel((u32)param->lum_noise_reduction->lim_min,
> > + &res->capture_reg->l1isp.L1_VPRO_YNR_LIM_MIN);
> > + writel((u32)param->lum_noise_reduction->lim_max,
> > + &res->capture_reg->l1isp.L1_VPRO_YNR_LIM_MAX);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_YNR_SW);
> > + }
> > +
> > + /* edge enhancement */
> > + if (param->edge_enhancement) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
> > + writel((u32)param->edge_enhancement->gain_min,
> > + &res->capture_reg->l1isp.L1_VPRO_ETE_GAIN_MIN);
> > + writel((u32)param->edge_enhancement->gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_ETE_GAIN_MAX);
> > + writel((u32)param->edge_enhancement->lim_min,
> > + &res->capture_reg->l1isp.L1_VPRO_ETE_LIM_MIN);
> > + writel((u32)param->edge_enhancement->lim_max,
> > + &res->capture_reg->l1isp.L1_VPRO_ETE_LIM_MAX);
> > + writel((u32)param->edge_enhancement->coring_min,
> > +
> &res->capture_reg->l1isp.L1_VPRO_ETE_CORING_MIN);
> > + writel((u32)param->edge_enhancement->coring_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_ETE_CORING_MAX);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_ETE_SW);
> > + }
> > +
> > + /* UV suppression */
> > + if (param->uv_suppression) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
> > + writel((u32)param->uv_suppression->bk_slv,
> > + &res->capture_reg->l1isp.L1_VPRO_CSUP_BK_SLV);
> > + writel(param->uv_suppression->bk_mp,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_BK_MP);
> > + writel(param->uv_suppression->black,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_BLACK);
> > +
> > + writel((u32)param->uv_suppression->wh_slv,
> > + &res->capture_reg->l1isp.L1_VPRO_CSUP_WH_SLV);
> > + writel(param->uv_suppression->wh_mp,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_WH_MP);
> > + writel(param->uv_suppression->white,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_WHITE);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_UVSUP_SW);
> > + }
> > +
> > + /* coring suppression */
> > + if (param->coring_suppression) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
> > + writel((u32)param->coring_suppression->lv_min,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_LV_MIN);
> > + writel((u32)param->coring_suppression->lv_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_LV_MAX);
> > + writel((u32)param->coring_suppression->gain_min,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_GAIN_MIN);
> > + writel((u32)param->coring_suppression->gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_GAIN_MAX);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_CSUP_CORING_SW);
> > + }
> > +
> > + /* edge suppression */
> > + if (param->edge_suppression) {
> > + writel(HWD_VIIF_ENABLE,
> &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
> > + writel((u32)param->edge_suppression->gain,
> > +
> &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_GAIN);
> > + writel((u32)param->edge_suppression->lim,
> > +
> &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_LIM);
> > + } else {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_VPRO_EDGE_SUP_SW);
> > + }
> > +
> > + /* color level */
> > + if (param->color_level) {
> > + writel(param->color_level->cb_gain,
> &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
> > + writel(param->color_level->cr_gain,
> &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
> > + writel(param->color_level->cbr_mgain_min,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
> > + writel(param->color_level->cbp_gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
> > + writel(param->color_level->cbm_gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
> > + writel(param->color_level->crp_gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
> > + writel(param->color_level->crm_gain_max,
> > +
> &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
> > + } else {
> > + /* disable */
> > + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CB_GAIN);
> > + writel(1024U, &res->capture_reg->l1isp.L1_VPRO_CR_GAIN);
> > + writel(1024U,
> &res->capture_reg->l1isp.L1_VPRO_CBR_MGAIN_MIN);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CB_P_GAIN_MAX);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CB_M_GAIN_MAX);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CR_P_GAIN_MAX);
> > + writel(0U,
> &res->capture_reg->l1isp.L1_VPRO_CR_M_GAIN_MAX);
> > + }
> > +
> > + /* color noise reduction */
> > + writel(param->color_noise_reduction_enable,
> &res->capture_reg->l1isp.L1_VPRO_CNR_SW);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_avg_lum_generation() - Configure L1ISP average
> luminance generation parameters.
> > + *
> > + * @param: pointer to auto exposure parameters
> > + * Return: 0 operation completed successfully
> > + * Return: -EINVAL Parameter error
> > + * - each parameter of "param" is out of range
> > + */
> > +s32 hwd_viif_l1_set_avg_lum_generation(struct hwd_viif_res *res,
> > + const struct
> viif_l1_avg_lum_generation_config *param)
> > +{
> > + u32 idx, j;
> > + u32 val;
> > +
> > + if (!param) {
> > + writel(HWD_VIIF_DISABLE,
> &res->capture_reg->l1isp.L1_AEXP_ON);
> > + return 0;
> > + }
> > +
> > + val = readl(&res->capture_reg->l1isp.L1_SYSM_WIDTH);
> > + if (param->aexp_start_x > (val - 1U))
> > + return -EINVAL;
> > +
> > + if (param->aexp_block_width <
> HWD_VIIF_L1_AEXP_MIN_BLOCK_WIDTH ||
> > + param->aexp_block_width > val) {
> > + return -EINVAL;
> > + }
> > + if (param->aexp_block_width % 64U)
> > + return -EINVAL;
> > +
> > + val = readl(&res->capture_reg->l1isp.L1_SYSM_HEIGHT);
> > + if (param->aexp_start_y > (val - 1U))
> > + return -EINVAL;
> > +
> > + if (param->aexp_block_height <
> HWD_VIIF_L1_AEXP_MIN_BLOCK_HEIGHT ||
> > + param->aexp_block_height > val) {
> > + return -EINVAL;
> > + }
> > + if (param->aexp_block_height % 64U)
> > + return -EINVAL;
> > +
> > + for (idx = 0; idx < 8U; idx++) {
> > + for (j = 0; j < 8U; j++) {
> > + if (param->aexp_weight[idx][j] >
> HWD_VIIF_L1_AEXP_MAX_WEIGHT)
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + if (param->aexp_satur_ratio > HWD_VIIF_L1_AEXP_MAX_BLOCK_TH
> ||
> > + param->aexp_black_ratio >
> HWD_VIIF_L1_AEXP_MAX_BLOCK_TH ||
> > + param->aexp_satur_level >
> HWD_VIIF_L1_AEXP_MAX_SATURATION_PIXEL_TH) {
> > + return -EINVAL;
> > + }
> > +
> > + for (idx = 0; idx < 4U; idx++) {
> > + if (param->aexp_ave4linesy[idx] > (val - 4U))
> > + return -EINVAL;
> > + }
> > +
> > + writel(HWD_VIIF_ENABLE, &res->capture_reg->l1isp.L1_AEXP_ON);
> > + writel(param->aexp_start_x,
> &res->capture_reg->l1isp.L1_AEXP_START_X);
> > + writel(param->aexp_start_y,
> &res->capture_reg->l1isp.L1_AEXP_START_Y);
> > + writel(param->aexp_block_width,
> &res->capture_reg->l1isp.L1_AEXP_BLOCK_WIDTH);
> > + writel(param->aexp_block_height,
> &res->capture_reg->l1isp.L1_AEXP_BLOCK_HEIGHT);
> > +
> > + val = (param->aexp_weight[0][0] << 14U) |
> (param->aexp_weight[0][1] << 12U) |
> > + (param->aexp_weight[0][2] << 10U) |
> (param->aexp_weight[0][3] << 8U) |
> > + (param->aexp_weight[0][4] << 6U) |
> (param->aexp_weight[0][5] << 4U) |
> > + (param->aexp_weight[0][6] << 2U) |
> (param->aexp_weight[0][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_0);
> > +
> > + val = (param->aexp_weight[1][0] << 14U) |
> (param->aexp_weight[1][1] << 12U) |
> > + (param->aexp_weight[1][2] << 10U) |
> (param->aexp_weight[1][3] << 8U) |
> > + (param->aexp_weight[1][4] << 6U) |
> (param->aexp_weight[1][5] << 4U) |
> > + (param->aexp_weight[1][6] << 2U) |
> (param->aexp_weight[1][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_1);
> > +
> > + val = (param->aexp_weight[2][0] << 14U) |
> (param->aexp_weight[2][1] << 12U) |
> > + (param->aexp_weight[2][2] << 10U) |
> (param->aexp_weight[2][3] << 8U) |
> > + (param->aexp_weight[2][4] << 6U) |
> (param->aexp_weight[2][5] << 4U) |
> > + (param->aexp_weight[2][6] << 2U) |
> (param->aexp_weight[2][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_2);
> > +
> > + val = (param->aexp_weight[3][0] << 14U) |
> (param->aexp_weight[3][1] << 12U) |
> > + (param->aexp_weight[3][2] << 10U) |
> (param->aexp_weight[3][3] << 8U) |
> > + (param->aexp_weight[3][4] << 6U) |
> (param->aexp_weight[3][5] << 4U) |
> > + (param->aexp_weight[3][6] << 2U) |
> (param->aexp_weight[3][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_3);
> > +
> > + val = (param->aexp_weight[4][0] << 14U) |
> (param->aexp_weight[4][1] << 12U) |
> > + (param->aexp_weight[4][2] << 10U) |
> (param->aexp_weight[4][3] << 8U) |
> > + (param->aexp_weight[4][4] << 6U) |
> (param->aexp_weight[4][5] << 4U) |
> > + (param->aexp_weight[4][6] << 2U) |
> (param->aexp_weight[4][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_4);
> > +
> > + val = (param->aexp_weight[5][0] << 14U) |
> (param->aexp_weight[5][1] << 12U) |
> > + (param->aexp_weight[5][2] << 10U) |
> (param->aexp_weight[5][3] << 8U) |
> > + (param->aexp_weight[5][4] << 6U) |
> (param->aexp_weight[5][5] << 4U) |
> > + (param->aexp_weight[5][6] << 2U) |
> (param->aexp_weight[5][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_5);
> > +
> > + val = (param->aexp_weight[6][0] << 14U) |
> (param->aexp_weight[6][1] << 12U) |
> > + (param->aexp_weight[6][2] << 10U) |
> (param->aexp_weight[6][3] << 8U) |
> > + (param->aexp_weight[6][4] << 6U) |
> (param->aexp_weight[6][5] << 4U) |
> > + (param->aexp_weight[6][6] << 2U) |
> (param->aexp_weight[6][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_6);
> > +
> > + val = (param->aexp_weight[7][0] << 14U) |
> (param->aexp_weight[7][1] << 12U) |
> > + (param->aexp_weight[7][2] << 10U) |
> (param->aexp_weight[7][3] << 8U) |
> > + (param->aexp_weight[7][4] << 6U) |
> (param->aexp_weight[7][5] << 4U) |
> > + (param->aexp_weight[7][6] << 2U) |
> (param->aexp_weight[7][7]);
> > + writel(val, &res->capture_reg->l1isp.L1_AEXP_WEIGHT_7);
> > +
> > + writel(param->aexp_satur_ratio,
> &res->capture_reg->l1isp.L1_AEXP_SATUR_RATIO);
> > + writel(param->aexp_black_ratio,
> &res->capture_reg->l1isp.L1_AEXP_BLACK_RATIO);
> > + writel(param->aexp_satur_level,
> &res->capture_reg->l1isp.L1_AEXP_SATUR_LEVEL);
> > +
> > + writel(param->aexp_ave4linesy[0],
> &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY0);
> > + writel(param->aexp_ave4linesy[1],
> &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY1);
> > + writel(param->aexp_ave4linesy[2],
> &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY2);
> > + writel(param->aexp_ave4linesy[3],
> &res->capture_reg->l1isp.L1_AEXP_AVE4LINESY3);
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * hwd_viif_l1_set_irq_mask() - Set L1ISP interruption mask.
> > + *
> > + * @mask: mask setting
> > + * Return: None
> > + */
> > +void hwd_viif_l1_set_irq_mask(struct hwd_viif_res *res, u32 mask)
> > +{
> > + writel(mask, &res->capture_reg->l1isp.L1_CRGBF_ISP_INT_MASK);
> > +}
> > diff --git a/drivers/media/platform/visconti/viif_controls.c
> b/drivers/media/platform/visconti/viif_controls.c
> > new file mode 100644
> > index 00000000000..2793fb0a807
> > --- /dev/null
> > +++ b/drivers/media/platform/visconti/viif_controls.c
> > @@ -0,0 +1,1153 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> > +/* Toshiba Visconti Video Capture Support
> > + *
> > + * (C) Copyright 2022 TOSHIBA CORPORATION
> > + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/pm_runtime.h>
> > +#include <media/v4l2-common.h>
> > +#include <media/v4l2-subdev.h>
> > +
> > +#include "viif.h"
> > +
> > +static int viif_main_set_rawpack_mode(struct viif_device *viif_dev, u32
> *rawpack)
> > +{
> > + if (vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
> > + return -EBUSY;
> > +
> > + if (*rawpack == VIIF_RAWPACK_DISABLE) {
> > + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_DISABLE;
> > + return 0;
> > + }
> > + if (*rawpack == VIIF_RAWPACK_MSBFIRST) {
> > + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_MSBFIRST;
> > + return 0;
> > + }
> > + if (*rawpack == VIIF_RAWPACK_LSBFIRST) {
> > + viif_dev->rawpack_mode = HWD_VIIF_RAWPACK_LSBFIRST;
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int viif_l1_set_input_mode(struct viif_device *viif_dev,
> > + struct viif_l1_input_mode_config
> *input_mode)
> > +{
> > + u32 mode, raw_color_filter;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + /* SDR input is not supported */
> > + if (input_mode->mode == VIIF_L1_INPUT_HDR)
> > + mode = HWD_VIIF_L1_INPUT_HDR;
> > + else if (input_mode->mode == VIIF_L1_INPUT_PWL)
> > + mode = HWD_VIIF_L1_INPUT_PWL;
> > + else if (input_mode->mode == VIIF_L1_INPUT_HDR_IMG_CORRECT)
> > + mode = HWD_VIIF_L1_INPUT_HDR_IMG_CORRECT;
> > + else if (input_mode->mode == VIIF_L1_INPUT_PWL_IMG_CORRECT)
> > + mode = HWD_VIIF_L1_INPUT_PWL_IMG_CORRECT;
> > + else
> > + return -EINVAL;
> > +
> > + if (input_mode->raw_color_filter == VIIF_L1_RAW_GR_R_B_GB)
> > + raw_color_filter = HWD_VIIF_L1_RAW_GR_R_B_GB;
> > + else if (input_mode->raw_color_filter == VIIF_L1_RAW_R_GR_GB_B)
> > + raw_color_filter = HWD_VIIF_L1_RAW_R_GR_GB_B;
> > + else if (input_mode->raw_color_filter == VIIF_L1_RAW_B_GB_GR_R)
> > + raw_color_filter = HWD_VIIF_L1_RAW_B_GB_GR_R;
> > + else if (input_mode->raw_color_filter == VIIF_L1_RAW_GB_B_R_GR)
> > + raw_color_filter = HWD_VIIF_L1_RAW_GB_B_R_GR;
> > + else
> > + return -EINVAL;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_input_mode(viif_dev->hwd_res, mode,
> input_mode->depth,
> > + raw_color_filter);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_rgb_to_y_coef(struct viif_device *viif_dev,
> > + struct viif_l1_rgb_to_y_coef_config
> *l1_rgb_to_y_coef)
> > +{
> > + int ret;
> > + unsigned long irqflags;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_rgb_to_y_coef(viif_dev->hwd_res,
> l1_rgb_to_y_coef->coef_r,
> > + l1_rgb_to_y_coef->coef_g,
> l1_rgb_to_y_coef->coef_b);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_ag_mode(struct viif_device *viif_dev,
> > + struct viif_l1_ag_mode_config *l1_ag_mode)
> > +{
> > + int ret;
> > + unsigned long irqflags;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_ag_mode(viif_dev->hwd_res, l1_ag_mode);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_ag(struct viif_device *viif_dev, struct viif_l1_ag_config
> *l1_ag)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_ag(viif_dev->hwd_res, l1_ag->gain_h,
> l1_ag->gain_m, l1_ag->gain_l);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_hdre(struct viif_device *viif_dev, struct
> viif_l1_hdre_config *l1_hdre)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_hdre(viif_dev->hwd_res, l1_hdre);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_img_extraction(struct viif_device *viif_dev,
> > + struct viif_l1_img_extraction_config
> *img_extract)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_img_extraction(viif_dev->hwd_res,
> img_extract->input_black_gr,
> > + img_extract->input_black_r,
> img_extract->input_black_b,
> > + img_extract->input_black_gb);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192
> > +static int viif_l1_set_dpc(struct viif_device *viif_dev, struct viif_l1_dpc_config
> *l1_dpc)
> > +{
> > + uintptr_t table_h_paddr = 0;
> > + uintptr_t table_m_paddr = 0;
> > + uintptr_t table_l_paddr = 0;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if (l1_dpc->table_h_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
> > + u64_to_user_ptr(l1_dpc->table_h_addr),
> > + VISCONTI_VIIF_DPC_TABLE_SIZE))
> > + return -EFAULT;
>
> NACK!
>
> I thought those addresses in a struct were iffy. This is not supported, it
> basically bypasses the whole control framework.
I understand.
> The way to do this is to create separate array controls for these tables.
> And table_h_addr becomes a simple 0 or 1 value, indicating whether to use
> the table set by that control. For small arrays it is also an option to
> embed them in the control structure.
As I wrote in reply for patch 2/6, I thought embedding is the only solution.
Thank you for giving another plan: adding controls for tables.
When I use individual controls for tables, are there some orderings between controls?
-- such that control DPC_TABLE_{H,M,L} should be configured before SET_DPC
> Are these l, h and m tables independent from one another? I.e. is it possible
> to set l but not h and m? I suspect it is all or nothing, and in that case you
> need only a single control to set all three tables (a two dimensional array).
These three tables can be setup individually.
> Anyway, the same issue applies to all the controls were you pass addresses for
> tables, that all needs to change.
All right. These controls must be fixed.
> > + table_h_paddr =
> (uintptr_t)viif_dev->table_paddr->dpc_table_h;
> > + }
> > + if (l1_dpc->table_m_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->dpc_table_m,
> > + u64_to_user_ptr(l1_dpc->table_m_addr),
> > + VISCONTI_VIIF_DPC_TABLE_SIZE))
> > + return -EFAULT;
> > + table_m_paddr =
> (uintptr_t)viif_dev->table_paddr->dpc_table_m;
> > + }
> > + if (l1_dpc->table_l_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->dpc_table_l,
> > + u64_to_user_ptr(l1_dpc->table_l_addr),
> > + VISCONTI_VIIF_DPC_TABLE_SIZE))
> > + return -EFAULT;
> > + table_l_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_l;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_dpc_table_transmission(viif_dev->hwd_res,
> table_h_paddr,
> > + table_m_paddr,
> table_l_paddr);
> > + if (ret)
> > + goto err;
> > +
> > + ret = hwd_viif_l1_set_dpc(viif_dev->hwd_res, &l1_dpc->param_h,
> &l1_dpc->param_m,
> > + &l1_dpc->param_l);
> > +
> > +err:
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > + return ret;
> > +}
> > +
> > +static int
> > +viif_l1_set_preset_white_balance(struct viif_device *viif_dev,
> > + struct viif_l1_preset_white_balance_config
> *l1_preset_wb)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_preset_white_balance(viif_dev->hwd_res,
> l1_preset_wb->dstmaxval,
> > + &l1_preset_wb->param_h,
> &l1_preset_wb->param_m,
> > +
> &l1_preset_wb->param_l);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int
> > +viif_l1_set_raw_color_noise_reduction(struct viif_device *viif_dev,
> > + struct
> viif_l1_raw_color_noise_reduction_config *raw_color)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_raw_color_noise_reduction(viif_dev->hwd_res,
> &raw_color->param_h,
> > +
> &raw_color->param_m, &raw_color->param_l);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_hdrs(struct viif_device *viif_dev, struct
> viif_l1_hdrs_config *hdrs)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_hdrs(viif_dev->hwd_res, hdrs);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_black_level_correction(struct viif_device *viif_dev,
> > + struct
> viif_l1_black_level_correction_config *blc)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_black_level_correction(viif_dev->hwd_res, blc);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +#define VISCONTI_VIIF_LSC_TABLE_BYTES 1536
> > +
> > +static int viif_l1_set_lsc(struct viif_device *viif_dev, struct viif_l1_lsc_config
> *l1_lsc)
> > +{
> > + struct viif_l1_lsc_parabola_param lsc_para;
> > + struct viif_l1_lsc_grid_param lsc_grid;
> > + struct hwd_viif_l1_lsc hwd_params;
> > + struct viif_l1_lsc lsc_params;
> > + uintptr_t table_gr_paddr = 0;
> > + uintptr_t table_gb_paddr = 0;
> > + uintptr_t table_r_paddr = 0;
> > + uintptr_t table_b_paddr = 0;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if (!l1_lsc->param_addr) {
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_lsc(viif_dev->hwd_res, NULL);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > + return ret;
> > + }
> > +
> > + if (l1_lsc->table_gr_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->lsc_table_gr,
> > + u64_to_user_ptr(l1_lsc->table_gr_addr),
> > + VISCONTI_VIIF_LSC_TABLE_BYTES))
> > + return -EFAULT;
> > + table_gr_paddr =
> (uintptr_t)viif_dev->table_paddr->lsc_table_gr;
> > + }
> > + if (l1_lsc->table_r_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->lsc_table_r,
> > + u64_to_user_ptr(l1_lsc->table_r_addr),
> > + VISCONTI_VIIF_LSC_TABLE_BYTES))
> > + return -EFAULT;
> > + table_r_paddr = (uintptr_t)viif_dev->table_paddr->lsc_table_r;
> > + }
> > + if (l1_lsc->table_b_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->lsc_table_b,
> > + u64_to_user_ptr(l1_lsc->table_b_addr),
> > + VISCONTI_VIIF_LSC_TABLE_BYTES))
> > + return -EFAULT;
> > + table_b_paddr =
> (uintptr_t)viif_dev->table_paddr->lsc_table_b;
> > + }
> > + if (l1_lsc->table_gb_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->lsc_table_gb,
> > + u64_to_user_ptr(l1_lsc->table_gb_addr),
> > + VISCONTI_VIIF_LSC_TABLE_BYTES))
> > + return -EFAULT;
> > + table_gb_paddr =
> (uintptr_t)viif_dev->table_paddr->lsc_table_gb;
> > + }
> > +
> > + if (copy_from_user(&lsc_params,
> u64_to_user_ptr(l1_lsc->param_addr),
> > + sizeof(struct viif_l1_lsc)))
> > + return -EFAULT;
> > +
> > + hwd_params.lssc_parabola_param = NULL;
> > + hwd_params.lssc_grid_param = NULL;
> > +
> > + if (lsc_params.lssc_parabola_param_addr) {
> > + if (copy_from_user(&lsc_para,
> u64_to_user_ptr(lsc_params.lssc_parabola_param_addr),
> > + sizeof(struct viif_l1_lsc_parabola_param)))
> > + return -EFAULT;
> > + hwd_params.lssc_parabola_param = &lsc_para;
> > + }
> > +
> > + if (lsc_params.lssc_grid_param_addr) {
> > + if (copy_from_user(&lsc_grid,
> u64_to_user_ptr(lsc_params.lssc_grid_param_addr),
> > + sizeof(struct viif_l1_lsc_grid_param)))
> > + return -EFAULT;
> > + hwd_params.lssc_grid_param = &lsc_grid;
> > + }
> > +
> > + hwd_params.lssc_pwhb_r_gain_max =
> lsc_params.lssc_pwhb_r_gain_max;
> > + hwd_params.lssc_pwhb_r_gain_min =
> lsc_params.lssc_pwhb_r_gain_min;
> > + hwd_params.lssc_pwhb_gr_gain_max =
> lsc_params.lssc_pwhb_gr_gain_max;
> > + hwd_params.lssc_pwhb_gr_gain_min =
> lsc_params.lssc_pwhb_gr_gain_min;
> > + hwd_params.lssc_pwhb_gb_gain_max =
> lsc_params.lssc_pwhb_gb_gain_max;
> > + hwd_params.lssc_pwhb_gb_gain_min =
> lsc_params.lssc_pwhb_gb_gain_min;
> > + hwd_params.lssc_pwhb_b_gain_max =
> lsc_params.lssc_pwhb_b_gain_max;
> > + hwd_params.lssc_pwhb_b_gain_min =
> lsc_params.lssc_pwhb_b_gain_min;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_lsc_table_transmission(viif_dev->hwd_res,
> table_gr_paddr,
> > + table_r_paddr,
> table_b_paddr, table_gb_paddr);
> > + if (ret)
> > + goto err;
> > +
> > + ret = hwd_viif_l1_set_lsc(viif_dev->hwd_res, &hwd_params);
> > +err:
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_main_process(struct viif_device *viif_dev,
> > + struct viif_l1_main_process_config *mpro)
> > +{
> > + struct viif_l1_color_matrix_correction color_matrix;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if (mpro->param_addr) {
> > + if (copy_from_user(&color_matrix,
> u64_to_user_ptr(mpro->param_addr),
> > + sizeof(struct
> viif_l1_color_matrix_correction)))
> > + return -EFAULT;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_main_process(viif_dev->hwd_res,
> mpro->demosaic_mode,
> > + mpro->damp_lsbsel,
> > + mpro->param_addr ?
> &color_matrix : NULL,
> > + mpro->dst_maxval);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_awb(struct viif_device *viif_dev, struct
> viif_l1_awb_config *l1_awb)
> > +{
> > + struct viif_l1_awb param;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if (l1_awb->param_addr) {
> > + if (copy_from_user(¶m,
> u64_to_user_ptr(l1_awb->param_addr),
> > + sizeof(struct viif_l1_awb)))
> > + return -EFAULT;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_awb(viif_dev->hwd_res, l1_awb->param_addr ?
> ¶m : NULL,
> > + l1_awb->awhb_wbmrg,
> l1_awb->awhb_wbmgg, l1_awb->awhb_wbmbg);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_lock_awb_gain(struct viif_device *viif_dev, u32 *enable)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_lock_awb_gain(viif_dev->hwd_res, *enable);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_hdrc(struct viif_device *viif_dev, struct
> viif_l1_hdrc_config *hdrc)
> > +{
> > + struct viif_l1_hdrc param;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if (hdrc->param_addr) {
> > + if (copy_from_user(¶m,
> u64_to_user_ptr(hdrc->param_addr),
> > + sizeof(struct viif_l1_hdrc)))
> > + return -EFAULT;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_hdrc(viif_dev->hwd_res, hdrc->param_addr ?
> ¶m : NULL,
> > + hdrc->hdrc_thr_sft_amt);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_hdrc_ltm(struct viif_device *viif_dev,
> > + struct viif_l1_hdrc_ltm_config *l1_hdrc_ltm)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_hdrc_ltm(viif_dev->hwd_res, l1_hdrc_ltm);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_gamma(struct viif_device *viif_dev, struct
> viif_l1_gamma_config *l1_gamma)
> > +{
> > + struct viif_l1_gamma param;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if (l1_gamma->param_addr) {
> > + if (copy_from_user(¶m,
> u64_to_user_ptr(l1_gamma->param_addr),
> > + sizeof(struct viif_l1_gamma)))
> > + return -EFAULT;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_gamma(viif_dev->hwd_res,
> l1_gamma->param_addr ? ¶m : NULL);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int
> > +viif_l1_set_img_quality_adjustment(struct viif_device *viif_dev,
> > + struct
> viif_l1_img_quality_adjustment_config *img_quality)
> > +{
> > + struct hwd_viif_l1_img_quality_adjustment hwd_img_quality;
> > + struct viif_l1_lum_noise_reduction lum_noise;
> > + struct viif_l1_nonlinear_contrast nonlinear;
> > + struct viif_l1_coring_suppression coring;
> > + struct viif_l1_edge_enhancement edge_enh;
> > + struct viif_l1_edge_suppression edge_sup;
> > + struct viif_l1_uv_suppression uv;
> > + struct viif_l1_color_level color;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + hwd_img_quality.coef_cb = img_quality->coef_cb;
> > + hwd_img_quality.coef_cr = img_quality->coef_cr;
> > + hwd_img_quality.brightness = img_quality->brightness;
> > + hwd_img_quality.linear_contrast = img_quality->linear_contrast;
> > + hwd_img_quality.color_noise_reduction_enable =
> img_quality->color_noise_reduction_enable;
> > +
> > + if (img_quality->nonlinear_contrast_addr) {
> > + if (copy_from_user(&nonlinear,
> > +
> u64_to_user_ptr(img_quality->nonlinear_contrast_addr),
> > + sizeof(struct viif_l1_nonlinear_contrast)))
> > + return -EFAULT;
> > + hwd_img_quality.nonlinear_contrast = &nonlinear;
> > + } else {
> > + hwd_img_quality.nonlinear_contrast = NULL;
> > + }
> > + if (img_quality->lum_noise_reduction_addr) {
> > + if (copy_from_user(&lum_noise,
> > +
> u64_to_user_ptr(img_quality->lum_noise_reduction_addr),
> > + sizeof(struct viif_l1_lum_noise_reduction)))
> > + return -EFAULT;
> > + hwd_img_quality.lum_noise_reduction = &lum_noise;
> > + } else {
> > + hwd_img_quality.lum_noise_reduction = NULL;
> > + }
> > + if (img_quality->edge_enhancement_addr) {
> > + if (copy_from_user(&edge_enh,
> u64_to_user_ptr(img_quality->edge_enhancement_addr),
> > + sizeof(struct viif_l1_edge_enhancement)))
> > + return -EFAULT;
> > + hwd_img_quality.edge_enhancement = &edge_enh;
> > + } else {
> > + hwd_img_quality.edge_enhancement = NULL;
> > + }
> > + if (img_quality->uv_suppression_addr) {
> > + if (copy_from_user(&uv,
> u64_to_user_ptr(img_quality->uv_suppression_addr),
> > + sizeof(struct viif_l1_uv_suppression)))
> > + return -EFAULT;
> > + hwd_img_quality.uv_suppression = &uv;
> > + } else {
> > + hwd_img_quality.uv_suppression = NULL;
> > + }
> > + if (img_quality->coring_suppression_addr) {
> > + if (copy_from_user(&coring,
> u64_to_user_ptr(img_quality->coring_suppression_addr),
> > + sizeof(struct viif_l1_coring_suppression)))
> > + return -EFAULT;
> > + hwd_img_quality.coring_suppression = &coring;
> > + } else {
> > + hwd_img_quality.coring_suppression = NULL;
> > + }
> > + if (img_quality->edge_suppression_addr) {
> > + if (copy_from_user(&edge_sup,
> u64_to_user_ptr(img_quality->edge_suppression_addr),
> > + sizeof(struct viif_l1_edge_suppression)))
> > + return -EFAULT;
> > + hwd_img_quality.edge_suppression = &edge_sup;
> > + } else {
> > + hwd_img_quality.edge_suppression = NULL;
> > + }
> > + if (img_quality->color_level_addr) {
> > + if (copy_from_user(&color,
> u64_to_user_ptr(img_quality->color_level_addr),
> > + sizeof(struct viif_l1_color_level)))
> > + return -EFAULT;
> > + hwd_img_quality.color_level = &color;
> > + } else {
> > + hwd_img_quality.color_level = NULL;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_img_quality_adjustment(viif_dev->hwd_res,
> &hwd_img_quality);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_l1_set_avg_lum_generation(struct viif_device *viif_dev,
> > + struct
> viif_l1_avg_lum_generation_config *l1_avg_lum)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l1_set_avg_lum_generation(viif_dev->hwd_res,
> l1_avg_lum);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + return ret;
> > +}
> > +
> > +#define VISCONTI_VIIF_DPC_TABLE_SIZE_MIN 1024
> > +#define VISCONTI_VIIF_DPC_TABLE_SIZE_MAX 8192
> > +static int viif_l2_set_undist(struct viif_device *viif_dev, struct
> viif_l2_undist_config *undist)
> > +{
> > + uintptr_t table_write_g_paddr = 0;
> > + uintptr_t table_read_b_paddr = 0;
> > + uintptr_t table_read_g_paddr = 0;
> > + uintptr_t table_read_r_paddr = 0;
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + if ((undist->size && undist->size <
> VISCONTI_VIIF_DPC_TABLE_SIZE_MIN) ||
> > + undist->size > VISCONTI_VIIF_DPC_TABLE_SIZE_MAX)
> > + return -EINVAL;
> > +
> > + if (undist->write_g_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->undist_write_g,
> > + u64_to_user_ptr(undist->write_g_addr),
> undist->size))
> > + return -EFAULT;
> > + table_write_g_paddr =
> (uintptr_t)viif_dev->table_paddr->undist_write_g;
> > + }
> > + if (undist->read_b_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->undist_read_b,
> > + u64_to_user_ptr(undist->read_b_addr),
> undist->size))
> > + return -EFAULT;
> > + table_read_b_paddr =
> (uintptr_t)viif_dev->table_paddr->undist_read_b;
> > + }
> > + if (undist->read_g_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->undist_read_g,
> > + u64_to_user_ptr(undist->read_g_addr),
> undist->size))
> > + return -EFAULT;
> > + table_read_g_paddr =
> (uintptr_t)viif_dev->table_paddr->undist_read_g;
> > + }
> > + if (undist->read_r_addr) {
> > + if (copy_from_user(viif_dev->table_vaddr->undist_read_r,
> > + u64_to_user_ptr(undist->read_r_addr),
> undist->size))
> > + return -EFAULT;
> > + table_read_r_paddr =
> (uintptr_t)viif_dev->table_paddr->undist_read_r;
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l2_set_undist_table_transmission(viif_dev->hwd_res,
> table_write_g_paddr,
> > + table_read_b_paddr,
> table_read_g_paddr,
> > + table_read_r_paddr,
> undist->size);
> > + if (ret) {
> > + dev_err(viif_dev->dev, "l2_set_undist_table_transmission
> error. %d\n", ret);
> > + goto err;
> > + }
> > +
> > + ret = hwd_viif_l2_set_undist(viif_dev->hwd_res, &undist->param);
> > +
> > +err:
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > + return ret;
> > +}
> > +
> > +static int viif_l2_set_roi(struct viif_device *viif_dev, struct viif_l2_roi_config
> *roi)
> > +{
> > + unsigned long irqflags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l2_set_roi(viif_dev->hwd_res, roi);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > + return ret;
> > +}
> > +
> > +static int viif_l2_set_roi_wrap(struct viif_device *viif_dev, struct
> viif_l2_roi_config *roi)
> > +{
> > + int ret;
> > +
> > + ret = viif_l2_set_roi(viif_dev, roi);
> > + if (!ret)
> > + visconti_viif_isp_set_compose_rect(viif_dev, roi);
> > +
> > + return ret;
> > +}
> > +
> > +#define VISCONTI_VIIF_GANMMA_TABLE_SIZE 512
> > +static int viif_l2_set_gamma(struct viif_device *viif_dev, struct
> viif_l2_gamma_config *l2_gamma)
> > +{
> > + struct hwd_viif_l2_gamma_table hwd_table = { 0 };
> > + int pathid = l2_gamma->pathid;
> > + unsigned long irqflags;
> > + int postid;
> > + int ret;
> > + u32 i;
> > +
> > + if (pathid == CAPTURE_PATH_MAIN_POST0)
> > + postid = VIIF_L2ISP_POST_0;
> > + else if (pathid == CAPTURE_PATH_MAIN_POST1)
> > + postid = VIIF_L2ISP_POST_1;
> > + else
> > + return -EINVAL;
> > +
> > + for (i = 0; i < 6; i++) {
> > + if (l2_gamma->table_addr[i]) {
> > + if
> (copy_from_user(viif_dev->table_vaddr->l2_gamma_table[pathid][i],
> > +
> u64_to_user_ptr(l2_gamma->table_addr[i]),
> > +
> VISCONTI_VIIF_GANMMA_TABLE_SIZE))
> > + return -EFAULT;
> > + hwd_table.table[i] =
> > +
> (uintptr_t)viif_dev->table_paddr->l2_gamma_table[pathid][i];
> > + }
> > + }
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + ret = hwd_viif_l2_set_gamma_table_transmission(viif_dev->hwd_res,
> postid, &hwd_table);
> > + if (ret)
> > + goto err;
> > +
> > + ret = hwd_viif_l2_set_gamma(viif_dev->hwd_res, postid,
> l2_gamma->enable, l2_gamma->vsplit,
> > + l2_gamma->mode);
> > +err:
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > + return ret;
> > +}
> > +
> > +static int
> > +viif_csi2rx_get_calibration_status(struct viif_device *viif_dev,
> > + struct viif_csi2rx_dphy_calibration_status
> *calibration_status)
> > +{
> > + int ret;
> > +
> > + if (!vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
> > + return -EIO;
>
> EIO is definitely the wrong error code since that indicates a HW issue, and
> that's not the case. Do you need to return an error here? Is there a reasonable
> calibration status that you can return instead?
>
> Presumably if it is not streaming, then that means 'uncalibrated', so perhaps
> returning an 'uncalibrated' status here makes the more sense.
Status code for each member of control struct is either of: NOT_DONE, SUCCESS or FAIL.
NOT_DONE (or newly introduced UNCALIBRATED) can be set instead of returning -EIO.
> Also, I suspect you actually mean vb2_start_streaming_called() here. I assume
> that the calibration step happens in start_streaming() which can be called later
> than VIDIOC_STREAMON (which is the ioctl that sets 'is streaming' to true).
I'll use vb2_start_streaming_called.
> > +
> > + ret = hwd_viif_csi2rx_get_calibration_status(viif_dev->hwd_res,
> calibration_status);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_csi2rx_get_err_status(struct viif_device *viif_dev,
> > + struct viif_csi2rx_err_status *csi_err)
> > +{
> > + int ret;
> > +
> > + if (!vb2_is_streaming(&viif_dev->cap_dev0.vb2_vq))
> > + return -EIO;
> > +
> > + ret = hwd_viif_csi2rx_get_err_status(viif_dev->hwd_res,
> &csi_err->err_phy_fatal,
> > + &csi_err->err_pkt_fatal,
> &csi_err->err_frame_fatal,
> > + &csi_err->err_phy,
> &csi_err->err_pkt,
> > + &csi_err->err_line);
> > +
> > + return ret;
> > +}
> > +
> > +static int viif_isp_get_last_capture_status(struct viif_device *viif_dev,
> > + struct viif_isp_capture_status
> *status)
> > +{
> > + struct hwd_viif_l1_info l1_info;
> > + unsigned long irqflags;
> > + int i, j;
> > +
> > + spin_lock_irqsave(&viif_dev->lock, irqflags);
> > + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> > + hwd_viif_isp_get_info(viif_dev->hwd_res, &l1_info, NULL);
> > + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> > + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> > +
> > + status->l1_info.avg_lum_weight = l1_info.avg_lum_weight;
> > + for (i = 0; i < 8; i++) {
> > + for (j = 0; j < 8; j++)
> > + status->l1_info.avg_lum_block[i][j] =
> l1_info.avg_lum_block[i][j];
> > + }
> > + for (i = 0; i < 4; i++)
> > + status->l1_info.avg_lum_four_line_lum[i] =
> l1_info.avg_lum_four_line_lum[i];
> > +
> > + status->l1_info.avg_satur_pixnum = l1_info.avg_satur_pixnum;
> > + status->l1_info.avg_black_pixnum = l1_info.avg_black_pixnum;
> > + status->l1_info.awb_ave_u = l1_info.awb_ave_u;
> > + status->l1_info.awb_ave_v = l1_info.awb_ave_v;
> > + status->l1_info.awb_accumulated_pixel =
> l1_info.awb_accumulated_pixel;
> > + status->l1_info.awb_gain_r = l1_info.awb_gain_r;
> > + status->l1_info.awb_gain_g = l1_info.awb_gain_g;
> > + status->l1_info.awb_gain_b = l1_info.awb_gain_b;
> > + status->l1_info.awb_status_u = l1_info.awb_status_u;
> > + status->l1_info.awb_status_v = l1_info.awb_status_v;
> > +
> > + return 0;
> > +}
> > +
> > +static int viif_isp_get_reported_errors(struct viif_device *viif_dev,
> > + struct viif_reported_errors *status)
> > +{
> > + status->main = viif_dev->reported_err_main;
> > + status->sub = viif_dev->reported_err_sub;
> > + status->csi2rx = viif_dev->reported_err_csi2rx;
> > + viif_dev->reported_err_main = 0;
> > + viif_dev->reported_err_sub = 0;
> > + viif_dev->reported_err_csi2rx = 0;
> > +
> > + return 0;
> > +}
> > +
> > +/* ===== v4l2 subdevice control handlers ===== */
> > +#define COMPOUND_TYPE_SAMPLE01 0x0280
> > +
> > +static int visconti_viif_isp_set_ctrl(struct v4l2_ctrl *ctrl)
> > +{
> > + struct viif_device *viif_dev = ctrl->priv;
> > +
> > + pr_info("isp_set_ctrl: %s", ctrl->name);
> > + if (pm_runtime_status_suspended(viif_dev->dev)) {
> > + pr_info("warning: visconti viif HW is not powered");
> > + return 0;
> > + }
> > +
> > + switch (ctrl->id) {
> > + case V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE:
> > + return viif_main_set_rawpack_mode(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE:
> > + return viif_l1_set_input_mode(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF:
> > + return viif_l1_set_rgb_to_y_coef(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE:
> > + return viif_l1_set_ag_mode(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG:
> > + return viif_l1_set_ag(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE:
> > + return viif_l1_set_hdre(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION:
> > + return viif_l1_set_img_extraction(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC:
> > + return viif_l1_set_dpc(viif_dev, ctrl->p_new.p);
> > + case
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE:
> > + return viif_l1_set_preset_white_balance(viif_dev,
> ctrl->p_new.p);
> > + case
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION:
> > + return viif_l1_set_raw_color_noise_reduction(viif_dev,
> ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS:
> > + return viif_l1_set_hdrs(viif_dev, ctrl->p_new.p);
> > + case
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION:
> > + return viif_l1_set_black_level_correction(viif_dev,
> ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC:
> > + return viif_l1_set_lsc(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS:
> > + return viif_l1_set_main_process(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB:
> > + return viif_l1_set_awb(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN:
> > + return viif_l1_lock_awb_gain(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC:
> > + return viif_l1_set_hdrc(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM:
> > + return viif_l1_set_hdrc_ltm(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA:
> > + return viif_l1_set_gamma(viif_dev, ctrl->p_new.p);
> > + case
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT:
> > + return viif_l1_set_img_quality_adjustment(viif_dev,
> ctrl->p_new.p);
> > + case
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION:
> > + return viif_l1_set_avg_lum_generation(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST:
> > + return viif_l2_set_undist(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI:
> > + return viif_l2_set_roi_wrap(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA:
> > + return viif_l2_set_gamma(viif_dev, ctrl->p_new.p);
> > + default:
> > + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
> > + break;
> > + }
> > + return 0;
> > +}
> > +
> > +static int visconti_viif_isp_get_ctrl(struct v4l2_ctrl *ctrl)
> > +{
> > + struct viif_device *viif_dev = ctrl->priv;
> > +
> > + pr_info("isp_get_ctrl: %s", ctrl->name);
> > + if (pm_runtime_status_suspended(viif_dev->dev)) {
> > + pr_info("warning: visconti viif HW is not powered");
> > + return 0;
> > + }
> > +
> > + switch (ctrl->id) {
> > + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
> > + return viif_csi2rx_get_calibration_status(viif_dev,
> ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
> > + return viif_csi2rx_get_err_status(viif_dev, ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
> > + return viif_isp_get_last_capture_status(viif_dev,
> ctrl->p_new.p);
> > + case V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
> > + return viif_isp_get_reported_errors(viif_dev, ctrl->p_new.p);
>
> My question for these four controls is: are these really volatile controls?
> A volatile control means that the hardware can change the registers at any
> time without telling the CPU about it via an interrupt or some similar
> mechanism.
>
> If there *is* such a mechanism, then it is not a volatile control, instead the
> driver has to update the control value whenever the HW informs it about the
> new value.
>
> I can't tell, so that's why I ask here to double check.
>
I quickly checked HW and found ...
* CSI2RX_GET_CALIBRATION_STATUS: No interrupt mechanism
* CSI2RX_GET_ERR_STATUS: An interrupt handler can be used
* GET_LAST_CAPTURE_STATUS: information can be updated at Vsync interrupt
* GET_LAST_ERROR: An interrupt handler can be used
I'll try building control values while running interrupt services.
Do I have to do G_EXT_CTRLS followed by S_EXT_CTRLS if I want Read-To-Clear operation?
Currently, GET_LAST_ERROR control reports accumerated errors since last read.
> > + default:
> > + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
> > + break;
> > + }
> > + return 0;
> > +}
> > +
> > +/* ===== register v4l2 subdevice controls ===== */
> > +static bool visconti_viif_isp_custom_ctrl_equal(const struct v4l2_ctrl *ctrl,
> > + union v4l2_ctrl_ptr ptr1,
> union v4l2_ctrl_ptr ptr2)
> > +{
> > + return !memcmp(ptr1.p_const, ptr2.p_const, ctrl->elem_size);
> > +}
> > +
> > +static void visconti_viif_isp_custom_ctrl_init(const struct v4l2_ctrl *ctrl, u32
> idx,
> > + union v4l2_ctrl_ptr ptr)
> > +{
> > + if (ctrl->p_def.p_const)
> > + memcpy(ptr.p, ctrl->p_def.p_const, ctrl->elem_size);
> > + else
> > + memset(ptr.p, 0, ctrl->elem_size);
> > +}
> > +
> > +static void visconti_viif_isp_custom_ctrl_log(const struct v4l2_ctrl *ctrl)
> > +{
> > +}
> > +
> > +static int visconti_viif_isp_custom_ctrl_validate(const struct v4l2_ctrl *ctrl,
> > + union v4l2_ctrl_ptr ptr)
> > +{
> > + pr_info("std_validate: %s", ctrl->name);
> > + return 0;
> > +}
> > +
> > +static const struct v4l2_ctrl_type_ops custom_type_ops = {
> > + .equal = visconti_viif_isp_custom_ctrl_equal,
> > + .init = visconti_viif_isp_custom_ctrl_init,
> > + .log = visconti_viif_isp_custom_ctrl_log,
> > + .validate = visconti_viif_isp_custom_ctrl_validate,
> > +};
>
> This is not needed, it's not doing anything that the control framework already
> does by default.
I'll remove it.
> > +
> > +static const struct v4l2_ctrl_ops visconti_viif_isp_ctrl_ops = {
> > + .g_volatile_ctrl = visconti_viif_isp_get_ctrl,
> > + .s_ctrl = visconti_viif_isp_set_ctrl,
>
> As mentioned above, you should add a try_ctrl callback as well to do the
> validation. Note that if there is a try_ctrl callback, then set_ctrl doesn't
> need to do the validation anymore since try_ctrl will be called before set_ctrl.
I'll implement try_ctrl callback reusing validation routines.
> > +};
> > +
> > +/* ----- control handler ----- */
> > +#define CTRL_CONFIG_DEFAULT_ENTRY
> \
> > + .ops = &visconti_viif_isp_ctrl_ops, .type_ops = &custom_type_ops, \
> > + .type = COMPOUND_TYPE_SAMPLE01, .flags =
> V4L2_CTRL_FLAG_EXECUTE_ON_WRITE
>
> Why is V4L2_CTRL_FLAG_EXECUTE_ON_WRITE needed?
Currently, this driver accepts individual s_ctrl calls and configure HW registers while running,
instead of setting all the cached control values at starting streaming.
Therefore, V4L2_CTRL_FLAG_EXECUTE_ON_WRITE is needed to let a mechanism kick a callback
even if a given control value is identical to the previous value.
As in response to patch 2/6, I will try add initial value to each control.
After that, I'll try add HW setup routine at starting streaming
so that EXECUTE_ON_WRITE flags are removed.
> > +
> > +#define CTRL_CONFIG_RDONLY_ENTRY
> \
> > + .ops = &visconti_viif_isp_ctrl_ops, .type_ops = &custom_type_ops, \
> > + .type = COMPOUND_TYPE_SAMPLE01, .flags =
> V4L2_CTRL_FLAG_VOLATILE
>
> Shouldn't the READ_ONLY flag be set as well?
I'll add READ_ONLY flag.
> > +
> > +static const struct v4l2_ctrl_config visconti_viif_isp_ctrl_config[] = {
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE,
> > + .name = "rawpack_mode",
>
> These strings appear as the name of the control and are supposed to be
> human readable. So I would write this as: "Rawpack Mode", and (for the
> next control): "L1 Input Mode", etc.
I'll change name field to human readable format.
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(u32),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE,
> > + .name = "l1_input_mode",
> > + .p_def = { .p_const = NULL },
>
> Just drop this, no need to initialize fields to 0.
I'll drop these initializations.
> > + .elem_size = sizeof(struct viif_l1_input_mode_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF,
> > + .name = "l1_rgb_to_y_coef",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_rgb_to_y_coef_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE,
> > + .name = "l1_ag_mode",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_ag_mode_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG,
> > + .name = "l1_ag",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_ag_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE,
> > + .name = "l1_hdre",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_hdre_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION,
> > + .name = "l1_img_extraction",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_img_extraction_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC,
> > + .name = "l1_dpc",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_dpc_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE,
> > + .name = "l1_preset_white_balance",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_preset_white_balance_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION,
> > + .name = "l1_raw_color_noise_reduction",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct
> viif_l1_raw_color_noise_reduction_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS,
> > + .name = "l1_set_hdrs",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_hdrs_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION,
> > + .name = "l1_black_level_correction",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct
> viif_l1_black_level_correction_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC,
> > + .name = "l1_lsc",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_lsc_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS,
> > + .name = "l1_main_process",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_main_process_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB,
> > + .name = "l1_awb",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_awb_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN,
> > + .name = "l1_lock_awb_gain",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(u32),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC,
> > + .name = "l1_hdrc",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_hdrc_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM,
> > + .name = "l1_hdrc_ltm",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_hdrc_ltm_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA,
> > + .name = "l1_gamma",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_gamma_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT,
> > + .name = "l1_img_quality_adjustment",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct
> viif_l1_img_quality_adjustment_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION,
> > + .name = "l1_avg_lum",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l1_avg_lum_generation_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST,
> > + .name = "l2_undist",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l2_undist_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI,
> > + .name = "l2_roi",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l2_roi_config),
> > + },
> > + {
> > + CTRL_CONFIG_DEFAULT_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA,
> > + .name = "l2_gamma",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_l2_gamma_config),
> > + },
> > + {
> > + CTRL_CONFIG_RDONLY_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS,
> > + .name = "csi2rx_calibration_status",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_csi2rx_dphy_calibration_status),
> > + },
> > + {
> > + CTRL_CONFIG_RDONLY_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS,
> > + .name = "csi2rx_err_status",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_csi2rx_err_status),
> > + },
> > + {
> > + CTRL_CONFIG_RDONLY_ENTRY,
> > + .id =
> V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS,
> > + .name = "last_capture_status",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_isp_capture_status),
> > + },
> > + {
> > + CTRL_CONFIG_RDONLY_ENTRY,
> > + .id = V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS,
> > + .name = "reported errors",
> > + .p_def = { .p_const = NULL },
> > + .elem_size = sizeof(struct viif_reported_errors),
> > + },
> > +};
> > +
> > +int visconti_viif_isp_init_controls(struct viif_device *viif_dev)
> > +{
> > + struct v4l2_ctrl_handler *ctrl_handler =
> &viif_dev->isp_subdev.ctrl_handler;
> > + int ret;
> > + int i;
> > +
> > + ret = v4l2_ctrl_handler_init(ctrl_handler, 10);
>
> Replace 10 by ARRAY_SIZE(visconti_viif_isp_ctrl_config), that way the
> control handler has the right hint about the number of controls.
I'll fix it.
> > + if (ret) {
> > + dev_err(viif_dev->dev, "failed on v4l2_ctrl_handler_init");
> > + return ret;
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(visconti_viif_isp_ctrl_config); i++) {
> > + struct v4l2_ctrl *ctrl;
> > +
> > + ctrl = v4l2_ctrl_new_custom(ctrl_handler,
> &visconti_viif_isp_ctrl_config[i],
> > + viif_dev);
> > + if (!ctrl) {
> > + dev_err(viif_dev->dev, "failed to add ctrl crop: %d",
> ctrl_handler->error);
> > + return ctrl_handler->error;
> > + }
> > + }
> > +
> > + viif_dev->isp_subdev.sd.ctrl_handler =
> &viif_dev->isp_subdev.ctrl_handler;
> > + return 0;
> > +}
> > diff --git a/drivers/media/platform/visconti/viif_isp.c
> b/drivers/media/platform/visconti/viif_isp.c
> > index 9314e6e8661..9aeb8bcab9b 100644
> > --- a/drivers/media/platform/visconti/viif_isp.c
> > +++ b/drivers/media/platform/visconti/viif_isp.c
> > @@ -818,6 +818,8 @@ int visconti_viif_isp_register(struct viif_device
> *viif_dev)
> >
> > mutex_init(&viif_dev->isp_subdev.ops_lock);
> >
> > + visconti_viif_isp_init_controls(viif_dev);
> > +
> > ret = media_entity_pads_init(&sd->entity, 4, pads);
> > if (ret) {
> > dev_err(viif_dev->dev, "Failed on media_entity_pads_init\n");
>
> Regards,
>
> Hans
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-26 0:38 ` yuji2.ishikawa
@ 2023-01-26 8:39 ` Hans Verkuil
2023-01-26 11:35 ` Laurent Pinchart
2023-02-02 12:42 ` yuji2.ishikawa
0 siblings, 2 replies; 42+ messages in thread
From: Hans Verkuil @ 2023-01-26 8:39 UTC (permalink / raw)
To: yuji2.ishikawa, laurent.pinchart, mchehab, nobuhiro1.iwamatsu,
robh+dt, krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
On 26/01/2023 01:38, yuji2.ishikawa@toshiba.co.jp wrote:
>>> +#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192
>>> +static int viif_l1_set_dpc(struct viif_device *viif_dev, struct viif_l1_dpc_config
>> *l1_dpc)
>>> +{
>>> + uintptr_t table_h_paddr = 0;
>>> + uintptr_t table_m_paddr = 0;
>>> + uintptr_t table_l_paddr = 0;
>>> + unsigned long irqflags;
>>> + int ret;
>>> +
>>> + if (l1_dpc->table_h_addr) {
>>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
>>> + u64_to_user_ptr(l1_dpc->table_h_addr),
>>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
>>> + return -EFAULT;
>>
>> NACK!
>>
>> I thought those addresses in a struct were iffy. This is not supported, it
>> basically bypasses the whole control framework.
>
> I understand.
>
>> The way to do this is to create separate array controls for these tables.
>> And table_h_addr becomes a simple 0 or 1 value, indicating whether to use
>> the table set by that control. For small arrays it is also an option to
>> embed them in the control structure.
>
> As I wrote in reply for patch 2/6, I thought embedding is the only solution.
> Thank you for giving another plan: adding controls for tables.
> When I use individual controls for tables, are there some orderings between controls?
> -- such that control DPC_TABLE_{H,M,L} should be configured before SET_DPC
There is no ordering dependency. But you can cluster controls:
https://linuxtv.org/downloads/v4l-dvb-apis-new/driver-api/v4l2-controls.html#control-clusters
The idea is that userspace sets all the related controls with one VIDIOC_S_EXT_CTRLS
ioctl, and then for the clustered controls the s_ctrl callback is called only
once.
You can also check in try_ctrl if the controls in a cluster are sane. E.g.
if control A has value 1, and that requires that control B has a value >= 5,
then try_ctrl can verify that. Normally controls are independent from one
another, but clustering will link them together.
It's really what you want here. A good example is here: drivers/media/common/cx2341x.c
It's used by several PCI drivers that use this MPEG codec chipset, and it uses
clusters and also implements try_ctrl.
>
>> Are these l, h and m tables independent from one another? I.e. is it possible
>> to set l but not h and m? I suspect it is all or nothing, and in that case you
>> need only a single control to set all three tables (a two dimensional array).
>
> These three tables can be setup individually.
>
>> Anyway, the same issue applies to all the controls were you pass addresses for
>> tables, that all needs to change.
>
> All right. These controls must be fixed.
>
>>> + table_h_paddr =
>> (uintptr_t)viif_dev->table_paddr->dpc_table_h;
>>> + }
>>> + if (l1_dpc->table_m_addr) {
>>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_m,
>>> + u64_to_user_ptr(l1_dpc->table_m_addr),
>>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
>>> + return -EFAULT;
>>> + table_m_paddr =
>> (uintptr_t)viif_dev->table_paddr->dpc_table_m;
>>> + }
>>> + if (l1_dpc->table_l_addr) {
>>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_l,
>>> + u64_to_user_ptr(l1_dpc->table_l_addr),
>>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
>>> + return -EFAULT;
>>> + table_l_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_l;
>>> + }
>>> +
>>> + spin_lock_irqsave(&viif_dev->lock, irqflags);
>>> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
>>> + ret = hwd_viif_l1_set_dpc_table_transmission(viif_dev->hwd_res,
>> table_h_paddr,
>>> + table_m_paddr,
>> table_l_paddr);
>>> + if (ret)
>>> + goto err;
>>> +
>>> + ret = hwd_viif_l1_set_dpc(viif_dev->hwd_res, &l1_dpc->param_h,
>> &l1_dpc->param_m,
>>> + &l1_dpc->param_l);
>>> +
>>> +err:
>>> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
>>> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
>>> + return ret;
>>> +}
<snip>
>>> +static int visconti_viif_isp_get_ctrl(struct v4l2_ctrl *ctrl)
>>> +{
>>> + struct viif_device *viif_dev = ctrl->priv;
>>> +
>>> + pr_info("isp_get_ctrl: %s", ctrl->name);
>>> + if (pm_runtime_status_suspended(viif_dev->dev)) {
>>> + pr_info("warning: visconti viif HW is not powered");
>>> + return 0;
>>> + }
>>> +
>>> + switch (ctrl->id) {
>>> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
>>> + return viif_csi2rx_get_calibration_status(viif_dev,
>> ctrl->p_new.p);
>>> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
>>> + return viif_csi2rx_get_err_status(viif_dev, ctrl->p_new.p);
>>> + case V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
>>> + return viif_isp_get_last_capture_status(viif_dev,
>> ctrl->p_new.p);
>>> + case V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
>>> + return viif_isp_get_reported_errors(viif_dev, ctrl->p_new.p);
>>
>> My question for these four controls is: are these really volatile controls?
>> A volatile control means that the hardware can change the registers at any
>> time without telling the CPU about it via an interrupt or some similar
>> mechanism.
>>
>> If there *is* such a mechanism, then it is not a volatile control, instead the
>> driver has to update the control value whenever the HW informs it about the
>> new value.
>>
>> I can't tell, so that's why I ask here to double check.
>>
>
> I quickly checked HW and found ...
>
> * CSI2RX_GET_CALIBRATION_STATUS: No interrupt mechanism
So that remains volatile.
> * CSI2RX_GET_ERR_STATUS: An interrupt handler can be used
> * GET_LAST_CAPTURE_STATUS: information can be updated at Vsync interrupt
For these two you can use v4l2_ctrl_s_ctrl to set the new value.
Note that this function takes a mutex, so you might not be able
to call it directly from the irq handler.
> * GET_LAST_ERROR: An interrupt handler can be used
>
> I'll try building control values while running interrupt services.
> Do I have to do G_EXT_CTRLS followed by S_EXT_CTRLS if I want Read-To-Clear operation?
> Currently, GET_LAST_ERROR control reports accumerated errors since last read.
Interesting use-case. I think this can stay a volatile control. Make sure
to document that reading this control will clear the values.
>
>>> + default:
>>> + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
>>> + break;
>>> + }
>>> + return 0;
>>> +}
Regards,
Hans
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-26 8:39 ` Hans Verkuil
@ 2023-01-26 11:35 ` Laurent Pinchart
2023-02-03 1:35 ` yuji2.ishikawa
2023-02-02 12:42 ` yuji2.ishikawa
1 sibling, 1 reply; 42+ messages in thread
From: Laurent Pinchart @ 2023-01-26 11:35 UTC (permalink / raw)
To: Hans Verkuil
Cc: yuji2.ishikawa, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie, linux-media,
linux-arm-kernel, linux-kernel, devicetree
On Thu, Jan 26, 2023 at 09:39:59AM +0100, Hans Verkuil wrote:
> On 26/01/2023 01:38, yuji2.ishikawa@toshiba.co.jp wrote:
> >>> +#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192
> >>> +static int viif_l1_set_dpc(struct viif_device *viif_dev, struct viif_l1_dpc_config
> >> *l1_dpc)
> >>> +{
> >>> + uintptr_t table_h_paddr = 0;
> >>> + uintptr_t table_m_paddr = 0;
> >>> + uintptr_t table_l_paddr = 0;
> >>> + unsigned long irqflags;
> >>> + int ret;
> >>> +
> >>> + if (l1_dpc->table_h_addr) {
> >>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
> >>> + u64_to_user_ptr(l1_dpc->table_h_addr),
> >>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> >>> + return -EFAULT;
> >>
> >> NACK!
> >>
> >> I thought those addresses in a struct were iffy. This is not supported, it
> >> basically bypasses the whole control framework.
> >
> > I understand.
> >
> >> The way to do this is to create separate array controls for these tables.
> >> And table_h_addr becomes a simple 0 or 1 value, indicating whether to use
> >> the table set by that control. For small arrays it is also an option to
> >> embed them in the control structure.
> >
> > As I wrote in reply for patch 2/6, I thought embedding is the only solution.
> > Thank you for giving another plan: adding controls for tables.
> > When I use individual controls for tables, are there some orderings between controls?
> > -- such that control DPC_TABLE_{H,M,L} should be configured before SET_DPC
>
> There is no ordering dependency. But you can cluster controls:
>
> https://linuxtv.org/downloads/v4l-dvb-apis-new/driver-api/v4l2-controls.html#control-clusters
>
> The idea is that userspace sets all the related controls with one VIDIOC_S_EXT_CTRLS
> ioctl, and then for the clustered controls the s_ctrl callback is called only
> once.
>
> You can also check in try_ctrl if the controls in a cluster are sane. E.g.
> if control A has value 1, and that requires that control B has a value >= 5,
> then try_ctrl can verify that. Normally controls are independent from one
> another, but clustering will link them together.
>
> It's really what you want here. A good example is here: drivers/media/common/cx2341x.c
> It's used by several PCI drivers that use this MPEG codec chipset, and it uses
> clusters and also implements try_ctrl.
I think controls are the wrong tool for this job though. The ISP
requires a large number of parameters, which would I think be better
suited passed as a parameters buffer like the ipu3 and rkisp1 driver do
for most of the data. Some parameters may still make sense as controls
(possibly mostly for the CSI2RX parameters), but I haven't checked that
in details.
> >> Are these l, h and m tables independent from one another? I.e. is it possible
> >> to set l but not h and m? I suspect it is all or nothing, and in that case you
> >> need only a single control to set all three tables (a two dimensional array).
> >
> > These three tables can be setup individually.
> >
> >> Anyway, the same issue applies to all the controls were you pass addresses for
> >> tables, that all needs to change.
> >
> > All right. These controls must be fixed.
> >
> >>> + table_h_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_h;
> >>> + }
> >>> + if (l1_dpc->table_m_addr) {
> >>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_m,
> >>> + u64_to_user_ptr(l1_dpc->table_m_addr),
> >>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> >>> + return -EFAULT;
> >>> + table_m_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_m;
> >>> + }
> >>> + if (l1_dpc->table_l_addr) {
> >>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_l,
> >>> + u64_to_user_ptr(l1_dpc->table_l_addr),
> >>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> >>> + return -EFAULT;
> >>> + table_l_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_l;
> >>> + }
> >>> +
> >>> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> >>> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> >>> + ret = hwd_viif_l1_set_dpc_table_transmission(viif_dev->hwd_res, table_h_paddr,
> >>> + table_m_paddr, table_l_paddr);
> >>> + if (ret)
> >>> + goto err;
> >>> +
> >>> + ret = hwd_viif_l1_set_dpc(viif_dev->hwd_res, &l1_dpc->param_h, &l1_dpc->param_m,
> >>> + &l1_dpc->param_l);
> >>> +
> >>> +err:
> >>> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> >>> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> >>> + return ret;
> >>> +}
>
> <snip>
>
> >>> +static int visconti_viif_isp_get_ctrl(struct v4l2_ctrl *ctrl)
> >>> +{
> >>> + struct viif_device *viif_dev = ctrl->priv;
> >>> +
> >>> + pr_info("isp_get_ctrl: %s", ctrl->name);
> >>> + if (pm_runtime_status_suspended(viif_dev->dev)) {
> >>> + pr_info("warning: visconti viif HW is not powered");
> >>> + return 0;
> >>> + }
> >>> +
> >>> + switch (ctrl->id) {
> >>> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
> >>> + return viif_csi2rx_get_calibration_status(viif_dev, ctrl->p_new.p);
> >>> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
> >>> + return viif_csi2rx_get_err_status(viif_dev, ctrl->p_new.p);
> >>> + case V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
> >>> + return viif_isp_get_last_capture_status(viif_dev, ctrl->p_new.p);
> >>> + case V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
> >>> + return viif_isp_get_reported_errors(viif_dev, ctrl->p_new.p);
> >>
> >> My question for these four controls is: are these really volatile controls?
> >> A volatile control means that the hardware can change the registers at any
> >> time without telling the CPU about it via an interrupt or some similar
> >> mechanism.
> >>
> >> If there *is* such a mechanism, then it is not a volatile control, instead the
> >> driver has to update the control value whenever the HW informs it about the
> >> new value.
> >>
> >> I can't tell, so that's why I ask here to double check.
> >
> > I quickly checked HW and found ...
> >
> > * CSI2RX_GET_CALIBRATION_STATUS: No interrupt mechanism
>
> So that remains volatile.
>
> > * CSI2RX_GET_ERR_STATUS: An interrupt handler can be used
> > * GET_LAST_CAPTURE_STATUS: information can be updated at Vsync interrupt
>
> For these two you can use v4l2_ctrl_s_ctrl to set the new value.
> Note that this function takes a mutex, so you might not be able
> to call it directly from the irq handler.
>
> > * GET_LAST_ERROR: An interrupt handler can be used
> >
> > I'll try building control values while running interrupt services.
> > Do I have to do G_EXT_CTRLS followed by S_EXT_CTRLS if I want Read-To-Clear operation?
> > Currently, GET_LAST_ERROR control reports accumerated errors since last read.
>
> Interesting use-case. I think this can stay a volatile control. Make sure
> to document that reading this control will clear the values.
>
> >>> + default:
> >>> + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
> >>> + break;
> >>> + }
> >>> + return 0;
> >>> +}
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-26 11:35 ` Laurent Pinchart
@ 2023-02-03 1:35 ` yuji2.ishikawa
0 siblings, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-03 1:35 UTC (permalink / raw)
To: laurent.pinchart, hverkuil
Cc: mchehab, nobuhiro1.iwamatsu, robh+dt, krzysztof.kozlowski+dt,
rafael.j.wysocki, broonie, linux-media, linux-arm-kernel,
linux-kernel, devicetree
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Thursday, January 26, 2023 8:36 PM
> To: Hans Verkuil <hverkuil@xs4all.nl>
> Cc: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; mchehab@kernel.org; iwamatsu nobuhiro(岩松
> 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> rafael.j.wysocki@intel.com; broonie@kernel.org; linux-media@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver v4l2 controls handler
>
> On Thu, Jan 26, 2023 at 09:39:59AM +0100, Hans Verkuil wrote:
> > On 26/01/2023 01:38, yuji2.ishikawa@toshiba.co.jp wrote:
> > >>> +#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192 static int
> > >>> +viif_l1_set_dpc(struct viif_device *viif_dev, struct
> > >>> +viif_l1_dpc_config
> > >> *l1_dpc)
> > >>> +{
> > >>> + uintptr_t table_h_paddr = 0;
> > >>> + uintptr_t table_m_paddr = 0;
> > >>> + uintptr_t table_l_paddr = 0;
> > >>> + unsigned long irqflags;
> > >>> + int ret;
> > >>> +
> > >>> + if (l1_dpc->table_h_addr) {
> > >>> + if
> (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
> > >>> +
> u64_to_user_ptr(l1_dpc->table_h_addr),
> > >>> +
> VISCONTI_VIIF_DPC_TABLE_SIZE))
> > >>> + return -EFAULT;
> > >>
> > >> NACK!
> > >>
> > >> I thought those addresses in a struct were iffy. This is not
> > >> supported, it basically bypasses the whole control framework.
> > >
> > > I understand.
> > >
> > >> The way to do this is to create separate array controls for these tables.
> > >> And table_h_addr becomes a simple 0 or 1 value, indicating whether
> > >> to use the table set by that control. For small arrays it is also
> > >> an option to embed them in the control structure.
> > >
> > > As I wrote in reply for patch 2/6, I thought embedding is the only solution.
> > > Thank you for giving another plan: adding controls for tables.
> > > When I use individual controls for tables, are there some orderings between
> controls?
> > > -- such that control DPC_TABLE_{H,M,L} should be configured before
> > > SET_DPC
> >
> > There is no ordering dependency. But you can cluster controls:
> >
> > https://linuxtv.org/downloads/v4l-dvb-apis-new/driver-api/v4l2-control
> > s.html#control-clusters
> >
> > The idea is that userspace sets all the related controls with one
> > VIDIOC_S_EXT_CTRLS ioctl, and then for the clustered controls the
> > s_ctrl callback is called only once.
> >
> > You can also check in try_ctrl if the controls in a cluster are sane. E.g.
> > if control A has value 1, and that requires that control B has a value
> > >= 5, then try_ctrl can verify that. Normally controls are independent
> > from one another, but clustering will link them together.
> >
> > It's really what you want here. A good example is here:
> > drivers/media/common/cx2341x.c It's used by several PCI drivers that
> > use this MPEG codec chipset, and it uses clusters and also implements
> try_ctrl.
>
> I think controls are the wrong tool for this job though. The ISP requires a large
> number of parameters, which would I think be better suited passed as a
> parameters buffer like the ipu3 and rkisp1 driver do for most of the data. Some
> parameters may still make sense as controls (possibly mostly for the CSI2RX
> parameters), but I haven't checked that in details.
>
I'm thinking about passing some parameters (especially large tables) with streaming interface (like rkisp1-param).
However this change should be done carefully because 1) HW limitation can be involved and 2) design of userland can change greatly.
Some of my concerns are:
* Some parameters (e.g. L1ISP_INPUT_MODE) should be set before streaming start.
Are Parameters via streaming interface available before streaming start?
I suppose vb2_ops::buf_queue() would be called for ioctl(QBUF),
but I'm not for sure I can use the content stored in vb2_buffer.
* Does streaming interface accept multiple patterns of data layout?
I suppose it accepts only one data layout which includes all the possible parameters and corresponding enable/disable flags. Perhaps, idea like union can be applied to exclusive parameters?
* Can I call QBUF of parameter buffer multiple times for a frame?
I suppose it depends on driver's implementation but most of the drivers assume one QBUF for a frame.
I need more knowledge how userland use drivers. Architecture specific codes in libcamera might help me?
> --
> Regards,
>
> Laurent Pinchart
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler
2023-01-26 8:39 ` Hans Verkuil
2023-01-26 11:35 ` Laurent Pinchart
@ 2023-02-02 12:42 ` yuji2.ishikawa
1 sibling, 0 replies; 42+ messages in thread
From: yuji2.ishikawa @ 2023-02-02 12:42 UTC (permalink / raw)
To: hverkuil, laurent.pinchart, mchehab, nobuhiro1.iwamatsu, robh+dt,
krzysztof.kozlowski+dt, rafael.j.wysocki, broonie
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree
> -----Original Message-----
> From: Hans Verkuil <hverkuil@xs4all.nl>
> Sent: Thursday, January 26, 2023 5:40 PM
> To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開)
> <yuji2.ishikawa@toshiba.co.jp>; laurent.pinchart@ideasonboard.com;
> mchehab@kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; rafael.j.wysocki@intel.com;
> broonie@kernel.org
> Cc: linux-media@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti
> Video Input Interface driver v4l2 controls handler
>
> On 26/01/2023 01:38, yuji2.ishikawa@toshiba.co.jp wrote:
> >>> +#define VISCONTI_VIIF_DPC_TABLE_SIZE 8192 static int
> >>> +viif_l1_set_dpc(struct viif_device *viif_dev, struct
> >>> +viif_l1_dpc_config
> >> *l1_dpc)
> >>> +{
> >>> + uintptr_t table_h_paddr = 0;
> >>> + uintptr_t table_m_paddr = 0;
> >>> + uintptr_t table_l_paddr = 0;
> >>> + unsigned long irqflags;
> >>> + int ret;
> >>> +
> >>> + if (l1_dpc->table_h_addr) {
> >>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_h,
> >>> + u64_to_user_ptr(l1_dpc->table_h_addr),
> >>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> >>> + return -EFAULT;
> >>
> >> NACK!
> >>
> >> I thought those addresses in a struct were iffy. This is not
> >> supported, it basically bypasses the whole control framework.
> >
> > I understand.
> >
> >> The way to do this is to create separate array controls for these tables.
> >> And table_h_addr becomes a simple 0 or 1 value, indicating whether to
> >> use the table set by that control. For small arrays it is also an
> >> option to embed them in the control structure.
> >
> > As I wrote in reply for patch 2/6, I thought embedding is the only solution.
> > Thank you for giving another plan: adding controls for tables.
> > When I use individual controls for tables, are there some orderings between
> controls?
> > -- such that control DPC_TABLE_{H,M,L} should be configured before
> > SET_DPC
>
> There is no ordering dependency. But you can cluster controls:
>
> https://linuxtv.org/downloads/v4l-dvb-apis-new/driver-api/v4l2-controls.html#
> control-clusters
>
> The idea is that userspace sets all the related controls with one
> VIDIOC_S_EXT_CTRLS ioctl, and then for the clustered controls the s_ctrl
> callback is called only once.
>
> You can also check in try_ctrl if the controls in a cluster are sane. E.g.
> if control A has value 1, and that requires that control B has a value >= 5, then
> try_ctrl can verify that. Normally controls are independent from one another, but
> clustering will link them together.
>
> It's really what you want here. A good example is here:
> drivers/media/common/cx2341x.c It's used by several PCI drivers that use this
> MPEG codec chipset, and it uses clusters and also implements try_ctrl.
Thank you for the information. Clustered controls surely will help.
I also have to check if streaming interface works better (as Laurent suggested).
From recent conversation, compound control might not be designed for passing large amount (some kilobytes) of data.
How large the payload assumed to be for typical usecases?
> >
> >> Are these l, h and m tables independent from one another? I.e. is it
> >> possible to set l but not h and m? I suspect it is all or nothing,
> >> and in that case you need only a single control to set all three tables (a two
> dimensional array).
> >
> > These three tables can be setup individually.
> >
> >> Anyway, the same issue applies to all the controls were you pass
> >> addresses for tables, that all needs to change.
> >
> > All right. These controls must be fixed.
> >
> >>> + table_h_paddr =
> >> (uintptr_t)viif_dev->table_paddr->dpc_table_h;
> >>> + }
> >>> + if (l1_dpc->table_m_addr) {
> >>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_m,
> >>> + u64_to_user_ptr(l1_dpc->table_m_addr),
> >>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> >>> + return -EFAULT;
> >>> + table_m_paddr =
> >> (uintptr_t)viif_dev->table_paddr->dpc_table_m;
> >>> + }
> >>> + if (l1_dpc->table_l_addr) {
> >>> + if (copy_from_user(viif_dev->table_vaddr->dpc_table_l,
> >>> + u64_to_user_ptr(l1_dpc->table_l_addr),
> >>> + VISCONTI_VIIF_DPC_TABLE_SIZE))
> >>> + return -EFAULT;
> >>> + table_l_paddr = (uintptr_t)viif_dev->table_paddr->dpc_table_l;
> >>> + }
> >>> +
> >>> + spin_lock_irqsave(&viif_dev->lock, irqflags);
> >>> + hwd_viif_isp_guard_start(viif_dev->hwd_res);
> >>> + ret = hwd_viif_l1_set_dpc_table_transmission(viif_dev->hwd_res,
> >> table_h_paddr,
> >>> + table_m_paddr,
> >> table_l_paddr);
> >>> + if (ret)
> >>> + goto err;
> >>> +
> >>> + ret = hwd_viif_l1_set_dpc(viif_dev->hwd_res, &l1_dpc->param_h,
> >> &l1_dpc->param_m,
> >>> + &l1_dpc->param_l);
> >>> +
> >>> +err:
> >>> + hwd_viif_isp_guard_end(viif_dev->hwd_res);
> >>> + spin_unlock_irqrestore(&viif_dev->lock, irqflags);
> >>> + return ret;
> >>> +}
>
> <snip>
>
> >>> +static int visconti_viif_isp_get_ctrl(struct v4l2_ctrl *ctrl) {
> >>> + struct viif_device *viif_dev = ctrl->priv;
> >>> +
> >>> + pr_info("isp_get_ctrl: %s", ctrl->name);
> >>> + if (pm_runtime_status_suspended(viif_dev->dev)) {
> >>> + pr_info("warning: visconti viif HW is not powered");
> >>> + return 0;
> >>> + }
> >>> +
> >>> + switch (ctrl->id) {
> >>> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
> >>> + return viif_csi2rx_get_calibration_status(viif_dev,
> >> ctrl->p_new.p);
> >>> + case V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
> >>> + return viif_csi2rx_get_err_status(viif_dev, ctrl->p_new.p);
> >>> + case V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
> >>> + return viif_isp_get_last_capture_status(viif_dev,
> >> ctrl->p_new.p);
> >>> + case V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
> >>> + return viif_isp_get_reported_errors(viif_dev, ctrl->p_new.p);
> >>
> >> My question for these four controls is: are these really volatile controls?
> >> A volatile control means that the hardware can change the registers
> >> at any time without telling the CPU about it via an interrupt or some
> >> similar mechanism.
> >>
> >> If there *is* such a mechanism, then it is not a volatile control,
> >> instead the driver has to update the control value whenever the HW
> >> informs it about the new value.
> >>
> >> I can't tell, so that's why I ask here to double check.
> >>
> >
> > I quickly checked HW and found ...
> >
> > * CSI2RX_GET_CALIBRATION_STATUS: No interrupt mechanism
>
> So that remains volatile.
>
> > * CSI2RX_GET_ERR_STATUS: An interrupt handler can be used
> > * GET_LAST_CAPTURE_STATUS: information can be updated at Vsync
> > interrupt
>
> For these two you can use v4l2_ctrl_s_ctrl to set the new value.
> Note that this function takes a mutex, so you might not be able to call it directly
> from the irq handler.
Thank you for your comment.
I'll use workqueue.
> > * GET_LAST_ERROR: An interrupt handler can be used
> >
> > I'll try building control values while running interrupt services.
> > Do I have to do G_EXT_CTRLS followed by S_EXT_CTRLS if I want
> Read-To-Clear operation?
> > Currently, GET_LAST_ERROR control reports accumerated errors since last
> read.
>
> Interesting use-case. I think this can stay a volatile control. Make sure to
> document that reading this control will clear the values.
I'll add the description of this behavior.
> >
> >>> + default:
> >>> + pr_info("unknown_ctrl: id=%08X val=%d", ctrl->id, ctrl->val);
> >>> + break;
> >>> + }
> >>> + return 0;
> >>> +}
>
> Regards,
>
> Hans
Regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v5 5/6] documentation: media: add documentation for Toshiba Visconti Video Input Interface driver
2023-01-11 2:24 [PATCH v5 0/6] Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
` (3 preceding siblings ...)
2023-01-11 2:24 ` [PATCH v5 4/6] media: platform: visconti: Add Toshiba Visconti Video Input Interface driver v4l2 controls handler Yuji Ishikawa
@ 2023-01-11 2:24 ` Yuji Ishikawa
2023-01-11 2:24 ` [PATCH v5 6/6] MAINTAINERS: Add entries for Toshiba Visconti Video Input Interface Yuji Ishikawa
5 siblings, 0 replies; 42+ messages in thread
From: Yuji Ishikawa @ 2023-01-11 2:24 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree, yuji2.ishikawa
Added basic description of Video Input Interface driver of
Toshiba Visconti architecture.
It includes hardware organization, structure of the driver
and description of vendor specific V4L2 controls
to configure the embedded image signal processor.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
---
Changelog v3:
- Newly add documentation to describe SW and HW
Changelog v4:
- no change
Changelog v5:
- no change
---
.../driver-api/media/drivers/index.rst | 1 +
.../media/drivers/visconti-viif.rst | 455 ++++++++++++++++++
2 files changed, 456 insertions(+)
create mode 100644 Documentation/driver-api/media/drivers/visconti-viif.rst
diff --git a/Documentation/driver-api/media/drivers/index.rst b/Documentation/driver-api/media/drivers/index.rst
index 32406490557..ea46cab34ea 100644
--- a/Documentation/driver-api/media/drivers/index.rst
+++ b/Documentation/driver-api/media/drivers/index.rst
@@ -26,6 +26,7 @@ Video4Linux (V4L) drivers
sh_mobile_ceu_camera
tuners
vimc-devel
+ visconti-viif
zoran
ccs/ccs
diff --git a/Documentation/driver-api/media/drivers/visconti-viif.rst b/Documentation/driver-api/media/drivers/visconti-viif.rst
new file mode 100644
index 00000000000..f139f60f9cb
--- /dev/null
+++ b/Documentation/driver-api/media/drivers/visconti-viif.rst
@@ -0,0 +1,455 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+============================================
+Visconti Video Input Interface (VIIF) Driver
+============================================
+
+Overview
+========
+
+The Visconti VIIF Hardware
+--------------------------
+
+The Visconti Video Input Interface (VIIF) hardware is a proprietary videocapture device of Toshiba.
+Following function modules are integrated:
+
+* MIPI CSI2 receiver (CSI2RX)
+* L1 Image Signal Processor (L1ISP)
+
+ * Correction, enhancement, adjustment on RAW pictures.
+
+* L2 Image Signal Processor (L2ISP)
+
+ * Lens distortion correction
+ * Scaling
+ * Cropping
+
+* Video DMAC
+
+ * format picture (RGB, YUV, Grayscale, ...)
+ * write picture into DRAM
+
+Visconti5 SoC has two VIIF hardware instances.
+
+software architecture
+---------------------
+
+The Visconti VIIF driver is composed of following components:
+
+* (image sensor driver)
+* Visconti ISP subdevice driver
+
+ * corresponding to CSI2RX, L1ISP, L2ISP (Lens distortion correction, Scaling)
+
+* Visconti Capture V4L2 device driver
+
+ * corresponding to L2ISP (Cropping) and Video DMAC
+ * multiple output videobuf queues
+
+ * main path0 (RGB, YUV, Grayscale, ...)
+ * main path1 (RGB, YUV, Grayscale, ...)
+ * sub path (RAW picture)
+
+::
+
+ +-----------+ +------------------------+ +-------------------------+
+ | Sensor | | ISP | | Capture MAIN PATH0 |
+ | subdevice | ---- | subdevice | --+-- | V4L2 device |
+ | (IMX219) | | (CSI2RX, L1ISP, L2ISP) | | | (L2ISP crop, VideoDMAC) |
+ +-----------+ +------------------------+ | +-------------------------+
+ |
+ | +-------------------------+
+ | | Capture MAIN PATH1 |
+ +-- | V4L2 device |
+ | | (L2ISP crop, VideoDMAC) |
+ | +-------------------------+
+ |
+ | +-------------------------+
+ | | Capture SUB PATH |
+ +-- | V4L2 device |
+ | (L2ISP crop, VideoDMAC) |
+ +-------------------------+
+
+
+The VIIF driver provides following device nodes for Visconti5 SoC:
+
+* VIIF0
+
+ * /dev/media0
+ * /dev/video0 (main path0)
+ * /dev/video1 (main path1)
+ * /dev/video2 (sub path)
+
+* VIIF1
+
+ * /dev/media1
+ * /dev/video3
+ * /dev/video4
+ * /dev/video5
+
+Use of coherent memory
+----------------------
+
+Visconti5 SoC has two independent DDR SDRAM controllers.
+Each controller is mapped to 36bit address space.
+
+Accelerator bus masters have two paths to access memory;
+one is directly connected to SDRAM controller,
+the another is connected via a cache coherency bus
+which keeps coherency among CPUs.
+
+From acclerators and CPUs, the address map is following:
+
+* 0x0_8000_0000 DDR0 direct access
+* 0x4_8000_0000 DDR0 coherency bus
+* 0x8_8000_0000 DDR1 direct access
+* 0xC_8000_0000 DDR1 coherency bus
+
+The base address can be specified with "memory" and "reserved-memory" elements
+in a device tree description.
+It's not recommended to mix direct address and coherent address.
+
+The Visconti5 VIIF driver always use only direct address to configure Video DMACs of the hardware.
+This design is to avoid great performance loss at coherency bus caused by massive memory access.
+You should not put the dma_coherent attribute to viif element in device tree.
+Cache operations are done automatically by videobuf2 driver.
+
+Tested environment
+------------------
+
+The Visconti VIIF driver was tested with following items:
+
+* IMX219 image sensor
+* IMX335 image sensor
+* TC358743 HDMI to MIPI CSI2 converter
+
+IOCTLs
+======
+
+Following public IOCTLs are supported
+
+* VIDIOC_QUERYCAP
+* VIDIOC_ENUM_FMT
+* VIDIOC_TRY_FMT
+* VIDIOC_S_FMT
+* VIDIOC_G_FMT
+* VIDIOC_ENUM_INPUT
+* VIDIOC_G_INPUT
+* VIDIOC_S_INPUT
+* VIDIOC_G_SELECTION
+* VIDIOC_S_SELECTION
+* VIDIOC_DV_TIMINGS_CAP
+* VIDIOC_ENUM_DV_TIMINGS
+* VIDIOC_G_DV_TIMINGS
+* VIDIOC_S_DV_TIMINGS
+* VIDIOC_QUERY_DV_TIMINGS
+* VIDIOC_G_EDID
+* VIDIOC_S_EDID
+* VIDIOC_G_PARM
+* VIDIOC_S_PARM
+* VIDIOC_ENUM_FRAMESIZES
+* VIDIOC_ENUM_FRAMEINTERVALS
+* VIDIOC_G_EXT_CTRLS
+* VIDIOC_S_EXT_CTRLS
+
+Vendor specific v4l2 controls
+=============================
+
+.. _V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE:
+
+V4L2_CID_VISCONTI_VIIF_MAIN_SET_RAWPACK_MODE
+--------------------------------------------
+
+This control sets the format to pack multiple RAW pixel values into a word.
+
+This control accepts a __u32 value defined as `enum viif_rawpack_mode`.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_INPUT_MODE
+--------------------------------------------
+
+This control sets L1ISP preprocessing mode for RAW input images.
+
+This control accepts a `struct viif_l1_input_mode_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RGB_TO_Y_COEF
+-----------------------------------------------
+
+This control sets parameters to yield Y value from RGB pixel values.
+
+This control accepts a `struct viif_l1_rgb_to_y_coef_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE
+-----------------------------------------
+
+This control sets rules for yielding analog gains for each feature in L1ISP.
+Related features are:
+
+* Optical Black Clamp Correction (OBCC)
+* Defect Pixel Correction (DPC)
+* RAW Color Noise Reduction (RCNR)
+* Lens Shading Correction (LSC)
+* Color matrix correction (MPRO)
+* Image quality adjustment (VPRO)
+
+The base gain is brought by V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG control.
+
+This control accepts a `struct viif_l1_ag_mode_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG
+------------------------------------
+
+This control sets base analog gain values comonly used in L1ISP features.
+Each analog gain in some features also refers V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AG_MODE control.
+
+This control accepts a `struct viif_l1_ag_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRE
+--------------------------------------
+
+This controls sets parameters for HDR Expansion feature.
+
+This control accepts a `struct viif_l1_hdre_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_EXTRACTION
+------------------------------------------------
+
+This control sets black level parameters for L1ISP inputs.
+
+This control accepts a `struct viif_l1_img_extraction_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_DPC
+-------------------------------------
+
+This control sets parameters for Defect Pixel Correction.
+
+This control accepts a `struct viif_l1_dpc_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_PRESET_WHITE_BALANCE
+------------------------------------------------------
+
+This control sets parameters for white balance.
+
+This control accepts a `struct viif_l1_preset_white_balance_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_RAW_COLOR_NOISE_REDUCTION
+-----------------------------------------------------------
+
+This control sets parameters for RAW color noise reduction (RCNR) feature.
+
+This control accepts a `struct viif_l1_raw_color_noise_reduction_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRS
+--------------------------------------
+
+This control sets parameters for HDR synthesis.
+
+This control accepts a `struct viif_l1_hdrs_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_BLACK_LEVEL_CORRECTION
+--------------------------------------------------------
+
+This control sets parameters for black level correction feature.
+
+This control accepts a `struct viif_l1_black_level_correction_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_LSC
+-------------------------------------
+
+This control sets parameters for Lens Shading Correction feature.
+L1ISP supports 2 correction methods:
+
+* parabola shading
+* grid shading
+
+This control accepts a `struct viif_l1_lsc_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_MAIN_PROCESS
+----------------------------------------------
+
+This controls sets parameter for the MAIN PROCESS feature which is composed of:
+
+* demosaic
+* color matrix correction
+
+This control accepts a `struct viif_l1_main_process_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AWB
+-------------------------------------
+
+This control sets parameter for auto white balance feature.
+
+This control accepts a `struct viif_l1_awb_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_LOCK_AWB_GAIN
+-------------------------------------------
+
+This control requests enable/disable of lock for AWB gain.
+
+This control accepts a u32 value; 0 for disable lock, 1 for enable lock.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC
+--------------------------------------
+
+This control sets parameter for HDR Compression feature.
+
+This control accepts a `struct viif_l1_hdrc_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_HDRC_LTM
+------------------------------------------
+
+This control sets parameter for HDR Compression Local Tone Mapping feature.
+
+This control accepts a `struct viif_l1_hdrc_ltm_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_GAMMA
+---------------------------------------
+
+This control sets parameter for gamma correction at L1ISP.
+
+This control accepts a `struct viif_l1_gamma_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_IMG_QUALITY_ADJUSTMENT
+--------------------------------------------------------
+
+This control sets parameter for VPRO feature which is composed of:
+
+* luminance adjustment:
+
+ * brightness adjustment
+ * linear contrast adjusment
+ * nonlinear contrast adjustment
+ * luminance noise reduction
+ * edge enhancement
+
+* chroma adjustment:
+
+ * chroma suppression
+ * color level adjustment
+ * chroma noise reduction
+ * coring suppression
+ * edge chroma suppression
+ * color noise reduction
+
+This control accepts a `struct viif_l1_img_quality_adjustment_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L1_SET_AVG_LUM_GENERATION
+----------------------------------------------------
+
+This control sets parameter for average luminance statistics feature.
+
+This control accepts a `struct viif_l1_avg_lum_generation_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_UNDIST
+----------------------------------------
+
+This control sets parameter for the lens undistortion feature of L2ISP.
+Lens undistortion parameters are defined as either or combination of polinomial parameter and grid table.
+
+This control accepts a `struct viif_l2_undist_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_ROI
+-------------------------------------
+
+This control sets dimensions of intermediate images and scaling parameter of L2ISP.
+If you are inserested in cropping pictures,
+you should use VIDIOC_S_SELECTION ioctl for the corresponding capture device.
+
+This control accepts a `struct viif_l2_roi_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA:
+
+V4L2_CID_VISCONTI_VIIF_ISP_L2_SET_GAMMA
+---------------------------------------
+
+This control sets gamma parameter for L2ISP.
+
+This control accepts a `struct viif_l2_gamma_config` instance.
+
+.. _V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS:
+
+V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_CALIBRATION_STATUS
+----------------------------------------------------
+
+This control provides CSI2 receiver calibration status.
+
+This control fills a `struct viif_csi2rx_cal_status` instance with current status.
+
+.. _V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS:
+
+V4L2_CID_VISCONTI_VIIF_CSI2RX_GET_ERR_STATUS
+--------------------------------------------
+
+This control provides CSI2 receiver error description.
+
+This control fills a `struct viif_csi2rx_err_status` instance with current status.
+
+.. _V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS:
+
+V4L2_CID_VISCONTI_VIIF_GET_LAST_CAPTURE_STATUS
+----------------------------------------------
+
+This control provides status information for the last captured frame.
+
+This control fills a `struct viif_l1_info` instance with current status.
+
+.. _V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS:
+
+V4L2_CID_VISCONTI_VIIF_GET_REPORTED_ERRORS
+------------------------------------------
+
+This control provides error information since the last read of this control.
+
+This control fills a `struct viif_reported_errors` instance with current status.
+
+Structures
+==========
+
+.. kernel-doc:: include/uapi/linux/visconti_viif.h
+
+Code example
+============
+
--
2.25.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v5 6/6] MAINTAINERS: Add entries for Toshiba Visconti Video Input Interface
2023-01-11 2:24 [PATCH v5 0/6] Add Toshiba Visconti Video Input Interface driver Yuji Ishikawa
` (4 preceding siblings ...)
2023-01-11 2:24 ` [PATCH v5 5/6] documentation: media: add documentation for Toshiba Visconti Video Input Interface driver Yuji Ishikawa
@ 2023-01-11 2:24 ` Yuji Ishikawa
5 siblings, 0 replies; 42+ messages in thread
From: Yuji Ishikawa @ 2023-01-11 2:24 UTC (permalink / raw)
To: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Nobuhiro Iwamatsu, Rob Herring, Krzysztof Kozlowski,
Rafael J . Wysocki, Mark Brown
Cc: linux-media, linux-arm-kernel, linux-kernel, devicetree, yuji2.ishikawa
Added entries for visconti Video Input Interface driver, including;
* device tree bindings
* source files
* documentation files
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
---
Changelog v2:
- no change
Changelog v3:
- added entry for driver API documentation
Changelog v4:
- added entry for header file
Changelog v5:
- no change
---
MAINTAINERS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 886d3f69ee6..e83ec3af09e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3014,18 +3014,22 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git
F: Documentation/devicetree/bindings/arm/toshiba.yaml
F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
F: Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
+F: Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml
F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
F: Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
+F: Documentation/driver-api/media/drivers/visconti-viif.rst
F: arch/arm64/boot/dts/toshiba/
F: drivers/clk/visconti/
+F: drivers/media/platform/visconti/
F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
F: drivers/gpio/gpio-visconti.c
F: drivers/pci/controller/dwc/pcie-visconti.c
F: drivers/pinctrl/visconti/
F: drivers/watchdog/visconti_wdt.c
+F: include/uapi/linux/visconti_viif.h
N: visconti
ARM/UNIPHIER ARCHITECTURE
--
2.25.1
^ permalink raw reply related [flat|nested] 42+ messages in thread