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From: Conor Dooley <conor@kernel.org>
To: Hal Feng <hal.feng@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Date: Thu, 16 Feb 2023 18:20:34 +0000	[thread overview]
Message-ID: <Y+5z8skN2DuvxDEL@spud> (raw)
In-Reply-To: <5cf0fe71-fd17-fb28-c01e-28356081ba76@starfivetech.com>

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Hey Hal!

On Thu, Feb 16, 2023 at 10:42:20PM +0800, Hal Feng wrote:
> On Tue, 27 Dec 2022 20:15:20 +0000, Conor Dooley wrote:
> > On Mon, Dec 26, 2022 at 12:26:32AM +0800, Hal Feng wrote:
> >> On Tue, 20 Dec 2022 23:14:39 +0000, Conor Dooley wrote:
> >> > On Tue, Dec 20, 2022 at 08:50:50AM +0800, Hal Feng wrote:
> >> > > From: Emil Renner Berthing <kernel@esmil.dk>
> >> > > 
> >> > > Add bindings for the system clock and reset generator (SYSCRG) on the
> >> > > JH7110 RISC-V SoC by StarFive Ltd.
> >> > > 
> >> > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> >> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > 
> >> > > +  clocks:
> >> > > +    items:
> >> > > +      - description: Main Oscillator (24 MHz)
> >> > > +      - description: GMAC1 RMII reference
> >> > > +      - description: GMAC1 RGMII RX
> >> > > +      - description: External I2S TX bit clock
> >> > > +      - description: External I2S TX left/right channel clock
> >> > > +      - description: External I2S RX bit clock
> >> > > +      - description: External I2S RX left/right channel clock
> >> > > +      - description: External TDM clock
> >> > > +      - description: External audio master clock
> >> > 
> >> > So, from peeking at the clock driver & the dt - it looks like a bunch of
> >> > these are not actually required?
> >> 
> >> These clocks are used as root clocks or optional parent clocks in clock tree.
> >> Some of them are optional, but they are required if we want to describe the
> >> complete clock tree of JH7110 SoC.
> > 
> > Perhaps I have a misunderstand of what required means. To me, required
> > means "you must provide this clock for the SoC to operate in all
> > configurations".
> > Optional therefore would be for things that are needed only for some
> > configurations and may be omitted if not required.
> > 
> > From your comment below, boards with a JH7110 may choose not to populate
> > both external clock inputs to a mux. In that case, "dummy" clocks should
> > not have to be provided in the DT of such boards to satisfy this binding
> > which seems wrong to me..
> 
> Please see the picture of these external clocks in clock tree.
> 
> # mount -t debugfs none /mnt
> # cat /mnt/clk/clk_summary
>                                  enable  prepare  protect                                duty  hardware
>    clock                          count    count    count        rate   accuracy phase  cycle    enable
> -------------------------------------------------------------------------------------------------------
>  *mclk_ext*                             0        0        0    12288000          0     0  50000         Y
>  *tdm_ext*                              0        0        0    49152000          0     0  50000         Y
>  *i2srx_lrck_ext*                       0        0        0      192000          0     0  50000         Y
>  *i2srx_bclk_ext*                       0        0        0    12288000          0     0  50000         Y
>  *i2stx_lrck_ext*                       0        0        0      192000          0     0  50000         Y
>  *i2stx_bclk_ext*                       0        0        0    12288000          0     0  50000         Y
>  *gmac1_rgmii_rxin*                     0        0        0   125000000          0     0  50000         Y
>     gmac1_rx                          0        0        0   125000000          0     0  50000         Y
>        gmac1_rx_inv                   0        0        0   125000000          0   180  50000         Y
>  *gmac1_rmii_refin*                     0        0        0    50000000          0     0  50000         Y
>     gmac1_rmii_rtx                    0        0        0    50000000          0     0  50000         Y
>        gmac1_tx                       0        0        0    50000000          0     0  50000         N
>           gmac1_tx_inv                0        0        0    50000000          0   180  50000         Y
>  *osc*                                  4        4        0    24000000          0     0  50000         Y
>     apb_func                          0        0        0    24000000          0     0  50000         Y
>  ...
> 
> The clock "gmac1_rgmii_rxin" and the clock "gmac1_rmii_refin" are
> actually used as the parent of other clocks.

> The "dummy" clocks
> you said are all internal clocks.

No, what I meant by "dummy" clocks is that if you make clocks "required"
in the binding that are not needed by the hardware for operation a
customer of yours might have to add "dummy" clocks to their devicetree
to pass dtbs_check.

> For the audio related clocks (mclk_ext/tdm_ext/i2srx_lrck_ext/
> i2srx_bclk_ext/i2stx_lrck_ext/i2stx_bclk_ext), they will be used
> as the parent clocks in audio related drivers. Note that some
> clocks need to select different clocks as parent according to
> requirement.
> So all these external clocks are required.
> 
> > 
> > It would seem to me that you need to set minItems < maxItems here to
> > account for that & you do in fact need clock-names.
> > 
> >> 
> >> > I'd have ploughed through this, but having read Krzysztof's comments on
> >> > the DTS I'm not sure that this binding is correct.
> >> > https://lore.kernel.org/linux-riscv/20221220011247.35560-1-hal.feng@starfivetech.com/T/#mdf67621a2344dce801aa8015d4963593a2c28bcc
> >> > 
> >> > I *think* the DT is correct - the fixed clocks are all inputs from clock
> >> > sources on the board and as such they are empty in soc.dtsi and are
> >> > populated in board.dts?
> >> 
> >> Yes, the fixed clocks are all clock sources on the board and input to the SoC.
> >> 
> >> > 
> >> > However, are they all actually required? In the driver I see:
> >> > 	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
> >> > 		    JH7110_SYSCLK_GMAC1_RGMII_RXIN,
> >> > 		    JH7110_SYSCLK_GMAC1_RMII_RTX),
> >> > That macro is:
> >> > #define JH71X0__MUX(_idx, _name, _nparents, ...) [_idx] = {			\
> >> > 	.name = _name,								\
> >> > 	.flags = 0,								\
> >> > 	.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT,			\
> >> > 	.parents = { __VA_ARGS__ },						\
> >> > }

> >> > AFAICT, RMII reference feeds RMII_RTX & RGMII RX *is* RGMII_RXIN?
> >> > Does that mean you need to populate only one of GMAC1 RMII reference
> >> > and GMAC1 RMGII RX and the other is optional?

> >> Yes, actually only one of them is chosen as the root clock
> >> source of the clock "gmac1_rx".
|  *gmac1_rgmii_rxin*   
|     gmac1_rx          
|        gmac1_rx_inv   
|  *gmac1_rmii_refin*   
|     gmac1_rmii_rtx    
|        gmac1_tx       
|           gmac1_tx_inv
|
| description: GMAC1 RMII reference
| description: GMAC1 RGMII RX


So you're telling me that you can either:
- Provide GMAC1 RMII reference and GMAC1 RGMII RX & then use different
  clocks for gmac1_rx and gmac1_tx
- Provide only GMAC1 RMII reference & use it for both gmac1_tx *and*
  gmac1_rx

Is that correct?

> >> > 
> >> > > +
> >> > > +  clock-names:
> >> > > +    items:
> >> > > +      - const: osc
> >> > > +      - const: gmac1_rmii_refin
> >> > > +      - const: gmac1_rgmii_rxin
> >> > > +      - const: i2stx_bclk_ext
> >> > > +      - const: i2stx_lrck_ext
> >> > > +      - const: i2srx_bclk_ext
> >> > > +      - const: i2srx_lrck_ext
> >> > > +      - const: tdm_ext
> >> > > +      - const: mclk_ext
> >> > 
> >> > If all clocks are in fact required though, isn't this kinda pointless to
> >> > have since we already know that the order is fixed from the "clocks"
> >> > property?
> >> > Krzk/Rob?
> >> 
> >> The clock-names are used to easily identify these clocks in the clock driver.
> > 
> > *IF* all clocks were in fact required, which they aren't, you could rely
> > on the order alone in the driver as it is enforced by the binding.
> 
> OK, I'll remove "clock-names" property in the bindings and device tree.
> Instead, will use index to get these clocks in drivers.

Hang on until you answer my question above before deleting this from the
dt-binding & driver ;)


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  reply	other threads:[~2023-02-16 18:20 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-20  0:50 [PATCH v3 00/11] Basic clock and reset support for StarFive JH7110 RISC-V SoC Hal Feng
2022-12-20  0:50 ` [PATCH v3 01/11] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2022-12-20 21:54   ` Conor Dooley
2022-12-20  0:50 ` [PATCH v3 02/11] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2022-12-20 22:08   ` Conor Dooley
2022-12-23  6:23     ` Hal Feng
2022-12-20  0:50 ` [PATCH v3 03/11] reset: Create subdirectory for StarFive drivers Hal Feng
2022-12-20 22:15   ` Conor Dooley
2022-12-23  7:02     ` Hal Feng
2022-12-20  0:50 ` [PATCH v3 04/11] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2022-12-20 22:28   ` Conor Dooley
2022-12-23  7:49     ` Hal Feng
2022-12-20  0:50 ` [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2022-12-20  2:40   ` kernel test robot
2022-12-20 22:31   ` Conor Dooley
2022-12-24  3:48   ` kernel test robot
2022-12-20  0:50 ` [PATCH v3 06/11] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2022-12-20 22:49   ` Conor Dooley
2022-12-20  0:50 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2022-12-20 20:12   ` Rob Herring
2022-12-20 23:14   ` Conor Dooley
2022-12-20 23:16     ` Conor Dooley
2022-12-25 16:26     ` Hal Feng
2022-12-27 20:15       ` Conor Dooley
2023-02-16 14:42         ` Hal Feng
2023-02-16 18:20           ` Conor Dooley [this message]
2023-02-17  2:27             ` Hal Feng
2023-02-17  7:51               ` Conor Dooley
2023-02-17 12:20                 ` Hal Feng
2023-02-17 13:32                   ` Conor Dooley
2023-02-17 15:47                     ` Krzysztof Kozlowski
2023-02-17 16:27                       ` Conor Dooley
2023-02-18 10:20                         ` Krzysztof Kozlowski
2023-02-18 11:17                           ` Conor Dooley
2023-02-18 14:55                             ` Krzysztof Kozlowski
2023-02-18 15:08                               ` Conor Dooley
2023-02-21 22:17             ` Stephen Boyd
2023-02-21 23:39               ` Conor Dooley
2023-02-22 13:27                 ` Hal Feng
2023-02-22 16:26                   ` Conor Dooley
2023-02-23  3:03                     ` Hal Feng
2023-02-23  6:18                       ` Conor Dooley
2023-02-23  9:52                         ` Hal Feng
2022-12-20  0:50 ` [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2022-12-20 20:14   ` Rob Herring
2022-12-20 23:19   ` Conor Dooley
2023-02-16 17:19     ` Hal Feng
2022-12-20  0:50 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2022-12-23  9:57   ` kernel test robot
2023-01-05 11:32   ` kernel test robot
2023-02-19 21:23   ` Emil Renner Berthing
2023-02-21  6:44     ` Hal Feng
2022-12-20  0:50 ` [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2022-12-23 11:28   ` kernel test robot
2023-01-05 13:44   ` kernel test robot
2022-12-20  0:50 ` [PATCH v3 11/11] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2022-12-20  7:14   ` kernel test robot
2022-12-23 12:39   ` kernel test robot
2022-12-27 19:20   ` kernel test robot
2023-01-05 15:35   ` kernel test robot

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