From: Conor Dooley <conor@kernel.org>
To: Hal Feng <hal.feng@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
Date: Tue, 20 Dec 2022 22:31:05 +0000 [thread overview]
Message-ID: <Y6I3qbp34+0Mc4lk@spud> (raw)
In-Reply-To: <20221220005054.34518-6-hal.feng@starfivetech.com>
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On Tue, Dec 20, 2022 at 08:50:48AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> For the common code will be shared with the StarFive JH7110 SoC.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Label on the tin seems to match the contents.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> ---
> .../reset/starfive/reset-starfive-jh7100.c | 2 +-
> .../reset/starfive/reset-starfive-jh71x0.c | 50 +++++++++----------
> .../reset/starfive/reset-starfive-jh71x0.h | 2 +-
> 3 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
> index 9d7cb4ed8869..5f06e5ae3346 100644
> --- a/drivers/reset/starfive/reset-starfive-jh7100.c
> +++ b/drivers/reset/starfive/reset-starfive-jh7100.c
> @@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> - return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
> + return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
> base + JH7100_RESET_ASSERT0,
> base + JH7100_RESET_STATUS0,
> jh7100_reset_asserted,
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
> index ee8c28f9bcb5..1f201c612583 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.c
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-or-later
> /*
> - * Reset driver for the StarFive JH7100 SoC
> + * Reset driver for the StarFive JH71X0 SoCs
> *
> * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
> */
> @@ -13,7 +13,7 @@
> #include <linux/reset-controller.h>
> #include <linux/spinlock.h>
>
> -struct jh7100_reset {
> +struct jh71x0_reset {
> struct reset_controller_dev rcdev;
> /* protect registers against concurrent read-modify-write */
> spinlock_t lock;
> @@ -22,16 +22,16 @@ struct jh7100_reset {
> const u64 *asserted;
> };
>
> -static inline struct jh7100_reset *
> -jh7100_reset_from(struct reset_controller_dev *rcdev)
> +static inline struct jh71x0_reset *
> +jh71x0_reset_from(struct reset_controller_dev *rcdev)
> {
> - return container_of(rcdev, struct jh7100_reset, rcdev);
> + return container_of(rcdev, struct jh71x0_reset, rcdev);
> }
>
> -static int jh7100_reset_update(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
> unsigned long id, bool assert)
> {
> - struct jh7100_reset *data = jh7100_reset_from(rcdev);
> + struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
> unsigned long offset = BIT_ULL_WORD(id);
> u64 mask = BIT_ULL_MASK(id);
> void __iomem *reg_assert = data->assert + offset * sizeof(u64);
> @@ -60,34 +60,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
> return ret;
> }
>
> -static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
> unsigned long id)
> {
> - return jh7100_reset_update(rcdev, id, true);
> + return jh71x0_reset_update(rcdev, id, true);
> }
>
> -static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
> unsigned long id)
> {
> - return jh7100_reset_update(rcdev, id, false);
> + return jh71x0_reset_update(rcdev, id, false);
> }
>
> -static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
> unsigned long id)
> {
> int ret;
>
> - ret = jh7100_reset_assert(rcdev, id);
> + ret = jh71x0_reset_assert(rcdev, id);
> if (ret)
> return ret;
>
> - return jh7100_reset_deassert(rcdev, id);
> + return jh71x0_reset_deassert(rcdev, id);
> }
>
> -static int jh7100_reset_status(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
> unsigned long id)
> {
> - struct jh7100_reset *data = jh7100_reset_from(rcdev);
> + struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
> unsigned long offset = BIT_ULL_WORD(id);
> u64 mask = BIT_ULL_MASK(id);
> void __iomem *reg_status = data->status + offset * sizeof(u64);
> @@ -96,25 +96,25 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
> return !((value ^ data->asserted[offset]) & mask);
> }
>
> -static const struct reset_control_ops jh7100_reset_ops = {
> - .assert = jh7100_reset_assert,
> - .deassert = jh7100_reset_deassert,
> - .reset = jh7100_reset_reset,
> - .status = jh7100_reset_status,
> +static const struct reset_control_ops jh71x0_reset_ops = {
> + .assert = jh71x0_reset_assert,
> + .deassert = jh71x0_reset_deassert,
> + .reset = jh71x0_reset_reset,
> + .status = jh71x0_reset_status,
> };
>
> -int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
> +int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
> void __iomem *assert, void __iomem *status,
> const u64 *asserted, unsigned int nr_resets,
> struct module *owner)
> {
> - struct jh7100_reset *data;
> + struct jh71x0_reset *data;
>
> data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> if (!data)
> return -ENOMEM;
>
> - data->rcdev.ops = &jh7100_reset_ops;
> + data->rcdev.ops = &jh71x0_reset_ops;
> data->rcdev.owner = owner;
> data->rcdev.nr_resets = nr_resets;
> data->rcdev.dev = dev;
> @@ -127,4 +127,4 @@ int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_no
>
> return devm_reset_controller_register(dev, &data->rcdev);
> }
> -EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
> +EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
> index 1fc5a648c8d8..ac9e80dd3f59 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
> @@ -6,7 +6,7 @@
> #ifndef __RESET_STARFIVE_JH71X0_H
> #define __RESET_STARFIVE_JH71X0_H
>
> -int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
> +int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
> void __iomem *assert, void __iomem *status,
> const u64 *asserted, unsigned int nr_resets,
> struct module *owner);
> --
> 2.38.1
>
>
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next prev parent reply other threads:[~2022-12-20 22:31 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-20 0:50 [PATCH v3 00/11] Basic clock and reset support for StarFive JH7110 RISC-V SoC Hal Feng
2022-12-20 0:50 ` [PATCH v3 01/11] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2022-12-20 21:54 ` Conor Dooley
2022-12-20 0:50 ` [PATCH v3 02/11] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2022-12-20 22:08 ` Conor Dooley
2022-12-23 6:23 ` Hal Feng
2022-12-20 0:50 ` [PATCH v3 03/11] reset: Create subdirectory for StarFive drivers Hal Feng
2022-12-20 22:15 ` Conor Dooley
2022-12-23 7:02 ` Hal Feng
2022-12-20 0:50 ` [PATCH v3 04/11] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2022-12-20 22:28 ` Conor Dooley
2022-12-23 7:49 ` Hal Feng
2022-12-20 0:50 ` [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2022-12-20 2:40 ` kernel test robot
2022-12-20 22:31 ` Conor Dooley [this message]
2022-12-24 3:48 ` kernel test robot
2022-12-20 0:50 ` [PATCH v3 06/11] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2022-12-20 22:49 ` Conor Dooley
2022-12-20 0:50 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2022-12-20 20:12 ` Rob Herring
2022-12-20 23:14 ` Conor Dooley
2022-12-20 23:16 ` Conor Dooley
2022-12-25 16:26 ` Hal Feng
2022-12-27 20:15 ` Conor Dooley
2023-02-16 14:42 ` Hal Feng
2023-02-16 18:20 ` Conor Dooley
2023-02-17 2:27 ` Hal Feng
2023-02-17 7:51 ` Conor Dooley
2023-02-17 12:20 ` Hal Feng
2023-02-17 13:32 ` Conor Dooley
2023-02-17 15:47 ` Krzysztof Kozlowski
2023-02-17 16:27 ` Conor Dooley
2023-02-18 10:20 ` Krzysztof Kozlowski
2023-02-18 11:17 ` Conor Dooley
2023-02-18 14:55 ` Krzysztof Kozlowski
2023-02-18 15:08 ` Conor Dooley
2023-02-21 22:17 ` Stephen Boyd
2023-02-21 23:39 ` Conor Dooley
2023-02-22 13:27 ` Hal Feng
2023-02-22 16:26 ` Conor Dooley
2023-02-23 3:03 ` Hal Feng
2023-02-23 6:18 ` Conor Dooley
2023-02-23 9:52 ` Hal Feng
2022-12-20 0:50 ` [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2022-12-20 20:14 ` Rob Herring
2022-12-20 23:19 ` Conor Dooley
2023-02-16 17:19 ` Hal Feng
2022-12-20 0:50 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2022-12-23 9:57 ` kernel test robot
2023-01-05 11:32 ` kernel test robot
2023-02-19 21:23 ` Emil Renner Berthing
2023-02-21 6:44 ` Hal Feng
2022-12-20 0:50 ` [PATCH v3 10/11] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2022-12-23 11:28 ` kernel test robot
2023-01-05 13:44 ` kernel test robot
2022-12-20 0:50 ` [PATCH v3 11/11] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2022-12-20 7:14 ` kernel test robot
2022-12-23 12:39 ` kernel test robot
2022-12-27 19:20 ` kernel test robot
2023-01-05 15:35 ` kernel test robot
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