From: Vinod Koul <vkoul@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: martin.petersen@oracle.com, jejb@linux.ibm.com,
andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
konrad.dybcio@somainline.org, robh+dt@kernel.org,
quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org,
dmitry.baryshkov@linaro.org, ahalaney@redhat.com
Subject: Re: [PATCH v2 02/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode
Date: Fri, 11 Nov 2022 12:31:15 +0530 [thread overview]
Message-ID: <Y23zO68Bb5R0xLq/@matsya> (raw)
In-Reply-To: <20221031180217.32512-3-manivannan.sadhasivam@linaro.org>
On 31-10-22, 23:32, Manivannan Sadhasivam wrote:
> Add separate tables_hs_b instance to allow the PHY driver to configure the
> PHY in HS Series B mode. The individual SoC configs need to supply the
> serdes register setting in tables_hs_b and the UFS driver can request the
> Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index cdfda4e6d575..4c6a2b5afc9a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -20,6 +20,8 @@
> #include <linux/reset.h>
> #include <linux/slab.h>
>
> +#include <ufs/unipro.h>
> +
> #include <dt-bindings/phy/phy.h>
>
> #include "phy-qcom-qmp.h"
> @@ -549,6 +551,8 @@ struct qmp_phy_cfg {
>
> /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> const struct qmp_phy_cfg_tables tables;
> + /* Additional sequence for HS Series B */
> + const struct qmp_phy_cfg_tables tables_hs_b;
what am i missing, where was tables_hs_b added?
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -582,6 +586,7 @@ struct qmp_phy_cfg {
> * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
> * @pcs_misc: iomapped memory space for lane's pcs_misc
> * @qmp: QMP phy to which this lane belongs
> + * @mode: PHY mode configured by the UFS driver
> */
> struct qmp_phy {
> struct phy *phy;
> @@ -594,6 +599,7 @@ struct qmp_phy {
> void __iomem *rx2;
> void __iomem *pcs_misc;
> struct qcom_qmp *qmp;
> + u32 mode;
> };
>
> /**
> @@ -983,6 +989,8 @@ static int qmp_ufs_power_on(struct phy *phy)
> int ret;
>
> qmp_ufs_serdes_init(qphy, &cfg->tables);
> + if (qphy->mode == PHY_MODE_UFS_HS_B)
> + qmp_ufs_serdes_init(qphy, &cfg->tables_hs_b);
>
> qmp_ufs_lanes_init(qphy, &cfg->tables);
>
> @@ -1070,6 +1078,15 @@ static int qmp_ufs_disable(struct phy *phy)
> return qmp_ufs_exit(phy);
> }
>
> +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + qphy->mode = mode;
> +
> + return 0;
> +}
> +
> static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> {
> struct qcom_qmp *qmp = dev_get_drvdata(dev);
> @@ -1105,6 +1122,7 @@ static int qmp_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
> static const struct phy_ops qcom_qmp_ufs_ops = {
> .power_on = qmp_ufs_enable,
> .power_off = qmp_ufs_disable,
> + .set_mode = qmp_ufs_set_mode,
> .owner = THIS_MODULE,
> };
>
> --
> 2.25.1
--
~Vinod
next prev parent reply other threads:[~2022-11-11 7:01 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 18:02 [PATCH v2 00/15] ufs: qcom: Add HS-G4 support Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 01/15] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tables struct Manivannan Sadhasivam
2022-11-11 6:57 ` Vinod Koul
2022-10-31 18:02 ` [PATCH v2 02/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Manivannan Sadhasivam
2022-11-11 7:01 ` Vinod Koul [this message]
2022-11-22 16:21 ` Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 03/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 04/15] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 05/15] phy: qcom-qmp-ufs: Move HS Rate B register setting to tables_hs_b Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 06/15] dt-bindings: ufs: Add "max-device-gear" property for UFS device Manivannan Sadhasivam
2022-11-02 16:29 ` Rob Herring
2022-11-02 19:09 ` Krzysztof Kozlowski
2022-11-03 12:28 ` Manivannan Sadhasivam
2022-11-03 15:23 ` Krzysztof Kozlowski
2022-11-22 16:22 ` Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 07/15] arm64: dts: qcom: qrb5165-rb5: Add max-device-gear property to UFS node Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 08/15] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 09/15] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Manivannan Sadhasivam
2022-10-31 20:01 ` Andrew Halaney
2022-10-31 18:02 ` [PATCH v2 10/15] scsi: ufs: ufs-qcom: Use bitfields where appropriate Manivannan Sadhasivam
2022-10-31 18:02 ` [PATCH v2 11/15] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Manivannan Sadhasivam
2022-10-31 20:05 ` Andrew Halaney
2022-10-31 18:02 ` [PATCH v2 12/15] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Manivannan Sadhasivam
2022-11-01 15:12 ` Andrew Halaney
2022-10-31 18:02 ` [PATCH v2 13/15] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Manivannan Sadhasivam
2022-10-31 20:31 ` Andrew Halaney
2022-10-31 18:02 ` [PATCH v2 14/15] scsi: ufs: ufs-qcom: Add support for finding HS gear on new UFS versions Manivannan Sadhasivam
2022-10-31 20:52 ` Andrew Halaney
2022-10-31 18:02 ` [PATCH v2 15/15] MAINTAINERS: Add myself as the maintainer for Qcom UFS driver Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y23zO68Bb5R0xLq/@matsya \
--to=vkoul@kernel.org \
--cc=ahalaney@redhat.com \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=jejb@linux.ibm.com \
--cc=konrad.dybcio@somainline.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux-scsi@vger.kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=martin.petersen@oracle.com \
--cc=quic_cang@quicinc.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).