From: Jason Gunthorpe <jgg@nvidia.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
x86@kernel.org, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Dave Jiang <dave.jiang@intel.com>,
Alex Williamson <alex.williamson@redhat.com>,
Kevin Tian <kevin.tian@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Logan Gunthorpe <logang@deltatee.com>,
Ashok Raj <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
Allen Hubbe <allenbh@gmail.com>,
"Ahmed S. Darwish" <darwi@linutronix.de>,
Reinette Chatre <reinette.chatre@intel.com>
Subject: Re: [patch 12/33] PCI/MSI: Add support for per device MSI[X] domains
Date: Wed, 16 Nov 2022 15:13:04 -0400 [thread overview]
Message-ID: <Y3U2QFeoDB17kbIC@nvidia.com> (raw)
In-Reply-To: <20221111135205.951710169@linutronix.de>
On Fri, Nov 11, 2022 at 02:58:30PM +0100, Thomas Gleixner wrote:
> +static struct msi_domain_template pci_msi_template = {
> + .chip = {
> + .name = "PCI-MSI",
> + .irq_mask = pci_mask_msi,
> + .irq_unmask = pci_unmask_msi,
> + .irq_write_msi_msg = pci_msi_domain_write_msg,
> + .flags = IRQCHIP_ONESHOT_SAFE,
> + },
> +
> + .ops = {
> + .set_desc = pci_device_domain_set_desc,
> + },
> +
> + .info = {
> + .flags = MSI_COMMON_FLAGS | MSI_FLAG_MULTI_PCI_MSI,
> + .bus_token = DOMAIN_BUS_PCI_DEVICE_MSI,
> + },
> +};
> +
> +static void pci_mask_msix(struct irq_data *data)
> +{
> + pci_msix_mask(irq_data_get_msi_desc(data));
> +}
> +
> +static void pci_unmask_msix(struct irq_data *data)
> +{
> + pci_msix_unmask(irq_data_get_msi_desc(data));
> +}
> +
> +static struct msi_domain_template pci_msix_template = {
> + .chip = {
> + .name = "PCI-MSIX",
> + .irq_mask = pci_mask_msix,
> + .irq_unmask = pci_unmask_msix,
> + .irq_write_msi_msg = pci_msi_domain_write_msg,
> + .flags = IRQCHIP_ONESHOT_SAFE,
> + },
> +
> + .ops = {
> + .set_desc = pci_device_domain_set_desc,
> + },
> +
> + .info = {
> + .flags = MSI_COMMON_FLAGS | MSI_FLAG_PCI_MSIX,
> + .bus_token = DOMAIN_BUS_PCI_DEVICE_MSIX,
> + },
> +};
I like this splitting alot, it makes the whole thing make so much more
sense.
> +bool pci_setup_msi_device_domain(struct pci_dev *pdev)
> +{
> + if (WARN_ON_ONCE(pdev->msix_enabled))
> + return false;
> +
> + if (pci_match_device_domain(pdev, DOMAIN_BUS_PCI_DEVICE_MSI))
> + return true;
> + if (pci_match_device_domain(pdev, DOMAIN_BUS_PCI_DEVICE_MSIX))
> + msi_remove_device_irq_domain(&pdev->dev, MSI_DEFAULT_DOMAIN);
> +
> + return pci_create_device_domain(pdev, &pci_msi_template, 1);
Hardwired to one 1? What about multi-msi?
Jason
next prev parent reply other threads:[~2022-11-16 19:13 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 13:58 [patch 00/33] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 3 implementation Thomas Gleixner
2022-11-11 13:58 ` [patch 01/33] genirq/msi: Rearrange MSI domain flags Thomas Gleixner
2022-11-16 18:41 ` Jason Gunthorpe
2022-11-11 13:58 ` [patch 02/33] genirq/msi: Provide struct msi_parent_ops Thomas Gleixner
2022-11-16 18:57 ` Jason Gunthorpe
2022-11-17 15:58 ` Thomas Gleixner
2022-11-18 13:52 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 03/33] genirq/msi: Provide data structs for per device domains Thomas Gleixner
2022-11-11 13:58 ` [patch 04/33] genirq/msi: Add size info to struct msi_domain_info Thomas Gleixner
2022-11-11 13:58 ` [patch 05/33] genirq/msi: Split msi_create_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains Thomas Gleixner
2022-11-11 13:58 ` [patch 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 08/33] genirq/msi: Provide msi_match_device_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 09/33] genirq/msi: Add range checking to msi_insert_desc() Thomas Gleixner
2022-11-11 13:58 ` [patch 10/33] PCI/MSI: Split __pci_write_msi_msg() Thomas Gleixner
2022-11-16 20:10 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] Thomas Gleixner
2022-11-11 13:58 ` [patch 12/33] PCI/MSI: Add support for per device MSI[X] domains Thomas Gleixner
2022-11-16 19:13 ` Jason Gunthorpe [this message]
2022-11-16 22:38 ` Thomas Gleixner
2022-11-17 0:22 ` Jason Gunthorpe
2022-11-17 8:45 ` Thomas Gleixner
2022-11-16 20:22 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 13/33] x86/apic/vector: Provide MSI parent domain Thomas Gleixner
2022-11-16 19:18 ` Jason Gunthorpe
2022-11-17 20:06 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() Thomas Gleixner
2022-11-16 20:13 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 15/33] iommu/vt-d: Switch to MSI parent domains Thomas Gleixner
2022-11-11 13:58 ` [patch 16/33] iommu/amd: Switch to MSI base domains Thomas Gleixner
2022-11-11 13:58 ` [patch 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 18/33] genirq/msi: Provide struct msi_map Thomas Gleixner
2022-11-11 13:58 ` [patch 19/33] genirq/msi: Provide msi_desc::msi_data Thomas Gleixner
2022-11-16 19:28 ` Jason Gunthorpe
2022-11-17 8:48 ` Thomas Gleixner
2022-11-17 13:33 ` Jason Gunthorpe
2022-11-18 22:08 ` Thomas Gleixner
2022-11-21 17:20 ` Jason Gunthorpe
2022-11-21 19:40 ` Thomas Gleixner
2022-11-22 1:52 ` Jason Gunthorpe
2022-11-22 20:49 ` Thomas Gleixner
2022-11-23 16:58 ` Jason Gunthorpe
2022-11-23 18:38 ` Thomas Gleixner
2022-12-01 12:24 ` Thomas Gleixner
2022-12-02 0:35 ` Jason Gunthorpe
2022-12-02 2:14 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() Thomas Gleixner
2022-11-11 13:58 ` [patch 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-16 19:36 ` Jason Gunthorpe
2022-11-17 9:40 ` Thomas Gleixner
2022-11-17 23:33 ` Reinette Chatre
2022-11-18 0:58 ` Thomas Gleixner
2022-11-18 9:15 ` Thomas Gleixner
2022-11-18 11:05 ` Thomas Gleixner
2022-11-18 18:18 ` Reinette Chatre
2022-11-18 22:31 ` Thomas Gleixner
2022-11-18 22:59 ` Reinette Chatre
2022-11-19 0:19 ` Reinette Chatre
2022-11-11 13:58 ` [patch 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-16 19:36 ` Jason Gunthorpe
2022-11-11 13:58 ` [patch 23/33] PCI/MSI: Split MSIX descriptor setup Thomas Gleixner
2022-11-16 20:13 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 24/33] PCI/MSI: Provide prepare_desc() MSI domain op Thomas Gleixner
2022-11-16 19:40 ` Jason Gunthorpe
2022-11-16 20:26 ` Bjorn Helgaas
2022-11-16 22:42 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X Thomas Gleixner
2022-11-16 20:19 ` Bjorn Helgaas
2022-11-16 22:43 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-11 13:58 ` [patch 27/33] genirq/msi: Provide constants for PCI/IMS support Thomas Gleixner
2022-11-16 19:54 ` Jason Gunthorpe
2022-11-17 9:46 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support Thomas Gleixner
2022-11-16 20:17 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() Thomas Gleixner
2022-11-16 20:14 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 30/33] x86/apic/msi: Enable PCI/IMS Thomas Gleixner
2022-11-11 13:59 ` [patch 31/33] iommu/vt-d: " Thomas Gleixner
2022-11-11 13:59 ` [patch 32/33] iommu/amd: " Thomas Gleixner
2022-11-11 13:59 ` [patch 33/33] irqchip: Add IDXD Interrupt Message Store driver Thomas Gleixner
2022-12-02 17:55 ` Reinette Chatre
2022-12-02 19:51 ` Thomas Gleixner
2022-12-02 21:16 ` Reinette Chatre
2022-12-05 15:20 ` Thomas Gleixner
2022-12-05 17:19 ` Reinette Chatre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y3U2QFeoDB17kbIC@nvidia.com \
--to=jgg@nvidia.com \
--cc=alex.williamson@redhat.com \
--cc=allenbh@gmail.com \
--cc=ashok.raj@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=darwi@linutronix.de \
--cc=dave.jiang@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=jdmason@kudzu.us \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=logang@deltatee.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=maz@kernel.org \
--cc=reinette.chatre@intel.com \
--cc=tglx@linutronix.de \
--cc=will@kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).