From: Thierry Reding <thierry.reding@gmail.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: jonathanh@nvidia.com, digetx@gmail.com, wsa@the-dreams.de,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-i2c@vger.kernel.org
Subject: Re: [PATCH v3] i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX FIFO
Date: Fri, 15 Jan 2021 16:57:36 +0100 [thread overview]
Message-ID: <YAG7cJb2y3Yym1xy@ulmo> (raw)
In-Reply-To: <1610478161-4877-2-git-send-email-skomatineni@nvidia.com>
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On Tue, Jan 12, 2021 at 11:02:41AM -0800, Sowjanya Komatineni wrote:
> VI I2C controller has known hardware bug where immediate multiple
> writes to TX_FIFO register gets stuck.
>
> Recommended software work around is to read I2C register after
> each write to TX_FIFO register to flush out the data.
>
> This patch implements this work around for VI I2C controller.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/i2c/busses/i2c-tegra.c | 22 +++++++++++++++++++++-
> 1 file changed, 21 insertions(+), 1 deletion(-)
Acked-by: Thierry Reding <treding@nvidia.com>
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next prev parent reply other threads:[~2021-01-15 15:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 19:02 [PATCH v3] Create i2c_writesl_vi() to use with VI I2C Sowjanya Komatineni
2021-01-12 19:02 ` [PATCH v3] i2c: tegra: Create i2c_writesl_vi() to use with VI I2C for filling TX FIFO Sowjanya Komatineni
2021-01-12 19:17 ` Dmitry Osipenko
2021-01-15 15:57 ` Thierry Reding [this message]
2021-01-17 11:24 ` Wolfram Sang
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