From: Thierry Reding <thierry.reding@gmail.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/5] clk: tegra: Ensure that PLLU configuration is applied properly
Date: Fri, 15 Jan 2021 16:13:25 +0100 [thread overview]
Message-ID: <YAGxFbvrHHcOCZIW@ulmo> (raw)
In-Reply-To: <20210112122724.1712-4-digetx@gmail.com>
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On Tue, Jan 12, 2021 at 03:27:22PM +0300, Dmitry Osipenko wrote:
> The PLLU (USB) consists of the PLL configuration itself and configuration
> of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114,
> where T114 immediately bails out if PLLU is enabled and T30 re-enables
> a potentially already enabled PLL (left after bootloader) and then fully
> reprograms it, which could be unsafe to do. The correct way should be to
> skip enabling of the PLL if it's already enabled and then apply
> configuration to the outputs. This patch doesn't fix any known problems,
> it's a minor improvement.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/clk/tegra/clk-pll.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
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next prev parent reply other threads:[~2021-01-15 15:14 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 12:27 [PATCH v2 0/5] Couple improvements for Tegra clk driver Dmitry Osipenko
2021-01-12 12:27 ` [PATCH v2 1/5] clk: tegra30: Use 300MHz for video decoder by default Dmitry Osipenko
2021-01-15 15:02 ` Thierry Reding
2021-01-12 12:27 ` [PATCH v2 2/5] clk: tegra: Fix refcounting of gate clocks Dmitry Osipenko
2021-01-15 15:17 ` Thierry Reding
2021-01-12 12:27 ` [PATCH v2 3/5] clk: tegra: Ensure that PLLU configuration is applied properly Dmitry Osipenko
2021-01-15 15:13 ` Thierry Reding [this message]
2021-01-12 12:27 ` [PATCH v2 4/5] clk: tegra: Halve SCLK rate on Tegra20 Dmitry Osipenko
2021-01-15 15:14 ` Thierry Reding
2021-01-12 12:27 ` [PATCH v2 5/5] MAINTAINERS: Hand Tegra clk driver to Jon and Thierry Dmitry Osipenko
2021-01-15 15:15 ` Thierry Reding
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