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* [PATCH v2 0/3] phy: Add Support for SM8350 UFS
@ 2021-02-04 16:58 Vinod Koul
  2021-02-04 16:58 ` [PATCH v2 1/3] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-04 16:58 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: linux-arm-msm, Bjorn Andersson, Andy Gross, Vinod Koul,
	Rob Herring, Asutosh Das, Jack Pham, devicetree, linux-kernel

This series adds support for UFS found in SM8350 SoC.

We add binding for UFS phy and new regsiters for QMPv5 followed by UFS phy
tables.

Vinod Koul (3):
  dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
  phy: qcom-qmp: Add UFS V5 registers found in SM8350
  phy: qcom-qmp: Add support for SM8350 UFS phy

 .../devicetree/bindings/phy/qcom,qmp-phy.yaml |   1 +
 drivers/phy/qualcomm/phy-qcom-qmp.c           | 127 ++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h           |  47 +++++++
 3 files changed, 175 insertions(+)

-- 
2.26.2


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH v2 1/3] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
  2021-02-04 16:58 [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
@ 2021-02-04 16:58 ` Vinod Koul
  2021-02-04 16:58 ` [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350 Vinod Koul
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-04 16:58 UTC (permalink / raw)
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	Rob Herring, Asutosh Das, Jack Pham, devicetree, linux-kernel

Add the compatible strings for the UFS PHY found on SM8350 SoC.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 62c4f2ba5b9f..bf804c12fa5f 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -38,6 +38,7 @@ properties:
       - qcom,sm8250-qmp-modem-pcie-phy
       - qcom,sm8250-qmp-usb3-phy
       - qcom,sm8250-qmp-usb3-uni-phy
+      - qcom,sm8350-qmp-ufs-phy
       - qcom,sm8350-qmp-usb3-phy
       - qcom,sm8350-qmp-usb3-uni-phy
       - qcom,sdx55-qmp-usb3-uni-phy
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350
  2021-02-04 16:58 [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
  2021-02-04 16:58 ` [PATCH v2 1/3] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
@ 2021-02-04 16:58 ` Vinod Koul
  2021-02-05 16:05   ` Bjorn Andersson
  2021-02-04 16:58 ` [PATCH v2 3/3] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
  2021-02-06  9:55 ` [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
  3 siblings, 1 reply; 6+ messages in thread
From: Vinod Koul @ 2021-02-04 16:58 UTC (permalink / raw)
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	Rob Herring, Asutosh Das, Jack Pham, devicetree, linux-kernel

Add the registers for UFS found in SM8350. The UFS phy used in SM8350
seems to have same offsets as V5 phy, although Documentation for that is
lacking.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp.h | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index dff7be5a1cc1..71ce3aa174ae 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -824,6 +824,32 @@
 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE			0xbc
 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST		0xe0
 
+/* Only for QMP V5 PHY - QSERDES COM registers */
+#define QSERDES_V5_COM_PLL_IVCO				0x058
+#define QSERDES_V5_COM_CP_CTRL_MODE0			0x074
+#define QSERDES_V5_COM_CP_CTRL_MODE1			0x078
+#define QSERDES_V5_COM_PLL_RCTRL_MODE0			0x07c
+#define QSERDES_V5_COM_PLL_RCTRL_MODE1			0x080
+#define QSERDES_V5_COM_PLL_CCTRL_MODE0			0x084
+#define QSERDES_V5_COM_PLL_CCTRL_MODE1			0x088
+#define QSERDES_V5_COM_SYSCLK_EN_SEL			0x094
+#define QSERDES_V5_COM_LOCK_CMP_EN			0x0a4
+#define QSERDES_V5_COM_LOCK_CMP1_MODE0			0x0ac
+#define QSERDES_V5_COM_LOCK_CMP2_MODE0			0x0b0
+#define QSERDES_V5_COM_LOCK_CMP1_MODE1			0x0b4
+#define QSERDES_V5_COM_DEC_START_MODE0			0x0bc
+#define QSERDES_V5_COM_LOCK_CMP2_MODE1			0x0b8
+#define QSERDES_V5_COM_DEC_START_MODE1			0x0c4
+#define QSERDES_V5_COM_VCO_TUNE_MAP			0x10c
+#define QSERDES_V5_COM_VCO_TUNE_INITVAL2		0x124
+#define QSERDES_V5_COM_HSCLK_SEL			0x158
+#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL		0x15c
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
+#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
+
 /* Only for QMP V5 PHY - TX registers */
 #define QSERDES_V5_TX_RES_CODE_LANE_TX			0x34
 #define QSERDES_V5_TX_RES_CODE_LANE_RX			0x38
@@ -837,6 +863,10 @@
 #define QSERDES_V5_TX_RCV_DETECT_LVL_2			0xa4
 #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN			0xc0
 #define QSERDES_V5_TX_PI_QEC_CTRL			0xe4
+#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178
+#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c
+#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180
+#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184
 
 /* Only for QMP V5 PHY - RX registers */
 #define QSERDES_V5_RX_UCDR_FO_GAIN			0x008
@@ -893,6 +923,23 @@
 #define QSERDES_V5_RX_DCC_CTRL1				0x1a8
 #define QSERDES_V5_RX_VTH_CODE				0x1b0
 
+/* Only for QMP V5 PHY - UFS PCS registers */
+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB	0x00c
+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB	0x010
+#define QPHY_V5_PCS_UFS_PLL_CNTL			0x02c
+#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x030
+#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x038
+#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY		0x074
+#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY		0x0b4
+#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL		0x124
+#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME		0x150
+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1			0x154
+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2			0x158
+#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND		0x160
+#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND			0x168
+#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1		0x1d8
+#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1		0x1e0
+
 /* Only for QMP V5 PHY - USB3 have different offsets than V4 */
 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1		0x300
 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x304
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v2 3/3] phy: qcom-qmp: Add support for SM8350 UFS phy
  2021-02-04 16:58 [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
  2021-02-04 16:58 ` [PATCH v2 1/3] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
  2021-02-04 16:58 ` [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350 Vinod Koul
@ 2021-02-04 16:58 ` Vinod Koul
  2021-02-06  9:55 ` [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
  3 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-04 16:58 UTC (permalink / raw)
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	Rob Herring, Asutosh Das, Jack Pham, devicetree, linux-kernel

Add the tables for init sequences for UFS QMP phy found in  SM8350 SoC.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 127 ++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index dbc12a19b702..4c6e0e86632b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1983,6 +1983,106 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 };
 
+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+
+	/* Rate B */
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
+	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
+	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
@@ -2971,6 +3071,30 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
 	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
 };
 
+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
+	.type			= PHY_TYPE_UFS,
+	.nlanes			= 2,
+
+	.serdes_tbl		= sm8350_ufsphy_serdes_tbl,
+	.serdes_tbl_num		= ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
+	.tx_tbl			= sm8350_ufsphy_tx_tbl,
+	.tx_tbl_num		= ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
+	.rx_tbl			= sm8350_ufsphy_rx_tbl,
+	.rx_tbl_num		= ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
+	.pcs_tbl		= sm8350_ufsphy_pcs_tbl,
+	.pcs_tbl_num		= ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
+	.clk_list		= sdm845_ufs_phy_clk_l,
+	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+	.vreg_list		= qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.regs			= sm8150_ufsphy_regs_layout,
+
+	.start_ctrl		= SERDES_START,
+	.pwrdn_ctrl		= SW_PWRDN,
+
+	.is_dual_lane_phy	= true,
+};
+
 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
 	.type			= PHY_TYPE_USB3,
 	.nlanes			= 1,
@@ -4379,6 +4503,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
 	}, {
 		.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
 		.data = &sm8250_qmp_gen3x2_pciephy_cfg,
+	}, {
+		.compatible = "qcom,sm8350-qmp-ufs-phy",
+		.data = &sm8350_ufsphy_cfg,
 	}, {
 		.compatible = "qcom,sm8350-qmp-usb3-phy",
 		.data = &sm8350_usb3phy_cfg,
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350
  2021-02-04 16:58 ` [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350 Vinod Koul
@ 2021-02-05 16:05   ` Bjorn Andersson
  0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2021-02-05 16:05 UTC (permalink / raw)
  To: Vinod Koul
  Cc: linux-arm-msm, Andy Gross, Rob Herring, Asutosh Das, Jack Pham,
	devicetree, linux-kernel

On Thu 04 Feb 10:58 CST 2021, Vinod Koul wrote:

> Add the registers for UFS found in SM8350. The UFS phy used in SM8350
> seems to have same offsets as V5 phy, although Documentation for that is
> lacking.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp.h | 47 +++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index dff7be5a1cc1..71ce3aa174ae 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -824,6 +824,32 @@
>  #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE			0xbc
>  #define QPHY_V4_PCS_PCIE_PRESET_P10_POST		0xe0
>  
> +/* Only for QMP V5 PHY - QSERDES COM registers */
> +#define QSERDES_V5_COM_PLL_IVCO				0x058
> +#define QSERDES_V5_COM_CP_CTRL_MODE0			0x074
> +#define QSERDES_V5_COM_CP_CTRL_MODE1			0x078
> +#define QSERDES_V5_COM_PLL_RCTRL_MODE0			0x07c
> +#define QSERDES_V5_COM_PLL_RCTRL_MODE1			0x080
> +#define QSERDES_V5_COM_PLL_CCTRL_MODE0			0x084
> +#define QSERDES_V5_COM_PLL_CCTRL_MODE1			0x088
> +#define QSERDES_V5_COM_SYSCLK_EN_SEL			0x094
> +#define QSERDES_V5_COM_LOCK_CMP_EN			0x0a4
> +#define QSERDES_V5_COM_LOCK_CMP1_MODE0			0x0ac
> +#define QSERDES_V5_COM_LOCK_CMP2_MODE0			0x0b0
> +#define QSERDES_V5_COM_LOCK_CMP1_MODE1			0x0b4
> +#define QSERDES_V5_COM_DEC_START_MODE0			0x0bc
> +#define QSERDES_V5_COM_LOCK_CMP2_MODE1			0x0b8
> +#define QSERDES_V5_COM_DEC_START_MODE1			0x0c4
> +#define QSERDES_V5_COM_VCO_TUNE_MAP			0x10c
> +#define QSERDES_V5_COM_VCO_TUNE_INITVAL2		0x124
> +#define QSERDES_V5_COM_HSCLK_SEL			0x158
> +#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL		0x15c
> +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
> +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
> +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
> +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> +
>  /* Only for QMP V5 PHY - TX registers */
>  #define QSERDES_V5_TX_RES_CODE_LANE_TX			0x34
>  #define QSERDES_V5_TX_RES_CODE_LANE_RX			0x38
> @@ -837,6 +863,10 @@
>  #define QSERDES_V5_TX_RCV_DETECT_LVL_2			0xa4
>  #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN			0xc0
>  #define QSERDES_V5_TX_PI_QEC_CTRL			0xe4
> +#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x178
> +#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x17c
> +#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x180
> +#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x184
>  
>  /* Only for QMP V5 PHY - RX registers */
>  #define QSERDES_V5_RX_UCDR_FO_GAIN			0x008
> @@ -893,6 +923,23 @@
>  #define QSERDES_V5_RX_DCC_CTRL1				0x1a8
>  #define QSERDES_V5_RX_VTH_CODE				0x1b0
>  
> +/* Only for QMP V5 PHY - UFS PCS registers */
> +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB	0x00c
> +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB	0x010
> +#define QPHY_V5_PCS_UFS_PLL_CNTL			0x02c
> +#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x030
> +#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x038
> +#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY		0x074
> +#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY		0x0b4
> +#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL		0x124
> +#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME		0x150
> +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1			0x154
> +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2			0x158
> +#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND		0x160
> +#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND			0x168
> +#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1		0x1d8
> +#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1		0x1e0
> +
>  /* Only for QMP V5 PHY - USB3 have different offsets than V4 */
>  #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1		0x300
>  #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x304
> -- 
> 2.26.2
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/3] phy: Add Support for SM8350 UFS
  2021-02-04 16:58 [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
                   ` (2 preceding siblings ...)
  2021-02-04 16:58 ` [PATCH v2 3/3] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
@ 2021-02-06  9:55 ` Vinod Koul
  3 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-06  9:55 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: linux-arm-msm, Bjorn Andersson, Andy Gross, Rob Herring,
	Asutosh Das, Jack Pham, devicetree, linux-kernel

On 04-02-21, 22:28, Vinod Koul wrote:
> This series adds support for UFS found in SM8350 SoC.
> 
> We add binding for UFS phy and new regsiters for QMPv5 followed by UFS phy
> tables.

Applied, thanks

-- 
~Vinod

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-02-06  9:56 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-04 16:58 [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul
2021-02-04 16:58 ` [PATCH v2 1/3] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
2021-02-04 16:58 ` [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350 Vinod Koul
2021-02-05 16:05   ` Bjorn Andersson
2021-02-04 16:58 ` [PATCH v2 3/3] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
2021-02-06  9:55 ` [PATCH v2 0/3] phy: Add Support for SM8350 UFS Vinod Koul

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