From: Sean Christopherson <seanjc@google.com>
To: Like Xu <like.xu@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Kan Liang <kan.liang@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
wei.w.wang@intel.com, Borislav Petkov <bp@alien8.de>,
kvm@vger.kernel.org, x86@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 8/9] KVM: x86: Expose Architectural LBR CPUID leaf
Date: Wed, 3 Mar 2021 10:01:43 -0800 [thread overview]
Message-ID: <YD/PB18qLqS7noKH@google.com> (raw)
In-Reply-To: <YD/IeTdqbK9kEDNp@google.com>
On Wed, Mar 03, 2021, Sean Christopherson wrote:
> On Wed, Mar 03, 2021, Like Xu wrote:
> > If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, then KVM supports Arch
> > LBRs and CPUID leaf 01CH indicates details of the Arch LBRs capabilities.
> > Currently, KVM only supports the current host LBR depth for guests,
> > which is also the maximum supported depth on the host.
> >
> > Signed-off-by: Like Xu <like.xu@linux.intel.com>
> > ---
> > arch/x86/kvm/cpuid.c | 25 ++++++++++++++++++++++++-
> > arch/x86/kvm/vmx/vmx.c | 2 ++
> > 2 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> > index b4247f821277..4473324fe7be 100644
> > --- a/arch/x86/kvm/cpuid.c
> > +++ b/arch/x86/kvm/cpuid.c
> > @@ -450,7 +450,7 @@ void kvm_set_cpu_caps(void)
> > F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
> > F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
> > F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
> > - F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16)
> > + F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | F(ARCH_LBR)
> > );
> >
> > /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
>
> ...
>
> > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> > index 2f307689a14b..034708a3df20 100644
> > --- a/arch/x86/kvm/vmx/vmx.c
> > +++ b/arch/x86/kvm/vmx/vmx.c
> > @@ -7258,6 +7258,8 @@ static __init void vmx_set_cpu_caps(void)
> > kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
> > if (vmx_pt_mode_is_host_guest())
> > kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
> > + if (cpu_has_vmx_arch_lbr())
> > + kvm_cpu_cap_check_and_set(X86_FEATURE_ARCH_LBR);
>
> Using kvm_cpu_cap_check_and_set(), which queries boot_cpu_has(), is only
> necessary if a feature is not exposed by default in kvm_set_cpu_caps(). That's
> why INTEL_PT uses it. ARCH_LBR on the other hand is set in the "enable by
> default" mask.
>
> That being said, it's probably a bad idea to advertise ARCH_LBR by default. In
> the unlikely case that AMD adds support for ARCH_LBR, enable-by-default means
> guest will be able to use ARCH_LBR on old KVMs that presumably would lack support
> for ARCH_LBR on SVM.
>
> TL;DR: omit F(ARCH_LBR) or replace it with "0 /* ARCH_LBR */".
Actually, I take that back. It'll require changing SVM, but due to the XSS
interaction it's probably cleaner to leaf F(ARCH_LBR) as is, and do:
if (!cpu_has_vmx_arch_lbr())
kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR);
and then unconditionally clear the cap for SVM. In a way, that's arguably
better documentation as it explicitly shows that SVM lacks supports.
More thoughts in the next patch...
next prev parent reply other threads:[~2021-03-03 20:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 13:57 [PATCH v3 0/9] KVM: x86/pmu: Guest Architectural LBR Enabling Like Xu
2021-03-03 13:57 ` [PATCH v3 1/9] perf/x86/intel: Fix a comment about guest LBR support Like Xu
2021-03-03 16:49 ` Sean Christopherson
2021-03-03 13:57 ` [PATCH v3 2/9] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Like Xu
2021-03-03 13:57 ` [PATCH v3 3/9] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR Like Xu
2021-03-03 13:57 ` [PATCH v3 4/9] perf/x86/lbr: Use GFP_ATOMIC for cpuc->lbr_xsave memory allocation Like Xu
2021-03-03 13:57 ` [PATCH v3 5/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR Like Xu
2021-03-03 16:58 ` Sean Christopherson
2021-03-04 2:30 ` Xu, Like
2021-03-04 16:12 ` Sean Christopherson
2021-03-05 2:33 ` Xu, Like
2021-03-03 13:57 ` [PATCH v3 6/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL " Like Xu
2021-03-03 17:19 ` Sean Christopherson
2021-03-04 2:58 ` Xu, Like
2021-03-04 16:25 ` Sean Christopherson
2021-03-03 13:57 ` [PATCH v3 7/9] KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field Like Xu
2021-03-03 17:26 ` Sean Christopherson
2021-03-04 3:02 ` Xu, Like
2021-03-04 17:23 ` Sean Christopherson
2021-03-05 6:35 ` Xu, Like
2021-03-03 13:57 ` [PATCH v3 8/9] KVM: x86: Expose Architectural LBR CPUID leaf Like Xu
2021-03-03 17:34 ` Sean Christopherson
2021-03-03 18:01 ` Sean Christopherson [this message]
2021-03-03 13:57 ` [PATCH v3 9/9] KVM: x86: Add XSAVE Support for Architectural LBRs Like Xu
2021-03-03 18:03 ` Sean Christopherson
2021-03-04 3:43 ` Like Xu
2021-03-04 16:31 ` Sean Christopherson
2021-03-05 2:57 ` Xu, Like
2021-03-03 13:57 ` [kvm-unit-tests PATCH] x86: Update guest LBR tests for Architectural LBR Like Xu
2021-03-03 18:05 ` Sean Christopherson
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