[PATCH RESEND 1/2] perf/x86: Skip checking MSR for MSR 0x0

* [PATCH RESEND 1/2] perf/x86: Skip checking MSR for MSR 0x0
@ 2021-04-21  2:18 Like Xu
  2021-04-21  2:18 ` [PATCH RESEND 2/2] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region Like Xu
  2021-04-21 15:30 ` [PATCH RESEND 1/2] perf/x86: Skip checking MSR for MSR 0x0 Sean Christopherson
  0 siblings, 2 replies; 8+ messages in thread
From: Like Xu @ 2021-04-21  2:18 UTC (permalink / raw)
  To: Peter Zijlstra, Kan Liang
  Cc: Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, Thomas Gleixner,
	Borislav Petkov, x86, linux-kernel, Like Xu

The Architecture LBR does not have MSR_LBR_TOS (0x000001c9).
When ARCH_LBR we don't set lbr_tos, the failure from the
check_msr() against MSR 0x000 will make x86_pmu.lbr_nr = 0,
thereby preventing the initialization of the guest LBR.

Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/intel/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5272f349dca2..5036496caa60 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4751,10 +4751,10 @@ static bool check_msr(unsigned long msr, u64 mask)
 	u64 val_old, val_new, val_tmp;
 
 	/*
-	 * Disable the check for real HW, so we don't
+	 * Disable the check for real HW or non-sense msr, so we don't
 	 * mess with potentionaly enabled registers:
 	 */
-	if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
+	if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) || !msr)
 		return true;
 
 	/*
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 8+ messages in thread