From: Sean Christopherson <seanjc@google.com>
To: "Liu, Jing2" <jing2.liu@linux.intel.com>
Cc: pbonzini@redhat.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org, jing2.liu@intel.com
Subject: Re: [PATCH RFC 7/7] kvm: x86: AMX XCR0 support for guest
Date: Wed, 26 May 2021 14:54:01 +0000 [thread overview]
Message-ID: <YK5hCUoPo4OJzeU0@google.com> (raw)
In-Reply-To: <43eb3317-4101-0786-57f4-f35e7ec094eb@linux.intel.com>
On Wed, May 26, 2021, Liu, Jing2 wrote:
>
> On 5/25/2021 5:53 AM, Sean Christopherson wrote:
> > On Sun, Feb 07, 2021, Jing Liu wrote:
> > > Two XCR0 bits are defined for AMX to support XSAVE mechanism.
> > > Bit 17 is for tilecfg and bit 18 is for tiledata.
> > This fails to explain why they must be set in tandem.
> The spec says, "executing the XSETBV instruction causes a general-protection
> fault (#GP) if ECX=0 and EAX[17] ≠ EAX[18] (XTILECFG and XTILEDATA must be
> enabled together). This implies that the value of XCR0[17:18] is always
> either 00b or 11b."
>
> I can add more to changelog if this is reasonable.
Ya, please do. It doesn't have to be the full thing verbatim (but that's ok, too),
but the requirement does need to be called out.
> > Out of curisoity, assuming they do indeed need to be set/cleared as a
> > pair, what's the point of having two separate bits?
>
> What I can see is to separate different states and mirror by XFD which can
> set bits separately.
Ah, that would make sense. Thanks!
prev parent reply other threads:[~2021-05-26 14:54 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-07 15:42 [PATCH RFC 0/7] Introduce support for guest AMX feature Jing Liu
2021-02-07 15:42 ` [PATCH RFC 1/7] kvm: x86: Expose XFD CPUID to guest Jing Liu
2021-05-24 21:34 ` Sean Christopherson
2021-06-07 3:27 ` Liu, Jing2
2021-02-07 15:42 ` [PATCH RFC 2/7] kvm: x86: Introduce XFD MSRs as passthrough " Jing Liu
2021-05-24 21:43 ` Sean Christopherson
2021-05-24 21:57 ` Jim Mattson
2021-06-02 3:12 ` Liu, Jing2
2021-06-23 17:50 ` Dave Hansen
2021-06-28 2:00 ` Liu, Jing2
2021-06-29 17:58 ` Dave Hansen
2021-07-06 7:33 ` Liu, Jing2
2021-02-07 15:42 ` [PATCH RFC 3/7] kvm: x86: XSAVE state and XFD MSRs context switch Jing Liu
2021-02-07 11:49 ` Borislav Petkov
2021-02-08 3:35 ` Liu, Jing2
2021-02-08 10:25 ` Paolo Bonzini
2021-02-08 17:31 ` Sean Christopherson
2021-02-08 17:45 ` Paolo Bonzini
2021-02-08 18:04 ` Sean Christopherson
2021-02-08 18:12 ` Paolo Bonzini
2021-02-08 18:55 ` Konrad Rzeszutek Wilk
2021-02-22 8:51 ` Liu, Jing2
2021-02-22 8:36 ` Liu, Jing2
2021-02-07 15:42 ` [PATCH RFC 4/7] kvm: x86: Add new ioctls for XSAVE extension Jing Liu
2021-05-24 21:50 ` Sean Christopherson
2021-05-26 6:09 ` Liu, Jing2
2021-05-26 14:43 ` Sean Christopherson
2021-06-01 10:24 ` Liu, Jing2
2021-06-07 5:23 ` Liu, Jing2
2021-05-24 22:06 ` Jim Mattson
2021-05-26 6:11 ` Liu, Jing2
2021-02-07 15:42 ` [PATCH RFC 5/7] kvm: x86: Revise CPUID.D.1.EBX for alignment rule Jing Liu
2021-05-24 21:28 ` Sean Christopherson
2021-06-03 4:45 ` Liu, Jing2
2021-02-07 15:42 ` [PATCH RFC 6/7] kvm: x86: Add AMX_TILE, AMX_INT8 and AMX_BF16 support Jing Liu
2021-02-07 15:42 ` [PATCH RFC 7/7] kvm: x86: AMX XCR0 support for guest Jing Liu
2021-05-24 21:53 ` Sean Christopherson
2021-05-26 7:54 ` Liu, Jing2
2021-05-26 14:54 ` Sean Christopherson [this message]
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