From: Rob Herring <robh@kernel.org>
To: Bharat Bhushan <bbhushan2@marvell.com>
Cc: will@kernel.org, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, sgoutham@marvell.com
Subject: Re: [PATCH 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor
Date: Thu, 29 Jul 2021 17:29:46 -0600 [thread overview]
Message-ID: <YQM56mlxM19UDu93@robh.at.kernel.org> (raw)
In-Reply-To: <20210726091027.798-2-bbhushan2@marvell.com>
On Mon, Jul 26, 2021 at 02:40:24PM +0530, Bharat Bhushan wrote:
> Add binding documentation for the Marvell CN10k DDR
> performance monitor unit.
>
> Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
> ---
> .../bindings/perf/marvell-cn10k-ddr.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.txt
Bindings are in DT schema format now.
Rob
next prev parent reply other threads:[~2021-07-29 23:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-26 9:10 [PATCH 0/4] cn10k DDR Performance monitor support Bharat Bhushan
2021-07-26 9:10 ` [PATCH 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor Bharat Bhushan
2021-07-29 23:29 ` Rob Herring [this message]
2021-08-03 11:38 ` [EXT] " Bharat Bhushan
2021-07-26 9:10 ` [PATCH 2/4] perf/marvell: ADD cn10k DDR PMU basic support Bharat Bhushan
2021-07-26 9:10 ` [PATCH 3/4] perf/marvell: cn10k DDR perfmon event overflow handling Bharat Bhushan
2021-07-26 9:10 ` [PATCH 4/4] perf/marvell: cn10k DDR perf event core ownership Bharat Bhushan
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