From: "Luck, Tony" <tony.luck@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Peter Zijlstra <peterz@infradead.org>,
Andy Lutomirski <luto@kernel.org>,
Dave Hansen <dave.hansen@intel.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
Joerg Roedel <joro@8bytes.org>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Dave Jiang <dave.jiang@intel.com>,
Jacob Jun Pan <jacob.jun.pan@intel.com>,
Ashok Raj <ashok.raj@intel.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
iommu@lists.linux-foundation.org, x86 <x86@kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting
Date: Thu, 23 Sep 2021 09:40:50 -0700 [thread overview]
Message-ID: <YUyuEjlrcOeCp4qQ@agluck-desk2.amr.corp.intel.com> (raw)
In-Reply-To: <87y27nfjel.ffs@tglx>
On Thu, Sep 23, 2021 at 04:36:50PM +0200, Thomas Gleixner wrote:
> On Mon, Sep 20 2021 at 19:23, Fenghua Yu wrote:
> >
> > +#ifdef CONFIG_INTEL_IOMMU_SVM
> > +void pasid_put(struct task_struct *tsk, struct mm_struct *mm);
> > +#else
> > +static inline void pasid_put(struct task_struct *tsk, struct mm_struct *mm) { }
> > +#endif
>
> This code is again defining that PASID is entirely restricted to
> INTEL. It's true, that no other vendor supports this, but PASID is
> a non-vendor specific concept.
>
> Sticking this into INTEL code means that any other PASID implementation
> has to rip it out again from INTEL code and make it a run time property.
>
> The refcounting issue should be the same for all PASID mechanisms which
> attach PASID to a mm. What's INTEL specific about that?
>
> So can we pretty please do that correct right away?
It's a bit messy (surprise).
There are two reasons to hold a refcount on a PASID
1) The process has done a bind on a device that uses PASIDs
This one isn't dependent on Intel.
2) A task within a process is using ENQCMD (and thus holds
a reference on the PASID because IA32_PASID MSR for this
task has the PASID value loaded with the enable bit set).
This is (currently) Intel specific (until others
implement an ENQCMD-like feature to allow apps to
access PASID enabled devices without going through
the OS).
Perhaps some better function naming might help? E.g. have
a task_pasid_put() function that handles the process exit
case separatley from the device unbind case.
void task_pasid_put(void)
{
if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
return;
if (current->has_valid_pasid) {
mutex_lock(&pasid_mutex);
iommu_sva_free_pasid(mm);
mutex_unlock(&pasid_mutex);
}
}
-Tony
next prev parent reply other threads:[~2021-09-23 16:40 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 19:23 [PATCH 0/8] Re-enable ENQCMD and PASID MSR Fenghua Yu
2021-09-20 19:23 ` [PATCH 1/8] iommu/vt-d: Clean up unused PASID updating functions Fenghua Yu
2021-09-29 7:34 ` Lu Baolu
2021-09-30 0:40 ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 2/8] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu
2021-09-20 19:23 ` [PATCH 3/8] sched: Define and initialize a flag to identify valid PASID in the task Fenghua Yu
2021-09-20 19:23 ` [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Fenghua Yu
2021-09-22 21:07 ` Peter Zijlstra
2021-09-22 21:11 ` Peter Zijlstra
2021-09-22 21:26 ` Luck, Tony
2021-09-23 7:03 ` Peter Zijlstra
2021-09-22 21:33 ` Dave Hansen
2021-09-23 7:05 ` Peter Zijlstra
2021-09-22 21:36 ` Fenghua Yu
2021-09-22 23:39 ` Fenghua Yu
2021-09-23 17:14 ` Luck, Tony
2021-09-24 13:37 ` Peter Zijlstra
2021-09-24 15:39 ` Luck, Tony
2021-09-29 9:00 ` Peter Zijlstra
2021-09-23 11:31 ` Thomas Gleixner
2021-09-23 23:17 ` Andy Lutomirski
2021-09-24 2:56 ` Fenghua Yu
2021-09-24 5:12 ` Andy Lutomirski
2021-09-27 21:02 ` Luck, Tony
2021-09-27 23:51 ` Dave Hansen
2021-09-28 18:50 ` Luck, Tony
2021-09-28 19:19 ` Dave Hansen
2021-09-28 20:28 ` Luck, Tony
2021-09-28 20:55 ` Dave Hansen
2021-09-28 23:10 ` Luck, Tony
2021-09-28 23:50 ` Fenghua Yu
2021-09-29 0:08 ` Luck, Tony
2021-09-29 0:26 ` Yu, Fenghua
2021-09-29 1:06 ` Luck, Tony
2021-09-29 1:16 ` Fenghua Yu
2021-09-29 2:11 ` Luck, Tony
2021-09-29 1:56 ` Yu, Fenghua
2021-09-29 2:15 ` Luck, Tony
2021-09-29 16:58 ` Andy Lutomirski
2021-09-29 17:07 ` Luck, Tony
2021-09-29 17:48 ` Andy Lutomirski
2021-09-20 19:23 ` [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Fenghua Yu
2021-09-23 5:43 ` Lu Baolu
2021-09-30 0:44 ` Fenghua Yu
2021-09-23 14:36 ` Thomas Gleixner
2021-09-23 16:40 ` Luck, Tony [this message]
2021-09-23 17:48 ` Thomas Gleixner
2021-09-24 13:18 ` Thomas Gleixner
2021-09-24 16:12 ` Luck, Tony
2021-09-24 23:03 ` Andy Lutomirski
2021-09-24 23:11 ` Luck, Tony
2021-09-29 9:54 ` Peter Zijlstra
2021-09-29 12:28 ` Thomas Gleixner
2021-09-29 16:51 ` Luck, Tony
2021-09-29 17:07 ` Fenghua Yu
2021-09-29 16:59 ` Andy Lutomirski
2021-09-29 17:15 ` Thomas Gleixner
2021-09-29 17:41 ` Luck, Tony
2021-09-29 17:46 ` Andy Lutomirski
2021-09-29 18:07 ` Fenghua Yu
2021-09-29 18:31 ` Luck, Tony
2021-09-29 20:07 ` Thomas Gleixner
2021-09-24 16:12 ` Fenghua Yu
2021-09-25 23:13 ` Thomas Gleixner
2021-09-28 16:36 ` Fenghua Yu
2021-09-23 23:09 ` Andy Lutomirski
2021-09-23 23:22 ` Luck, Tony
2021-09-24 5:17 ` Andy Lutomirski
2021-09-20 19:23 ` [PATCH 6/8] x86/cpufeatures: Re-enable ENQCMD Fenghua Yu
2021-09-20 19:23 ` [PATCH 7/8] tools/objtool: Check for use of the ENQCMD instruction in the kernel Fenghua Yu
2021-09-22 21:03 ` Peter Zijlstra
2021-09-22 23:44 ` Fenghua Yu
2021-09-23 7:17 ` Peter Zijlstra
2021-09-23 15:26 ` Fenghua Yu
2021-09-24 0:55 ` Josh Poimboeuf
2021-09-24 0:57 ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 8/8] docs: x86: Change documentation for SVA (Shared Virtual Addressing) Fenghua Yu
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