* [PATCH 1/3] perf vendor events: For the Neoverse N2
@ 2021-12-03 12:35 Andrew Kilroy
2021-12-03 12:35 ` [PATCH 2/3] perf vendor events: Fix whitespace Andrew Kilroy
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Andrew Kilroy @ 2021-12-03 12:35 UTC (permalink / raw)
To: linux-kernel, linux-perf-users, acme
Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
linux-arm-kernel
Updates the common and microarch json file to add counters
available in the Neoverse N2 chip, but should also apply to other ArmV8
and ArmV9 cpus. Specified in ArmV8 architecture reference manual
https://developer.arm.com/documentation/ddi0487/gb/?lang=en
Some of the counters added to armv8-common-and-microarch.json are
specified in the ArmV9 architecture reference manual supplement
(issue A.a):
https://developer.arm.com/documentation/ddi0608/aa
The additional ArmV9 counters are
TRB_WRAP
TRCEXTOUT0
TRCEXTOUT1
TRCEXTOUT2
TRCEXTOUT3
CTI_TRIGOUT4
CTI_TRIGOUT5
CTI_TRIGOUT6
CTI_TRIGOUT7
This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
perf list to output the counter names in categories.
A subsequent patch renames armv8-common-and-microarch.json and
armv8-recommended.json to reflect that counters for armv9 are being
added.
Counters on the Neoverse N2 are stated in its reference manual:
https://developer.arm.com/documentation/102099/0000
Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
.../arch/arm64/arm/neoverse-n2/branch.json | 8 +
.../arch/arm64/arm/neoverse-n2/bus.json | 20 ++
.../arch/arm64/arm/neoverse-n2/cache.json | 155 ++++++++++++++
.../arch/arm64/arm/neoverse-n2/exception.json | 47 +++++
.../arm64/arm/neoverse-n2/instruction.json | 143 +++++++++++++
.../arch/arm64/arm/neoverse-n2/memory.json | 38 ++++
.../arch/arm64/arm/neoverse-n2/other.json | 5 +
.../arch/arm64/arm/neoverse-n2/pipeline.json | 23 ++
.../arch/arm64/arm/neoverse-n2/spe.json | 14 ++
.../arch/arm64/arm/neoverse-n2/trace.json | 29 +++
.../arm64/armv8-common-and-microarch.json | 198 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
12 files changed, 681 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/other.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/spe.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/trace.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json
new file mode 100644
index 000000000000..79f2016c53b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/branch.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/bus.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/bus.json
new file mode 100644
index 000000000000..579c1c993d17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/bus.json
@@ -0,0 +1,20 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "CNT_CYCLES"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/cache.json
new file mode 100644
index 000000000000..0141f749bff3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/cache.json
@@ -0,0 +1,155 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB"
+ },
+ {
+ "ArchStdEvent": "DTLB_WALK"
+ },
+ {
+ "ArchStdEvent": "ITLB_WALK"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE_LMISS"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_LMISS_RD"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_LMISS_RD"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/exception.json
new file mode 100644
index 000000000000..344a2d552ad5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/exception.json
@@ -0,0 +1,47 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "MEMORY_ERROR"
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF"
+ },
+ {
+ "ArchStdEvent": "EXC_SVC"
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ },
+ {
+ "ArchStdEvent": "EXC_SMC"
+ },
+ {
+ "ArchStdEvent": "EXC_HVC"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json
new file mode 100644
index 000000000000..e57cd55937c6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json
@@ -0,0 +1,143 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_RETIRED"
+ },
+ {
+ "ArchStdEvent": "OP_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC"
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_HP_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_SP_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_EMPTY_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_FULL_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_LDFF_SPEC"
+ },
+ {
+ "ArchStdEvent": "SVE_LDFF_FAULT_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_SCALE_OPS_SPEC"
+ },
+ {
+ "ArchStdEvent": "FP_FIXED_OPS_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT8_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT16_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT32_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SVE_INT64_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/memory.json
new file mode 100644
index 000000000000..e522113aeb96
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/memory.json
@@ -0,0 +1,38 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDST_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "LD_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "ST_ALIGN_LAT"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/other.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/other.json
new file mode 100644
index 000000000000..20d8365756c5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/other.json
@@ -0,0 +1,5 @@
+[
+ {
+ "ArchStdEvent": "REMOTE_ACCESS"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/pipeline.json
new file mode 100644
index 000000000000..f9fae15f7555
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/pipeline.json
@@ -0,0 +1,23 @@
+[
+ {
+ "ArchStdEvent": "STALL_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_BACKEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_SLOT"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND_MEM"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/spe.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/spe.json
new file mode 100644
index 000000000000..20f2165c85fe
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/spe.json
@@ -0,0 +1,14 @@
+[
+ {
+ "ArchStdEvent": "SAMPLE_POP"
+ },
+ {
+ "ArchStdEvent": "SAMPLE_FEED"
+ },
+ {
+ "ArchStdEvent": "SAMPLE_FILTRATE"
+ },
+ {
+ "ArchStdEvent": "SAMPLE_COLLISION"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/trace.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/trace.json
new file mode 100644
index 000000000000..3116135c59e2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/trace.json
@@ -0,0 +1,29 @@
+[
+ {
+ "ArchStdEvent": "TRB_WRAP"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT0"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT1"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT2"
+ },
+ {
+ "ArchStdEvent": "TRCEXTOUT3"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT4"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT5"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT6"
+ },
+ {
+ "ArchStdEvent": "CTI_TRIGOUT7"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
index 423767510aff..80d7a70829a0 100644
--- a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
+++ b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
@@ -299,6 +299,30 @@
"EventName": "STALL_SLOT",
"BriefDescription": "No operation sent for execution on a slot"
},
+ {
+ "PublicDescription": "Sample Population",
+ "EventCode": "0x4000",
+ "EventName": "SAMPLE_POP",
+ "BriefDescription": "Sample Population"
+ },
+ {
+ "PublicDescription": "Sample Taken",
+ "EventCode": "0x4001",
+ "EventName": "SAMPLE_FEED",
+ "BriefDescription": "Sample Taken"
+ },
+ {
+ "PublicDescription": "Sample Taken and not removed by filtering",
+ "EventCode": "0x4002",
+ "EventName": "SAMPLE_FILTRATE",
+ "BriefDescription": "Sample Taken and not removed by filtering"
+ },
+ {
+ "PublicDescription": "Sample collided with previous sample",
+ "EventCode": "0x4003",
+ "EventName": "SAMPLE_COLLISION",
+ "BriefDescription": "Sample collided with previous sample"
+ },
{
"PublicDescription": "Constant frequency cycles. The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0.",
"EventCode": "0x4004",
@@ -329,6 +353,96 @@
"EventName": "L3D_CACHE_LMISS_RD",
"BriefDescription": "Level 3 data cache long-latency read miss"
},
+ {
+ "PublicDescription": "Trace buffer current write pointer wrapped",
+ "EventCode": "0x400C",
+ "EventName": "TRB_WRAP",
+ "BriefDescription": "Trace buffer current write pointer wrapped"
+ },
+ {
+ "PublicDescription": "PE Trace Unit external output 0",
+ "EventCode": "0x4010",
+ "EventName": "TRCEXTOUT0",
+ "BriefDescription": "PE Trace Unit external output 0"
+ },
+ {
+ "PublicDescription": "PE Trace Unit external output 1",
+ "EventCode": "0x4011",
+ "EventName": "TRCEXTOUT1",
+ "BriefDescription": "PE Trace Unit external output 1"
+ },
+ {
+ "PublicDescription": "PE Trace Unit external output 2",
+ "EventCode": "0x4012",
+ "EventName": "TRCEXTOUT2",
+ "BriefDescription": "PE Trace Unit external output 2"
+ },
+ {
+ "PublicDescription": "PE Trace Unit external output 3",
+ "EventCode": "0x4013",
+ "EventName": "TRCEXTOUT3",
+ "BriefDescription": "PE Trace Unit external output 3"
+ },
+ {
+ "PublicDescription": "Cross-trigger Interface output trigger 4",
+ "EventCode": "0x4018",
+ "EventName": "CTI_TRIGOUT4",
+ "BriefDescription": "Cross-trigger Interface output trigger 4"
+ },
+ {
+ "PublicDescription": "Cross-trigger Interface output trigger 5 ",
+ "EventCode": "0x4019",
+ "EventName": "CTI_TRIGOUT5",
+ "BriefDescription": "Cross-trigger Interface output trigger 5 "
+ },
+ {
+ "PublicDescription": "Cross-trigger Interface output trigger 6",
+ "EventCode": "0x401A",
+ "EventName": "CTI_TRIGOUT6",
+ "BriefDescription": "Cross-trigger Interface output trigger 6"
+ },
+ {
+ "PublicDescription": "Cross-trigger Interface output trigger 7",
+ "EventCode": "0x401B",
+ "EventName": "CTI_TRIGOUT7",
+ "BriefDescription": "Cross-trigger Interface output trigger 7"
+ },
+ {
+ "PublicDescription": "Access with additional latency from alignment",
+ "EventCode": "0x4020",
+ "EventName": "LDST_ALIGN_LAT",
+ "BriefDescription": "Access with additional latency from alignment"
+ },
+ {
+ "PublicDescription": "Load with additional latency from alignment",
+ "EventCode": "0x4021",
+ "EventName": "LD_ALIGN_LAT",
+ "BriefDescription": "Load with additional latency from alignment"
+ },
+ {
+ "PublicDescription": "Store with additional latency from alignment",
+ "EventCode": "0x4022",
+ "EventName": "ST_ALIGN_LAT",
+ "BriefDescription": "Store with additional latency from alignment"
+ },
+ {
+ "PublicDescription": "Checked data memory access",
+ "EventCode": "0x4024",
+ "EventName": "MEM_ACCESS_CHECKED",
+ "BriefDescription": "Checked data memory access"
+ },
+ {
+ "PublicDescription": "Checked data memory access, read",
+ "EventCode": "0x4025",
+ "EventName": "MEM_ACCESS_CHECKED_RD",
+ "BriefDescription": "Checked data memory access, read"
+ },
+ {
+ "PublicDescription": "Checked data memory access, write",
+ "EventCode": "0x4026",
+ "EventName": "MEM_ACCESS_CHECKED_WR",
+ "BriefDescription": "Checked data memory access, write"
+ },
{
"PublicDescription": "SIMD Instruction architecturally executed.",
"EventCode": "0x8000",
@@ -341,6 +455,18 @@
"EventName": "SVE_INST_RETIRED",
"BriefDescription": "Instruction architecturally executed, SVE."
},
+ {
+ "PublicDescription": "ASE operations speculatively executed",
+ "EventCode": "0x8005",
+ "EventName": "ASE_INST_SPEC",
+ "BriefDescription": "ASE operations speculatively executed"
+ },
+ {
+ "PublicDescription": "SVE operations speculatively executed",
+ "EventCode": "0x8006",
+ "EventName": "SVE_INST_SPEC",
+ "BriefDescription": "SVE operations speculatively executed"
+ },
{
"PublicDescription": "Microarchitectural operation, Operations speculatively executed.",
"EventCode": "0x8008",
@@ -359,6 +485,24 @@
"EventName": "FP_SPEC",
"BriefDescription": "Floating-point Operations speculatively executed."
},
+ {
+ "PublicDescription": "Floating-point half-precision operations speculatively executed",
+ "EventCode": "0x8014",
+ "EventName": "FP_HP_SPEC",
+ "BriefDescription": "Floating-point half-precision operations speculatively executed"
+ },
+ {
+ "PublicDescription": "Floating-point single-precision operations speculatively executed",
+ "EventCode": "0x8018",
+ "EventName": "FP_SP_SPEC",
+ "BriefDescription": "Floating-point single-precision operations speculatively executed"
+ },
+ {
+ "PublicDescription": "Floating-point double-precision operations speculatively executed",
+ "EventCode": "0x801C",
+ "EventName": "FP_DP_SPEC",
+ "BriefDescription": "Floating-point double-precision operations speculatively executed"
+ },
{
"PublicDescription": "Floating-point FMA Operations speculatively executed.",
"EventCode": "0x8028",
@@ -389,6 +533,30 @@
"EventName": "SVE_PRED_SPEC",
"BriefDescription": "SVE predicated Operations speculatively executed."
},
+ {
+ "PublicDescription": "SVE predicated operations with no active predicates speculatively executed",
+ "EventCode": "0x8075",
+ "EventName": "SVE_PRED_EMPTY_SPEC",
+ "BriefDescription": "SVE predicated operations with no active predicates speculatively executed"
+ },
+ {
+ "PublicDescription": "SVE predicated operations speculatively executed with all active predicates",
+ "EventCode": "0x8076",
+ "EventName": "SVE_PRED_FULL_SPEC",
+ "BriefDescription": "SVE predicated operations speculatively executed with all active predicates"
+ },
+ {
+ "PublicDescription": "SVE predicated operations speculatively executed with partially active predicates",
+ "EventCode": "0x8077",
+ "EventName": "SVE_PRED_PARTIAL_SPEC",
+ "BriefDescription": "SVE predicated operations speculatively executed with partially active predicates"
+ },
+ {
+ "PublicDescription": "SVE predicated operations with empty or partially active predicates",
+ "EventCode": "0x8079",
+ "EventName": "SVE_PRED_NOT_FULL_SPEC",
+ "BriefDescription": "SVE predicated operations with empty or partially active predicates"
+ },
{
"PublicDescription": "SVE MOVPRFX Operations speculatively executed.",
"EventCode": "0x807C",
@@ -497,6 +665,12 @@
"EventName": "SVE_LDFF_SPEC",
"BriefDescription": "SVE First-fault load Operations speculatively executed."
},
+ {
+ "PublicDescription": "SVE first-fault load operations speculatively executed which set FFR bit to 0",
+ "EventCode": "0x80BD",
+ "EventName": "SVE_LDFF_FAULT_SPEC",
+ "BriefDescription": "SVE first-fault load operations speculatively executed which set FFR bit to 0"
+ },
{
"PublicDescription": "Scalable floating-point element Operations speculatively executed.",
"EventCode": "0x80C0",
@@ -544,5 +718,29 @@
"EventCode": "0x80C7",
"EventName": "FP_DP_FIXED_OPS_SPEC",
"BriefDescription": "Non-scalable double-precision floating-point element Operations speculatively executed."
+ },
+ {
+ "PublicDescription": "Advanced SIMD and SVE 8-bit integer operations speculatively executed",
+ "EventCode": "0x80E3",
+ "EventName": "ASE_SVE_INT8_SPEC",
+ "BriefDescription": "Advanced SIMD and SVE 8-bit integer operations speculatively executed"
+ },
+ {
+ "PublicDescription": "Advanced SIMD and SVE 16-bit integer operations speculatively executed",
+ "EventCode": "0x80E7",
+ "EventName": "ASE_SVE_INT16_SPEC",
+ "BriefDescription": "Advanced SIMD and SVE 16-bit integer operations speculatively executed"
+ },
+ {
+ "PublicDescription": "Advanced SIMD and SVE 32-bit integer operations speculatively executed",
+ "EventCode": "0x80EB",
+ "EventName": "ASE_SVE_INT32_SPEC",
+ "BriefDescription": "Advanced SIMD and SVE 32-bit integer operations speculatively executed"
+ },
+ {
+ "PublicDescription": "Advanced SIMD and SVE 64-bit integer operations speculatively executed",
+ "EventCode": "0x80EF",
+ "EventName": "ASE_SVE_INT64_SPEC",
+ "BriefDescription": "Advanced SIMD and SVE 64-bit integer operations speculatively executed"
}
]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 31d8b57ca9bb..b899db48c12a 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -19,6 +19,7 @@
0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
0x00000000410fd400,v1,arm/neoverse-v1,core
+0x00000000410fd490,v1,arm/neoverse-n2,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000460f0010,v1,fujitsu/a64fx,core
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] perf vendor events: Fix whitespace
2021-12-03 12:35 [PATCH 1/3] perf vendor events: For the Neoverse N2 Andrew Kilroy
@ 2021-12-03 12:35 ` Andrew Kilroy
2021-12-07 9:36 ` John Garry
2021-12-03 12:35 ` [PATCH 3/3] perf vendor events: Rename arm64 arch std event files Andrew Kilroy
2021-12-07 9:57 ` [PATCH 1/3] perf vendor events: For the Neoverse N2 John Garry
2 siblings, 1 reply; 9+ messages in thread
From: Andrew Kilroy @ 2021-12-03 12:35 UTC (permalink / raw)
To: linux-kernel, linux-perf-users, acme
Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
linux-arm-kernel
Correct indentation to 4 spaces, same as the other json files.
Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
.../arch/arm64/armv8-recommended.json | 202 +++++++++---------
1 file changed, 101 insertions(+), 101 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
index d0a19866563d..210afa856091 100644
--- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
+++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
@@ -148,305 +148,305 @@
"EventCode": "0x60",
"EventName": "BUS_ACCESS_RD",
"BriefDescription": "Bus access read"
- },
- {
+ },
+ {
"PublicDescription": "Bus access write",
"EventCode": "0x61",
"EventName": "BUS_ACCESS_WR",
"BriefDescription": "Bus access write"
- },
- {
+ },
+ {
"PublicDescription": "Bus access, Normal, Cacheable, Shareable",
"EventCode": "0x62",
"EventName": "BUS_ACCESS_SHARED",
"BriefDescription": "Bus access, Normal, Cacheable, Shareable"
- },
- {
+ },
+ {
"PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
"EventCode": "0x63",
"EventName": "BUS_ACCESS_NOT_SHARED",
"BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
- },
- {
+ },
+ {
"PublicDescription": "Bus access, Normal",
"EventCode": "0x64",
"EventName": "BUS_ACCESS_NORMAL",
"BriefDescription": "Bus access, Normal"
- },
- {
+ },
+ {
"PublicDescription": "Bus access, peripheral",
"EventCode": "0x65",
"EventName": "BUS_ACCESS_PERIPH",
"BriefDescription": "Bus access, peripheral"
- },
- {
+ },
+ {
"PublicDescription": "Data memory access, read",
"EventCode": "0x66",
"EventName": "MEM_ACCESS_RD",
"BriefDescription": "Data memory access, read"
- },
- {
+ },
+ {
"PublicDescription": "Data memory access, write",
"EventCode": "0x67",
"EventName": "MEM_ACCESS_WR",
"BriefDescription": "Data memory access, write"
- },
- {
+ },
+ {
"PublicDescription": "Unaligned access, read",
"EventCode": "0x68",
"EventName": "UNALIGNED_LD_SPEC",
"BriefDescription": "Unaligned access, read"
- },
- {
+ },
+ {
"PublicDescription": "Unaligned access, write",
"EventCode": "0x69",
"EventName": "UNALIGNED_ST_SPEC",
"BriefDescription": "Unaligned access, write"
- },
- {
+ },
+ {
"PublicDescription": "Unaligned access",
"EventCode": "0x6a",
"EventName": "UNALIGNED_LDST_SPEC",
"BriefDescription": "Unaligned access"
- },
- {
+ },
+ {
"PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX",
"EventCode": "0x6c",
"EventName": "LDREX_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX"
- },
- {
+ },
+ {
"PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass",
"EventCode": "0x6d",
"EventName": "STREX_PASS_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass"
- },
- {
+ },
+ {
"PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail",
"EventCode": "0x6e",
"EventName": "STREX_FAIL_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail"
- },
- {
+ },
+ {
"PublicDescription": "Exclusive operation speculatively executed, STREX or STX",
"EventCode": "0x6f",
"EventName": "STREX_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX or STX"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, load",
"EventCode": "0x70",
"EventName": "LD_SPEC",
"BriefDescription": "Operation speculatively executed, load"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, store",
"EventCode": "0x71",
"EventName": "ST_SPEC",
"BriefDescription": "Operation speculatively executed, store"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, load or store",
"EventCode": "0x72",
"EventName": "LDST_SPEC",
"BriefDescription": "Operation speculatively executed, load or store"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, integer data processing",
"EventCode": "0x73",
"EventName": "DP_SPEC",
"BriefDescription": "Operation speculatively executed, integer data processing"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, Advanced SIMD instruction",
"EventCode": "0x74",
"EventName": "ASE_SPEC",
"BriefDescription": "Operation speculatively executed, Advanced SIMD instruction"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, floating-point instruction",
"EventCode": "0x75",
"EventName": "VFP_SPEC",
"BriefDescription": "Operation speculatively executed, floating-point instruction"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, software change of the PC",
"EventCode": "0x76",
"EventName": "PC_WRITE_SPEC",
"BriefDescription": "Operation speculatively executed, software change of the PC"
- },
- {
+ },
+ {
"PublicDescription": "Operation speculatively executed, Cryptographic instruction",
"EventCode": "0x77",
"EventName": "CRYPTO_SPEC",
"BriefDescription": "Operation speculatively executed, Cryptographic instruction"
- },
- {
+ },
+ {
"PublicDescription": "Branch speculatively executed, immediate branch",
"EventCode": "0x78",
"EventName": "BR_IMMED_SPEC",
"BriefDescription": "Branch speculatively executed, immediate branch"
- },
- {
+ },
+ {
"PublicDescription": "Branch speculatively executed, procedure return",
"EventCode": "0x79",
"EventName": "BR_RETURN_SPEC",
"BriefDescription": "Branch speculatively executed, procedure return"
- },
- {
+ },
+ {
"PublicDescription": "Branch speculatively executed, indirect branch",
"EventCode": "0x7a",
"EventName": "BR_INDIRECT_SPEC",
"BriefDescription": "Branch speculatively executed, indirect branch"
- },
- {
+ },
+ {
"PublicDescription": "Barrier speculatively executed, ISB",
"EventCode": "0x7c",
"EventName": "ISB_SPEC",
"BriefDescription": "Barrier speculatively executed, ISB"
- },
- {
+ },
+ {
"PublicDescription": "Barrier speculatively executed, DSB",
"EventCode": "0x7d",
"EventName": "DSB_SPEC",
"BriefDescription": "Barrier speculatively executed, DSB"
- },
- {
+ },
+ {
"PublicDescription": "Barrier speculatively executed, DMB",
"EventCode": "0x7e",
"EventName": "DMB_SPEC",
"BriefDescription": "Barrier speculatively executed, DMB"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Other synchronous",
"EventCode": "0x81",
"EventName": "EXC_UNDEF",
"BriefDescription": "Exception taken, Other synchronous"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Supervisor Call",
"EventCode": "0x82",
"EventName": "EXC_SVC",
"BriefDescription": "Exception taken, Supervisor Call"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Instruction Abort",
"EventCode": "0x83",
"EventName": "EXC_PABORT",
"BriefDescription": "Exception taken, Instruction Abort"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Data Abort and SError",
"EventCode": "0x84",
"EventName": "EXC_DABORT",
"BriefDescription": "Exception taken, Data Abort and SError"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, IRQ",
"EventCode": "0x86",
"EventName": "EXC_IRQ",
"BriefDescription": "Exception taken, IRQ"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, FIQ",
"EventCode": "0x87",
"EventName": "EXC_FIQ",
"BriefDescription": "Exception taken, FIQ"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Secure Monitor Call",
"EventCode": "0x88",
"EventName": "EXC_SMC",
"BriefDescription": "Exception taken, Secure Monitor Call"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Hypervisor Call",
"EventCode": "0x8a",
"EventName": "EXC_HVC",
"BriefDescription": "Exception taken, Hypervisor Call"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Instruction Abort not taken locally",
"EventCode": "0x8b",
"EventName": "EXC_TRAP_PABORT",
"BriefDescription": "Exception taken, Instruction Abort not taken locally"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Data Abort or SError not taken locally",
"EventCode": "0x8c",
"EventName": "EXC_TRAP_DABORT",
"BriefDescription": "Exception taken, Data Abort or SError not taken locally"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, Other traps not taken locally",
"EventCode": "0x8d",
"EventName": "EXC_TRAP_OTHER",
"BriefDescription": "Exception taken, Other traps not taken locally"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, IRQ not taken locally",
"EventCode": "0x8e",
"EventName": "EXC_TRAP_IRQ",
"BriefDescription": "Exception taken, IRQ not taken locally"
- },
- {
+ },
+ {
"PublicDescription": "Exception taken, FIQ not taken locally",
"EventCode": "0x8f",
"EventName": "EXC_TRAP_FIQ",
"BriefDescription": "Exception taken, FIQ not taken locally"
- },
- {
+ },
+ {
"PublicDescription": "Release consistency operation speculatively executed, Load-Acquire",
"EventCode": "0x90",
"EventName": "RC_LD_SPEC",
"BriefDescription": "Release consistency operation speculatively executed, Load-Acquire"
- },
- {
+ },
+ {
"PublicDescription": "Release consistency operation speculatively executed, Store-Release",
"EventCode": "0x91",
"EventName": "RC_ST_SPEC",
"BriefDescription": "Release consistency operation speculatively executed, Store-Release"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache access, read",
"EventCode": "0xa0",
"EventName": "L3D_CACHE_RD",
"BriefDescription": "Attributable Level 3 data or unified cache access, read"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache access, write",
"EventCode": "0xa1",
"EventName": "L3D_CACHE_WR",
"BriefDescription": "Attributable Level 3 data or unified cache access, write"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache refill, read",
"EventCode": "0xa2",
"EventName": "L3D_CACHE_REFILL_RD",
"BriefDescription": "Attributable Level 3 data or unified cache refill, read"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache refill, write",
"EventCode": "0xa3",
"EventName": "L3D_CACHE_REFILL_WR",
"BriefDescription": "Attributable Level 3 data or unified cache refill, write"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim",
"EventCode": "0xa6",
"EventName": "L3D_CACHE_WB_VICTIM",
"BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean",
"EventCode": "0xa7",
"EventName": "L3D_CACHE_WB_CLEAN",
"BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean"
- },
- {
+ },
+ {
"PublicDescription": "Attributable Level 3 data or unified cache access, invalidate",
"EventCode": "0xa8",
"EventName": "L3D_CACHE_INVAL",
"BriefDescription": "Attributable Level 3 data or unified cache access, invalidate"
- }
+ }
]
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] perf vendor events: Rename arm64 arch std event files
2021-12-03 12:35 [PATCH 1/3] perf vendor events: For the Neoverse N2 Andrew Kilroy
2021-12-03 12:35 ` [PATCH 2/3] perf vendor events: Fix whitespace Andrew Kilroy
@ 2021-12-03 12:35 ` Andrew Kilroy
2021-12-07 9:57 ` [PATCH 1/3] perf vendor events: For the Neoverse N2 John Garry
2 siblings, 0 replies; 9+ messages in thread
From: Andrew Kilroy @ 2021-12-03 12:35 UTC (permalink / raw)
To: linux-kernel, linux-perf-users, acme
Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
linux-arm-kernel
The previous commit adds pmu events into the files
armv8-common-and-microarch.json
armv8-recommended.json
that are actually specified in an armv9 reference supplement, not armv8.
As such, naming the files with the armv8 prefix seems artificial.
This patch renames the files to reflect that these two files are for
arch std events regardless of whether they are defined in armv8 or
armv9.
Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
...{armv8-common-and-microarch.json => common-and-microarch.json} | 0
.../arch/arm64/{armv8-recommended.json => recommended.json} | 0
2 files changed, 0 insertions(+), 0 deletions(-)
rename tools/perf/pmu-events/arch/arm64/{armv8-common-and-microarch.json => common-and-microarch.json} (100%)
rename tools/perf/pmu-events/arch/arm64/{armv8-recommended.json => recommended.json} (100%)
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
rename to tools/perf/pmu-events/arch/arm64/common-and-microarch.json
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/recommended.json
similarity index 100%
rename from tools/perf/pmu-events/arch/arm64/armv8-recommended.json
rename to tools/perf/pmu-events/arch/arm64/recommended.json
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] perf vendor events: Fix whitespace
2021-12-03 12:35 ` [PATCH 2/3] perf vendor events: Fix whitespace Andrew Kilroy
@ 2021-12-07 9:36 ` John Garry
2021-12-07 14:47 ` Arnaldo Carvalho de Melo
0 siblings, 1 reply; 9+ messages in thread
From: John Garry @ 2021-12-07 9:36 UTC (permalink / raw)
To: Andrew Kilroy, linux-kernel, linux-perf-users, acme
Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel
On 03/12/2021 12:35, Andrew Kilroy wrote:
> Correct indentation to 4 spaces, same as the other json files.
>
> Signed-off-by: Andrew Kilroy<andrew.kilroy@arm.com>
Reviewed-by: John Garry <john.garry@huawei.com>
As an aside, maybe we should improve the parser to find these inconsistencies in formatting.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] perf vendor events: For the Neoverse N2
2021-12-03 12:35 [PATCH 1/3] perf vendor events: For the Neoverse N2 Andrew Kilroy
2021-12-03 12:35 ` [PATCH 2/3] perf vendor events: Fix whitespace Andrew Kilroy
2021-12-03 12:35 ` [PATCH 3/3] perf vendor events: Rename arm64 arch std event files Andrew Kilroy
@ 2021-12-07 9:57 ` John Garry
2021-12-07 12:13 ` Andrew Kilroy
2 siblings, 1 reply; 9+ messages in thread
From: John Garry @ 2021-12-07 9:57 UTC (permalink / raw)
To: Andrew Kilroy, linux-kernel, linux-perf-users, acme
Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel
On 03/12/2021 12:35, Andrew Kilroy wrote:
> Updates the common and microarch json file to add counters
> available in the Neoverse N2 chip, but should also apply to other ArmV8
> and ArmV9 cpus. Specified in ArmV8 architecture reference manual
>
> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>
> Some of the counters added to armv8-common-and-microarch.json are
> specified in the ArmV9 architecture reference manual supplement
> (issue A.a):
>
> https://developer.arm.com/documentation/ddi0608/aa
>
> The additional ArmV9 counters are
>
> TRB_WRAP
> TRCEXTOUT0
> TRCEXTOUT1
> TRCEXTOUT2
> TRCEXTOUT3
> CTI_TRIGOUT4
> CTI_TRIGOUT5
> CTI_TRIGOUT6
> CTI_TRIGOUT7
>
> This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
> perf list to output the counter names in categories.
>
> A subsequent patch renames armv8-common-and-microarch.json and
> armv8-recommended.json to reflect that counters for armv9 are being
> added.
This commentary should be in a cover letter. Please do that.
And did you consider just adding a armv9-common-and-microarch.json and
armv9-recommended.json instead of adding to and renaming the v8 version?
I know that it creates scattered definitions, but we already have that in
dividing the common and the recommended JSONs.
Thanks,
John
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] perf vendor events: For the Neoverse N2
2021-12-07 9:57 ` [PATCH 1/3] perf vendor events: For the Neoverse N2 John Garry
@ 2021-12-07 12:13 ` Andrew Kilroy
2021-12-07 14:49 ` Arnaldo Carvalho de Melo
2021-12-08 12:30 ` John Garry
0 siblings, 2 replies; 9+ messages in thread
From: Andrew Kilroy @ 2021-12-07 12:13 UTC (permalink / raw)
To: John Garry, linux-kernel, linux-perf-users, acme
Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel
On 07/12/2021 09:57, John Garry wrote:
> On 03/12/2021 12:35, Andrew Kilroy wrote:
>> Updates the common and microarch json file to add counters
>> available in the Neoverse N2 chip, but should also apply to other ArmV8
>> and ArmV9 cpus. Specified in ArmV8 architecture reference manual
>>
>> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>>
>> Some of the counters added to armv8-common-and-microarch.json are
>> specified in the ArmV9 architecture reference manual supplement
>> (issue A.a):
>>
>> https://developer.arm.com/documentation/ddi0608/aa
>>
>> The additional ArmV9 counters are
>>
>> TRB_WRAP
>> TRCEXTOUT0
>> TRCEXTOUT1
>> TRCEXTOUT2
>> TRCEXTOUT3
>> CTI_TRIGOUT4
>> CTI_TRIGOUT5
>> CTI_TRIGOUT6
>> CTI_TRIGOUT7
>>
>> This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
>> perf list to output the counter names in categories.
>>
>> A subsequent patch renames armv8-common-and-microarch.json and
>> armv8-recommended.json to reflect that counters for armv9 are being
>> added.
>
> This commentary should be in a cover letter. Please do that.
>
> And did you consider just adding a armv9-common-and-microarch.json and
> armv9-recommended.json instead of adding to and renaming the v8 version?
> I know that it creates scattered definitions, but we already have that in
> dividing the common and the recommended JSONs.
>
I considered it, but I wasn't sure what was preferable. I thought I'd
get some feedback. Do you consider the separation important? Any
particular reason?
> Thanks,
> John
Andrew
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] perf vendor events: Fix whitespace
2021-12-07 9:36 ` John Garry
@ 2021-12-07 14:47 ` Arnaldo Carvalho de Melo
0 siblings, 0 replies; 9+ messages in thread
From: Arnaldo Carvalho de Melo @ 2021-12-07 14:47 UTC (permalink / raw)
To: John Garry
Cc: Andrew Kilroy, linux-kernel, linux-perf-users, Will Deacon,
Mathieu Poirier, Leo Yan, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, linux-arm-kernel
Em Tue, Dec 07, 2021 at 09:36:40AM +0000, John Garry escreveu:
> On 03/12/2021 12:35, Andrew Kilroy wrote:
> > Correct indentation to 4 spaces, same as the other json files.
> >
> > Signed-off-by: Andrew Kilroy<andrew.kilroy@arm.com>
>
> Reviewed-by: John Garry <john.garry@huawei.com>
>
> As an aside, maybe we should improve the parser to find these inconsistencies in formatting.
Thanks, applied.
- Arnaldo
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] perf vendor events: For the Neoverse N2
2021-12-07 12:13 ` Andrew Kilroy
@ 2021-12-07 14:49 ` Arnaldo Carvalho de Melo
2021-12-08 12:30 ` John Garry
1 sibling, 0 replies; 9+ messages in thread
From: Arnaldo Carvalho de Melo @ 2021-12-07 14:49 UTC (permalink / raw)
To: Andrew Kilroy
Cc: John Garry, linux-kernel, linux-perf-users, Will Deacon,
Mathieu Poirier, Leo Yan, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, linux-arm-kernel
Em Tue, Dec 07, 2021 at 12:13:16PM +0000, Andrew Kilroy escreveu:
>
>
> On 07/12/2021 09:57, John Garry wrote:
> > On 03/12/2021 12:35, Andrew Kilroy wrote:
> > > Updates the common and microarch json file to add counters
> > > available in the Neoverse N2 chip, but should also apply to other ArmV8
> > > and ArmV9 cpus. Specified in ArmV8 architecture reference manual
> > >
> > > https://developer.arm.com/documentation/ddi0487/gb/?lang=en
> > >
> > > Some of the counters added to armv8-common-and-microarch.json are
> > > specified in the ArmV9 architecture reference manual supplement
> > > (issue A.a):
> > >
> > > https://developer.arm.com/documentation/ddi0608/aa
> > >
> > > The additional ArmV9 counters are
> > >
> > > TRB_WRAP
> > > TRCEXTOUT0
> > > TRCEXTOUT1
> > > TRCEXTOUT2
> > > TRCEXTOUT3
> > > CTI_TRIGOUT4
> > > CTI_TRIGOUT5
> > > CTI_TRIGOUT6
> > > CTI_TRIGOUT7
> > >
> > > This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
> > > perf list to output the counter names in categories.
> > >
> > > A subsequent patch renames armv8-common-and-microarch.json and
> > > armv8-recommended.json to reflect that counters for armv9 are being
> > > added.
> >
> > This commentary should be in a cover letter. Please do that.
> >
> > And did you consider just adding a armv9-common-and-microarch.json and
> > armv9-recommended.json instead of adding to and renaming the v8 version?
> > I know that it creates scattered definitions, but we already have that in
> > dividing the common and the recommended JSONs.
> >
>
> I considered it, but I wasn't sure what was preferable. I thought I'd get
> some feedback. Do you consider the separation important? Any particular
> reason?
Applied the second patch, waiting for a conclusion to this discussion to
pick the other two patches.
- Arnaldo
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] perf vendor events: For the Neoverse N2
2021-12-07 12:13 ` Andrew Kilroy
2021-12-07 14:49 ` Arnaldo Carvalho de Melo
@ 2021-12-08 12:30 ` John Garry
1 sibling, 0 replies; 9+ messages in thread
From: John Garry @ 2021-12-08 12:30 UTC (permalink / raw)
To: Andrew Kilroy, linux-kernel, linux-perf-users, acme
Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel
On 07/12/2021 12:13, Andrew Kilroy wrote:
> On 07/12/2021 09:57, John Garry wrote:
>> On 03/12/2021 12:35, Andrew Kilroy wrote:
>>> Updates the common and microarch json file to add counters
>>> available in the Neoverse N2 chip, but should also apply to other ArmV8
>>> and ArmV9 cpus. Specified in ArmV8 architecture reference manual
>>>
>>> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>>>
>>> Some of the counters added to armv8-common-and-microarch.json are
>>> specified in the ArmV9 architecture reference manual supplement
>>> (issue A.a):
>>>
>>> https://developer.arm.com/documentation/ddi0608/aa
>>>
>>> The additional ArmV9 counters are
>>>
>>> TRB_WRAP
>>> TRCEXTOUT0
>>> TRCEXTOUT1
>>> TRCEXTOUT2
>>> TRCEXTOUT3
>>> CTI_TRIGOUT4
>>> CTI_TRIGOUT5
>>> CTI_TRIGOUT6
>>> CTI_TRIGOUT7
>>>
>>> This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
>>> perf list to output the counter names in categories.
>>>
>>> A subsequent patch renames armv8-common-and-microarch.json and
>>> armv8-recommended.json to reflect that counters for armv9 are being
>>> added.
>>
>> This commentary should be in a cover letter. Please do that.
>>
>> And did you consider just adding a armv9-common-and-microarch.json and
>> armv9-recommended.json instead of adding to and renaming the v8 version?
>> I know that it creates scattered definitions, but we already have that in
>> dividing the common and the recommended JSONs.
>>
>
> I considered it, but I wasn't sure what was preferable. I thought I'd
> get some feedback. Do you consider the separation important? Any
> particular reason?
At the moment I don't think that it's a big issue. I just thought it
better to keep a structured and distinct file organisation by having
separate files. v9 stuff is quite new, so we can wait for other input here.
Thanks,
John
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-12-08 12:31 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-03 12:35 [PATCH 1/3] perf vendor events: For the Neoverse N2 Andrew Kilroy
2021-12-03 12:35 ` [PATCH 2/3] perf vendor events: Fix whitespace Andrew Kilroy
2021-12-07 9:36 ` John Garry
2021-12-07 14:47 ` Arnaldo Carvalho de Melo
2021-12-03 12:35 ` [PATCH 3/3] perf vendor events: Rename arm64 arch std event files Andrew Kilroy
2021-12-07 9:57 ` [PATCH 1/3] perf vendor events: For the Neoverse N2 John Garry
2021-12-07 12:13 ` Andrew Kilroy
2021-12-07 14:49 ` Arnaldo Carvalho de Melo
2021-12-08 12:30 ` John Garry
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).