* [PATCH 01/11] dt-bindings: qoriq-clock: add missing compatible for lx2160a
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-29 20:50 ` Rob Herring
2021-11-10 22:21 ` [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: " Li Yang
` (9 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Li Yang
The compatbile string is already in use, fix the binding to include it.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index f7d48f23da44..10119d9ef4b1 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -44,6 +44,7 @@ Required properties:
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
+ * "fsl,lx2160a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 01/11] dt-bindings: qoriq-clock: add missing compatible for lx2160a
2021-11-10 22:21 ` [PATCH 01/11] dt-bindings: qoriq-clock: add missing compatible for lx2160a Li Yang
@ 2021-11-29 20:50 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2021-11-29 20:50 UTC (permalink / raw)
To: Li Yang
Cc: Shawn Guo, Michael Turquette, Stephen Boyd, devicetree,
linux-kernel, linux-arm-kernel
On Wed, Nov 10, 2021 at 04:21:50PM -0600, Li Yang wrote:
> The compatbile string is already in use, fix the binding to include it.
typo
>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
> 1 file changed, 1 insertion(+)
With that fixed,
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
2021-11-10 22:21 ` [PATCH 01/11] dt-bindings: qoriq-clock: add missing compatible for lx2160a Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-29 20:53 ` Rob Herring
2021-11-10 22:21 ` [PATCH 03/11] arm64: dts: lx2160a: fix scl-gpios property name Li Yang
` (8 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Li Yang
The compatbile string is already in use, fix the chip list in binding to
include it.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
index b5cb374dc47d..10a91cc8b997 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
@@ -8,7 +8,7 @@ Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
- reg : should contain base address and length of DCFG memory-mapped registers
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
2021-11-10 22:21 ` [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: " Li Yang
@ 2021-11-29 20:53 ` Rob Herring
2021-11-29 23:28 ` Leo Li
0 siblings, 1 reply; 16+ messages in thread
From: Rob Herring @ 2021-11-29 20:53 UTC (permalink / raw)
To: Li Yang
Cc: Shawn Guo, Michael Turquette, Stephen Boyd, devicetree,
linux-kernel, linux-arm-kernel
On Wed, Nov 10, 2021 at 04:21:51PM -0600, Li Yang wrote:
> The compatbile string is already in use, fix the chip list in binding to
same typo.
> include it.
>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> .../devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
2021-11-29 20:53 ` Rob Herring
@ 2021-11-29 23:28 ` Leo Li
0 siblings, 0 replies; 16+ messages in thread
From: Leo Li @ 2021-11-29 23:28 UTC (permalink / raw)
To: Rob Herring
Cc: Shawn Guo, Michael Turquette, Stephen Boyd, devicetree,
linux-kernel, linux-arm-kernel
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Monday, November 29, 2021 2:54 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: add missing
> compatible for lx2160a
>
> On Wed, Nov 10, 2021 at 04:21:51PM -0600, Li Yang wrote:
> > The compatbile string is already in use, fix the chip list in binding to
>
> same typo.
>
> > include it.
> >
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > ---
> > .../devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Acked-by: Rob Herring <robh@kernel.org>
Thanks. Both typo fixed and applied to fsl-soc tree.
Regards,
Leo
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 03/11] arm64: dts: lx2160a: fix scl-gpios property name
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
2021-11-10 22:21 ` [PATCH 01/11] dt-bindings: qoriq-clock: add missing compatible for lx2160a Li Yang
2021-11-10 22:21 ` [PATCH 02/11] dt-bindings: fsl,layerscape-dcfg: " Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:21 ` [PATCH 04/11] arm64: dts: lx2160a-rdb: Add Inphi PHY node Li Yang
` (7 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Zhang Ying-22455, Li Yang
From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Fix the typo in the property name.
Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c4b1a59ba424..51c4f61007cd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -719,7 +719,7 @@ i2c0: i2c@2000000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
- scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -768,7 +768,7 @@ i2c4: i2c@2040000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
- scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 04/11] arm64: dts: lx2160a-rdb: Add Inphi PHY node
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (2 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 03/11] arm64: dts: lx2160a: fix scl-gpios property name Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:21 ` [PATCH 05/11] arm64: dts: lx2160a: add optee-tz node Li Yang
` (6 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Ioana Radulescu,
Vicentiu Galanopulo, Florin Chiculita, Li Yang
From: Ioana Radulescu <ruxandra.radulescu@nxp.com>
DPMAC5 and DPMAC6 are connected to 25G Inphi PHY
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 028ff8074b9d..0ec41838e54e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -49,6 +49,14 @@ &dpmac4 {
managed = "in-band-status";
};
+&dpmac5 {
+ phy-handle = <&inphi_phy>;
+};
+
+&dpmac6 {
+ phy-handle = <&inphi_phy>;
+};
+
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
@@ -109,6 +117,15 @@ can-transceiver {
};
};
+&emdio2 {
+ status = "okay";
+
+ inphi_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0210.7440";
+ reg = <0x0>;
+ };
+};
+
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/11] arm64: dts: lx2160a: add optee-tz node
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (3 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 04/11] arm64: dts: lx2160a-rdb: Add Inphi PHY node Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:21 ` [PATCH 06/11] arm64: dts: lx2160a-qds: enable sata nodes Li Yang
` (5 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Pankaj Gupta, Li Yang
From: Pankaj Gupta <pankaj.gupta@nxp.com>
Disabled by default in SoC dtsi and enables in board dts files.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
3 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index d858d9c8b583..8354af0b31e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -156,6 +156,10 @@ rtc@51 {
};
};
+&optee {
+ status = "okay";
+};
+
&sata0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 0ec41838e54e..0c44b3cbef77 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -219,6 +219,10 @@ rtc@51 {
};
};
+&optee {
+ status = "okay";
+};
+
&pcs_mdio3 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 51c4f61007cd..5d1f84f4de29 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1751,4 +1751,12 @@ dpmac18: ethernet@12 {
};
};
};
+
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ status = "disabled";
+ };
+ };
};
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/11] arm64: dts: lx2160a-qds: enable sata nodes
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (4 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 05/11] arm64: dts: lx2160a: add optee-tz node Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 23:48 ` Leo Li
2021-11-10 22:21 ` [PATCH 07/11] arm64: dts: lx2160aqds: Add mdio mux nodes Li Yang
` (4 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Peng Ma, Li Yang
From: Peng Ma <peng.ma@nxp.com>
Enables sata support on lx2160a-qds.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 8354af0b31e3..480520152e1a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -191,3 +191,19 @@ &usb0 {
&usb1 {
status = "okay";
};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* RE: [PATCH 06/11] arm64: dts: lx2160a-qds: enable sata nodes
2021-11-10 22:21 ` [PATCH 06/11] arm64: dts: lx2160a-qds: enable sata nodes Li Yang
@ 2021-11-10 23:48 ` Leo Li
0 siblings, 0 replies; 16+ messages in thread
From: Leo Li @ 2021-11-10 23:48 UTC (permalink / raw)
To: Leo Li, Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel
> -----Original Message-----
> From: Li Yang <leoyang.li@nxp.com>
> Sent: Wednesday, November 10, 2021 4:22 PM
> To: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> <robh+dt@kernel.org>; Michael Turquette <mturquette@baylibre.com>;
> Stephen Boyd <sboyd@kernel.org>
> Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Peng Ma <peng.ma@nxp.com>; Leo Li
> <leoyang.li@nxp.com>
> Subject: [PATCH 06/11] arm64: dts: lx2160a-qds: enable sata nodes
>
> From: Peng Ma <peng.ma@nxp.com>
>
> Enables sata support on lx2160a-qds.
>
> Signed-off-by: Peng Ma <peng.ma@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
Please skip this patch. Looks like an updated one has been merged.
> ---
> .../arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> index 8354af0b31e3..480520152e1a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> @@ -191,3 +191,19 @@ &usb0 {
> &usb1 {
> status = "okay";
> };
> +
> +&sata0 {
> + status = "okay";
> +};
> +
> +&sata1 {
> + status = "okay";
> +};
> +
> +&sata2 {
> + status = "okay";
> +};
> +
> +&sata3 {
> + status = "okay";
> +};
> --
> 2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 07/11] arm64: dts: lx2160aqds: Add mdio mux nodes
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (5 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 06/11] arm64: dts: lx2160a-qds: enable sata nodes Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:21 ` [PATCH 08/11] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon Li Yang
` (3 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Pankaj Bansal, Li Yang
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The two external MDIO buses used to communicate with phy devices that
are external to SOC are muxed in LX2160AQDS board. These buses can be
routed to any one of the eight IO slots on LX2160AQDS board depending on
value in fpga register 0x54. Additionally the external MDIO1 is used to
communicate to the onboard RGMII phy devices. The mdio1 is controlled
by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga
register.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 480520152e1a..242c76298793 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -31,6 +31,130 @@ sb_3v3: regulator-sb3v3 {
regulator-boot-on;
regulator-always-on;
};
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* On-board PHY #1 RGMI1*/
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 { /* On-board PHY #2 RGMI2*/
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@18 { /* Slot #1 */
+ reg = <0x18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@19 { /* Slot #2 */
+ reg = <0x19>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1a { /* Slot #3 */
+ reg = <0x1a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1b { /* Slot #4 */
+ reg = <0x1b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1c { /* Slot #5 */
+ reg = <0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1d { /* Slot #6 */
+ reg = <0x1d>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1e { /* Slot #7 */
+ reg = <0x1e>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1f { /* Slot #8 */
+ reg = <0x1f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* Slot #1 (secondary EMI) */
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 { /* Slot #2 (secondary EMI) */
+ reg = <0x01>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@2 { /* Slot #3 (secondary EMI) */
+ reg = <0x02>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@3 { /* Slot #4 (secondary EMI) */
+ reg = <0x03>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@4 { /* Slot #5 (secondary EMI) */
+ reg = <0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@5 { /* Slot #6 (secondary EMI) */
+ reg = <0x05>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@6 { /* Slot #7 (secondary EMI) */
+ reg = <0x06>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@7 { /* Slot #8 (secondary EMI) */
+ reg = <0x07>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
&can0 {
@@ -81,6 +205,14 @@ dflash2: flash@0 {
};
};
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
&esdhc0 {
status = "okay";
};
@@ -107,6 +239,19 @@ mt35xu512aba0: flash@0 {
&i2c0 {
status = "okay";
+ fpga@66 {
+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
+ "simple-mfd";
+ reg = <0x66>;
+
+ mux: mux-controller {
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
+ };
+ };
+
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/11] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (6 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 07/11] arm64: dts: lx2160aqds: Add mdio mux nodes Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:21 ` [PATCH 09/11] arm64: dts: lx2160a: add pcie EP mode nodes Li Yang
` (2 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Li Yang, Hou Zhiqiang
The original dts was created based on the non-production rev1 silicon
which was only used for evaluation. Update the PCIe nodes to align with
the different controller used in production rev2 silicon.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 96 +++++++++----------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 5d1f84f4de29..05a3d403fe0c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1088,10 +1088,10 @@ sata3: sata@3230000 {
};
pcie1: pcie@3400000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
- <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1100,26 +1100,26 @@ pcie1: pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie2: pcie@3500000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
- <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1128,26 +1128,26 @@ pcie2: pcie@3500000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie3: pcie@3600000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
- <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1156,26 +1156,26 @@ pcie3: pcie@3600000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <256>;
- ppio-wins = <24>;
+ num-viewport = <256>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie4: pcie@3700000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
- <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1184,26 +1184,26 @@ pcie4: pcie@3700000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie5: pcie@3800000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
- <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
+ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1212,26 +1212,26 @@ pcie5: pcie@3800000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <256>;
- ppio-wins = <24>;
+ num-viewport = <256>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie6: pcie@3900000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
- <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
+ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1240,18 +1240,18 @@ pcie6: pcie@3900000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/11] arm64: dts: lx2160a: add pcie EP mode nodes
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (7 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 08/11] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:21 ` [PATCH 10/11] arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes Li Yang
2021-11-10 22:22 ` [PATCH 11/11] arm64: dts: lx2162aqds: support SD UHS-I and eMMC HS400 modes Li Yang
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Xiaowei Bao, Li Yang,
Hou Zhiqiang
From: Xiaowei Bao <xiaowei.bao@nxp.com>
The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 05a3d403fe0c..7835ad42da04 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1115,6 +1115,16 @@ pcie1: pcie@3400000 {
status = "disabled";
};
+ pcie_ep1: pcie_ep@3400000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie2: pcie@3500000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -1143,6 +1153,16 @@ pcie2: pcie@3500000 {
status = "disabled";
};
+ pcie_ep2: pcie_ep@3500000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie3: pcie@3600000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -1171,6 +1191,16 @@ pcie3: pcie@3600000 {
status = "disabled";
};
+ pcie_ep3: pcie_ep@3600000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
pcie4: pcie@3700000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
@@ -1199,6 +1229,16 @@ pcie4: pcie@3700000 {
status = "disabled";
};
+ pcie_ep4: pcie_ep@3700000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie5: pcie@3800000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
@@ -1227,6 +1267,16 @@ pcie5: pcie@3800000 {
status = "disabled";
};
+ pcie_ep5: pcie_ep@3800000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
pcie6: pcie@3900000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
@@ -1255,6 +1305,16 @@ pcie6: pcie@3900000 {
status = "disabled";
};
+ pcie_ep6: pcie_ep@3900000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/11] arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (8 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 09/11] arm64: dts: lx2160a: add pcie EP mode nodes Li Yang
@ 2021-11-10 22:21 ` Li Yang
2021-11-10 22:22 ` [PATCH 11/11] arm64: dts: lx2162aqds: support SD UHS-I and eMMC HS400 modes Li Yang
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:21 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Ran Wang, Li Yang
From: Ran Wang <ran.wang_1@nxp.com>
Enable USB3 HW LPM feature for lx2160a.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 7835ad42da04..01b6075a2803 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1023,6 +1023,7 @@ usb0: usb@3100000 {
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ usb3-lpm-capable;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
@@ -1034,6 +1035,7 @@ usb1: usb@3110000 {
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ usb3-lpm-capable;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 11/11] arm64: dts: lx2162aqds: support SD UHS-I and eMMC HS400 modes
2021-11-10 22:21 [PATCH 00/11] lx216x DTS updates Li Yang
` (9 preceding siblings ...)
2021-11-10 22:21 ` [PATCH 10/11] arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes Li Yang
@ 2021-11-10 22:22 ` Li Yang
10 siblings, 0 replies; 16+ messages in thread
From: Li Yang @ 2021-11-10 22:22 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-kernel, linux-arm-kernel, Yangbo Lu, Li Yang
From: Yangbo Lu <yangbo.lu@nxp.com>
The default NXP SDHC adapter cards for LX2162AQDS are SD 2.0/3.0
adapter card for eSDHC1, and eMMC 5.1 adapter card for eSDHC2.
Add speed modes properties supported by the two adapters in device
tree node.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index e1defee1ad27..1db9c1b58e7a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -226,10 +226,17 @@ &emdio2 {
};
&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread