[RFC PATCH net-next 0/4] Add support for LAN937x T1 Phy

[RFC PATCH net-next 0/4] Add support for LAN937x T1 Phy

[Arun Ramadoss]

LAN937x is a Multi-port 100Base-T1 Switch and it internally uses LAN87xx
T1 Phy.  This series of patch update the intialization routine for the
LAN87xx phy and also add LAN937x part support. Added the T1 Phy
master-slave configuration through ethtool.

Arun Ramadoss (4):
  net: phy: used the genphy_soft_reset for phy reset in Lan87xx
  net: phy: updated the initialization routine for LAN87xx
  net: phy: added the LAN937x phy support
  net: phy: added master-slave config and cable diagnostics for Lan937x

 drivers/net/phy/microchip_t1.c | 373 +++++++++++++++++++++++++++------
 1 file changed, 308 insertions(+), 65 deletions(-)

-- 
2.33.0

[RFC PATCH net-next 1/4] net: phy: used the genphy_soft_reset for phy reset in Lan87xx

[Arun Ramadoss]

Replaced current code for soft resetting phy to genphy_soft_reset
function. And added the macro for LAN87xx Phy ID.

Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/phy/microchip_t1.c | 32 ++++++++++++--------------------
 1 file changed, 12 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
index bc50224d43dd..ece21c1e5716 100644
--- a/drivers/net/phy/microchip_t1.c
+++ b/drivers/net/phy/microchip_t1.c
@@ -9,6 +9,9 @@
 #include <linux/ethtool.h>
 #include <linux/ethtool_netlink.h>
 
+#define LAN87XX_PHY_ID			0x0007c150
+#define MICROCHIP_PHY_ID_MASK		0xfffffff0
+
 /* External Register Control Register */
 #define LAN87XX_EXT_REG_CTL                     (0x14)
 #define LAN87XX_EXT_REG_CTL_RD_CTL              (0x1000)
@@ -197,20 +200,10 @@ static int lan87xx_phy_init(struct phy_device *phydev)
 	if (rc < 0)
 		return rc;
 
-	/* Soft Reset the SMI block */
-	rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
-					0x00, 0x8000, 0x8000);
-	if (rc < 0)
-		return rc;
-
-	/* Check to see if the self-clearing bit is cleared */
-	usleep_range(1000, 2000);
-	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
-			 PHYACC_ATTR_BANK_SMI, 0x00, 0);
+	/* phy Soft reset */
+	rc = genphy_soft_reset(phydev);
 	if (rc < 0)
 		return rc;
-	if ((rc & 0x8000) != 0)
-		return -ETIMEDOUT;
 
 	/* PHY Initialization */
 	for (i = 0; i < ARRAY_SIZE(init); i++) {
@@ -273,6 +266,9 @@ static int lan87xx_config_init(struct phy_device *phydev)
 {
 	int rc = lan87xx_phy_init(phydev);
 
+	if (rc < 0)
+		phydev_err(phydev, "failed to initialize phy\n");
+
 	return rc < 0 ? rc : 0;
 }
 
@@ -506,18 +502,14 @@ static int lan87xx_cable_test_get_status(struct phy_device *phydev,
 
 static struct phy_driver microchip_t1_phy_driver[] = {
 	{
-		.phy_id         = 0x0007c150,
-		.phy_id_mask    = 0xfffffff0,
-		.name           = "Microchip LAN87xx T1",
+		.phy_id         = LAN87XX_PHY_ID,
+		.phy_id_mask    = MICROCHIP_PHY_ID_MASK,
+		.name           = "LAN87xx T1",
 		.flags          = PHY_POLL_CABLE_TEST,
-
 		.features       = PHY_BASIC_T1_FEATURES,
-
 		.config_init	= lan87xx_config_init,
-
 		.config_intr    = lan87xx_phy_config_intr,
 		.handle_interrupt = lan87xx_handle_interrupt,
-
 		.suspend        = genphy_suspend,
 		.resume         = genphy_resume,
 		.cable_test_start = lan87xx_cable_test_start,
@@ -528,7 +520,7 @@ static struct phy_driver microchip_t1_phy_driver[] = {
 module_phy_driver(microchip_t1_phy_driver);
 
 static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
-	{ 0x0007c150, 0xfffffff0 },
+	{ LAN87XX_PHY_ID, MICROCHIP_PHY_ID_MASK},
 	{ }
 };
 
-- 
2.33.0

[RFC PATCH net-next 2/4] net: phy: updated the initialization routine for LAN87xx

[Arun Ramadoss]

The new initialization sequence is the improvement to the existing init
routine. Init routine does soft reset, run init script and set
Hw_init. Added the new access_ereg_clr_poll_timeout() for polling phy
bank write.

Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/phy/microchip_t1.c | 219 ++++++++++++++++++++++++++-------
 1 file changed, 177 insertions(+), 42 deletions(-)

diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
index ece21c1e5716..33325e5bd884 100644
--- a/drivers/net/phy/microchip_t1.c
+++ b/drivers/net/phy/microchip_t1.c
@@ -40,6 +40,7 @@
 #define	PHYACC_ATTR_MODE_READ		0
 #define	PHYACC_ATTR_MODE_WRITE		1
 #define	PHYACC_ATTR_MODE_MODIFY		2
+#define	PHYACC_ATTR_MODE_POLL		3
 
 #define	PHYACC_ATTR_BANK_SMI		0
 #define	PHYACC_ATTR_BANK_MISC		1
@@ -53,6 +54,28 @@
 #define	LAN87XX_CABLE_TEST_OPEN	1
 #define	LAN87XX_CABLE_TEST_SAME_SHORT	2
 
+/* T1 Registers */
+#define T1_AFE_PORT_CFG1_REG		0x0B
+#define T1_POWER_DOWN_CONTROL_REG	0x1A
+#define T1_SLV_FD_MULT_CFG_REG		0x18
+#define T1_CDR_CFG_PRE_LOCK_REG		0x05
+#define T1_CDR_CFG_POST_LOCK_REG	0x06
+#define T1_LCK_STG2_MUFACT_CFG_REG	0x1A
+#define T1_LCK_STG3_MUFACT_CFG_REG	0x1B
+#define T1_POST_LCK_MUFACT_CFG_REG	0x1C
+#define T1_TX_RX_FIFO_CFG_REG		0x02
+#define T1_TX_LPF_FIR_CFG_REG		0x55
+#define T1_SQI_CONFIG_REG		0x2E
+#define T1_MDIO_CONTROL2_REG		0x10
+#define T1_INTERRUPT_SOURCE_REG		0x18
+#define T1_INTERRUPT2_SOURCE_REG	0x08
+#define T1_EQ_FD_STG1_FRZ_CFG		0x69
+#define T1_EQ_FD_STG2_FRZ_CFG		0x6A
+#define T1_EQ_FD_STG3_FRZ_CFG		0x6B
+#define T1_EQ_FD_STG4_FRZ_CFG		0x6C
+#define T1_EQ_WT_FD_LCK_FRZ_CFG		0x6D
+#define T1_PST_EQ_LCK_STG1_FRZ_CFG	0x6E
+
 #define DRIVER_AUTHOR	"Nisar Sayed <nisar.sayed@microchip.com>"
 #define DRIVER_DESC	"Microchip LAN87XX T1 PHY driver"
 
@@ -120,6 +143,18 @@ static int access_ereg_modify_changed(struct phy_device *phydev,
 	return rc;
 }
 
+static int access_ereg_clr_poll_timeout(struct phy_device *phydev, u8 bank,
+					u8 offset, u16 mask, u16 clr)
+{
+	int val;
+
+	if (bank != PHYACC_ATTR_BANK_SMI)
+		return -EINVAL;
+
+	return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,
+				     150, 30000, true);
+}
+
 static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
 {
 	int rc;
@@ -160,46 +195,146 @@ static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
 static int lan87xx_phy_init(struct phy_device *phydev)
 {
 	static const struct access_ereg_val init[] = {
-		/* TX Amplitude = 5 */
-		{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_AFE, 0x0B,
-		 0x000A, 0x001E},
-		/* Clear SMI interrupts */
-		{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, 0x18,
-		 0, 0},
-		/* Clear MISC interrupts */
-		{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 0x08,
-		 0, 0},
-		/* Turn on TC10 Ring Oscillator (ROSC) */
-		{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_MISC, 0x20,
-		 0x0020, 0x0020},
-		/* WUR Detect Length to 1.2uS, LPC Detect Length to 1.09uS */
-		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_PCS, 0x20,
-		 0x283C, 0},
-		/* Wake_In Debounce Length to 39uS, Wake_Out Length to 79uS */
-		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x21,
-		 0x274F, 0},
-		/* Enable Auto Wake Forward to Wake_Out, ROSC on, Sleep,
-		 * and Wake_In to wake PHY
-		 */
-		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20,
-		 0x80A7, 0},
-		/* Enable WUP Auto Fwd, Enable Wake on MDI, Wakeup Debouncer
-		 * to 128 uS
-		 */
-		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x24,
-		 0xF110, 0},
-		/* Enable HW Init */
-		{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_SMI, 0x1A,
-		 0x0100, 0x0100},
+		/* TXPD/TXAMP6 Configs */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
+		  T1_AFE_PORT_CFG1_REG,       0x002D,  0 },
+		/* HW_Init Hi and Force_ED */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
+		  T1_POWER_DOWN_CONTROL_REG,  0x0308,  0 },
+		/* Equalizer Full Duplex Freeze - T1 Slave */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_EQ_FD_STG1_FRZ_CFG,     0x0002,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_EQ_FD_STG2_FRZ_CFG,     0x0002,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_EQ_FD_STG3_FRZ_CFG,     0x0002,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_EQ_FD_STG4_FRZ_CFG,     0x0002,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_EQ_WT_FD_LCK_FRZ_CFG,    0x0002,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002,  0 },
+		/* Slave Full Duplex Multi Configs */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_SLV_FD_MULT_CFG_REG,     0x0D53,  0 },
+		/* CDR Pre and Post Lock Configs */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_CDR_CFG_PRE_LOCK_REG,    0x0AB2,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_CDR_CFG_POST_LOCK_REG,   0x0AB3,  0 },
+		/* Lock Stage 2-3 Multi Factor Config */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB,  0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB,  0 },
+		/* Pointer delay */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },
+		/* Tx iir edits */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
+		/* SQI enable */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
+		  T1_SQI_CONFIG_REG,		0x9572, 0 },
+		/* Flag LPS and WUR as idle errors */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
+		  T1_MDIO_CONTROL2_REG,		0x0014, 0 },
+		/* HW_Init toggle, undo force ED, TXPD off */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
+		  T1_POWER_DOWN_CONTROL_REG,	0x0200, 0 },
+		/* Reset PCS to trigger hardware initialization */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
+		  T1_MDIO_CONTROL2_REG,		0x0094, 0 },
+		/* Poll till Hardware is initialized */
+		{ PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI,
+		  T1_MDIO_CONTROL2_REG,		0x0080, 0 },
+		/* Tx AMP - 0x06  */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
+		  T1_AFE_PORT_CFG1_REG,		0x000C, 0 },
+		/* Read INTERRUPT_SOURCE Register */
+		{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
+		  T1_INTERRUPT_SOURCE_REG,	0,	0 },
+		/* Read INTERRUPT_SOURCE Register */
+		{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC,
+		  T1_INTERRUPT2_SOURCE_REG,	0,	0 },
+		/* HW_Init Hi */
+		{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
+		  T1_POWER_DOWN_CONTROL_REG,	0x0300, 0 },
 	};
 	int rc, i;
 
-	/* Start manual initialization procedures in Managed Mode */
-	rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
-					0x1a, 0x0000, 0x0100);
-	if (rc < 0)
-		return rc;
-
 	/* phy Soft reset */
 	rc = genphy_soft_reset(phydev);
 	if (rc < 0)
@@ -207,11 +342,11 @@ static int lan87xx_phy_init(struct phy_device *phydev)
 
 	/* PHY Initialization */
 	for (i = 0; i < ARRAY_SIZE(init); i++) {
-		if (init[i].mode == PHYACC_ATTR_MODE_MODIFY) {
-			rc = access_ereg_modify_changed(phydev, init[i].bank,
-							init[i].offset,
-							init[i].val,
-							init[i].mask);
+		if (init[i].mode == PHYACC_ATTR_MODE_POLL) {
+			rc = access_ereg_clr_poll_timeout(phydev, init[i].bank,
+							  init[i].offset,
+							  init[i].val,
+							  init[i].mask);
 		} else {
 			rc = access_ereg(phydev, init[i].mode, init[i].bank,
 					 init[i].offset, init[i].val);
-- 
2.33.0

[RFC PATCH net-next 3/4] net: phy: added the LAN937x phy support

[Arun Ramadoss]

LAN937x T1 Phy is based on LAN87xx Phy, so reusing the init script of
the Lan87xx. There is a workaround in accessing the DSP bank register
for Lan937x Phy. Whenever there is a bank switch to DSP registers, then
we need a dummy read access before proceeding to the actual register
access.

Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/phy/microchip_t1.c | 47 +++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
index 33325e5bd884..634a1423182a 100644
--- a/drivers/net/phy/microchip_t1.c
+++ b/drivers/net/phy/microchip_t1.c
@@ -10,6 +10,7 @@
 #include <linux/ethtool_netlink.h>
 
 #define LAN87XX_PHY_ID			0x0007c150
+#define LAN937X_T1_PHY_ID		0x0007c181
 #define MICROCHIP_PHY_ID_MASK		0xfffffff0
 
 /* External Register Control Register */
@@ -76,8 +77,12 @@
 #define T1_EQ_WT_FD_LCK_FRZ_CFG		0x6D
 #define T1_PST_EQ_LCK_STG1_FRZ_CFG	0x6E
 
+#define T1_REG_BANK_SEL_MASK		0x7
+#define T1_REG_BANK_SEL			8
+#define T1_REG_ADDR_MASK		0xFF
+
 #define DRIVER_AUTHOR	"Nisar Sayed <nisar.sayed@microchip.com>"
-#define DRIVER_DESC	"Microchip LAN87XX T1 PHY driver"
+#define DRIVER_DESC	"Microchip LAN87XX/LAN937x T1 PHY driver"
 
 struct access_ereg_val {
 	u8  mode;
@@ -115,6 +120,32 @@ static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
 
 	ereg |= (bank << 8) | offset;
 
+	/* DSP bank access workaround for lan937x */
+	if (phydev->phy_id == LAN937X_T1_PHY_ID) {
+		u8 prev_bank;
+		u16 val;
+
+		/* Read previous selected bank */
+		rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);
+		if (rc < 0)
+			return rc;
+
+		/* store the prev_bank */
+		prev_bank = (rc >> T1_REG_BANK_SEL) & T1_REG_BANK_SEL_MASK;
+
+		if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
+			val = ereg & ~T1_REG_ADDR_MASK;
+
+			val &= ~LAN87XX_EXT_REG_CTL_WR_CTL;
+			val |= LAN87XX_EXT_REG_CTL_RD_CTL;
+
+			/* access twice for DSP bank change,dummy access */
+			rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
+			if (rc < 0)
+				return rc;
+		}
+	}
+
 	rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
 	if (rc < 0)
 		return rc;
@@ -397,7 +428,7 @@ static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev)
 	return IRQ_HANDLED;
 }
 
-static int lan87xx_config_init(struct phy_device *phydev)
+static int lan_phy_config_init(struct phy_device *phydev)
 {
 	int rc = lan87xx_phy_init(phydev);
 
@@ -642,13 +673,22 @@ static struct phy_driver microchip_t1_phy_driver[] = {
 		.name           = "LAN87xx T1",
 		.flags          = PHY_POLL_CABLE_TEST,
 		.features       = PHY_BASIC_T1_FEATURES,
-		.config_init	= lan87xx_config_init,
+		.config_init	= lan_phy_config_init,
 		.config_intr    = lan87xx_phy_config_intr,
 		.handle_interrupt = lan87xx_handle_interrupt,
 		.suspend        = genphy_suspend,
 		.resume         = genphy_resume,
 		.cable_test_start = lan87xx_cable_test_start,
 		.cable_test_get_status = lan87xx_cable_test_get_status,
+	},
+	{
+		.phy_id		= LAN937X_T1_PHY_ID,
+		.phy_id_mask	= MICROCHIP_PHY_ID_MASK,
+		.name		= "LAN937x T1",
+		.features	= PHY_BASIC_T1_FEATURES,
+		.config_init	= lan_phy_config_init,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
 	}
 };
 
@@ -656,6 +696,7 @@ module_phy_driver(microchip_t1_phy_driver);
 
 static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
 	{ LAN87XX_PHY_ID, MICROCHIP_PHY_ID_MASK},
+	{ LAN937X_T1_PHY_ID, MICROCHIP_PHY_ID_MASK},
 	{ }
 };
 
-- 
2.33.0

[RFC PATCH net-next 4/4] net: phy: added master-slave config and cable diagnostics for Lan937x

[Arun Ramadoss]

To configure the Lan937x T1 phy as master or slave using the ethtool -s
<dev> master-slave <forced-master/forced-slave>, the config_aneg and
read status functions are added. And for the cable-diagnostics, used the
lan87xx routines.

Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/phy/microchip_t1.c | 75 ++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
index 634a1423182a..3a0d4c4fab0a 100644
--- a/drivers/net/phy/microchip_t1.c
+++ b/drivers/net/phy/microchip_t1.c
@@ -81,6 +81,9 @@
 #define T1_REG_BANK_SEL			8
 #define T1_REG_ADDR_MASK		0xFF
 
+#define T1_MODE_STAT_REG		0x11
+#define T1_LINK_UP_MSK			BIT(0)
+
 #define DRIVER_AUTHOR	"Nisar Sayed <nisar.sayed@microchip.com>"
 #define DRIVER_DESC	"Microchip LAN87XX/LAN937x T1 PHY driver"
 
@@ -435,6 +438,11 @@ static int lan_phy_config_init(struct phy_device *phydev)
 	if (rc < 0)
 		phydev_err(phydev, "failed to initialize phy\n");
 
+	phydev->duplex = DUPLEX_FULL;
+	phydev->speed = SPEED_100;
+	phydev->pause = 0;
+	phydev->asym_pause = 0;
+
 	return rc < 0 ? rc : 0;
 }
 
@@ -666,6 +674,69 @@ static int lan87xx_cable_test_get_status(struct phy_device *phydev,
 	return 0;
 }
 
+static int lan937x_read_status(struct phy_device *phydev)
+{
+	int rc;
+
+	rc = phy_read(phydev, T1_MODE_STAT_REG);
+	if (rc < 0)
+		return rc;
+
+	if (rc & T1_LINK_UP_MSK)
+		phydev->link = 1;
+	else
+		phydev->link = 0;
+
+	phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
+	phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+
+	rc = phy_read(phydev, MII_CTRL1000);
+	if (rc < 0)
+		return rc;
+
+	if (rc & CTL1000_AS_MASTER)
+		phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
+	else
+		phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
+
+	rc = phy_read(phydev, MII_STAT1000);
+	if (rc < 0)
+		return rc;
+
+	if (rc & LPA_1000MSRES)
+		phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
+	else
+		phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
+
+	return 0;
+}
+
+static int lan937x_config_aneg(struct phy_device *phydev)
+{
+	int rc;
+	u16 ctl = 0;
+
+	switch (phydev->master_slave_set) {
+	case MASTER_SLAVE_CFG_MASTER_FORCE:
+		ctl |= CTL1000_AS_MASTER;
+		break;
+	case MASTER_SLAVE_CFG_SLAVE_FORCE:
+		break;
+	case MASTER_SLAVE_CFG_UNKNOWN:
+	case MASTER_SLAVE_CFG_UNSUPPORTED:
+		return 0;
+	default:
+		phydev_warn(phydev, "Unsupported Master/Slave mode\n");
+		return -EOPNOTSUPP;
+	}
+
+	rc = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
+	if (rc == 1)
+		rc = genphy_soft_reset(phydev);
+
+	return rc;
+}
+
 static struct phy_driver microchip_t1_phy_driver[] = {
 	{
 		.phy_id         = LAN87XX_PHY_ID,
@@ -689,6 +760,10 @@ static struct phy_driver microchip_t1_phy_driver[] = {
 		.config_init	= lan_phy_config_init,
 		.suspend	= genphy_suspend,
 		.resume		= genphy_resume,
+		.config_aneg    = lan937x_config_aneg,
+		.read_status	= lan937x_read_status,
+		.cable_test_start = lan87xx_cable_test_start,
+		.cable_test_get_status = lan87xx_cable_test_get_status,
 	}
 };
 
-- 
2.33.0

Re: [RFC PATCH net-next 4/4] net: phy: added master-slave config and cable diagnostics for Lan937x

[Russell King (Oracle)]

On Mon, Feb 28, 2022 at 07:35:10PM +0530, Arun Ramadoss wrote:
> To configure the Lan937x T1 phy as master or slave using the ethtool -s
> <dev> master-slave <forced-master/forced-slave>, the config_aneg and
> read status functions are added. And for the cable-diagnostics, used the
> lan87xx routines.
> 
> Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/phy/microchip_t1.c | 75 ++++++++++++++++++++++++++++++++++
>  1 file changed, 75 insertions(+)
> 
> diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
> index 634a1423182a..3a0d4c4fab0a 100644
> --- a/drivers/net/phy/microchip_t1.c
> +++ b/drivers/net/phy/microchip_t1.c
> @@ -81,6 +81,9 @@
>  #define T1_REG_BANK_SEL			8
>  #define T1_REG_ADDR_MASK		0xFF
>  
> +#define T1_MODE_STAT_REG		0x11
> +#define T1_LINK_UP_MSK			BIT(0)
> +
>  #define DRIVER_AUTHOR	"Nisar Sayed <nisar.sayed@microchip.com>"
>  #define DRIVER_DESC	"Microchip LAN87XX/LAN937x T1 PHY driver"
>  
> @@ -435,6 +438,11 @@ static int lan_phy_config_init(struct phy_device *phydev)
>  	if (rc < 0)
>  		phydev_err(phydev, "failed to initialize phy\n");
>  
> +	phydev->duplex = DUPLEX_FULL;
> +	phydev->speed = SPEED_100;
> +	phydev->pause = 0;
> +	phydev->asym_pause = 0;

Shouldn't this be done in lan937x_read_status()?

Have you tested this patch with various invocations of ethtool -s ?
E.g. autoneg on, autoneg off at various forced speeds, both suitable
for the PHY and unsuitable? Are all these sensibly handled?

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Re: [RFC PATCH net-next 4/4] net: phy: added master-slave config and cable diagnostics for Lan937x

[Arun.Ramadoss]

On Mon, 2022-02-28 at 14:12 +0000, Russell King (Oracle) wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Mon, Feb 28, 2022 at 07:35:10PM +0530, Arun Ramadoss wrote:
> > To configure the Lan937x T1 phy as master or slave using the
> > ethtool -s
> > <dev> master-slave <forced-master/forced-slave>, the config_aneg
> > and
> > read status functions are added. And for the cable-diagnostics,
> > used the
> > lan87xx routines.
> > 
> > Signed-off-by: Prasanna Vengateshan <
> > prasanna.vengateshan@microchip.com>
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> >  drivers/net/phy/microchip_t1.c | 75
> > ++++++++++++++++++++++++++++++++++
> >  1 file changed, 75 insertions(+)
> > 
> > diff --git a/drivers/net/phy/microchip_t1.c
> > b/drivers/net/phy/microchip_t1.c
> > index 634a1423182a..3a0d4c4fab0a 100644
> > --- a/drivers/net/phy/microchip_t1.c
> > +++ b/drivers/net/phy/microchip_t1.c
> > @@ -81,6 +81,9 @@
> >  #define T1_REG_BANK_SEL                      8
> >  #define T1_REG_ADDR_MASK             0xFF
> > 
> > +#define T1_MODE_STAT_REG             0x11
> > +#define T1_LINK_UP_MSK                       BIT(0)
> > +
> >  #define DRIVER_AUTHOR        "Nisar Sayed <
> > nisar.sayed@microchip.com>"
> >  #define DRIVER_DESC  "Microchip LAN87XX/LAN937x T1 PHY driver"
> > 
> > @@ -435,6 +438,11 @@ static int lan_phy_config_init(struct
> > phy_device *phydev)
> >       if (rc < 0)
> >               phydev_err(phydev, "failed to initialize phy\n");
> > 
> > +     phydev->duplex = DUPLEX_FULL;
> > +     phydev->speed = SPEED_100;
> > +     phydev->pause = 0;
> > +     phydev->asym_pause = 0;
> 
> Shouldn't this be done in lan937x_read_status()?
> 
> Have you tested this patch with various invocations of ethtool -s ?
> E.g. autoneg on, autoneg off at various forced speeds, both suitable
> for the PHY and unsuitable? Are all these sensibly handled?
> 
Thanks for the comment.

LAN937x is 100BaseT1 Phy and it doesn't provide option for changing
speed and autonegotiation. Since it is fixed and not going to change
using ethtool -s command, I added it in the config_init routine. I took
the drivers/net/phy/nxp-tja11xx as reference in which speed is
initialised in config_init routine. I tested the patch using the
ethtool -s for changing the master/slave configuration. For other
change like speed/duplex setting, driver will not make change. When I
execute ethtool <dev>, it returns the default value 100Mbps, Full
duplex.
If lan937x_read_status( ) is the suitable place, then I will move it
there. 

> Thanks.
> 
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Re: [RFC PATCH net-next 1/4] net: phy: used the genphy_soft_reset for phy reset in Lan87xx

[Andrew Lunn]

On Mon, Feb 28, 2022 at 07:35:07PM +0530, Arun Ramadoss wrote:
> Replaced current code for soft resetting phy to genphy_soft_reset
> function. And added the macro for LAN87xx Phy ID.

Hi Arun

Please don't mix multiple things in one patch.

Looking at the actual path, you have:

> +#define LAN87XX_PHY_ID			0x0007c150
> +#define MICROCHIP_PHY_ID_MASK		0xfffffff0

Part of macros for PHY ID.

> +
>  /* External Register Control Register */
>  #define LAN87XX_EXT_REG_CTL                     (0x14)
>  #define LAN87XX_EXT_REG_CTL_RD_CTL              (0x1000)
> @@ -197,20 +200,10 @@ static int lan87xx_phy_init(struct phy_device *phydev)
>  	if (rc < 0)
>  		return rc;
>  
> -	/* Soft Reset the SMI block */
> -	rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
> -					0x00, 0x8000, 0x8000);
> -	if (rc < 0)
> -		return rc;
> -
> -	/* Check to see if the self-clearing bit is cleared */
> -	usleep_range(1000, 2000);
> -	rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
> -			 PHYACC_ATTR_BANK_SMI, 0x00, 0);
> +	/* phy Soft reset */
> +	rc = genphy_soft_reset(phydev);
>  	if (rc < 0)
>  		return rc;
> -	if ((rc & 0x8000) != 0)
> -		return -ETIMEDOUT;

Soft reset.

>  
>  	/* PHY Initialization */
>  	for (i = 0; i < ARRAY_SIZE(init); i++) {
> @@ -273,6 +266,9 @@ static int lan87xx_config_init(struct phy_device *phydev)
>  {
>  	int rc = lan87xx_phy_init(phydev);
>  
> +	if (rc < 0)
> +		phydev_err(phydev, "failed to initialize phy\n");
> +

A new error message.

>  	return rc < 0 ? rc : 0;
>  }
>  
> @@ -506,18 +502,14 @@ static int lan87xx_cable_test_get_status(struct phy_device *phydev,
>  
>  static struct phy_driver microchip_t1_phy_driver[] = {
>  	{
> -		.phy_id         = 0x0007c150,
> -		.phy_id_mask    = 0xfffffff0,
> -		.name           = "Microchip LAN87xx T1",
> +		.phy_id         = LAN87XX_PHY_ID,
> +		.phy_id_mask    = MICROCHIP_PHY_ID_MASK,

2nd part of the PHY ID macros.

> +		.name           = "LAN87xx T1",

A change in name.

>  		.flags          = PHY_POLL_CABLE_TEST,
> -
>  		.features       = PHY_BASIC_T1_FEATURES,
> -
>  		.config_init	= lan87xx_config_init,
> -
>  		.config_intr    = lan87xx_phy_config_intr,
>  		.handle_interrupt = lan87xx_handle_interrupt,
> -

White space changes.

You can also use PHY_ID_MATCH_MODEL().

    Andrew

Re: [RFC PATCH net-next 3/4] net: phy: added the LAN937x phy support

[Andrew Lunn]

On Mon, Feb 28, 2022 at 07:35:09PM +0530, Arun Ramadoss wrote:
> LAN937x T1 Phy is based on LAN87xx Phy, so reusing the init script of
> the Lan87xx. There is a workaround in accessing the DSP bank register
> for Lan937x Phy. Whenever there is a bank switch to DSP registers, then
> we need a dummy read access before proceeding to the actual register
> access.
> 
> Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/phy/microchip_t1.c | 47 +++++++++++++++++++++++++++++++---
>  1 file changed, 44 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
> index 33325e5bd884..634a1423182a 100644
> --- a/drivers/net/phy/microchip_t1.c
> +++ b/drivers/net/phy/microchip_t1.c
> @@ -10,6 +10,7 @@
>  #include <linux/ethtool_netlink.h>
>  
>  #define LAN87XX_PHY_ID			0x0007c150
> +#define LAN937X_T1_PHY_ID		0x0007c181

I guess the last 1 is meaningless, given the mask?

  Andrew

Re: [RFC PATCH net-next 3/4] net: phy: added the LAN937x phy support

[Arun.Ramadoss]

On Wed, 2022-03-02 at 04:22 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Mon, Feb 28, 2022 at 07:35:09PM +0530, Arun Ramadoss wrote:
> > LAN937x T1 Phy is based on LAN87xx Phy, so reusing the init script
> > of
> > the Lan87xx. There is a workaround in accessing the DSP bank
> > register
> > for Lan937x Phy. Whenever there is a bank switch to DSP registers,
> > then
> > we need a dummy read access before proceeding to the actual
> > register
> > access.
> > 
> > Signed-off-by: Prasanna Vengateshan <
> > prasanna.vengateshan@microchip.com>
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> >  drivers/net/phy/microchip_t1.c | 47
> > +++++++++++++++++++++++++++++++---
> >  1 file changed, 44 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/net/phy/microchip_t1.c
> > b/drivers/net/phy/microchip_t1.c
> > index 33325e5bd884..634a1423182a 100644
> > --- a/drivers/net/phy/microchip_t1.c
> > +++ b/drivers/net/phy/microchip_t1.c
> > @@ -10,6 +10,7 @@
> >  #include <linux/ethtool_netlink.h>
> > 
> >  #define LAN87XX_PHY_ID                       0x0007c150
> > +#define LAN937X_T1_PHY_ID            0x0007c181
> 
> I guess the last 1 is meaningless, given the mask?
Thanks Andrew for the comment.
I will make 3:0 bits of phy_id to 0.
> 
>   Andrew

Re: [RFC PATCH net-next 1/4] net: phy: used the genphy_soft_reset for phy reset in Lan87xx

[Arun.Ramadoss]

On Wed, 2022-03-02 at 04:19 +0100, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Mon, Feb 28, 2022 at 07:35:07PM +0530, Arun Ramadoss wrote:
> > Replaced current code for soft resetting phy to genphy_soft_reset
> > function. And added the macro for LAN87xx Phy ID.
> 
> Hi Arun
> 
> Please don't mix multiple things in one patch.
> 
> Looking at the actual path, you have:
> 
> > +#define LAN87XX_PHY_ID                       0x0007c150
> > +#define MICROCHIP_PHY_ID_MASK                0xfffffff0
> 
> Part of macros for PHY ID.
> 
> > +
> >  /* External Register Control Register */
> >  #define LAN87XX_EXT_REG_CTL                     (0x14)
> >  #define LAN87XX_EXT_REG_CTL_RD_CTL              (0x1000)
> > @@ -197,20 +200,10 @@ static int lan87xx_phy_init(struct phy_device
> > *phydev)
> >       if (rc < 0)
> >               return rc;
> > 
> > -     /* Soft Reset the SMI block */
> > -     rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
> > -                                     0x00, 0x8000, 0x8000);
> > -     if (rc < 0)
> > -             return rc;
> > -
> > -     /* Check to see if the self-clearing bit is cleared */
> > -     usleep_range(1000, 2000);
> > -     rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
> > -                      PHYACC_ATTR_BANK_SMI, 0x00, 0);
> > +     /* phy Soft reset */
> > +     rc = genphy_soft_reset(phydev);
> >       if (rc < 0)
> >               return rc;
> > -     if ((rc & 0x8000) != 0)
> > -             return -ETIMEDOUT;
> 
> Soft reset.
> 
> > 
> >       /* PHY Initialization */
> >       for (i = 0; i < ARRAY_SIZE(init); i++) {
> > @@ -273,6 +266,9 @@ static int lan87xx_config_init(struct
> > phy_device *phydev)
> >  {
> >       int rc = lan87xx_phy_init(phydev);
> > 
> > +     if (rc < 0)
> > +             phydev_err(phydev, "failed to initialize phy\n");
> > +
> 
> A new error message.
> 
> >       return rc < 0 ? rc : 0;
> >  }
> > 
> > @@ -506,18 +502,14 @@ static int
> > lan87xx_cable_test_get_status(struct phy_device *phydev,
> > 
> >  static struct phy_driver microchip_t1_phy_driver[] = {
> >       {
> > -             .phy_id         = 0x0007c150,
> > -             .phy_id_mask    = 0xfffffff0,
> > -             .name           = "Microchip LAN87xx T1",
> > +             .phy_id         = LAN87XX_PHY_ID,
> > +             .phy_id_mask    = MICROCHIP_PHY_ID_MASK,
> 
> 2nd part of the PHY ID macros.
> 
> > +             .name           = "LAN87xx T1",
> 
> A change in name.
> 
> >               .flags          = PHY_POLL_CABLE_TEST,
> > -
> >               .features       = PHY_BASIC_T1_FEATURES,
> > -
> >               .config_init    = lan87xx_config_init,
> > -
> >               .config_intr    = lan87xx_phy_config_intr,
> >               .handle_interrupt = lan87xx_handle_interrupt,
> > -
> 
> White space changes.
> 
> You can also use PHY_ID_MATCH_MODEL().
> 
>     Andrew
Thanks for the comment. I will keep one change per patch and split this
patch & resend.