[PATCH v3 0/7] Add APCS support for SDX65

[PATCH v3 0/7] Add APCS support for SDX65

[Rohit Agarwal]

Hello,

Changes from v2:
 - Addressed Stephen's comments and made necessary changes.
 - Rebased on top

Changes from v1:
 - Addressed Mani's comments and made necessary changes.
 - Removed the last patch from the series as it became redundant after making changes.

This series adds APCS mailbox and clock support for SDX65. The APCS IP
in SDX65 provides IPC and clock functionalities. Hence, mailbox support
is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
driver "apcs-sdx65" is added.

Thanks,
Rohit

Rohit Agarwal (7):
  dt-bindings: mailbox: Add binding for SDX65 APCS
  mailbox: qcom: Add support for SDX65 APCS IPC
  dt-bindings: clock: Add A7 PLL binding for SDX65
  clk: qcom: Add A7 PLL support for SDX65
  ARM: dts: qcom: sdx65: Add support for A7 PLL clock
  ARM: dts: qcom: sdx65: Add support for APCS block
  clk: qcom: Add SDX65 APCS clock controller support

 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml |  3 ++-
 .../bindings/mailbox/qcom,apcs-kpss-global.yaml         |  1 +
 arch/arm/boot/dts/qcom-sdx65.dtsi                       | 17 +++++++++++++++++
 drivers/clk/qcom/Kconfig                                | 12 ++++++------
 drivers/clk/qcom/a7-pll.c                               |  1 +
 drivers/mailbox/qcom-apcs-ipc-mailbox.c                 |  5 +++++
 6 files changed, 32 insertions(+), 7 deletions(-)

-- 
2.7.4

[PATCH v3 1/7] dt-bindings: mailbox: Add binding for SDX65 APCS

[Rohit Agarwal]

Add devicetree YAML binding for SDX65 APCS GCC block. The APCS block
acts as the mailbox controller and also provides a clock output and
takes 3 clock sources (pll, aux, ref) as input.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 01e9d91..688ae8b 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -91,6 +91,7 @@ allOf:
         compatible:
           enum:
             - qcom,sdx55-apcs-gcc
+            - qcom,sdx65-apcs-gcc
     then:
       properties:
         clocks:
-- 
2.7.4

[PATCH v3 2/7] mailbox: qcom: Add support for SDX65 APCS IPC

[Rohit Agarwal]

In SDX65, the IPC bits are located in the APCS GCC block. Also, this block
can provide clock functionality. Hence, add support for IPC with correct
offset and name of the clock provider.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 9325d2a..54d7659 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
 	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
 };
 
+static const struct qcom_apcs_ipc_data sdx65_apcs_data = {
+	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
+};
+
 static const struct regmap_config apcs_regmap_config = {
 	.reg_bits = 32,
 	.reg_stride = 4,
@@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
 	{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
 	{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
 	{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
+	{ .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
-- 
2.7.4

[PATCH v3 3/7] dt-bindings: clock: Add A7 PLL binding for SDX65

[Rohit Agarwal]

Add YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..b8889dc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,13 +10,14 @@ maintainers:
   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 
 description:
-  The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+  The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
   frequency clock to the CPU.
 
 properties:
   compatible:
     enum:
       - qcom,sdx55-a7pll
+      - qcom,sdx65-a7pll
 
   reg:
     maxItems: 1
-- 
2.7.4

[PATCH v3 4/7] clk: qcom: Add A7 PLL support for SDX65

[Rohit Agarwal]

Add support for PLL found in Qualcomm SDX65 platforms which is used to
provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
frequency clock to the CPU above 1GHz as compared to the other sources
like GPLL0.

In this driver, the power domain is attached to the cpudev. This is
required for CPUFreq functionality and there seems to be no better place
to do other than this driver (no dedicated CPUFreq driver).

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 drivers/clk/qcom/Kconfig  | 6 +++---
 drivers/clk/qcom/a7-pll.c | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 42c8741..5159a1d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -29,11 +29,11 @@ config QCOM_A53PLL
 	  devices.
 
 config QCOM_A7PLL
-	tristate "SDX55 A7 PLL"
+	tristate "A7 PLL driver for SDX55 and SDX65"
 	help
-	  Support for the A7 PLL on SDX55 devices. It provides the CPU with
+	  Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
 	  frequencies above 1GHz.
-	  Say Y if you want to support higher CPU frequencies on SDX55
+	  Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
 	  devices.
 
 config QCOM_CLK_APCS_MSM8916
diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c
index c4a53e5..adb2121 100644
--- a/drivers/clk/qcom/a7-pll.c
+++ b/drivers/clk/qcom/a7-pll.c
@@ -84,6 +84,7 @@ static int qcom_a7pll_probe(struct platform_device *pdev)
 
 static const struct of_device_id qcom_a7pll_match_table[] = {
 	{ .compatible = "qcom,sdx55-a7pll" },
+	{ .compatible = "qcom,sdx65-a7pll" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
-- 
2.7.4

[PATCH v3 5/7] ARM: dts: qcom: sdx65: Add support for A7 PLL clock

[Rohit Agarwal]

On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 653df15..0219445 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -125,6 +125,14 @@
 			      <0x17802000 0x1000>;
 		};
 
+		a7pll: clock@17808000 {
+			compatible = "qcom,sdx65-a7pll";
+			reg = <0x17808000 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <0>;
+		};
+
 		timer@17820000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
2.7.4

[PATCH v3 6/7] ARM: dts: qcom: sdx65: Add support for APCS block

[Rohit Agarwal]

The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 0219445..b02d598 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -133,6 +133,15 @@
 			#clock-cells = <0>;
 		};
 
+		apcs: mailbox@17810000 {
+			compatible = "qcom,sdx65-apcs-gcc", "syscon";
+			reg = <0x17810000 0x2000>;
+			#mbox-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
+			clock-names = "ref", "pll", "aux";
+			#clock-cells = <0>;
+		};
+
 		timer@17820000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
2.7.4

[PATCH v3 7/7] clk: qcom: Add SDX65 APCS clock controller support

[Rohit Agarwal]

Update APCS Kconfig to reflect support for SDX65
APCS clock controller.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 drivers/clk/qcom/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5159a1d..a2fa9af 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996
 	  drivers for dynamic power management.
 
 config QCOM_CLK_APCS_SDX55
-	tristate "SDX55 APCS Clock Controller"
+	tristate "SDX55 and SDX65 APCS Clock Controller"
 	depends on QCOM_APCS_IPC || COMPILE_TEST
 	help
-	  Support for the APCS Clock Controller on SDX55 platform. The
+	  Support for the APCS Clock Controller on SDX55, SDX65 platform. The
 	  APCS is managing the mux and divider which feeds the CPUs.
 	  Say Y if you want to support CPU frequency scaling on devices
-	  such as SDX55.
+	  such as SDX55, SDX65.
 
 config QCOM_CLK_RPM
 	tristate "RPM based Clock Controller"
-- 
2.7.4

Re: [PATCH v3 2/7] mailbox: qcom: Add support for SDX65 APCS IPC

[Manivannan Sadhasivam]

On Mon, Feb 21, 2022 at 10:52:28AM +0530, Rohit Agarwal wrote:
> In SDX65, the IPC bits are located in the APCS GCC block. Also, this block
> can provide clock functionality. Hence, add support for IPC with correct
> offset and name of the clock provider.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 9325d2a..54d7659 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
>  	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
>  };
>  
> +static const struct qcom_apcs_ipc_data sdx65_apcs_data = {
> +	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
> +};

What I suggested was reusing the "qcom,sdx55-apcs-gcc" compatible in devicetree.
So with that, you won't need this specific compatible for SDX65 that essentially
duplicates SDX55.

Thanks,
Mani

> +
>  static const struct regmap_config apcs_regmap_config = {
>  	.reg_bits = 32,
>  	.reg_stride = 4,
> @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
>  	{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
>  	{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
>  	{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
> +	{ .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data },
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
> -- 
> 2.7.4
> 

Re: [PATCH v3 7/7] clk: qcom: Add SDX65 APCS clock controller support

[Manivannan Sadhasivam]

On Mon, Feb 21, 2022 at 10:52:33AM +0530, Rohit Agarwal wrote:
> Update APCS Kconfig to reflect support for SDX65
> APCS clock controller.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  drivers/clk/qcom/Kconfig | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 5159a1d..a2fa9af 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996
>  	  drivers for dynamic power management.
>  
>  config QCOM_CLK_APCS_SDX55
> -	tristate "SDX55 APCS Clock Controller"
> +	tristate "SDX55 and SDX65 APCS Clock Controller"
>  	depends on QCOM_APCS_IPC || COMPILE_TEST
>  	help
> -	  Support for the APCS Clock Controller on SDX55 platform. The
> +	  Support for the APCS Clock Controller on SDX55, SDX65 platform. The
>  	  APCS is managing the mux and divider which feeds the CPUs.
>  	  Say Y if you want to support CPU frequency scaling on devices
> -	  such as SDX55.
> +	  such as SDX55, SDX65.
>  
>  config QCOM_CLK_RPM
>  	tristate "RPM based Clock Controller"
> -- 
> 2.7.4
> 

Re: [PATCH v3 4/7] clk: qcom: Add A7 PLL support for SDX65

[Manivannan Sadhasivam]

On Mon, Feb 21, 2022 at 10:52:30AM +0530, Rohit Agarwal wrote:
> Add support for PLL found in Qualcomm SDX65 platforms which is used to
> provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
> frequency clock to the CPU above 1GHz as compared to the other sources
> like GPLL0.
> 
> In this driver, the power domain is attached to the cpudev. This is
> required for CPUFreq functionality and there seems to be no better place
> to do other than this driver (no dedicated CPUFreq driver).
> 

This tells what the driver is doing but not essentially what this patch does
i.e., you need to mention how the SDX65 PLL is added to the driver. Since you
are reusing the existing driver, this needs to be mentioned.

> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  drivers/clk/qcom/Kconfig  | 6 +++---
>  drivers/clk/qcom/a7-pll.c | 1 +
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 42c8741..5159a1d 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -29,11 +29,11 @@ config QCOM_A53PLL
>  	  devices.
>  
>  config QCOM_A7PLL
> -	tristate "SDX55 A7 PLL"
> +	tristate "A7 PLL driver for SDX55 and SDX65"
>  	help
> -	  Support for the A7 PLL on SDX55 devices. It provides the CPU with
> +	  Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
>  	  frequencies above 1GHz.
> -	  Say Y if you want to support higher CPU frequencies on SDX55
> +	  Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
>  	  devices.
>  
>  config QCOM_CLK_APCS_MSM8916
> diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c
> index c4a53e5..adb2121 100644
> --- a/drivers/clk/qcom/a7-pll.c
> +++ b/drivers/clk/qcom/a7-pll.c
> @@ -84,6 +84,7 @@ static int qcom_a7pll_probe(struct platform_device *pdev)
>  
>  static const struct of_device_id qcom_a7pll_match_table[] = {
>  	{ .compatible = "qcom,sdx55-a7pll" },
> +	{ .compatible = "qcom,sdx65-a7pll" },

I think here also you can just reuse the "qcom,sdx55-a7pll" compatible.

Thanks,
Mani

>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
> -- 
> 2.7.4
> 

Re: [PATCH v3 0/7] Add APCS support for SDX65

[Manivannan Sadhasivam]

On Mon, Feb 21, 2022 at 10:52:26AM +0530, Rohit Agarwal wrote:
> Hello,
> 
> Changes from v2:
>  - Addressed Stephen's comments and made necessary changes.
>  - Rebased on top
> 
> Changes from v1:
>  - Addressed Mani's comments and made necessary changes.
>  - Removed the last patch from the series as it became redundant after making changes.
> 
> This series adds APCS mailbox and clock support for SDX65. The APCS IP
> in SDX65 provides IPC and clock functionalities. Hence, mailbox support
> is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
> driver "apcs-sdx65" is added.

You seem to have missed adding r-o-b tags.

Thanks,
Mani

> 
> Thanks,
> Rohit
> 
> Rohit Agarwal (7):
>   dt-bindings: mailbox: Add binding for SDX65 APCS
>   mailbox: qcom: Add support for SDX65 APCS IPC
>   dt-bindings: clock: Add A7 PLL binding for SDX65
>   clk: qcom: Add A7 PLL support for SDX65
>   ARM: dts: qcom: sdx65: Add support for A7 PLL clock
>   ARM: dts: qcom: sdx65: Add support for APCS block
>   clk: qcom: Add SDX65 APCS clock controller support
> 
>  Documentation/devicetree/bindings/clock/qcom,a7pll.yaml |  3 ++-
>  .../bindings/mailbox/qcom,apcs-kpss-global.yaml         |  1 +
>  arch/arm/boot/dts/qcom-sdx65.dtsi                       | 17 +++++++++++++++++
>  drivers/clk/qcom/Kconfig                                | 12 ++++++------
>  drivers/clk/qcom/a7-pll.c                               |  1 +
>  drivers/mailbox/qcom-apcs-ipc-mailbox.c                 |  5 +++++
>  6 files changed, 32 insertions(+), 7 deletions(-)
> 
> -- 
> 2.7.4
> 

Re: [PATCH v3 4/7] clk: qcom: Add A7 PLL support for SDX65

[Rohit Agarwal]

On 2/21/2022 11:10 AM, Manivannan Sadhasivam wrote:
> On Mon, Feb 21, 2022 at 10:52:30AM +0530, Rohit Agarwal wrote:
>> Add support for PLL found in Qualcomm SDX65 platforms which is used to
>> provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
>> frequency clock to the CPU above 1GHz as compared to the other sources
>> like GPLL0.
>>
>> In this driver, the power domain is attached to the cpudev. This is
>> required for CPUFreq functionality and there seems to be no better place
>> to do other than this driver (no dedicated CPUFreq driver).
>>
> This tells what the driver is doing but not essentially what this patch does
> i.e., you need to mention how the SDX65 PLL is added to the driver. Since you
> are reusing the existing driver, this needs to be mentioned.
Will update.
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig  | 6 +++---
>>   drivers/clk/qcom/a7-pll.c | 1 +
>>   2 files changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 42c8741..5159a1d 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -29,11 +29,11 @@ config QCOM_A53PLL
>>   	  devices.
>>   
>>   config QCOM_A7PLL
>> -	tristate "SDX55 A7 PLL"
>> +	tristate "A7 PLL driver for SDX55 and SDX65"
>>   	help
>> -	  Support for the A7 PLL on SDX55 devices. It provides the CPU with
>> +	  Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
>>   	  frequencies above 1GHz.
>> -	  Say Y if you want to support higher CPU frequencies on SDX55
>> +	  Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
>>   	  devices.
>>   
>>   config QCOM_CLK_APCS_MSM8916
>> diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c
>> index c4a53e5..adb2121 100644
>> --- a/drivers/clk/qcom/a7-pll.c
>> +++ b/drivers/clk/qcom/a7-pll.c
>> @@ -84,6 +84,7 @@ static int qcom_a7pll_probe(struct platform_device *pdev)
>>   
>>   static const struct of_device_id qcom_a7pll_match_table[] = {
>>   	{ .compatible = "qcom,sdx55-a7pll" },
>> +	{ .compatible = "qcom,sdx65-a7pll" },
> I think here also you can just reuse the "qcom,sdx55-a7pll" compatible.
Ok, Will update. Thanks!
>
> Thanks,
> Mani
>
>>   	{ }
>>   };
>>   MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
>> -- 
>> 2.7.4
>>

Re: [PATCH v3 2/7] mailbox: qcom: Add support for SDX65 APCS IPC

[Rohit Agarwal]

On 2/21/2022 11:05 AM, Manivannan Sadhasivam wrote:
> On Mon, Feb 21, 2022 at 10:52:28AM +0530, Rohit Agarwal wrote:
>> In SDX65, the IPC bits are located in the APCS GCC block. Also, this block
>> can provide clock functionality. Hence, add support for IPC with correct
>> offset and name of the clock provider.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> index 9325d2a..54d7659 100644
>> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> @@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
>>   	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
>>   };
>>   
>> +static const struct qcom_apcs_ipc_data sdx65_apcs_data = {
>> +	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
>> +};
> What I suggested was reusing the "qcom,sdx55-apcs-gcc" compatible in devicetree.
> So with that, you won't need this specific compatible for SDX65 that essentially
> duplicates SDX55.
Clear. Will update. Thanks!
> Thanks,
> Mani
>
>> +
>>   static const struct regmap_config apcs_regmap_config = {
>>   	.reg_bits = 32,
>>   	.reg_stride = 4,
>> @@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
>>   	{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
>>   	{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
>>   	{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
>> +	{ .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data },
>>   	{}
>>   };
>>   MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
>> -- 
>> 2.7.4
>>

Re: [PATCH v3 1/7] dt-bindings: mailbox: Add binding for SDX65 APCS

[Rob Herring]

On Mon, Feb 21, 2022 at 10:52:27AM +0530, Rohit Agarwal wrote:
> Add devicetree YAML binding for SDX65 APCS GCC block. The APCS block
> acts as the mailbox controller and also provides a clock output and
> takes 3 clock sources (pll, aux, ref) as input.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
> index 01e9d91..688ae8b 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
> @@ -91,6 +91,7 @@ allOf:
>          compatible:
>            enum:
>              - qcom,sdx55-apcs-gcc
> +            - qcom,sdx65-apcs-gcc

Did you test this on your dts file? This doesn't work. You need to also 
add the compatible to the main 'compatible' schema.

>      then:
>        properties:
>          clocks:
> -- 
> 2.7.4
> 
>