* [v2] Add support for hwrng on PolarFire SoC @ 2022-04-08 10:09 conor.dooley 2022-04-08 10:09 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support conor.dooley 0 siblings, 1 reply; 6+ messages in thread From: conor.dooley @ 2022-04-08 10:09 UTC (permalink / raw) To: herbert; +Cc: linux-kernel, linux-crypto, linux-riscv, Conor Dooley From: Conor Dooley <conor.dooley@microchip.com> As it says on the tin, add support for the hardware rng on PolarFire SoC, which is accessed via the system controller. I dropped the maintainers entry change that v1 had, I will send a single update via RISCV to avoid any conflicts. On v1 I replied saying there was a refcount issue, but that's not actually the case, so no changes required there. Thanks, Conor Changes since v1: - Rebased on v5.18-rc1 - Dropped the MAINTAINERS change - Added quality estimation Conor Dooley (1): hwrng: mpfs - add polarfire soc hwrng support drivers/char/hw_random/Kconfig | 13 ++++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/mpfs-rng.c | 104 ++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/char/hw_random/mpfs-rng.c -- 2.35.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support 2022-04-08 10:09 [v2] Add support for hwrng on PolarFire SoC conor.dooley @ 2022-04-08 10:09 ` conor.dooley 2022-04-15 8:37 ` hwrng: mpfs - Enable COMPILE_TEST Herbert Xu 2022-04-15 8:40 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support Herbert Xu 0 siblings, 2 replies; 6+ messages in thread From: conor.dooley @ 2022-04-08 10:09 UTC (permalink / raw) To: herbert; +Cc: linux-kernel, linux-crypto, linux-riscv, Conor Dooley From: Conor Dooley <conor.dooley@microchip.com> Add a driver to access the hardware random number generator on the Polarfire SoC. The hwrng can only be accessed via the system controller, so use the mailbox interface the system controller exposes to access the hwrng. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- drivers/char/hw_random/Kconfig | 13 ++++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/mpfs-rng.c | 104 ++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/char/hw_random/mpfs-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index a087156a5818..c3a9f17bf31c 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -385,6 +385,19 @@ config HW_RANDOM_PIC32 If unsure, say Y. +config HW_RANDOM_POLARFIRE_SOC + tristate "Microchip PolarFire SoC Random Number Generator support" + depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL + help + This driver provides kernel-side support for the Random Number + Generator hardware found on PolarFire SoC (MPFS). + + To compile this driver as a module, choose M here. The + module will be called mfps_rng. + + If unsure, say N. + + config HW_RANDOM_MESON tristate "Amlogic Meson Random Number Generator support" depends on HW_RANDOM diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index 584d47ba32f7..3e948cf04476 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -46,3 +46,4 @@ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o +obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o diff --git a/drivers/char/hw_random/mpfs-rng.c b/drivers/char/hw_random/mpfs-rng.c new file mode 100644 index 000000000000..5813da617a48 --- /dev/null +++ b/drivers/char/hw_random/mpfs-rng.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) hardware random driver + * + * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley <conor.dooley@microchip.com> + */ + +#include <linux/module.h> +#include <linux/hw_random.h> +#include <linux/platform_device.h> +#include <soc/microchip/mpfs.h> + +#define CMD_OPCODE 0x21 +#define CMD_DATA_SIZE 0U +#define CMD_DATA NULL +#define MBOX_OFFSET 0U +#define RESP_OFFSET 0U +#define RNG_RESP_BYTES 32U + +struct mpfs_rng { + struct mpfs_sys_controller *sys_controller; + struct hwrng rng; +}; + +static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) +{ + struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng); + u32 response_msg[RNG_RESP_BYTES / sizeof(u32)]; + unsigned int count = 0, copy_size_bytes; + int ret; + + struct mpfs_mss_response response = { + .resp_status = 0U, + .resp_msg = (u32 *)response_msg, + .resp_size = RNG_RESP_BYTES + }; + struct mpfs_mss_msg msg = { + .cmd_opcode = CMD_OPCODE, + .cmd_data_size = CMD_DATA_SIZE, + .response = &response, + .cmd_data = CMD_DATA, + .mbox_offset = MBOX_OFFSET, + .resp_offset = RESP_OFFSET + }; + + while (count < max) { + ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg); + if (ret) + return ret; + + copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count; + memcpy(buf + count, response_msg, copy_size_bytes); + + count += copy_size_bytes; + if (!wait) + break; + } + + return count; +} + +static int mpfs_rng_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_rng *rng_priv; + int ret; + + rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL); + if (!rng_priv) + return -ENOMEM; + + rng_priv->sys_controller = mpfs_sys_controller_get(&pdev->dev); + if (IS_ERR(rng_priv->sys_controller)) + return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller), + "Failed to register system controller hwrng sub device\n"); + + rng_priv->rng.read = mpfs_rng_read; + rng_priv->rng.name = pdev->name; + rng_priv->rng.quality = 1024; + + platform_set_drvdata(pdev, rng_priv); + + ret = devm_hwrng_register(&pdev->dev, &rng_priv->rng); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to register MPFS hwrng\n"); + + dev_info(&pdev->dev, "Registered MPFS hwrng\n"); + + return 0; +} + +static struct platform_driver mpfs_rng_driver = { + .driver = { + .name = "mpfs-rng", + }, + .probe = mpfs_rng_probe, +}; +module_platform_driver(mpfs_rng_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); +MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver"); -- 2.35.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* hwrng: mpfs - Enable COMPILE_TEST 2022-04-08 10:09 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support conor.dooley @ 2022-04-15 8:37 ` Herbert Xu 2022-04-15 10:18 ` Conor.Dooley 2022-04-15 8:40 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support Herbert Xu 1 sibling, 1 reply; 6+ messages in thread From: Herbert Xu @ 2022-04-15 8:37 UTC (permalink / raw) To: conor.dooley; +Cc: linux-kernel, linux-crypto, linux-riscv The dependency on HW_RANDOM is redundant so this patch removes it. As this driver seems to cross-compile just fine we could also enable COMPILE_TEST. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 18aa97974b8b..dad084c0ecee 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -387,7 +387,7 @@ config HW_RANDOM_PIC32 config HW_RANDOM_POLARFIRE_SOC tristate "Microchip PolarFire SoC Random Number Generator support" - depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL + depends on POLARFIRE_SOC_SYS_CTRL || COMPILE_TEST help This driver provides kernel-side support for the Random Number Generator hardware found on PolarFire SoC (MPFS). -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: hwrng: mpfs - Enable COMPILE_TEST 2022-04-15 8:37 ` hwrng: mpfs - Enable COMPILE_TEST Herbert Xu @ 2022-04-15 10:18 ` Conor.Dooley 2022-04-15 10:20 ` Conor.Dooley 0 siblings, 1 reply; 6+ messages in thread From: Conor.Dooley @ 2022-04-15 10:18 UTC (permalink / raw) To: herbert; +Cc: linux-kernel, linux-crypto, linux-riscv On 15/04/2022 08:37, Herbert Xu wrote: > The dependency on HW_RANDOM is redundant so this patch removes it. > As this driver seems to cross-compile just fine we could also enable > COMPILE_TEST. Sorry about that. Compile test makes sense to me too. Reviewed-by: Conor Dooley <conor.dooley@microchip.com Thanks for applying my patch :) Conor > > Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> > > diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig > index 18aa97974b8b..dad084c0ecee 100644 > --- a/drivers/char/hw_random/Kconfig > +++ b/drivers/char/hw_random/Kconfig > @@ -387,7 +387,7 @@ config HW_RANDOM_PIC32 > > config HW_RANDOM_POLARFIRE_SOC > tristate "Microchip PolarFire SoC Random Number Generator support" > - depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL > + depends on POLARFIRE_SOC_SYS_CTRL || COMPILE_TEST > help > This driver provides kernel-side support for the Random Number > Generator hardware found on PolarFire SoC (MPFS). ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: hwrng: mpfs - Enable COMPILE_TEST 2022-04-15 10:18 ` Conor.Dooley @ 2022-04-15 10:20 ` Conor.Dooley 0 siblings, 0 replies; 6+ messages in thread From: Conor.Dooley @ 2022-04-15 10:20 UTC (permalink / raw) To: herbert; +Cc: linux-kernel, linux-crypto, linux-riscv On 15/04/2022 10:18, Conor.Dooley@microchip.com wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 15/04/2022 08:37, Herbert Xu wrote: >> The dependency on HW_RANDOM is redundant so this patch removes it. >> As this driver seems to cross-compile just fine we could also enable >> COMPILE_TEST. > > Sorry about that. Compile test makes sense to me too. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com woops, missing a >. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks for applying my patch :) > Conor > >> >> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> >> >> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig >> index 18aa97974b8b..dad084c0ecee 100644 >> --- a/drivers/char/hw_random/Kconfig >> +++ b/drivers/char/hw_random/Kconfig >> @@ -387,7 +387,7 @@ config HW_RANDOM_PIC32 >> >> config HW_RANDOM_POLARFIRE_SOC >> tristate "Microchip PolarFire SoC Random Number Generator support" >> - depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL >> + depends on POLARFIRE_SOC_SYS_CTRL || COMPILE_TEST >> help >> This driver provides kernel-side support for the Random Number >> Generator hardware found on PolarFire SoC (MPFS). > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support 2022-04-08 10:09 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support conor.dooley 2022-04-15 8:37 ` hwrng: mpfs - Enable COMPILE_TEST Herbert Xu @ 2022-04-15 8:40 ` Herbert Xu 1 sibling, 0 replies; 6+ messages in thread From: Herbert Xu @ 2022-04-15 8:40 UTC (permalink / raw) To: conor.dooley; +Cc: linux-kernel, linux-crypto, linux-riscv On Fri, Apr 08, 2022 at 10:09:12AM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add a driver to access the hardware random number generator on the > Polarfire SoC. The hwrng can only be accessed via the system controller, > so use the mailbox interface the system controller exposes to access the > hwrng. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/char/hw_random/Kconfig | 13 ++++ > drivers/char/hw_random/Makefile | 1 + > drivers/char/hw_random/mpfs-rng.c | 104 ++++++++++++++++++++++++++++++ > 3 files changed, 118 insertions(+) > create mode 100644 drivers/char/hw_random/mpfs-rng.c Patch applied. Thanks. -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-15 10:20 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-08 10:09 [v2] Add support for hwrng on PolarFire SoC conor.dooley 2022-04-08 10:09 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support conor.dooley 2022-04-15 8:37 ` hwrng: mpfs - Enable COMPILE_TEST Herbert Xu 2022-04-15 10:18 ` Conor.Dooley 2022-04-15 10:20 ` Conor.Dooley 2022-04-15 8:40 ` [PATCH v2 1/1] hwrng: mpfs - add polarfire soc hwrng support Herbert Xu
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