[PATCH] i2c: pasemi: Wait for write xfers to finish

[PATCH] i2c: pasemi: Wait for write xfers to finish

[Martin Povišer]

Wait for completion of write transfers before returning from the driver.
At first sight it may seem advantageous to leave write transfers queued
for the controller to carry out on its own time, but there's a couple of
issues with it:

 * Driver doesn't check for FIFO space.

 * The queued writes can complete while the driver is in its I2C read
   transfer path which means it will get confused by the raising of
   XEN (the 'transaction ended' signal). This can cause a spurious
   ENODATA error due to premature reading of the MRXFIFO register.

Adding the wait fixes some unreliability issues with the driver. There's
some efficiency cost to it (especially with pasemi_smb_waitready doing
its polling), but that will be alleviated once the driver receives
interrupt support.

Fixes: beb58aa39e6e ("i2c: PA Semi SMBus driver")
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
---

Tested on Apple's t8103 chip. To my knowledge the PA Semi controller
in its pre-Apple occurences behaves the same as far as this patch is
concerned.

 drivers/i2c/busses/i2c-pasemi-core.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/i2c/busses/i2c-pasemi-core.c b/drivers/i2c/busses/i2c-pasemi-core.c
index 7728c8460dc0..9028ffb58cc0 100644
--- a/drivers/i2c/busses/i2c-pasemi-core.c
+++ b/drivers/i2c/busses/i2c-pasemi-core.c
@@ -137,6 +137,12 @@ static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
 
 		TXFIFO_WR(smbus, msg->buf[msg->len-1] |
 			  (stop ? MTXFIFO_STOP : 0));
+
+		if (stop) {
+			err = pasemi_smb_waitready(smbus);
+			if (err)
+				goto reset_out;
+		}
 	}
 
 	return 0;
-- 
2.33.0

Re: [PATCH] i2c: pasemi: Wait for write xfers to finish

[Sven Peter]

On Tue, Mar 29, 2022, at 20:38, Martin Povišer wrote:
> Wait for completion of write transfers before returning from the driver.
> At first sight it may seem advantageous to leave write transfers queued
> for the controller to carry out on its own time, but there's a couple of
> issues with it:
>
>  * Driver doesn't check for FIFO space.

Maybe we should also check that in a follow-up patch :-)

>
>  * The queued writes can complete while the driver is in its I2C read
>    transfer path which means it will get confused by the raising of
>    XEN (the 'transaction ended' signal). This can cause a spurious
>    ENODATA error due to premature reading of the MRXFIFO register.
>
> Adding the wait fixes some unreliability issues with the driver. There's
> some efficiency cost to it (especially with pasemi_smb_waitready doing
> its polling), but that will be alleviated once the driver receives
> interrupt support.
>
> Fixes: beb58aa39e6e ("i2c: PA Semi SMBus driver")
> Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
> ---

Reviewed-by: Sven Peter <sven@svenpeter.dev>

>
> Tested on Apple's t8103 chip. To my knowledge the PA Semi controller
> in its pre-Apple occurences behaves the same as far as this patch is
> concerned.
>
>  drivers/i2c/busses/i2c-pasemi-core.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-pasemi-core.c 
> b/drivers/i2c/busses/i2c-pasemi-core.c
> index 7728c8460dc0..9028ffb58cc0 100644
> --- a/drivers/i2c/busses/i2c-pasemi-core.c
> +++ b/drivers/i2c/busses/i2c-pasemi-core.c
> @@ -137,6 +137,12 @@ static int pasemi_i2c_xfer_msg(struct i2c_adapter 
> *adapter,
> 
>  		TXFIFO_WR(smbus, msg->buf[msg->len-1] |
>  			  (stop ? MTXFIFO_STOP : 0));
> +
> +		if (stop) {
> +			err = pasemi_smb_waitready(smbus);
> +			if (err)
> +				goto reset_out;
> +		}

Looks like pasemi_smb_xfer doesn't suffer from the same issue.
I wonder if every device connected to the bus on the original PA Semi boards
only used that path and that's why no one noticed it.


Sven

Re: [PATCH] i2c: pasemi: Wait for write xfers to finish

[Wolfram Sang]

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On Tue, Mar 29, 2022 at 08:38:17PM +0200, Martin Povišer wrote:
> Wait for completion of write transfers before returning from the driver.
> At first sight it may seem advantageous to leave write transfers queued
> for the controller to carry out on its own time, but there's a couple of
> issues with it:
> 
>  * Driver doesn't check for FIFO space.
> 
>  * The queued writes can complete while the driver is in its I2C read
>    transfer path which means it will get confused by the raising of
>    XEN (the 'transaction ended' signal). This can cause a spurious
>    ENODATA error due to premature reading of the MRXFIFO register.
> 
> Adding the wait fixes some unreliability issues with the driver. There's
> some efficiency cost to it (especially with pasemi_smb_waitready doing
> its polling), but that will be alleviated once the driver receives
> interrupt support.
> 
> Fixes: beb58aa39e6e ("i2c: PA Semi SMBus driver")
> Signed-off-by: Martin Povišer <povik+lin@cutebit.org>

Applied to for-current, thanks!


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