* [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace
@ 2021-12-21 12:51 Sumit Gupta
2021-12-21 12:51 ` [Patch v3 1/9] soc: tegra: set ERD bit to mask inband errors Sumit Gupta
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
The patch series adds Control BackBone(CBB) error handling
driver for Tegra194, Tegra234 and Tegra-Grace SOC's.
Tegra194 is using CBB version 1.0. Tegra234 and Tegra-Grace
are using CBB version 2.0. Both CBB1.0 and CBB2.0 have
different internal architecture. So, separate drivers are
required.
Tegra194 and Tegra234 are using Device Tree. Tegra-Grace is
using ACPI.
---
v2 -> v3:
- fixed warnings with GCC 11.2 and W=1 reported by kernel test robot.
- changed some function names to make consistent with tegra_cbb_*.
v1 -> v2:
- moved err-notifier-base and off-mask-erd from DT to driver.
- yaml fixes by Thierry.
Sumit Gupta (9):
soc: tegra: set ERD bit to mask inband errors
dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding
dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
arm64: tegra: Add node for CBB1.0 in Tegra194 SOC
soc: tegra: cbb: Add CBB1.0 driver for Tegra194
dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB2.0 binding
arm64: tegra: Add node for CBB2.0 in Tegra234 SOC
soc: tegra: cbb: Add driver for Tegra234 CBB2.0
soc: tegra: cbb: Add support for tegra-grace SOC
.../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +
.../arm/tegra/nvidia,tegra194-cbb.yaml | 93 +
.../arm/tegra/nvidia,tegra234-cbb.yaml | 70 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 62 +-
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 42 +
drivers/soc/tegra/Kconfig | 9 +
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/cbb/Makefile | 9 +
drivers/soc/tegra/cbb/tegra-cbb.c | 198 ++
drivers/soc/tegra/cbb/tegra194-cbb.c | 2261 +++++++++++++++++
drivers/soc/tegra/cbb/tegra234-cbb.c | 829 ++++++
drivers/soc/tegra/fuse/tegra-apbmisc.c | 29 +-
include/soc/tegra/fuse.h | 6 +
include/soc/tegra/tegra-cbb.h | 43 +
include/soc/tegra/tegra-grace-cbb.h | 219 ++
include/soc/tegra/tegra194-cbb.h | 158 ++
include/soc/tegra/tegra234-cbb.h | 342 +++
17 files changed, 4408 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
create mode 100644 drivers/soc/tegra/cbb/Makefile
create mode 100644 drivers/soc/tegra/cbb/tegra-cbb.c
create mode 100644 drivers/soc/tegra/cbb/tegra194-cbb.c
create mode 100644 drivers/soc/tegra/cbb/tegra234-cbb.c
create mode 100644 include/soc/tegra/tegra-cbb.h
create mode 100644 include/soc/tegra/tegra-grace-cbb.h
create mode 100644 include/soc/tegra/tegra194-cbb.h
create mode 100644 include/soc/tegra/tegra234-cbb.h
--
2.17.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Patch v3 1/9] soc: tegra: set ERD bit to mask inband errors
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 2/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding Sumit Gupta
` (7 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Add function to set Error Response Disable bit in MISCREG_CCROC_ERR_CONFIG
register from the Control Backbone(CBB) error handler driver.
ERD bit allows masking of SError due to inband errors which are caused by
illegal register accesses through CBB. When the bit is set, interrupt is
used for reporting errors and magic code '0xdead2003' is returned.
This change is only required for Tegra194 SOC as the config is moved to CBB
register space for future SOC's. Also, remove unmapping the apbmisc_base as
it's required to get the base address for accessing the misc register.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/soc/tegra/fuse/tegra-apbmisc.c | 29 ++++++++++++++++++++++++--
include/soc/tegra/fuse.h | 6 ++++++
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index 590c862538d0..de833f8d2408 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -16,12 +16,16 @@
#define FUSE_SKU_INFO 0x10
+#define ERD_ERR_CONFIG 0x120c
+#define ERD_MASK_INBAND_ERR 0x1
+
#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+static void __iomem *apbmisc_base;
static bool long_ram_code;
static u32 strapping;
static u32 chipid;
@@ -93,6 +97,28 @@ u32 tegra_read_ram_code(void)
}
EXPORT_SYMBOL_GPL(tegra_read_ram_code);
+/*
+ * The function sets ERD(Error Response Disable) bit.
+ * This allows to mask inband errors and always send an
+ * OKAY response from CBB to the master which caused error.
+ */
+int tegra194_miscreg_mask_serror(void)
+{
+ if (!apbmisc_base)
+ return -EPROBE_DEFER;
+
+ if (!of_machine_is_compatible("nvidia,tegra194")) {
+ WARN(1, "Only supported for Tegra194 devices!\n");
+ return -EOPNOTSUPP;
+ }
+
+ writel_relaxed(ERD_MASK_INBAND_ERR,
+ apbmisc_base + ERD_ERR_CONFIG);
+
+ return 0;
+}
+EXPORT_SYMBOL(tegra194_miscreg_mask_serror);
+
static const struct of_device_id apbmisc_match[] __initconst = {
{ .compatible = "nvidia,tegra20-apbmisc", },
{ .compatible = "nvidia,tegra186-misc", },
@@ -134,7 +160,7 @@ void __init tegra_init_revision(void)
void __init tegra_init_apbmisc(void)
{
- void __iomem *apbmisc_base, *strapping_base;
+ void __iomem *strapping_base;
struct resource apbmisc, straps;
struct device_node *np;
@@ -196,7 +222,6 @@ void __init tegra_init_apbmisc(void)
pr_err("failed to map APBMISC registers\n");
} else {
chipid = readl_relaxed(apbmisc_base + 4);
- iounmap(apbmisc_base);
}
strapping_base = ioremap(straps.start, resource_size(&straps));
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index 67d2bc856fbc..977c334136e9 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -58,6 +58,7 @@ u32 tegra_read_chipid(void);
u8 tegra_get_chip_id(void);
u8 tegra_get_platform(void);
bool tegra_is_silicon(void);
+int tegra194_miscreg_mask_serror(void);
#else
static struct tegra_sku_info tegra_sku_info __maybe_unused;
@@ -95,6 +96,11 @@ static inline bool tegra_is_silicon(void)
{
return false;
}
+
+static inline int tegra194_miscreg_mask_serror(void)
+{
+ return false;
+}
#endif
struct device *tegra_soc_device_register(void);
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 2/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
2021-12-21 12:51 ` [Patch v3 1/9] soc: tegra: set ERD bit to mask inband errors Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding Sumit Gupta
` (6 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Add device-tree binding documentation to represent the error handling
driver for Control Backbone (CBB) version 1.0 used in Tegra194 SOC.
The driver prints debug information about failed transactions due to
illegal register accesses on receiving interrupt from CBB.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
.../arm/tegra/nvidia,tegra194-cbb.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml
new file mode 100644
index 000000000000..3167f0450298
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra194 CBB 1.0 device tree bindings
+
+maintainers:
+ - Sumit Gupta <sumitg@nvidia.com>
+
+description: |+
+ The Control Backbone (CBB) is comprised of the physical path from an initiator to a target's
+ register configuration space. CBB 1.0 has multiple hierarchical sub-NOCs (Network-on-Chip) and
+ connects various initiators and targets using different bridges like AXIP2P, AXI2APB.
+
+ This driver handles errors due to illegal register accesses reported by the NOCs inside the CBB.
+ NOCs reporting errors are cluster NOCs "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB
+ Central NOC" which is the main NOC.
+
+ By default, the access issuing initiator is informed about the error using SError or Data Abort
+ exception unless the ERD (Error Response Disable) is enabled/set for that initiator. If the ERD
+ is enabled, then SError or Data Abort is masked and the error is reported with interrupt.
+
+ - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the errors due to illegal
+ accesses from CCPLEX are reported by interrupts. If ERD is not set, then error is reported by
+ SError.
+ - For other initiators, the ERD is disabled. So, the access issuing initiator is informed about
+ the illegal access by Data Abort exception. In addition, an interrupt is also generated to
+ CCPLEX. These initiators include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
+ engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder engine) etc which can
+ initiate transactions.
+
+ The driver prints relevant debug information like Error Code, Error Description, Master, Address,
+ AXI ID, Cache, Protection, Security Group etc on receiving error notification.
+
+properties:
+ $nodename:
+ pattern: "^[a-z]+-noc@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - nvidia,tegra194-cbb-noc
+ - nvidia,tegra194-aon-noc
+ - nvidia,tegra194-bpmp-noc
+ - nvidia,tegra194-rce-noc
+ - nvidia,tegra194-sce-noc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ CCPLEX receives secure or nonsecure interrupt depending on error type. A secure interrupt is
+ received for SEC(firewall) & SLV errors and a non-secure interrupt is received for TMO & DEC
+ errors.
+ items:
+ - description: non-secure interrupt
+ - description: secure interrupt
+
+ nvidia,axi2apb:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description:
+ Specifies the node having all axi2apb bridges which need to be checked for any error logged
+ in their status register.
+
+ nvidia,apbmisc:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description:
+ Specifies the apbmisc node which need to be used for reading ERD register.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - nvidia,axi2apb
+ - nvidia,apbmisc
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ cbb-noc@2300000 {
+ compatible = "nvidia,tegra194-cbb-noc";
+ reg = <0x02300000 0x1000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
2021-12-21 12:51 ` [Patch v3 1/9] soc: tegra: set ERD bit to mask inband errors Sumit Gupta
2021-12-21 12:51 ` [Patch v3 2/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-22 18:35 ` Rob Herring
2021-12-21 12:51 ` [Patch v3 4/9] arm64: tegra: Add node for CBB1.0 in Tegra194 SOC Sumit Gupta
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira, Thierry Reding
Add device-tree binding documentation to represent the axi2apb bridges
used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for APB
slaves are reported as slave error because APB bas single bit to report
error. So, CBB driver needs to further check error status registers of
all the axi2apb bridges to find error type.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
new file mode 100644
index 000000000000..788a13f8aa93
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra194 AXI2APB bridge
+
+maintainers:
+ - Sumit Gupta <sumitg@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^axi2apb@([0-9a-f]+)$"
+
+ compatible:
+ enum:
+ - nvidia,tegra194-axi2apb
+
+ reg:
+ maxItems: 6
+ description: Physical base address and length of registers for all bridges
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ axi2apb: axi2apb@2390000 {
+ compatible = "nvidia,tegra194-axi2apb";
+ reg = <0x02390000 0x1000>,
+ <0x023a0000 0x1000>,
+ <0x023b0000 0x1000>,
+ <0x023c0000 0x1000>,
+ <0x023d0000 0x1000>,
+ <0x023e0000 0x1000>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 4/9] arm64: tegra: Add node for CBB1.0 in Tegra194 SOC
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
` (2 preceding siblings ...)
2021-12-21 12:51 ` [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 5/9] soc: tegra: cbb: Add CBB1.0 driver for Tegra194 Sumit Gupta
` (4 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Adding device tree nodes to enable the driver for handling errors from
Control Backbone(CBB). CBB version 1.0 is used in Tegra194 SOC.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 62 +++++++++++++++++++++++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 851e049b3519..dddc4982b35a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -22,7 +22,7 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
- misc@100000 {
+ apbmisc: misc@100000 {
compatible = "nvidia,tegra194-misc";
reg = <0x00100000 0xf000>,
<0x0010f000 0x1000>;
@@ -87,6 +87,27 @@
gpio-controller;
};
+ cbb-noc@2300000 {
+ compatible = "nvidia,tegra194-cbb-noc";
+ reg = <0x02300000 0x1000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
+ axi2apb: axi2apb@2390000 {
+ compatible = "nvidia,tegra194-axi2apb";
+ reg = <0x2390000 0x1000>,
+ <0x23a0000 0x1000>,
+ <0x23b0000 0x1000>,
+ <0x23c0000 0x1000>,
+ <0x23d0000 0x1000>,
+ <0x23e0000 0x1000>;
+ status = "okay";
+ };
+
ethernet@2490000 {
compatible = "nvidia,tegra194-eqos",
"nvidia,tegra186-eqos",
@@ -1359,6 +1380,26 @@
#phy-cells = <0>;
};
+ sce-noc@b600000 {
+ compatible = "nvidia,tegra194-sce-noc";
+ reg = <0xb600000 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
+ rce-noc@be00000 {
+ compatible = "nvidia,tegra194-rce-noc";
+ reg = <0xbe00000 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
reg = <0x0c150000 0x90000>;
@@ -1374,6 +1415,15 @@
#mbox-cells = <2>;
};
+ aon-noc@c600000 {
+ compatible = "nvidia,tegra194-aon-noc";
+ reg = <0xc600000 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x0c240000 0x10000>;
@@ -1552,6 +1602,16 @@
status = "okay";
};
+ bpmp-noc@d600000 {
+ compatible = "nvidia,tegra194-bpmp-noc";
+ reg = <0xd600000 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,axi2apb = <&axi2apb>;
+ nvidia,apbmisc = <&apbmisc>;
+ status = "okay";
+ };
+
host1x@13e00000 {
compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 5/9] soc: tegra: cbb: Add CBB1.0 driver for Tegra194
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
` (3 preceding siblings ...)
2021-12-21 12:51 ` [Patch v3 4/9] arm64: tegra: Add node for CBB1.0 in Tegra194 SOC Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 6/9] dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB2.0 binding Sumit Gupta
` (3 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Adding driver to handle errors from Control Backbone(CBB) which are
generated due to illegal accesses. CBB1.0 is used in Tegra194 SOC.
When an error is reported from a NOC within CBB, the driver prints
debug information about failed transaction like Error Code, Error
Description, Master, Address, AXI ID, Cache, Protection, Security
Group etc. It then causes system crash using BUG_ON() or call WARN()
based on whether the error type is fatal or not.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/soc/tegra/Kconfig | 9 +
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/cbb/Makefile | 8 +
drivers/soc/tegra/cbb/tegra-cbb.c | 198 +++
drivers/soc/tegra/cbb/tegra194-cbb.c | 2261 ++++++++++++++++++++++++++
include/soc/tegra/tegra-cbb.h | 43 +
include/soc/tegra/tegra194-cbb.h | 158 ++
7 files changed, 2678 insertions(+)
create mode 100644 drivers/soc/tegra/cbb/Makefile
create mode 100644 drivers/soc/tegra/cbb/tegra-cbb.c
create mode 100644 drivers/soc/tegra/cbb/tegra194-cbb.c
create mode 100644 include/soc/tegra/tegra-cbb.h
create mode 100644 include/soc/tegra/tegra194-cbb.h
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 8b53ed1cc67e..0520b9744ec4 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -161,3 +161,12 @@ config SOC_TEGRA30_VOLTAGE_COUPLER
bool "Voltage scaling support for Tegra30 SoCs"
depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
depends on REGULATOR
+
+config SOC_TEGRA_CBB
+ tristate "Tegra driver to handle error from CBB"
+ depends on ARCH_TEGRA_194_SOC
+ default y
+ help
+ Support for handling error from Tegra Control Backbone(CBB).
+ This driver handles the errors from CBB and prints debug
+ information about the failed transactions.
diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile
index 054e862b63d8..d722f512dc9d 100644
--- a/drivers/soc/tegra/Makefile
+++ b/drivers/soc/tegra/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += fuse/
+obj-y += cbb/
obj-y += common.o
obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o
diff --git a/drivers/soc/tegra/cbb/Makefile b/drivers/soc/tegra/cbb/Makefile
new file mode 100644
index 000000000000..3f9ff6575628
--- /dev/null
+++ b/drivers/soc/tegra/cbb/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Control Backbone Driver code.
+#
+ifdef CONFIG_SOC_TEGRA_CBB
+obj-y += tegra-cbb.o
+obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-cbb.o
+endif
diff --git a/drivers/soc/tegra/cbb/tegra-cbb.c b/drivers/soc/tegra/cbb/tegra-cbb.c
new file mode 100644
index 000000000000..75583c938a97
--- /dev/null
+++ b/drivers/soc/tegra/cbb/tegra-cbb.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ */
+
+#include <asm/cpufeature.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/version.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/tegra-cbb.h>
+
+void tegra_cbb_print_err(struct seq_file *file, const char *fmt, ...)
+{
+ va_list args;
+ struct va_format vaf;
+
+ va_start(args, fmt);
+
+ if (file) {
+ seq_vprintf(file, fmt, args);
+ } else {
+ vaf.fmt = fmt;
+ vaf.va = &args;
+ pr_crit("%pV", &vaf);
+ }
+
+ va_end(args);
+}
+
+void tegra_cbb_print_cache(struct seq_file *file, u32 cache)
+{
+ char *buff_str;
+ char *mod_str;
+ char *rd_str;
+ char *wr_str;
+
+ buff_str = (cache & BIT(0)) ? "Bufferable " : "";
+ mod_str = (cache & BIT(1)) ? "Modifiable " : "";
+ rd_str = (cache & BIT(2)) ? "Read-Allocate " : "";
+ wr_str = (cache & BIT(3)) ? "Write-Allocate" : "";
+
+ if (cache == 0x0)
+ buff_str = "Device Non-Bufferable";
+
+ tegra_cbb_print_err(file, "\t Cache\t\t\t: 0x%x -- %s%s%s%s\n",
+ cache, buff_str, mod_str, rd_str, wr_str);
+}
+
+void tegra_cbb_print_prot(struct seq_file *file, u32 prot)
+{
+ char *data_str;
+ char *secure_str;
+ char *priv_str;
+
+ data_str = (prot & 0x4) ? "Instruction" : "Data";
+ secure_str = (prot & 0x2) ? "Non-Secure" : "Secure";
+ priv_str = (prot & 0x1) ? "Privileged" : "Unprivileged";
+
+ tegra_cbb_print_err(file, "\t Protection\t\t: 0x%x -- %s, %s, %s Access\n",
+ prot, priv_str, secure_str, data_str);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int created_root;
+
+static int cbb_err_show(struct seq_file *file, void *data)
+{
+ struct tegra_cbb *cbb = file->private;
+
+ return cbb->ops->cbb_err_debugfs_show(cbb, file, data);
+}
+
+static int cbb_err_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, cbb_err_show, inode->i_private);
+}
+
+static const struct file_operations cbb_err_fops = {
+ .open = cbb_err_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release
+};
+
+static int tegra_cbb_err_dbgfs_init(struct tegra_cbb *cbb)
+{
+ struct dentry *d;
+
+ if (!created_root) {
+ d = debugfs_create_file("tegra_cbb_err", 0444, NULL, cbb,
+ &cbb_err_fops);
+ if (IS_ERR_OR_NULL(d)) {
+ pr_err
+ ("%s: could not create 'tegra_cbb_err' node\n",
+ __func__);
+ return PTR_ERR(d);
+ }
+ created_root = true;
+ }
+ return 0;
+}
+
+#else
+static int tegra_cbb_err_dbgfs_init(void) { return 0; }
+#endif
+
+void tegra_cbb_stallen(struct tegra_cbb *cbb)
+{
+ if (cbb->ops->stallen)
+ cbb->ops->stallen(cbb);
+}
+
+void tegra_cbb_faulten(struct tegra_cbb *cbb)
+{
+ if (cbb->ops->faulten)
+ cbb->ops->faulten(cbb);
+}
+
+void tegra_cbb_errclr(struct tegra_cbb *cbb)
+{
+ if (cbb->ops->errclr)
+ cbb->ops->errclr(cbb);
+}
+
+u32 tegra_cbb_errvld(struct tegra_cbb *cbb)
+{
+ if (cbb->ops->errvld)
+ return cbb->ops->errvld(cbb);
+ else
+ return 0;
+}
+
+int tegra_cbb_err_getirq(struct platform_device *pdev, int *nonsec_irq, int *sec_irq)
+{
+ int num_intr = 0;
+ int intr_indx = 0;
+
+ num_intr = platform_irq_count(pdev);
+ if (!num_intr)
+ return -EINVAL;
+
+ if (num_intr == 2) {
+ *nonsec_irq = platform_get_irq(pdev, intr_indx);
+ if (*nonsec_irq <= 0) {
+ dev_err(&pdev->dev, "can't get irq (%d)\n", *nonsec_irq);
+ return -ENOENT;
+ }
+ intr_indx++;
+ }
+
+ *sec_irq = platform_get_irq(pdev, intr_indx);
+ if (*sec_irq <= 0) {
+ dev_err(&pdev->dev, "can't get irq (%d)\n", *sec_irq);
+ return -ENOENT;
+ }
+
+ if (num_intr == 1)
+ dev_info(&pdev->dev, "secure_irq = %d\n", *sec_irq);
+ if (num_intr == 2)
+ dev_info(&pdev->dev, "secure_irq = %d, nonsecure_irq = %d>\n",
+ *sec_irq, *nonsec_irq);
+ return 0;
+}
+
+int tegra_cbb_register_isr_enaberr(struct tegra_cbb *cbb)
+{
+ struct platform_device *pdev = cbb->pdev;
+ int ret = 0;
+
+ ret = tegra_cbb_err_dbgfs_init(cbb);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to create debugfs\n");
+ return ret;
+ }
+
+ /* register interrupt handler for errors due to different initiators */
+ ret = cbb->ops->cbb_intr_enable(cbb);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to register CBB Interrupt ISR");
+ return ret;
+ }
+
+ cbb->ops->cbb_err_enable(cbb);
+ dsb(sy);
+
+ return 0;
+}
diff --git a/drivers/soc/tegra/cbb/tegra194-cbb.c b/drivers/soc/tegra/cbb/tegra194-cbb.c
new file mode 100644
index 000000000000..740fc2a029f9
--- /dev/null
+++ b/drivers/soc/tegra/cbb/tegra194-cbb.c
@@ -0,0 +1,2261 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ *
+ * The driver handles Error's from Control Backbone(CBB) generated due to
+ * illegal accesses. When an error is reported from a NOC within CBB,
+ * the driver checks ErrVld status of all three Error Logger's of that NOC.
+ * It then prints debug information about failed transaction using ErrLog
+ * registers of error logger which has ErrVld set. Currently, SLV, DEC,
+ * TMO, SEC, UNS are the codes which are supported by CBB.
+ */
+
+#include <asm/cpufeature.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/version.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/tegra-cbb.h>
+#include <soc/tegra/tegra194-cbb.h>
+
+static LIST_HEAD(cbb_noc_list);
+static DEFINE_SPINLOCK(cbb_noc_lock);
+
+static const char *t194_cbb_trantype[] = {
+ "RD - Read, Incrementing",
+ "RDW - Read, Wrap", /* Not Supported */
+ "RDX - Exclusive Read", /* Not Supported */
+ "RDL - Linked Read", /* Not Supported */
+ "WR - Write, Incrementing",
+ "WRW - Write, Wrap", /* Not Supported */
+ "WRC - Exclusive Write", /* Not Supported */
+ "PRE - Preamble Sequence for Fixed Accesses"
+};
+
+static const char *t194_axi2apb_err[] = {
+ "SFIFONE - Status FIFO Not Empty interrupt",
+ "SFIFOF - Status FIFO Full interrupt",
+ "TIM - Timer(Timeout) interrupt",
+ "SLV - SLVERR interrupt",
+ "NULL",
+ "ERBF - Early response buffer Full interrupt",
+ "NULL",
+ "RDFIFOF - Read Response FIFO Full interrupt",
+ "WRFIFOF - Write Response FIFO Full interrupt",
+ "CH0DFIFOF - Ch0 Data FIFO Full interrupt",
+ "CH1DFIFOF - Ch1 Data FIFO Full interrupt",
+ "CH2DFIFOF - Ch2 Data FIFO Full interrupt",
+ "UAT - Unsupported alignment type error",
+ "UBS - Unsupported burst size error",
+ "UBE - Unsupported Byte Enable error",
+ "UBT - Unsupported burst type error",
+ "BFS - Block Firewall security error",
+ "ARFS - Address Range Firewall security error",
+ "CH0RFIFOF - Ch0 Request FIFO Full interrupt",
+ "CH1RFIFOF - Ch1 Request FIFO Full interrupt",
+ "CH2RFIFOF - Ch2 Request FIFO Full interrupt"
+};
+
+static const char *t194_master_id[] = {
+ "CCPLEX", /* 0x1 */
+ "CCPLEX_DPMU", /* 0x2 */
+ "BPMP", /* 0x3 */
+ "AON", /* 0x4 */
+ "SCE", /* 0x5 */
+ "GPCDMA_PERIPHERAL", /* 0x6 */
+ "TSECA", /* 0x7 */
+ "TSECB", /* 0x8 */
+ "JTAGM_DFT", /* 0x9 */
+ "CORESIGHT_AXIAP", /* 0xa */
+ "APE", /* 0xb */
+ "PEATR", /* 0xc */
+ "NVDEC", /* 0xd */
+ "RCE", /* 0xe */
+ "NVDEC1" /* 0xf */
+};
+
+static const struct tegra_noc_errors t194_noc_errors[] = {
+ {.errcode = "SLV",
+ .src = "Target",
+ .type = "Target error detected by CBB slave"
+ },
+ {.errcode = "DEC",
+ .src = "Initiator NIU",
+ .type = "Address decode error"
+ },
+ {.errcode = "UNS",
+ .src = "Target NIU",
+ .type = "Unsupported request. Not a valid transaction"
+ },
+ {.errcode = "DISC", /* Not Supported by CBB */
+ .src = "Power Disconnect",
+ .type = "Disconnected target or domain"
+ },
+ {.errcode = "SEC",
+ .src = "Initiator NIU or Firewall",
+ .type = "Security violation. Firewall error"
+ },
+ {.errcode = "HIDE", /* Not Supported by CBB */
+ .src = "Firewall",
+ .type = "Hidden security violation, reported as OK to initiator"
+ },
+ {.errcode = "TMO",
+ .src = "Target NIU",
+ .type = "Target time-out error"
+ },
+ {.errcode = "RSV",
+ .src = "None",
+ .type = "Reserved"
+ }
+};
+
+/*
+ * CBB NOC aperture lookup table as per file "cbb_central_noc_Structure.info".
+ */
+static char *t194_cbbcentralnoc_routeid_initflow[] = {
+ "aon_p2ps/I/aon", /* 0x0 */
+ "ape_p2ps/I/ape_p2ps", /* 0x1 */
+ "bpmp_p2ps/I/bpmp_p2ps", /* 0x2 */
+ "ccroc_p2ps/I/ccroc_p2ps", /* 0x3 */
+ "csite_p2ps/I/0", /* 0x4 */
+ "gpcdma_mmio_p2ps/I/0", /* 0x5 */
+ "jtag_p2ps/I/0", /* 0x6 */
+ "nvdec1_p2ps/I/0", /* 0x7 */
+ "nvdec_p2ps/I/0", /* 0x8 */
+ "rce_p2ps/I/rce_p2ps", /* 0x9 */
+ "sce_p2ps/I/sce_p2ps", /* 0xA */
+ "tseca_p2ps/I/0", /* 0xB */
+ "tsecb_p2ps/I/0", /* 0xC */
+ "RESERVED", /* 0xD */
+ "RESERVED", /* 0xE */
+ "RESERVED" /* 0xF */
+};
+
+static char *t194_cbbcentralnoc_routeid_targflow[] = {
+ "SVC/T/intreg", /*0x0*/
+ "axis_satellite_axi2apb_p2pm/T/axis_satellite_axi2apb_p2pm", /*0x1*/
+ "axis_satellite_grout/T/axis_satellite_grout", /*0x2*/
+ "cbb_firewall/T/cbb_firewall", /*0x3*/
+ "gpu_p2pm/T/gpu_p2pm", /*0x4*/
+ "host1x_p2pm/T/host1x_p2pm", /*0x5*/
+ "sapb_3_p2pm/T/sapb_3_p2pm", /*0x6*/
+ "smmu0_p2pm/T/smmu0_p2pm", /*0x7*/
+ "smmu1_p2pm/T/smmu1_p2pm", /*0x8*/
+ "smmu2_p2pm/T/smmu2_p2pm", /*0x9*/
+ "stm_p2pm/T/stm_p2pm", /*0xA*/
+ "RESERVED", /*0xB*/
+ "RESERVED", /*0xC*/
+ "RESERVED", /*0xD*/
+ "RESERVED", /*0xE*/
+ "RESERVED" /*0xF*/
+};
+
+/*
+ * Fields of CBB NOC lookup table:
+ * Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
+ * Targ mapping, Targ localAddress
+ * ----------------------------------------------------------------------------
+ */
+static const struct tegra194_cbb_aperture t194_cbbcentralnoc_apert_lookup[] = {
+ { 0x0, 0x0, 0x00, 0x0, 0x02300000, 0, 0x0 },
+ { 0x0, 0x1, 0x00, 0x0, 0x02003000, 0, 0x02003000 },
+ { 0x0, 0x1, 0x01, 0x0, 0x02006000, 2, 0x02006000 },
+ { 0x0, 0x1, 0x02, 0x0, 0x02016000, 3, 0x02016000 },
+ { 0x0, 0x1, 0x03, 0x0, 0x0201d000, 4, 0x0201d000 },
+ { 0x0, 0x1, 0x04, 0x0, 0x0202b000, 6, 0x0202b000 },
+ { 0x0, 0x1, 0x05, 0x0, 0x02434000, 20, 0x02434000 },
+ { 0x0, 0x1, 0x06, 0x0, 0x02436000, 21, 0x02436000 },
+ { 0x0, 0x1, 0x07, 0x0, 0x02438000, 22, 0x02438000 },
+ { 0x0, 0x1, 0x08, 0x0, 0x02445000, 24, 0x02445000 },
+ { 0x0, 0x1, 0x09, 0x0, 0x02446000, 25, 0x02446000 },
+ { 0x0, 0x1, 0x0a, 0x0, 0x02004000, 1, 0x02004000 },
+ { 0x0, 0x1, 0x0b, 0x0, 0x0201e000, 5, 0x0201e000 },
+ { 0x0, 0x1, 0x0c, 0x0, 0x0202c000, 7, 0x0202c000 },
+ { 0x0, 0x1, 0x0d, 0x0, 0x02204000, 8, 0x02204000 },
+ { 0x0, 0x1, 0x0e, 0x0, 0x02214000, 9, 0x02214000 },
+ { 0x0, 0x1, 0x0f, 0x0, 0x02224000, 10, 0x02224000 },
+ { 0x0, 0x1, 0x10, 0x0, 0x02234000, 11, 0x02234000 },
+ { 0x0, 0x1, 0x11, 0x0, 0x02244000, 12, 0x02244000 },
+ { 0x0, 0x1, 0x12, 0x0, 0x02254000, 13, 0x02254000 },
+ { 0x0, 0x1, 0x13, 0x0, 0x02264000, 14, 0x02264000 },
+ { 0x0, 0x1, 0x14, 0x0, 0x02274000, 15, 0x02274000 },
+ { 0x0, 0x1, 0x15, 0x0, 0x02284000, 16, 0x02284000 },
+ { 0x0, 0x1, 0x16, 0x0, 0x0243a000, 23, 0x0243a000 },
+ { 0x0, 0x1, 0x17, 0x0, 0x02370000, 17, 0x02370000 },
+ { 0x0, 0x1, 0x18, 0x0, 0x023d0000, 18, 0x023d0000 },
+ { 0x0, 0x1, 0x19, 0x0, 0x023e0000, 19, 0x023e0000 },
+ { 0x0, 0x1, 0x1a, 0x0, 0x02450000, 26, 0x02450000 },
+ { 0x0, 0x1, 0x1b, 0x0, 0x02460000, 27, 0x02460000 },
+ { 0x0, 0x1, 0x1c, 0x0, 0x02490000, 28, 0x02490000 },
+ { 0x0, 0x1, 0x1d, 0x0, 0x03130000, 31, 0x03130000 },
+ { 0x0, 0x1, 0x1e, 0x0, 0x03160000, 32, 0x03160000 },
+ { 0x0, 0x1, 0x1f, 0x0, 0x03270000, 33, 0x03270000 },
+ { 0x0, 0x1, 0x20, 0x0, 0x032e0000, 35, 0x032e0000 },
+ { 0x0, 0x1, 0x21, 0x0, 0x03300000, 36, 0x03300000 },
+ { 0x0, 0x1, 0x22, 0x0, 0x13090000, 40, 0x13090000 },
+ { 0x0, 0x1, 0x23, 0x0, 0x20120000, 43, 0x20120000 },
+ { 0x0, 0x1, 0x24, 0x0, 0x20170000, 44, 0x20170000 },
+ { 0x0, 0x1, 0x25, 0x0, 0x20190000, 45, 0x20190000 },
+ { 0x0, 0x1, 0x26, 0x0, 0x201b0000, 46, 0x201b0000 },
+ { 0x0, 0x1, 0x27, 0x0, 0x20250000, 47, 0x20250000 },
+ { 0x0, 0x1, 0x28, 0x0, 0x20260000, 48, 0x20260000 },
+ { 0x0, 0x1, 0x29, 0x0, 0x20420000, 49, 0x20420000 },
+ { 0x0, 0x1, 0x2a, 0x0, 0x20460000, 50, 0x20460000 },
+ { 0x0, 0x1, 0x2b, 0x0, 0x204f0000, 51, 0x204f0000 },
+ { 0x0, 0x1, 0x2c, 0x0, 0x20520000, 52, 0x20520000 },
+ { 0x0, 0x1, 0x2d, 0x0, 0x20580000, 53, 0x20580000 },
+ { 0x0, 0x1, 0x2e, 0x0, 0x205a0000, 54, 0x205a0000 },
+ { 0x0, 0x1, 0x2f, 0x0, 0x205c0000, 55, 0x205c0000 },
+ { 0x0, 0x1, 0x30, 0x0, 0x20690000, 56, 0x20690000 },
+ { 0x0, 0x1, 0x31, 0x0, 0x20770000, 57, 0x20770000 },
+ { 0x0, 0x1, 0x32, 0x0, 0x20790000, 58, 0x20790000 },
+ { 0x0, 0x1, 0x33, 0x0, 0x20880000, 59, 0x20880000 },
+ { 0x0, 0x1, 0x34, 0x0, 0x20990000, 62, 0x20990000 },
+ { 0x0, 0x1, 0x35, 0x0, 0x20e10000, 65, 0x20e10000 },
+ { 0x0, 0x1, 0x36, 0x0, 0x20e70000, 66, 0x20e70000 },
+ { 0x0, 0x1, 0x37, 0x0, 0x20e80000, 67, 0x20e80000 },
+ { 0x0, 0x1, 0x38, 0x0, 0x20f30000, 68, 0x20f30000 },
+ { 0x0, 0x1, 0x39, 0x0, 0x20f50000, 69, 0x20f50000 },
+ { 0x0, 0x1, 0x3a, 0x0, 0x20fc0000, 70, 0x20fc0000 },
+ { 0x0, 0x1, 0x3b, 0x0, 0x21110000, 72, 0x21110000 },
+ { 0x0, 0x1, 0x3c, 0x0, 0x21270000, 73, 0x21270000 },
+ { 0x0, 0x1, 0x3d, 0x0, 0x21290000, 74, 0x21290000 },
+ { 0x0, 0x1, 0x3e, 0x0, 0x21840000, 75, 0x21840000 },
+ { 0x0, 0x1, 0x3f, 0x0, 0x21880000, 76, 0x21880000 },
+ { 0x0, 0x1, 0x40, 0x0, 0x218d0000, 77, 0x218d0000 },
+ { 0x0, 0x1, 0x41, 0x0, 0x21950000, 78, 0x21950000 },
+ { 0x0, 0x1, 0x42, 0x0, 0x21960000, 79, 0x21960000 },
+ { 0x0, 0x1, 0x43, 0x0, 0x21a10000, 80, 0x21a10000 },
+ { 0x0, 0x1, 0x44, 0x0, 0x024a0000, 29, 0x024a0000 },
+ { 0x0, 0x1, 0x45, 0x0, 0x024c0000, 30, 0x024c0000 },
+ { 0x0, 0x1, 0x46, 0x0, 0x032c0000, 34, 0x032c0000 },
+ { 0x0, 0x1, 0x47, 0x0, 0x03400000, 37, 0x03400000 },
+ { 0x0, 0x1, 0x48, 0x0, 0x130a0000, 41, 0x130a0000 },
+ { 0x0, 0x1, 0x49, 0x0, 0x130c0000, 42, 0x130c0000 },
+ { 0x0, 0x1, 0x4a, 0x0, 0x208a0000, 60, 0x208a0000 },
+ { 0x0, 0x1, 0x4b, 0x0, 0x208c0000, 61, 0x208c0000 },
+ { 0x0, 0x1, 0x4c, 0x0, 0x209a0000, 63, 0x209a0000 },
+ { 0x0, 0x1, 0x4d, 0x0, 0x21a40000, 81, 0x21a40000 },
+ { 0x0, 0x1, 0x4e, 0x0, 0x03440000, 38, 0x03440000 },
+ { 0x0, 0x1, 0x4f, 0x0, 0x20d00000, 64, 0x20d00000 },
+ { 0x0, 0x1, 0x50, 0x0, 0x21000000, 71, 0x21000000 },
+ { 0x0, 0x1, 0x51, 0x0, 0x0b000000, 39, 0x0b000000 },
+ { 0x0, 0x2, 0x00, 0x0, 0x00000000, 0, 0x00000000 },
+ { 0x0, 0x3, 0x00, 0x0, 0x02340000, 0, 0x00000000 },
+ { 0x0, 0x4, 0x00, 0x0, 0x17000000, 0, 0x17000000 },
+ { 0x0, 0x4, 0x01, 0x0, 0x18000000, 1, 0x18000000 },
+ { 0x0, 0x5, 0x00, 0x0, 0x13e80000, 1, 0x13e80000 },
+ { 0x0, 0x5, 0x01, 0x0, 0x15810000, 12, 0x15810000 },
+ { 0x0, 0x5, 0x02, 0x0, 0x15840000, 14, 0x15840000 },
+ { 0x0, 0x5, 0x03, 0x0, 0x15a40000, 17, 0x15a40000 },
+ { 0x0, 0x5, 0x04, 0x0, 0x13f00000, 3, 0x13f00000 },
+ { 0x0, 0x5, 0x05, 0x0, 0x15820000, 13, 0x15820000 },
+ { 0x0, 0x5, 0x06, 0x0, 0x13ec0000, 2, 0x13ec0000 },
+ { 0x0, 0x5, 0x07, 0x0, 0x15200000, 6, 0x15200000 },
+ { 0x0, 0x5, 0x08, 0x0, 0x15340000, 7, 0x15340000 },
+ { 0x0, 0x5, 0x09, 0x0, 0x15380000, 8, 0x15380000 },
+ { 0x0, 0x5, 0x0a, 0x0, 0x15500000, 10, 0x15500000 },
+ { 0x0, 0x5, 0x0b, 0x0, 0x155c0000, 11, 0x155c0000 },
+ { 0x0, 0x5, 0x0c, 0x0, 0x15a00000, 16, 0x15a00000 },
+ { 0x0, 0x5, 0x0d, 0x0, 0x13e00000, 0, 0x13e00000 },
+ { 0x0, 0x5, 0x0e, 0x0, 0x15100000, 5, 0x15100000 },
+ { 0x0, 0x5, 0x0f, 0x0, 0x15480000, 9, 0x15480000 },
+ { 0x0, 0x5, 0x10, 0x0, 0x15880000, 15, 0x15880000 },
+ { 0x0, 0x5, 0x11, 0x0, 0x15a80000, 18, 0x15a80000 },
+ { 0x0, 0x5, 0x12, 0x0, 0x15b00000, 19, 0x15b00000 },
+ { 0x0, 0x5, 0x13, 0x0, 0x14800000, 4, 0x14800000 },
+ { 0x0, 0x5, 0x14, 0x0, 0x15c00000, 20, 0x15c00000 },
+ { 0x0, 0x5, 0x15, 0x0, 0x16000000, 21, 0x16000000 },
+ { 0x0, 0x6, 0x00, 0x0, 0x02000000, 4, 0x02000000 },
+ { 0x0, 0x6, 0x01, 0x0, 0x02007000, 5, 0x02007000 },
+ { 0x0, 0x6, 0x02, 0x0, 0x02008000, 6, 0x02008000 },
+ { 0x0, 0x6, 0x03, 0x0, 0x02013000, 7, 0x02013000 },
+ { 0x0, 0x6, 0x04, 0x0, 0x0201c000, 8, 0x0201c000 },
+ { 0x0, 0x6, 0x05, 0x0, 0x02020000, 9, 0x02020000 },
+ { 0x0, 0x6, 0x06, 0x0, 0x0202a000, 10, 0x0202a000 },
+ { 0x0, 0x6, 0x07, 0x0, 0x0202e000, 11, 0x0202e000 },
+ { 0x0, 0x6, 0x08, 0x0, 0x06400000, 33, 0x06400000 },
+ { 0x0, 0x6, 0x09, 0x0, 0x02038000, 12, 0x02038000 },
+ { 0x0, 0x6, 0x0a, 0x0, 0x00100000, 0, 0x00100000 },
+ { 0x0, 0x6, 0x0b, 0x0, 0x023b0000, 13, 0x023b0000 },
+ { 0x0, 0x6, 0x0c, 0x0, 0x02800000, 16, 0x02800000 },
+ { 0x0, 0x6, 0x0d, 0x0, 0x030e0000, 22, 0x030e0000 },
+ { 0x0, 0x6, 0x0e, 0x0, 0x03800000, 23, 0x03800000 },
+ { 0x0, 0x6, 0x0f, 0x0, 0x03980000, 25, 0x03980000 },
+ { 0x0, 0x6, 0x10, 0x0, 0x03a60000, 26, 0x03a60000 },
+ { 0x0, 0x6, 0x11, 0x0, 0x03d80000, 31, 0x03d80000 },
+ { 0x0, 0x6, 0x12, 0x0, 0x20000000, 36, 0x20000000 },
+ { 0x0, 0x6, 0x13, 0x0, 0x20050000, 38, 0x20050000 },
+ { 0x0, 0x6, 0x14, 0x0, 0x201e0000, 40, 0x201e0000 },
+ { 0x0, 0x6, 0x15, 0x0, 0x20280000, 42, 0x20280000 },
+ { 0x0, 0x6, 0x16, 0x0, 0x202c0000, 43, 0x202c0000 },
+ { 0x0, 0x6, 0x17, 0x0, 0x20390000, 44, 0x20390000 },
+ { 0x0, 0x6, 0x18, 0x0, 0x20430000, 45, 0x20430000 },
+ { 0x0, 0x6, 0x19, 0x0, 0x20440000, 46, 0x20440000 },
+ { 0x0, 0x6, 0x1a, 0x0, 0x204e0000, 47, 0x204e0000 },
+ { 0x0, 0x6, 0x1b, 0x0, 0x20550000, 48, 0x20550000 },
+ { 0x0, 0x6, 0x1c, 0x0, 0x20570000, 49, 0x20570000 },
+ { 0x0, 0x6, 0x1d, 0x0, 0x20590000, 50, 0x20590000 },
+ { 0x0, 0x6, 0x1e, 0x0, 0x20730000, 52, 0x20730000 },
+ { 0x0, 0x6, 0x1f, 0x0, 0x209f0000, 54, 0x209f0000 },
+ { 0x0, 0x6, 0x20, 0x0, 0x20e20000, 55, 0x20e20000 },
+ { 0x0, 0x6, 0x21, 0x0, 0x20ed0000, 56, 0x20ed0000 },
+ { 0x0, 0x6, 0x22, 0x0, 0x20fd0000, 57, 0x20fd0000 },
+ { 0x0, 0x6, 0x23, 0x0, 0x21120000, 59, 0x21120000 },
+ { 0x0, 0x6, 0x24, 0x0, 0x211a0000, 60, 0x211a0000 },
+ { 0x0, 0x6, 0x25, 0x0, 0x21850000, 61, 0x21850000 },
+ { 0x0, 0x6, 0x26, 0x0, 0x21860000, 62, 0x21860000 },
+ { 0x0, 0x6, 0x27, 0x0, 0x21890000, 63, 0x21890000 },
+ { 0x0, 0x6, 0x28, 0x0, 0x21970000, 64, 0x21970000 },
+ { 0x0, 0x6, 0x29, 0x0, 0x21990000, 65, 0x21990000 },
+ { 0x0, 0x6, 0x2a, 0x0, 0x21a00000, 66, 0x21a00000 },
+ { 0x0, 0x6, 0x2b, 0x0, 0x21a90000, 68, 0x21a90000 },
+ { 0x0, 0x6, 0x2c, 0x0, 0x21ac0000, 70, 0x21ac0000 },
+ { 0x0, 0x6, 0x2d, 0x0, 0x01f80000, 3, 0x01f80000 },
+ { 0x0, 0x6, 0x2e, 0x0, 0x024e0000, 14, 0x024e0000 },
+ { 0x0, 0x6, 0x2f, 0x0, 0x030c0000, 21, 0x030c0000 },
+ { 0x0, 0x6, 0x30, 0x0, 0x03820000, 24, 0x03820000 },
+ { 0x0, 0x6, 0x31, 0x0, 0x03aa0000, 27, 0x03aa0000 },
+ { 0x0, 0x6, 0x32, 0x0, 0x03c80000, 29, 0x03c80000 },
+ { 0x0, 0x6, 0x33, 0x0, 0x130e0000, 34, 0x130e0000 },
+ { 0x0, 0x6, 0x34, 0x0, 0x20020000, 37, 0x20020000 },
+ { 0x0, 0x6, 0x35, 0x0, 0x20060000, 39, 0x20060000 },
+ { 0x0, 0x6, 0x36, 0x0, 0x20200000, 41, 0x20200000 },
+ { 0x0, 0x6, 0x37, 0x0, 0x206a0000, 51, 0x206a0000 },
+ { 0x0, 0x6, 0x38, 0x0, 0x20740000, 53, 0x20740000 },
+ { 0x0, 0x6, 0x39, 0x0, 0x20fe0000, 58, 0x20fe0000 },
+ { 0x0, 0x6, 0x3a, 0x0, 0x21a20000, 67, 0x21a20000 },
+ { 0x0, 0x6, 0x3b, 0x0, 0x21aa0000, 69, 0x21aa0000 },
+ { 0x0, 0x6, 0x3c, 0x0, 0x02b80000, 17, 0x02b80000 },
+ { 0x0, 0x6, 0x3d, 0x0, 0x03080000, 20, 0x03080000 },
+ { 0x0, 0x6, 0x3e, 0x0, 0x13100000, 35, 0x13100000 },
+ { 0x0, 0x6, 0x3f, 0x0, 0x01f00000, 2, 0x01f00000 },
+ { 0x0, 0x6, 0x40, 0x0, 0x03000000, 19, 0x03000000 },
+ { 0x0, 0x6, 0x41, 0x0, 0x03c00000, 28, 0x03c00000 },
+ { 0x0, 0x6, 0x42, 0x0, 0x03d00000, 30, 0x03d00000 },
+ { 0x0, 0x6, 0x43, 0x0, 0x01700000, 1, 0x01700000 },
+ { 0x0, 0x6, 0x44, 0x0, 0x02c00000, 18, 0x02c00000 },
+ { 0x0, 0x6, 0x45, 0x0, 0x02600000, 15, 0x02600000 },
+ { 0x0, 0x6, 0x46, 0x0, 0x06000000, 32, 0x06000000 },
+ { 0x0, 0x6, 0x47, 0x0, 0x24000000, 71, 0x24000000 },
+ { 0x0, 0x7, 0x00, 0x0, 0x12000000, 0, 0x12000000 },
+ { 0x0, 0x8, 0x00, 0x0, 0x11000000, 0, 0x11000000 },
+ { 0x0, 0x9, 0x00, 0x0, 0x10000000, 0, 0x10000000 },
+ { 0x0, 0xA, 0x00, 0x0, 0x22000000, 0, 0x22000000 }
+};
+
+/*
+ * BPMP NOC aperture lookup table as per file "BPMP_NOC_Structure.info".
+ */
+static char *t194_bpmpnoc_routeid_initflow[] = {
+ "cbb_i/I/0", /* 0x0 */
+ "cpu_m_i/I/0", /* 0x1 */
+ "cpu_p_i/I/0", /* 0x2 */
+ "cvc_i/I/0", /* 0x3 */
+ "dma_m_i/I/0", /* 0x4 */
+ "dma_p_i/I/0", /* 0x5 */
+ "RESERVED", /* 0x6 */
+ "RESERVED" /* 0x6 */
+};
+
+static char *t194_bpmpnoc_routeid_targflow[] = {
+ "multiport0_t/T/actmon", /* 0x0 */
+ "multiport0_t/T/ast_0", /* 0x1 */
+ "multiport0_t/T/ast_1", /* 0x2 */
+ "multiport0_t/T/atcm_cfg", /* 0x3 */
+ "multiport0_t/T/car", /* 0x4 */
+ "multiport0_t/T/central_pwr_mgr", /* 0x5 */
+ "multiport0_t/T/central_vtg_ctlr", /* 0x6 */
+ "multiport0_t/T/cfg", /* 0x7 */
+ "multiport0_t/T/dma", /* 0x8 */
+ "multiport0_t/T/err_collator", /* 0x9 */
+ "multiport0_t/T/err_collator_car", /* 0xA */
+ "multiport0_t/T/fpga_misc", /* 0xB */
+ "multiport0_t/T/fpga_uart", /* 0xC */
+ "multiport0_t/T/gte", /* 0xD */
+ "multiport0_t/T/hsp", /* 0xE */
+ "multiport0_t/T/misc", /* 0xF */
+ "multiport0_t/T/pm", /* 0x10 */
+ "multiport0_t/T/simon0", /* 0x11 */
+ "multiport0_t/T/simon1", /* 0x12 */
+ "multiport0_t/T/simon2", /* 0x13 */
+ "multiport0_t/T/simon3", /* 0x14 */
+ "multiport0_t/T/simon4", /* 0x15 */
+ "multiport0_t/T/soc_therm", /* 0x16 */
+ "multiport0_t/T/tke", /* 0x17 */
+ "multiport0_t/T/vic_0", /* 0x18 */
+ "multiport0_t/T/vic_1", /* 0x19 */
+ "ast0_t/T/0", /* 0x1A */
+ "ast1_t/T/0", /* 0x1B */
+ "bpmp_noc_firewall/T/0", /* 0x1C */
+ "cbb_t/T/0", /* 0x1D */
+ "cpu_t/T/0", /* 0x1E */
+ "svc_t/T/0" /* 0x1F */
+};
+
+/*
+ * Fields of BPMP NOC lookup table:
+ * Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
+ * Targ mapping, Targ localAddress
+ * ----------------------------------------------------------------------------
+ */
+static const struct tegra194_cbb_aperture t194_bpmpnoc_apert_lookup[] = {
+ { 0x0, 0x1C, 0x0, 0x0, 0xd640000, 0, 0x0000000 },
+ { 0x0, 0x1E, 0x0, 0x0, 0xd400000, 0, 0xd400000 },
+ { 0x0, 0x00, 0x0, 0x0, 0xd230000, 0, 0x0000000 },
+ { 0x0, 0x01, 0x0, 0x0, 0xd040000, 0, 0x0000000 },
+ { 0x0, 0x02, 0x0, 0x0, 0xd050000, 0, 0x0000000 },
+ { 0x0, 0x03, 0x0, 0x0, 0xd000000, 0, 0x0000000 },
+ { 0x0, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0xe0000 },
+ { 0x0, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0xc0000 },
+ { 0x0, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x80000 },
+ { 0x0, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x0000000 },
+ { 0x0, 0x05, 0x0, 0x0, 0xd2a0000, 0, 0x0000000 },
+ { 0x0, 0x06, 0x0, 0x0, 0xd290000, 0, 0x0000000 },
+ { 0x0, 0x07, 0x0, 0x0, 0xd2c0000, 0, 0x0000000 },
+ { 0x0, 0x08, 0x0, 0x0, 0xd0e0000, 4, 0x80000 },
+ { 0x0, 0x08, 0x1, 0x0, 0xd060000, 0, 0x0000000 },
+ { 0x0, 0x08, 0x2, 0x0, 0xd080000, 1, 0x20000 },
+ { 0x0, 0x08, 0x3, 0x0, 0xd0a0000, 2, 0x40000 },
+ { 0x0, 0x08, 0x4, 0x0, 0xd0c0000, 3, 0x60000 },
+ { 0x0, 0x09, 0x0, 0x0, 0xd650000, 0, 0x0000000 },
+ { 0x0, 0x0A, 0x0, 0x0, 0x20af0000, 0, 0x0000000 },
+ { 0x0, 0x0B, 0x0, 0x0, 0xd3e0000, 0, 0x0000000 },
+ { 0x0, 0x0C, 0x0, 0x0, 0xd3d0000, 0, 0x0000000 },
+ { 0x0, 0x0D, 0x0, 0x0, 0xd1e0000, 0, 0x0000000 },
+ { 0x0, 0x0E, 0x0, 0x0, 0xd150000, 0, 0x0000000 },
+ { 0x0, 0x0E, 0x1, 0x0, 0xd160000, 1, 0x10000 },
+ { 0x0, 0x0E, 0x2, 0x0, 0xd170000, 2, 0x20000 },
+ { 0x0, 0x0E, 0x3, 0x0, 0xd180000, 3, 0x30000 },
+ { 0x0, 0x0E, 0x4, 0x0, 0xd190000, 4, 0x40000 },
+ { 0x0, 0x0E, 0x5, 0x0, 0xd1a0000, 5, 0x50000 },
+ { 0x0, 0x0E, 0x6, 0x0, 0xd1b0000, 6, 0x60000 },
+ { 0x0, 0x0E, 0x7, 0x0, 0xd1c0000, 7, 0x70000 },
+ { 0x0, 0x0E, 0x8, 0x0, 0xd1d0000, 8, 0x80000 },
+ { 0x0, 0x0F, 0x0, 0x0, 0xd660000, 0, 0x0000000 },
+ { 0x0, 0x10, 0x0, 0x0, 0xd1f0000, 0, 0x0000000 },
+ { 0x0, 0x10, 0x1, 0x0, 0xd200000, 1, 0x10000 },
+ { 0x0, 0x10, 0x2, 0x0, 0xd210000, 2, 0x20000 },
+ { 0x0, 0x10, 0x3, 0x0, 0xd220000, 3, 0x30000 },
+ { 0x0, 0x11, 0x0, 0x0, 0xd240000, 0, 0x0000000 },
+ { 0x0, 0x12, 0x0, 0x0, 0xd250000, 0, 0x0000000 },
+ { 0x0, 0x13, 0x0, 0x0, 0xd260000, 0, 0x0000000 },
+ { 0x0, 0x14, 0x0, 0x0, 0xd270000, 0, 0x0000000 },
+ { 0x0, 0x15, 0x0, 0x0, 0xd2b0000, 0, 0x0000000 },
+ { 0x0, 0x16, 0x0, 0x0, 0xd280000, 0, 0x0000000 },
+ { 0x0, 0x17, 0x0, 0x0, 0xd0f0000, 0, 0x0000000 },
+ { 0x0, 0x17, 0x1, 0x0, 0xd100000, 1, 0x10000 },
+ { 0x0, 0x17, 0x2, 0x0, 0xd110000, 2, 0x20000 },
+ { 0x0, 0x17, 0x3, 0x0, 0xd120000, 3, 0x30000 },
+ { 0x0, 0x17, 0x4, 0x0, 0xd130000, 4, 0x40000 },
+ { 0x0, 0x17, 0x5, 0x0, 0xd140000, 5, 0x50000 },
+ { 0x0, 0x18, 0x0, 0x0, 0xd020000, 0, 0x0000000 },
+ { 0x0, 0x19, 0x0, 0x0, 0xd030000, 0, 0x0000000 },
+ { 0x0, 0x1F, 0x0, 0x0, 0xd600000, 0, 0x0000000 },
+ { 0x0, 0x1F, 0x1, 0x0, 0x0, 0, 0x0000000 },
+ { 0x1, 0x1A, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
+ { 0x1, 0x1A, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
+ { 0x1, 0x1A, 0x2, 0x0, 0x0, 0, 0x0000000 },
+ { 0x2, 0x1C, 0x0, 0x0, 0xd640000, 0, 0x0000000 },
+ { 0x2, 0x1D, 0x0, 0x0, 0x20b00000, 8, 0x20b00000 },
+ { 0x2, 0x1D, 0x1, 0x0, 0x20800000, 7, 0x20800000 },
+ { 0x2, 0x1D, 0x2, 0x0, 0x20c00000, 9, 0x20c00000 },
+ { 0x2, 0x1D, 0x3, 0x0, 0xd800000, 3, 0xd800000 },
+ { 0x2, 0x1D, 0x4, 0x0, 0x20000000, 6, 0x20000000 },
+ { 0x2, 0x1D, 0x5, 0x0, 0xc000000, 2, 0xc000000 },
+ { 0x2, 0x1D, 0x6, 0x0, 0x21000000, 10, 0x21000000 },
+ { 0x2, 0x1D, 0x7, 0x0, 0xe000000, 4, 0xe000000 },
+ { 0x2, 0x1D, 0x8, 0x0, 0x22000000, 11, 0x22000000 },
+ { 0x2, 0x1D, 0x9, 0x0, 0x8000000, 1, 0x8000000 },
+ { 0x2, 0x1D, 0xa, 0x0, 0x24000000, 12, 0x24000000 },
+ { 0x2, 0x1D, 0xb, 0x0, 0x0, 0, 0x0000000 },
+ { 0x2, 0x1D, 0xc, 0x0, 0x28000000, 13, 0x28000000 },
+ { 0x2, 0x1D, 0xd, 0x0, 0x10000000, 5, 0x10000000 },
+ { 0x2, 0x1D, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
+ { 0x2, 0x00, 0x0, 0x0, 0xd230000, 0, 0x0000000 },
+ { 0x2, 0x01, 0x0, 0x0, 0xd040000, 0, 0x0000000 },
+ { 0x2, 0x02, 0x0, 0x0, 0xd050000, 0, 0x0000000 },
+ { 0x2, 0x03, 0x0, 0x0, 0xd000000, 0, 0x0000000 },
+ { 0x2, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0xe0000 },
+ { 0x2, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0xc0000 },
+ { 0x2, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x80000 },
+ { 0x2, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x0000000 },
+ { 0x2, 0x05, 0x0, 0x0, 0xd2a0000, 0, 0x0000000 },
+ { 0x2, 0x06, 0x0, 0x0, 0xd290000, 0, 0x0000000 },
+ { 0x2, 0x07, 0x0, 0x0, 0xd2c0000, 0, 0x0000000 },
+ { 0x2, 0x08, 0x0, 0x0, 0xd0e0000, 4, 0x80000 },
+ { 0x2, 0x08, 0x1, 0x0, 0xd060000, 0, 0x0000000 },
+ { 0x2, 0x08, 0x2, 0x0, 0xd080000, 1, 0x20000 },
+ { 0x2, 0x08, 0x3, 0x0, 0xd0a0000, 2, 0x40000 },
+ { 0x2, 0x08, 0x4, 0x0, 0xd0c0000, 3, 0x60000 },
+ { 0x2, 0x09, 0x0, 0x0, 0xd650000, 0, 0x0000000 },
+ { 0x2, 0x0A, 0x0, 0x0, 0x20af0000, 0, 0x0000000 },
+ { 0x2, 0x0B, 0x0, 0x0, 0xd3e0000, 0, 0x0000000 },
+ { 0x2, 0x0C, 0x0, 0x0, 0xd3d0000, 0, 0x0000000 },
+ { 0x2, 0x0D, 0x0, 0x0, 0xd1e0000, 0, 0x0000000 },
+ { 0x2, 0x0E, 0x0, 0x0, 0xd150000, 0, 0x0000000 },
+ { 0x2, 0x0E, 0x1, 0x0, 0xd160000, 1, 0x10000 },
+ { 0x2, 0x0E, 0x2, 0x0, 0xd170000, 2, 0x20000 },
+ { 0x2, 0x0E, 0x3, 0x0, 0xd180000, 3, 0x30000 },
+ { 0x2, 0x0E, 0x4, 0x0, 0xd190000, 4, 0x40000 },
+ { 0x2, 0x0E, 0x5, 0x0, 0xd1a0000, 5, 0x50000 },
+ { 0x2, 0x0E, 0x6, 0x0, 0xd1b0000, 6, 0x60000 },
+ { 0x2, 0x0E, 0x7, 0x0, 0xd1c0000, 7, 0x70000 },
+ { 0x2, 0x0E, 0x8, 0x0, 0xd1d0000, 8, 0x80000 },
+ { 0x2, 0x0F, 0x0, 0x0, 0xd660000, 0, 0x0000000 },
+ { 0x2, 0x10, 0x0, 0x0, 0xd1f0000, 0, 0x0000000 },
+ { 0x2, 0x10, 0x1, 0x0, 0xd200000, 1, 0x10000 },
+ { 0x2, 0x10, 0x2, 0x0, 0xd210000, 2, 0x20000 },
+ { 0x2, 0x10, 0x3, 0x0, 0xd220000, 3, 0x30000 },
+ { 0x2, 0x11, 0x0, 0x0, 0xd240000, 0, 0x0000000 },
+ { 0x2, 0x12, 0x0, 0x0, 0xd250000, 0, 0x0000000 },
+ { 0x2, 0x13, 0x0, 0x0, 0xd260000, 0, 0x0000000 },
+ { 0x2, 0x14, 0x0, 0x0, 0xd270000, 0, 0x0000000 },
+ { 0x2, 0x15, 0x0, 0x0, 0xd2b0000, 0, 0x0000000 },
+ { 0x2, 0x16, 0x0, 0x0, 0xd280000, 0, 0x0000000 },
+ { 0x2, 0x17, 0x0, 0x0, 0xd0f0000, 0, 0x0000000 },
+ { 0x2, 0x17, 0x1, 0x0, 0xd100000, 1, 0x10000 },
+ { 0x2, 0x17, 0x2, 0x0, 0xd110000, 2, 0x20000 },
+ { 0x2, 0x17, 0x3, 0x0, 0xd120000, 3, 0x30000 },
+ { 0x2, 0x17, 0x4, 0x0, 0xd130000, 4, 0x40000 },
+ { 0x2, 0x17, 0x5, 0x0, 0xd140000, 5, 0x50000 },
+ { 0x2, 0x18, 0x0, 0x0, 0xd020000, 0, 0x0000000 },
+ { 0x2, 0x19, 0x0, 0x0, 0xd030000, 0, 0x0000000 },
+ { 0x2, 0x1F, 0x0, 0x0, 0xd600000, 0, 0x0000000 },
+ { 0x2, 0x1F, 0x1, 0x0, 0x0, 0, 0x0000000 },
+ { 0x3, 0x1B, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
+ { 0x3, 0x1B, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
+ { 0x3, 0x1C, 0x0, 0x2, 0xd640000, 0, 0x0000000 },
+ { 0x3, 0x1D, 0x0, 0x2, 0x20b00000, 8, 0x20b00000 },
+ { 0x3, 0x1D, 0x1, 0x2, 0x20800000, 7, 0x20800000 },
+ { 0x3, 0x1D, 0x2, 0x2, 0x20c00000, 9, 0x20c00000 },
+ { 0x3, 0x1D, 0x3, 0x2, 0xd800000, 3, 0xd800000 },
+ { 0x3, 0x1D, 0x4, 0x2, 0x20000000, 6, 0x20000000 },
+ { 0x3, 0x1D, 0x5, 0x2, 0xc000000, 2, 0xc000000 },
+ { 0x3, 0x1D, 0x6, 0x2, 0x21000000, 10, 0x21000000 },
+ { 0x3, 0x1D, 0x7, 0x2, 0xe000000, 4, 0xe000000 },
+ { 0x3, 0x1D, 0x8, 0x2, 0x22000000, 11, 0x22000000 },
+ { 0x3, 0x1D, 0x9, 0x2, 0x8000000, 1, 0x8000000 },
+ { 0x3, 0x1D, 0xa, 0x2, 0x24000000, 12, 0x24000000 },
+ { 0x3, 0x1D, 0xb, 0x2, 0x0, 0, 0x0000000 },
+ { 0x3, 0x1D, 0xc, 0x2, 0x28000000, 13, 0x28000000 },
+ { 0x3, 0x1D, 0xd, 0x2, 0x10000000, 5, 0x10000000 },
+ { 0x3, 0x1D, 0xe, 0x2, 0x30000000, 14, 0x30000000 },
+ { 0x3, 0x1E, 0x0, 0x2, 0xd400000, 0, 0xd400000 },
+ { 0x3, 0x00, 0x0, 0x2, 0xd230000, 0, 0x0000000 },
+ { 0x3, 0x01, 0x0, 0x2, 0xd040000, 0, 0x0000000 },
+ { 0x3, 0x02, 0x0, 0x2, 0xd050000, 0, 0x0000000 },
+ { 0x3, 0x03, 0x0, 0x2, 0xd000000, 0, 0x0000000 },
+ { 0x3, 0x04, 0x0, 0x2, 0x20ae0000, 3, 0xe0000 },
+ { 0x3, 0x04, 0x1, 0x2, 0x20ac0000, 2, 0xc0000 },
+ { 0x3, 0x04, 0x2, 0x2, 0x20a80000, 1, 0x80000 },
+ { 0x3, 0x04, 0x3, 0x2, 0x20a00000, 0, 0x0000000 },
+ { 0x3, 0x05, 0x0, 0x2, 0xd2a0000, 0, 0x0000000 },
+ { 0x3, 0x06, 0x0, 0x2, 0xd290000, 0, 0x0000000 },
+ { 0x3, 0x07, 0x0, 0x2, 0xd2c0000, 0, 0x0000000 },
+ { 0x3, 0x08, 0x0, 0x2, 0xd0e0000, 4, 0x80000 },
+ { 0x3, 0x08, 0x1, 0x2, 0xd060000, 0, 0x0000000 },
+ { 0x3, 0x08, 0x2, 0x2, 0xd080000, 1, 0x20000 },
+ { 0x3, 0x08, 0x3, 0x2, 0xd0a0000, 2, 0x40000 },
+ { 0x3, 0x08, 0x4, 0x2, 0xd0c0000, 3, 0x60000 },
+ { 0x3, 0x09, 0x0, 0x2, 0xd650000, 0, 0x0000000 },
+ { 0x3, 0x0A, 0x0, 0x2, 0x20af0000, 0, 0x0000000 },
+ { 0x3, 0x0B, 0x0, 0x2, 0xd3e0000, 0, 0x0000000 },
+ { 0x3, 0x0C, 0x0, 0x2, 0xd3d0000, 0, 0x0000000 },
+ { 0x3, 0x0D, 0x0, 0x2, 0xd1e0000, 0, 0x0000000 },
+ { 0x3, 0x0E, 0x0, 0x2, 0xd150000, 0, 0x0000000 },
+ { 0x3, 0x0E, 0x1, 0x2, 0xd160000, 1, 0x10000 },
+ { 0x3, 0x0E, 0x2, 0x2, 0xd170000, 2, 0x20000 },
+ { 0x3, 0x0E, 0x3, 0x2, 0xd180000, 3, 0x30000 },
+ { 0x3, 0x0E, 0x4, 0x2, 0xd190000, 4, 0x40000 },
+ { 0x3, 0x0E, 0x5, 0x2, 0xd1a0000, 5, 0x50000 },
+ { 0x3, 0x0E, 0x6, 0x2, 0xd1b0000, 6, 0x60000 },
+ { 0x3, 0x0E, 0x7, 0x2, 0xd1c0000, 7, 0x70000 },
+ { 0x3, 0x0E, 0x8, 0x2, 0xd1d0000, 8, 0x80000 },
+ { 0x3, 0x0F, 0x0, 0x2, 0xd660000, 0, 0x0000000 },
+ { 0x3, 0x10, 0x0, 0x2, 0xd1f0000, 0, 0x0000000 },
+ { 0x3, 0x10, 0x1, 0x2, 0xd200000, 1, 0x10000 },
+ { 0x3, 0x10, 0x2, 0x2, 0xd210000, 2, 0x20000 },
+ { 0x3, 0x10, 0x3, 0x2, 0xd220000, 3, 0x30000 },
+ { 0x3, 0x11, 0x0, 0x2, 0xd240000, 0, 0x0000000 },
+ { 0x3, 0x12, 0x0, 0x2, 0xd250000, 0, 0x0000000 },
+ { 0x3, 0x13, 0x0, 0x2, 0xd260000, 0, 0x0000000 },
+ { 0x3, 0x14, 0x0, 0x2, 0xd270000, 0, 0x0000000 },
+ { 0x3, 0x15, 0x0, 0x2, 0xd2b0000, 0, 0x0000000 },
+ { 0x3, 0x16, 0x0, 0x2, 0xd280000, 0, 0x0000000 },
+ { 0x3, 0x17, 0x0, 0x2, 0xd0f0000, 0, 0x0000000 },
+ { 0x3, 0x17, 0x1, 0x2, 0xd100000, 1, 0x10000 },
+ { 0x3, 0x17, 0x2, 0x2, 0xd110000, 2, 0x20000 },
+ { 0x3, 0x17, 0x3, 0x2, 0xd120000, 3, 0x30000 },
+ { 0x3, 0x17, 0x4, 0x2, 0xd130000, 4, 0x40000 },
+ { 0x3, 0x17, 0x5, 0x2, 0xd140000, 5, 0x50000 },
+ { 0x3, 0x18, 0x0, 0x2, 0xd020000, 0, 0x0000000 },
+ { 0x3, 0x19, 0x0, 0x2, 0xd030000, 0, 0x0000000 },
+ { 0x3, 0x1F, 0x0, 0x2, 0xd600000, 0, 0x0000000 },
+ { 0x3, 0x1F, 0x1, 0x0, 0x0, 0, 0x0000000 },
+ { 0x4, 0x1B, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
+ { 0x4, 0x1B, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
+ { 0x4, 0x1E, 0x0, 0x2, 0xd400000, 0, 0xd400000 },
+ { 0x4, 0x1E, 0x1, 0x0, 0x0, 0, 0x0000000 },
+ { 0x5, 0x1C, 0x0, 0x0, 0xd640000, 0, 0x0000000 },
+ { 0x5, 0x1D, 0x0, 0x0, 0x20b00000, 8, 0x20b00000 },
+ { 0x5, 0x1D, 0x1, 0x0, 0x20800000, 7, 0x20800000 },
+ { 0x5, 0x1D, 0x2, 0x0, 0x20c00000, 9, 0x20c00000 },
+ { 0x5, 0x1D, 0x3, 0x0, 0xd800000, 3, 0xd800000 },
+ { 0x5, 0x1D, 0x4, 0x0, 0x20000000, 6, 0x20000000 },
+ { 0x5, 0x1D, 0x5, 0x0, 0xc000000, 2, 0xc000000 },
+ { 0x5, 0x1D, 0x6, 0x0, 0x21000000, 10, 0x21000000 },
+ { 0x5, 0x1D, 0x7, 0x0, 0xe000000, 4, 0xe000000 },
+ { 0x5, 0x1D, 0x8, 0x0, 0x22000000, 11, 0x22000000 },
+ { 0x5, 0x1D, 0x9, 0x0, 0x8000000, 1, 0x8000000 },
+ { 0x5, 0x1D, 0xa, 0x0, 0x24000000, 12, 0x24000000 },
+ { 0x5, 0x1D, 0xb, 0x0, 0x0, 0, 0x0000000 },
+ { 0x5, 0x1D, 0xc, 0x0, 0x28000000, 13, 0x28000000 },
+ { 0x5, 0x1D, 0xd, 0x0, 0x10000000, 5, 0x10000000 },
+ { 0x5, 0x1D, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
+ { 0x5, 0x00, 0x0, 0x0, 0xd230000, 0, 0x0000000 },
+ { 0x5, 0x01, 0x0, 0x0, 0xd040000, 0, 0x0000000 },
+ { 0x5, 0x02, 0x0, 0x0, 0xd050000, 0, 0x0000000 },
+ { 0x5, 0x03, 0x0, 0x0, 0xd000000, 0, 0x0000000 },
+ { 0x5, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0xe0000 },
+ { 0x5, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0xc0000 },
+ { 0x5, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x80000 },
+ { 0x5, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x0000000 },
+ { 0x5, 0x05, 0x0, 0x0, 0xd2a0000, 0, 0x0000000 },
+ { 0x5, 0x06, 0x0, 0x0, 0xd290000, 0, 0x0000000 },
+ { 0x5, 0x07, 0x0, 0x0, 0xd2c0000, 0, 0x0000000 },
+ { 0x5, 0x08, 0x0, 0x0, 0xd0e0000, 4, 0x80000 },
+ { 0x5, 0x08, 0x1, 0x0, 0xd060000, 0, 0x0000000 },
+ { 0x5, 0x08, 0x2, 0x0, 0xd080000, 1, 0x20000 },
+ { 0x5, 0x08, 0x3, 0x0, 0xd0a0000, 2, 0x40000 },
+ { 0x5, 0x08, 0x4, 0x0, 0xd0c0000, 3, 0x60000 },
+ { 0x5, 0x09, 0x0, 0x0, 0xd650000, 0, 0x0000000 },
+ { 0x5, 0x0A, 0x0, 0x0, 0x20af0000, 0, 0x0000000 },
+ { 0x5, 0x0B, 0x0, 0x0, 0xd3e0000, 0, 0x0000000 },
+ { 0x5, 0x0C, 0x0, 0x0, 0xd3d0000, 0, 0x0000000 },
+ { 0x5, 0x0D, 0x0, 0x0, 0xd1e0000, 0, 0x0000000 },
+ { 0x5, 0x0E, 0x0, 0x0, 0xd150000, 0, 0x0000000 },
+ { 0x5, 0x0E, 0x1, 0x0, 0xd160000, 1, 0x10000 },
+ { 0x5, 0x0E, 0x2, 0x0, 0xd170000, 2, 0x20000 },
+ { 0x5, 0x0E, 0x3, 0x0, 0xd180000, 3, 0x30000 },
+ { 0x5, 0x0E, 0x4, 0x0, 0xd190000, 4, 0x40000 },
+ { 0x5, 0x0E, 0x5, 0x0, 0xd1a0000, 5, 0x50000 },
+ { 0x5, 0x0E, 0x6, 0x0, 0xd1b0000, 6, 0x60000 },
+ { 0x5, 0x0E, 0x7, 0x0, 0xd1c0000, 7, 0x70000 },
+ { 0x5, 0x0E, 0x8, 0x0, 0xd1d0000, 8, 0x80000 },
+ { 0x5, 0x0F, 0x0, 0x0, 0xd660000, 0, 0x0000000 },
+ { 0x5, 0x10, 0x0, 0x0, 0xd1f0000, 0, 0x0000000 },
+ { 0x5, 0x10, 0x1, 0x0, 0xd200000, 1, 0x10000 },
+ { 0x5, 0x10, 0x2, 0x0, 0xd210000, 2, 0x20000 },
+ { 0x5, 0x10, 0x3, 0x0, 0xd220000, 3, 0x30000 },
+ { 0x5, 0x11, 0x0, 0x0, 0xd240000, 0, 0x0000000 },
+ { 0x5, 0x12, 0x0, 0x0, 0xd250000, 0, 0x0000000 },
+ { 0x5, 0x13, 0x0, 0x0, 0xd260000, 0, 0x0000000 },
+ { 0x5, 0x14, 0x0, 0x0, 0xd270000, 0, 0x0000000 },
+ { 0x5, 0x15, 0x0, 0x0, 0xd2b0000, 0, 0x0000000 },
+ { 0x5, 0x16, 0x0, 0x0, 0xd280000, 0, 0x0000000 },
+ { 0x5, 0x17, 0x0, 0x0, 0xd0f0000, 0, 0x0000000 },
+ { 0x5, 0x17, 0x1, 0x0, 0xd100000, 1, 0x10000 },
+ { 0x5, 0x17, 0x2, 0x0, 0xd110000, 2, 0x20000 },
+ { 0x5, 0x17, 0x3, 0x0, 0xd120000, 3, 0x30000 },
+ { 0x5, 0x17, 0x4, 0x0, 0xd130000, 4, 0x40000 },
+ { 0x5, 0x17, 0x5, 0x0, 0xd140000, 5, 0x50000 },
+ { 0x5, 0x18, 0x0, 0x0, 0xd020000, 0, 0x0000000 },
+ { 0x5, 0x19, 0x0, 0x0, 0xd030000, 0, 0x0000000 },
+ { 0x5, 0x1F, 0x0, 0x0, 0xd600000, 0, 0x0000000 },
+ { 0x5, 0x1F, 0x1, 0x0, 0x0, 0, 0x0000000 }
+};
+
+/*
+ * AON NOC aperture lookup table as per file "AON_NOC_Structure.info".
+ */
+static char *t194_aonnoc_routeid_initflow[] = {
+ "cbb_i/I/0", /* 0x0 */
+ "cpu_p_i/I/0", /* 0x1 */
+ "dma_m_i/I/0", /* 0x2 */
+ "dma_p_i/I/0" /* 0x3 */
+};
+
+static char *t194_aonnoc_routeid_targflow[] = {
+ "multiport1_t/T/aon_misc", /* 0 */
+ "multiport1_t/T/avic0", /* 1 */
+ "multiport1_t/T/avic1", /* 2 */
+ "multiport1_t/T/can1", /* 3 */
+ "multiport1_t/T/can2", /* 4 */
+ "multiport1_t/T/dma", /* 5 */
+ "multiport1_t/T/dmic", /* 6 */
+ "multiport1_t/T/err_collator", /* 7 */
+ "multiport1_t/T/fpga_misc", /* 8 */
+ "multiport1_t/T/gte", /* 9 */
+ "multiport1_t/T/hsp", /* A */
+ "multiport1_t/T/i2c2", /* B */
+ "multiport1_t/T/i2c8", /* C */
+ "multiport1_t/T/pwm", /* D */
+ "multiport1_t/T/spi2", /* E */
+ "multiport1_t/T/tke", /* F */
+ "multiport1_t/T/uartg", /* 10 */
+ "RESERVED", /* 11 */
+ "RESERVED", /* 12 */
+ "RESERVED", /* 13 */
+ "RESERVED", /* 14 */
+ "RESERVED", /* 15 */
+ "RESERVED", /* 16 */
+ "RESERVED", /* 17 */
+ "RESERVED", /* 18 */
+ "RESERVED", /* 19 */
+ "RESERVED", /* 1A */
+ "RESERVED", /* 1B */
+ "RESERVED", /* 1C */
+ "RESERVED", /* 1D */
+ "RESERVED", /* 1E */
+ "RESERVED", /* 1F */
+ "multiport0_t/T/aovc", /* 20 */
+ "multiport0_t/T/atcm", /* 21 */
+ "multiport0_t/T/cast", /* 22 */
+ "multiport0_t/T/dast", /* 23 */
+ "multiport0_t/T/err_collator_car", /* 24 */
+ "multiport0_t/T/gpio", /* 25 */
+ "multiport0_t/T/i2c10", /* 26 */
+ "multiport0_t/T/mss", /* 27 */
+ "multiport0_t/T/padctl_a12", /* 28 */
+ "multiport0_t/T/padctl_a14", /* 29 */
+ "multiport0_t/T/padctl_a15", /* 2A */
+ "multiport0_t/T/rtc", /* 2B */
+ "multiport0_t/T/tsc", /* 2C */
+ "RESERVED", /* 2D */
+ "RESERVED", /* 2E */
+ "RESERVED", /* 2F */
+ "multiport2_t/T/aon_vref_ro", /* 30 */
+ "multiport2_t/T/aopm", /* 31 */
+ "multiport2_t/T/car", /* 32 */
+ "multiport2_t/T/pmc", /* 33 */
+ "ast1_t/T/0", /* 34 */
+ "cbb_t/T/0", /* 35 */
+ "cpu_t/T/0", /* 36 */
+ "firewall_t/T/0", /* 37 */
+ "svc_t/T/0", /* 38 */
+ "uartc/T/uartc", /* 39 */
+ "RESERVED", /* 3A */
+ "RESERVED", /* 3B */
+ "RESERVED", /* 3C */
+ "RESERVED", /* 3D */
+ "RESERVED", /* 3E */
+ "RESERVED" /* 3F */
+};
+
+/*
+ * Fields of AON NOC lookup table:
+ * Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
+ * Targ mapping, Targ localAddress
+ * ----------------------------------------------------------------------------
+ */
+static const struct tegra194_cbb_aperture t194_aonnoc_aperture_lookup[] = {
+ { 0x0, 0x37, 0x0, 0, 0xc640000, 0, 0x0 },
+ { 0x0, 0x20, 0x0, 0, 0xc3b0000, 0, 0x0 },
+ { 0x0, 0x21, 0x0, 0, 0xc000000, 0, 0x0 },
+ { 0x0, 0x22, 0x0, 0, 0xc040000, 0, 0x0 },
+ { 0x0, 0x23, 0x0, 0, 0xc050000, 0, 0x0 },
+ { 0x0, 0x24, 0x0, 0, 0x20cf0000, 0, 0x0 },
+ { 0x0, 0x25, 0x0, 0, 0xc2f0000, 0, 0x0 },
+ { 0x0, 0x26, 0x0, 0, 0xc230000, 0, 0x0 },
+ { 0x0, 0x27, 0x0, 0, 0xc350000, 0, 0x0 },
+ { 0x0, 0x28, 0x0, 0, 0xc301000, 0, 0x0 },
+ { 0x0, 0x29, 0x0, 0, 0xc302000, 0, 0x0 },
+ { 0x0, 0x2A, 0x0, 0, 0xc303000, 0, 0x0 },
+ { 0x0, 0x2B, 0x0, 0, 0xc2a0000, 0, 0x0 },
+ { 0x0, 0x2C, 0x0, 0, 0xc2b0000, 0, 0x0 },
+ { 0x0, 0x2C, 0x1, 0, 0xc2c0000, 1, 0x10000 },
+ { 0x0, 0x2C, 0x2, 0, 0xc2d0000, 2, 0x20000 },
+ { 0x0, 0x2C, 0x3, 0, 0xc2e0000, 3, 0x30000 },
+ { 0x0, 0x0, 0x0, 0, 0xc660000, 0, 0x0 },
+ { 0x0, 0x1, 0x0, 0, 0xc020000, 0, 0x0 },
+ { 0x0, 0x2, 0x0, 0, 0xc030000, 0, 0x0 },
+ { 0x0, 0x3, 0x0, 0, 0xc310000, 0, 0x0 },
+ { 0x0, 0x4, 0x0, 0, 0xc320000, 0, 0x0 },
+ { 0x0, 0x5, 0x0, 0, 0xc0a0000, 2, 0x40000 },
+ { 0x0, 0x5, 0x1, 0, 0xc0b0000, 3, 0x50000 },
+ { 0x0, 0x5, 0x2, 0, 0xc0e0000, 5, 0x80000 },
+ { 0x0, 0x5, 0x3, 0, 0xc060000, 0, 0x0 },
+ { 0x0, 0x5, 0x4, 0, 0xc080000, 1, 0x20000 },
+ { 0x0, 0x5, 0x5, 0, 0xc0c0000, 4, 0x60000 },
+ { 0x0, 0x6, 0x0, 0, 0xc330000, 0, 0x0 },
+ { 0x0, 0x7, 0x0, 0, 0xc650000, 0, 0x0 },
+ { 0x0, 0x8, 0x0, 0, 0xc3e0000, 0, 0x0 },
+ { 0x0, 0x9, 0x0, 0, 0xc1e0000, 0, 0x0 },
+ { 0x0, 0xA, 0x0, 0, 0xc150000, 0, 0x0 },
+ { 0x0, 0xA, 0x1, 0, 0xc160000, 1, 0x10000 },
+ { 0x0, 0xA, 0x2, 0, 0xc170000, 2, 0x20000 },
+ { 0x0, 0xA, 0x3, 0, 0xc180000, 3, 0x30000 },
+ { 0x0, 0xA, 0x4, 0, 0xc190000, 4, 0x40000 },
+ { 0x0, 0xA, 0x5, 0, 0xc1a0000, 5, 0x50000 },
+ { 0x0, 0xA, 0x6, 0, 0xc1b0000, 6, 0x60000 },
+ { 0x0, 0xA, 0x7, 0, 0xc1c0000, 7, 0x70000 },
+ { 0x0, 0xA, 0x8, 0, 0xc1d0000, 8, 0x80000 },
+ { 0x0, 0xB, 0x0, 0, 0xc240000, 0, 0x0 },
+ { 0x0, 0xC, 0x0, 0, 0xc250000, 0, 0x0 },
+ { 0x0, 0xD, 0x0, 0, 0xc340000, 0, 0x0 },
+ { 0x0, 0xE, 0x0, 0, 0xc260000, 0, 0x0 },
+ { 0x0, 0xF, 0x0, 0, 0xc0f0000, 0, 0x0 },
+ { 0x0, 0xF, 0x1, 0, 0xc100000, 1, 0x10000 },
+ { 0x0, 0xF, 0x2, 0, 0xc110000, 2, 0x20000 },
+ { 0x0, 0xF, 0x3, 0, 0xc120000, 3, 0x30000 },
+ { 0x0, 0xF, 0x4, 0, 0xc130000, 4, 0x40000 },
+ { 0x0, 0xF, 0x5, 0, 0xc140000, 5, 0x50000 },
+ { 0x0, 0x10, 0x0, 0, 0xc290000, 0, 0x0 },
+ { 0x0, 0x30, 0x0, 0, 0x20ce0000, 0, 0x0 },
+ { 0x0, 0x31, 0x0, 0, 0xc1f0000, 0, 0x0 },
+ { 0x0, 0x31, 0x1, 0, 0xc200000, 1, 0x10000 },
+ { 0x0, 0x31, 0x2, 0, 0xc210000, 2, 0x20000 },
+ { 0x0, 0x31, 0x3, 0, 0xc220000, 3, 0x30000 },
+ { 0x0, 0x32, 0x0, 0, 0x20cc0000, 3, 0x1c0000 },
+ { 0x0, 0x32, 0x1, 0, 0x20c80000, 2, 0x180000 },
+ { 0x0, 0x32, 0x2, 0, 0x20c00000, 1, 0x100000 },
+ { 0x0, 0x32, 0x3, 0, 0x20b00000, 0, 0x0 },
+ { 0x0, 0x33, 0x0, 0, 0xc360000, 0, 0x0 },
+ { 0x0, 0x33, 0x1, 0, 0xc370000, 1, 0x10000 },
+ { 0x0, 0x33, 0x2, 0, 0xc3a0000, 3, 0x40000 },
+ { 0x0, 0x33, 0x3, 0, 0xc380000, 2, 0x20000 },
+ { 0x0, 0x38, 0x0, 0, 0xc600000, 0, 0x0 },
+ { 0x0, 0x38, 0x1, 0, 0x0000000, 0, 0x0, },
+ { 0x0, 0x39, 0x0, 0, 0xc280000, 0, 0x0 },
+ { 0x1, 0x35, 0x0, 0, 0x0000000, 0, 0x0, },
+ { 0x1, 0x35, 0x1, 0, 0x100000, 1, 0x100000 },
+ { 0x1, 0x35, 0x2, 0, 0x5a00000, 11, 0x5a00000 },
+ { 0x1, 0x35, 0x3, 0, 0x5b00000, 32, 0x5b00000 },
+ { 0x1, 0x35, 0x4, 0, 0x5c00000, 33, 0x5c00000 },
+ { 0x1, 0x35, 0x5, 0, 0x5d00000, 12, 0x5d00000 },
+ { 0x1, 0x35, 0x6, 0, 0x20000000, 19, 0x20000000 },
+ { 0x1, 0x35, 0x7, 0, 0x20100000, 20, 0x20100000 },
+ { 0x1, 0x35, 0x8, 0, 0x20a00000, 24, 0x20a00000 },
+ { 0x1, 0x35, 0x9, 0, 0x20d00000, 25, 0x20d00000 },
+ { 0x1, 0x35, 0xa, 0, 0x200000, 2, 0x200000 },
+ { 0x1, 0x35, 0xb, 0, 0x5800000, 10, 0x5800000 },
+ { 0x1, 0x35, 0xc, 0, 0x5e00000, 13, 0x5e00000 },
+ { 0x1, 0x35, 0xd, 0, 0x20200000, 21, 0x20200000 },
+ { 0x1, 0x35, 0xe, 0, 0x20800000, 23, 0x20800000 },
+ { 0x1, 0x35, 0xf, 0, 0x20e00000, 26, 0x20e00000 },
+ { 0x1, 0x35, 0x10, 0, 0x400000, 3, 0x400000 },
+ { 0x1, 0x35, 0x11, 0, 0x20400000, 22, 0x20400000 },
+ { 0x1, 0x35, 0x12, 0, 0x800000, 4, 0x800000 },
+ { 0x1, 0x35, 0x13, 0, 0x5000000, 9, 0x5000000 },
+ { 0x1, 0x35, 0x14, 0, 0xc800000, 34, 0xc800000 },
+ { 0x1, 0x35, 0x15, 0, 0x1000000, 5, 0x1000000 },
+ { 0x1, 0x35, 0x16, 0, 0x3000000, 7, 0x3000000 },
+ { 0x1, 0x35, 0x17, 0, 0x4000000, 8, 0x4000000 },
+ { 0x1, 0x35, 0x18, 0, 0xd000000, 16, 0xd000000 },
+ { 0x1, 0x35, 0x19, 0, 0x21000000, 27, 0x21000000 },
+ { 0x1, 0x35, 0x1a, 0, 0x2000000, 6, 0x2000000 },
+ { 0x1, 0x35, 0x1b, 0, 0x6000000, 14, 0x6000000 },
+ { 0x1, 0x35, 0x1c, 0, 0xe000000, 17, 0xe000000 },
+ { 0x1, 0x35, 0x1d, 0, 0x22000000, 28, 0x22000000 },
+ { 0x1, 0x35, 0x1e, 0, 0x8000000, 15, 0x8000000 },
+ { 0x1, 0x35, 0x1f, 0, 0x24000000, 29, 0x24000000 },
+ { 0x1, 0x35, 0x20, 0, 0x28000000, 30, 0x28000000 },
+ { 0x1, 0x35, 0x21, 0, 0x10000000, 18, 0x10000000 },
+ { 0x1, 0x35, 0x22, 0, 0x30000000, 31, 0x30000000 },
+ { 0x1, 0x37, 0x0, 0, 0xc640000, 0, 0x0 },
+ { 0x1, 0x20, 0x0, 0, 0xc3b0000, 0, 0x0 },
+ { 0x1, 0x21, 0x0, 0, 0xc000000, 0, 0x0 },
+ { 0x1, 0x22, 0x0, 0, 0xc040000, 0, 0x0 },
+ { 0x1, 0x23, 0x0, 0, 0xc050000, 0, 0x0 },
+ { 0x1, 0x24, 0x0, 0, 0x20cf0000, 0, 0x0 },
+ { 0x1, 0x25, 0x0, 0, 0xc2f0000, 0, 0x0 },
+ { 0x1, 0x26, 0x0, 0, 0xc230000, 0, 0x0 },
+ { 0x1, 0x27, 0x0, 0, 0xc350000, 0, 0x0 },
+ { 0x1, 0x28, 0x0, 0, 0xc301000, 0, 0x0 },
+ { 0x1, 0x29, 0x0, 0, 0xc302000, 0, 0x0 },
+ { 0x1, 0x2A, 0x0, 0, 0xc303000, 0, 0x0 },
+ { 0x1, 0x2B, 0x0, 0, 0xc2a0000, 0, 0x0 },
+ { 0x1, 0x2C, 0x0, 0, 0xc2b0000, 0, 0x0 },
+ { 0x1, 0x2C, 0x1, 0, 0xc2c0000, 1, 0x10000 },
+ { 0x1, 0x2C, 0x2, 0, 0xc2d0000, 2, 0x20000 },
+ { 0x1, 0x2C, 0x3, 0, 0xc2e0000, 3, 0x30000 },
+ { 0x1, 0x0, 0x0, 0, 0xc660000, 0, 0x0 },
+ { 0x1, 0x1, 0x0, 0, 0xc020000, 0, 0x0 },
+ { 0x1, 0x2, 0x0, 0, 0xc030000, 0, 0x0 },
+ { 0x1, 0x3, 0x0, 0, 0xc310000, 0, 0x0 },
+ { 0x1, 0x4, 0x0, 0, 0xc320000, 0, 0x0 },
+ { 0x1, 0x5, 0x0, 0, 0xc0a0000, 2, 0x40000 },
+ { 0x1, 0x5, 0x1, 0, 0xc0b0000, 3, 0x50000 },
+ { 0x1, 0x5, 0x2, 0, 0xc0e0000, 5, 0x80000 },
+ { 0x1, 0x5, 0x3, 0, 0xc060000, 0, 0x0 },
+ { 0x1, 0x5, 0x4, 0, 0xc080000, 1, 0x20000 },
+ { 0x1, 0x5, 0x5, 0, 0xc0c0000, 4, 0x60000 },
+ { 0x1, 0x6, 0x0, 0, 0xc330000, 0, 0x0 },
+ { 0x1, 0x7, 0x0, 0, 0xc650000, 0, 0x0 },
+ { 0x1, 0x8, 0x0, 0, 0xc3e0000, 0, 0x0 },
+ { 0x1, 0x9, 0x0, 0, 0xc1e0000, 0, 0x0 },
+ { 0x1, 0xA, 0x0, 0, 0xc150000, 0, 0x0 },
+ { 0x1, 0xA, 0x1, 0, 0xc160000, 1, 0x10000 },
+ { 0x1, 0xA, 0x2, 0, 0xc170000, 2, 0x20000 },
+ { 0x1, 0xA, 0x3, 0, 0xc180000, 3, 0x30000 },
+ { 0x1, 0xA, 0x4, 0, 0xc190000, 4, 0x40000 },
+ { 0x1, 0xA, 0x5, 0, 0xc1a0000, 5, 0x50000 },
+ { 0x1, 0xA, 0x6, 0, 0xc1b0000, 6, 0x60000 },
+ { 0x1, 0xA, 0x7, 0, 0xc1c0000, 7, 0x70000 },
+ { 0x1, 0xA, 0x8, 0, 0xc1d0000, 8, 0x80000 },
+ { 0x1, 0xB, 0x0, 0, 0xc240000, 0, 0x0 },
+ { 0x1, 0xC, 0x0, 0, 0xc250000, 0, 0x0 },
+ { 0x1, 0xD, 0x0, 0, 0xc340000, 0, 0x0 },
+ { 0x1, 0xE, 0x0, 0, 0xc260000, 0, 0x0 },
+ { 0x1, 0xF, 0x0, 0, 0xc0f0000, 0, 0x0 },
+ { 0x1, 0xF, 0x1, 0, 0xc100000, 1, 0x10000 },
+ { 0x1, 0xF, 0x2, 0, 0xc110000, 2, 0x20000 },
+ { 0x1, 0xF, 0x3, 0, 0xc120000, 3, 0x30000 },
+ { 0x1, 0xF, 0x4, 0, 0xc130000, 4, 0x40000 },
+ { 0x1, 0xF, 0x5, 0, 0xc140000, 5, 0x50000 },
+ { 0x1, 0x10, 0x0, 0, 0xc290000, 0, 0x0 },
+ { 0x1, 0x30, 0x0, 0, 0x20ce0000, 0, 0x0 },
+ { 0x1, 0x31, 0x0, 0, 0xc1f0000, 0, 0x0 },
+ { 0x1, 0x31, 0x1, 0, 0xc200000, 1, 0x10000 },
+ { 0x1, 0x31, 0x2, 0, 0xc210000, 2, 0x20000 },
+ { 0x1, 0x31, 0x3, 0, 0xc220000, 3, 0x30000 },
+ { 0x1, 0x32, 0x0, 0, 0x20cc0000, 3, 0x1c0000 },
+ { 0x1, 0x32, 0x1, 0, 0x20c80000, 2, 0x180000 },
+ { 0x1, 0x32, 0x2, 0, 0x20c00000, 1, 0x100000 },
+ { 0x1, 0x32, 0x3, 0, 0x20b00000, 0, 0x0 },
+ { 0x1, 0x33, 0x0, 0, 0xc360000, 0, 0x0 },
+ { 0x1, 0x33, 0x1, 0, 0xc370000, 1, 0x10000 },
+ { 0x1, 0x33, 0x2, 0, 0xc3a0000, 3, 0x40000 },
+ { 0x1, 0x33, 0x3, 0, 0xc380000, 2, 0x20000 },
+ { 0x1, 0x38, 0x0, 0, 0xc600000, 0, 0x0 },
+ { 0x1, 0x38, 0x1, 0, 0x0000000, 0, 0x0, },
+ { 0x1, 0x39, 0x0, 0, 0xc280000, 0, 0x0 },
+ { 0x2, 0x34, 0x0, 0, 0x40000000, 0, 0x40000000 },
+ { 0x2, 0x34, 0x1, 0, 0x80000000, 1, 0x80000000 },
+ { 0x2, 0x36, 0x0, 0, 0xc400000, 0, 0xc400000 },
+ { 0x2, 0x36, 0x1, 0, 0x0000000, 0, 0x0, },
+ { 0x3, 0x35, 0x0, 0, 0x0000000, 0, 0x0, },
+ { 0x3, 0x35, 0x1, 0, 0x100000, 1, 0x100000 },
+ { 0x3, 0x35, 0x2, 0, 0x5a00000, 11, 0x5a00000 },
+ { 0x3, 0x35, 0x3, 0, 0x5b00000, 32, 0x5b00000 },
+ { 0x3, 0x35, 0x4, 0, 0x5c00000, 33, 0x5c00000 },
+ { 0x3, 0x35, 0x5, 0, 0x5d00000, 12, 0x5d00000 },
+ { 0x3, 0x35, 0x6, 0, 0x20000000, 19, 0x20000000 },
+ { 0x3, 0x35, 0x7, 0, 0x20100000, 20, 0x20100000 },
+ { 0x3, 0x35, 0x8, 0, 0x20a00000, 24, 0x20a00000 },
+ { 0x3, 0x35, 0x9, 0, 0x20d00000, 25, 0x20d00000 },
+ { 0x3, 0x35, 0xa, 0, 0x200000, 2, 0x200000 },
+ { 0x3, 0x35, 0xb, 0, 0x5800000, 10, 0x5800000 },
+ { 0x3, 0x35, 0xc, 0, 0x5e00000, 13, 0x5e00000 },
+ { 0x3, 0x35, 0xd, 0, 0x20200000, 21, 0x20200000 },
+ { 0x3, 0x35, 0xe, 0, 0x20800000, 23, 0x20800000 },
+ { 0x3, 0x35, 0xf, 0, 0x20e00000, 26, 0x20e00000 },
+ { 0x3, 0x35, 0x10, 0, 0x400000, 3, 0x400000 },
+ { 0x3, 0x35, 0x11, 0, 0x20400000, 22, 0x20400000 },
+ { 0x3, 0x35, 0x12, 0, 0x800000, 4, 0x800000 },
+ { 0x3, 0x35, 0x13, 0, 0x5000000, 9, 0x5000000 },
+ { 0x3, 0x35, 0x14, 0, 0xc800000, 34, 0xc800000 },
+ { 0x3, 0x35, 0x15, 0, 0x1000000, 5, 0x1000000 },
+ { 0x3, 0x35, 0x16, 0, 0x3000000, 7, 0x3000000 },
+ { 0x3, 0x35, 0x17, 0, 0x4000000, 8, 0x4000000 },
+ { 0x3, 0x35, 0x18, 0, 0xd000000, 16, 0xd000000 },
+ { 0x3, 0x35, 0x19, 0, 0x21000000, 27, 0x21000000 },
+ { 0x3, 0x35, 0x1a, 0, 0x2000000, 6, 0x2000000 },
+ { 0x3, 0x35, 0x1b, 0, 0x6000000, 14, 0x6000000 },
+ { 0x3, 0x35, 0x1c, 0, 0xe000000, 17, 0xe000000 },
+ { 0x3, 0x35, 0x1d, 0, 0x22000000, 28, 0x22000000 },
+ { 0x3, 0x35, 0x1e, 0, 0x8000000, 15, 0x8000000 },
+ { 0x3, 0x35, 0x1f, 0, 0x24000000, 29, 0x24000000 },
+ { 0x3, 0x35, 0x20, 0, 0x28000000, 30, 0x28000000 },
+ { 0x3, 0x35, 0x21, 0, 0x10000000, 18, 0x10000000 },
+ { 0x3, 0x35, 0x22, 0, 0x30000000, 31, 0x30000000 },
+ { 0x3, 0x37, 0x0, 0, 0xc640000, 0, 0x0 },
+ { 0x3, 0x20, 0x0, 0, 0xc3b0000, 0, 0x0 },
+ { 0x3, 0x21, 0x0, 0, 0xc000000, 0, 0x0 },
+ { 0x3, 0x22, 0x0, 0, 0xc040000, 0, 0x0 },
+ { 0x3, 0x23, 0x0, 0, 0xc050000, 0, 0x0 },
+ { 0x3, 0x24, 0x0, 0, 0x20cf0000, 0, 0x0 },
+ { 0x3, 0x25, 0x0, 0, 0xc2f0000, 0, 0x0 },
+ { 0x3, 0x26, 0x0, 0, 0xc230000, 0, 0x0 },
+ { 0x3, 0x27, 0x0, 0, 0xc350000, 0, 0x0 },
+ { 0x3, 0x28, 0x0, 0, 0xc301000, 0, 0x0 },
+ { 0x3, 0x29, 0x0, 0, 0xc302000, 0, 0x0 },
+ { 0x3, 0x2A, 0x0, 0, 0xc303000, 0, 0x0 },
+ { 0x3, 0x2B, 0x0, 0, 0xc2a0000, 0, 0x0 },
+ { 0x3, 0x2C, 0x0, 0, 0xc2b0000, 0, 0x0 },
+ { 0x3, 0x2C, 0x1, 0, 0xc2c0000, 1, 0x10000 },
+ { 0x3, 0x2C, 0x2, 0, 0xc2d0000, 2, 0x20000 },
+ { 0x3, 0x2C, 0x3, 0, 0xc2e0000, 3, 0x30000 },
+ { 0x3, 0x0, 0x0, 0, 0xc660000, 0, 0x0 },
+ { 0x3, 0x1, 0x0, 0, 0xc020000, 0, 0x0 },
+ { 0x3, 0x2, 0x0, 0, 0xc030000, 0, 0x0 },
+ { 0x3, 0x3, 0x0, 0, 0xc310000, 0, 0x0 },
+ { 0x3, 0x4, 0x0, 0, 0xc320000, 0, 0x0 },
+ { 0x3, 0x5, 0x0, 0, 0xc0a0000, 2, 0x40000 },
+ { 0x3, 0x5, 0x1, 0, 0xc0b0000, 3, 0x50000 },
+ { 0x3, 0x5, 0x2, 0, 0xc0e0000, 5, 0x80000 },
+ { 0x3, 0x5, 0x3, 0, 0xc060000, 0, 0x0 },
+ { 0x3, 0x5, 0x4, 0, 0xc080000, 1, 0x20000 },
+ { 0x3, 0x5, 0x5, 0, 0xc0c0000, 4, 0x60000 },
+ { 0x3, 0x6, 0x0, 0, 0xc330000, 0, 0x0 },
+ { 0x3, 0x7, 0x0, 0, 0xc650000, 0, 0x0 },
+ { 0x3, 0x8, 0x0, 0, 0xc3e0000, 0, 0x0 },
+ { 0x3, 0x9, 0x0, 0, 0xc1e0000, 0, 0x0 },
+ { 0x3, 0xA, 0x0, 0, 0xc150000, 0, 0x0 },
+ { 0x3, 0xA, 0x1, 0, 0xc160000, 1, 0x10000 },
+ { 0x3, 0xA, 0x2, 0, 0xc170000, 2, 0x20000 },
+ { 0x3, 0xA, 0x3, 0, 0xc180000, 3, 0x30000 },
+ { 0x3, 0xA, 0x4, 0, 0xc190000, 4, 0x40000 },
+ { 0x3, 0xA, 0x5, 0, 0xc1a0000, 5, 0x50000 },
+ { 0x3, 0xA, 0x6, 0, 0xc1b0000, 6, 0x60000 },
+ { 0x3, 0xA, 0x7, 0, 0xc1c0000, 7, 0x70000 },
+ { 0x3, 0xA, 0x8, 0, 0xc1d0000, 8, 0x80000 },
+ { 0x3, 0xB, 0x0, 0, 0xc240000, 0, 0x0 },
+ { 0x3, 0xC, 0x0, 0, 0xc250000, 0, 0x0 },
+ { 0x3, 0xD, 0x0, 0, 0xc340000, 0, 0x0 },
+ { 0x3, 0xE, 0x0, 0, 0xc260000, 0, 0x0 },
+ { 0x3, 0xF, 0x0, 0, 0xc0f0000, 0, 0x0 },
+ { 0x3, 0xF, 0x1, 0, 0xc100000, 1, 0x10000 },
+ { 0x3, 0xF, 0x2, 0, 0xc110000, 2, 0x20000 },
+ { 0x3, 0xF, 0x3, 0, 0xc120000, 3, 0x30000 },
+ { 0x3, 0xF, 0x4, 0, 0xc130000, 4, 0x40000 },
+ { 0x3, 0xF, 0x5, 0, 0xc140000, 5, 0x50000 },
+ { 0x3, 0x10, 0x0, 0, 0xc290000, 0, 0x0 },
+ { 0x3, 0x30, 0x0, 0, 0x20ce0000, 0, 0x0 },
+ { 0x3, 0x31, 0x0, 0, 0xc1f0000, 0, 0x0 },
+ { 0x3, 0x31, 0x1, 0, 0xc200000, 1, 0x10000 },
+ { 0x3, 0x31, 0x2, 0, 0xc210000, 2, 0x20000 },
+ { 0x3, 0x31, 0x3, 0, 0xc220000, 3, 0x30000 },
+ { 0x3, 0x32, 0x0, 0, 0x20cc0000, 3, 0x1c0000 },
+ { 0x3, 0x32, 0x1, 0, 0x20c80000, 2, 0x180000 },
+ { 0x3, 0x32, 0x2, 0, 0x20c00000, 1, 0x100000 },
+ { 0x3, 0x32, 0x3, 0, 0x20b00000, 0, 0x0 },
+ { 0x3, 0x33, 0x0, 0, 0xc360000, 0, 0x0 },
+ { 0x3, 0x33, 0x1, 0, 0xc370000, 1, 0x10000 },
+ { 0x3, 0x33, 0x2, 0, 0xc3a0000, 3, 0x40000 },
+ { 0x3, 0x33, 0x3, 0, 0xc380000, 2, 0x20000 },
+ { 0x3, 0x38, 0x0, 0, 0xc600000, 0, 0x0 },
+ { 0x3, 0x38, 0x1, 0, 0x0, 0, 0x0 },
+ { 0x3, 0x39, 0x0, 0, 0xc280000, 0, 0x0 }
+};
+
+/*
+ * SCE/RCE NOC aperture lookup table as per file "AON_NOC_Structure.info".
+ */
+static char *t194_scenoc_routeid_initflow[] = {
+ "cbb_i/I/0", /* 0 */
+ "cpu_m_i/I/0", /* 1 */
+ "cpu_p_i/I/0", /* 2 */
+ "dma_m_i/I/0", /* 3 */
+ "dma_p_i/I/0", /* 4 */
+ "RESERVED", /* 5 */
+ "RESERVED", /* 6 */
+ "RESERVED" /* 7 */
+};
+
+static char *t194_scenoc_routeid_targflow[] = {
+ "multiport0_t/T/atcm_cfg", /* 0x0 */
+ "multiport0_t/T/car", /* 0x1 */
+ "multiport0_t/T/cast", /* 0x2 */
+ "multiport0_t/T/cfg", /* 0x3 */
+ "multiport0_t/T/dast", /* 0x4 */
+ "multiport0_t/T/dma", /* 0x5 */
+ "multiport0_t/T/err_collator", /* 0x6 */
+ "multiport0_t/T/err_collator_car", /* 0x7 */
+ "multiport0_t/T/fpga_misc", /* 0x8 */
+ "multiport0_t/T/fpga_uart", /* 0x9 */
+ "multiport0_t/T/gte", /* 0xA */
+ "multiport0_t/T/hsp", /* 0xB */
+ "multiport0_t/T/misc", /* 0xC */
+ "multiport0_t/T/pm", /* 0xD */
+ "multiport0_t/T/tke", /* 0xE */
+ "RESERVED", /* 0xF */
+ "multiport1_t/T/hsm", /* 0x10 */
+ "multiport1_t/T/vic0", /* 0x11 */
+ "multiport1_t/T/vic1", /* 0x12 */
+ "ast0_t/T/0", /* 0x13 */
+ "ast1_t/T/0", /* 0x14 */
+ "cbb_t/T/0", /* 0x15 */
+ "cpu_t/T/0", /* 0x16 */
+ "sce_noc_firewall/T/0", /* 0x17 */
+ "svc_t/T/0", /* 0x18 */
+ "RESERVED", /* 0x19 */
+ "RESERVED", /* 0x1A */
+ "RESERVED", /* 0x1B */
+ "RESERVED", /* 0x1C */
+ "RESERVED", /* 0x1D */
+ "RESERVED", /* 0x1E */
+ "RESERVED" /* 0x1F */
+};
+
+/*
+ * Fields of SCE/RCE NOC lookup table:
+ * Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
+ * Targ mapping, Targ localAddress
+ * ----------------------------------------------------------------------------
+ */
+static const struct tegra194_cbb_aperture t194_scenoc_apert_lookup[] = {
+ { 0x0, 0x16, 0x0, 0, 0xb400000, 0, 0xb400000 },
+ { 0x0, 0x16, 0x1, 0, 0xbc00000, 1, 0xbc00000 },
+ { 0x0, 0x0, 0x0, 0, 0xb000000, 0, 0x0 },
+ { 0x0, 0x0, 0x1, 0, 0xb800000, 1, 0x0 },
+ { 0x0, 0x1, 0x0, 0, 0x20de0000, 3, 0xe0000 },
+ { 0x0, 0x1, 0x1, 0, 0x210e0000, 7, 0xe0000 },
+ { 0x0, 0x1, 0x2, 0, 0x20dc0000, 2, 0xc0000 },
+ { 0x0, 0x1, 0x3, 0, 0x210c0000, 6, 0xc0000 },
+ { 0x0, 0x1, 0x4, 0, 0x20d80000, 1, 0x80000 },
+ { 0x0, 0x1, 0x5, 0, 0x21080000, 5, 0x80000 },
+ { 0x0, 0x1, 0x6, 0, 0x20d00000, 0, 0x0 },
+ { 0x0, 0x1, 0x7, 0, 0x21000000, 4, 0x0 },
+ { 0x0, 0x2, 0x0, 0, 0xb040000, 0, 0x0 },
+ { 0x0, 0x2, 0x1, 0, 0xb840000, 1, 0x0 },
+ { 0x0, 0x3, 0x0, 0, 0xb230000, 0, 0x0 },
+ { 0x0, 0x3, 0x1, 0, 0xba30000, 1, 0x0 },
+ { 0x0, 0x4, 0x0, 0, 0xb050000, 0, 0x0 },
+ { 0x0, 0x4, 0x1, 0, 0xb850000, 1, 0x0 },
+ { 0x0, 0x5, 0x0, 0, 0xb060000, 0, 0x0 },
+ { 0x0, 0x5, 0x1, 0, 0xb070000, 1, 0x10000 },
+ { 0x0, 0x5, 0x2, 0, 0xb080000, 2, 0x20000 },
+ { 0x0, 0x5, 0x3, 0, 0xb090000, 3, 0x30000 },
+ { 0x0, 0x5, 0x4, 0, 0xb0a0000, 4, 0x40000 },
+ { 0x0, 0x5, 0x5, 0, 0xb0b0000, 5, 0x50000 },
+ { 0x0, 0x5, 0x6, 0, 0xb0c0000, 6, 0x60000 },
+ { 0x0, 0x5, 0x7, 0, 0xb0d0000, 7, 0x70000 },
+ { 0x0, 0x5, 0x8, 0, 0xb0e0000, 8, 0x80000 },
+ { 0x0, 0x5, 0x9, 0, 0xb860000, 9, 0x0 },
+ { 0x0, 0x5, 0xa, 0, 0xb870000, 10, 0x10000 },
+ { 0x0, 0x5, 0xb, 0, 0xb880000, 11, 0x20000 },
+ { 0x0, 0x5, 0xc, 0, 0xb890000, 12, 0x30000 },
+ { 0x0, 0x5, 0xd, 0, 0xb8a0000, 13, 0x40000 },
+ { 0x0, 0x5, 0xe, 0, 0xb8b0000, 14, 0x50000 },
+ { 0x0, 0x5, 0xf, 0, 0xb8c0000, 15, 0x60000 },
+ { 0x0, 0x5, 0x10, 0, 0xb8d0000, 16, 0x70000 },
+ { 0x0, 0x5, 0x11, 0, 0xb8e0000, 17, 0x80000 },
+ { 0x0, 0x6, 0x0, 0, 0xb650000, 0, 0x0 },
+ { 0x0, 0x6, 0x1, 0, 0xbe50000, 1, 0x0 },
+ { 0x0, 0x7, 0x0, 0, 0x20df0000, 0, 0x0 },
+ { 0x0, 0x7, 0x1, 0, 0x210f0000, 1, 0x0 },
+ { 0x0, 0x8, 0x0, 0, 0xb3e0000, 0, 0x0 },
+ { 0x0, 0x8, 0x1, 0, 0xbbe0000, 1, 0x0 },
+ { 0x0, 0x9, 0x0, 0, 0xb3d0000, 0, 0x0 },
+ { 0x0, 0x9, 0x1, 0, 0xbbd0000, 1, 0x0 },
+ { 0x0, 0xA, 0x0, 0, 0xb1e0000, 0, 0x0 },
+ { 0x0, 0xA, 0x1, 0, 0xb9e0000, 1, 0x0 },
+ { 0x0, 0xB, 0x0, 0, 0xb150000, 0, 0x0 },
+ { 0x0, 0xB, 0x1, 0, 0xb160000, 1, 0x10000 },
+ { 0x0, 0xB, 0x2, 0, 0xb170000, 2, 0x20000 },
+ { 0x0, 0xB, 0x3, 0, 0xb180000, 3, 0x30000 },
+ { 0x0, 0xB, 0x4, 0, 0xb190000, 4, 0x40000 },
+ { 0x0, 0xB, 0x5, 0, 0xb1a0000, 5, 0x50000 },
+ { 0x0, 0xB, 0x6, 0, 0xb1b0000, 6, 0x60000 },
+ { 0x0, 0xB, 0x7, 0, 0xb1c0000, 7, 0x70000 },
+ { 0x0, 0xB, 0x8, 0, 0xb1d0000, 8, 0x80000 },
+ { 0x0, 0xB, 0x9, 0, 0xb950000, 9, 0x0 },
+ { 0x0, 0xB, 0xa, 0, 0xb960000, 10, 0x10000 },
+ { 0x0, 0xB, 0xb, 0, 0xb970000, 11, 0x20000 },
+ { 0x0, 0xB, 0xc, 0, 0xb980000, 12, 0x30000 },
+ { 0x0, 0xB, 0xd, 0, 0xb990000, 13, 0x40000 },
+ { 0x0, 0xB, 0xe, 0, 0xb9a0000, 14, 0x50000 },
+ { 0x0, 0xB, 0xf, 0, 0xb9b0000, 15, 0x60000 },
+ { 0x0, 0xB, 0x10, 0, 0xb9c0000, 16, 0x70000 },
+ { 0x0, 0xB, 0x11, 0, 0xb9d0000, 17, 0x80000 },
+ { 0x0, 0xC, 0x0, 0, 0xb660000, 0, 0x0 },
+ { 0x0, 0xC, 0x1, 0, 0xbe60000, 1, 0x0 },
+ { 0x0, 0xD, 0x0, 0, 0xb1f0000, 0, 0x0 },
+ { 0x0, 0xD, 0x1, 0, 0xb200000, 1, 0x10000 },
+ { 0x0, 0xD, 0x2, 0, 0xb210000, 2, 0x20000 },
+ { 0x0, 0xD, 0x3, 0, 0xb220000, 3, 0x30000 },
+ { 0x0, 0xD, 0x4, 0, 0xb9f0000, 4, 0x0 },
+ { 0x0, 0xD, 0x5, 0, 0xba00000, 5, 0x10000 },
+ { 0x0, 0xD, 0x6, 0, 0xba10000, 6, 0x20000 },
+ { 0x0, 0xD, 0x7, 0, 0xba20000, 7, 0x30000 },
+ { 0x0, 0xE, 0x0, 0, 0xb0f0000, 0, 0x0 },
+ { 0x0, 0xE, 0x1, 0, 0xb100000, 1, 0x10000 },
+ { 0x0, 0xE, 0x2, 0, 0xb110000, 2, 0x20000 },
+ { 0x0, 0xE, 0x3, 0, 0xb120000, 3, 0x30000 },
+ { 0x0, 0xE, 0x4, 0, 0xb130000, 4, 0x40000 },
+ { 0x0, 0xE, 0x5, 0, 0xb140000, 5, 0x50000 },
+ { 0x0, 0xE, 0x6, 0, 0xb8f0000, 6, 0x0 },
+ { 0x0, 0xE, 0x7, 0, 0xb900000, 7, 0x10000 },
+ { 0x0, 0xE, 0x8, 0, 0xb910000, 8, 0x20000 },
+ { 0x0, 0xE, 0x9, 0, 0xb920000, 9, 0x30000 },
+ { 0x0, 0xE, 0xa, 0, 0xb930000, 10, 0x40000 },
+ { 0x0, 0xE, 0xb, 0, 0xb940000, 11, 0x50000 },
+ { 0x0, 0x10, 0x0, 0, 0xb240000, 0, 0x0 },
+ { 0x0, 0x10, 0x1, 0, 0xba40000, 1, 0x0 },
+ { 0x0, 0x11, 0x0, 0, 0xb020000, 0, 0x0 },
+ { 0x0, 0x11, 0x1, 0, 0xb820000, 1, 0x0 },
+ { 0x0, 0x12, 0x0, 0, 0xb030000, 0, 0x0 },
+ { 0x0, 0x12, 0x1, 0, 0xb830000, 1, 0x0 },
+ { 0x0, 0x17, 0x0, 0, 0xb640000, 0, 0x0 },
+ { 0x0, 0x17, 0x1, 0, 0xbe40000, 1, 0x0 },
+ { 0x0, 0x18, 0x0, 0, 0xb600000, 0, 0x0 },
+ { 0x0, 0x18, 0x1, 0, 0xbe00000, 1, 0x0 },
+ { 0x0, 0x18, 0x2, 0, 0x0, 0, 0x0 },
+ { 0x0, 0x18, 0x3, 0, 0x0, 0, 0x0 },
+ { 0x1, 0x13, 0x0, 0, 0x40000000, 0, 0x40000000 },
+ { 0x1, 0x13, 0x1, 1, 0x80000000, 1, 0x80000000 },
+ { 0x1, 0x13, 0x2, 0, 0x0, 0, 0x0 },
+ { 0x2, 0x15, 0x0, 0, 0x20c00000, 8, 0x20c00000 },
+ { 0x2, 0x15, 0x1, 0, 0x21100000, 22, 0x21100000 },
+ { 0x2, 0x15, 0x2, 0, 0x20e00000, 9, 0x20e00000 },
+ { 0x2, 0x15, 0x3, 0, 0x21200000, 23, 0x21200000 },
+ { 0x2, 0x15, 0x4, 0, 0x20800000, 7, 0x20800000 },
+ { 0x2, 0x15, 0x5, 0, 0x21400000, 24, 0x21400000 },
+ { 0x2, 0x15, 0x6, 0, 0xb000000, 18, 0xb000000 },
+ { 0x2, 0x15, 0x7, 0, 0xb800000, 3, 0xb800000 },
+ { 0x2, 0x15, 0x8, 0, 0x20000000, 6, 0x20000000 },
+ { 0x2, 0x15, 0x9, 0, 0x21800000, 25, 0x21800000 },
+ { 0x2, 0x15, 0xa, 0, 0xa000000, 2, 0xa000000 },
+ { 0x2, 0x15, 0xb, 0, 0xa000000, 17, 0xa000000 },
+ { 0x2, 0x15, 0xc, 0, 0x20000000, 21, 0x20000000 },
+ { 0x2, 0x15, 0xd, 0, 0x21000000, 10, 0x21000000 },
+ { 0x2, 0x15, 0xe, 0, 0x8000000, 1, 0x8000000 },
+ { 0x2, 0x15, 0xf, 0, 0x8000000, 16, 0x8000000 },
+ { 0x2, 0x15, 0x10, 0, 0x22000000, 11, 0x22000000 },
+ { 0x2, 0x15, 0x11, 0, 0x22000000, 26, 0x22000000 },
+ { 0x2, 0x15, 0x12, 0, 0xc000000, 4, 0xc000000 },
+ { 0x2, 0x15, 0x13, 0, 0xc000000, 19, 0xc000000 },
+ { 0x2, 0x15, 0x14, 0, 0x24000000, 12, 0x24000000 },
+ { 0x2, 0x15, 0x15, 0, 0x24000000, 27, 0x24000000 },
+ { 0x2, 0x15, 0x16, 0, 0x0, 0, 0x0 },
+ { 0x2, 0x15, 0x17, 0, 0x0, 15, 0x0 },
+ { 0x2, 0x15, 0x18, 0, 0x28000000, 13, 0x28000000 },
+ { 0x2, 0x15, 0x19, 0, 0x28000000, 28, 0x28000000 },
+ { 0x2, 0x15, 0x1a, 0, 0x10000000, 5, 0x10000000 },
+ { 0x2, 0x15, 0x1b, 0, 0x10000000, 20, 0x10000000 },
+ { 0x2, 0x15, 0x1c, 0, 0x30000000, 14, 0x30000000 },
+ { 0x2, 0x15, 0x1d, 0, 0x30000000, 29, 0x30000000 },
+ { 0x2, 0x0, 0x0, 0, 0xb000000, 0, 0x0 },
+ { 0x2, 0x0, 0x1, 0, 0xb800000, 1, 0x0 },
+ { 0x2, 0x1, 0x0, 0, 0x20de0000, 3, 0xe0000 },
+ { 0x2, 0x1, 0x1, 0, 0x210e0000, 7, 0xe0000 },
+ { 0x2, 0x1, 0x2, 0, 0x20dc0000, 2, 0xc0000 },
+ { 0x2, 0x1, 0x3, 0, 0x210c0000, 6, 0xc0000 },
+ { 0x2, 0x1, 0x4, 0, 0x20d80000, 1, 0x80000 },
+ { 0x2, 0x1, 0x5, 0, 0x21080000, 5, 0x80000 },
+ { 0x2, 0x1, 0x6, 0, 0x20d00000, 0, 0x0 },
+ { 0x2, 0x1, 0x7, 0, 0x21000000, 4, 0x0 },
+ { 0x2, 0x2, 0x0, 0, 0xb040000, 0, 0x0 },
+ { 0x2, 0x2, 0x1, 0, 0xb840000, 1, 0x0 },
+ { 0x2, 0x3, 0x0, 0, 0xb230000, 0, 0x0 },
+ { 0x2, 0x3, 0x1, 0, 0xba30000, 1, 0x0 },
+ { 0x2, 0x4, 0x0, 0, 0xb050000, 0, 0x0 },
+ { 0x2, 0x4, 0x1, 0, 0xb850000, 1, 0x0 },
+ { 0x2, 0x5, 0x0, 0, 0xb060000, 0, 0x0 },
+ { 0x2, 0x5, 0x1, 0, 0xb070000, 1, 0x10000 },
+ { 0x2, 0x5, 0x2, 0, 0xb080000, 2, 0x20000 },
+ { 0x2, 0x5, 0x3, 0, 0xb090000, 3, 0x30000 },
+ { 0x2, 0x5, 0x4, 0, 0xb0a0000, 4, 0x40000 },
+ { 0x2, 0x5, 0x5, 0, 0xb0b0000, 5, 0x50000 },
+ { 0x2, 0x5, 0x6, 0, 0xb0c0000, 6, 0x60000 },
+ { 0x2, 0x5, 0x7, 0, 0xb0d0000, 7, 0x70000 },
+ { 0x2, 0x5, 0x8, 0, 0xb0e0000, 8, 0x80000 },
+ { 0x2, 0x5, 0x9, 0, 0xb860000, 9, 0x0 },
+ { 0x2, 0x5, 0xa, 0, 0xb870000, 10, 0x10000 },
+ { 0x2, 0x5, 0xb, 0, 0xb880000, 11, 0x20000 },
+ { 0x2, 0x5, 0xc, 0, 0xb890000, 12, 0x30000 },
+ { 0x2, 0x5, 0xd, 0, 0xb8a0000, 13, 0x40000 },
+ { 0x2, 0x5, 0xe, 0, 0xb8b0000, 14, 0x50000 },
+ { 0x2, 0x5, 0xf, 0, 0xb8c0000, 15, 0x60000 },
+ { 0x2, 0x5, 0x10, 0, 0xb8d0000, 16, 0x70000 },
+ { 0x2, 0x5, 0x11, 0, 0xb8e0000, 17, 0x80000 },
+ { 0x2, 0x6, 0x0, 0, 0xb650000, 0, 0x0 },
+ { 0x2, 0x6, 0x1, 0, 0xbe50000, 1, 0x0 },
+ { 0x2, 0x7, 0x0, 0, 0x20df0000, 0, 0x0 },
+ { 0x2, 0x7, 0x1, 0, 0x210f0000, 1, 0x0 },
+ { 0x2, 0x8, 0x0, 0, 0xb3e0000, 0, 0x0 },
+ { 0x2, 0x8, 0x1, 0, 0xbbe0000, 1, 0x0 },
+ { 0x2, 0x9, 0x0, 0, 0xb3d0000, 0, 0x0 },
+ { 0x2, 0x9, 0x1, 0, 0xbbd0000, 1, 0x0 },
+ { 0x2, 0xA, 0x0, 0, 0xb1e0000, 0, 0x0 },
+ { 0x2, 0xA, 0x1, 0, 0xb9e0000, 1, 0x0 },
+ { 0x2, 0xB, 0x0, 0, 0xb150000, 0, 0x0 },
+ { 0x2, 0xB, 0x1, 0, 0xb160000, 1, 0x10000 },
+ { 0x2, 0xB, 0x2, 0, 0xb170000, 2, 0x20000 },
+ { 0x2, 0xB, 0x3, 0, 0xb180000, 3, 0x30000 },
+ { 0x2, 0xB, 0x4, 0, 0xb190000, 4, 0x40000 },
+ { 0x2, 0xB, 0x5, 0, 0xb1a0000, 5, 0x50000 },
+ { 0x2, 0xB, 0x6, 0, 0xb1b0000, 6, 0x60000 },
+ { 0x2, 0xB, 0x7, 0, 0xb1c0000, 7, 0x70000 },
+ { 0x2, 0xB, 0x8, 0, 0xb1d0000, 8, 0x80000 },
+ { 0x2, 0xB, 0x9, 0, 0xb950000, 9, 0x0 },
+ { 0x2, 0xB, 0xa, 0, 0xb960000, 10, 0x10000 },
+ { 0x2, 0xB, 0xb, 0, 0xb970000, 11, 0x20000 },
+ { 0x2, 0xB, 0xc, 0, 0xb980000, 12, 0x30000 },
+ { 0x2, 0xB, 0xd, 0, 0xb990000, 13, 0x40000 },
+ { 0x2, 0xB, 0xe, 0, 0xb9a0000, 14, 0x50000 },
+ { 0x2, 0xB, 0xf, 0, 0xb9b0000, 15, 0x60000 },
+ { 0x2, 0xB, 0x10, 0, 0xb9c0000, 16, 0x70000 },
+ { 0x2, 0xB, 0x11, 0, 0xb9d0000, 17, 0x80000 },
+ { 0x2, 0xC, 0x0, 0, 0xb660000, 0, 0x0 },
+ { 0x2, 0xC, 0x1, 0, 0xbe60000, 1, 0x0 },
+ { 0x2, 0xD, 0x0, 0, 0xb1f0000, 0, 0x0 },
+ { 0x2, 0xD, 0x1, 0, 0xb200000, 1, 0x10000 },
+ { 0x2, 0xD, 0x2, 0, 0xb210000, 2, 0x20000 },
+ { 0x2, 0xD, 0x3, 0, 0xb220000, 3, 0x30000 },
+ { 0x2, 0xD, 0x4, 0, 0xb9f0000, 4, 0x0 },
+ { 0x2, 0xD, 0x5, 0, 0xba00000, 5, 0x10000 },
+ { 0x2, 0xD, 0x6, 0, 0xba10000, 6, 0x20000 },
+ { 0x2, 0xD, 0x7, 0, 0xba20000, 7, 0x30000 },
+ { 0x2, 0xE, 0x0, 0, 0xb0f0000, 0, 0x0 },
+ { 0x2, 0xE, 0x1, 0, 0xb100000, 1, 0x10000 },
+ { 0x2, 0xE, 0x2, 0, 0xb110000, 2, 0x20000 },
+ { 0x2, 0xE, 0x3, 0, 0xb120000, 3, 0x30000 },
+ { 0x2, 0xE, 0x4, 0, 0xb130000, 4, 0x40000 },
+ { 0x2, 0xE, 0x5, 0, 0xb140000, 5, 0x50000 },
+ { 0x2, 0xE, 0x6, 0, 0xb8f0000, 6, 0x0 },
+ { 0x2, 0xE, 0x7, 0, 0xb900000, 7, 0x10000 },
+ { 0x2, 0xE, 0x8, 0, 0xb910000, 8, 0x20000 },
+ { 0x2, 0xE, 0x9, 0, 0xb920000, 9, 0x30000 },
+ { 0x2, 0xE, 0xa, 0, 0xb930000, 10, 0x40000 },
+ { 0x2, 0xE, 0xb, 0, 0xb940000, 11, 0x50000 },
+ { 0x2, 0x10, 0x0, 0, 0xb240000, 0, 0x0 },
+ { 0x2, 0x10, 0x1, 0, 0xba40000, 1, 0x0 },
+ { 0x2, 0x11, 0x0, 0, 0xb020000, 0, 0x0 },
+ { 0x2, 0x11, 0x1, 0, 0xb820000, 1, 0x0 },
+ { 0x2, 0x12, 0x0, 0, 0xb030000, 0, 0x0 },
+ { 0x2, 0x12, 0x1, 0, 0xb830000, 1, 0x0 },
+ { 0x2, 0x17, 0x0, 0, 0xb640000, 0, 0x0 },
+ { 0x2, 0x17, 0x1, 0, 0xbe40000, 1, 0x0 },
+ { 0x2, 0x18, 0x0, 0, 0xb600000, 0, 0x0 },
+ { 0x2, 0x18, 0x1, 0, 0xbe00000, 1, 0x0 },
+ { 0x2, 0x18, 0x2, 0, 0x0, 0, 0x0 },
+ { 0x2, 0x18, 0x3, 0, 0x0, 0, 0x0 },
+ { 0x3, 0x14, 0x0, 0, 0x40000000, 0, 0x40000000 },
+ { 0x3, 0x14, 0x1, 1, 0x80000000, 1, 0x80000000 },
+ { 0x3, 0x16, 0x0, 2, 0xb400000, 0, 0xb400000 },
+ { 0x3, 0x16, 0x1, 2, 0xbc00000, 1, 0xbc00000 },
+ { 0x3, 0x16, 0x2, 0, 0x0, 0, 0x0 },
+ { 0x3, 0x16, 0x3, 0, 0x0, 0, 0x0 },
+ { 0x4, 0x15, 0x0, 0, 0x20c00000, 8, 0x20c00000 },
+ { 0x4, 0x15, 0x1, 0, 0x21100000, 22, 0x21100000 },
+ { 0x4, 0x15, 0x2, 0, 0x20e00000, 9, 0x20e00000 },
+ { 0x4, 0x15, 0x3, 0, 0x21200000, 23, 0x21200000 },
+ { 0x4, 0x15, 0x4, 0, 0x20800000, 7, 0x20800000 },
+ { 0x4, 0x15, 0x5, 0, 0x21400000, 24, 0x21400000 },
+ { 0x4, 0x15, 0x6, 0, 0xb000000, 18, 0xb000000 },
+ { 0x4, 0x15, 0x7, 0, 0xb800000, 3, 0xb800000 },
+ { 0x4, 0x15, 0x8, 0, 0x20000000, 6, 0x20000000 },
+ { 0x4, 0x15, 0x9, 0, 0x21800000, 25, 0x21800000 },
+ { 0x4, 0x15, 0xa, 0, 0xa000000, 2, 0xa000000 },
+ { 0x4, 0x15, 0xb, 0, 0xa000000, 17, 0xa000000 },
+ { 0x4, 0x15, 0xc, 0, 0x20000000, 21, 0x20000000 },
+ { 0x4, 0x15, 0xd, 0, 0x21000000, 10, 0x21000000 },
+ { 0x4, 0x15, 0xe, 0, 0x8000000, 1, 0x8000000 },
+ { 0x4, 0x15, 0xf, 0, 0x8000000, 16, 0x8000000 },
+ { 0x4, 0x15, 0x10, 0, 0x22000000, 11, 0x22000000 },
+ { 0x4, 0x15, 0x11, 0, 0x22000000, 26, 0x22000000 },
+ { 0x4, 0x15, 0x12, 0, 0xc000000, 4, 0xc000000 },
+ { 0x4, 0x15, 0x13, 0, 0xc000000, 19, 0xc000000 },
+ { 0x4, 0x15, 0x14, 0, 0x24000000, 12, 0x24000000 },
+ { 0x4, 0x15, 0x15, 0, 0x24000000, 27, 0x24000000 },
+ { 0x4, 0x15, 0x16, 0, 0x0, 0, 0x0 },
+ { 0x4, 0x15, 0x17, 0, 0x0, 15, 0x0 },
+ { 0x4, 0x15, 0x18, 0, 0x28000000, 13, 0x28000000 },
+ { 0x4, 0x15, 0x19, 0, 0x28000000, 28, 0x28000000 },
+ { 0x4, 0x15, 0x1a, 0, 0x10000000, 5, 0x10000000 },
+ { 0x4, 0x15, 0x1b, 0, 0x10000000, 20, 0x10000000 },
+ { 0x4, 0x15, 0x1c, 0, 0x30000000, 14, 0x30000000 },
+ { 0x4, 0x15, 0x1d, 0, 0x30000000, 29, 0x30000000 },
+ { 0x4, 0x0, 0x0, 0, 0xb000000, 0, 0x0 },
+ { 0x4, 0x0, 0x1, 0, 0xb800000, 1, 0x0 },
+ { 0x4, 0x1, 0x0, 0, 0x20de0000, 3, 0xe0000 },
+ { 0x4, 0x1, 0x1, 0, 0x210e0000, 7, 0xe0000 },
+ { 0x4, 0x1, 0x2, 0, 0x20dc0000, 2, 0xc0000 },
+ { 0x4, 0x1, 0x3, 0, 0x210c0000, 6, 0xc0000 },
+ { 0x4, 0x1, 0x4, 0, 0x20d80000, 1, 0x80000 },
+ { 0x4, 0x1, 0x5, 0, 0x21080000, 5, 0x80000 },
+ { 0x4, 0x1, 0x6, 0, 0x20d00000, 0, 0x0 },
+ { 0x4, 0x1, 0x7, 0, 0x21000000, 4, 0x0 },
+ { 0x4, 0x2, 0x0, 0, 0xb040000, 0, 0x0 },
+ { 0x4, 0x2, 0x1, 0, 0xb840000, 1, 0x0 },
+ { 0x4, 0x3, 0x0, 0, 0xb230000, 0, 0x0 },
+ { 0x4, 0x3, 0x1, 0, 0xba30000, 1, 0x0 },
+ { 0x4, 0x4, 0x0, 0, 0xb050000, 0, 0x0 },
+ { 0x4, 0x4, 0x1, 0, 0xb850000, 1, 0x0 },
+ { 0x4, 0x5, 0x0, 0, 0xb060000, 0, 0x0 },
+ { 0x4, 0x5, 0x1, 0, 0xb070000, 1, 0x10000 },
+ { 0x4, 0x5, 0x2, 0, 0xb080000, 2, 0x20000 },
+ { 0x4, 0x5, 0x3, 0, 0xb090000, 3, 0x30000 },
+ { 0x4, 0x5, 0x4, 0, 0xb0a0000, 4, 0x40000 },
+ { 0x4, 0x5, 0x5, 0, 0xb0b0000, 5, 0x50000 },
+ { 0x4, 0x5, 0x6, 0, 0xb0c0000, 6, 0x60000 },
+ { 0x4, 0x5, 0x7, 0, 0xb0d0000, 7, 0x70000 },
+ { 0x4, 0x5, 0x8, 0, 0xb0e0000, 8, 0x80000 },
+ { 0x4, 0x5, 0x9, 0, 0xb860000, 9, 0x0 },
+ { 0x4, 0x5, 0xa, 0, 0xb870000, 10, 0x10000 },
+ { 0x4, 0x5, 0xb, 0, 0xb880000, 11, 0x20000 },
+ { 0x4, 0x5, 0xc, 0, 0xb890000, 12, 0x30000 },
+ { 0x4, 0x5, 0xd, 0, 0xb8a0000, 13, 0x40000 },
+ { 0x4, 0x5, 0xe, 0, 0xb8b0000, 14, 0x50000 },
+ { 0x4, 0x5, 0xf, 0, 0xb8c0000, 15, 0x60000 },
+ { 0x4, 0x5, 0x10, 0, 0xb8d0000, 16, 0x70000 },
+ { 0x4, 0x5, 0x11, 0, 0xb8e0000, 17, 0x80000 },
+ { 0x4, 0x6, 0x0, 0, 0xb650000, 0, 0x0 },
+ { 0x4, 0x6, 0x1, 0, 0xbe50000, 1, 0x0 },
+ { 0x4, 0x7, 0x0, 0, 0x20df0000, 0, 0x0 },
+ { 0x4, 0x7, 0x1, 0, 0x210f0000, 1, 0x0 },
+ { 0x4, 0x8, 0x0, 0, 0xb3e0000, 0, 0x0 },
+ { 0x4, 0x8, 0x1, 0, 0xbbe0000, 1, 0x0 },
+ { 0x4, 0x9, 0x0, 0, 0xb3d0000, 0, 0x0 },
+ { 0x4, 0x9, 0x1, 0, 0xbbd0000, 1, 0x0 },
+ { 0x4, 0xA, 0x0, 0, 0xb1e0000, 0, 0x0 },
+ { 0x4, 0xA, 0x1, 0, 0xb9e0000, 1, 0x0 },
+ { 0x4, 0xB, 0x0, 0, 0xb150000, 0, 0x0 },
+ { 0x4, 0xB, 0x1, 0, 0xb160000, 1, 0x10000 },
+ { 0x4, 0xB, 0x2, 0, 0xb170000, 2, 0x20000 },
+ { 0x4, 0xB, 0x3, 0, 0xb180000, 3, 0x30000 },
+ { 0x4, 0xB, 0x4, 0, 0xb190000, 4, 0x40000 },
+ { 0x4, 0xB, 0x5, 0, 0xb1a0000, 5, 0x50000 },
+ { 0x4, 0xB, 0x6, 0, 0xb1b0000, 6, 0x60000 },
+ { 0x4, 0xB, 0x7, 0, 0xb1c0000, 7, 0x70000 },
+ { 0x4, 0xB, 0x8, 0, 0xb1d0000, 8, 0x80000 },
+ { 0x4, 0xB, 0x9, 0, 0xb950000, 9, 0x0 },
+ { 0x4, 0xB, 0xa, 0, 0xb960000, 10, 0x10000 },
+ { 0x4, 0xB, 0xb, 0, 0xb970000, 11, 0x20000 },
+ { 0x4, 0xB, 0xc, 0, 0xb980000, 12, 0x30000 },
+ { 0x4, 0xB, 0xd, 0, 0xb990000, 13, 0x40000 },
+ { 0x4, 0xB, 0xe, 0, 0xb9a0000, 14, 0x50000 },
+ { 0x4, 0xB, 0xf, 0, 0xb9b0000, 15, 0x60000 },
+ { 0x4, 0xB, 0x10, 0, 0xb9c0000, 16, 0x70000 },
+ { 0x4, 0xB, 0x11, 0, 0xb9d0000, 17, 0x80000 },
+ { 0x4, 0xC, 0x0, 0, 0xb660000, 0, 0x0 },
+ { 0x4, 0xC, 0x1, 0, 0xbe60000, 1, 0x0 },
+ { 0x4, 0xD, 0x0, 0, 0xb1f0000, 0, 0x0 },
+ { 0x4, 0xD, 0x1, 0, 0xb200000, 1, 0x10000 },
+ { 0x4, 0xD, 0x2, 0, 0xb210000, 2, 0x20000 },
+ { 0x4, 0xD, 0x3, 0, 0xb220000, 3, 0x30000 },
+ { 0x4, 0xD, 0x4, 0, 0xb9f0000, 4, 0x0 },
+ { 0x4, 0xD, 0x5, 0, 0xba00000, 5, 0x10000 },
+ { 0x4, 0xD, 0x6, 0, 0xba10000, 6, 0x20000 },
+ { 0x4, 0xD, 0x7, 0, 0xba20000, 7, 0x30000 },
+ { 0x4, 0xE, 0x0, 0, 0xb0f0000, 0, 0x0 },
+ { 0x4, 0xE, 0x1, 0, 0xb100000, 1, 0x10000 },
+ { 0x4, 0xE, 0x2, 0, 0xb110000, 2, 0x20000 },
+ { 0x4, 0xE, 0x3, 0, 0xb120000, 3, 0x30000 },
+ { 0x4, 0xE, 0x4, 0, 0xb130000, 4, 0x40000 },
+ { 0x4, 0xE, 0x5, 0, 0xb140000, 5, 0x50000 },
+ { 0x4, 0xE, 0x6, 0, 0xb8f0000, 6, 0x0 },
+ { 0x4, 0xE, 0x7, 0, 0xb900000, 7, 0x10000 },
+ { 0x4, 0xE, 0x8, 0, 0xb910000, 8, 0x20000 },
+ { 0x4, 0xE, 0x9, 0, 0xb920000, 9, 0x30000 },
+ { 0x4, 0xE, 0xa, 0, 0xb930000, 10, 0x40000 },
+ { 0x4, 0xE, 0xb, 0, 0xb940000, 11, 0x50000 },
+ { 0x4, 0x10, 0x0, 0, 0xb240000, 0, 0x0 },
+ { 0x4, 0x10, 0x1, 0, 0xba40000, 1, 0x0 },
+ { 0x4, 0x11, 0x0, 0, 0xb020000, 0, 0x0 },
+ { 0x4, 0x11, 0x1, 0, 0xb820000, 1, 0x0 },
+ { 0x4, 0x12, 0x0, 0, 0xb030000, 0, 0x0 },
+ { 0x4, 0x12, 0x1, 0, 0xb830000, 1, 0x0 },
+ { 0x4, 0x17, 0x0, 0, 0xb640000, 0, 0x0 },
+ { 0x4, 0x17, 0x1, 0, 0xbe40000, 1, 0x0 },
+ { 0x4, 0x18, 0x0, 0, 0xb600000, 0, 0x0 },
+ { 0x4, 0x18, 0x1, 0, 0xbe00000, 1, 0x0 },
+ { 0x4, 0x18, 0x2, 0, 0x0, 0, 0x0 },
+ { 0x4, 0x18, 0x3, 0, 0x0, 0, 0x0 }
+};
+
+static void cbbcentralnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
+{
+ info->initflow = FIELD_GET(CBB_NOC_INITFLOW, routeid);
+ info->targflow = FIELD_GET(CBB_NOC_TARGFLOW, routeid);
+ info->targ_subrange = FIELD_GET(CBB_NOC_TARG_SUBRANGE, routeid);
+ info->seqid = FIELD_GET(CBB_NOC_SEQID, routeid);
+}
+
+static void bpmpnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
+{
+ info->initflow = FIELD_GET(BPMP_NOC_INITFLOW, routeid);
+ info->targflow = FIELD_GET(BPMP_NOC_TARGFLOW, routeid);
+ info->targ_subrange = FIELD_GET(BPMP_NOC_TARG_SUBRANGE, routeid);
+ info->seqid = FIELD_GET(BPMP_NOC_SEQID, routeid);
+}
+
+static void aonnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
+{
+ info->initflow = FIELD_GET(AON_NOC_INITFLOW, routeid);
+ info->targflow = FIELD_GET(AON_NOC_TARGFLOW, routeid);
+ info->targ_subrange = FIELD_GET(AON_NOC_TARG_SUBRANGE, routeid);
+ info->seqid = FIELD_GET(AON_NOC_SEQID, routeid);
+}
+
+static void scenoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
+{
+ info->initflow = FIELD_GET(SCE_NOC_INITFLOW, routeid);
+ info->targflow = FIELD_GET(SCE_NOC_TARGFLOW, routeid);
+ info->targ_subrange = FIELD_GET(SCE_NOC_TARG_SUBRANGE, routeid);
+ info->seqid = FIELD_GET(SCE_NOC_SEQID, routeid);
+}
+
+static void cbbcentralnoc_parse_userbits(struct tegra194_cbb_userbits *usrbits, u32 elog_5)
+{
+ usrbits->axcache = FIELD_GET(CBB_NOC_AXCACHE, elog_5);
+ usrbits->non_mod = FIELD_GET(CBB_NOC_NON_MOD, elog_5);
+ usrbits->axprot = FIELD_GET(CBB_NOC_AXPROT, elog_5);
+ usrbits->falconsec = FIELD_GET(CBB_NOC_FALCONSEC, elog_5);
+ usrbits->grpsec = FIELD_GET(CBB_NOC_GRPSEC, elog_5);
+ usrbits->vqc = FIELD_GET(CBB_NOC_VQC, elog_5);
+ usrbits->mstr_id = FIELD_GET(CBB_NOC_MSTR_ID, elog_5) - 1;
+ usrbits->axi_id = FIELD_GET(CBB_NOC_AXI_ID, elog_5);
+}
+
+static void clusternoc_parse_userbits(struct tegra194_cbb_userbits *usrbits, u32 elog_5)
+{
+ usrbits->axcache = FIELD_GET(CLUSTER_NOC_AXCACHE, elog_5);
+ usrbits->axprot = FIELD_GET(CLUSTER_NOC_AXCACHE, elog_5);
+ usrbits->falconsec = FIELD_GET(CLUSTER_NOC_FALCONSEC, elog_5);
+ usrbits->grpsec = FIELD_GET(CLUSTER_NOC_GRPSEC, elog_5);
+ usrbits->vqc = FIELD_GET(CLUSTER_NOC_VQC, elog_5);
+ usrbits->mstr_id = FIELD_GET(CLUSTER_NOC_MSTR_ID, elog_5) - 1;
+}
+
+static void tegra194_cbb_faulten(struct tegra_cbb *cbb)
+{
+ void __iomem *addr = ((struct tegra_cbb_errlog_record *)cbb->err_rec)->vaddr;
+
+ writel(1, addr + ERRLOGGER_0_FAULTEN_0);
+ writel(1, addr + ERRLOGGER_1_FAULTEN_0);
+ writel(1, addr + ERRLOGGER_2_FAULTEN_0);
+}
+
+static void tegra194_cbb_stallen(struct tegra_cbb *cbb)
+{
+ void __iomem *addr = ((struct tegra_cbb_errlog_record *)cbb->err_rec)->vaddr;
+
+ writel(1, addr + ERRLOGGER_0_STALLEN_0);
+ writel(1, addr + ERRLOGGER_1_STALLEN_0);
+ writel(1, addr + ERRLOGGER_2_STALLEN_0);
+}
+
+static void tegra194_cbb_errclr(struct tegra_cbb *cbb)
+{
+ void __iomem *addr = ((struct tegra_cbb_errlog_record *)cbb->err_rec)->vaddr;
+
+ writel(1, addr + ERRLOGGER_0_ERRCLR_0);
+ writel(1, addr + ERRLOGGER_1_ERRCLR_0);
+ writel(1, addr + ERRLOGGER_2_ERRCLR_0);
+ dsb(sy);
+}
+
+static u32 tegra194_cbb_errvld(struct tegra_cbb *cbb)
+{
+ void __iomem *addr = ((struct tegra_cbb_errlog_record *)cbb->err_rec)->vaddr;
+ u32 value = 0;
+
+ value = readl(addr + ERRLOGGER_0_ERRVLD_0);
+ value |= (readl(addr + ERRLOGGER_1_ERRVLD_0) << 1);
+ value |= (readl(addr + ERRLOGGER_2_ERRVLD_0) << 2);
+
+ dsb(sy);
+ return value;
+}
+
+static u32 tegra194_axi2apb_errstatus(void __iomem *addr)
+{
+ u32 value = 0;
+
+ value = readl(addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
+ writel(0xFFFFFFFF, addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
+ return value;
+}
+
+static bool tegra194_axi2apb_err(struct seq_file *file, int bridge, u32 status)
+{
+ size_t max = ARRAY_SIZE(t194_axi2apb_err);
+ bool is_fatal = true;
+ int j = 0;
+
+ for (j = 0; j < max; j++) {
+ if (status & (1 << j)) {
+ tegra_cbb_print_err(file, "\t AXI2APB_%d bridge error: %s\n",
+ bridge + 1, t194_axi2apb_err[j]);
+ if (strstr(t194_axi2apb_err[j], "Firewall"))
+ is_fatal = false;
+ }
+ }
+ return is_fatal;
+}
+
+/*
+ * Fetch InitlocalAddress from NOC Aperture lookup table
+ * using Targflow, Targsubrange
+ */
+static u32 get_init_localaddress(const struct tegra194_cbb_aperture *info,
+ const struct tegra194_cbb_aperture *aper, int max)
+{
+ int t_f = 0, t_sr = 0;
+ u32 i_locaddr = 0;
+ int targflow = info->targflow;
+ int targ_subrange = info->targ_subrange;
+
+ for (t_f = 0; t_f < max; t_f++) {
+ if (aper[t_f].targflow == targflow) {
+ t_sr = t_f;
+ do {
+ if (aper[t_sr].targ_subrange == targ_subrange) {
+ i_locaddr = aper[t_sr].init_localaddress;
+ return i_locaddr;
+ }
+ if (t_sr >= max)
+ return 0;
+ t_sr++;
+ } while (aper[t_sr].targflow == aper[t_sr - 1].targflow);
+ t_f = t_sr;
+ }
+ }
+
+ return i_locaddr;
+}
+
+static void print_errlog5(struct seq_file *file, struct tegra_cbb_errlog_record *errlog)
+{
+ struct tegra194_cbb_userbits userbits;
+ u32 errlog5 = errlog->errlog5;
+
+ errlog->noc_parse_userbits(&userbits, errlog5);
+ if (!strcmp(errlog->name, "cbb-noc")) {
+ tegra_cbb_print_err(file, "\t Non-Modify\t\t: 0x%x\n", userbits.non_mod);
+ tegra_cbb_print_err(file, "\t AXI ID\t\t: 0x%x\n", userbits.axi_id);
+ }
+
+ tegra_cbb_print_err(file, "\t Master ID\t\t: %s\n",
+ errlog->cbb_master_id[userbits.mstr_id]);
+ tegra_cbb_print_err(file, "\t Security Group(GRPSEC): 0x%x\n", userbits.grpsec);
+ tegra_cbb_print_cache(file, userbits.axcache);
+ tegra_cbb_print_prot(file, userbits.axprot);
+ tegra_cbb_print_err(file, "\t FALCONSEC\t\t: 0x%x\n", userbits.falconsec);
+ tegra_cbb_print_err(file, "\t Virtual Queuing Channel(VQC): 0x%x\n", userbits.vqc);
+}
+
+/*
+ * Fetch Base Address/InitlocalAddress from NOC aperture lookup table
+ * using TargFlow & Targ_subRange extracted from RouteId.
+ * Perform address reconstruction as below:
+ * Address = Base Address + (ErrLog3+ErrLog4)
+ */
+static void
+print_errlog3_4(struct seq_file *file, u32 errlog3, u32 errlog4,
+ const struct tegra194_cbb_aperture *trans_info,
+ const struct tegra194_cbb_aperture *noc_aperture, int max)
+{
+ u64 addr = 0;
+
+ addr = errlog4;
+ addr = (addr << 32) | errlog3;
+
+ /*
+ * if errlog4[7]="1", then it's a joker entry.
+ * joker entry is a rare phenomenon and address is not reliable.
+ * debug should be done using the routeid information alone.
+ */
+ if (errlog4 & 0x80)
+ tegra_cbb_print_err(file, "\t debug using routeid alone as below"
+ " address is a joker entry and notreliable");
+
+ addr += get_init_localaddress(trans_info, noc_aperture, max);
+
+ tegra_cbb_print_err(file, "\t Address accessed\t: 0x%llx\n", addr);
+}
+
+/*
+ * Get RouteId from ErrLog1+ErrLog2 registers and fetch values of
+ * InitFlow, TargFlow, Targ_subRange and SeqId values from RouteId
+ */
+static void
+print_errlog1_2(struct seq_file *file, struct tegra_cbb_errlog_record *errlog,
+ struct tegra194_cbb_aperture *info)
+{
+ u64 routeid = 0;
+ u32 seqid = 0;
+
+ routeid = errlog->errlog2;
+ routeid = (routeid << 32) | errlog->errlog1;
+ tegra_cbb_print_err(file, "\t RouteId\t\t: 0x%llx\n", routeid);
+
+ errlog->noc_parse_routeid(info, routeid);
+
+ tegra_cbb_print_err(file, "\t InitFlow\t\t: %s\n",
+ errlog->noc_routeid_initflow[info->initflow]);
+
+ tegra_cbb_print_err(file, "\t Targflow\t\t: %s\n",
+ errlog->noc_routeid_targflow[info->targflow]);
+
+ tegra_cbb_print_err(file, "\t TargSubRange\t\t: %d\n", info->targ_subrange);
+ tegra_cbb_print_err(file, "\t SeqId\t\t\t: %d\n", seqid);
+}
+
+/*
+ * Print transcation type, error code and description from ErrLog0 for all
+ * errors. For NOC slave errors, all relevant error info is printed using
+ * ErrLog0 only. But additional information is printed for errors from
+ * APB slaves because for them:
+ * - All errors are logged as SLV(slave) errors due to APB having only single
+ * bit pslverr to report all errors.
+ * - Exact cause is printed by reading DMAAPB_X_RAW_INTERRUPT_STATUS register.
+ * - The driver prints information showing AXI2APB bridge and exact error
+ * only if there is error in any AXI2APB slave.
+ * - There is still no way to disambiguate a DEC error from SLV error type.
+ */
+static bool print_errlog0(struct seq_file *file,
+ struct tegra_cbb_errlog_record *errlog)
+{
+ struct tegra194_cbb_packet_header hdr;
+ bool is_fatal = true;
+
+ hdr.lock = errlog->errlog0 & 0x1;
+ hdr.opc = FIELD_GET(CBB_ERR_OPC, errlog->errlog0);
+ hdr.errcode = FIELD_GET(CBB_ERR_ERRCODE, errlog->errlog0);
+ hdr.len1 = FIELD_GET(CBB_ERR_LEN1, errlog->errlog0);
+ hdr.format = (errlog->errlog0 >> 31);
+
+ tegra_cbb_print_err(file, "\t Transaction Type\t: %s\n",
+ t194_cbb_trantype[hdr.opc]);
+ tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
+ t194_noc_errors[hdr.errcode].errcode);
+ tegra_cbb_print_err(file, "\t Error Source\t\t: %s\n",
+ t194_noc_errors[hdr.errcode].src);
+ tegra_cbb_print_err(file, "\t Error Description\t: %s\n",
+ t194_noc_errors[hdr.errcode].type);
+ /*
+ * Donot crash system for errors which are only notifications
+ * to indicate a transaction was not allowed to be attempted.
+ */
+
+ if (!strcmp(t194_noc_errors[hdr.errcode].errcode, "SEC") ||
+ !strcmp(t194_noc_errors[hdr.errcode].errcode, "DEC") ||
+ !strcmp(t194_noc_errors[hdr.errcode].errcode, "UNS") ||
+ !strcmp(t194_noc_errors[hdr.errcode].errcode, "DISC")
+ )
+ is_fatal = false;
+ else if (!strcmp(t194_noc_errors[hdr.errcode].errcode, "SLV") &&
+ errlog->is_ax2apb_bridge_connected) {
+ int i = 0;
+ u32 status = 0;
+
+ /* For all SLV errors, read DMAAPB_X_RAW_INTERRUPT_STATUS
+ * register to get error status for all AXI2APB bridges.
+ * Print bridge details if a bit is set in a bridge's
+ * status register due to error in a APB slave connected
+ * to that bridge. For other NOC slaves, none of the status
+ * register will be set.
+ */
+
+ for (i = 0; i < errlog->apb_bridge_cnt; i++) {
+ status = tegra194_axi2apb_errstatus(errlog->axi2abp_bases[i]);
+
+ if (status)
+ is_fatal = tegra194_axi2apb_err(file, i, status);
+ }
+ }
+ tegra_cbb_print_err(file, "\t Packet header Lock\t: %d\n", hdr.lock);
+ tegra_cbb_print_err(file, "\t Packet header Len1\t: %d\n", hdr.len1);
+ if (hdr.format)
+ tegra_cbb_print_err(file, "\t NOC protocol version\t: %s\n",
+ "version >= 2.7");
+ else
+ tegra_cbb_print_err(file, "\t NOC protocol version\t: %s\n",
+ "version < 2.7");
+ return is_fatal;
+}
+
+/*
+ * Print debug information about failed transaction using
+ * ErrLog registers of error loggger having ErrVld set
+ */
+static bool print_errloggerX_info(struct seq_file *file,
+ struct tegra_cbb_errlog_record *errlog,
+ int errloggerX)
+{
+ struct tegra194_cbb_aperture info = {0,};
+ bool is_fatal = true;
+
+ tegra_cbb_print_err(file, "\tError Logger\t\t: %d\n", errloggerX);
+ if (errloggerX == 0) {
+ errlog->errlog0 = readl(errlog->vaddr + ERRLOGGER_0_ERRLOG0_0);
+ errlog->errlog1 = readl(errlog->vaddr + ERRLOGGER_0_ERRLOG1_0);
+ errlog->errlog2 = readl(errlog->vaddr + ERRLOGGER_0_RSVD_00_0);
+ errlog->errlog3 = readl(errlog->vaddr + ERRLOGGER_0_ERRLOG3_0);
+ errlog->errlog4 = readl(errlog->vaddr + ERRLOGGER_0_ERRLOG4_0);
+ errlog->errlog5 = readl(errlog->vaddr + ERRLOGGER_0_ERRLOG5_0);
+ } else if (errloggerX == 1) {
+ errlog->errlog0 = readl(errlog->vaddr + ERRLOGGER_1_ERRLOG0_0);
+ errlog->errlog1 = readl(errlog->vaddr + ERRLOGGER_1_ERRLOG1_0);
+ errlog->errlog2 = readl(errlog->vaddr + ERRLOGGER_1_RSVD_00_0);
+ errlog->errlog3 = readl(errlog->vaddr + ERRLOGGER_1_ERRLOG3_0);
+ errlog->errlog4 = readl(errlog->vaddr + ERRLOGGER_1_ERRLOG4_0);
+ errlog->errlog5 = readl(errlog->vaddr + ERRLOGGER_1_ERRLOG5_0);
+ } else if (errloggerX == 2) {
+ errlog->errlog0 = readl(errlog->vaddr + ERRLOGGER_2_ERRLOG0_0);
+ errlog->errlog1 = readl(errlog->vaddr + ERRLOGGER_2_ERRLOG1_0);
+ errlog->errlog2 = readl(errlog->vaddr + ERRLOGGER_2_RSVD_00_0);
+ errlog->errlog3 = readl(errlog->vaddr + ERRLOGGER_2_ERRLOG3_0);
+ errlog->errlog4 = readl(errlog->vaddr + ERRLOGGER_2_ERRLOG4_0);
+ errlog->errlog5 = readl(errlog->vaddr + ERRLOGGER_2_ERRLOG5_0);
+ }
+
+ tegra_cbb_print_err(file, "\tErrLog0\t\t\t: 0x%x\n", errlog->errlog0);
+ is_fatal = print_errlog0(file, errlog);
+
+ tegra_cbb_print_err(file, "\tErrLog1\t\t\t: 0x%x\n", errlog->errlog1);
+ tegra_cbb_print_err(file, "\tErrLog2\t\t\t: 0x%x\n", errlog->errlog2);
+ print_errlog1_2(file, errlog, &info);
+
+ tegra_cbb_print_err(file, "\tErrLog3\t\t\t: 0x%x\n", errlog->errlog3);
+ tegra_cbb_print_err(file, "\tErrLog4\t\t\t: 0x%x\n", errlog->errlog4);
+ print_errlog3_4(file, errlog->errlog3, errlog->errlog4,
+ &info, errlog->noc_aperture, errlog->max_aperture);
+
+ tegra_cbb_print_err(file, "\tErrLog5\t\t\t: 0x%x\n", errlog->errlog5);
+ if (errlog->errlog5)
+ print_errlog5(file, errlog);
+ return is_fatal;
+}
+
+static bool print_errlog(struct seq_file *file, struct tegra_cbb *cbb,
+ struct tegra_cbb_errlog_record *errlog, u32 errvld)
+{
+ bool is_fatal = true;
+
+ pr_crit("**************************************\n");
+ pr_crit("CPU:%d, Error:%s\n", smp_processor_id(), errlog->name);
+
+ if (errvld & 0x1)
+ is_fatal = print_errloggerX_info(file, errlog, 0);
+ else if (errvld & 0x2)
+ is_fatal = print_errloggerX_info(file, errlog, 1);
+ else if (errvld & 0x4)
+ is_fatal = print_errloggerX_info(file, errlog, 2);
+
+ tegra_cbb_errclr(cbb);
+ tegra_cbb_print_err(file, "\t**************************************\n");
+ return is_fatal;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static DEFINE_MUTEX(cbb_err_mutex);
+
+static int tegra194_cbb_err_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
+{
+ struct tegra_cbb_errlog_record *errlog;
+ u32 errvld = 0;
+
+ mutex_lock(&cbb_err_mutex);
+
+ list_for_each_entry(errlog, &cbb_noc_list, node) {
+ cbb = errlog->cbb;
+ errvld = tegra_cbb_errvld(cbb);
+ if (errvld)
+ print_errlog(file, cbb, errlog, errvld);
+ }
+
+ mutex_unlock(&cbb_err_mutex);
+ return 0;
+}
+#endif
+
+/*
+ * Handler for CBB errors from different initiators
+ */
+static irqreturn_t tegra194_cbb_err_isr(int irq, void *data)
+{
+ bool is_inband_err = false, is_fatal = false;
+ struct tegra_cbb_errlog_record *errlog;
+ struct tegra_cbb *cbb = data;
+ unsigned int errvld = 0;
+ unsigned long flags;
+ u8 mstr_id = 0;
+
+ spin_lock_irqsave(&cbb_noc_lock, flags);
+
+ list_for_each_entry(errlog, &cbb_noc_list, node) {
+ errvld = tegra_cbb_errvld(cbb);
+
+ if (errvld && ((irq == errlog->sec_irq) ||
+ (irq == errlog->nonsec_irq))) {
+ tegra_cbb_print_err(NULL, "CPU:%d, Error:%s@0x%llx,irq=%d\n",
+ smp_processor_id(), errlog->name,
+ errlog->start, irq);
+
+ is_fatal = print_errlog(NULL, cbb, errlog, errvld);
+
+ mstr_id = FIELD_GET(USRBITS_MSTR_ID, errlog->errlog5) - 1;
+ /*
+ * If illegal request is from CCPLEX(0x1)
+ * initiator then call BUG() to crash system.
+ */
+ if ((mstr_id == 0x1) && errlog->erd_mask_inband_err)
+ is_inband_err = 1;
+ }
+ }
+ spin_unlock_irqrestore(&cbb_noc_lock, flags);
+
+ if (is_inband_err) {
+ if (is_fatal)
+ BUG();
+ else
+ WARN(true, "Warning due to CBB Error\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Register handler for CBB_NONSECURE & CBB_SECURE interrupts
+ * for reporting CBB errors
+ */
+static int tegra194_cbb_intr_en(struct tegra_cbb *cbb)
+{
+ struct platform_device *pdev = cbb->pdev;
+ int sec_irq, nonsec_irq;
+ int err = 0;
+
+ sec_irq = ((struct tegra_cbb_errlog_record *)cbb->err_rec)->sec_irq;
+ nonsec_irq = ((struct tegra_cbb_errlog_record *)cbb->err_rec)->nonsec_irq;
+ if (sec_irq) {
+ err = devm_request_irq(&pdev->dev, sec_irq, tegra194_cbb_err_isr,
+ 0, dev_name(&pdev->dev), cbb);
+ if (err) {
+ dev_err(&pdev->dev, "%s: Unable to register (%d) interrupt\n",
+ __func__, sec_irq);
+ goto isr_err_free_sec_irq;
+ }
+ }
+ if (nonsec_irq) {
+ err = devm_request_irq(&pdev->dev, nonsec_irq, tegra194_cbb_err_isr,
+ 0, dev_name(&pdev->dev), cbb);
+ if (err) {
+ dev_err(&pdev->dev, "%s: Unable to register (%d) interrupt\n",
+ __func__, nonsec_irq);
+ goto isr_err_free_nonsec_irq;
+ }
+ }
+
+ return 0;
+
+isr_err_free_nonsec_irq:
+ if (nonsec_irq)
+ free_irq(nonsec_irq, pdev);
+isr_err_free_sec_irq:
+ if (sec_irq)
+ free_irq(sec_irq, pdev);
+
+ return err;
+}
+
+static void tegra194_cbb_err_en(struct tegra_cbb *cbb)
+{
+ /*
+ * Set “StallEn=1” to enable queuing of error packets till
+ * first is served & cleared
+ */
+ tegra_cbb_stallen(cbb);
+
+ /* set “FaultEn=1” to enable error reporting signal “Fault” */
+ tegra_cbb_faulten(cbb);
+}
+
+static struct tegra_cbb_err_ops tegra194_cbb_errlogger_ops = {
+ .errvld = tegra194_cbb_errvld,
+ .errclr = tegra194_cbb_errclr,
+ .faulten = tegra194_cbb_faulten,
+ .stallen = tegra194_cbb_stallen,
+ .cbb_err_enable = tegra194_cbb_err_en,
+ .cbb_intr_enable = tegra194_cbb_intr_en,
+#ifdef CONFIG_DEBUG_FS
+ .cbb_err_debugfs_show = tegra194_cbb_err_show,
+#endif
+};
+
+static struct tegra_cbb_noc_data tegra194_cbb_central_noc_data = {
+ .name = "cbb-noc",
+ .erd_mask_inband_err = true,
+ .cbb_master_id = t194_master_id,
+ .noc_aperture = t194_cbbcentralnoc_apert_lookup,
+ .max_aperture = ARRAY_SIZE(t194_cbbcentralnoc_apert_lookup),
+ .noc_routeid_initflow = t194_cbbcentralnoc_routeid_initflow,
+ .noc_routeid_targflow = t194_cbbcentralnoc_routeid_targflow,
+ .noc_parse_routeid = cbbcentralnoc_parse_routeid,
+ .noc_parse_userbits = cbbcentralnoc_parse_userbits
+};
+
+static struct tegra_cbb_noc_data tegra194_aon_noc_data = {
+ .name = "aon-noc",
+ .erd_mask_inband_err = false,
+ .cbb_master_id = t194_master_id,
+ .noc_aperture = t194_aonnoc_aperture_lookup,
+ .max_aperture = ARRAY_SIZE(t194_aonnoc_aperture_lookup),
+ .noc_routeid_initflow = t194_aonnoc_routeid_initflow,
+ .noc_routeid_targflow = t194_aonnoc_routeid_targflow,
+ .noc_parse_routeid = aonnoc_parse_routeid,
+ .noc_parse_userbits = clusternoc_parse_userbits
+};
+
+static struct tegra_cbb_noc_data tegra194_bpmp_noc_data = {
+ .name = "bpmp-noc",
+ .erd_mask_inband_err = false,
+ .cbb_master_id = t194_master_id,
+ .noc_aperture = t194_bpmpnoc_apert_lookup,
+ .max_aperture = ARRAY_SIZE(t194_bpmpnoc_apert_lookup),
+ .noc_routeid_initflow = t194_bpmpnoc_routeid_initflow,
+ .noc_routeid_targflow = t194_bpmpnoc_routeid_targflow,
+ .noc_parse_routeid = bpmpnoc_parse_routeid,
+ .noc_parse_userbits = clusternoc_parse_userbits
+};
+
+static struct tegra_cbb_noc_data tegra194_rce_noc_data = {
+ .name = "rce-noc",
+ .erd_mask_inband_err = false,
+ .cbb_master_id = t194_master_id,
+ .noc_aperture = t194_scenoc_apert_lookup,
+ .max_aperture = ARRAY_SIZE(t194_scenoc_apert_lookup),
+ .noc_routeid_initflow = t194_scenoc_routeid_initflow,
+ .noc_routeid_targflow = t194_scenoc_routeid_targflow,
+ .noc_parse_routeid = scenoc_parse_routeid,
+ .noc_parse_userbits = clusternoc_parse_userbits
+};
+
+static struct tegra_cbb_noc_data tegra194_sce_noc_data = {
+ .name = "sce-noc",
+ .erd_mask_inband_err = false,
+ .cbb_master_id = t194_master_id,
+ .noc_aperture = t194_scenoc_apert_lookup,
+ .max_aperture = ARRAY_SIZE(t194_scenoc_apert_lookup),
+ .noc_routeid_initflow = t194_scenoc_routeid_initflow,
+ .noc_routeid_targflow = t194_scenoc_routeid_targflow,
+ .noc_parse_routeid = scenoc_parse_routeid,
+ .noc_parse_userbits = clusternoc_parse_userbits
+};
+
+static const struct of_device_id tegra194_cbb_match[] = {
+ {.compatible = "nvidia,tegra194-cbb-noc",
+ .data = &tegra194_cbb_central_noc_data},
+ {.compatible = "nvidia,tegra194-aon-noc",
+ .data = &tegra194_aon_noc_data},
+ {.compatible = "nvidia,tegra194-bpmp-noc",
+ .data = &tegra194_bpmp_noc_data},
+ {.compatible = "nvidia,tegra194-rce-noc",
+ .data = &tegra194_rce_noc_data},
+ {.compatible = "nvidia,tegra194-sce-noc",
+ .data = &tegra194_sce_noc_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, tegra194_cbb_match);
+
+static int
+tegra194_cbb_get_axi2apb_data(struct platform_device *pdev, struct device_node *np,
+ int *apb_bridge_cnt, void __iomem ***bases)
+{
+ static void __iomem **axi2apb_bases;
+ int i = 0;
+
+ if (axi2apb_bases) {
+ *bases = axi2apb_bases;
+ return 0;
+ }
+
+ *apb_bridge_cnt = (of_property_count_elems_of_size(np, "reg", sizeof(u32))) / 4;
+
+ axi2apb_bases = devm_kzalloc(&pdev->dev, sizeof(void *) * (*apb_bridge_cnt), GFP_KERNEL);
+ if (!axi2apb_bases)
+ return -ENOMEM;
+
+ for (i = 0; i < *apb_bridge_cnt; i++) {
+ void __iomem *base = of_iomap(np, i);
+
+ if (!base) {
+ dev_err(&pdev->dev, "failed to map axi2apb range\n");
+ return -ENOENT;
+ }
+ axi2apb_bases[i] = base;
+ }
+ *bases = axi2apb_bases;
+
+ return 0;
+}
+
+static int
+tegra194_cbb_errlogger_init(const struct tegra_cbb_noc_data *pdata,
+ struct tegra_cbb *cbb, struct resource *res_base)
+{
+ struct platform_device *pdev = cbb->pdev;
+ struct tegra_cbb_errlog_record *errlog;
+ struct device_node *np = NULL;
+ unsigned long flags = 0;
+ int err = 0;
+
+ errlog = (struct tegra_cbb_errlog_record *)cbb->err_rec;
+ errlog->vaddr = devm_ioremap_resource(&pdev->dev, res_base);
+ if (IS_ERR(errlog->vaddr))
+ return -EINVAL;
+
+ errlog->name = pdata->name;
+ errlog->start = res_base->start;
+ errlog->erd_mask_inband_err = pdata->erd_mask_inband_err;
+ errlog->cbb_master_id = pdata->cbb_master_id;
+ errlog->noc_aperture = pdata->noc_aperture;
+ errlog->max_aperture = pdata->max_aperture;
+ errlog->noc_routeid_initflow = pdata->noc_routeid_initflow;
+ errlog->noc_routeid_targflow = pdata->noc_routeid_targflow;
+ errlog->noc_parse_routeid = pdata->noc_parse_routeid;
+ errlog->noc_parse_userbits = pdata->noc_parse_userbits;
+ errlog->cbb = cbb;
+
+ np = of_parse_phandle(pdev->dev.of_node, "nvidia,axi2apb", 0);
+ if (np) {
+ errlog->is_ax2apb_bridge_connected = 1;
+ dev_info(&pdev->dev, "axi2apb bridge info present\n");
+
+ err = tegra194_cbb_get_axi2apb_data(pdev, np,
+ &(errlog->apb_bridge_cnt),
+ &(errlog->axi2abp_bases));
+ if (err) {
+ dev_err(&pdev->dev, "axi2apb bridge read failed\n");
+ return err;
+ }
+ }
+
+ err = tegra_cbb_err_getirq(pdev, &errlog->nonsec_irq, &errlog->sec_irq);
+ if (err)
+ return err;
+
+ cbb->ops = &tegra194_cbb_errlogger_ops;
+
+ spin_lock_irqsave(&cbb_noc_lock, flags);
+ list_add(&errlog->node, &cbb_noc_list);
+ spin_unlock_irqrestore(&cbb_noc_lock, flags);
+
+ return 0;
+};
+
+static int tegra194_cbb_probe(struct platform_device *pdev)
+{
+ struct tegra_cbb_errlog_record *errlog = NULL;
+ const struct tegra_cbb_noc_data *pdata;
+ struct resource *res_base;
+ struct tegra_cbb *cbb;
+ int err = 0;
+
+ pdata = of_device_get_match_data(&pdev->dev);
+ if (!pdata) {
+ dev_err(&pdev->dev, "No device match found\n");
+ return -EINVAL;
+ }
+
+ if (pdata->erd_mask_inband_err) {
+ /*
+ * Set Error Response Disable(ERD) bit to mask SError/inband
+ * error and only trigger interrupts for illegal access from
+ * CCPLEX initiator.
+ */
+ err = tegra194_miscreg_mask_serror();
+ if (err) {
+ dev_err(&pdev->dev, "couldn't mask inband errors\n");
+ return err;
+ }
+ }
+
+ res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res_base) {
+ dev_err(&pdev->dev, "Could not find base address");
+ return -ENOENT;
+ }
+
+ cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
+ if (!cbb)
+ return -ENOMEM;
+
+ errlog = devm_kzalloc(&pdev->dev, sizeof(*errlog), GFP_KERNEL);
+ if (!errlog)
+ return -ENOMEM;
+
+ cbb->err_rec = errlog;
+ cbb->pdev = pdev;
+ err = tegra194_cbb_errlogger_init(pdata, cbb, res_base);
+ if (err) {
+ dev_err(&pdev->dev, "cbberr init for soc failing\n");
+ return err;
+ }
+
+ platform_set_drvdata(pdev, cbb);
+
+ return tegra_cbb_register_isr_enaberr(cbb);
+}
+
+static int tegra194_cbb_remove(struct platform_device *pdev)
+{
+ struct tegra_cbb_errlog_record *errlog, *el_noc, *temp_el;
+ struct tegra_cbb *cbb;
+ unsigned long flags;
+
+ cbb = platform_get_drvdata(pdev);
+ if (!cbb)
+ return -EINVAL;
+
+ errlog = (struct tegra_cbb_errlog_record *)cbb->err_rec;
+
+ spin_lock_irqsave(&cbb_noc_lock, flags);
+ list_for_each_entry_safe(el_noc, temp_el, &cbb_noc_list, node) {
+ if (errlog->start == el_noc->start) {
+ list_del(&el_noc->node);
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&cbb_noc_lock, flags);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra194_cbb_resume_noirq(struct device *dev)
+{
+ struct tegra_cbb *cbb = dev_get_drvdata(dev);
+ struct tegra_cbb_errlog_record *errlog;
+
+ errlog = (struct tegra_cbb_errlog_record *)cbb->err_rec;
+
+ if (!errlog)
+ return -EINVAL;
+
+ tegra194_cbb_err_en(cbb);
+ dsb(sy);
+
+ dev_info(dev, "%s resumed\n", errlog->name);
+ return 0;
+}
+
+static const struct dev_pm_ops tegra194_cbb_pm = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra194_cbb_resume_noirq)
+};
+#endif
+
+static struct platform_driver tegra194_cbb_driver = {
+ .probe = tegra194_cbb_probe,
+ .remove = tegra194_cbb_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tegra19x-cbb",
+ .of_match_table = of_match_ptr(tegra194_cbb_match),
+#ifdef CONFIG_PM_SLEEP
+ .pm = &tegra194_cbb_pm,
+#endif
+ },
+};
+
+static int __init tegra194_cbb_init(void)
+{
+ return platform_driver_register(&tegra194_cbb_driver);
+}
+
+static void __exit tegra194_cbb_exit(void)
+{
+ platform_driver_unregister(&tegra194_cbb_driver);
+}
+
+pure_initcall(tegra194_cbb_init);
+module_exit(tegra194_cbb_exit);
+
+MODULE_AUTHOR("Sumit Gupta <sumitg@nvidia.com>");
+MODULE_DESCRIPTION("Control Backbone error handling driver for Tegra194");
+MODULE_LICENSE("GPL v2");
diff --git a/include/soc/tegra/tegra-cbb.h b/include/soc/tegra/tegra-cbb.h
new file mode 100644
index 000000000000..a9ddc6d53aee
--- /dev/null
+++ b/include/soc/tegra/tegra-cbb.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ */
+
+#ifndef __TEGRA_CBBERR_H
+#define __TEGRA_CBBERR_H
+
+struct tegra_noc_errors {
+ char *errcode;
+ char *src;
+ char *type;
+};
+
+struct tegra_cbb {
+ struct tegra_cbb_err_ops *ops;
+ struct platform_device *pdev;
+ void *err_rec;
+};
+
+struct tegra_cbb_err_ops {
+ int (*cbb_err_debugfs_show)(struct tegra_cbb *cbb, struct seq_file *s, void *v);
+ int (*cbb_intr_enable)(struct tegra_cbb *cbb);
+ void (*cbb_err_enable)(struct tegra_cbb *cbb);
+ void (*faulten)(struct tegra_cbb *cbb);
+ void (*stallen)(struct tegra_cbb *cbb);
+ void (*errclr)(struct tegra_cbb *cbb);
+ u32 (*errvld)(struct tegra_cbb *cbb);
+};
+
+int tegra_cbb_err_getirq(struct platform_device *pdev, int *nonsec_irq, int *sec_irq);
+__printf(2, 3) void tegra_cbb_print_err(struct seq_file *file, const char *fmt, ...);
+
+void tegra_cbb_print_cache(struct seq_file *file, u32 cache);
+void tegra_cbb_print_prot(struct seq_file *file, u32 prot);
+int tegra_cbb_register_isr_enaberr(struct tegra_cbb *cbb);
+
+void tegra_cbb_faulten(struct tegra_cbb *cbb);
+void tegra_cbb_stallen(struct tegra_cbb *cbb);
+void tegra_cbb_errclr(struct tegra_cbb *cbb);
+u32 tegra_cbb_errvld(struct tegra_cbb *cbb);
+
+#endif /* __TEGRA_CBBERR_H */
diff --git a/include/soc/tegra/tegra194-cbb.h b/include/soc/tegra/tegra194-cbb.h
new file mode 100644
index 000000000000..4b0dec239954
--- /dev/null
+++ b/include/soc/tegra/tegra194-cbb.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ */
+
+#define ERRLOGGER_0_ID_COREID_0 0x00000000
+#define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
+#define ERRLOGGER_0_FAULTEN_0 0x00000008
+#define ERRLOGGER_0_ERRVLD_0 0x0000000c
+#define ERRLOGGER_0_ERRCLR_0 0x00000010
+#define ERRLOGGER_0_ERRLOG0_0 0x00000014
+#define ERRLOGGER_0_ERRLOG1_0 0x00000018
+#define ERRLOGGER_0_RSVD_00_0 0x0000001c
+#define ERRLOGGER_0_ERRLOG3_0 0x00000020
+#define ERRLOGGER_0_ERRLOG4_0 0x00000024
+#define ERRLOGGER_0_ERRLOG5_0 0x00000028
+#define ERRLOGGER_0_STALLEN_0 0x00000038
+
+#define ERRLOGGER_1_ID_COREID_0 0x00000080
+#define ERRLOGGER_1_ID_REVISIONID_0 0x00000084
+#define ERRLOGGER_1_FAULTEN_0 0x00000088
+#define ERRLOGGER_1_ERRVLD_0 0x0000008c
+#define ERRLOGGER_1_ERRCLR_0 0x00000090
+#define ERRLOGGER_1_ERRLOG0_0 0x00000094
+#define ERRLOGGER_1_ERRLOG1_0 0x00000098
+#define ERRLOGGER_1_RSVD_00_0 0x0000009c
+#define ERRLOGGER_1_ERRLOG3_0 0x000000A0
+#define ERRLOGGER_1_ERRLOG4_0 0x000000A4
+#define ERRLOGGER_1_ERRLOG5_0 0x000000A8
+#define ERRLOGGER_1_STALLEN_0 0x000000b8
+
+#define ERRLOGGER_2_ID_COREID_0 0x00000100
+#define ERRLOGGER_2_ID_REVISIONID_0 0x00000104
+#define ERRLOGGER_2_FAULTEN_0 0x00000108
+#define ERRLOGGER_2_ERRVLD_0 0x0000010c
+#define ERRLOGGER_2_ERRCLR_0 0x00000110
+#define ERRLOGGER_2_ERRLOG0_0 0x00000114
+#define ERRLOGGER_2_ERRLOG1_0 0x00000118
+#define ERRLOGGER_2_RSVD_00_0 0x0000011c
+#define ERRLOGGER_2_ERRLOG3_0 0x00000120
+#define ERRLOGGER_2_ERRLOG4_0 0x00000124
+#define ERRLOGGER_2_ERRLOG5_0 0x00000128
+#define ERRLOGGER_2_STALLEN_0 0x00000138
+
+
+#define CBB_NOC_INITFLOW GENMASK(23, 20)
+#define CBB_NOC_TARGFLOW GENMASK(19, 16)
+#define CBB_NOC_TARG_SUBRANGE GENMASK(15, 9)
+#define CBB_NOC_SEQID GENMASK(8, 0)
+
+#define BPMP_NOC_INITFLOW GENMASK(20, 18)
+#define BPMP_NOC_TARGFLOW GENMASK(17, 13)
+#define BPMP_NOC_TARG_SUBRANGE GENMASK(12, 9)
+#define BPMP_NOC_SEQID GENMASK(8, 0)
+
+#define AON_NOC_INITFLOW GENMASK(22, 21)
+#define AON_NOC_TARGFLOW GENMASK(20, 15)
+#define AON_NOC_TARG_SUBRANGE GENMASK(14, 9)
+#define AON_NOC_SEQID GENMASK(8, 0)
+
+#define SCE_NOC_INITFLOW GENMASK(21, 19)
+#define SCE_NOC_TARGFLOW GENMASK(18, 14)
+#define SCE_NOC_TARG_SUBRANGE GENMASK(13, 9)
+#define SCE_NOC_SEQID GENMASK(8, 0)
+
+#define CBB_NOC_AXCACHE GENMASK(3, 0)
+#define CBB_NOC_NON_MOD GENMASK(4, 4)
+#define CBB_NOC_AXPROT GENMASK(7, 5)
+#define CBB_NOC_FALCONSEC GENMASK(9, 8)
+#define CBB_NOC_GRPSEC GENMASK(16, 10)
+#define CBB_NOC_VQC GENMASK(18, 17)
+#define CBB_NOC_MSTR_ID GENMASK(22, 19)
+#define CBB_NOC_AXI_ID GENMASK(30, 23)
+
+#define CLUSTER_NOC_AXCACHE GENMASK(3, 0)
+#define CLUSTER_NOC_AXPROT GENMASK(6, 4)
+#define CLUSTER_NOC_FALCONSEC GENMASK(8, 7)
+#define CLUSTER_NOC_GRPSEC GENMASK(15, 9)
+#define CLUSTER_NOC_VQC GENMASK(17, 16)
+#define CLUSTER_NOC_MSTR_ID GENMASK(21, 18)
+
+#define USRBITS_MSTR_ID GENMASK(21, 18)
+
+#define CBB_ERR_OPC GENMASK(4, 1)
+#define CBB_ERR_ERRCODE GENMASK(10, 8)
+#define CBB_ERR_LEN1 GENMASK(27, 16)
+
+#define DMAAPB_X_RAW_INTERRUPT_STATUS 0x2ec
+
+struct tegra194_cbb_packet_header {
+ bool lock; // [0]
+ u8 opc; // [4:1]
+ u8 errcode;// [10:8]= RD, RDW, RDL, RDX, WR, WRW, WRC, PRE, URG
+ u16 len1; // [27:16]
+ bool format; // [31] = 1 -> FlexNoC versions 2.7 & above
+};
+
+struct tegra194_cbb_aperture {
+ u8 initflow;
+ u8 targflow;
+ u8 targ_subrange;
+ u8 init_mapping;
+ u32 init_localaddress;
+ u8 targ_mapping;
+ u32 targ_localaddress;
+ u16 seqid;
+};
+
+struct tegra194_cbb_userbits {
+ u8 axcache;
+ u8 non_mod;
+ u8 axprot;
+ u8 falconsec;
+ u8 grpsec;
+ u8 vqc;
+ u8 mstr_id;
+ u8 axi_id;
+};
+
+struct tegra_cbb_noc_data {
+ char *name;
+ bool erd_mask_inband_err;
+ const char **cbb_master_id;
+ int max_aperture;
+ const struct tegra194_cbb_aperture *noc_aperture;
+ char **noc_routeid_initflow;
+ char **noc_routeid_targflow;
+ void (*noc_parse_routeid)(struct tegra194_cbb_aperture *info, u64 routeid);
+ void (*noc_parse_userbits)(struct tegra194_cbb_userbits *usrbits, u32 elog_5);
+};
+
+struct tegra_cbb_errlog_record {
+ struct list_head node;
+ char *name;
+ phys_addr_t start;
+ void __iomem *vaddr;
+ int num_intr;
+ int sec_irq;
+ int nonsec_irq;
+ u32 errlog0;
+ u32 errlog1;
+ u32 errlog2;
+ u32 errlog3;
+ u32 errlog4;
+ u32 errlog5;
+ int apb_bridge_cnt;
+ void __iomem **axi2abp_bases;
+ bool is_ax2apb_bridge_connected;
+ bool erd_mask_inband_err;
+ const char **cbb_master_id;
+ struct tegra_cbb *cbb;
+ int max_aperture;
+ const struct tegra194_cbb_aperture *noc_aperture;
+ char **noc_routeid_initflow;
+ char **noc_routeid_targflow;
+ void (*noc_parse_routeid)(struct tegra194_cbb_aperture *info, u64 routeid);
+ void (*noc_parse_userbits)(struct tegra194_cbb_userbits *usrbits, u32 elog_5);
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 6/9] dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB2.0 binding
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
` (4 preceding siblings ...)
2021-12-21 12:51 ` [Patch v3 5/9] soc: tegra: cbb: Add CBB1.0 driver for Tegra194 Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 7/9] arm64: tegra: Add node for CBB2.0 in Tegra234 SOC Sumit Gupta
` (2 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Add device-tree binding documentation to represent CBB2.0 (Control
Backbone) error handling driver. The driver prints debug information
about failed transaction on receiving interrupt from CBB2.0.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
.../arm/tegra/nvidia,tegra234-cbb.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
new file mode 100644
index 000000000000..fa4383be19d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra CBB 2.0 Error handling driver device tree bindings
+
+maintainers:
+ - Sumit Gupta <sumitg@nvidia.com>
+
+description: |+
+ The Control Backbone (CBB) is comprised of the physical path from an initiator to a target's
+ register configuration space. CBB 2.0 consists of multiple sub-blocks connected to each other
+ to create a topology. The Tegra234 SoC has different fabrics based on CBB2.0 architecture which
+ include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and "CBB central fabric".
+
+ In CBB 2.0, each initiator which can issue transactions connects to a Root Master Node (MN)
+ before it connects to any other element of the fabric. Each Root MN contains a Error Monitor
+ (EM) which detects and logs error. Interrupts from various EM blocks are collated by Error
+ Notifier (EN) which is per fabric and presents a single interrupt from fabric to the SoC
+ interrupt controller.
+
+ The driver handles errors from CBB due to illegal register accesses and prints debug information
+ about failed transaction on receiving the interrupt from EN. Debug information includes Error
+ Code, Error Description, MasterID, Fabric, SlaveID, Address, Cache, Protection, Security Group
+ etc on receiving error notification.
+
+ If the Error Response Disable (ERD) is set/enabled for an initiator, then SError or Data abort
+ exception error response is masked and an interrupt is used for reporting errors due to illegal
+ accesses from that initiator. The value returned on read failures is '0xFFFFFFFF' for
+ compatibility with PCIE.
+
+properties:
+ $nodename:
+ pattern: "^[a-z]+-fabric@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - nvidia,tegra234-aon-fabric
+ - nvidia,tegra234-bpmp-fabric
+ - nvidia,tegra234-cbb-fabric
+ - nvidia,tegra234-dce-fabric
+ - nvidia,tegra234-rce-fabric
+ - nvidia,tegra234-sce-fabric
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: secure interrupt from error notifier
+
+additionalProperties: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ cbb-fabric@1300000 {
+ compatible = "nvidia,tegra234-cbb-fabric";
+ reg = <0x13a00000 0x400000>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 7/9] arm64: tegra: Add node for CBB2.0 in Tegra234 SOC
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
` (5 preceding siblings ...)
2021-12-21 12:51 ` [Patch v3 6/9] dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB2.0 binding Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 8/9] soc: tegra: cbb: Add driver for Tegra234 CBB2.0 Sumit Gupta
2021-12-21 12:51 ` [Patch v3 9/9] soc: tegra: cbb: Add support for tegra-grace SOC Sumit Gupta
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Control Backbone(CBB) version 2.0 is used in Tegra234 SOC.
Adding nodes to enable handling of errors from different
CBB 2.0 based fabrics in Tegra234 SOC.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 42 ++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index f0efb3a62804..400403343529 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -73,6 +73,20 @@
#mbox-cells = <2>;
};
+ sce-fabric@b600000 {
+ compatible = "nvidia,tegra234-sce-fabric";
+ reg = <0xb600000 0x40000>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
+ rce-fabric@be00000 {
+ compatible = "nvidia,tegra234-rce-fabric";
+ reg = <0xbe00000 0x40000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
@@ -109,6 +123,27 @@
interrupt-controller;
};
+ aon-fabric@c600000 {
+ compatible = "nvidia,tegra234-aon-fabric";
+ reg = <0xc600000 0x40000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
+ bpmp-fabric@d600000 {
+ compatible = "nvidia,tegra234-bpmp-fabric";
+ reg = <0xd600000 0x40000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
+ dce-fabric@de00000 {
+ compatible = "nvidia,tegra234-sce-fabric";
+ reg = <0xde00000 0x40000>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
gic: interrupt-controller@f400000 {
compatible = "arm,gic-v3";
reg = <0x0f400000 0x010000>, /* GICD */
@@ -120,6 +155,13 @@
#interrupt-cells = <3>;
interrupt-controller;
};
+
+ cbb-fabric@0x13a00000 {
+ compatible = "nvidia,tegra234-cbb-fabric";
+ reg = <0x13a00000 0x400000>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
};
sysram@40000000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 8/9] soc: tegra: cbb: Add driver for Tegra234 CBB2.0
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
` (6 preceding siblings ...)
2021-12-21 12:51 ` [Patch v3 7/9] arm64: tegra: Add node for CBB2.0 in Tegra234 SOC Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 9/9] soc: tegra: cbb: Add support for tegra-grace SOC Sumit Gupta
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Adding driver to handle errors from CBB version 2.0 which is
used in Tegra234 SOC. The driver prints debug information about
failed transaction on receiving interrupt from Error Notifier.
Error notifier collates the interrupts from various Error
Monitor blocks and presents a single interrupt to the SOC
Interrupt Controller.
For timeout errors, the driver also does the lookup to find
timedout clients and prints client id. The IP's who want to
reset if there is a timeout will have to call BPMP from the
client IP's driver. BPMP firmware will also clear the timeout
bit after resetting the IP so that next transactions are send
to them after reset.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/soc/tegra/Kconfig | 2 +-
drivers/soc/tegra/cbb/Makefile | 1 +
drivers/soc/tegra/cbb/tegra234-cbb.c | 741 +++++++++++++++++++++++++++
include/soc/tegra/tegra234-cbb.h | 342 +++++++++++++
4 files changed, 1085 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/tegra/cbb/tegra234-cbb.c
create mode 100644 include/soc/tegra/tegra234-cbb.h
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 0520b9744ec4..f0cf6a33cb5b 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -164,7 +164,7 @@ config SOC_TEGRA30_VOLTAGE_COUPLER
config SOC_TEGRA_CBB
tristate "Tegra driver to handle error from CBB"
- depends on ARCH_TEGRA_194_SOC
+ depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
default y
help
Support for handling error from Tegra Control Backbone(CBB).
diff --git a/drivers/soc/tegra/cbb/Makefile b/drivers/soc/tegra/cbb/Makefile
index 3f9ff6575628..71877d20651f 100644
--- a/drivers/soc/tegra/cbb/Makefile
+++ b/drivers/soc/tegra/cbb/Makefile
@@ -5,4 +5,5 @@
ifdef CONFIG_SOC_TEGRA_CBB
obj-y += tegra-cbb.o
obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-cbb.o
+obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-cbb.o
endif
diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c
new file mode 100644
index 000000000000..56069eb8dc2b
--- /dev/null
+++ b/drivers/soc/tegra/cbb/tegra234-cbb.c
@@ -0,0 +1,741 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ *
+ * The driver handles Error's from Control Backbone(CBB) version 2.0.
+ * generated due to illegal accesses. The driver prints debug information
+ * about failed transaction on receiving interrupt from Error Notifier.
+ * Error types supported by CBB2.0 are:
+ * UNSUPPORTED_ERR, PWRDOWN_ERR, TIMEOUT_ERR, FIREWALL_ERR, DECODE_ERR,
+ * SLAVE_ERR
+ */
+
+#include <asm/cpufeature.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/version.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/tegra-cbb.h>
+#include <soc/tegra/tegra234-cbb.h>
+
+static LIST_HEAD(cbb_errmon_list);
+static DEFINE_SPINLOCK(cbb_errmon_lock);
+
+static void tegra234_cbb_errmon_faulten(struct tegra_cbb *cbb)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ void __iomem *addr;
+
+ errmon = (struct tegra_cbb_errmon_record *)cbb->err_rec;
+
+ addr = errmon->vaddr + errmon->err_notifier_base;
+ writel(0x1FF, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
+ dsb(sy);
+}
+
+static void tegra234_cbb_errmon_errclr(struct tegra_cbb *cbb)
+{
+ void __iomem *addr;
+
+ addr = ((struct tegra_cbb_errmon_record *)cbb->err_rec)->addr_errmon;
+
+ writel(0x3F, addr + FABRIC_MN_MASTER_ERR_STATUS_0);
+ dsb(sy);
+}
+
+static u32 tegra234_cbb_errmon_errvld(struct tegra_cbb *cbb)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ void __iomem *addr;
+ u32 errvld;
+
+ errmon = (struct tegra_cbb_errmon_record *)cbb->err_rec;
+
+ addr = errmon->vaddr + errmon->err_notifier_base;
+ errvld = readl(addr + FABRIC_EN_CFG_STATUS_0_0);
+ dsb(sy);
+
+ return errvld;
+}
+
+static void tegra234_cbb_mn_mask_serror(struct tegra_cbb *cbb)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ void __iomem *erd_mask;
+
+ errmon = (struct tegra_cbb_errmon_record *)cbb->err_rec;
+
+ erd_mask = errmon->vaddr + errmon->off_mask_erd;
+ writel(0x1, erd_mask);
+ dsb(sy);
+}
+
+u32 tegra234_cbb_readl(unsigned long offset)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ bool flag = 0;
+ u32 val = 0;
+
+ if (offset > 0x3FFFFF) {
+ pr_err("%s: wrong offset value\n", __func__);
+ return 0;
+ }
+
+ list_for_each_entry(errmon, &cbb_errmon_list, node) {
+ if (strstr(errmon->name, "cbb")) {
+ val = readl(errmon->vaddr + offset);
+ flag = true;
+ break;
+ }
+ }
+ if (!flag)
+ pr_err("%s: cbb fabric not initialized\n", __func__);
+
+ return val;
+}
+EXPORT_SYMBOL(tegra234_cbb_readl);
+
+void tegra234_cbb_writel(unsigned long offset, u32 val)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ bool flag = 0;
+
+ if (offset > 0x3FFFFF) {
+ pr_err("%s: wrong offset value\n", __func__);
+ return;
+ }
+
+ list_for_each_entry(errmon, &cbb_errmon_list, node) {
+ if (strstr(errmon->name, "cbb")) {
+ writel(val, errmon->vaddr + offset);
+ flag = true;
+ break;
+ }
+ }
+ if (!flag)
+ pr_err("%s: cbb fabric not initialized\n", __func__);
+}
+EXPORT_SYMBOL(tegra234_cbb_writel);
+
+static u32 tegra234_cbb_get_tmo_slv(void __iomem *addr)
+{
+ u32 timeout;
+
+ timeout = readl(addr);
+ return timeout;
+}
+
+static void tegra234_cbb_tmo_slv(struct seq_file *file, char *slv_name,
+ void __iomem *addr, u32 tmo_status)
+{
+ tegra_cbb_print_err(file, "\t %s : 0x%x\n", slv_name, tmo_status);
+}
+
+static void tegra234_cbb_lookup_apbslv(struct seq_file *file, char *slave_name, u64 addr)
+{
+ unsigned int blkno_tmo_status, tmo_status;
+ unsigned int reset_client, client_id;
+ char slv_name[40];
+ int block_num = 0;
+
+ tmo_status = tegra234_cbb_get_tmo_slv((void __iomem *)addr);
+ if (tmo_status)
+ tegra_cbb_print_err(file, "\t %s_BLOCK_TMO_STATUS : 0x%x\n",
+ slave_name, tmo_status);
+
+ while (tmo_status) {
+ if (!(tmo_status & BIT(0)))
+ goto next_iter;
+
+ addr = addr + APB_BLOCK_NUM_TMO_OFFSET + (block_num * 4);
+ blkno_tmo_status = tegra234_cbb_get_tmo_slv((void __iomem *)addr);
+ reset_client = blkno_tmo_status;
+
+ if (blkno_tmo_status) {
+ client_id = 1;
+ while (blkno_tmo_status) {
+ if (blkno_tmo_status & 0x1) {
+ if (reset_client != 0xffffffff)
+ reset_client &= client_id;
+
+ sprintf(slv_name, "%s_BLOCK%d_TMO", slave_name, block_num);
+
+ tegra234_cbb_tmo_slv(file, slv_name, (void __iomem *)addr,
+ reset_client);
+ }
+ blkno_tmo_status >>= 1;
+ client_id <<= 1;
+ }
+ }
+next_iter:
+ tmo_status >>= 1;
+ block_num++;
+ }
+}
+
+static void tegra234_lookup_slave_timeout(struct seq_file *file,
+ struct tegra_cbb_errmon_record *errmon,
+ u8 slave_id, u8 fab_id)
+{
+ struct tegra_sn_addr_map *sn_lookup = errmon->sn_addr_map;
+ void __iomem *base_addr = errmon->vaddr;
+ unsigned int tmo_status;
+ char slv_name[40];
+ int i = slave_id;
+ u64 addr = 0;
+
+ /*
+ * 1) Get slave node name and address mapping using slave_id.
+ * 2) Check if the timed out slave node is APB or AXI.
+ * 3) If AXI, then print timeout register and reset axi slave
+ * using <FABRIC>_SN_<>_SLV_TIMEOUT_STATUS_0_0 register.
+ * 4) If APB, then perform an additional lookup to find the client
+ * which timed out.
+ * a) Get block number from the index of set bit in
+ * <FABRIC>_SN_AXI2APB_<>_BLOCK_TMO_STATUS_0 register.
+ * b) Get address of register repective to block number i.e.
+ * <FABRIC>_SN_AXI2APB_<>_BLOCK<index-set-bit>_TMO_0.
+ * c) Read the register in above step to get client_id which
+ * timed out as per the set bits.
+ * d) Reset the timedout client and print details.
+ * e) Goto step-a till all bits are set.
+ */
+
+ addr = (u64)base_addr + sn_lookup[i].off_slave;
+
+ if (strstr(sn_lookup[i].slave_name, "AXI2APB")) {
+ addr = addr + APB_BLOCK_TMO_STATUS_0;
+ tegra234_cbb_lookup_apbslv(file, sn_lookup[i].slave_name, addr);
+ } else {
+ addr = addr + AXI_SLV_TIMEOUT_STATUS_0_0;
+
+ tmo_status = tegra234_cbb_get_tmo_slv((void __iomem *)addr);
+ if (tmo_status) {
+ sprintf(slv_name, "%s_SLV_TIMEOUT_STATUS", sn_lookup[i].slave_name);
+ tegra234_cbb_tmo_slv(file, slv_name, (void __iomem *)addr, tmo_status);
+ }
+ }
+}
+
+static void print_errmon_err(struct seq_file *file, struct tegra_cbb_errmon_record *errmon,
+ unsigned int em_err_status, unsigned int em_overflow_status)
+{
+ int err_type = 0;
+
+ if (em_err_status & (em_err_status - 1))
+ tegra_cbb_print_err(file, "\t Multiple type of errors reported\n");
+
+ while (em_err_status) {
+ if (em_err_status & 0x1)
+ tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
+ t234_errmon_errors[err_type].errcode);
+ em_err_status >>= 1;
+ err_type++;
+ }
+
+ err_type = 0;
+ while (em_overflow_status) {
+ if (em_overflow_status & 0x1)
+ tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n",
+ t234_errmon_errors[err_type].errcode);
+ em_overflow_status >>= 1;
+ err_type++;
+ }
+}
+
+static void print_errlog_err(struct seq_file *file, struct tegra_cbb_errmon_record *errmon)
+{
+ u8 cache_type = 0, prot_type = 0, burst_length = 0;
+ u8 mstr_id = 0, grpsec = 0, vqc = 0, falconsec = 0;
+ u8 beat_size = 0, access_type = 0, access_id = 0;
+ u8 slave_id = 0, fab_id = 0, burst_type = 0;
+ char fabric_name[20];
+
+ mstr_id = FIELD_GET(FAB_EM_EL_MSTRID, errmon->mn_user_bits);
+ vqc = FIELD_GET(FAB_EM_EL_VQC, errmon->mn_user_bits);
+ grpsec = FIELD_GET(FAB_EM_EL_GRPSEC, errmon->mn_user_bits);
+ falconsec = FIELD_GET(FAB_EM_EL_FALCONSEC, errmon->mn_user_bits);
+
+ fab_id = FIELD_GET(FAB_EM_EL_FABID, errmon->mn_attr2);
+ slave_id = FIELD_GET(FAB_EM_EL_SLAVEID, errmon->mn_attr2);
+
+ access_id = FIELD_GET(FAB_EM_EL_ACCESSID, errmon->mn_attr1);
+
+ cache_type = FIELD_GET(FAB_EM_EL_AXCACHE, errmon->mn_attr0);
+ prot_type = FIELD_GET(FAB_EM_EL_AXPROT, errmon->mn_attr0);
+ burst_length = FIELD_GET(FAB_EM_EL_BURSTLENGTH, errmon->mn_attr0);
+ burst_type = FIELD_GET(FAB_EM_EL_BURSTTYPE, errmon->mn_attr0);
+ beat_size = FIELD_GET(FAB_EM_EL_BEATSIZE, errmon->mn_attr0);
+ access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, errmon->mn_attr0);
+
+ tegra_cbb_print_err(file, "\n");
+ tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
+ t234_errmon_errors[errmon->err_type].errcode);
+
+ tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", errmon->tegra_cbb_master_id[mstr_id]);
+ tegra_cbb_print_err(file, "\t Address\t\t: 0x%llx\n", (u64)errmon->addr_access);
+
+ tegra_cbb_print_cache(file, cache_type);
+ tegra_cbb_print_prot(file, prot_type);
+
+ tegra_cbb_print_err(file, "\t Access_Type\t\t: %s", (access_type) ? "Write\n" : "Read\n");
+ tegra_cbb_print_err(file, "\t Access_ID\t\t: 0x%x", access_id);
+
+ if (fab_id == PSC_FAB_ID)
+ strcpy(fabric_name, "psc-fabric");
+ else if (fab_id == FSI_FAB_ID)
+ strcpy(fabric_name, "fsi-fabric");
+ else
+ strcpy(fabric_name, errmon->name);
+
+ tegra_cbb_print_err(file, "\t Fabric\t\t: %s\n", fabric_name);
+ tegra_cbb_print_err(file, "\t Slave_Id\t\t: 0x%x\n", slave_id);
+ tegra_cbb_print_err(file, "\t Burst_length\t\t: 0x%x\n", burst_length);
+ tegra_cbb_print_err(file, "\t Burst_type\t\t: 0x%x\n", burst_type);
+ tegra_cbb_print_err(file, "\t Beat_size\t\t: 0x%x\n", beat_size);
+ tegra_cbb_print_err(file, "\t VQC\t\t\t: 0x%x\n", vqc);
+ tegra_cbb_print_err(file, "\t GRPSEC\t\t: 0x%x\n", grpsec);
+ tegra_cbb_print_err(file, "\t FALCONSEC\t\t: 0x%x\n", falconsec);
+
+ if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID))
+ return;
+
+ if (!strcmp(errmon->noc_errors[errmon->err_type].errcode, "TIMEOUT_ERR")) {
+ tegra234_lookup_slave_timeout(file, errmon, slave_id, fab_id);
+ return;
+ }
+ tegra_cbb_print_err(file, "\t Slave\t\t\t: %s\n",
+ errmon->sn_addr_map[slave_id].slave_name);
+}
+
+static int print_errmonX_info(struct seq_file *file, struct tegra_cbb_errmon_record *errmon)
+{
+ unsigned int em_overflow_status = 0;
+ unsigned int em_err_status = 0;
+ unsigned int el_err_status = 0;
+ u64 addr = 0;
+
+ errmon->err_type = 0;
+
+ em_err_status = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_ERR_STATUS_0);
+ if (!em_err_status) {
+ pr_err("Error Notifier received a spurious notification\n");
+ BUG();
+ }
+
+ if (em_err_status == 0xFFFFFFFF) {
+ pr_err("CBB registers returning all 1's which is invalid\n");
+ return -EINVAL;
+ }
+
+ /*get overflow flag*/
+ em_overflow_status = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0);
+
+ print_errmon_err(file, errmon, em_err_status, em_overflow_status);
+
+ el_err_status = readl(errmon->addr_errmon + FABRIC_MN_MASTER_LOG_ERR_STATUS_0);
+ if (!el_err_status) {
+ pr_info("Error Monitor doesn't have Error Logger\n");
+ return -EINVAL;
+ }
+
+ while (el_err_status) {
+ if (el_err_status & BIT(0)) {
+ addr = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_LOG_ADDR_HIGH_0);
+ addr = (addr << 32) |
+ readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_LOG_ADDR_LOW_0);
+ errmon->addr_access = (void __iomem *)addr;
+
+ errmon->mn_attr0 = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0);
+
+ errmon->mn_attr1 = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0);
+
+ errmon->mn_attr2 = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0);
+
+ errmon->mn_user_bits = readl(errmon->addr_errmon +
+ FABRIC_MN_MASTER_LOG_USER_BITS0_0);
+
+ print_errlog_err(file, errmon);
+ }
+ errmon->err_type++;
+ el_err_status >>= 1;
+ }
+ return 0;
+}
+
+static int print_err_notifier(struct seq_file *file, struct tegra_cbb *cbb,
+ struct tegra_cbb_errmon_record *errmon, int err_notifier_sts)
+{
+ u64 em_addr_offset = 0;
+ u64 em_phys_addr = 0;
+ int errmon_no = 1;
+ int ret = 0;
+
+ pr_crit("**************************************\n");
+ pr_crit("CPU:%d, Error:%s, Errmon:%d\n", smp_processor_id(),
+ errmon->name, err_notifier_sts);
+
+ while (err_notifier_sts) {
+ if (err_notifier_sts & BIT(0)) {
+ writel(errmon_no, errmon->vaddr + errmon->err_notifier_base +
+ FABRIC_EN_CFG_ADDR_INDEX_0_0);
+
+ em_phys_addr = readl(errmon->vaddr + errmon->err_notifier_base +
+ FABRIC_EN_CFG_ADDR_HI_0);
+ em_phys_addr = (em_phys_addr << 32) |
+ readl(errmon->vaddr + errmon->err_notifier_base +
+ FABRIC_EN_CFG_ADDR_LOW_0);
+
+ em_addr_offset = em_phys_addr - errmon->start;
+ errmon->addr_errmon = (void __iomem *)(errmon->vaddr + em_addr_offset);
+
+ errmon->errmon_no = errmon_no;
+
+ ret = print_errmonX_info(file, errmon);
+ tegra234_cbb_errmon_errclr(cbb);
+ if (ret)
+ return ret;
+ }
+ err_notifier_sts >>= 1;
+ errmon_no <<= 1;
+ }
+
+ tegra_cbb_print_err(file, "\t**************************************\n");
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static DEFINE_MUTEX(cbb_err_mutex);
+
+static int tegra234_cbb_err_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ unsigned int errvld = 0;
+ int ret = 0;
+
+ mutex_lock(&cbb_err_mutex);
+
+ list_for_each_entry(errmon, &cbb_errmon_list, node) {
+ cbb = errmon->cbb;
+ errvld = tegra_cbb_errvld(cbb);
+ if (errvld) {
+ ret = print_err_notifier(file, cbb, errmon, errvld);
+ if (ret)
+ goto en_show_exit;
+ }
+ }
+
+en_show_exit:
+ mutex_unlock(&cbb_err_mutex);
+ return ret;
+}
+#endif
+
+/*
+ * Handler for CBB errors
+ */
+static irqreturn_t tegra234_cbb_err_isr(int irq, void *data)
+{
+ struct tegra_cbb_errmon_record *errmon;
+ struct tegra_cbb *cbb = data;
+ bool is_inband_err = 0;
+ unsigned long flags;
+ u32 errvld = 0;
+ u8 mstr_id = 0;
+ int ret = 0;
+
+ spin_lock_irqsave(&cbb_errmon_lock, flags);
+
+ list_for_each_entry(errmon, &cbb_errmon_list, node) {
+ errvld = tegra_cbb_errvld(cbb);
+
+ if (errvld && (irq == errmon->sec_irq)) {
+ tegra_cbb_print_err(NULL, "CPU:%d, Error:%s@0x%llx, irq=%d\n",
+ smp_processor_id(), errmon->name,
+ errmon->start, irq);
+
+ ret = print_err_notifier(NULL, cbb, errmon, errvld);
+ if (ret)
+ goto en_isr_exit;
+
+ mstr_id = FIELD_GET(USRBITS_MSTR_ID, errmon->mn_user_bits);
+
+ /* If illegal request is from CCPLEX(id:0x1)
+ * master then call BUG() to crash system.
+ */
+ if ((mstr_id == 0x1) && errmon->erd_mask_inband_err)
+ is_inband_err = 1;
+ }
+ }
+en_isr_exit:
+ spin_unlock_irqrestore(&cbb_errmon_lock, flags);
+
+ WARN_ON(is_inband_err);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Register handler for CBB_SECURE interrupt for reporting errors
+ */
+static int tegra234_cbb_intr_en(struct tegra_cbb *cbb)
+{
+ struct platform_device *pdev = cbb->pdev;
+ int sec_irq;
+ int err = 0;
+
+ sec_irq = ((struct tegra_cbb_errmon_record *)cbb->err_rec)->sec_irq;
+
+ if (sec_irq) {
+ err = devm_request_irq(&pdev->dev, sec_irq, tegra234_cbb_err_isr,
+ 0, dev_name(&pdev->dev), cbb);
+ if (err) {
+ dev_err(&pdev->dev, "%s: Unable to register (%d) interrupt\n",
+ __func__, sec_irq);
+ goto isr_err_free_sec_irq;
+ }
+ }
+ return 0;
+
+isr_err_free_sec_irq:
+ free_irq(sec_irq, pdev);
+
+ return err;
+}
+
+static void tegra234_cbb_err_en(struct tegra_cbb *cbb)
+{
+ tegra_cbb_faulten(cbb);
+}
+
+static struct tegra_cbb_err_ops tegra234_cbb_errmon_ops = {
+ .errvld = tegra234_cbb_errmon_errvld,
+ .errclr = tegra234_cbb_errmon_errclr,
+ .faulten = tegra234_cbb_errmon_faulten,
+ .cbb_err_enable = tegra234_cbb_err_en,
+ .cbb_intr_enable = tegra234_cbb_intr_en,
+#ifdef CONFIG_DEBUG_FS
+ .cbb_err_debugfs_show = tegra234_cbb_err_show
+#endif
+};
+
+static struct tegra_cbb_fabric_data tegra234_aon_fab_data = {
+ .name = "aon-fabric",
+ .tegra_cbb_master_id = t234_master_id,
+ .sn_addr_map = t234_aon_sn_lookup,
+ .noc_errors = t234_errmon_errors,
+ .err_notifier_base = 0x17000
+};
+
+static struct tegra_cbb_fabric_data tegra234_bpmp_fab_data = {
+ .name = "bpmp-fabric",
+ .tegra_cbb_master_id = t234_master_id,
+ .sn_addr_map = t234_bpmp_sn_lookup,
+ .noc_errors = t234_errmon_errors,
+ .err_notifier_base = 0x19000
+};
+
+static struct tegra_cbb_fabric_data tegra234_cbb_fab_data = {
+ .name = "cbb-fabric",
+ .tegra_cbb_master_id = t234_master_id,
+ .sn_addr_map = t234_cbb_sn_lookup,
+ .noc_errors = t234_errmon_errors,
+ .err_notifier_base = 0x60000,
+ .off_mask_erd = 0x3a004
+};
+
+static struct tegra_cbb_fabric_data tegra234_dce_fab_data = {
+ .name = "dce-fabric",
+ .tegra_cbb_master_id = t234_master_id,
+ .sn_addr_map = t234_dce_sn_lookup,
+ .noc_errors = t234_errmon_errors,
+ .err_notifier_base = 0x19000
+};
+
+static struct tegra_cbb_fabric_data tegra234_rce_fab_data = {
+ .name = "rce-fabric",
+ .tegra_cbb_master_id = t234_master_id,
+ .sn_addr_map = t234_rce_sn_lookup,
+ .noc_errors = t234_errmon_errors,
+ .err_notifier_base = 0x19000
+};
+
+static struct tegra_cbb_fabric_data tegra234_sce_fab_data = {
+ .name = "sce-fabric",
+ .tegra_cbb_master_id = t234_master_id,
+ .sn_addr_map = t234_sce_sn_lookup,
+ .noc_errors = t234_errmon_errors,
+ .err_notifier_base = 0x19000
+};
+
+static const struct of_device_id tegra234_cbb_dt_ids[] = {
+ {.compatible = "nvidia,tegra234-cbb-fabric",
+ .data = &tegra234_cbb_fab_data},
+ {.compatible = "nvidia,tegra234-aon-fabric",
+ .data = &tegra234_aon_fab_data},
+ {.compatible = "nvidia,tegra234-bpmp-fabric",
+ .data = &tegra234_bpmp_fab_data},
+ {.compatible = "nvidia,tegra234-dce-fabric",
+ .data = &tegra234_dce_fab_data},
+ {.compatible = "nvidia,tegra234-rce-fabric",
+ .data = &tegra234_rce_fab_data},
+ {.compatible = "nvidia,tegra234-sce-fabric",
+ .data = &tegra234_sce_fab_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);
+
+static int
+tegra234_cbb_errmon_init(const struct tegra_cbb_fabric_data *pdata,
+ struct tegra_cbb *cbb, struct resource *res_base)
+{
+ struct platform_device *pdev = cbb->pdev;
+ struct tegra_cbb_errmon_record *errmon;
+ unsigned long flags = 0;
+ int err = 0;
+
+ errmon = (struct tegra_cbb_errmon_record *)cbb->err_rec;
+ errmon->vaddr = devm_ioremap_resource(&pdev->dev, res_base);
+ if (IS_ERR(errmon->vaddr))
+ return -EINVAL;
+
+ errmon->name = pdata->name;
+ errmon->start = res_base->start;
+ errmon->tegra_cbb_master_id = pdata->tegra_cbb_master_id;
+ errmon->err_notifier_base = pdata->err_notifier_base;
+ errmon->off_mask_erd = pdata->off_mask_erd;
+ errmon->sn_addr_map = pdata->sn_addr_map;
+ errmon->noc_errors = pdata->noc_errors;
+ errmon->cbb = cbb;
+
+ if (errmon->off_mask_erd)
+ errmon->erd_mask_inband_err = 1;
+
+ err = tegra_cbb_err_getirq(pdev, NULL, &errmon->sec_irq);
+ if (err)
+ return err;
+
+ cbb->ops = &tegra234_cbb_errmon_ops;
+
+ spin_lock_irqsave(&cbb_errmon_lock, flags);
+ list_add(&errmon->node, &cbb_errmon_list);
+ spin_unlock_irqrestore(&cbb_errmon_lock, flags);
+
+ return 0;
+};
+
+static int tegra234_cbb_probe(struct platform_device *pdev)
+{
+ struct tegra_cbb_errmon_record *errmon = NULL;
+ const struct tegra_cbb_fabric_data *pdata = NULL;
+ struct resource *res_base = NULL;
+ struct tegra_cbb *cbb;
+ int err = 0;
+
+ pdata = of_device_get_match_data(&pdev->dev);
+ if (!pdata) {
+ dev_err(&pdev->dev, "No device match found\n");
+ return -EINVAL;
+ }
+
+ res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res_base) {
+ dev_err(&pdev->dev, "Could not find base address");
+ return -ENOENT;
+ }
+
+ cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
+ if (!cbb)
+ return -ENOMEM;
+
+ errmon = devm_kzalloc(&pdev->dev, sizeof(*errmon), GFP_KERNEL);
+ if (!errmon)
+ return -ENOMEM;
+
+ cbb->err_rec = errmon;
+ cbb->pdev = pdev;
+ err = tegra234_cbb_errmon_init(pdata, cbb, res_base);
+ if (err) {
+ dev_err(&pdev->dev, "cbberr init for soc failing\n");
+ return err;
+ }
+
+ /* set ERD bit to mask SError and generate interrupt to report error */
+ if (errmon->erd_mask_inband_err)
+ tegra234_cbb_mn_mask_serror(cbb);
+
+ return tegra_cbb_register_isr_enaberr(cbb);
+}
+
+static int tegra234_cbb_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra234_cbb_resume_noirq(struct device *dev)
+{
+ struct tegra_cbb *cbb = dev_get_drvdata(dev);
+ struct tegra_cbb_errmon_record *errmon;
+
+ errmon = (struct tegra_cbb_errmon_record *)cbb->err_rec;
+
+ if (!errmon)
+ return -EINVAL;
+
+ tegra234_cbb_err_en(cbb);
+
+ dev_info(dev, "%s resumed\n", errmon->name);
+ return 0;
+}
+
+static const struct dev_pm_ops tegra234_cbb_pm = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra234_cbb_resume_noirq)
+};
+#endif
+
+static struct platform_driver tegra234_cbb_driver = {
+ .probe = tegra234_cbb_probe,
+ .remove = tegra234_cbb_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tegra234-cbb",
+ .of_match_table = of_match_ptr(tegra234_cbb_dt_ids),
+#ifdef CONFIG_PM_SLEEP
+ .pm = &tegra234_cbb_pm,
+#endif
+ },
+};
+
+static int __init tegra234_cbb_init(void)
+{
+ return platform_driver_register(&tegra234_cbb_driver);
+}
+
+static void __exit tegra234_cbb_exit(void)
+{
+ platform_driver_unregister(&tegra234_cbb_driver);
+}
+
+pure_initcall(tegra234_cbb_init);
+module_exit(tegra234_cbb_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Control Backbone 2.0 error handling driver for Tegra234");
diff --git a/include/soc/tegra/tegra234-cbb.h b/include/soc/tegra/tegra234-cbb.h
new file mode 100644
index 000000000000..8c3ff758c845
--- /dev/null
+++ b/include/soc/tegra/tegra234-cbb.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ */
+
+#define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
+#define FABRIC_EN_CFG_STATUS_0_0 0x40
+#define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
+#define FABRIC_EN_CFG_ADDR_LOW_0 0x80
+#define FABRIC_EN_CFG_ADDR_HI_0 0x84
+
+#define FABRIC_MN_MASTER_ERR_EN_0 0x200
+#define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
+#define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
+#define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
+
+#define FABRIC_MN_MASTER_LOG_ERR_STATUS_0 0x300
+#define FABRIC_MN_MASTER_LOG_ADDR_LOW_0 0x304
+#define FABRIC_MN_MASTER_LOG_ADDR_HIGH_0 0x308
+#define FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0 0x30c
+#define FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0 0x310
+#define FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0 0x314
+#define FABRIC_MN_MASTER_LOG_USER_BITS0_0 0x318
+
+#define AXI_SLV_TIMEOUT_STATUS_0_0 0x8
+#define APB_BLOCK_TMO_STATUS_0 0xC00
+#define APB_BLOCK_NUM_TMO_OFFSET 0x20
+
+#define FAB_EM_EL_MSTRID GENMASK(29, 24)
+#define FAB_EM_EL_VQC GENMASK(17, 16)
+#define FAB_EM_EL_GRPSEC GENMASK(14, 8)
+#define FAB_EM_EL_FALCONSEC GENMASK(1, 0)
+
+#define FAB_EM_EL_FABID GENMASK(20, 16)
+#define FAB_EM_EL_SLAVEID GENMASK(7, 0)
+
+#define FAB_EM_EL_ACCESSID GENMASK(7, 0)
+
+#define FAB_EM_EL_AXCACHE GENMASK(27, 24)
+#define FAB_EM_EL_AXPROT GENMASK(22, 20)
+#define FAB_EM_EL_BURSTLENGTH GENMASK(19, 12)
+#define FAB_EM_EL_BURSTTYPE GENMASK(9, 8)
+#define FAB_EM_EL_BEATSIZE GENMASK(6, 4)
+#define FAB_EM_EL_ACCESSTYPE GENMASK(0, 0)
+
+#define USRBITS_MSTR_ID GENMASK(29, 24)
+
+enum tegra_cbb_fabric_ids {
+ CBB_FAB_ID,
+ SCE_FAB_ID,
+ RCE_FAB_ID,
+ DCE_FAB_ID,
+ AON_FAB_ID,
+ PSC_FAB_ID,
+ BPMP_FAB_ID,
+ FSI_FAB_ID,
+ MAX_FAB_ID,
+};
+
+struct tegra_sn_addr_map {
+ char *slave_name;
+ u32 off_slave;
+};
+
+struct tegra_cbb_fabric_data {
+ char *name;
+ phys_addr_t off_mask_erd;
+ bool erd_mask_inband_err;
+ char **tegra_cbb_master_id;
+ phys_addr_t err_notifier_base;
+ struct tegra_noc_errors *noc_errors;
+ struct tegra_sn_addr_map *sn_addr_map;
+};
+
+struct tegra_cbb_errmon_record {
+ struct list_head node;
+ char *name;
+ int errmon_no;
+ int err_type;
+ phys_addr_t start;
+ phys_addr_t err_notifier_base;
+ int num_intr;
+ int sec_irq;
+ void __iomem *vaddr;
+ void __iomem *addr_errmon;
+ void __iomem *addr_access;
+ u32 mn_attr0;
+ u32 mn_attr1;
+ u32 mn_attr2;
+ u32 mn_user_bits;
+ phys_addr_t off_mask_erd;
+ bool erd_mask_inband_err;
+ struct tegra_cbb *cbb;
+ char **tegra_cbb_master_id;
+ struct tegra_noc_errors *noc_errors;
+ struct tegra_sn_addr_map *sn_addr_map;
+};
+
+u32 tegra234_cbb_readl(unsigned long offset);
+void tegra234_cbb_writel(unsigned long offset, u32 val);
+
+static char *t234_master_id[] = {
+ "TZ", /* 0x0 */
+ "CCPLEX", /* 0x1 */
+ "CCPMU", /* 0x2 */
+ "BPMP_FW", /* 0x3 */
+ "AON", /* 0x4 */
+ "SCE", /* 0x5 */
+ "GPCDMA_P", /* 0x6 */
+ "TSECA_NONSECURE", /* 0x7 */
+ "TSECA_LIGHTSECURE", /* 0x8 */
+ "TSECA_HEAVYSECURE", /* 0x9 */
+ "CORESIGHT", /* 0xA */
+ "APE", /* 0xB */
+ "PEATRANS", /* 0xC */
+ "JTAGM_DFT", /* 0xD */
+ "RCE", /* 0xE */
+ "DCE", /* 0xF */
+ "PSC_FW_USER", /* 0x10 */
+ "PSC_FW_SUPERVISOR", /* 0x11 */
+ "PSC_FW_MACHINE", /* 0x12 */
+ "PSC_BOOT", /* 0x13 */
+ "BPMP_BOOT", /* 0x14 */
+ "NVDEC_NONSECURE", /* 0x15 */
+ "NVDEC_LIGHTSECURE", /* 0x16 */
+ "NVDEC_HEAVYSECURE", /* 0x17 */
+ "CBB_INTERNAL", /* 0x18 */
+ "RSVD" /* 0x3F */
+};
+
+static struct tegra_noc_errors t234_errmon_errors[] = {
+ {.errcode = "SLAVE_ERR",
+ .type = "Slave being accessed responded with an error"
+ },
+ {.errcode = "DECODE_ERR",
+ .type = "Attempt to access an address hole"
+ },
+ {.errcode = "FIREWALL_ERR",
+ .type = "Attempt to access a region which is firewall protected"
+ },
+ {.errcode = "TIMEOUT_ERR",
+ .type = "No response returned by slave"
+ },
+ {.errcode = "PWRDOWN_ERR",
+ .type = "Attempt to access a portion of fabric that is powered down"
+ },
+ {.errcode = "UNSUPPORTED_ERR",
+ .type = "Attempt to access a slave through an unsupported access"
+ }
+};
+
+#define AON_SN_AXI2APB_1 0x00000
+#define AON_SN_AST1_T 0x14000
+#define AON_SN_CBB_T 0x15000
+#define AON_SN_CPU_T 0x16000
+
+#define BPMP_SN_AXI2APB_1 0x00000
+#define BPMP_SN_AST0_T 0x15000
+#define BPMP_SN_AST1_T 0x16000
+#define BPMP_SN_CBB_T 0x17000
+#define BPMP_SN_CPU_T 0x18000
+
+#define DCE_SN_AXI2APB_1 0x00000
+#define DCE_SN_AST0_T 0x15000
+#define DCE_SN_AST1_T 0x16000
+#define DCE_SN_CPU_T 0x18000
+
+#define RCE_SN_AXI2APB_1 0x00000
+#define RCE_SN_AST0_T 0x15000
+#define RCE_SN_AST1_T 0x16000
+#define RCE_SN_CPU_T 0x18000
+
+#define SCE_SN_AXI2APB_1 0x00000
+#define SCE_SN_AST0_T 0x15000
+#define SCE_SN_AST1_T 0x16000
+#define SCE_SN_CBB_T 0x17000
+#define SCE_SN_CPU_T 0x18000
+
+#define CBB_SN_AON_SLAVE 0x40000
+#define CBB_SN_BPMP_SLAVE 0x41000
+#define CBB_SN_CBB_CENTRAL 0x42000
+#define CBB_SN_HOST1X 0x43000
+#define CBB_SN_STM 0x44000
+#define CBB_SN_FSI_SLAVE 0x45000
+#define CBB_SN_PSC_SLAVE 0x46000
+#define CBB_SN_PCIE_C1 0x47000
+#define CBB_SN_PCIE_C2 0x48000
+#define CBB_SN_PCIE_C3 0x49000
+#define CBB_SN_PCIE_C0 0x4A000
+#define CBB_SN_PCIE_C4 0x4B000
+#define CBB_SN_GPU 0x4C000
+#define CBB_SN_SMMU0 0x4D000
+#define CBB_SN_SMMU1 0x4E000
+#define CBB_SN_SMMU2 0x4F000
+#define CBB_SN_SMMU3 0x50000
+#define CBB_SN_SMMU4 0x51000
+#define CBB_SN_PCIE_C10 0x52000
+#define CBB_SN_PCIE_C7 0x53000
+#define CBB_SN_PCIE_C8 0x54000
+#define CBB_SN_PCIE_C9 0x55000
+#define CBB_SN_PCIE_C5 0x56000
+#define CBB_SN_PCIE_C6 0x57000
+#define CBB_SN_DCE_SLAVE 0x58000
+#define CBB_SN_RCE_SLAVE 0x59000
+#define CBB_SN_SCE_SLAVE 0x5A000
+#define CBB_SN_AXI2APB_1 0x70000
+#define CBB_SN_AXI2APB_10 0x71000
+#define CBB_SN_AXI2APB_11 0x72000
+#define CBB_SN_AXI2APB_12 0x73000
+#define CBB_SN_AXI2APB_13 0x74000
+#define CBB_SN_AXI2APB_14 0x75000
+#define CBB_SN_AXI2APB_15 0x76000
+#define CBB_SN_AXI2APB_16 0x77000
+#define CBB_SN_AXI2APB_17 0x78000
+#define CBB_SN_AXI2APB_18 0x79000
+#define CBB_SN_AXI2APB_19 0x7A000
+#define CBB_SN_AXI2APB_2 0x7B000
+#define CBB_SN_AXI2APB_20 0x7C000
+#define CBB_SN_AXI2APB_21 0x7D000
+#define CBB_SN_AXI2APB_22 0x7E000
+#define CBB_SN_AXI2APB_23 0x7F000
+#define CBB_SN_AXI2APB_25 0x80000
+#define CBB_SN_AXI2APB_26 0x81000
+#define CBB_SN_AXI2APB_27 0x82000
+#define CBB_SN_AXI2APB_28 0x83000
+#define CBB_SN_AXI2APB_29 0x84000
+#define CBB_SN_AXI2APB_30 0x85000
+#define CBB_SN_AXI2APB_31 0x86000
+#define CBB_SN_AXI2APB_32 0x87000
+#define CBB_SN_AXI2APB_33 0x88000
+#define CBB_SN_AXI2APB_34 0x89000
+#define CBB_SN_AXI2APB_35 0x92000
+#define CBB_SN_AXI2APB_4 0x8B000
+#define CBB_SN_AXI2APB_5 0x8C000
+#define CBB_SN_AXI2APB_6 0x8D000
+#define CBB_SN_AXI2APB_7 0x8E000
+#define CBB_SN_AXI2APB_8 0x8F000
+#define CBB_SN_AXI2APB_9 0x90000
+#define CBB_SN_AXI2APB_3 0x91000
+
+#define SLAVE_LOOKUP(sn) #sn, sn
+
+static struct tegra_sn_addr_map t234_aon_sn_lookup[] = {
+ { SLAVE_LOOKUP(AON_SN_AXI2APB_1) },
+ { SLAVE_LOOKUP(AON_SN_AST1_T) },
+ { SLAVE_LOOKUP(AON_SN_CBB_T) },
+ { SLAVE_LOOKUP(AON_SN_CPU_T) }
+};
+
+static struct tegra_sn_addr_map t234_bpmp_sn_lookup[] = {
+ { SLAVE_LOOKUP(BPMP_SN_AXI2APB_1) },
+ { SLAVE_LOOKUP(BPMP_SN_AST0_T) },
+ { SLAVE_LOOKUP(BPMP_SN_AST1_T) },
+ { SLAVE_LOOKUP(BPMP_SN_CBB_T) },
+ { SLAVE_LOOKUP(BPMP_SN_CPU_T) },
+};
+
+static struct tegra_sn_addr_map t234_sce_sn_lookup[] = {
+ { SLAVE_LOOKUP(SCE_SN_AXI2APB_1) },
+ { SLAVE_LOOKUP(SCE_SN_AST0_T) },
+ { SLAVE_LOOKUP(SCE_SN_AST1_T) },
+ { SLAVE_LOOKUP(SCE_SN_CBB_T) },
+ { SLAVE_LOOKUP(SCE_SN_CPU_T) }
+};
+
+static struct tegra_sn_addr_map t234_dce_sn_lookup[] = {
+ { SLAVE_LOOKUP(DCE_SN_AXI2APB_1) },
+ { SLAVE_LOOKUP(DCE_SN_AST0_T) },
+ { SLAVE_LOOKUP(DCE_SN_AST1_T) },
+ { SLAVE_LOOKUP(DCE_SN_CPU_T) }
+};
+
+static struct tegra_sn_addr_map t234_rce_sn_lookup[] = {
+ { SLAVE_LOOKUP(RCE_SN_AXI2APB_1) },
+ { SLAVE_LOOKUP(RCE_SN_AST0_T) },
+ { SLAVE_LOOKUP(RCE_SN_AST1_T) },
+ { SLAVE_LOOKUP(RCE_SN_CPU_T) }
+};
+
+static struct tegra_sn_addr_map t234_cbb_sn_lookup[] = {
+ { SLAVE_LOOKUP(CBB_SN_AON_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_BPMP_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_CBB_CENTRAL) },
+ { SLAVE_LOOKUP(CBB_SN_HOST1X) },
+ { SLAVE_LOOKUP(CBB_SN_STM) },
+ { SLAVE_LOOKUP(CBB_SN_FSI_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_PSC_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C1) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C2) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C3) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C0) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C4) },
+ { SLAVE_LOOKUP(CBB_SN_GPU) },
+ { SLAVE_LOOKUP(CBB_SN_SMMU0) },
+ { SLAVE_LOOKUP(CBB_SN_SMMU1) },
+ { SLAVE_LOOKUP(CBB_SN_SMMU2) },
+ { SLAVE_LOOKUP(CBB_SN_SMMU3) },
+ { SLAVE_LOOKUP(CBB_SN_SMMU4) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C10) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C7) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C8) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C9) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C5) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C6) },
+ { SLAVE_LOOKUP(CBB_SN_DCE_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_RCE_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_SCE_SLAVE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_1) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_10) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_11) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_12) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_13) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_14) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_15) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_16) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_17) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_18) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_19) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_2) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_20) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_21) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_22) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_23) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_25) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_26) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_27) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_28) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_29) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_30) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_31) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_32) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_33) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_34) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_35) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_4) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_5) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_6) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_7) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_8) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_9) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_3) }
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch v3 9/9] soc: tegra: cbb: Add support for tegra-grace SOC
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
` (7 preceding siblings ...)
2021-12-21 12:51 ` [Patch v3 8/9] soc: tegra: cbb: Add driver for Tegra234 CBB2.0 Sumit Gupta
@ 2021-12-21 12:51 ` Sumit Gupta
8 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2021-12-21 12:51 UTC (permalink / raw)
To: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
robh+dt
Cc: kbuild-all, sumitg, bbasu, vsethi, jsequeira
Adding support for Tegra Grace SOC which uses CBB2.0 architecture
based fabrics. Also, adding ACPI support required for Grace.
Fabrics reporting errors in Grace are "CBB Fabric" and "BPMP Fabric".
"CBB Fabric" connects various other CBB2.0 based fabrics and also
services the Initiators and Targets which are connected to itself.
"BPMP Fabric" is present in BPMP cluster.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/soc/tegra/cbb/tegra234-cbb.c | 90 ++++++++++-
include/soc/tegra/tegra-grace-cbb.h | 219 +++++++++++++++++++++++++++
2 files changed, 308 insertions(+), 1 deletion(-)
create mode 100644 include/soc/tegra/tegra-grace-cbb.h
diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c
index 56069eb8dc2b..07c8fff830f9 100644
--- a/drivers/soc/tegra/cbb/tegra234-cbb.c
+++ b/drivers/soc/tegra/cbb/tegra234-cbb.c
@@ -11,6 +11,7 @@
*/
#include <asm/cpufeature.h>
+#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/module.h>
@@ -27,6 +28,7 @@
#include <soc/tegra/fuse.h>
#include <soc/tegra/tegra-cbb.h>
#include <soc/tegra/tegra234-cbb.h>
+#include <soc/tegra/tegra-grace-cbb.h>
static LIST_HEAD(cbb_errmon_list);
static DEFINE_SPINLOCK(cbb_errmon_lock);
@@ -258,14 +260,33 @@ static void print_errlog_err(struct seq_file *file, struct tegra_cbb_errmon_reco
u8 cache_type = 0, prot_type = 0, burst_length = 0;
u8 mstr_id = 0, grpsec = 0, vqc = 0, falconsec = 0;
u8 beat_size = 0, access_type = 0, access_id = 0;
+ u8 requester_socket_id = 0, local_socket_id = 0;
u8 slave_id = 0, fab_id = 0, burst_type = 0;
char fabric_name[20];
+ bool is_numa = 0;
+
+ if (num_possible_nodes() > 1)
+ is_numa = true;
mstr_id = FIELD_GET(FAB_EM_EL_MSTRID, errmon->mn_user_bits);
vqc = FIELD_GET(FAB_EM_EL_VQC, errmon->mn_user_bits);
grpsec = FIELD_GET(FAB_EM_EL_GRPSEC, errmon->mn_user_bits);
falconsec = FIELD_GET(FAB_EM_EL_FALCONSEC, errmon->mn_user_bits);
+ /*
+ * For SOC with multiple NUMA nodes, print cross socket access
+ * errors only if initiator/master_id is CCPLEX, CPMU or GPU.
+ */
+ if (is_numa) {
+ local_socket_id = numa_node_id();
+ requester_socket_id = FIELD_GET(REQ_SOCKET_ID, errmon->mn_attr2);
+
+ if (requester_socket_id != local_socket_id) {
+ if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))
+ return;
+ }
+ }
+
fab_id = FIELD_GET(FAB_EM_EL_FABID, errmon->mn_attr2);
slave_id = FIELD_GET(FAB_EM_EL_SLAVEID, errmon->mn_attr2);
@@ -298,6 +319,15 @@ static void print_errlog_err(struct seq_file *file, struct tegra_cbb_errmon_reco
else
strcpy(fabric_name, errmon->name);
+ if (is_numa) {
+ tegra_cbb_print_err(file, "\t Requester_Socket_Id\t: 0x%x\n",
+ requester_socket_id);
+ tegra_cbb_print_err(file, "\t Local_Socket_Id\t: 0x%x\n",
+ local_socket_id);
+ tegra_cbb_print_err(file, "\t No. of NUMA_NODES\t: 0x%x\n",
+ num_possible_nodes());
+ }
+
tegra_cbb_print_err(file, "\t Fabric\t\t: %s\n", fabric_name);
tegra_cbb_print_err(file, "\t Slave_Id\t\t: 0x%x\n", slave_id);
tegra_cbb_print_err(file, "\t Burst_length\t\t: 0x%x\n", burst_length);
@@ -585,6 +615,23 @@ static struct tegra_cbb_fabric_data tegra234_sce_fab_data = {
.err_notifier_base = 0x19000
};
+static struct tegra_cbb_fabric_data tegra_grace_cbb_fab_data = {
+ .name = "cbb-fabric",
+ .tegra_cbb_master_id = tegra_grace_master_id,
+ .sn_addr_map = tegra_grace_cbb_sn_lookup,
+ .noc_errors = tegra_grace_errmon_errors,
+ .err_notifier_base = 0x60000,
+ .off_mask_erd = 0x40004
+};
+
+static struct tegra_cbb_fabric_data tegra_grace_bpmp_fab_data = {
+ .name = "bpmp-fabric",
+ .tegra_cbb_master_id = tegra_grace_master_id,
+ .sn_addr_map = tegra_grace_bpmp_sn_lookup,
+ .noc_errors = tegra_grace_errmon_errors,
+ .err_notifier_base = 0x19000
+};
+
static const struct of_device_id tegra234_cbb_dt_ids[] = {
{.compatible = "nvidia,tegra234-cbb-fabric",
.data = &tegra234_cbb_fab_data},
@@ -602,6 +649,36 @@ static const struct of_device_id tegra234_cbb_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);
+struct cbb_acpi_uid_noc {
+ const char *hid;
+ const char *uid;
+ const struct tegra_cbb_fabric_data *fab;
+};
+
+static const struct cbb_acpi_uid_noc cbb_acpi_uids[] = {
+ { "NVDA1070", "1", &tegra_grace_cbb_fab_data },
+ { "NVDA1070", "2", &tegra_grace_bpmp_fab_data },
+ { },
+};
+
+static const struct acpi_device_id tegra_grace_cbb_acpi_ids[] = {
+ { "NVDA1070" },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, tegra_grace_cbb_acpi_ids);
+
+static const struct
+tegra_cbb_fabric_data *cbb_acpi_get_fab_data(struct acpi_device *adev)
+{
+ const struct cbb_acpi_uid_noc *u;
+
+ for (u = cbb_acpi_uids; u->hid; u++) {
+ if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
+ return u->fab;
+ }
+ return NULL;
+}
+
static int
tegra234_cbb_errmon_init(const struct tegra_cbb_fabric_data *pdata,
struct tegra_cbb *cbb, struct resource *res_base)
@@ -646,10 +723,20 @@ static int tegra234_cbb_probe(struct platform_device *pdev)
struct tegra_cbb_errmon_record *errmon = NULL;
const struct tegra_cbb_fabric_data *pdata = NULL;
struct resource *res_base = NULL;
+ struct device *dev = &pdev->dev;
+ struct acpi_device *device;
struct tegra_cbb *cbb;
int err = 0;
- pdata = of_device_get_match_data(&pdev->dev);
+ if (of_machine_is_compatible("nvidia,tegra23x") ||
+ of_machine_is_compatible("nvidia,tegra234")) {
+ pdata = of_device_get_match_data(&pdev->dev);
+ } else {
+ device = ACPI_COMPANION(dev);
+ if (!device)
+ return -ENODEV;
+ pdata = cbb_acpi_get_fab_data(device);
+ }
if (!pdata) {
dev_err(&pdev->dev, "No device match found\n");
return -EINVAL;
@@ -718,6 +805,7 @@ static struct platform_driver tegra234_cbb_driver = {
.owner = THIS_MODULE,
.name = "tegra234-cbb",
.of_match_table = of_match_ptr(tegra234_cbb_dt_ids),
+ .acpi_match_table = ACPI_PTR(tegra_grace_cbb_acpi_ids),
#ifdef CONFIG_PM_SLEEP
.pm = &tegra234_cbb_pm,
#endif
diff --git a/include/soc/tegra/tegra-grace-cbb.h b/include/soc/tegra/tegra-grace-cbb.h
new file mode 100644
index 000000000000..91cde80e773a
--- /dev/null
+++ b/include/soc/tegra/tegra-grace-cbb.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved
+ */
+
+static char *tegra_grace_master_id[] = {
+ "TZ", /* 0x0 */
+ "CCPLEX", /* 0x1 */
+ "CCPMU", /* 0x2 */
+ "BPMP_FW", /* 0x3 */
+ "PSC_FW_USER", /* 0x4 */
+ "PSC_FW_SUPERVISOR", /* 0x5 */
+ "PSC_FW_MACHINE", /* 0x6 */
+ "PSC_BOOT", /* 0x7 */
+ "BPMP_BOOT", /* 0x8 */
+ "JTAGM_DFT", /* 0x9 */
+ "CORESIGHT", /* 0xA */
+ "GPU", /* 0xB */
+ "PEATRANS", /* 0xC */
+ "RSVD" /* 0x3F */
+};
+
+/*
+ * Possible causes for Slave and Timeout errors.
+ * SLAVE_ERR:
+ * Slave being accessed responded with an error. Slave could return
+ * an error for various cases :
+ * Unsupported access, clamp setting when power gated, register
+ * level firewall(SCR), address hole within the slave, etc
+ *
+ * TIMEOUT_ERR:
+ * No response returned by slave. Can be due to slave being clock
+ * gated, under reset, powered down or slave inability to respond
+ * for an internal slave issue
+ */
+
+static struct tegra_noc_errors tegra_grace_errmon_errors[] = {
+ {.errcode = "SLAVE_ERR",
+ .type = "Slave being accessed responded with an error."
+ },
+ {.errcode = "DECODE_ERR",
+ .type = "Attempt to access an address hole or Reserved region of memory."
+ },
+ {.errcode = "FIREWALL_ERR",
+ .type = "Attempt to access a region which is firewalled."
+ },
+ {.errcode = "TIMEOUT_ERR",
+ .type = "No response returned by slave."
+ },
+ {.errcode = "PWRDOWN_ERR",
+ .type = "Attempt to access a portion of the fabric that is powered down."
+ },
+ {.errcode = "UNSUPPORTED_ERR",
+ .type = "Attempt to access a slave through an unsupported access."
+ },
+ {.errcode = "POISON_ERR",
+ .type = "Slave responds with poison error to indicate error in data."
+ },
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "RSVD"},
+ {.errcode = "NO_SUCH_ADDRESS_ERR",
+ .type = "The address belongs to the pri_target range but there is no register implemented at the address."
+ },
+ {.errcode = "TASK_ERR",
+ .type = "Attempt to update a PRI task when the current task has still not completed."
+ },
+ {.errcode = "EXTERNAL_ERR",
+ .type = "Indicates that an external PRI register access met with an error due to any issue in the unit."
+ },
+ {.errcode = "INDEX_ERR",
+ .type = "Applicable to PRI index aperture pair, when the programmed index is outside the range defined in the manual."
+ },
+ {.errcode = "RESET_ERR",
+ .type = "Target in Reset Error: Attempt to access a SubPri or external PRI register but they are in reset."
+ },
+ {.errcode = "REGISTER_RST_ERR",
+ .type = "Attempt to access a PRI register but the register is partial or completely in reset."
+ },
+ {.errcode = "POWER_GATED_ERR",
+ .type = "Returned by external PRI client when the external access goes to a power gated domain."
+ },
+ {.errcode = "SUBPRI_FS_ERR",
+ .type = "Subpri is floorswept: Attempt to access a subpri through the main pri target but subPri logic is floorswept."
+ },
+ {.errcode = "SUBPRI_CLK_OFF_ERR",
+ .type = "Subpri clock is off: Attempt to access a subpri through the main pri target but subPris clock is gated/off."
+ }
+};
+
+#define REQ_SOCKET_ID GENMASK(27, 24)
+
+#define BPMP_SN_AXI2APB_1_BASE 0x00000
+#define BPMP_SN_CBB_T_BASE 0x15000
+#define BPMP_SN_CPU_T_BASE 0x16000
+#define BPMP_SN_DBB0_T_BASE 0x17000
+#define BPMP_SN_DBB1_T_BASE 0x18000
+
+#define CBB_SN_CCPLEX_SLAVE_BASE 0x50000
+#define CBB_SN_PCIE_C8_BASE 0x51000
+#define CBB_SN_PCIE_C9_BASE 0x52000
+#define CBB_SN_PCIE_C4_BASE 0x53000
+#define CBB_SN_PCIE_C5_BASE 0x54000
+#define CBB_SN_PCIE_C6_BASE 0x55000
+#define CBB_SN_PCIE_C7_BASE 0x56000
+#define CBB_SN_PCIE_C2_BASE 0x57000
+#define CBB_SN_PCIE_C3_BASE 0x58000
+#define CBB_SN_PCIE_C0_BASE 0x59000
+#define CBB_SN_PCIE_C1_BASE 0x5A000
+#define CBB_SN_AON_SLAVE_BASE 0x5B000
+#define CBB_SN_BPMP_SLAVE_BASE 0x5C000
+#define CBB_SN_PSC_SLAVE_BASE 0x5D000
+#define CBB_SN_STM_BASE 0x5E000
+#define CBB_SN_AXI2APB_1_BASE 0x70000
+#define CBB_SN_AXI2APB_10_BASE 0x71000
+#define CBB_SN_AXI2APB_11_BASE 0x72000
+#define CBB_SN_AXI2APB_12_BASE 0x73000
+#define CBB_SN_AXI2APB_13_BASE 0x74000
+#define CBB_SN_AXI2APB_14_BASE 0x75000
+#define CBB_SN_AXI2APB_15_BASE 0x76000
+#define CBB_SN_AXI2APB_16_BASE 0x77000
+#define CBB_SN_AXI2APB_17_BASE 0x78000
+#define CBB_SN_AXI2APB_18_BASE 0x79000
+#define CBB_SN_AXI2APB_19_BASE 0x7A000
+#define CBB_SN_AXI2APB_2_BASE 0x7B000
+#define CBB_SN_AXI2APB_20_BASE 0x7C000
+#define CBB_SN_AXI2APB_21_BASE 0x7D000
+#define CBB_SN_AXI2APB_22_BASE 0x7E000
+#define CBB_SN_AXI2APB_23_BASE 0x7F000
+#define CBB_SN_AXI2APB_24_BASE 0x80000
+#define CBB_SN_AXI2APB_25_BASE 0x81000
+#define CBB_SN_AXI2APB_26_BASE 0x82000
+#define CBB_SN_AXI2APB_27_BASE 0x83000
+#define CBB_SN_AXI2APB_28_BASE 0x84000
+#define CBB_SN_AXI2APB_29_BASE 0x85000
+#define CBB_SN_AXI2APB_30_BASE 0x86000
+#define CBB_SN_AXI2APB_4_BASE 0x87000
+#define CBB_SN_AXI2APB_5_BASE 0x88000
+#define CBB_SN_AXI2APB_6_BASE 0x89000
+#define CBB_SN_AXI2APB_7_BASE 0x8A000
+#define CBB_SN_AXI2APB_8_BASE 0x8B000
+#define CBB_SN_AXI2APB_9_BASE 0x8C000
+#define CBB_SN_AXI2APB_3_BASE 0x8D000
+
+#define SLAVE_LOOKUP(sn) #sn, sn
+
+static struct tegra_sn_addr_map tegra_grace_bpmp_sn_lookup[] = {
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { SLAVE_LOOKUP(BPMP_SN_CBB_T_BASE) },
+ { SLAVE_LOOKUP(BPMP_SN_CPU_T_BASE) },
+ { SLAVE_LOOKUP(BPMP_SN_AXI2APB_1_BASE) },
+ { SLAVE_LOOKUP(BPMP_SN_DBB0_T_BASE) },
+ { SLAVE_LOOKUP(BPMP_SN_DBB1_T_BASE) }
+};
+
+static struct tegra_sn_addr_map tegra_grace_cbb_sn_lookup[] = {
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C8_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C9_BASE) },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { SLAVE_LOOKUP(CBB_SN_AON_SLAVE_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_BPMP_SLAVE_BASE) },
+ { "RSVD", 0 },
+ { "RSVD", 0 },
+ { SLAVE_LOOKUP(CBB_SN_PSC_SLAVE_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_STM_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_1_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_10_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_11_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_12_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_13_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_14_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_15_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_16_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_17_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_18_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_19_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_2_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_20_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_4_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_5_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_6_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_7_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_8_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_9_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_3_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_21_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_22_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_23_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_24_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_25_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_26_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_27_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_28_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C4_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C5_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C6_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C7_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C2_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C3_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C0_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_PCIE_C1_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_CCPLEX_SLAVE_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_29_BASE) },
+ { SLAVE_LOOKUP(CBB_SN_AXI2APB_30_BASE) }
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2021-12-21 12:51 ` [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding Sumit Gupta
@ 2021-12-22 18:35 ` Rob Herring
2021-12-23 8:24 ` Sumit Gupta
0 siblings, 1 reply; 18+ messages in thread
From: Rob Herring @ 2021-12-22 18:35 UTC (permalink / raw)
To: Sumit Gupta
Cc: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
kbuild-all, bbasu, vsethi, jsequeira, Thierry Reding
On Tue, Dec 21, 2021 at 06:21:11PM +0530, Sumit Gupta wrote:
> Add device-tree binding documentation to represent the axi2apb bridges
> used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for APB
> slaves are reported as slave error because APB bas single bit to report
> error. So, CBB driver needs to further check error status registers of
> all the axi2apb bridges to find error type.
>
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> new file mode 100644
> index 000000000000..788a13f8aa93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: NVIDIA Tegra194 AXI2APB bridge
> +
> +maintainers:
> + - Sumit Gupta <sumitg@nvidia.com>
> +
> +properties:
> + $nodename:
> + pattern: "^axi2apb@([0-9a-f]+)$"
> +
> + compatible:
> + enum:
> + - nvidia,tegra194-axi2apb
> +
> + reg:
> + maxItems: 6
> + description: Physical base address and length of registers for all bridges
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + axi2apb: axi2apb@2390000 {
As axi2apb appears to be a bus, then all the child nodes (APB devices)
should be under this node.
Is NVidia still putting all the devices at the root level rather than
under a bus node which is preferred?
> + compatible = "nvidia,tegra194-axi2apb";
> + reg = <0x02390000 0x1000>,
> + <0x023a0000 0x1000>,
> + <0x023b0000 0x1000>,
> + <0x023c0000 0x1000>,
> + <0x023d0000 0x1000>,
> + <0x023e0000 0x1000>;
> + };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2021-12-22 18:35 ` Rob Herring
@ 2021-12-23 8:24 ` Sumit Gupta
2021-12-27 15:41 ` Rob Herring
0 siblings, 1 reply; 18+ messages in thread
From: Sumit Gupta @ 2021-12-23 8:24 UTC (permalink / raw)
To: Rob Herring
Cc: linux-tegra, linux-kernel, devicetree, thierry.reding, jonathanh,
kbuild-all, bbasu, vsethi, jsequeira, Thierry Reding,
Sumit Gupta
> On Tue, Dec 21, 2021 at 06:21:11PM +0530, Sumit Gupta wrote:
>> Add device-tree binding documentation to represent the axi2apb bridges
>> used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for APB
>> slaves are reported as slave error because APB bas single bit to report
>> error. So, CBB driver needs to further check error status registers of
>> all the axi2apb bridges to find error type.
>>
>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++
>> 1 file changed, 40 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>> new file mode 100644
>> index 000000000000..788a13f8aa93
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>> @@ -0,0 +1,40 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: NVIDIA Tegra194 AXI2APB bridge
>> +
>> +maintainers:
>> + - Sumit Gupta <sumitg@nvidia.com>
>> +
>> +properties:
>> + $nodename:
>> + pattern: "^axi2apb@([0-9a-f]+)$"
>> +
>> + compatible:
>> + enum:
>> + - nvidia,tegra194-axi2apb
>> +
>> + reg:
>> + maxItems: 6
>> + description: Physical base address and length of registers for all bridges
>> +
>> +additionalProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +examples:
>> + - |
>> + axi2apb: axi2apb@2390000 {
>
> As axi2apb appears to be a bus, then all the child nodes (APB devices)
> should be under this node.
axi2apb is a bridge which coverts an AXI to APB interface and not a bus.
CBB stretches to the various partitions using different bridges like
axi2apb, axip2p etc connected either as single or in chain.
The bridge reports if error and that gets logged in NOC's error logger.
For APB slaves, all errors are logged as slave errors as there is a
single error bit. So, we need to read the error status register of the
bridges to further triage the reason of the error.
>
> Is NVidia still putting all the devices at the root level rather than
> under a bus node which is preferred?
All the cbb noc nodes in T194 and fabric nodes in T234 are under "bus@0"
node.
>
>> + compatible = "nvidia,tegra194-axi2apb";
>> + reg = <0x02390000 0x1000>,
>> + <0x023a0000 0x1000>,
>> + <0x023b0000 0x1000>,
>> + <0x023c0000 0x1000>,
>> + <0x023d0000 0x1000>,
>> + <0x023e0000 0x1000>;
>> + };
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2021-12-23 8:24 ` Sumit Gupta
@ 2021-12-27 15:41 ` Rob Herring
2022-02-23 13:22 ` Thierry Reding
0 siblings, 1 reply; 18+ messages in thread
From: Rob Herring @ 2021-12-27 15:41 UTC (permalink / raw)
To: Sumit Gupta
Cc: linux-tegra, linux-kernel, devicetree, Thierry Reding,
Jon Hunter, kbuild-all, bbasu, vsethi, jsequeira, Thierry Reding
On Thu, Dec 23, 2021 at 4:24 AM Sumit Gupta <sumitg@nvidia.com> wrote:
> > On Tue, Dec 21, 2021 at 06:21:11PM +0530, Sumit Gupta wrote:
> >> Add device-tree binding documentation to represent the axi2apb bridges
> >> used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for APB
> >> slaves are reported as slave error because APB bas single bit to report
> >> error. So, CBB driver needs to further check error status registers of
> >> all the axi2apb bridges to find error type.
> >>
> >> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >> .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++
> >> 1 file changed, 40 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> >> new file mode 100644
> >> index 000000000000..788a13f8aa93
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> >> @@ -0,0 +1,40 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
> >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> >> +
> >> +title: NVIDIA Tegra194 AXI2APB bridge
> >> +
> >> +maintainers:
> >> + - Sumit Gupta <sumitg@nvidia.com>
> >> +
> >> +properties:
> >> + $nodename:
> >> + pattern: "^axi2apb@([0-9a-f]+)$"
> >> +
> >> + compatible:
> >> + enum:
> >> + - nvidia,tegra194-axi2apb
> >> +
> >> + reg:
> >> + maxItems: 6
> >> + description: Physical base address and length of registers for all bridges
> >> +
> >> +additionalProperties: false
> >> +
> >> +required:
> >> + - compatible
> >> + - reg
> >> +
> >> +examples:
> >> + - |
> >> + axi2apb: axi2apb@2390000 {
> >
> > As axi2apb appears to be a bus, then all the child nodes (APB devices)
> > should be under this node.
>
> axi2apb is a bridge which coverts an AXI to APB interface and not a bus.
A bus and bridge node are pretty much one and the same in DT
representation. A PCI host bridge has a PCI bus beneath it for
example.
Rob
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2021-12-27 15:41 ` Rob Herring
@ 2022-02-23 13:22 ` Thierry Reding
2022-03-16 7:45 ` Sumit Gupta
0 siblings, 1 reply; 18+ messages in thread
From: Thierry Reding @ 2022-02-23 13:22 UTC (permalink / raw)
To: Rob Herring
Cc: Sumit Gupta, linux-tegra, linux-kernel, devicetree, Jon Hunter,
kbuild-all, bbasu, vsethi, jsequeira, Thierry Reding
[-- Attachment #1: Type: text/plain, Size: 3725 bytes --]
On Mon, Dec 27, 2021 at 11:41:10AM -0400, Rob Herring wrote:
> On Thu, Dec 23, 2021 at 4:24 AM Sumit Gupta <sumitg@nvidia.com> wrote:
> > > On Tue, Dec 21, 2021 at 06:21:11PM +0530, Sumit Gupta wrote:
> > >> Add device-tree binding documentation to represent the axi2apb bridges
> > >> used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for APB
> > >> slaves are reported as slave error because APB bas single bit to report
> > >> error. So, CBB driver needs to further check error status registers of
> > >> all the axi2apb bridges to find error type.
> > >>
> > >> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> > >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> > >> ---
> > >> .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++
> > >> 1 file changed, 40 insertions(+)
> > >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> > >>
> > >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> > >> new file mode 100644
> > >> index 000000000000..788a13f8aa93
> > >> --- /dev/null
> > >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> > >> @@ -0,0 +1,40 @@
> > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > >> +%YAML 1.2
> > >> +---
> > >> +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
> > >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > >> +
> > >> +title: NVIDIA Tegra194 AXI2APB bridge
> > >> +
> > >> +maintainers:
> > >> + - Sumit Gupta <sumitg@nvidia.com>
> > >> +
> > >> +properties:
> > >> + $nodename:
> > >> + pattern: "^axi2apb@([0-9a-f]+)$"
> > >> +
> > >> + compatible:
> > >> + enum:
> > >> + - nvidia,tegra194-axi2apb
> > >> +
> > >> + reg:
> > >> + maxItems: 6
> > >> + description: Physical base address and length of registers for all bridges
> > >> +
> > >> +additionalProperties: false
> > >> +
> > >> +required:
> > >> + - compatible
> > >> + - reg
> > >> +
> > >> +examples:
> > >> + - |
> > >> + axi2apb: axi2apb@2390000 {
> > >
> > > As axi2apb appears to be a bus, then all the child nodes (APB devices)
> > > should be under this node.
> >
> > axi2apb is a bridge which coverts an AXI to APB interface and not a bus.
>
> A bus and bridge node are pretty much one and the same in DT
> representation. A PCI host bridge has a PCI bus beneath it for
> example.
Sorry for taking so long to reply, this fell through the cracks.
These aren't really bridges as such. CBB (which we call /bus@0 in DT) is
a sort of large container for all IP. Within that there are various shim
layers that connect these "legacy" interfaces to CBB. I suppose you
could call them bridges, but it's a bit of a stretch. From a software
point of view there is no observable translation happening. The only
reason why we need this is for improved error reporting.
The TRM also doesn't make a distinction between the various bridges. The
devices are all just mapped into a single address space via the CBB.
My understanding is that this is also gone in newer chips, so matters
become a bit simpler there.
Reorganizing /bus@0 into multiple bridges and busses would be a lot of
churn and likely confuse people that want to correlate what's in the TRM
to what's in DT, so I don't think it's worth it.
For newer chips we may want to keep this in mind so we structure the DT
more accurately from the beginning, though as I said, things have been
simplified a bit, so this may not be an issue anymore.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2022-02-23 13:22 ` Thierry Reding
@ 2022-03-16 7:45 ` Sumit Gupta
2022-04-07 6:24 ` Sumit Gupta
0 siblings, 1 reply; 18+ messages in thread
From: Sumit Gupta @ 2022-03-16 7:45 UTC (permalink / raw)
To: Thierry Reding, Rob Herring
Cc: linux-tegra, linux-kernel, devicetree, Jon Hunter, kbuild-all,
bbasu, vsethi, jsequeira, Thierry Reding, Sumit Gupta
>>>>> Add device-tree binding documentation to represent the axi2apb bridges
>>>>> used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for APB
>>>>> slaves are reported as slave error because APB bas single bit to report
>>>>> error. So, CBB driver needs to further check error status registers of
>>>>> all the axi2apb bridges to find error type.
>>>>>
>>>>> Signed-off-by: Sumit Gupta<sumitg@nvidia.com>
>>>>> Signed-off-by: Thierry Reding<treding@nvidia.com>
>>>>> ---
>>>>> .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++
>>>>> 1 file changed, 40 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..788a13f8aa93
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>> @@ -0,0 +1,40 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id:"http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
>>>>> +$schema:"http://devicetree.org/meta-schemas/core.yaml#"
>>>>> +
>>>>> +title: NVIDIA Tegra194 AXI2APB bridge
>>>>> +
>>>>> +maintainers:
>>>>> + - Sumit Gupta<sumitg@nvidia.com>
>>>>> +
>>>>> +properties:
>>>>> + $nodename:
>>>>> + pattern: "^axi2apb@([0-9a-f]+)$"
>>>>> +
>>>>> + compatible:
>>>>> + enum:
>>>>> + - nvidia,tegra194-axi2apb
>>>>> +
>>>>> + reg:
>>>>> + maxItems: 6
>>>>> + description: Physical base address and length of registers for all bridges
>>>>> +
>>>>> +additionalProperties: false
>>>>> +
>>>>> +required:
>>>>> + - compatible
>>>>> + - reg
>>>>> +
>>>>> +examples:
>>>>> + - |
>>>>> + axi2apb: axi2apb@2390000 {
>>>> As axi2apb appears to be a bus, then all the child nodes (APB devices)
>>>> should be under this node.
>>> axi2apb is a bridge which coverts an AXI to APB interface and not a bus.
>> A bus and bridge node are pretty much one and the same in DT
>> representation. A PCI host bridge has a PCI bus beneath it for
>> example.
> Sorry for taking so long to reply, this fell through the cracks.
>
> These aren't really bridges as such. CBB (which we call /bus@0 in DT) is
> a sort of large container for all IP. Within that there are various shim
> layers that connect these "legacy" interfaces to CBB. I suppose you
> could call them bridges, but it's a bit of a stretch. From a software
> point of view there is no observable translation happening. The only
> reason why we need this is for improved error reporting.
>
> The TRM also doesn't make a distinction between the various bridges. The
> devices are all just mapped into a single address space via the CBB.
>
> My understanding is that this is also gone in newer chips, so matters
> become a bit simpler there.
>
> Reorganizing /bus@0 into multiple bridges and busses would be a lot of
> churn and likely confuse people that want to correlate what's in the TRM
> to what's in DT, so I don't think it's worth it.
>
> For newer chips we may want to keep this in mind so we structure the DT
> more accurately from the beginning, though as I said, things have been
> simplified a bit, so this may not be an issue anymore.
>
> Thierry
Hi Thierry,
Thank you for answering the concern.
Hi Rob,
Can you please ACK to help queue the patch series for next.
Regards,
Sumit
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2022-03-16 7:45 ` Sumit Gupta
@ 2022-04-07 6:24 ` Sumit Gupta
2022-05-05 14:04 ` Rob Herring
0 siblings, 1 reply; 18+ messages in thread
From: Sumit Gupta @ 2022-04-07 6:24 UTC (permalink / raw)
To: Thierry Reding, Rob Herring
Cc: linux-tegra, linux-kernel, devicetree, Jon Hunter, kbuild-all,
bbasu, vsethi, jsequeira, Thierry Reding, Sumit Gupta
>
>>>>>> Add device-tree binding documentation to represent the axi2apb
>>>>>> bridges
>>>>>> used by Control Backbone (CBB) 1.0 in Tegra194 SOC. All errors for
>>>>>> APB
>>>>>> slaves are reported as slave error because APB bas single bit to
>>>>>> report
>>>>>> error. So, CBB driver needs to further check error status
>>>>>> registers of
>>>>>> all the axi2apb bridges to find error type.
>>>>>>
>>>>>> Signed-off-by: Sumit Gupta<sumitg@nvidia.com>
>>>>>> Signed-off-by: Thierry Reding<treding@nvidia.com>
>>>>>> ---
>>>>>> .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40
>>>>>> +++++++++++++++++++
>>>>>> 1 file changed, 40 insertions(+)
>>>>>> create mode 100644
>>>>>> Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>>
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>>
>>>>>> new file mode 100644
>>>>>> index 000000000000..788a13f8aa93
>>>>>> --- /dev/null
>>>>>> +++
>>>>>> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>>
>>>>>> @@ -0,0 +1,40 @@
>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>>> +%YAML 1.2
>>>>>> +---
>>>>>> +$id:"http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
>>>>>>
>>>>>> +$schema:"http://devicetree.org/meta-schemas/core.yaml#"
>>>>>> +
>>>>>> +title: NVIDIA Tegra194 AXI2APB bridge
>>>>>> +
>>>>>> +maintainers:
>>>>>> + - Sumit Gupta<sumitg@nvidia.com>
>>>>>> +
>>>>>> +properties:
>>>>>> + $nodename:
>>>>>> + pattern: "^axi2apb@([0-9a-f]+)$"
>>>>>> +
>>>>>> + compatible:
>>>>>> + enum:
>>>>>> + - nvidia,tegra194-axi2apb
>>>>>> +
>>>>>> + reg:
>>>>>> + maxItems: 6
>>>>>> + description: Physical base address and length of registers
>>>>>> for all bridges
>>>>>> +
>>>>>> +additionalProperties: false
>>>>>> +
>>>>>> +required:
>>>>>> + - compatible
>>>>>> + - reg
>>>>>> +
>>>>>> +examples:
>>>>>> + - |
>>>>>> + axi2apb: axi2apb@2390000 {
>>>>> As axi2apb appears to be a bus, then all the child nodes (APB devices)
>>>>> should be under this node.
>>>> axi2apb is a bridge which coverts an AXI to APB interface and not a
>>>> bus.
>>> A bus and bridge node are pretty much one and the same in DT
>>> representation. A PCI host bridge has a PCI bus beneath it for
>>> example.
>> Sorry for taking so long to reply, this fell through the cracks.
>>
>> These aren't really bridges as such. CBB (which we call /bus@0 in DT) is
>> a sort of large container for all IP. Within that there are various shim
>> layers that connect these "legacy" interfaces to CBB. I suppose you
>> could call them bridges, but it's a bit of a stretch. From a software
>> point of view there is no observable translation happening. The only
>> reason why we need this is for improved error reporting.
>>
>> The TRM also doesn't make a distinction between the various bridges. The
>> devices are all just mapped into a single address space via the CBB.
>>
>> My understanding is that this is also gone in newer chips, so matters
>> become a bit simpler there.
>>
>> Reorganizing /bus@0 into multiple bridges and busses would be a lot of
>> churn and likely confuse people that want to correlate what's in the TRM
>> to what's in DT, so I don't think it's worth it.
>>
>> For newer chips we may want to keep this in mind so we structure the DT
>> more accurately from the beginning, though as I said, things have been
>> simplified a bit, so this may not be an issue anymore.
>>
>> Thierry
>
> Hi Thierry,
> Thank you for answering the concern.
>
> Hi Rob,
> Can you please ACK to help queue the patch series for next.
>
> Regards,
> Sumit
Ping.
Regards,
Sumit
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2022-04-07 6:24 ` Sumit Gupta
@ 2022-05-05 14:04 ` Rob Herring
2022-05-05 17:19 ` Sumit Gupta
0 siblings, 1 reply; 18+ messages in thread
From: Rob Herring @ 2022-05-05 14:04 UTC (permalink / raw)
To: Sumit Gupta
Cc: Thierry Reding, linux-tegra, linux-kernel, devicetree,
Jon Hunter, kbuild-all, bbasu, vsethi, jsequeira, Thierry Reding
On Thu, Apr 07, 2022 at 11:54:16AM +0530, Sumit Gupta wrote:
>
> >
> > > > > > > Add device-tree binding documentation to represent
> > > > > > > the axi2apb bridges
> > > > > > > used by Control Backbone (CBB) 1.0 in Tegra194 SOC.
> > > > > > > All errors for APB
> > > > > > > slaves are reported as slave error because APB bas
> > > > > > > single bit to report
> > > > > > > error. So, CBB driver needs to further check error
> > > > > > > status registers of
> > > > > > > all the axi2apb bridges to find error type.
> > > > > > >
> > > > > > > Signed-off-by: Sumit Gupta<sumitg@nvidia.com>
> > > > > > > Signed-off-by: Thierry Reding<treding@nvidia.com>
> > > > > > > ---
> > > > > > > .../arm/tegra/nvidia,tegra194-axi2apb.yaml |
> > > > > > > 40 +++++++++++++++++++
> > > > > > > 1 file changed, 40 insertions(+)
> > > > > > > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> > > > > > >
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> > > > > > >
> > > > > > > new file mode 100644
> > > > > > > index 000000000000..788a13f8aa93
> > > > > > > --- /dev/null
> > > > > > > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
> > > > > > >
> > > > > > > @@ -0,0 +1,40 @@
> > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > +%YAML 1.2
> > > > > > > +---
> > > > > > > +$id:"http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
> > > > > > >
> > > > > > > +$schema:"http://devicetree.org/meta-schemas/core.yaml#"
> > > > > > > +
> > > > > > > +title: NVIDIA Tegra194 AXI2APB bridge
> > > > > > > +
> > > > > > > +maintainers:
> > > > > > > + - Sumit Gupta<sumitg@nvidia.com>
> > > > > > > +
> > > > > > > +properties:
> > > > > > > + $nodename:
> > > > > > > + pattern: "^axi2apb@([0-9a-f]+)$"
> > > > > > > +
> > > > > > > + compatible:
> > > > > > > + enum:
> > > > > > > + - nvidia,tegra194-axi2apb
> > > > > > > +
> > > > > > > + reg:
> > > > > > > + maxItems: 6
> > > > > > > + description: Physical base address and length
> > > > > > > of registers for all bridges
> > > > > > > +
> > > > > > > +additionalProperties: false
> > > > > > > +
> > > > > > > +required:
> > > > > > > + - compatible
> > > > > > > + - reg
> > > > > > > +
> > > > > > > +examples:
> > > > > > > + - |
> > > > > > > + axi2apb: axi2apb@2390000 {
> > > > > > As axi2apb appears to be a bus, then all the child nodes (APB devices)
> > > > > > should be under this node.
> > > > > axi2apb is a bridge which coverts an AXI to APB interface
> > > > > and not a bus.
> > > > A bus and bridge node are pretty much one and the same in DT
> > > > representation. A PCI host bridge has a PCI bus beneath it for
> > > > example.
> > > Sorry for taking so long to reply, this fell through the cracks.
> > >
> > > These aren't really bridges as such. CBB (which we call /bus@0 in DT) is
> > > a sort of large container for all IP. Within that there are various shim
> > > layers that connect these "legacy" interfaces to CBB. I suppose you
> > > could call them bridges, but it's a bit of a stretch. From a software
> > > point of view there is no observable translation happening. The only
> > > reason why we need this is for improved error reporting.
> > >
> > > The TRM also doesn't make a distinction between the various bridges. The
> > > devices are all just mapped into a single address space via the CBB.
> > >
> > > My understanding is that this is also gone in newer chips, so matters
> > > become a bit simpler there.
> > >
> > > Reorganizing /bus@0 into multiple bridges and busses would be a lot of
> > > churn and likely confuse people that want to correlate what's in the TRM
> > > to what's in DT, so I don't think it's worth it.
> > >
> > > For newer chips we may want to keep this in mind so we structure the DT
> > > more accurately from the beginning, though as I said, things have been
> > > simplified a bit, so this may not be an issue anymore.
> > >
> > > Thierry
> >
> > Hi Thierry,
> > Thank you for answering the concern.
> >
> > Hi Rob,
> > Can you please ACK to help queue the patch series for next.
> >
> > Regards,
> > Sumit
>
> Ping.
No one is going to apply a 4 month old patch. For starters, the DT
meta-schema evolves and this could now have errors. Please resend.
Rob
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding
2022-05-05 14:04 ` Rob Herring
@ 2022-05-05 17:19 ` Sumit Gupta
0 siblings, 0 replies; 18+ messages in thread
From: Sumit Gupta @ 2022-05-05 17:19 UTC (permalink / raw)
To: Rob Herring
Cc: Thierry Reding, linux-tegra, linux-kernel, devicetree,
Jon Hunter, kbuild-all, bbasu, vsethi, jsequeira, Thierry Reding,
Sumit Gupta
On 05/05/22 19:34, Rob Herring wrote:
> External email: Use caution opening links or attachments
>
>
> On Thu, Apr 07, 2022 at 11:54:16AM +0530, Sumit Gupta wrote:
>>
>>>
>>>>>>>> Add device-tree binding documentation to represent
>>>>>>>> the axi2apb bridges
>>>>>>>> used by Control Backbone (CBB) 1.0 in Tegra194 SOC.
>>>>>>>> All errors for APB
>>>>>>>> slaves are reported as slave error because APB bas
>>>>>>>> single bit to report
>>>>>>>> error. So, CBB driver needs to further check error
>>>>>>>> status registers of
>>>>>>>> all the axi2apb bridges to find error type.
>>>>>>>>
>>>>>>>> Signed-off-by: Sumit Gupta<sumitg@nvidia.com>
>>>>>>>> Signed-off-by: Thierry Reding<treding@nvidia.com>
>>>>>>>> ---
>>>>>>>> .../arm/tegra/nvidia,tegra194-axi2apb.yaml |
>>>>>>>> 40 +++++++++++++++++++
>>>>>>>> 1 file changed, 40 insertions(+)
>>>>>>>> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>>>>
>>>>>>>>
>>>>>>>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>>>>
>>>>>>>> new file mode 100644
>>>>>>>> index 000000000000..788a13f8aa93
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
>>>>>>>>
>>>>>>>> @@ -0,0 +1,40 @@
>>>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>>>>> +%YAML 1.2
>>>>>>>> +---
>>>>>>>> +$id:"http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
>>>>>>>>
>>>>>>>> +$schema:"http://devicetree.org/meta-schemas/core.yaml#"
>>>>>>>> +
>>>>>>>> +title: NVIDIA Tegra194 AXI2APB bridge
>>>>>>>> +
>>>>>>>> +maintainers:
>>>>>>>> + - Sumit Gupta<sumitg@nvidia.com>
>>>>>>>> +
>>>>>>>> +properties:
>>>>>>>> + $nodename:
>>>>>>>> + pattern: "^axi2apb@([0-9a-f]+)$"
>>>>>>>> +
>>>>>>>> + compatible:
>>>>>>>> + enum:
>>>>>>>> + - nvidia,tegra194-axi2apb
>>>>>>>> +
>>>>>>>> + reg:
>>>>>>>> + maxItems: 6
>>>>>>>> + description: Physical base address and length
>>>>>>>> of registers for all bridges
>>>>>>>> +
>>>>>>>> +additionalProperties: false
>>>>>>>> +
>>>>>>>> +required:
>>>>>>>> + - compatible
>>>>>>>> + - reg
>>>>>>>> +
>>>>>>>> +examples:
>>>>>>>> + - |
>>>>>>>> + axi2apb: axi2apb@2390000 {
>>>>>>> As axi2apb appears to be a bus, then all the child nodes (APB devices)
>>>>>>> should be under this node.
>>>>>> axi2apb is a bridge which coverts an AXI to APB interface
>>>>>> and not a bus.
>>>>> A bus and bridge node are pretty much one and the same in DT
>>>>> representation. A PCI host bridge has a PCI bus beneath it for
>>>>> example.
>>>> Sorry for taking so long to reply, this fell through the cracks.
>>>>
>>>> These aren't really bridges as such. CBB (which we call /bus@0 in DT) is
>>>> a sort of large container for all IP. Within that there are various shim
>>>> layers that connect these "legacy" interfaces to CBB. I suppose you
>>>> could call them bridges, but it's a bit of a stretch. From a software
>>>> point of view there is no observable translation happening. The only
>>>> reason why we need this is for improved error reporting.
>>>>
>>>> The TRM also doesn't make a distinction between the various bridges. The
>>>> devices are all just mapped into a single address space via the CBB.
>>>>
>>>> My understanding is that this is also gone in newer chips, so matters
>>>> become a bit simpler there.
>>>>
>>>> Reorganizing /bus@0 into multiple bridges and busses would be a lot of
>>>> churn and likely confuse people that want to correlate what's in the TRM
>>>> to what's in DT, so I don't think it's worth it.
>>>>
>>>> For newer chips we may want to keep this in mind so we structure the DT
>>>> more accurately from the beginning, though as I said, things have been
>>>> simplified a bit, so this may not be an issue anymore.
>>>>
>>>> Thierry
>>>
>>> Hi Thierry,
>>> Thank you for answering the concern.
>>>
>>> Hi Rob,
>>> Can you please ACK to help queue the patch series for next.
>>>
>>> Regards,
>>> Sumit
>>
>> Ping.
>
> No one is going to apply a 4 month old patch. For starters, the DT
> meta-schema evolves and this could now have errors. Please resend.
>
Sent v4 with rebased patches on linux-next.
Regards,
Sumit
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-05-05 17:20 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-21 12:51 [Patch v3 0/9] CBB driver for Tegra194, Tegra234 & Tegra-Grace Sumit Gupta
2021-12-21 12:51 ` [Patch v3 1/9] soc: tegra: set ERD bit to mask inband errors Sumit Gupta
2021-12-21 12:51 ` [Patch v3 2/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding Sumit Gupta
2021-12-21 12:51 ` [Patch v3 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding Sumit Gupta
2021-12-22 18:35 ` Rob Herring
2021-12-23 8:24 ` Sumit Gupta
2021-12-27 15:41 ` Rob Herring
2022-02-23 13:22 ` Thierry Reding
2022-03-16 7:45 ` Sumit Gupta
2022-04-07 6:24 ` Sumit Gupta
2022-05-05 14:04 ` Rob Herring
2022-05-05 17:19 ` Sumit Gupta
2021-12-21 12:51 ` [Patch v3 4/9] arm64: tegra: Add node for CBB1.0 in Tegra194 SOC Sumit Gupta
2021-12-21 12:51 ` [Patch v3 5/9] soc: tegra: cbb: Add CBB1.0 driver for Tegra194 Sumit Gupta
2021-12-21 12:51 ` [Patch v3 6/9] dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB2.0 binding Sumit Gupta
2021-12-21 12:51 ` [Patch v3 7/9] arm64: tegra: Add node for CBB2.0 in Tegra234 SOC Sumit Gupta
2021-12-21 12:51 ` [Patch v3 8/9] soc: tegra: cbb: Add driver for Tegra234 CBB2.0 Sumit Gupta
2021-12-21 12:51 ` [Patch v3 9/9] soc: tegra: cbb: Add support for tegra-grace SOC Sumit Gupta
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