[GIT PULL] parisc architecture cache flush fixes for v5.18

* [GIT PULL] parisc architecture cache flush fixes for v5.18
@ 2022-05-19 15:39 Helge Deller
  2022-05-19 16:14 ` pr-tracker-bot
  0 siblings, 1 reply; 2+ messages in thread
From: Helge Deller @ 2022-05-19 15:39 UTC (permalink / raw)
  To: Linus Torvalds, linux-kernel, linux-parisc, James Bottomley,
	John David Anglin

Hi Linus,

please pull the latest parisc architecture fixes for kernel v5.18.

We had two big outstanding issues after v5.18-rc6:

a) 32-bit kernels on 64-bit machines (e.g. on a C3700 which is able to run 32-
and 64-bit kernels) failed early in userspace.

b) 64-bit kernels on PA8800/PA8900 CPUs (e.g. in a C8000) showed random
userspace segfaults. We assumed that those problems were caused by the
tmpalias flushes.

Dave did a lot of testing and reorganization of the current flush code and
fixed the 32-bit cache flushing. For PA8800/PA8900 CPUs he switched the code to
flush using the virtual address of user and kernel pages instead of using
tmpalias flushes.  The tmpalias flushes don't seem to work reliable on such
CPUs.

We tested the patches on a wide range machines (715/64, B160L, C3000,
C3700, C8000, rp3440) and they have been in for-next without any
conflicts.

Please pull.

Thanks,
Helge

----------------------------------------------------------------

The following changes since commit 42226c989789d8da4af1de0c31070c96726d990c:

  Linux 5.18-rc7 (2022-05-15 18:08:58 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git tags/for-5.18/parisc-4

for you to fetch changes up to 798082be69fea995a475ca1db8f9873589e207d9:

  parisc: Fix patch code locking and flushing (2022-05-17 21:52:59 +0200)

----------------------------------------------------------------
parisc architecture fixes for kernel v5.18

Rewrite the cache flush code for PA8800/PA8900 CPUs to flush using the virtual
address of user and kernel pages instead of using tmpalias flushes. Testing
showed, that tmpalias flushes don't work reliable on PA8800/PA8900 CPUs.

Fix flush code to allow 32-bit kernels to run on 64-bit capable machines, e.g.
a 32-bit kernel on C3700 machines.

----------------------------------------------------------------
John David Anglin (3):
      parisc: Disable debug code regarding cache flushes in handle_nadtlb_fault()
      parisc: Rewrite cache flush code for PA8800/PA8900
      parisc: Fix patch code locking and flushing

 arch/parisc/include/asm/cacheflush.h |  31 +---
 arch/parisc/include/asm/page.h       |   6 +-
 arch/parisc/kernel/cache.c           | 326 ++++++++++++++++++++++++-----------
 arch/parisc/kernel/patch.c           |  25 ++-
 arch/parisc/mm/fault.c               |   6 +-
 5 files changed, 251 insertions(+), 143 deletions(-)

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