* [PATCH] EDAC/ie31200: Add Skylake-S support
@ 2022-03-22 18:47 joshuahant
2022-03-29 14:58 ` Jason Baron
0 siblings, 1 reply; 7+ messages in thread
From: joshuahant @ 2022-03-22 18:47 UTC (permalink / raw)
To: jbaron; +Cc: linux-edac, linux-kernel, joshuahant
From: Josh Hant <joshuahant@gmail.com>
Add device IDs for Skylake-S CPUs according to datasheet.
Signed-off-by: Josh Hant <joshuahant@gmail.com>
---
Dear all,
I found that edac-util -v shows no memory controllers when using an
Intel i5-6100T with a Supermicro X11SAE motherboard. With this patch,
the ECC memory is detected. I tried to follow previous patches
that added new families of processors to the module.
This is my first submission to the kernel so please let me know if I
missed something in the process.
Thanks,
Josh Hant
drivers/edac/ie31200_edac.c | 26 +++++++++++++++++---------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index 9a9ff5ad611a..96a3f70d06e6 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -20,11 +20,14 @@
* 0c08: Xeon E3-1200 v3 Processor DRAM Controller
* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
* 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
+ * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
+ * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
* 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
*
* Based on Intel specification:
* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
+ * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
* https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
* https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
*
@@ -53,15 +56,17 @@
#define ie31200_printk(level, fmt, arg...) \
edac_printk(level, "ie31200", fmt, ##arg)
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
/* Coffee Lake-S */
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
@@ -80,6 +85,7 @@
#define DEVICE_ID_SKYLAKE_OR_LATER(did) \
(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
+ ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
(((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
@@ -577,6 +583,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
{ PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+ { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+ { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] EDAC/ie31200: Add Skylake-S support
2022-03-22 18:47 [PATCH] EDAC/ie31200: Add Skylake-S support joshuahant
@ 2022-03-29 14:58 ` Jason Baron
2022-07-12 10:21 ` [PATCH v2] " Josh Hant
0 siblings, 1 reply; 7+ messages in thread
From: Jason Baron @ 2022-03-29 14:58 UTC (permalink / raw)
To: joshuahant; +Cc: linux-edac, linux-kernel
On 3/22/22 14:47, joshuahant@gmail.com wrote:
> From: Josh Hant <joshuahant@gmail.com>
>
> Add device IDs for Skylake-S CPUs according to datasheet.
>
> Signed-off-by: Josh Hant <joshuahant@gmail.com>
> ---
> Dear all,
>
> I found that edac-util -v shows no memory controllers when using an
> Intel i5-6100T with a Supermicro X11SAE motherboard. With this patch,
> the ECC memory is detected. I tried to follow previous patches
> that added new families of processors to the module.
>
> This is my first submission to the kernel so please let me know if I
> missed something in the process.
>
> Thanks,
> Josh Hant
>
Hi Josh,
Thanks for your submission! Some comments below.
> drivers/edac/ie31200_edac.c | 26 +++++++++++++++++---------
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
> index 9a9ff5ad611a..96a3f70d06e6 100644
> --- a/drivers/edac/ie31200_edac.c
> +++ b/drivers/edac/ie31200_edac.c
> @@ -20,11 +20,14 @@
> * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
> * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
> * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
> + * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
> + * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
> * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
> *
> * Based on Intel specification:
> * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf__;!!GjvTz_vk!AMVZ8h7gNGrptmwFk4tdnr0n6gUXJhZWRRjaZ3_usWEhORCh3fhbT-HVOitdUQ$
> * https://urldefense.com/v3/__http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html__;!!GjvTz_vk!AMVZ8h7gNGrptmwFk4tdnr0n6gUXJhZWRRjaZ3_usWEhORCh3fhbT-HdDfO4eA$
> + * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf__;!!GjvTz_vk!AMVZ8h7gNGrptmwFk4tdnr0n6gUXJhZWRRjaZ3_usWEhORCh3fhbT-Ef_03qbw$
I didn't find register #s in the above doc. But this one seems to have them:
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html__;!!GjvTz_vk!AMVZ8h7gNGrptmwFk4tdnr0n6gUXJhZWRRjaZ3_usWEhORCh3fhbT-EznD3gEQ$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html__;!!GjvTz_vk!AMVZ8h7gNGrptmwFk4tdnr0n6gUXJhZWRRjaZ3_usWEhORCh3fhbT-FmC7_jRg$
> *
> @@ -53,15 +56,17 @@
> #define ie31200_printk(level, fmt, arg...) \
> edac_printk(level, "ie31200", fmt, ##arg)
>
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
>
> /* Coffee Lake-S */
> #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
> @@ -80,6 +85,7 @@
> #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
> (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
> ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
> (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
> PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
Looks like PCI_DEVICE_ID_INTEL_IE31200_HB_11 is missing from this check? IE you added
two new device ids, but added only 1 new check?
>
> @@ -577,6 +583,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
> { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> --
> 2.34.1
>
Also, just to confirm that after this patch the edac memory info/size is consistent with
what's in /proc/meminfo, dmidecode -t memory?
Thanks,
-Jason
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2] EDAC/ie31200: Add Skylake-S support
2022-03-29 14:58 ` Jason Baron
@ 2022-07-12 10:21 ` Josh Hant
2022-07-15 14:52 ` Jason Baron
0 siblings, 1 reply; 7+ messages in thread
From: Josh Hant @ 2022-07-12 10:21 UTC (permalink / raw)
To: jbaron; +Cc: joshuahant, linux-edac, linux-kernel
Add device IDs for Skylake-S CPUs according to datasheet.
Signed-off-by: Josh Hant <joshuahant@gmail.com>
---
Hi Jason,
Sorry for the late response. I added the missing check you asked for. I
kept the documentation the same for now. I found the register in table 3
of the original document I linked. If you would rather I provide the one
you linked, I'll do that in the next patch.
I confirmed that the name and size in /proc/meminfo is consistent with
what is in /sys/devices/system/edac/mc/mc0.
Thanks
-Josh
drivers/edac/ie31200_edac.c | 27 ++++++++++++++++++---------
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index 9a9ff5ad611a..3d322603bce8 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -20,11 +20,14 @@
* 0c08: Xeon E3-1200 v3 Processor DRAM Controller
* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
* 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
+ * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
+ * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
* 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
*
* Based on Intel specification:
* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
+ * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
* https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
* https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
*
@@ -53,15 +56,17 @@
#define ie31200_printk(level, fmt, arg...) \
edac_printk(level, "ie31200", fmt, ##arg)
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
/* Coffee Lake-S */
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
@@ -80,6 +85,8 @@
#define DEVICE_ID_SKYLAKE_OR_LATER(did) \
(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
+ ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
+ ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
(((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
@@ -577,6 +584,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
{ PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+ { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+ { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
--
2.34.3
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2] EDAC/ie31200: Add Skylake-S support
2022-07-12 10:21 ` [PATCH v2] " Josh Hant
@ 2022-07-15 14:52 ` Jason Baron
2022-07-16 0:53 ` [PATCH v3] " Josh Hant
0 siblings, 1 reply; 7+ messages in thread
From: Jason Baron @ 2022-07-15 14:52 UTC (permalink / raw)
To: Josh Hant; +Cc: linux-edac, linux-kernel
On 7/12/22 06:21, Josh Hant wrote:
> Add device IDs for Skylake-S CPUs according to datasheet.
>
> Signed-off-by: Josh Hant <joshuahant@gmail.com>
> ---
> Hi Jason,
>
> Sorry for the late response. I added the missing check you asked for. I
> kept the documentation the same for now. I found the register in table 3
> of the original document I linked. If you would rather I provide the one
> you linked, I'll do that in the next patch.
Yes, I think the link I had was useful, for example it had register offsets
for things like ECCERRLOG which I didn't see in the reference you linked.
Maybe just include both?
>
> I confirmed that the name and size in /proc/meminfo is consistent with
> what is in /sys/devices/system/edac/mc/mc0.
Ok, great. Yeah let's just add the extra documentation link and then the
patch seems fine.
Thanks,
-Jason
>
> Thanks
> -Josh
> drivers/edac/ie31200_edac.c | 27 ++++++++++++++++++---------
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
> index 9a9ff5ad611a..3d322603bce8 100644
> --- a/drivers/edac/ie31200_edac.c
> +++ b/drivers/edac/ie31200_edac.c
> @@ -20,11 +20,14 @@
> * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
> * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
> * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
> + * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
> + * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
> * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
> *
> * Based on Intel specification:
> * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9oZ-6raD$
> * https://urldefense.com/v3/__http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9m6NRBGA$
> + * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9gF6-zMQ$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9q7dFz1H$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9vbMAhyi$
> *
> @@ -53,15 +56,17 @@
> #define ie31200_printk(level, fmt, arg...) \
> edac_printk(level, "ie31200", fmt, ##arg)
>
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
>
> /* Coffee Lake-S */
> #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
> @@ -80,6 +85,8 @@
> #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
> (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
> ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
> (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
> PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
>
> @@ -577,6 +584,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
> { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> --
> 2.34.3
>
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3] EDAC/ie31200: Add Skylake-S support
2022-07-15 14:52 ` Jason Baron
@ 2022-07-16 0:53 ` Josh Hant
2022-07-19 17:02 ` Jason Baron
2022-08-25 8:37 ` Borislav Petkov
0 siblings, 2 replies; 7+ messages in thread
From: Josh Hant @ 2022-07-16 0:53 UTC (permalink / raw)
To: jbaron; +Cc: joshuahant, linux-edac, linux-kernel
Add device IDs for Skylake-S CPUs according to datasheet.
Signed-off-by: Josh Hant <joshuahant@gmail.com>
---
Here is the patch with both documents included.
Thanks,
Josh
drivers/edac/ie31200_edac.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index 9a9ff5ad611a..9ef13570f2e5 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -20,11 +20,15 @@
* 0c08: Xeon E3-1200 v3 Processor DRAM Controller
* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
* 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
+ * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
+ * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
* 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
*
* Based on Intel specification:
* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
+ * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
+ * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
* https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
* https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
*
@@ -53,15 +57,17 @@
#define ie31200_printk(level, fmt, arg...) \
edac_printk(level, "ie31200", fmt, ##arg)
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
/* Coffee Lake-S */
#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
@@ -80,6 +86,8 @@
#define DEVICE_ID_SKYLAKE_OR_LATER(did) \
(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
+ ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
+ ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
(((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
@@ -577,6 +585,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
{ PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+ { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+ { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
--
2.34.3
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3] EDAC/ie31200: Add Skylake-S support
2022-07-16 0:53 ` [PATCH v3] " Josh Hant
@ 2022-07-19 17:02 ` Jason Baron
2022-08-25 8:37 ` Borislav Petkov
1 sibling, 0 replies; 7+ messages in thread
From: Jason Baron @ 2022-07-19 17:02 UTC (permalink / raw)
To: Josh Hant; +Cc: linux-edac, linux-kernel
Hi Josh,
Looks good to me.
Acked-by: Jason Baron <jbaron@akamai.com>
Thanks,
-Jason
On 7/15/22 20:53, Josh Hant wrote:
> Add device IDs for Skylake-S CPUs according to datasheet.
>
> Signed-off-by: Josh Hant <joshuahant@gmail.com>
> ---
> Here is the patch with both documents included.
>
> Thanks,
> Josh
>
> drivers/edac/ie31200_edac.c | 28 +++++++++++++++++++---------
> 1 file changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
> index 9a9ff5ad611a..9ef13570f2e5 100644
> --- a/drivers/edac/ie31200_edac.c
> +++ b/drivers/edac/ie31200_edac.c
> @@ -20,11 +20,15 @@
> * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
> * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
> * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
> + * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
> + * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
> * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
> *
> * Based on Intel specification:
> * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf__;!!GjvTz_vk!XBdwBoztmGI-G7Ww0phwMfPvN7k3bH9_oq608DA9wgZX2IvKs2b7iWC9cI9-LQX5DtlulP9A73HxkjTU$
> * https://urldefense.com/v3/__http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html__;!!GjvTz_vk!XBdwBoztmGI-G7Ww0phwMfPvN7k3bH9_oq608DA9wgZX2IvKs2b7iWC9cI9-LQX5DtlulP9A7-ew3RWq$
> + * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf__;!!GjvTz_vk!XBdwBoztmGI-G7Ww0phwMfPvN7k3bH9_oq608DA9wgZX2IvKs2b7iWC9cI9-LQX5DtlulP9A7yvc2EC2$
> + * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf__;!!GjvTz_vk!XBdwBoztmGI-G7Ww0phwMfPvN7k3bH9_oq608DA9wgZX2IvKs2b7iWC9cI9-LQX5DtlulP9A7zHkZoPB$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html__;!!GjvTz_vk!XBdwBoztmGI-G7Ww0phwMfPvN7k3bH9_oq608DA9wgZX2IvKs2b7iWC9cI9-LQX5DtlulP9A75WQ5pDp$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html__;!!GjvTz_vk!XBdwBoztmGI-G7Ww0phwMfPvN7k3bH9_oq608DA9wgZX2IvKs2b7iWC9cI9-LQX5DtlulP9A7wPGcDEO$
> *
> @@ -53,15 +57,17 @@
> #define ie31200_printk(level, fmt, arg...) \
> edac_printk(level, "ie31200", fmt, ##arg)
>
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
>
> /* Coffee Lake-S */
> #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
> @@ -80,6 +86,8 @@
> #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
> (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
> ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
> (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
> PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
>
> @@ -577,6 +585,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
> { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> --
> 2.34.3
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3] EDAC/ie31200: Add Skylake-S support
2022-07-16 0:53 ` [PATCH v3] " Josh Hant
2022-07-19 17:02 ` Jason Baron
@ 2022-08-25 8:37 ` Borislav Petkov
1 sibling, 0 replies; 7+ messages in thread
From: Borislav Petkov @ 2022-08-25 8:37 UTC (permalink / raw)
To: Josh Hant; +Cc: jbaron, linux-edac, linux-kernel
On Fri, Jul 15, 2022 at 08:53:48PM -0400, Josh Hant wrote:
> Add device IDs for Skylake-S CPUs according to datasheet.
>
> Signed-off-by: Josh Hant <joshuahant@gmail.com>
> ---
> Here is the patch with both documents included.
>
> Thanks,
> Josh
>
> drivers/edac/ie31200_edac.c | 28 +++++++++++++++++++---------
> 1 file changed, 19 insertions(+), 9 deletions(-)
Applied, thanks.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-08-25 8:37 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-22 18:47 [PATCH] EDAC/ie31200: Add Skylake-S support joshuahant
2022-03-29 14:58 ` Jason Baron
2022-07-12 10:21 ` [PATCH v2] " Josh Hant
2022-07-15 14:52 ` Jason Baron
2022-07-16 0:53 ` [PATCH v3] " Josh Hant
2022-07-19 17:02 ` Jason Baron
2022-08-25 8:37 ` Borislav Petkov
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