[PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

v5 -- Remove DT property "brcm,completion-timeout-us" from	 
      "DT bindings" commit.  Although this error may be reported	 
      as a completion timeout, its cause was traced to an	 
      internal bus timeout which may occur even when there is	 
      no PCIe access being processed.  We set a timeout of four	 
      seconds only if we are operating in "L1SS CLKREQ#" mode.
   -- Correct CEM 2.0 reference provided by HW engineer,
      s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
   -- Add newline to dev_info() string (Stefan)
   -- Change variable rval to unsigned (Stefan)
   -- s/implementaion/implementation/ (Bjorn)
   -- s/superpowersave/powersupersave/ (Bjorn)
   -- Slightly modify message on "PERST#" commit.
   -- Rebase to torvalds master

v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
      driver probe() time.  This is done in Raspian Linux and its
      absence may be the cause of a failing test case.
   -- New commit that removes stale comment.

v3 -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)
   -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
   -- Put binding names in DT commit Subject (Bjorn)
   -- Add a verb to a commit's subject line (Bjorn)
   -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
   -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)

v2 -- Changed binding property 'brcm,completion-timeout-msec' to
      'brcm,completion-timeout-us'.  (StefanW for standard suffix).
   -- Warn when clamping timeout value, and include clamped
      region in message. Also add min and max in YAML. (StefanW)
   -- Qualify description of "brcm,completion-timeout-us" so that
      it refers to PCIe transactions. (StefanW)
   -- Remvove mention of Linux specifics in binding description. (StefanW)
   -- s/clkreq#/CLKREQ#/g (Bjorn)
   -- Refactor completion-timeout-us code to compare max and min to
      value given by the property (as opposed to the computed value).

v1 -- The current driver assumes the downstream devices can
      provide CLKREQ# for ASPM.  These commits accomodate devices
      w/ or w/o clkreq# and also handle L1SS-capable devices.

   -- The Raspian Linux folks have already been using a PCIe RC
      property "brcm,enable-l1ss".  These commits use the same
      property, in a backward-compatible manner, and the implementaion
      adds more detail and also automatically identifies devices w/o
      a clkreq# signal, i.e. most devices plugged into an RPi CM4
      IO board.

Jim Quinlan (5):
  dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
  PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
    device
  PCI: brcmstb: Set higher value for internal bus timeout
  PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted
  PCI: brcmstb: Remove stale comment

 .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
 drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
 2 files changed, 89 insertions(+), 11 deletions(-)


base-commit: ac9a78681b921877518763ba0e89202254349d1b
-- 
2.17.1

[PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

This commit adds the boolean "brcm,enable-l1ss" property:

  The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
  requires the driver probe() to deliberately place the HW one of three
  CLKREQ# modes:

  (a) CLKREQ# driven by the RC unconditionally
  (b) CLKREQ# driven by the EP for ASPM L0s, L1
  (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).

  The HW+driver can tell the difference between downstream devices that
  need (a) and (b), but does not know when to configure (c).  All devices
  should work fine when the driver chooses (a) or (b), but (c) may be
  desired to realize the extra power savings that L1SS offers.  So we
  introduce the boolean "brcm,enable-l1ss" property to inform the driver
  that (c) is desired.  Setting this property only makes sense when the
  downstream device is L1SS-capable and the OS is configured to activate
  this mode (e.g. policy==powersupersave).

  This property is already present in the Raspian version of Linux, but the
  upstream driver implementation that follows adds more details and
  discerns between (a) and (b).

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 7e15aae7d69e..8b61c2179608 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -64,6 +64,15 @@ properties:
 
   aspm-no-l0s: true
 
+  brcm,enable-l1ss:
+    description: Indicates that PCIe L1SS power savings
+      are desired, the downstream device is L1SS-capable, and the
+      OS has been configured to enable this mode.  For boards
+      using a mini-card connector, this mode may not meet the
+      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
+      of the PCI Express Mini CEM 2.0 specification.
+    type: boolean
+
   brcm,scb-sizes:
     description: u64 giving the 64bit PCIe memory
       viewport size of a memory controller.  There may be up to
-- 
2.17.1

[PATCH v5 2/5] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device

[Jim Quinlan]

The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be
deliberately set by the RC probe() into one of three mutually exclusive
modes:

  (a) No CLKREQ# expected or required, refclk is always available.
  (b) CLKREQ# is expected to be driven by downstream device when needed.
  (c) Bidirectional CLKREQ# for L1SS capable devices.

Previously, only (b) was supported by the driver, as almost all STB/CM
boards operate in this mode.  But now there is interest in activating L1SS
power savings from STB/CM customers, and also interest in accommodating
mode (a) for designs such as the RPi CM4 with IO board.

The HW+driver is able to tell us when mode (a) or (b) is needed.  All
devices should be functional using the RC-driver selected (a) or (b) mode.
For those with L1SS-capable devices that desire the power savings that come
with mode (c) we rely on the DT prop "brcm,enable-l1ss".  It would be nice
to do this automatically but there is no easy way to determine this at the
time the PCI RC driver executes its probe().  Using this mode only makes
sense when the downstream device is L1SS-capable and the OS has been
configured to activate L1SS (e.g. policy==powersupersave).

The "brcm,enable-l1ss" property has already been in use by Raspian Linux,
but this implementation adds more details and discerns between (a) and (b)
automatically.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 69 +++++++++++++++++++++++----
 1 file changed, 59 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index edf283e2b5dd..d30636a725d7 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -48,10 +48,17 @@
 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY			0x04dc
 #define  PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK	0xc00
 
+#define PCIE_RC_CFG_PRIV1_ROOT_CAP			0x4f8
+#define  PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK	0xf8
+
 #define PCIE_RC_DL_MDIO_ADDR				0x1100
 #define PCIE_RC_DL_MDIO_WR_DATA				0x1104
 #define PCIE_RC_DL_MDIO_RD_DATA				0x1108
 
+#define PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0			0x1e30
+#define  CLKREQ2_0_CLKREQ_IN_CNT_MASK			0x3f000000
+#define  CLKREQ2_0_CLKREQ_IN_MASK			0x40000000
+
 #define PCIE_MISC_MISC_CTRL				0x4008
 #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK	0x80
 #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK	0x400
@@ -121,9 +128,12 @@
 
 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG					0x4204
 #define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK		0x200000
 #define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
 #define  PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x00800000
-
+#define  PCIE_CLKREQ_MASK \
+	  (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \
+	   PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK)
 
 #define PCIE_INTR2_CPU_BASE		0x4300
 #define PCIE_MSI_INTR2_BASE		0x4500
@@ -1024,13 +1034,58 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 	return 0;
 }
 
+static void brcm_config_clkreq(struct brcm_pcie *pcie)
+{
+	bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
+	void __iomem *base = pcie->base;
+	u32 clkreq_set, tmp = readl(base + PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0);
+	bool clkreq_in_seen;
+
+	/*
+	 * We have "seen" CLKREQ# if it is asserted or has been in the past.
+	 * Note that the CLKREQ_IN_MASK is 1 if CLKREQ# is asserted.
+	 */
+	clkreq_in_seen = !!(tmp & CLKREQ2_0_CLKREQ_IN_MASK) ||
+		!!FIELD_GET(CLKREQ2_0_CLKREQ_IN_CNT_MASK, tmp);
+
+	/* Start with safest setting where we provide refclk regardless */
+	clkreq_set = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG) &
+		~PCIE_CLKREQ_MASK;
+
+	if (l1ss && IS_ENABLED(CONFIG_PCIEASPM)) {
+		/*
+		 * Note: For boards using a mini-card connector, this mode
+		 * (L1SS CLKREQ# mode) may not meet the TCRLon maximum time
+		 * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
+		 * Mini CEM 2.0 specification.
+		 */
+		clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
+		dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
+	} else {
+		if (clkreq_in_seen && IS_ENABLED(CONFIG_PCIEASPM)) {
+			clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+			dev_info(pcie->dev, "uni-dir CLKREQ# for L0s, L1 ASPM\n");
+		} else {
+			dev_info(pcie->dev, "CLKREQ# ignored; no ASPM\n");
+			/* Might as well unadvertise ASPM */
+			tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY) &
+				~PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK;
+			writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+		}
+		/* Setting the field to 2 unadvertises L1SS support */
+		tmp = readl(base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
+		u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK);
+		writel(tmp, base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
+	}
+	writel(clkreq_set, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
+}
+
 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	void __iomem *base = pcie->base;
 	u16 nlw, cls, lnksta;
 	bool ssc_good = false;
-	u32 tmp;
 	int ret, i;
 
 	/* Unassert the fundamental reset */
@@ -1055,6 +1110,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
 		return -ENODEV;
 	}
 
+	brcm_config_clkreq(pcie);
+
 	if (pcie->gen)
 		brcm_pcie_set_gen(pcie, pcie->gen);
 
@@ -1073,14 +1130,6 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie)
 		 pci_speed_string(pcie_link_speed[cls]), nlw,
 		 ssc_good ? "(SSC)" : "(!SSC)");
 
-	/*
-	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
-	 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
-	 */
-	tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
-	tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
-	writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
-
 	return 0;
 }
 
-- 
2.17.1

[PATCH v5 3/5] PCI: brcmstb: Set higher value for internal bus timeout

[Jim Quinlan]

During long periods of the PCIe RC HW being in an L1SS sleep state, there
may be a timeout on an internal bus access, even though there may not be
any PCIe access involved.  Such a timeout will cause a subsequent CPU
abort.

So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
four seconds instead of using its HW default.

Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index d30636a725d7..fe0415a98c63 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 	return 0;
 }
 
+/*
+ * This extends the timeout period for an access to an internal bus.  This
+ * access timeout may occur during L1SS sleep periods even without the
+ * presence of a PCIe access.
+ */
+static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
+{
+	/* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
+	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
+	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
+
+	/* Each unit in timeout register is 1/216,000,000 seconds */
+	writel(216 * timeout_us, pcie->base + REG_OFFSET);
+}
+
 static void brcm_config_clkreq(struct brcm_pcie *pcie)
 {
 	bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
@@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
 		 * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
 		 * Mini CEM 2.0 specification.
 		 */
+		brcm_extend_rbus_timeout(pcie);
 		clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
 		dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
 	} else {
-- 
2.17.1

[PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Jim Quinlan]

The current PCIe driver assumes PERST# is asserted when probe() is invoked.
The reasons are as follows:

(1) One Broadcom SOC (7278) causes a panic if the PERST# register is
    written during this time window.

(2) If PERST# is deasserted at Linux probe() time, experience and QA
    suspend/resume tests have shown that some endpoint devices fail if the
    PERST# is pulsed (deasserted => asserted => deasserted) quickly in this
    fashion, even though the timing is in accordance with their datasheets.

(3) Keeping things in reset tends to save power, if for some reason the
    PCIe driver is not yet present.

Broadcom STB and CM SOCs bootloaders always have PERST# asserted at
probe().  This is not necessarily the case for the 2711/RPi bootloader,
so, for 2711/RPi SOCs, do what Raspian OS does and assert PERST#.

[1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index fe0415a98c63..7b698a9a851e 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -884,6 +884,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 
 	/* Reset the bridge */
 	pcie->bridge_sw_init_set(pcie, 1);
+
+	/* Ensure that PERST# is asserted; some bootloaders may deassert it. */
+	if (pcie->type == BCM2711)
+		pcie->perst_set(pcie, 1);
+
 	usleep_range(100, 200);
 
 	/* Take the bridge out of reset */
-- 
2.17.1

[PATCH v5 5/5] PCI: brcmstb: Remove stale comment

[Jim Quinlan]

A comment says that Multi-MSI is not supported by the driver.
A past commit [1] added this feature, so the comment is
incorrect and is removed.

[1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI")

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 7b698a9a851e..acd478edbe2f 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -449,7 +449,6 @@ static struct irq_chip brcm_msi_irq_chip = {
 };
 
 static struct msi_domain_info brcm_msi_domain_info = {
-	/* Multi MSI is supported by the controller, but not by this driver */
 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 		   MSI_FLAG_MULTI_PCI_MSI),
 	.chip	= &brcm_msi_irq_chip,
-- 
2.17.1

Re: [PATCH v5 5/5] PCI: brcmstb: Remove stale comment

[Florian Fainelli]

On 5/8/23 15:01, Jim Quinlan wrote:
> A comment says that Multi-MSI is not supported by the driver.
> A past commit [1] added this feature, so the comment is
> incorrect and is removed.
> 
> [1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI")
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Cyril Brulebois]

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Hi Jim,

Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> v5 -- Remove DT property "brcm,completion-timeout-us" from	 
>       "DT bindings" commit.  Although this error may be reported	 
>       as a completion timeout, its cause was traced to an	 
>       internal bus timeout which may occur even when there is	 
>       no PCIe access being processed.  We set a timeout of four	 
>       seconds only if we are operating in "L1SS CLKREQ#" mode.
>    -- Correct CEM 2.0 reference provided by HW engineer,
>       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
>    -- Add newline to dev_info() string (Stefan)
>    -- Change variable rval to unsigned (Stefan)
>    -- s/implementaion/implementation/ (Bjorn)
>    -- s/superpowersave/powersupersave/ (Bjorn)
>    -- Slightly modify message on "PERST#" commit.
>    -- Rebase to torvalds master

Same results as with v4: looks good to me!

Using an official CM4 IO Board, I've successfully tested the same 9
setups as before, combining each:
 - CM4 Lite Rev 1.0
 - CM4 8/32 Rev 1.0
 - CM4 4/32 Rev 1.1

with each off-the-shelf PCIe/USB adapter at my disposal:
 - SupaHub PCE6U1C-R02, VER 006
 - SupaHub PCE6U1C-R02, VER 006S
 - Waveshare based on VIA VL805/806

Each system boots successfully, exposes the Kingston memory stick
plugged onto the PCIe/USB adapter, and happily reads data from it.

Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).


Tested-By: Cyril Brulebois <cyril@debamax.com>


Cheers,
-- 
Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
D-I release manager -- Release team member -- Freelance Consultant

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Re: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Cyril Brulebois]

[-- Attachment #1: Type: text/plain, Size: 1338 bytes --]

Hi,

Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> The current PCIe driver assumes PERST# is asserted when probe() is invoked.
> The reasons are as follows:
> 
> (1) One Broadcom SOC (7278) causes a panic if the PERST# register is
>     written during this time window.
> 
> (2) If PERST# is deasserted at Linux probe() time, experience and QA
>     suspend/resume tests have shown that some endpoint devices fail if the
>     PERST# is pulsed (deasserted => asserted => deasserted) quickly in this
>     fashion, even though the timing is in accordance with their datasheets.
> 
> (3) Keeping things in reset tends to save power, if for some reason the
>     PCIe driver is not yet present.
> 
> Broadcom STB and CM SOCs bootloaders always have PERST# asserted at
> probe().  This is not necessarily the case for the 2711/RPi bootloader,
> so, for 2711/RPi SOCs, do what Raspian OS does and assert PERST#.
> 
> [1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987

It would probably make sense to remove that [1] link entirely, to match
the reference removal between v4 and v5.


Cheers,
-- 
Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
D-I release manager -- Release team member -- Freelance Consultant

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Re: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 1473 bytes --]

On Tue, May 9, 2023 at 3:51 AM Cyril Brulebois <kibi@debian.org> wrote:
>
> Hi,
>
> Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> > The current PCIe driver assumes PERST# is asserted when probe() is invoked.
> > The reasons are as follows:
> >
> > (1) One Broadcom SOC (7278) causes a panic if the PERST# register is
> >     written during this time window.
> >
> > (2) If PERST# is deasserted at Linux probe() time, experience and QA
> >     suspend/resume tests have shown that some endpoint devices fail if the
> >     PERST# is pulsed (deasserted => asserted => deasserted) quickly in this
> >     fashion, even though the timing is in accordance with their datasheets.
> >
> > (3) Keeping things in reset tends to save power, if for some reason the
> >     PCIe driver is not yet present.
> >
> > Broadcom STB and CM SOCs bootloaders always have PERST# asserted at
> > probe().  This is not necessarily the case for the 2711/RPi bootloader,
> > so, for 2711/RPi SOCs, do what Raspian OS does and assert PERST#.
> >
> > [1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987
>
> It would probably make sense to remove that [1] link entirely, to match
> the reference removal between v4 and v5.
Yep
>
>
> Cheers,
> --
> Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
> D-I release manager -- Release team member -- Freelance Consultant

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Re: [PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

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On Tue, May 9, 2023 at 3:47 AM Cyril Brulebois <kibi@debian.org> wrote:
>
> Hi Jim,
>
> Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> > v5 -- Remove DT property "brcm,completion-timeout-us" from
> >       "DT bindings" commit.  Although this error may be reported
> >       as a completion timeout, its cause was traced to an
> >       internal bus timeout which may occur even when there is
> >       no PCIe access being processed.  We set a timeout of four
> >       seconds only if we are operating in "L1SS CLKREQ#" mode.
> >    -- Correct CEM 2.0 reference provided by HW engineer,
> >       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> >    -- Add newline to dev_info() string (Stefan)
> >    -- Change variable rval to unsigned (Stefan)
> >    -- s/implementaion/implementation/ (Bjorn)
> >    -- s/superpowersave/powersupersave/ (Bjorn)
> >    -- Slightly modify message on "PERST#" commit.
> >    -- Rebase to torvalds master
>
> Same results as with v4: looks good to me!
>
> Using an official CM4 IO Board, I've successfully tested the same 9
> setups as before, combining each:
>  - CM4 Lite Rev 1.0
>  - CM4 8/32 Rev 1.0
>  - CM4 4/32 Rev 1.1
>
> with each off-the-shelf PCIe/USB adapter at my disposal:
>  - SupaHub PCE6U1C-R02, VER 006
>  - SupaHub PCE6U1C-R02, VER 006S
>  - Waveshare based on VIA VL805/806
>
> Each system boots successfully, exposes the Kingston memory stick
> plugged onto the PCIe/USB adapter, and happily reads data from it.
>
> Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
> and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).
>
>
> Tested-By: Cyril Brulebois <cyril@debamax.com>

Thanks a lot for doing this Cyril!
>
>
> Cheers,
> --
> Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
> D-I release manager -- Release team member -- Freelance Consultant

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Re: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Bjorn Helgaas]

Re subject, what does the patch actually *do*?

It looks like it "asserts PERST# on BCM2711", which I think would be
more informative than "don't assume 2711 bootloader leaves PERST#
asserted".

On Mon, May 08, 2023 at 06:01:24PM -0400, Jim Quinlan wrote:
> The current PCIe driver assumes PERST# is asserted when probe() is invoked.
> The reasons are as follows:
> 
> (1) One Broadcom SOC (7278) causes a panic if the PERST# register is
>     written during this time window.
> 
> (2) If PERST# is deasserted at Linux probe() time, experience and QA
>     suspend/resume tests have shown that some endpoint devices fail if the
>     PERST# is pulsed (deasserted => asserted => deasserted) quickly in this
>     fashion, even though the timing is in accordance with their datasheets.
> 
> (3) Keeping things in reset tends to save power, if for some reason the
>     PCIe driver is not yet present.
> 
> Broadcom STB and CM SOCs bootloaders always have PERST# asserted at
> probe().  This is not necessarily the case for the 2711/RPi bootloader,
> so, for 2711/RPi SOCs, do what Raspian OS does and assert PERST#.
> 
> [1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987

Does this link go with something above?  "[1]" isn't mentioned above.
I did look at that message, but the connection to this patch isn't
obvious to me.

> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index fe0415a98c63..7b698a9a851e 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -884,6 +884,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
>  
>  	/* Reset the bridge */
>  	pcie->bridge_sw_init_set(pcie, 1);
> +
> +	/* Ensure that PERST# is asserted; some bootloaders may deassert it. */
> +	if (pcie->type == BCM2711)
> +		pcie->perst_set(pcie, 1);
> +
>  	usleep_range(100, 200);
>  
>  	/* Take the bridge out of reset */
> -- 
> 2.17.1
> 

Re: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Bjorn Helgaas]

On Wed, May 10, 2023 at 05:26:13PM -0500, Bjorn Helgaas wrote:
> ...

> > [1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987
> 
> Does this link go with something above?  "[1]" isn't mentioned above.
> I did look at that message, but the connection to this patch isn't
> obvious to me.

Sorry, I noticed after sending this that you and Cyril have already
taken care of this.

Re: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Jim Quinlan]

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On Wed, May 10, 2023 at 6:26 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> Re subject, what does the patch actually *do*?
>
> It looks like it "asserts PERST# on BCM2711", which I think would be
> more informative than "don't assume 2711 bootloader leaves PERST#
> asserted".

Do you have any other feedback on the other commits?  I can change the
subject message as you like  and the remove the stale footnote you and
Cyril noticed, and submit V6.

Thanks,
Jim Quinlan
Broadcom STB
>
> On Mon, May 08, 2023 at 06:01:24PM -0400, Jim Quinlan wrote:
> > The current PCIe driver assumes PERST# is asserted when probe() is invoked.
> > The reasons are as follows:
> >
> > (1) One Broadcom SOC (7278) causes a panic if the PERST# register is
> >     written during this time window.
> >
> > (2) If PERST# is deasserted at Linux probe() time, experience and QA
> >     suspend/resume tests have shown that some endpoint devices fail if the
> >     PERST# is pulsed (deasserted => asserted => deasserted) quickly in this
> >     fashion, even though the timing is in accordance with their datasheets.
> >
> > (3) Keeping things in reset tends to save power, if for some reason the
> >     PCIe driver is not yet present.
> >
> > Broadcom STB and CM SOCs bootloaders always have PERST# asserted at
> > probe().  This is not necessarily the case for the 2711/RPi bootloader,
> > so, for 2711/RPi SOCs, do what Raspian OS does and assert PERST#.
> >
> > [1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987
>
> Does this link go with something above?  "[1]" isn't mentioned above.
> I did look at that message, but the connection to this patch isn't
> obvious to me.
>
> > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > ---
> >  drivers/pci/controller/pcie-brcmstb.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > index fe0415a98c63..7b698a9a851e 100644
> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -884,6 +884,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> >
> >       /* Reset the bridge */
> >       pcie->bridge_sw_init_set(pcie, 1);
> > +
> > +     /* Ensure that PERST# is asserted; some bootloaders may deassert it. */
> > +     if (pcie->type == BCM2711)
> > +             pcie->perst_set(pcie, 1);
> > +
> >       usleep_range(100, 200);
> >
> >       /* Take the bridge out of reset */
> > --
> > 2.17.1
> >

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Re: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted

[Bjorn Helgaas]

On Wed, May 10, 2023 at 06:46:45PM -0400, Jim Quinlan wrote:
> On Wed, May 10, 2023 at 6:26 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> >
> > Re subject, what does the patch actually *do*?
> >
> > It looks like it "asserts PERST# on BCM2711", which I think would be
> > more informative than "don't assume 2711 bootloader leaves PERST#
> > asserted".
> 
> Do you have any other feedback on the other commits?  I can change the
> subject message as you like  and the remove the stale footnote you and
> Cyril noticed, and submit V6.

Nope, and there's really no hurry.  Trivial stuff like this can be easily
done when merging.  I think two postings per week is plenty.  Each new
posting takes work to look at, so it's a win to wait a bit and
accumulate non-trivial updates before reposting.

Bjorn

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> This commit adds the boolean "brcm,enable-l1ss" property:
> 
>   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
>   requires the driver probe() to deliberately place the HW one of three
>   CLKREQ# modes:
> 
>   (a) CLKREQ# driven by the RC unconditionally
>   (b) CLKREQ# driven by the EP for ASPM L0s, L1
>   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> 
>   The HW+driver can tell the difference between downstream devices that
>   need (a) and (b), but does not know when to configure (c).  All devices
>   should work fine when the driver chooses (a) or (b), but (c) may be
>   desired to realize the extra power savings that L1SS offers.  So we
>   introduce the boolean "brcm,enable-l1ss" property to inform the driver
>   that (c) is desired.  Setting this property only makes sense when the
>   downstream device is L1SS-capable and the OS is configured to activate
>   this mode (e.g. policy==powersupersave).
> 
>   This property is already present in the Raspian version of Linux, but the
>   upstream driver implementation that follows adds more details and
>   discerns between (a) and (b).
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 7e15aae7d69e..8b61c2179608 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -64,6 +64,15 @@ properties:
>  
>    aspm-no-l0s: true
>  
> +  brcm,enable-l1ss:
> +    description: Indicates that PCIe L1SS power savings
> +      are desired, the downstream device is L1SS-capable, and the
> +      OS has been configured to enable this mode.  For boards
> +      using a mini-card connector, this mode may not meet the
> +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> +      of the PCI Express Mini CEM 2.0 specification.

As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
the hardware capability and not system/OS behavior. If this flag specifies
whether the PCIe controller supports L1SS or not, then it is fine but apparantly
this specifies that all downstream devices are L1SS capable which you cannot
guarantee unless you poke into their LNKCAP during runtime.

You should handle this in the driver itself.

- Mani

> +    type: boolean
> +
>    brcm,scb-sizes:
>      description: u64 giving the 64bit PCIe memory
>        viewport size of a memory controller.  There may be up to
> -- 
> 2.17.1
> 

-- 
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Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > This commit adds the boolean "brcm,enable-l1ss" property:
> > >
> > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > >   requires the driver probe() to deliberately place the HW one of three
> > >   CLKREQ# modes:
> > >
> > >   (a) CLKREQ# driven by the RC unconditionally
> > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > >
> > >   The HW+driver can tell the difference between downstream devices that
> > >   need (a) and (b), but does not know when to configure (c).  All devices
> > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > >   desired to realize the extra power savings that L1SS offers.  So we
> > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > >   that (c) is desired.  Setting this property only makes sense when the
> > >   downstream device is L1SS-capable and the OS is configured to activate
> > >   this mode (e.g. policy==powersupersave).
> > >
> > >   This property is already present in the Raspian version of Linux, but the
> > >   upstream driver implementation that follows adds more details and
> > >   discerns between (a) and (b).
> > >
> > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > index 7e15aae7d69e..8b61c2179608 100644
> > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > @@ -64,6 +64,15 @@ properties:
> > >
> > >    aspm-no-l0s: true
> > >
> > > +  brcm,enable-l1ss:
> > > +    description: Indicates that PCIe L1SS power savings
> > > +      are desired, the downstream device is L1SS-capable, and the
> > > +      OS has been configured to enable this mode.  For boards
> > > +      using a mini-card connector, this mode may not meet the
> > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > +      of the PCI Express Mini CEM 2.0 specification.
> >
> > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > the hardware capability and not system/OS behavior.
> 
> The "brcm,enable-l1ss" does NOT configure the OS behavior.
> It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> configured for L1SS.
> It compensates for a problem in the PCIe core: the HW is not capable
> of dynamically
> switching between ASPM modes powersave and superpowersave.  I am actively
> advocating for our HW to change but that will take years.
> 

Okay, then I would say that the property name and commit message were a bit
misleading. 

I had briefly gone through the driver patch now. As per my understanding, you
have 2 modes in hw:

1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
the device (driving high) when the link is in L1.

2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.

Till now the driver only supported Clock PM through mode (1) but for supporting
L1SS you need to enable mode (2). And you are using this property to select mode
(2) when the L1SS supported devices are connected to the slot. Also, by
selecting this mode, you are loosing the benefit of mode (1) as both are not
compatible.

My suggestion would be to just drop mode (1) and use mode (2) in the driver as
most of the recent devices should support L1SS (ofc there are exemptions).

But moving that decision to DT still doesn't seem right to me as the hardware
supports both modes and you are (ab)using DT to choose one or the other.

- Mani

> If this flag specifies
> > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > this specifies that all downstream devices are L1SS capable which you cannot
> > guarantee unless you poke into their LNKCAP during runtime.
> Not true at all.  This setting affects only RC and whatever device is
> connected to its single downstream
> port.
> 
> >
> > You should handle this in the driver itself.
> 
> The driver has no way of knowing if the PCI subsystem is going from power_save
> to power_supersave or vice-versa -- there is no notification chain for this.  So
> what you say is not currently possible from the driver's perspective.
> 
> Perhaps you would be happy if we changed it to "l1ss-support" in the
> spirit of the
> existing "clkreq-support" PCI parameter?
> 
> Regards,
> Jim Quinlan
> Broadcom STB/CMi
> 
> >
> > - Mani
> >
> > > +    type: boolean
> > > +
> > >    brcm,scb-sizes:
> > >      description: u64 giving the 64bit PCIe memory
> > >        viewport size of a memory controller.  There may be up to
> > > --
> > > 2.17.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்

> Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
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> To: james.quinlan@broadcom.com
> Subject: Join me now in my Personal Room
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Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Lorenzo Pieralisi]

On Wed, Aug 23, 2023 at 11:46:50PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > >
> > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > >   requires the driver probe() to deliberately place the HW one of three
> > > >   CLKREQ# modes:
> > > >
> > > >   (a) CLKREQ# driven by the RC unconditionally
> > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > >
> > > >   The HW+driver can tell the difference between downstream devices that
> > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > >   that (c) is desired.  Setting this property only makes sense when the
> > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > >   this mode (e.g. policy==powersupersave).
> > > >
> > > >   This property is already present in the Raspian version of Linux, but the
> > > >   upstream driver implementation that follows adds more details and
> > > >   discerns between (a) and (b).
> > > >
> > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > @@ -64,6 +64,15 @@ properties:
> > > >
> > > >    aspm-no-l0s: true
> > > >
> > > > +  brcm,enable-l1ss:
> > > > +    description: Indicates that PCIe L1SS power savings
> > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > +      OS has been configured to enable this mode.  For boards
> > > > +      using a mini-card connector, this mode may not meet the
> > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > +      of the PCI Express Mini CEM 2.0 specification.
> > >
> > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > the hardware capability and not system/OS behavior.
> > 
> > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > configured for L1SS.
> > It compensates for a problem in the PCIe core: the HW is not capable
> > of dynamically
> > switching between ASPM modes powersave and superpowersave.  I am actively
> > advocating for our HW to change but that will take years.
> > 
> 
> Okay, then I would say that the property name and commit message were a bit
> misleading. 
> 
> I had briefly gone through the driver patch now. As per my understanding, you
> have 2 modes in hw:
> 
> 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> the device (driving high) when the link is in L1.
> 
> 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> 
> Till now the driver only supported Clock PM through mode (1) but for supporting
> L1SS you need to enable mode (2). And you are using this property to select mode
> (2) when the L1SS supported devices are connected to the slot. Also, by
> selecting this mode, you are loosing the benefit of mode (1) as both are not
> compatible.
> 
> My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> most of the recent devices should support L1SS (ofc there are exemptions).
> 
> But moving that decision to DT still doesn't seem right to me as the hardware
> supports both modes and you are (ab)using DT to choose one or the other.

Jim ? We need to queue this series as soon as possible, if we don't
reach consensus by this evening I will queue the last three patches
only.

Lorenzo

> - Mani
> 
> > If this flag specifies
> > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > this specifies that all downstream devices are L1SS capable which you cannot
> > > guarantee unless you poke into their LNKCAP during runtime.
> > Not true at all.  This setting affects only RC and whatever device is
> > connected to its single downstream
> > port.
> > 
> > >
> > > You should handle this in the driver itself.
> > 
> > The driver has no way of knowing if the PCI subsystem is going from power_save
> > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > what you say is not currently possible from the driver's perspective.
> > 
> > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > spirit of the
> > existing "clkreq-support" PCI parameter?
> > 
> > Regards,
> > Jim Quinlan
> > Broadcom STB/CMi
> > 
> > >
> > > - Mani
> > >
> > > > +    type: boolean
> > > > +
> > > >    brcm,scb-sizes:
> > > >      description: u64 giving the 64bit PCIe memory
> > > >        viewport size of a memory controller.  There may be up to
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
> 
> > Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> > From: Florian Fainelli <messenger@webex.com>
> > To: james.quinlan@broadcom.com
> > Subject: Join me now in my Personal Room
> > 
> > Hello,
> > 
> > Join me now in my Personal Room. 
> > 
> > JOIN WEBEX MEETING
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> > 
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> மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 8694 bytes --]

On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > >
> > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > >   requires the driver probe() to deliberately place the HW one of three
> > > >   CLKREQ# modes:
> > > >
> > > >   (a) CLKREQ# driven by the RC unconditionally
> > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > >
> > > >   The HW+driver can tell the difference between downstream devices that
> > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > >   that (c) is desired.  Setting this property only makes sense when the
> > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > >   this mode (e.g. policy==powersupersave).
> > > >
> > > >   This property is already present in the Raspian version of Linux, but the
> > > >   upstream driver implementation that follows adds more details and
> > > >   discerns between (a) and (b).
> > > >
> > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > @@ -64,6 +64,15 @@ properties:
> > > >
> > > >    aspm-no-l0s: true
> > > >
> > > > +  brcm,enable-l1ss:
> > > > +    description: Indicates that PCIe L1SS power savings
> > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > +      OS has been configured to enable this mode.  For boards
> > > > +      using a mini-card connector, this mode may not meet the
> > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > +      of the PCI Express Mini CEM 2.0 specification.
> > >
> > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > the hardware capability and not system/OS behavior.
> >
> > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > configured for L1SS.
> > It compensates for a problem in the PCIe core: the HW is not capable
> > of dynamically
> > switching between ASPM modes powersave and superpowersave.  I am actively
> > advocating for our HW to change but that will take years.
> >
>
> Okay, then I would say that the property name and commit message were a bit
> misleading.
>
> I had briefly gone through the driver patch now. As per my understanding, you
> have 2 modes in hw:
>
> 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> the device (driving high) when the link is in L1.
>
> 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.

No, there are three, as enumerated in the commit message of
"PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"

>
> Till now the driver only supported Clock PM through mode (1) but for supporting
> L1SS you need to enable mode (2). And you are using this property to select mode
> (2) when the L1SS supported devices are connected to the slot. Also, by
> selecting this mode, you are loosing the benefit of mode (1) as both are not
> compatible.
>
> My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> most of the recent devices should support L1SS (ofc there are exemptions).
The disadvantage of this, as stated by the PCIe core HW designer, was
that "doing so means
we cannot enable the Cock Power Management capability since it may run afoul of
the Tclron requirement."

I will attempt to press him on exactly what configurations and form
factors would be
vulnerable to this -- he was so convinced that it was a danger that he
is against
making L1SS mode the default.

>
> But moving that decision to DT still doesn't seem right to me as the hardware
> supports both modes and you are (ab)using DT to choose one or the other.

May be true, but there does not appear to be a Linux upstream-acceptable
way of doing this on the command line either; please see my recent post
on why this is so.

There will be cases where we want to override the default setting, either by
command line or DT, but you folks have to give me a viable path on
how to do this with it actually being accepted.

Regards,
Jim Quinlan
Broadcom STB/CM

>
> - Mani
>
> > If this flag specifies
> > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > this specifies that all downstream devices are L1SS capable which you cannot
> > > guarantee unless you poke into their LNKCAP during runtime.
> > Not true at all.  This setting affects only RC and whatever device is
> > connected to its single downstream
> > port.
> >
> > >
> > > You should handle this in the driver itself.
> >
> > The driver has no way of knowing if the PCI subsystem is going from power_save
> > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > what you say is not currently possible from the driver's perspective.
> >
> > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > spirit of the
> > existing "clkreq-support" PCI parameter?
> >
> > Regards,
> > Jim Quinlan
> > Broadcom STB/CMi
> >
> > >
> > > - Mani
> > >
> > > > +    type: boolean
> > > > +
> > > >    brcm,scb-sizes:
> > > >      description: u64 giving the 64bit PCIe memory
> > > >        viewport size of a memory controller.  There may be up to
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> > Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> > From: Florian Fainelli <messenger@webex.com>
> > To: james.quinlan@broadcom.com
> > Subject: Join me now in my Personal Room
> >
> > Hello,
> >
> > Join me now in my Personal Room.
> >
> > JOIN WEBEX MEETING
> > https://broadcom.webex.com/join/florian.fainelli  |  490 282 179
> >
> >
> > JOIN FROM A VIDEO CONFERENCING SYSTEM OR APPLICATION
> > Dial sip:florian.fainelli@broadcom.webex.com
> > You can also dial 173.243.2.68 and enter your meeting number.
> >
> >
> >
> > Can't join the meeting?
> > https://help.webex.com/docs/DOC-5412
> >
> > PHONE DIALING GUIDELINES:
> >         - Use Call Me when you are using office phone or Jabber.
> >         - Use Call Using Computer when you are at home or traveling.
> >
> > In Office Calls:
> >       - From Broadcom Office: 1-MEETING (1-6338464)
> >
> > Offsite Numbers Toll (Local) Calls:
> >       - Canada, Richmond: +1-778-308-4007
> >       - China: +86-400-819-1044
> >       - Germany, Munich: +49-892-312-9611
> >         - Germany, Regensburg: +49-(9)419-923-5940
> >         - India: 00-080-0050-1631
> >       - Israel: +97-239-786-477
> >         - Japan, Tokyo: +81-366-344-937
> >         - Malaysia: +603-2053-5189
> >       - Singapore: +65-6349-2439
> >       - South Korea, Seoul: +82-70-4732-0218
> >       - Taiwan, Taipei: +886-277-047-765
> >       - US, Denver: +1-720-726-9995
> >         - US, Los Angeles: +1-310-616-5312
> >         - US, Philadelphia: +1-215-305-7603
> >       - UK, London: +44-207-660-8897
> >         - UK, Manchester: +44-161-619-8089
> >
> > IMPORTANT NOTICE: Please note that this Webex service allows audio and other information sent during the session to be recorded, which may be discoverable in a legal matter. By joining this session, you automatically consent to such recordings. If you do not consent to being recorded, discuss your concerns with the host or do not join the session.
>
>
>
>
>
> --
> மணிவண்ணன் சதாசிவம்

[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4210 bytes --]

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > >
> > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > >   CLKREQ# modes:
> > > > >
> > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > >
> > > > >   The HW+driver can tell the difference between downstream devices that
> > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > >   this mode (e.g. policy==powersupersave).
> > > > >
> > > > >   This property is already present in the Raspian version of Linux, but the
> > > > >   upstream driver implementation that follows adds more details and
> > > > >   discerns between (a) and (b).
> > > > >
> > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > ---
> > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > >  1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > @@ -64,6 +64,15 @@ properties:
> > > > >
> > > > >    aspm-no-l0s: true
> > > > >
> > > > > +  brcm,enable-l1ss:
> > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > +      OS has been configured to enable this mode.  For boards
> > > > > +      using a mini-card connector, this mode may not meet the
> > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > >
> > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > the hardware capability and not system/OS behavior.
> > >
> > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > configured for L1SS.
> > > It compensates for a problem in the PCIe core: the HW is not capable
> > > of dynamically
> > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > advocating for our HW to change but that will take years.
> > >
> >
> > Okay, then I would say that the property name and commit message were a bit
> > misleading.
> >
> > I had briefly gone through the driver patch now. As per my understanding, you
> > have 2 modes in hw:
> >
> > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > the device (driving high) when the link is in L1.
> >
> > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> 
> No, there are three, as enumerated in the commit message of
> "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> 

Yeah, another one is refclk always on.

> >
> > Till now the driver only supported Clock PM through mode (1) but for supporting
> > L1SS you need to enable mode (2). And you are using this property to select mode
> > (2) when the L1SS supported devices are connected to the slot. Also, by
> > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > compatible.
> >
> > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > most of the recent devices should support L1SS (ofc there are exemptions).
> The disadvantage of this, as stated by the PCIe core HW designer, was
> that "doing so means
> we cannot enable the Cock Power Management capability since it may run afoul of
> the Tclron requirement."
> 

Ok.

> I will attempt to press him on exactly what configurations and form
> factors would be
> vulnerable to this -- he was so convinced that it was a danger that he
> is against
> making L1SS mode the default.
> 

Hmm. After looking at this problem in detail, it looks to me that you can still
use DT but not with the property you proposed. Since these are hardware modes,
you can have a single DT property that specifies the mode that the driver can
use to configure the hw. It is similar to "phy-mode" property we have for the
network controllers.

So you should have the property defined as below in binding:

brcm,clkreq-mode:
  $ref: /schemas/types.yaml#/definitions/uint32
  enum: [ 0, 1, 2 ]

Then create definition for each mode in "include/dt-bindings/pci/brcm,stb.h".

#define BRCM_STB_CLKREQ_CLOCK_PM	0
#define BRCM_STB_CLKREQ_L1SS		1
#define BRCM_STB_CLKREQ_ON		2

If the property is not specified, the driver should use "Clock PM" as the
default mode as it was doing earlier.

Also, I think you can get rid of other checks in the driver (like PCIEASPM
Kconfig, clkreq_seen etc...) and solely rely on this property to set the mode.

What do you think?

- Mani

> >
> > But moving that decision to DT still doesn't seem right to me as the hardware
> > supports both modes and you are (ab)using DT to choose one or the other.
> 
> May be true, but there does not appear to be a Linux upstream-acceptable
> way of doing this on the command line either; please see my recent post
> on why this is so.
> 
> There will be cases where we want to override the default setting, either by
> command line or DT, but you folks have to give me a viable path on
> how to do this with it actually being accepted.
> 
> Regards,
> Jim Quinlan
> Broadcom STB/CM
> 
> >
> > - Mani
> >
> > > If this flag specifies
> > > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > > this specifies that all downstream devices are L1SS capable which you cannot
> > > > guarantee unless you poke into their LNKCAP during runtime.
> > > Not true at all.  This setting affects only RC and whatever device is
> > > connected to its single downstream
> > > port.
> > >
> > > >
> > > > You should handle this in the driver itself.
> > >
> > > The driver has no way of knowing if the PCI subsystem is going from power_save
> > > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > > what you say is not currently possible from the driver's perspective.
> > >
> > > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > > spirit of the
> > > existing "clkreq-support" PCI parameter?
> > >
> > > Regards,
> > > Jim Quinlan
> > > Broadcom STB/CMi
> > >
> > > >
> > > > - Mani
> > > >
> > > > > +    type: boolean
> > > > > +
> > > > >    brcm,scb-sizes:
> > > > >      description: u64 giving the 64bit PCIe memory
> > > > >        viewport size of a memory controller.  There may be up to
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> >
> > > Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> > > From: Florian Fainelli <messenger@webex.com>
> > > To: james.quinlan@broadcom.com
> > > Subject: Join me now in my Personal Room
> > >
> > > Hello,
> > >
> > > Join me now in my Personal Room.
> > >
> > > JOIN WEBEX MEETING
> > > https://broadcom.webex.com/join/florian.fainelli  |  490 282 179
> > >
> > >
> > > JOIN FROM A VIDEO CONFERENCING SYSTEM OR APPLICATION
> > > Dial sip:florian.fainelli@broadcom.webex.com
> > > You can also dial 173.243.2.68 and enter your meeting number.
> > >
> > >
> > >
> > > Can't join the meeting?
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-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 8919 bytes --]

On Fri, Aug 25, 2023 at 2:45 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > >   CLKREQ# modes:
> > > > > >
> > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > >   this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > >   upstream driver implementation that follows adds more details and
> > > > > >   discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > >  1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > >    aspm-no-l0s: true
> > > > > >
> > > > > > +  brcm,enable-l1ss:
> > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > +      using a mini-card connector, this mode may not meet the
> > > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > >
> > > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > > the hardware capability and not system/OS behavior.
> > > >
> > > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > > configured for L1SS.
> > > > It compensates for a problem in the PCIe core: the HW is not capable
> > > > of dynamically
> > > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > > advocating for our HW to change but that will take years.
> > > >
> > >
> > > Okay, then I would say that the property name and commit message were a bit
> > > misleading.
> > >
> > > I had briefly gone through the driver patch now. As per my understanding, you
> > > have 2 modes in hw:
> > >
> > > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > > the device (driving high) when the link is in L1.
> > >
> > > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> >
> > No, there are three, as enumerated in the commit message of
> > "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> >
>
> Yeah, another one is refclk always on.
>
> > >
> > > Till now the driver only supported Clock PM through mode (1) but for supporting
> > > L1SS you need to enable mode (2). And you are using this property to select mode
> > > (2) when the L1SS supported devices are connected to the slot. Also, by
> > > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > > compatible.
> > >
> > > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > > most of the recent devices should support L1SS (ofc there are exemptions).
> > The disadvantage of this, as stated by the PCIe core HW designer, was
> > that "doing so means
> > we cannot enable the Cock Power Management capability since it may run afoul of
> > the Tclron requirement."
> >
>
> Ok.
>
> > I will attempt to press him on exactly what configurations and form
> > factors would be
> > vulnerable to this -- he was so convinced that it was a danger that he
> > is against
> > making L1SS mode the default.
> >
>
> Hmm. After looking at this problem in detail, it looks to me that you can still
> use DT but not with the property you proposed. Since these are hardware modes,
> you can have a single DT property that specifies the mode that the driver can
> use to configure the hw. It is similar to "phy-mode" property we have for the
> network controllers.
>
> So you should have the property defined as below in binding:
>
> brcm,clkreq-mode:
>   $ref: /schemas/types.yaml#/definitions/uint32
>   enum: [ 0, 1, 2 ]
>
> Then create definition for each mode in "include/dt-bindings/pci/brcm,stb.h".
>
> #define BRCM_STB_CLKREQ_CLOCK_PM        0
> #define BRCM_STB_CLKREQ_L1SS            1
> #define BRCM_STB_CLKREQ_ON              2
>
> If the property is not specified, the driver should use "Clock PM" as the
> default mode as it was doing earlier.
>
> Also, I think you can get rid of other checks in the driver (like PCIEASPM
> Kconfig, clkreq_seen etc...) and solely rely on this property to set the mode.
>
> What do you think?

Hi Mani,

I'm all for it; in fact this is quite similar to  my original design.
But then I decided to be backwards
compatible with RaspianOS's "brcm,enable-l1ss".

I will go in this direction for V7 and the only remaining issue is
what the default mode should
be and I will try my best to get time with the HW designer to weigh
the pros and cons.

Regards,
Jim Quinlan
Broadcom STB/CM

>
>
> - Mani
>
> > >
> > > But moving that decision to DT still doesn't seem right to me as the hardware
> > > supports both modes and you are (ab)using DT to choose one or the other.
> >
> > May be true, but there does not appear to be a Linux upstream-acceptable
> > way of doing this on the command line either; please see my recent post
> > on why this is so.
> >
> > There will be cases where we want to override the default setting, either by
> > command line or DT, but you folks have to give me a viable path on
> > how to do this with it actually being accepted.
> >
> > Regards,
> > Jim Quinlan
> > Broadcom STB/CM
> >
> > >
> > > - Mani
> > >
> > > > If this flag specifies
> > > > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > > > this specifies that all downstream devices are L1SS capable which you cannot
> > > > > guarantee unless you poke into their LNKCAP during runtime.
> > > > Not true at all.  This setting affects only RC and whatever device is
> > > > connected to its single downstream
> > > > port.
> > > >
> > > > >
> > > > > You should handle this in the driver itself.
> > > >
> > > > The driver has no way of knowing if the PCI subsystem is going from power_save
> > > > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > > > what you say is not currently possible from the driver's perspective.
> > > >
> > > > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > > > spirit of the
> > > > existing "clkreq-support" PCI parameter?
> > > >
> > > > Regards,
> > > > Jim Quinlan
> > > > Broadcom STB/CMi
> > > >
> > > > >
> > > > > - Mani
> > > > >
> > > > > > +    type: boolean
> > > > > > +
> > > > > >    brcm,scb-sizes:
> > > > > >      description: u64 giving the 64bit PCIe memory
> > > > > >        viewport size of a memory controller.  There may be up to
> > > > > > --
> > > > > > 2.17.1
> > > > > >
> > > > >
> > > > > --
> > > > > மணிவண்ணன் சதாசிவம்
> > >
>

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Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Rob Herring]

On Fri, Aug 25, 2023 at 1:45 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > >   CLKREQ# modes:
> > > > > >
> > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > >   this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > >   upstream driver implementation that follows adds more details and
> > > > > >   discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > >  1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > >    aspm-no-l0s: true
> > > > > >
> > > > > > +  brcm,enable-l1ss:
> > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > +      using a mini-card connector, this mode may not meet the
> > > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > >
> > > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > > the hardware capability and not system/OS behavior.
> > > >
> > > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > > configured for L1SS.
> > > > It compensates for a problem in the PCIe core: the HW is not capable
> > > > of dynamically
> > > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > > advocating for our HW to change but that will take years.
> > > >
> > >
> > > Okay, then I would say that the property name and commit message were a bit
> > > misleading.
> > >
> > > I had briefly gone through the driver patch now. As per my understanding, you
> > > have 2 modes in hw:
> > >
> > > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > > the device (driving high) when the link is in L1.
> > >
> > > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> >
> > No, there are three, as enumerated in the commit message of
> > "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> >
>
> Yeah, another one is refclk always on.
>
> > >
> > > Till now the driver only supported Clock PM through mode (1) but for supporting
> > > L1SS you need to enable mode (2). And you are using this property to select mode
> > > (2) when the L1SS supported devices are connected to the slot. Also, by
> > > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > > compatible.
> > >
> > > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > > most of the recent devices should support L1SS (ofc there are exemptions).
> > The disadvantage of this, as stated by the PCIe core HW designer, was
> > that "doing so means
> > we cannot enable the Cock Power Management capability since it may run afoul of
> > the Tclron requirement."
> >
>
> Ok.
>
> > I will attempt to press him on exactly what configurations and form
> > factors would be
> > vulnerable to this -- he was so convinced that it was a danger that he
> > is against
> > making L1SS mode the default.
> >
>
> Hmm. After looking at this problem in detail, it looks to me that you can still
> use DT but not with the property you proposed. Since these are hardware modes,
> you can have a single DT property that specifies the mode that the driver can
> use to configure the hw. It is similar to "phy-mode" property we have for the
> network controllers.
>
> So you should have the property defined as below in binding:
>
> brcm,clkreq-mode:
>   $ref: /schemas/types.yaml#/definitions/uint32
>   enum: [ 0, 1, 2 ]

Is this really Broadcom specific?

Rob

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Tue, Aug 29, 2023 at 07:22:18AM -0500, Rob Herring wrote:
> On Fri, Aug 25, 2023 at 1:45 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> > > On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > >
> > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > >   CLKREQ# modes:
> > > > > > >
> > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > >
> > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > >
> > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > >   discerns between (a) and (b).
> > > > > > >
> > > > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > >  1 file changed, 9 insertions(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > >
> > > > > > >    aspm-no-l0s: true
> > > > > > >
> > > > > > > +  brcm,enable-l1ss:
> > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > > +      using a mini-card connector, this mode may not meet the
> > > > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > > >
> > > > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > > > the hardware capability and not system/OS behavior.
> > > > >
> > > > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > > > configured for L1SS.
> > > > > It compensates for a problem in the PCIe core: the HW is not capable
> > > > > of dynamically
> > > > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > > > advocating for our HW to change but that will take years.
> > > > >
> > > >
> > > > Okay, then I would say that the property name and commit message were a bit
> > > > misleading.
> > > >
> > > > I had briefly gone through the driver patch now. As per my understanding, you
> > > > have 2 modes in hw:
> > > >
> > > > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > > > the device (driving high) when the link is in L1.
> > > >
> > > > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> > >
> > > No, there are three, as enumerated in the commit message of
> > > "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> > >
> >
> > Yeah, another one is refclk always on.
> >
> > > >
> > > > Till now the driver only supported Clock PM through mode (1) but for supporting
> > > > L1SS you need to enable mode (2). And you are using this property to select mode
> > > > (2) when the L1SS supported devices are connected to the slot. Also, by
> > > > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > > > compatible.
> > > >
> > > > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > > > most of the recent devices should support L1SS (ofc there are exemptions).
> > > The disadvantage of this, as stated by the PCIe core HW designer, was
> > > that "doing so means
> > > we cannot enable the Cock Power Management capability since it may run afoul of
> > > the Tclron requirement."
> > >
> >
> > Ok.
> >
> > > I will attempt to press him on exactly what configurations and form
> > > factors would be
> > > vulnerable to this -- he was so convinced that it was a danger that he
> > > is against
> > > making L1SS mode the default.
> > >
> >
> > Hmm. After looking at this problem in detail, it looks to me that you can still
> > use DT but not with the property you proposed. Since these are hardware modes,
> > you can have a single DT property that specifies the mode that the driver can
> > use to configure the hw. It is similar to "phy-mode" property we have for the
> > network controllers.
> >
> > So you should have the property defined as below in binding:
> >
> > brcm,clkreq-mode:
> >   $ref: /schemas/types.yaml#/definitions/uint32
> >   enum: [ 0, 1, 2 ]
> 
> Is this really Broadcom specific?
> 

AFAIU, rest of the controllers do not have issues supporting Clock PM and L1SS
in hw. Neither does the spec define any incompatibility. So to me, this looks
like Broadcom specific.

- Mani

> Rob

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