* [PATCH v3] meson saradc: fix clock divider mask length
@ 2023-06-06 16:53 George Stark
2023-06-06 19:14 ` Martin Blumenstingl
2023-06-06 22:52 ` andy.shevchenko
0 siblings, 2 replies; 4+ messages in thread
From: George Stark @ 2023-06-06 16:53 UTC (permalink / raw)
To: jic23, lars, neil.armstrong, khilman, jbrunet,
martin.blumenstingl, andriy.shevchenko, nuno.sa, gnstark
Cc: linux-iio, linux-arm-kernel, linux-kernel, linux-amlogic, kernel,
George Stark
According to datasheets of supported meson SOCs length of ADC_CLK_DIV
field is 6 bits long. Although all supported SOCs have the register
with that field documented later SOCs use external clock rather than
ADC internal clock so this patch affects only meson8 family (S8* SOCs)
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: George Stark <GNStark@sberdevices.ru>
---
Changelog:
v1 -> v2:
* Update commit message
v2 -> v3:
* Update commit message
---
drivers/iio/adc/meson_saradc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 85b6826cc10c..b93ff42b8c19 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -72,7 +72,7 @@
#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
- #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
--
2.38.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3] meson saradc: fix clock divider mask length
2023-06-06 16:53 [PATCH v3] meson saradc: fix clock divider mask length George Stark
@ 2023-06-06 19:14 ` Martin Blumenstingl
2023-06-06 22:52 ` andy.shevchenko
1 sibling, 0 replies; 4+ messages in thread
From: Martin Blumenstingl @ 2023-06-06 19:14 UTC (permalink / raw)
To: George Stark
Cc: jic23, lars, neil.armstrong, khilman, jbrunet, andriy.shevchenko,
nuno.sa, linux-iio, linux-arm-kernel, linux-kernel,
linux-amlogic, kernel
Thank you George!
On Tue, Jun 6, 2023 at 6:54 PM George Stark <gnstark@sberdevices.ru> wrote:
>
> According to datasheets of supported meson SOCs length of ADC_CLK_DIV
> field is 6 bits long. Although all supported SOCs have the register
> with that field documented later SOCs use external clock rather than
> ADC internal clock so this patch affects only meson8 family (S8* SOCs)
>
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> Signed-off-by: George Stark <GNStark@sberdevices.ru>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] meson saradc: fix clock divider mask length
2023-06-06 16:53 [PATCH v3] meson saradc: fix clock divider mask length George Stark
2023-06-06 19:14 ` Martin Blumenstingl
@ 2023-06-06 22:52 ` andy.shevchenko
2023-06-10 17:59 ` Jonathan Cameron
1 sibling, 1 reply; 4+ messages in thread
From: andy.shevchenko @ 2023-06-06 22:52 UTC (permalink / raw)
To: George Stark
Cc: jic23, lars, neil.armstrong, khilman, jbrunet,
martin.blumenstingl, andriy.shevchenko, nuno.sa, linux-iio,
linux-arm-kernel, linux-kernel, linux-amlogic, kernel
Tue, Jun 06, 2023 at 07:53:57PM +0300, George Stark kirjoitti:
> According to datasheets of supported meson SOCs length of ADC_CLK_DIV
the datasheets
> field is 6 bits long. Although all supported SOCs have the register
6-bit
> with that field documented later SOCs use external clock rather than
> ADC internal clock so this patch affects only meson8 family (S8* SOCs)
s/SOC/SoC/g, and mind the grammar period at the end.
I believe Jonathan can fix when applying this, no need to resend unless
he asks for it.
FWIW,
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> Signed-off-by: George Stark <GNStark@sberdevices.ru>
> ---
> Changelog:
>
> v1 -> v2:
> * Update commit message
> v2 -> v3:
> * Update commit message
> ---
> drivers/iio/adc/meson_saradc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> index 85b6826cc10c..b93ff42b8c19 100644
> --- a/drivers/iio/adc/meson_saradc.c
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -72,7 +72,7 @@
> #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
> #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>
> --
> 2.38.4
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] meson saradc: fix clock divider mask length
2023-06-06 22:52 ` andy.shevchenko
@ 2023-06-10 17:59 ` Jonathan Cameron
0 siblings, 0 replies; 4+ messages in thread
From: Jonathan Cameron @ 2023-06-10 17:59 UTC (permalink / raw)
To: andy.shevchenko
Cc: George Stark, lars, neil.armstrong, khilman, jbrunet,
martin.blumenstingl, andriy.shevchenko, nuno.sa, linux-iio,
linux-arm-kernel, linux-kernel, linux-amlogic, kernel
On Wed, 7 Jun 2023 01:52:26 +0300
andy.shevchenko@gmail.com wrote:
> Tue, Jun 06, 2023 at 07:53:57PM +0300, George Stark kirjoitti:
> > According to datasheets of supported meson SOCs length of ADC_CLK_DIV
>
> the datasheets
>
> > field is 6 bits long. Although all supported SOCs have the register
>
> 6-bit
>
> > with that field documented later SOCs use external clock rather than
> > ADC internal clock so this patch affects only meson8 family (S8* SOCs)
>
> s/SOC/SoC/g, and mind the grammar period at the end.
>
> I believe Jonathan can fix when applying this, no need to resend unless
> he asks for it.
>
Indeed - done and applied to the fixes-togreg branch of iio.git + marked it
for stable inclusion.
Thanks,
Jonathan
> FWIW,
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
>
> > Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> > Signed-off-by: George Stark <GNStark@sberdevices.ru>
> > ---
> > Changelog:
> >
> > v1 -> v2:
> > * Update commit message
> > v2 -> v3:
> > * Update commit message
> > ---
> > drivers/iio/adc/meson_saradc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> > index 85b6826cc10c..b93ff42b8c19 100644
> > --- a/drivers/iio/adc/meson_saradc.c
> > +++ b/drivers/iio/adc/meson_saradc.c
> > @@ -72,7 +72,7 @@
> > #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> > #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> > #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> > - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> > + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
> > #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> > #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> >
> > --
> > 2.38.4
> >
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-06-06 16:53 [PATCH v3] meson saradc: fix clock divider mask length George Stark
2023-06-06 19:14 ` Martin Blumenstingl
2023-06-06 22:52 ` andy.shevchenko
2023-06-10 17:59 ` Jonathan Cameron
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