From: Johan Hovold <johan@kernel.org>
To: Krishna Kurapati <quic_kriskura@quicinc.com>
Cc: Thinh Nguyen <Thinh.Nguyen@synopsys.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Felipe Balbi <balbi@kernel.org>,
Wesley Cheng <quic_wcheng@quicinc.com>,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
quic_pkondeti@quicinc.com, quic_ppratap@quicinc.com,
quic_jackp@quicinc.com, quic_harshq@quicinc.com,
ahalaney@redhat.com, quic_shazhuss@quicinc.com
Subject: Re: [PATCH v9 03/10] usb: dwc3: core: Access XHCI address space temporarily to read port info
Date: Tue, 27 Jun 2023 13:45:41 +0200 [thread overview]
Message-ID: <ZJrL5SXrSiYbvq2o@hovoldconsulting.com> (raw)
In-Reply-To: <20230621043628.21485-4-quic_kriskura@quicinc.com>
On Wed, Jun 21, 2023 at 10:06:21AM +0530, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
>
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
>
> Wherever we need to perform phy operations like:
>
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
>
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
>
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> drivers/usb/dwc3/core.c | 62 +++++++++++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 9 ++++++
> 2 files changed, 71 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index f6689b731718..32ec05fc242b 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -39,6 +39,7 @@
> #include "io.h"
>
> #include "debug.h"
> +#include "../host/xhci-ext-caps.h"
>
> #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
>
> @@ -1767,6 +1768,52 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> return 0;
> }
>
> +static int dwc3_read_port_info(struct dwc3 *dwc)
> +{
> + void __iomem *base;
> + u8 major_revision;
> + u32 offset = 0;
> + int ret = 0;
ret is never modified, so drop and return 0 unconditionally below.
You can add it back later in the series when you start using it.
> + u32 val;
> +
> + /*
> + * Remap xHCI address space to access XHCI ext cap regs,
> + * since it is needed to get port info.
> + */
> + base = ioremap(dwc->xhci_resources[0].start,
> + resource_size(&dwc->xhci_resources[0]));
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + do {
> + offset = xhci_find_next_ext_cap(base, offset,
> + XHCI_EXT_CAPS_PROTOCOL);
> +
You can drop this newline.
> + if (!offset)
> + break;
> +
> + val = readl(base + offset);
> + major_revision = XHCI_EXT_PORT_MAJOR(val);
> +
> + val = readl(base + offset + 0x08);
> + if (major_revision == 0x03) {
> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
> + } else if (major_revision <= 0x02) {
> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
> + } else {
> + dev_err(dwc->dev,
> + "Unrecognized port major revision %d\n",
> + major_revision);
> + }
> + } while (1);
> +
> + dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
> + dwc->num_usb2_ports, dwc->num_usb3_ports);
> +
> + iounmap(base);
Nit: I'd add a newline here.
> + return ret;
> +}
> +
> static int dwc3_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -1774,6 +1821,7 @@ static int dwc3_probe(struct platform_device *pdev)
> void __iomem *regs;
> struct dwc3 *dwc;
> int ret;
> + unsigned int hw_mode;
>
> dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
> if (!dwc)
> @@ -1854,6 +1902,20 @@ static int dwc3_probe(struct platform_device *pdev)
> goto err_disable_clks;
> }
>
> + /*
> + * Currently only DWC3 controllers that are host-only capable
> + * support Multiport.
> + */
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> + ret = dwc3_read_port_info(dwc);
> + if (ret)
> + goto err_disable_clks;
> + } else {
> + dwc->num_usb2_ports = 1;
> + dwc->num_usb3_ports = 1;
> + }
> +
> spin_lock_init(&dwc->lock);
> mutex_init(&dwc->mutex);
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 8b1295e4dcdd..42fb17aa66fa 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -33,6 +33,10 @@
>
> #include <linux/power_supply.h>
>
> +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
> +#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
> +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
Again, don't copy defines from xhci.
Looks like these should be moved to the xhci-ext-caps.h header along
with struct xhci_protocol_caps.
> +
> #define DWC3_MSG_MAX 500
>
> /* Global constants */
> @@ -1029,6 +1033,8 @@ struct dwc3_scratchpad_array {
> * @usb3_phy: pointer to USB3 PHY
> * @usb2_generic_phy: pointer to USB2 PHY
> * @usb3_generic_phy: pointer to USB3 PHY
> + * @num_usb2_ports: number of USB2 ports.
> + * @num_usb3_ports: number of USB3 ports.
Again, please drop the full stops ('.').
Johan
next prev parent reply other threads:[~2023-06-27 11:45 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 4:36 [PATCH v9 00/10] Add multiport support for DWC3 controllers Krishna Kurapati
2023-06-21 4:36 ` [PATCH v9 01/10] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport Krishna Kurapati
2023-06-23 20:41 ` Rob Herring
2023-06-27 11:20 ` Johan Hovold
2023-06-27 15:38 ` Johan Hovold
2023-07-02 19:11 ` Krishna Kurapati PSSNV
2023-07-21 8:10 ` Johan Hovold
2023-06-21 4:36 ` [PATCH v9 02/10] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Krishna Kurapati
2023-06-23 20:41 ` Rob Herring
2023-06-27 11:24 ` Johan Hovold
2023-06-21 4:36 ` [PATCH v9 03/10] usb: dwc3: core: Access XHCI address space temporarily to read port info Krishna Kurapati
2023-06-23 22:14 ` Thinh Nguyen
2023-06-27 11:45 ` Johan Hovold [this message]
2023-07-02 18:48 ` Krishna Kurapati PSSNV
2023-07-21 7:44 ` Johan Hovold
2023-07-23 14:59 ` Krishna Kurapati PSSNV
2023-07-24 15:41 ` Johan Hovold
2023-07-25 5:39 ` Krishna Kurapati PSSNV
2023-06-21 4:36 ` [PATCH v9 04/10] usb: dwc3: core: Skip setting event buffers for host only controllers Krishna Kurapati
2023-06-23 22:27 ` Thinh Nguyen
2023-06-24 7:20 ` Krishna Kurapati PSSNV
2023-06-26 23:34 ` Thinh Nguyen
2023-06-26 23:46 ` Thinh Nguyen
2023-07-02 18:45 ` Krishna Kurapati PSSNV
2023-07-05 22:40 ` Thinh Nguyen
2023-06-21 4:36 ` [PATCH v9 05/10] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati
2023-06-23 22:55 ` Thinh Nguyen
2023-06-24 7:15 ` Krishna Kurapati PSSNV
2023-06-27 12:09 ` Johan Hovold
2023-07-02 18:56 ` Krishna Kurapati PSSNV
2023-07-21 7:56 ` Johan Hovold
2023-08-01 1:30 ` Thinh Nguyen
2023-10-19 13:20 ` Johan Hovold
2023-06-21 4:36 ` [PATCH v9 06/10] usb: dwc3: qcom: Add support to read IRQ's related to multiport Krishna Kurapati
2023-06-21 10:05 ` Konrad Dybcio
2023-06-21 10:08 ` Krishna Kurapati PSSNV
2023-06-27 14:31 ` Johan Hovold
2023-07-02 18:59 ` Krishna Kurapati PSSNV
2023-07-11 6:42 ` Krishna Kurapati PSSNV
2023-07-21 8:14 ` Johan Hovold
2023-07-21 8:19 ` Krishna Kurapati PSSNV
2023-07-21 9:21 ` Johan Hovold
2023-07-21 9:35 ` Krishna Kurapati PSSNV
2023-07-21 11:11 ` Johan Hovold
2023-07-12 12:12 ` Johan Hovold
2023-07-12 18:26 ` Krishna Kurapati PSSNV
2023-07-14 9:05 ` Johan Hovold
2023-07-14 10:40 ` Krishna Kurapati PSSNV
2023-07-15 19:01 ` Krishna Kurapati PSSNV
2023-07-17 15:15 ` Krishna Kurapati PSSNV
2023-07-21 8:35 ` Johan Hovold
2023-07-21 8:45 ` Krishna Kurapati PSSNV
2023-06-21 4:36 ` [PATCH v9 07/10] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Krishna Kurapati
2023-06-27 15:05 ` Johan Hovold
2023-07-02 19:02 ` Krishna Kurapati PSSNV
2023-06-21 4:36 ` [PATCH v9 08/10] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 Krishna Kurapati
2023-06-23 22:39 ` Konrad Dybcio
2023-06-24 7:13 ` Krishna Kurapati PSSNV
2023-06-27 15:16 ` Johan Hovold
2023-07-02 19:10 ` Krishna Kurapati PSSNV
2023-07-21 8:08 ` Johan Hovold
2023-06-27 15:11 ` Johan Hovold
2023-06-21 4:36 ` [PATCH v9 09/10] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports Krishna Kurapati
2023-06-23 22:40 ` Konrad Dybcio
2023-06-21 4:36 ` [PATCH v9 10/10] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Krishna Kurapati
2023-06-23 22:42 ` Konrad Dybcio
2023-06-24 7:11 ` Krishna Kurapati PSSNV
2023-06-27 15:19 ` [PATCH v9 00/10] Add multiport support for DWC3 controllers Johan Hovold
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