From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH 1/1] PCI: Cleanup link activation wait logic
Date: Fri, 2 Feb 2024 16:31:49 +0200 (EET) [thread overview]
Message-ID: <a0e8ae37-cc11-2219-201e-d6740028b735@linux.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2402021359450.15781@angie.orcam.me.uk>
[-- Attachment #1: Type: text/plain, Size: 1911 bytes --]
On Fri, 2 Feb 2024, Maciej W. Rozycki wrote:
> On Fri, 2 Feb 2024, Ilpo Järvinen wrote:
>
> > 1. Change pcie_failed_link_retrain() to return true only if link was
> > retrained successfully due to the Target Speed quirk. If there is no
> > LBMS set, return false instead of true because no retraining was
> > even attempted. This seems correct considering expectations of both
> > callers of pcie_failed_link_retrain().
>
> You change the logic here in that the second conditional isn't run if the
> first has not. This is wrong, unclamping is not supposed to rely on LBMS.
> It is supposed to be always run and any failure has to be reported too, as
> a retraining error. I'll send an update according to what I have outlined
> before then, with some testing done first.
Oh I see now, I'm sorry, I didn't read all the way to the last paragraph
of the commit message because the earlier one in the commit message hinted
the restriction is removed afterwards so I thought it was only linked to
the first part of the quirk.
> > 2. Handle link-was-not-retrained-successfully return (false) from
> > pcie_failed_link_retrain() properly in pcie_wait_for_link_delay() by
> > directly returning false.
>
> I think it has to be a separate change, as a fix to what I can see is an
> issue with a three-way-merge done with commit 1abb47390350 ("Merge branch
> 'pci/enumeration'"); surely a bool result wasn't supposed to be assigned
> to an int variable carrying an error code.
>
> Either or both changes may have to be backported independently.
But can it be? Won't the intermediate state cause more breakage? (although
that obviously can only hit some very unfortunate bisecter so perhaps not
a big deal because one would need many holes to align, the biggest being
the link has to fail training which is rare to begin with).
--
i.
next prev parent reply other threads:[~2024-02-02 14:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 13:41 [PATCH 1/1] PCI: Cleanup link activation wait logic Ilpo Järvinen
2024-02-02 14:22 ` Maciej W. Rozycki
2024-02-02 14:31 ` Ilpo Järvinen [this message]
2024-02-10 1:50 ` Maciej W. Rozycki
2024-02-26 12:53 ` Maciej W. Rozycki
2024-02-16 13:28 ` Ilpo Järvinen
2024-02-16 13:58 ` Maciej W. Rozycki
2024-02-16 14:23 ` Ilpo Järvinen
2024-02-26 12:43 ` Maciej W. Rozycki
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