From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: Anup Patel <anup.patel@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: Re: [PATCH v6 3/6] irqchip: RISC-V per-HART local interrupt controller driver
Date: Sun, 31 May 2020 10:33:39 +0100 [thread overview]
Message-ID: <a5f1346544aec6e6da69836b7a6e0a6e@kernel.org> (raw)
In-Reply-To: <CAAhSdy3cnZwnjpqWkixmZ5-fi=GK1cSUsjah=P3Yp5hjv382hg@mail.gmail.com>
On 2020-05-31 06:36, Anup Patel wrote:
> On Sat, May 30, 2020 at 5:31 PM Marc Zyngier <maz@kernel.org> wrote:
[...]
>> > plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
>>
>> Why do you need to both disable the interrupt *and* change the
>> priority
>> threshold? It seems to be that one of them should be enough, but my
>> kno9wledge of the PLIC is limited. In any case, this would deserve a
>> comment.
>
> Okay, I will test and remove "disable the interrupt" part from
> plic_dying_cpu().
Be careful, as interrupt enabling/disabling is refcounted in order
to allow nesting. If you only enable on CPU_ON and not disable
on CPU_OFF, you will end-up with a depth that only increases,
up to the point where you hit the roof (it will take a while though).
I would keep the enable/disable as is, and drop the priority
setting from the CPU_OFF path.
>> > return 0;
>> > @@ -260,7 +266,11 @@ static int plic_starting_cpu(unsigned int cpu)
>> > {
>> > struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
>> >
>> > - csr_set(CSR_IE, IE_EIE);
>> > + if (plic_parent_irq)
>> > + enable_percpu_irq(plic_parent_irq,
>> > + irq_get_trigger_type(plic_parent_irq));
>> > + else
>> > + pr_warn("cpu%d: parent irq not available\n");
>>
>> What does it mean to carry on if the interrupt cannot be signaled?
>> Shouldn't you error out instead, and leave the CPU dead?
>
> The CPU is not dead if we cannot enable RISC-V INTC external
> interrupt because the Timer and IPIs interrupts are always through
> RISC-V INTC. The PLIC external interrupt not present for a CPU
> only means that that CPU cannot receive peripherial interrupts.
>
> On a sane RISC-V system, if PLIC is present then all CPUs should
> be able to get RISC-V INTC external interrupt. Base on this rationale,
> I have put a warning for plic_parent_irq == 0.
Fair enough.
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-05-31 9:33 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-30 10:07 [PATCH v6 0/6] New RISC-V Local Interrupt Controller Driver Anup Patel
2020-05-30 10:07 ` [PATCH v6 1/6] RISC-V: self-contained IPI handling routine Anup Patel
2020-05-30 10:07 ` [PATCH v6 2/6] RISC-V: Rename and move plic_find_hart_id() to arch directory Anup Patel
2020-05-30 10:07 ` [PATCH v6 3/6] irqchip: RISC-V per-HART local interrupt controller driver Anup Patel
2020-05-30 12:01 ` Marc Zyngier
2020-05-31 5:36 ` Anup Patel
2020-05-31 9:33 ` Marc Zyngier [this message]
2020-05-31 10:06 ` Anup Patel
2020-05-31 10:53 ` Marc Zyngier
2020-06-01 4:09 ` Anup Patel
2020-06-01 7:41 ` Marc Zyngier
2020-06-01 9:13 ` Anup Patel
2020-06-01 9:33 ` Guo Ren
2020-05-30 10:07 ` [PATCH v6 4/6] clocksource/drivers/timer-riscv: Use per-CPU timer interrupt Anup Patel
2020-05-30 11:41 ` Marc Zyngier
2020-05-31 5:52 ` Anup Patel
2020-05-30 10:07 ` [PATCH v6 5/6] RISC-V: Remove do_IRQ() function Anup Patel
2020-05-30 10:07 ` [PATCH v6 6/6] RISC-V: Force select RISCV_INTC for CONFIG_RISCV Anup Patel
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