From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <anup.patel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 4/6] clocksource/drivers/timer-riscv: Use per-CPU timer interrupt
Date: Sat, 30 May 2020 12:41:22 +0100 [thread overview]
Message-ID: <e9a832ec748671b4daef398ecf784db2@kernel.org> (raw)
In-Reply-To: <20200530100725.265481-5-anup.patel@wdc.com>
On 2020-05-30 11:07, Anup Patel wrote:
> Instead of directly calling RISC-V timer interrupt handler from
> RISC-V local interrupt conntroller driver, this patch implements
> RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
> of Linux IRQ subsystem.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/include/asm/irq.h | 2 --
> drivers/clocksource/timer-riscv.c | 41 ++++++++++++++++++++++++++++---
> drivers/irqchip/irq-riscv-intc.c | 8 ------
> 3 files changed, 38 insertions(+), 13 deletions(-)
>
> diff --git a/arch/riscv/include/asm/irq.h
> b/arch/riscv/include/asm/irq.h
> index a9e5f07a7e9c..9807ad164015 100644
> --- a/arch/riscv/include/asm/irq.h
> +++ b/arch/riscv/include/asm/irq.h
> @@ -10,8 +10,6 @@
> #include <linux/interrupt.h>
> #include <linux/linkage.h>
>
> -void riscv_timer_interrupt(void);
> -
> #include <asm-generic/irq.h>
>
> #endif /* _ASM_RISCV_IRQ_H */
> diff --git a/drivers/clocksource/timer-riscv.c
> b/drivers/clocksource/timer-riscv.c
> index c4f15c4068c0..1fe847983f50 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -12,8 +12,11 @@
> #include <linux/cpu.h>
> #include <linux/delay.h>
> #include <linux/irq.h>
> +#include <linux/irqdomain.h>
> #include <linux/sched_clock.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_irq.h>
> #include <asm/smp.h>
> #include <asm/sbi.h>
>
> @@ -39,6 +42,7 @@ static int riscv_clock_next_event(unsigned long
> delta,
> return 0;
> }
>
> +static unsigned int riscv_clock_event_irq;
> static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) =
> {
> .name = "riscv_timer_clockevent",
> .features = CLOCK_EVT_FEAT_ONESHOT,
> @@ -74,30 +78,36 @@ static int riscv_timer_starting_cpu(unsigned int
> cpu)
> struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
>
> ce->cpumask = cpumask_of(cpu);
> + ce->irq = riscv_clock_event_irq;
> clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
>
> - csr_set(CSR_IE, IE_TIE);
> + enable_percpu_irq(riscv_clock_event_irq,
> + irq_get_trigger_type(riscv_clock_event_irq));
> return 0;
> }
>
> static int riscv_timer_dying_cpu(unsigned int cpu)
> {
> - csr_clear(CSR_IE, IE_TIE);
> + disable_percpu_irq(riscv_clock_event_irq);
> return 0;
> }
>
> /* called directly from the low-level interrupt handler */
> -void riscv_timer_interrupt(void)
> +static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> {
> struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
>
> csr_clear(CSR_IE, IE_TIE);
> evdev->event_handler(evdev);
> +
> + return IRQ_HANDLED;
> }
>
> static int __init riscv_timer_init_dt(struct device_node *n)
> {
> int cpuid, hartid, error;
> + struct device_node *child;
> + struct irq_domain *domain;
>
> hartid = riscv_of_processor_hartid(n);
> if (hartid < 0) {
> @@ -115,6 +125,23 @@ static int __init riscv_timer_init_dt(struct
> device_node *n)
> if (cpuid != smp_processor_id())
> return 0;
>
> + domain = NULL;
> + for_each_child_of_node(n, child) {
> + domain = irq_find_host(child);
> + if (domain)
> + break;
> + }
This is a bit clumsy, and probably better written as:
child = of_get_compatible(n, "riscv,cpu-intc");
if (!child) { error out }
domain = irq_find_host(child);
It would be even better if each CPU would have its per-CPU interrupt
controller designated as such (with an interrupt-parent property),
meaning that you wouldn't have to do anything at all.
Too late for that anyway.
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-05-30 11:41 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-30 10:07 [PATCH v6 0/6] New RISC-V Local Interrupt Controller Driver Anup Patel
2020-05-30 10:07 ` [PATCH v6 1/6] RISC-V: self-contained IPI handling routine Anup Patel
2020-05-30 10:07 ` [PATCH v6 2/6] RISC-V: Rename and move plic_find_hart_id() to arch directory Anup Patel
2020-05-30 10:07 ` [PATCH v6 3/6] irqchip: RISC-V per-HART local interrupt controller driver Anup Patel
2020-05-30 12:01 ` Marc Zyngier
2020-05-31 5:36 ` Anup Patel
2020-05-31 9:33 ` Marc Zyngier
2020-05-31 10:06 ` Anup Patel
2020-05-31 10:53 ` Marc Zyngier
2020-06-01 4:09 ` Anup Patel
2020-06-01 7:41 ` Marc Zyngier
2020-06-01 9:13 ` Anup Patel
2020-06-01 9:33 ` Guo Ren
2020-05-30 10:07 ` [PATCH v6 4/6] clocksource/drivers/timer-riscv: Use per-CPU timer interrupt Anup Patel
2020-05-30 11:41 ` Marc Zyngier [this message]
2020-05-31 5:52 ` Anup Patel
2020-05-30 10:07 ` [PATCH v6 5/6] RISC-V: Remove do_IRQ() function Anup Patel
2020-05-30 10:07 ` [PATCH v6 6/6] RISC-V: Force select RISCV_INTC for CONFIG_RISCV Anup Patel
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