From: Georgi Djakov <georgi.djakov@linaro.org>
To: bjorn.andersson@linaro.org
Cc: Sibi Sankar <sibis@codeaurora.org>,
robh+dt@kernel.org, agross@kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, jonathan@marek.ca,
linux-pm@vger.kernel.org
Subject: Re: [PATCH 6/7] arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider
Date: Wed, 9 Sep 2020 11:05:03 +0300 [thread overview]
Message-ID: <a60ab579-baaf-06bd-02c7-ac584aeac3e4@linaro.org> (raw)
In-Reply-To: <20200801123049.32398-7-sibis@codeaurora.org>
On 8/1/20 15:30, Sibi Sankar wrote:
> Add Operation State Manager (OSM) L3 interconnect provider node on
> SM8150 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 0f6d84e8fd299..8563afd205ee9 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sm8150.h>
> #include <dt-bindings/thermal/thermal.h>
>
> @@ -1184,6 +1185,16 @@ apps_bcm_voter: bcm_voter {
> };
> };
>
> + osm_l3: interconnect@18321000 {
> + compatible = "qcom,sm8150-osm-l3";
> + reg = <0 0x18321000 0 0x1400>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@18323000 {
> compatible = "qcom,cpufreq-hw";
> reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
>
next prev parent reply other threads:[~2020-09-09 8:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-01 12:30 [PATCH 0/7] Add L3 provider support for SM8150/SM8250 Sibi Sankar
2020-08-01 12:30 ` [PATCH 1/7] dt-bindings: interconnect: Add OSM L3 DT binding on SM8150 Sibi Sankar
2020-08-17 21:16 ` Rob Herring
2020-08-01 12:30 ` [PATCH 2/7] interconnect: qcom: Add OSM L3 support " Sibi Sankar
2020-08-01 12:30 ` [PATCH 3/7] interconnect: qcom: Lay the groundwork for adding EPSS support Sibi Sankar
2020-08-01 12:30 ` [PATCH 4/7] dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250 Sibi Sankar
2020-08-17 21:16 ` Rob Herring
2020-08-01 12:30 ` [PATCH 5/7] interconnect: qcom: Add EPSS L3 support " Sibi Sankar
2020-08-01 12:30 ` [PATCH 6/7] arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider Sibi Sankar
2020-09-09 8:05 ` Georgi Djakov [this message]
2020-08-01 12:30 ` [PATCH 7/7] arm64: dts: qcom: sm8250: Add EPSS " Sibi Sankar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a60ab579-baaf-06bd-02c7-ac584aeac3e4@linaro.org \
--to=georgi.djakov@linaro.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=jonathan@marek.ca \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=sibis@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).