[PATCH v2 0/4] ARM: tegra: initial support for Colibri T30

[PATCH v2 0/4] ARM: tegra: initial support for Colibri T30

[stefan]

From: Stefan Agner <stefan@agner.ch>

This device tree cooked a while in our repository and is now quite
complete. All is tested on several Colibri T30 modules and
evaluation boards by Marcel and me. The device tree is splitted
into a module part and the carrier board. The former is then
included by the latter (in this case the evaluation board). The
comments "Colibri: " represent the SO-DIMM Pin name as defined
in the Colibri standard, and should be helpful for users
adopting the device tree for other carrier boards.

The second revision has one new patch which adds Toradex default
demo panels to the simple-panel driver. One could argue that those
panels are not actually part of the evaluation board, but when
customer build something with TFT panels they usually are integrated
into one system. Hence I descided to add them to the evaluation board
as well to have such a complete system, including TFT panel.

Note: Patch 1 is already applied!

Changes since v1:
- Extended with two TFT LCD panels from EDT
- Removed version specific compatible string and add modules compatible
  string in the carrier board file
- Removed serial alias and dr_mode property from USB controller
- Removed PMC status since this is enabled in tegra30.dtsi
- Lowered voltage of VDD_CPU to 1.15V again (tests were done with 1.15V)
- Added pinmux for lcd_m1 which makes data enable based panels working

Stefan Agner (3):
  ARM: tegra: enable MCP251x CAN controller and DS1307 RTC
  drm/panel: add support for EDT panels
  ARM: tegra: initial add of Colibri T30

 .../devicetree/bindings/panel/edt,et057090dhu.txt  |   7 +
 .../devicetree/bindings/panel/edt,et070080dh6.txt  |   7 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/tegra30-colibri-eval-v3.dts      | 205 +++++++++++
 arch/arm/boot/dts/tegra30-colibri.dtsi             | 377 +++++++++++++++++++++
 arch/arm/configs/tegra_defconfig                   |   6 +
 drivers/gpu/drm/panel/panel-simple.c               |  52 +++
 7 files changed, 655 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/edt,et057090dhu.txt
 create mode 100644 Documentation/devicetree/bindings/panel/edt,et070080dh6.txt
 create mode 100644 arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
 create mode 100644 arch/arm/boot/dts/tegra30-colibri.dtsi

-- 
1.9.2

[PATCH v2 1/3] ARM: tegra: enable MCP251x CAN controller and DS1307 RTC

[stefan]

From: Stefan Agner <stefan@agner.ch>

Toradex Colibri Evaluation Board uses the DS1307 RTC and the
MCP251x CAN controller. The NVIDIA Tegra 3 based Colibri T30
module can be used on this carrier board, hence enable those
drivers in tegra_defonfig.

Furthermore the NVIDIA Tegra 3 based Apalis T30 module too
contains two MCP251x CAN controller.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/configs/tegra_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 2926281..6329632 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -73,6 +73,11 @@ CONFIG_INET6_IPCOMP=y
 CONFIG_IPV6_MIP6=y
 CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_MCP251X=y
 CONFIG_BT=y
 CONFIG_BT_RFCOMM=y
 CONFIG_BT_BNEP=y
@@ -222,6 +227,7 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AS3722=y
+CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TPS6586X=y
-- 
1.9.2

[PATCH v2 2/3] drm/panel: add support for EDT panels

[stefan]

From: Stefan Agner <stefan@agner.ch>

This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
evaluation kits.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 .../devicetree/bindings/panel/edt,et057090dhu.txt  |  7 +++
 .../devicetree/bindings/panel/edt,et070080dh6.txt  |  7 +++
 drivers/gpu/drm/panel/panel-simple.c               | 52 ++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/edt,et057090dhu.txt
 create mode 100644 Documentation/devicetree/bindings/panel/edt,et070080dh6.txt

diff --git a/Documentation/devicetree/bindings/panel/edt,et057090dhu.txt b/Documentation/devicetree/bindings/panel/edt,et057090dhu.txt
new file mode 100644
index 0000000..4903d7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/edt,et057090dhu.txt
@@ -0,0 +1,7 @@
+Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
+
+Required properties:
+- compatible: should be "edt,et057090dhu"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/edt,et070080dh6.txt b/Documentation/devicetree/bindings/panel/edt,et070080dh6.txt
new file mode 100644
index 0000000..64986b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/edt,et070080dh6.txt
@@ -0,0 +1,7 @@
+Emerging Display Technology Corp. 7.0" WVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "edt,et070080dh6"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 309f29e..7e4103f 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -306,6 +306,52 @@ static const struct panel_desc chunghwa_claa101wa01a = {
 	},
 };
 
+static const struct drm_display_mode edt_et057090dhu_mode = {
+	.clock = 25175,
+	.hdisplay = 640,
+	.hsync_start = 640 + 16,
+	.hsync_end = 640 + 16 + 30,
+	.htotal = 640 + 16 + 30 + 114,
+	.vdisplay = 480,
+	.vsync_start = 480 + 10,
+	.vsync_end = 480 + 10 + 3,
+	.vtotal = 480 + 10 + 3 + 32,
+	.vrefresh = 60,
+	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc edt_et057090dhu = {
+	.modes = &edt_et057090dhu_mode,
+	.num_modes = 1,
+	.size = {
+		.width = 115,
+		.height = 86,
+	},
+};
+
+static const struct drm_display_mode edt_et070080dh6_mode = {
+	.clock = 33260,
+	.hdisplay = 800,
+	.hsync_start = 800 + 40,
+	.hsync_end = 800 + 40 + 128,
+	.htotal = 800 + 40 + 128 + 88,
+	.vdisplay = 480,
+	.vsync_start = 480 + 8,
+	.vsync_end = 480 + 8 + 2,
+	.vtotal = 480 + 8 + 2 + 35,
+	.vrefresh = 60,
+	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc edt_et070080dh6 = {
+	.modes = &edt_et070080dh6_mode,
+	.num_modes = 1,
+	.size = {
+		.width = 152,
+		.height = 91,
+	},
+};
+
 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 	.clock = 69300,
 	.hdisplay = 1366,
@@ -383,6 +429,12 @@ static const struct of_device_id platform_of_match[] = {
 		.compatible = "chunghwa,claa101wb01",
 		.data = &chunghwa_claa101wb01
 	}, {
+		.compatible = "edt,et057090dhu",
+		.data = &edt_et057090dhu,
+	}, {
+		.compatible = "edt,et070080dh6",
+		.data = &edt_et070080dh6,
+	}, {
 		.compatible = "lg,lp129qe",
 		.data = &lg_lp129qe,
 	}, {
-- 
1.9.2

[PATCH v2 3/3] ARM: tegra: initial add of Colibri T30

[stefan]

From: Stefan Agner <stefan@agner.ch>

This patch adds the device tree to support Toradex Colibri T30, a
computer on module which can be used on different carrier boards.

The module consists of a Tegra 30 SoC, two PMIC, DDR3L RAM, eMMC,
a LM95245 temperature sensor and an AX88772B USB Ethernet
Controller. Furthermore, there is a STMPE811 and SGTL5000 audio
codec which are not yet supported. Anything that is not self
contained on the module is disabled by default.

The device tree for the Evaluation Board includes the modules
device tree and enables the supported pheripherials of the carrier
board (the Evaluation Board supports almost all of them).

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 205 ++++++++++++++
 arch/arm/boot/dts/tegra30-colibri.dtsi        | 377 ++++++++++++++++++++++++++
 3 files changed, 583 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
 create mode 100644 arch/arm/boot/dts/tegra30-colibri.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..9e9669c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -367,6 +367,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra30-beaver.dtb \
 	tegra30-cardhu-a02.dtb \
 	tegra30-cardhu-a04.dtb \
+	tegra30-colibri-eval-v3.dtb \
 	tegra114-dalmore.dtb \
 	tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
new file mode 100644
index 0000000..7793abd
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -0,0 +1,205 @@
+/dts-v1/;
+
+#include "tegra30-colibri.dtsi"
+
+/ {
+	model = "Toradex Colibri T30 on Colibri Evaluation Board";
+	compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30";
+
+	aliases {
+		rtc0 = "/i2c@7000c000/rtc@68";
+		rtc1 = "/i2c@7000d000/tps65911@2d";
+		rtc2 = "/rtc@7000e000";
+	};
+
+	host1x@50000000 {
+		dc@54200000 {
+			rgb {
+				status = "okay";
+				nvidia,panel = <&panel>;
+			};
+		};
+		hdmi@54280000 {
+			status = "okay";
+		};
+	};
+
+	serial@70006000 {
+		status = "okay";
+	};
+
+	serial@70006040 {
+		compatible = "nvidia,tegra30-hsuart";
+		status = "okay";
+	};
+
+	serial@70006300 {
+		compatible = "nvidia,tegra30-hsuart";
+		status = "okay";
+	};
+
+	pwm@7000a000 {
+		status = "okay";
+	};
+
+	/*
+	 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+	 * board)
+	 */
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		/* M41T0M6 real time clock on carrier board */
+		rtc@68 {
+			compatible = "stm,m41t00";
+			reg = <0x68>;
+		};
+	};
+
+	/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
+	hdmiddc: i2c@7000c700 {
+		status = "okay";
+	};
+
+	/* SPI1: Colibri SSP */
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+		can0: can@0 {
+			compatible = "microchip,mcp2515";
+			reg = <0>;
+			clocks = <&clk16m>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+			spi-max-frequency = <10000000>;
+		};
+		spidev0: spi@1 {
+			compatible = "spidev";
+			reg = <1>;
+			spi-max-frequency = <25000000>;
+		};
+	};
+
+	sdhci@78000200 {
+		status = "okay";
+		bus-width = <4>;
+		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+		no-1-8-v;
+	};
+
+	/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
+	usb@7d000000 {
+		status = "okay";
+	};
+
+	usb-phy@7d000000 {
+		status = "okay";
+		dr_mode = "otg";
+		vbus-supply = <&usbc_vbus_reg>;
+	};
+
+	/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
+	usb@7d008000 {
+		status = "okay";
+	};
+
+	usb-phy@7d008000 {
+		status = "okay";
+		vbus-supply = <&usbh_vbus_reg>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		/* PWM<A> */
+		pwms = <&pwm 0 5000000>;
+		brightness-levels = <255 128 64 32 16 8 4 0>;
+		default-brightness-level = <6>;
+		/* BL_ON */
+		enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+	};
+
+	clocks {
+		clk16m: clk@1 {
+			compatible = "fixed-clock";
+			reg=<1>;
+			#clock-cells = <0>;
+			clock-frequency = <16000000>;
+			clock-output-names = "clk16m";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_POWER>;
+			debounce-interval = <10>;
+			gpio-key,wakeup;
+		};
+	};
+
+	panel: panel {
+		/*
+		 * edt,et057090dhu: EDT 5.7" LCD TFT
+		 * edt,et070080dh6: EDT 7.0" LCD TFT
+		 */
+		compatible = "edt,et057090dhu", "simple-panel";
+
+		backlight = <&backlight>;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		pwmb {
+			label = "PWM<B>";
+			pwms = <&pwm 1 19600>;
+			max-brightness = <255>;
+		};
+		pwmc {
+			label = "PWM<C>";
+			pwms = <&pwm 2 19600>;
+			max-brightness = <255>;
+		};
+		pwmd {
+			label = "PWM<D>";
+			pwms = <&pwm 3 19600>;
+			max-brightness = <255>;
+		};
+	};
+
+	regulators {
+		sys_5v0_reg: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		usbc_vbus_reg: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "usbc_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			vin-supply = <&sys_5v0_reg>;
+		};
+
+		/* USBH_PEN */
+		usbh_vbus_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "usbh_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+			vin-supply = <&sys_5v0_reg>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
new file mode 100644
index 0000000..bf16f8e
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -0,0 +1,377 @@
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+
+/*
+ * Toradex Colibri T30 Device Tree
+ * Compatible for Revisions 1.1B/1.1C/1.1D
+ */
+/ {
+	model = "Toradex Colibri T30";
+	compatible = "toradex,colibri_t30", "nvidia,tegra30";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	host1x@50000000 {
+		hdmi@54280000 {
+			vdd-supply = <&sys_3v3_reg>;
+			pll-supply = <&vio_reg>;
+
+			nvidia,hpd-gpio =
+				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+			nvidia,ddc-i2c-bus = <&hdmiddc>;
+		};
+	};
+
+	pinmux@70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			/* Colibri BL_ON */
+			pv2 {
+				nvidia,pins = "pv2";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Colibri Backlight PWM<A> */
+			sdmmc3_dat3_pb4 {
+				nvidia,pins =	"sdmmc3_dat3_pb4";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Colibri CAN_INT */
+			kb_row8_ps0 {
+				nvidia,pins = "kb_row8_ps0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/*
+			 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
+			 * todays display need DE, disable LCD_M1
+			 */
+			lcd_m1_pw1 {
+				nvidia,pins = "lcd_m1_pw1";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Thermal alert, need to be disabled */
+			lcd_dc1_pd2 {
+				nvidia,pins = "lcd_dc1_pd2";
+				nvidia,function = "rsvd3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Colibri MMC */
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			kb_row11_ps3 {
+				nvidia,pins =	"kb_row11_ps3",
+						"kb_row12_ps4",
+						"kb_row13_ps5",
+						"kb_row14_ps6",
+						"kb_row15_ps7";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Colibri SSP */
+			ulpi_clk_py0 {
+				nvidia,pins =   "ulpi_clk_py0",
+						"ulpi_dir_py1",
+						"ulpi_nxt_py2",
+						"ulpi_stp_py3";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc3_dat6_pd3 {
+				nvidia,pins =	"sdmmc3_dat6_pd3",
+						"sdmmc3_dat7_pd4";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Colibri UART_A */
+			ulpi_data0 {
+				nvidia,pins =   "ulpi_data0_po1",
+						"ulpi_data1_po2",
+						"ulpi_data2_po3",
+						"ulpi_data3_po4",
+						"ulpi_data4_po5",
+						"ulpi_data5_po6",
+						"ulpi_data6_po7",
+						"ulpi_data7_po0";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Colibri UART_B */
+			gmi_a16_pj7 {
+				nvidia,pins =   "gmi_a16_pj7",
+						"gmi_a17_pb0",
+						"gmi_a18_pb1",
+						"gmi_a19_pk7";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Colibri UART_C */
+			uart2_rxd {
+				nvidia,pins =   "uart2_rxd_pc3",
+						"uart2_txd_pc2";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* eMMC */
+			sdmmc4_clk_pcc4 {
+				nvidia,pins =	"sdmmc4_clk_pcc4",
+						"sdmmc4_rst_n_pcc3";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_dat0_paa0 {
+				nvidia,pins =	"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+		};
+	};
+
+	hdmiddc: i2c@7000c700 {
+		clock-frequency = <100000>;
+	};
+
+	/*
+	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+	 * touch screen controller
+	 */
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		pmic: tps65911@2d {
+			compatible = "ti,tps65911";
+			reg = <0x2d>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			vcc1-supply = <&sys_3v3_reg>;
+			vcc2-supply = <&sys_3v3_reg>;
+			vcc3-supply = <&vio_reg>;
+			vcc4-supply = <&sys_3v3_reg>;
+			vcc5-supply = <&sys_3v3_reg>;
+			vcc6-supply = <&vio_reg>;
+			vcc7-supply = <&sys_5v0_reg>;
+			vccio-supply = <&sys_3v3_reg>;
+
+			regulators {
+				/* SW1: +V1.35_VDDIO_DDR */
+				vdd1_reg: vdd1 {
+					regulator-name = "vddio_ddr_1v35";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+				};
+
+				/* SW2: unused */
+
+				/* SW CTRL: +V1.0_VDD_CPU */
+				vddctrl_reg: vddctrl {
+					regulator-name = "vdd_cpu,vdd_sys";
+					regulator-min-microvolt = <1150000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-always-on;
+				};
+
+				/* SWIO: +V1.8 */
+				vio_reg: vio {
+					regulator-name = "vdd_1v8_gen";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				/* LDO1: unused */
+
+				/*
+				 * EN_+V3.3 switching via FET:
+				 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
+				 * see also v3_3 fixed supply
+				 */
+				ldo2_reg: ldo2 {
+					regulator-name = "en_3v3";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				/* LDO3: unused */
+
+				/* +V1.2_VDD_RTC */
+				ldo4_reg: ldo4 {
+					regulator-name = "vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				/*
+				 * +V2.8_AVDD_VDAC:
+				 * only required for analog RGB
+				 */
+				ldo5_reg: ldo5 {
+					regulator-name = "avdd_vdac";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				/*
+				 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
+				 * but LDO6 can't set voltage in 50mV
+				 * granularity
+				 */
+				ldo6_reg: ldo6 {
+					regulator-name = "avdd_plle";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+				};
+
+				/* +V1.2_AVDD_PLL */
+				ldo7_reg: ldo7 {
+					regulator-name = "avdd_pll";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				/* +V1.0_VDD_DDR_HS */
+				ldo8_reg: ldo8 {
+					regulator-name = "vdd_ddr_hs";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		/*
+		 * LM95245 temperature sensor
+		 * Note: OVERT_N directly connected to PMIC PWRDN
+		 */
+		temp-sensor@4c {
+			compatible = "national,lm95245";
+			reg = <0x4c>;
+		};
+
+		/* SW: +V1.2_VDD_CORE */
+		tps62362@60 {
+			compatible = "ti,tps62362";
+			reg = <0x60>;
+
+			regulator-name = "tps62362-vout";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1400000>;
+			regulator-boot-on;
+			regulator-always-on;
+			ti,vsel0-state-low;
+			/* VSEL1: EN_CORE_DVFS_N low for DVFS */
+			ti,vsel1-state-low;
+		};
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <0>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	emmc: sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	/* EHCI instance 1: USB2_DP/N -> AX88772B */
+	usb@7d004000 {
+		status = "okay";
+	};
+
+	usb-phy@7d004000 {
+		status = "okay";
+		nvidia,is-wired = <1>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clk@0 {
+			compatible = "fixed-clock";
+			reg=<0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sys_3v3_reg: regulator@100 {
+			compatible = "regulator-fixed";
+			reg = <100>;
+			regulator-name = "3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
-- 
1.9.2

Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Thierry Reding]

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On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
> From: Stefan Agner <stefan@agner.ch>
> 
> This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
> evaluation kits.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Panel patches should go to the dri-devel mailing list as well.

Also a patch was posted only yesterday for a panel that seems to be the
exact same one as this, even though the name differs minimally, see:

	https://patchwork.kernel.org/patch/4175251/

Adding Philipp on Cc so you guys can work together whether this is
indeed the same panel. The only differences seem to be in the vertical
front and back porches, but I suspect that either settings will work on
both Tegra and i.MX.

Thierry

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Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Stefan Agner]

Hi Thierry, hi Philipp,

Am 2014-05-15 09:51, schrieb Thierry Reding:
> On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
>> From: Stefan Agner <stefan@agner.ch>
>>
>> This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
>> evaluation kits.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> Panel patches should go to the dri-devel mailing list as well.
> 
> Also a patch was posted only yesterday for a panel that seems to be the
> exact same one as this, even though the name differs minimally, see:
> 
> 	https://patchwork.kernel.org/patch/4175251/
> 
> Adding Philipp on Cc so you guys can work together whether this is
> indeed the same panel. The only differences seem to be in the vertical
> front and back porches, but I suspect that either settings will work on
> both Tegra and i.MX.

Its etm0700g0dh6 vs. et070080dh6, Philipp's panel is with captive multi
touch, (hence the M I guess). The panel itself really looks the same.

I found this overview of EDT displays:
http://www.dmbtechnics.com/scripts/passthru.php?id=7

There seem to be quite a lot variants with the same panel...

Regarding timings, I just checked the documentation, Philipp's timing
really matches the documented ones, I miscalculated the vertical back
porch.

How do we resolve that?

I would suggest that I split out that patch and remove the et070080dh6
panel and send the other as a single patch to the dri-devel mailing list
as well.

Philipp, could you add my display type (et070080dh6) to the compatible
list of your mode/panel entry?

Does this sound reasonable?

--
Stefan

Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Philipp Zabel]

Am Donnerstag, den 15.05.2014, 09:51 +0200 schrieb Thierry Reding:
> On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
> > From: Stefan Agner <stefan@agner.ch>
> > 
> > This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
> > evaluation kits.
> > 
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> Panel patches should go to the dri-devel mailing list as well.
> 
> Also a patch was posted only yesterday for a panel that seems to be the
> exact same one as this, even though the name differs minimally, see:
> 
> 	https://patchwork.kernel.org/patch/4175251/
> 
> Adding Philipp on Cc so you guys can work together whether this is
> indeed the same panel. The only differences seem to be in the vertical
> front and back porches, but I suspect that either settings will work on
> both Tegra and i.MX.

The ETM0700G0DH6 Datasheet lists 2 lines as the typical vsync pulse
width, 525 lines as the vertical period, and 35 lines as the vsync -de
time, which is vsync len + back porch.
So vertical timings 480 + 10 + 2 + 33 = 525 should be valid for the
ET0700G0DH6 panel:

https://www.glynshop.com/erp/owweb/Daten/DSS/EDT/Products/Specifications/Active%20Displays/ET0700G0DH6.pdf
et070080dh6

I have not seen the data sheet for ET070080DH6.

regards
Philipp

Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1917 bytes --]

On Thu, May 15, 2014 at 10:27:29AM +0200, Philipp Zabel wrote:
> Am Donnerstag, den 15.05.2014, 09:51 +0200 schrieb Thierry Reding:
> > On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
> > > From: Stefan Agner <stefan@agner.ch>
> > > 
> > > This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
> > > evaluation kits.
> > > 
> > > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > 
> > Panel patches should go to the dri-devel mailing list as well.
> > 
> > Also a patch was posted only yesterday for a panel that seems to be the
> > exact same one as this, even though the name differs minimally, see:
> > 
> > 	https://patchwork.kernel.org/patch/4175251/
> > 
> > Adding Philipp on Cc so you guys can work together whether this is
> > indeed the same panel. The only differences seem to be in the vertical
> > front and back porches, but I suspect that either settings will work on
> > both Tegra and i.MX.
> 
> The ETM0700G0DH6 Datasheet lists 2 lines as the typical vsync pulse
> width, 525 lines as the vertical period, and 35 lines as the vsync -de
> time, which is vsync len + back porch.
> So vertical timings 480 + 10 + 2 + 33 = 525 should be valid for the
> ET0700G0DH6 panel:

Shouldn't that work with 480 + 8 + 2 + 35 too? It seems to me that it
should still be safe for that panel. Similarily I'd expect your timings
to work on the ET070080DH6.

Irrespective of that they both seem to have different capabilities so
two compatible values should be fine. However for the purpose of the
simple panel driver they could be made to share the same timings if it
works for both panels and devices.

As for the touch panel on the ETM0700G0DH6, do you happen to know how
that's usually connected? I suspect it needs external hardware to
capture the YU, XL, YD and XR pins and turn that into raw coordinates
and pen down interrupts.

Thierry

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Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2180 bytes --]

On Thu, May 15, 2014 at 10:24:39AM +0200, Stefan Agner wrote:
> Hi Thierry, hi Philipp,
> 
> Am 2014-05-15 09:51, schrieb Thierry Reding:
> > On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
> >> From: Stefan Agner <stefan@agner.ch>
> >>
> >> This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
> >> evaluation kits.
> >>
> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
> > 
> > Panel patches should go to the dri-devel mailing list as well.
> > 
> > Also a patch was posted only yesterday for a panel that seems to be the
> > exact same one as this, even though the name differs minimally, see:
> > 
> > 	https://patchwork.kernel.org/patch/4175251/
> > 
> > Adding Philipp on Cc so you guys can work together whether this is
> > indeed the same panel. The only differences seem to be in the vertical
> > front and back porches, but I suspect that either settings will work on
> > both Tegra and i.MX.
> 
> Its etm0700g0dh6 vs. et070080dh6, Philipp's panel is with captive multi
> touch, (hence the M I guess). The panel itself really looks the same.
> 
> I found this overview of EDT displays:
> http://www.dmbtechnics.com/scripts/passthru.php?id=7
> 
> There seem to be quite a lot variants with the same panel...
> 
> Regarding timings, I just checked the documentation, Philipp's timing
> really matches the documented ones, I miscalculated the vertical back
> porch.

Okay, so that means that the panel works for you with the same timings
that Philipp has in the ETM0700G0DH6 patch? If so then I definitely
think we should be sharing the timings in the driver by making the two
compatible entries point to the same driver data.

> How do we resolve that?
> 
> I would suggest that I split out that patch and remove the et070080dh6
> panel and send the other as a single patch to the dri-devel mailing list
> as well.

Yes, that would work.

> Philipp, could you add my display type (et070080dh6) to the compatible
> list of your mode/panel entry?

I also noticed that Philipp's patch doesn't actually introduce the
device tree bindings, so that will have to be added as well.

Thierry

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Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Philipp Zabel]

Am Donnerstag, den 15.05.2014, 11:08 +0200 schrieb Thierry Reding:
> On Thu, May 15, 2014 at 10:27:29AM +0200, Philipp Zabel wrote:
> > Am Donnerstag, den 15.05.2014, 09:51 +0200 schrieb Thierry Reding:
> > > On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
> > > > From: Stefan Agner <stefan@agner.ch>
> > > > 
> > > > This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
> > > > evaluation kits.
> > > > 
> > > > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > > 
> > > Panel patches should go to the dri-devel mailing list as well.
> > > 
> > > Also a patch was posted only yesterday for a panel that seems to be the
> > > exact same one as this, even though the name differs minimally, see:
> > > 
> > > 	https://patchwork.kernel.org/patch/4175251/
> > > 
> > > Adding Philipp on Cc so you guys can work together whether this is
> > > indeed the same panel. The only differences seem to be in the vertical
> > > front and back porches, but I suspect that either settings will work on
> > > both Tegra and i.MX.
> > 
> > The ETM0700G0DH6 Datasheet lists 2 lines as the typical vsync pulse
> > width, 525 lines as the vertical period, and 35 lines as the vsync -de
> > time, which is vsync len + back porch.
> > So vertical timings 480 + 10 + 2 + 33 = 525 should be valid for the
> > ET0700G0DH6 panel:
> 
> Shouldn't that work with 480 + 8 + 2 + 35 too? It seems to me that it
> should still be safe for that panel. Similarily I'd expect your timings
> to work on the ET070080DH6.
>
> Irrespective of that they both seem to have different capabilities so
> two compatible values should be fine. However for the purpose of the
> simple panel driver they could be made to share the same timings if it
> works for both panels and devices.

Yes. As I understand, the 480 + 10 + 2 + 33 timing should be correct for
both panels.

> As for the touch panel on the ETM0700G0DH6, do you happen to know how
> that's usually connected? I suspect it needs external hardware to
> capture the YU, XL, YD and XR pins and turn that into raw coordinates
> and pen down interrupts.

The ETM0700G0DH6 has a capacitive touch screen with an EDT-FT5406
controller connected via I2C, at least on the panels that I have seen.

regards
Philipp

Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Philipp Zabel]

Am Donnerstag, den 15.05.2014, 11:12 +0200 schrieb Thierry Reding:
> On Thu, May 15, 2014 at 10:24:39AM +0200, Stefan Agner wrote:
> > Hi Thierry, hi Philipp,
> > 
> > Am 2014-05-15 09:51, schrieb Thierry Reding:
> > > On Wed, May 14, 2014 at 11:45:57PM +0200, stefan@agner.ch wrote:
> > >> From: Stefan Agner <stefan@agner.ch>
> > >>
> > >> This panels are sold by Toradex for Colibri T20/T30 and Apalis T30
> > >> evaluation kits.
> > >>
> > >> Signed-off-by: Stefan Agner <stefan@agner.ch>
> > > 
> > > Panel patches should go to the dri-devel mailing list as well.
> > > 
> > > Also a patch was posted only yesterday for a panel that seems to be the
> > > exact same one as this, even though the name differs minimally, see:
> > > 
> > > 	https://patchwork.kernel.org/patch/4175251/
> > > 
> > > Adding Philipp on Cc so you guys can work together whether this is
> > > indeed the same panel. The only differences seem to be in the vertical
> > > front and back porches, but I suspect that either settings will work on
> > > both Tegra and i.MX.
> > 
> > Its etm0700g0dh6 vs. et070080dh6, Philipp's panel is with captive multi
> > touch, (hence the M I guess). The panel itself really looks the same.
> > 
> > I found this overview of EDT displays:
> > http://www.dmbtechnics.com/scripts/passthru.php?id=7
> > 
> > There seem to be quite a lot variants with the same panel...
> > 
> > Regarding timings, I just checked the documentation, Philipp's timing
> > really matches the documented ones, I miscalculated the vertical back
> > porch.
> 
> Okay, so that means that the panel works for you with the same timings
> that Philipp has in the ETM0700G0DH6 patch? If so then I definitely
> think we should be sharing the timings in the driver by making the two
> compatible entries point to the same driver data.
> 
> > How do we resolve that?
> > 
> > I would suggest that I split out that patch and remove the et070080dh6
> > panel and send the other as a single patch to the dri-devel mailing list
> > as well.
> 
> Yes, that would work.
> 
> > Philipp, could you add my display type (et070080dh6) to the compatible
> > list of your mode/panel entry?
> 
> I also noticed that Philipp's patch doesn't actually introduce the
> device tree bindings, so that will have to be added as well.

Hmm, yes. Should I take over the edt,et070080dh6.txt from Stefan's
series and repost all, or can I just hand in the missing
edt,etm0700g0dh6.txt separately?

regards
Philipp

Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Stefan Agner]

Am 2014-05-15 11:08, schrieb Thierry Reding:
> On Thu, May 15, 2014 at 10:27:29AM +0200, Philipp Zabel wrote:
>> The ETM0700G0DH6 Datasheet lists 2 lines as the typical vsync pulse
>> width, 525 lines as the vertical period, and 35 lines as the vsync -de
>> time, which is vsync len + back porch.
>> So vertical timings 480 + 10 + 2 + 33 = 525 should be valid for the
>> ET0700G0DH6 panel:
> 
> Shouldn't that work with 480 + 8 + 2 + 35 too? It seems to me that it
> should still be safe for that panel. Similarily I'd expect your timings
> to work on the ET070080DH6.

Am 2014-05-15 11:12, schrieb Thierry Reding:
> Okay, so that means that the panel works for you with the same timings
> that Philipp has in the ETM0700G0DH6 patch? If so then I definitely
> think we should be sharing the timings in the driver by making the two
> compatible entries point to the same driver data.

FWIW, I checked and it works with both timings. And I bet it is really
the same panel its just a different touch on top.

> Irrespective of that they both seem to have different capabilities so
> two compatible values should be fine. However for the purpose of the
> simple panel driver they could be made to share the same timings if it
> works for both panels and devices.
> 
> As for the touch panel on the ETM0700G0DH6, do you happen to know how
> that's usually connected? I suspect it needs external hardware to
> capture the YU, XL, YD and XR pins and turn that into raw coordinates
> and pen down interrupts.

For Colibri Evaluation Board, those pins are routed to the generic
4-wire pins of the Colibri SO-DIMM. On the Colibri T30 module, those
pins are connected to a STMPE811. I also added that to the device tree
once, however it does not work properly atm, I need to debug this and
will send a patch at a later time.

--
Stefan

Re: [PATCH v2 2/3] drm/panel: add support for EDT panels

[Stefan Agner]

Am 2014-05-15 11:35, schrieb Philipp Zabel:
> Am Donnerstag, den 15.05.2014, 11:12 +0200 schrieb Thierry Reding:
<snip>
>> I also noticed that Philipp's patch doesn't actually introduce the
>> device tree bindings, so that will have to be added as well.
> 
> Hmm, yes. Should I take over the edt,et070080dh6.txt from Stefan's
> series and repost all, or can I just hand in the missing
> edt,etm0700g0dh6.txt separately?

Just sent a revision of my patch which doesn't contain that text file
anymore, hence for me it would be preferable if you can add both
files...

--
Stefan

Re: [PATCH v2 1/3] ARM: tegra: enable MCP251x CAN controller and DS1307 RTC

[Stephen Warren]

On 05/14/2014 03:45 PM, stefan@agner.ch wrote:
> From: Stefan Agner <stefan@agner.ch>
> 
> Toradex Colibri Evaluation Board uses the DS1307 RTC and the
> MCP251x CAN controller. The NVIDIA Tegra 3 based Colibri T30
> module can be used on this carrier board, hence enable those
> drivers in tegra_defonfig.
> 
> Furthermore the NVIDIA Tegra 3 based Apalis T30 module too
> contains two MCP251x CAN controller.

I already applied v1 of this one patch.

Re: [PATCH v2 3/3] ARM: tegra: initial add of Colibri T30

[Stephen Warren]

On 05/14/2014 03:45 PM, stefan@agner.ch wrote:
> From: Stefan Agner <stefan@agner.ch>
> 
> This patch adds the device tree to support Toradex Colibri T30, a
> computer on module which can be used on different carrier boards.
> 
> The module consists of a Tegra 30 SoC, two PMIC, DDR3L RAM, eMMC,
> a LM95245 temperature sensor and an AX88772B USB Ethernet
> Controller. Furthermore, there is a STMPE811 and SGTL5000 audio
> codec which are not yet supported. Anything that is not self
> contained on the module is disabled by default.
> 
> The device tree for the Evaluation Board includes the modules
> device tree and enables the supported pheripherials of the carrier
> board (the Evaluation Board supports almost all of them).

I've applied this to Tegra's for-3.16/dt branch.

A changelog in each individual patch would be useful. Splitting out
patches for the DRM tree and the Tegra tree into different series would
be useful. In this case, they don't depend on each-other.