[PATCH v6 0/7] Add JH7110 USB and USB PHY driver support

[PATCH v6 0/7] Add JH7110 USB and USB PHY driver support

[Minda Chen]

This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
The patch has been tested on the VisionFive 2 board.

This patchset should be applied after the patchset [1], [2] and [3]:
[1] https://patchwork.kernel.org/project/linux-riscv/cover/20230518101234.143748-1-xingyu.wu@starfivetech.com/
[2] https://patchwork.kernel.org/project/linux-clk/cover/20230512022036.97987-1-xingyu.wu@starfivetech.com
[3] https://patchwork.kernel.org/project/linux-phy/cover/20230412084540.295411-1-changhuang.liang@starfivetech.com/

This patchset is base on v6.4-rc1

patch 1 is usb phy dt-binding document.
patch 2 is Pcie PHY dt-binding document.
patch 3 is USB 2.0 PHY driver.
patch 4 is PCIe PHY driver.
patch 5 is usb dt-binding document.
patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
patch 7 is USB device tree configuration.

previous version
---
version 1 patchset are split to different kernel organization. It is
incorrect. But they were sent, and Emil sent comments. I think I should 
reserve them in cover-letter. To read the change records and previous version, 
please start with version 2. 

v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
v4: https://patchwork.kernel.org/project/linux-usb/cover/20230406015216.27034-1-minda.chen@starfivetech.com/
v5: https://patchwork.kernel.org/project/linux-usb/cover/20230420110052.3182-1-minda.chen@starfivetech.com/

changes
v6:
  1. (patch 3) remove the platform remove function.
  2. (patch 4)
     - add switch to pcie mode function.
     - remove the redundant init/exit function.
  3. (patch 5)
     - dts split to wrapper layer and cdns node. The codes are
       like v3.
     - add cdns3 sub node dts-binding references.
  4. (patch 6)
     For stg-syscon iomem 0x10240000 - 0x10240010 actually is belonged
     to usb, so USB contain its own registers. So do not merge the dts node.
     The codes are like v3.
     - remove the cdns3_platform_add function.
     - remove phy ops because cdns3 contain all the phy ops.
     - runtime suspend function just shutdown the clocks.
  5. (patch 7)
     - add cdns3 subnode again.

v5:
  1. (patch 1) set correct model name and commit title.
  2. (patch 2) change to '-item' in syscon property. change commit title.
  3. (patch 5)
     - change to '-item' in syscon configure.
     - change commit title and doc title.
  4. (patch 6)
     - add clk and phy deinit function
     - add clk deinit function if phy init failed.
     - coding style changes and other format changes. 

v4:
  1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
  2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
  3. (patch 3)
     - split PCIe PHY driver to patch 4.
     - replace dr_mode to phy mode in jh7110_usb2_phy.
  4. (patch 4) 
     - Makefile and Kconfig sorted by alphabet sequence.
     - Add PCIe PHY stg and syscon PHY connection configuration
       for USB 3.0.
  5. (patch 5)
     - commit message changed.
     - merge wrapper dts node and cdns3 node in example.
     - Add interrupts, reg, phy and dr_mode in property.
     - Add reset-name in property example.
  6. (patch 6)
     - For dts node is merged, Using platform_device_alloc and
       platform_device_add to generate cadence sub device.
     - IOMEM and IRQ resource are passed to Cadence sub device.
     - Add PHY ops process for PHY dts setting can not be passed to
       Cadence USB driver.
     - remove the stg and sys USB 3.0 PHY configuration.
     - Change the suspend clock reset and clock enable sequence.
     - Get all reset and clock resources before enable them in 
       cdns_clk_rst_init.
     - commit message changed.
  7. (patch 7)
     - merge wrapper dts node and cdns3 node in usb dts.
     - move the stg and sys USB 3.0 PHY confiuration to
       PCIe PHY dts node.
     - commit message changed.
     - Add reset-names dts.

v3:
  1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc. 
     USB PHY codes are moved to patch 3 and patch 4.
  2. (patch 5)
     - USB wrapper module dts document is moved to usb directory.
     - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
     - Some dts format changes. dts binding check pass.
  3. (patch 6)
     - Remove the PHY codes. 
     - Search 'dr_mode' and phy setting from Cadence subnode.
  4. (patch 7)
     - Add USB PHY dts configurion. 
     - 'dr_mode' is moved to Cadence controller submode.

v2:
  1. (patch 5) dt-binding changes. The document example is the same as dts config.
  2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
  3. (patch 7) dts nodes sorted by the address after @

Minda Chen (7):
  dt-bindings: phy: Add StarFive JH7110 USB PHY
  dt-bindings: phy: Add StarFive JH7110 PCIe PHY
  phy: starfive: Add JH7110 USB 2.0 PHY driver
  phy: starfive: Add JH7110 PCIE 2.0 PHY driver
  dt-bindings: usb: Add StarFive JH7110 USB controller
  usb: cdns3: Add StarFive JH7110 USB driver
  riscv: dts: starfive: Add USB dts configuration for JH7110

 .../phy/starfive,jh7110-pcie-phy.yaml         |  58 +++++
 .../bindings/phy/starfive,jh7110-usb-phy.yaml |  50 ++++
 .../bindings/usb/starfive,jh7110-usb.yaml     | 115 ++++++++
 MAINTAINERS                                   |  14 +
 .../jh7110-starfive-visionfive-2.dtsi         |   5 +
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  53 ++++
 drivers/phy/starfive/Kconfig                  |  21 ++
 drivers/phy/starfive/Makefile                 |   2 +
 drivers/phy/starfive/phy-jh7110-pcie.c        | 204 +++++++++++++++
 drivers/phy/starfive/phy-jh7110-usb.c         | 150 +++++++++++
 drivers/usb/cdns3/Kconfig                     |  11 +
 drivers/usb/cdns3/Makefile                    |   1 +
 drivers/usb/cdns3/cdns3-starfive.c            | 246 ++++++++++++++++++
 13 files changed, 930 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
 create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
 create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c


base-commit: ac9a78681b921877518763ba0e89202254349d1b
-- 
2.17.1

[PATCH v6 1/7] dt-bindings: phy: Add StarFive JH7110 USB PHY

[Minda Chen]

Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
new file mode 100644
index 000000000000..269e9f9f12b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 USB 2.0 PHY
+
+maintainers:
+  - Minda Chen <minda.chen@starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-usb-phy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  clocks:
+    items:
+      - description: PHY 125m
+      - description: app 125m
+
+  clock-names:
+    items:
+      - const: 125m
+      - const: app_125m
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    phy@10200000 {
+        compatible = "starfive,jh7110-usb-phy";
+        reg = <0x10200000 0x10000>;
+        clocks = <&syscrg 95>,
+                 <&stgcrg 6>;
+        clock-names = "125m", "app_125m";
+        #phy-cells = <0>;
+    };
-- 
2.17.1

[PATCH v6 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe PHY

[Minda Chen]

Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../phy/starfive,jh7110-pcie-phy.yaml         | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
new file mode 100644
index 000000000000..2e83a6164cd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 PCIe 2.0 PHY
+
+maintainers:
+  - Minda Chen <minda.chen@starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-pcie-phy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  starfive,sys-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to System Register Controller sys_syscon node.
+          - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
+    description:
+      The phandle to System Register Controller syscon node and the PHY connect offset
+      of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
+
+  starfive,stg-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to System Register Controller stg_syscon node.
+          - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
+          - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
+    description:
+      The phandle to System Register Controller syscon node and the offset
+      of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    phy@10210000 {
+        compatible = "starfive,jh7110-pcie-phy";
+        reg = <0x10210000 0x10000>;
+        #phy-cells = <0>;
+        starfive,sys-syscon = <&sys_syscon 0x18>;
+        starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
+    };
-- 
2.17.1

[PATCH v6 3/7] phy: starfive: Add JH7110 USB 2.0 PHY driver

[Minda Chen]

Add Starfive JH7110 SoC USB 2.0 PHY driver support.
USB 2.0 PHY default connect to Cadence USB controller.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 MAINTAINERS                           |   6 ++
 drivers/phy/starfive/Kconfig          |  11 ++
 drivers/phy/starfive/Makefile         |   1 +
 drivers/phy/starfive/phy-jh7110-usb.c | 150 ++++++++++++++++++++++++++
 4 files changed, 168 insertions(+)
 create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 0606ed87cf1c..b900f661c2e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20160,6 +20160,12 @@ S:	Supported
 F:	Documentation/devicetree/bindings/watchdog/starfive*
 F:	drivers/watchdog/starfive-wdt.c
 
+STARFIVE JH71X0 USB PHY DRIVER
+M:	Minda Chen <minda.chen@starfivetech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
+F:	drivers/phy/starfive/phy-jh7110-usb.c
+
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
 M:	Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index f989b8ff8bcb..2c013c390dee 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -11,3 +11,14 @@ config PHY_STARFIVE_DPHY_RX
 	  Choose this option if you have a StarFive D-PHY in your
 	  system. If M is selected, the module will be called
 	  phy-starfive-dphy-rx.
+
+config PHY_STARFIVE_JH7110_USB
+	tristate "Starfive JH7110 USB 2.0 PHY support"
+	depends on USB_SUPPORT
+	select GENERIC_PHY
+	select USB_PHY
+	help
+	  Enable this to support the StarFive USB 2.0 PHY,
+	  used with the Cadence USB controller.
+	  If M is selected, the module will be called
+	  phy-jh7110-usb.ko.
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index 7ec576cb30ae..176443852f4d 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_STARFIVE_DPHY_RX)      += phy-starfive-dphy-rx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB)	+= phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c
new file mode 100644
index 000000000000..90d788423705
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/usb/of.h>
+
+#define USB_125M_CLK_RATE		125000000
+#define USB_LS_KEEPALIVE_OFF		0x4
+#define USB_LS_KEEPALIVE_ENABLE		BIT(4)
+
+struct jh7110_usb2_phy {
+	struct phy *phy;
+	void __iomem *regs;
+	struct clk *usb_125m_clk;
+	struct clk *app_125m;
+	enum phy_mode mode;
+};
+
+static void jh7110_usb2_mode_set(struct jh7110_usb2_phy *phy)
+{
+	unsigned int val;
+
+	if (phy->mode != PHY_MODE_USB_HOST) {
+		/* Enable the LS speed keep-alive signal */
+		val = readl(phy->regs + USB_LS_KEEPALIVE_OFF);
+		val |= USB_LS_KEEPALIVE_ENABLE;
+		writel(val, phy->regs + USB_LS_KEEPALIVE_OFF);
+	}
+}
+
+static int jh7110_usb2_phy_set_mode(struct phy *_phy,
+				    enum phy_mode mode, int submode)
+{
+	struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+
+	switch (mode) {
+	case PHY_MODE_USB_HOST:
+	case PHY_MODE_USB_DEVICE:
+	case PHY_MODE_USB_OTG:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (mode != phy->mode) {
+		dev_dbg(&_phy->dev, "Changing phy to %d\n", mode);
+		phy->mode = mode;
+		jh7110_usb2_mode_set(phy);
+	}
+
+	return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+	struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+
+	ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(phy->app_125m);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+	struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+
+	clk_disable_unprepare(phy->app_125m);
+
+	return 0;
+}
+
+static const struct phy_ops jh7110_usb2_phy_ops = {
+	.init		= jh7110_usb2_phy_init,
+	.exit		= jh7110_usb2_phy_exit,
+	.set_mode	= jh7110_usb2_phy_set_mode,
+	.owner		= THIS_MODULE,
+};
+
+static int jh7110_usb_phy_probe(struct platform_device *pdev)
+{
+	struct jh7110_usb2_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *phy_provider;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	phy->usb_125m_clk = devm_clk_get(dev, "125m");
+	if (IS_ERR(phy->usb_125m_clk))
+		return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk),
+			"Failed to get 125m clock\n");
+
+	phy->app_125m = devm_clk_get(dev, "app_125m");
+	if (IS_ERR(phy->app_125m))
+		return dev_err_probe(dev, PTR_ERR(phy->app_125m),
+			"Failed to get app 125m clock\n");
+
+	phy->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(phy->regs))
+		return dev_err_probe(dev, PTR_ERR(phy->regs),
+			"Failed to map phy base\n");
+
+	phy->phy = devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops);
+	if (IS_ERR(phy->phy))
+		return dev_err_probe(dev, PTR_ERR(phy->phy),
+			"Failed to create phy\n");
+
+	phy_set_drvdata(phy->phy, phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id jh7110_usb_phy_of_match[] = {
+	{ .compatible = "starfive,jh7110-usb-phy" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match);
+
+static struct platform_driver jh7110_usb_phy_driver = {
+	.probe	= jh7110_usb_phy_probe,
+	.driver = {
+		.of_match_table	= jh7110_usb_phy_of_match,
+		.name  = "jh7110-usb-phy",
+	}
+};
+module_platform_driver(jh7110_usb_phy_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver");
+MODULE_AUTHOR("Minda Chen <minda.chen@starfivetech.com>");
+MODULE_LICENSE("GPL");
-- 
2.17.1

[PATCH v6 4/7] phy: starfive: Add JH7110 PCIE 2.0 PHY driver

[Minda Chen]

Add Starfive JH7110 SoC PCIe 2.0 PHY driver support.
PCIe 2.0 PHY default connect to PCIe controller.
PCIe PHY can connect to USB 3.0 controller.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 MAINTAINERS                            |   4 +-
 drivers/phy/starfive/Kconfig           |  10 ++
 drivers/phy/starfive/Makefile          |   1 +
 drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++++++++++++
 4 files changed, 218 insertions(+), 1 deletion(-)
 create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c

diff --git a/MAINTAINERS b/MAINTAINERS
index b900f661c2e0..5519f81c8296 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20160,10 +20160,12 @@ S:	Supported
 F:	Documentation/devicetree/bindings/watchdog/starfive*
 F:	drivers/watchdog/starfive-wdt.c
 
-STARFIVE JH71X0 USB PHY DRIVER
+STARFIVE JH71X0 PCIE AND USB PHY DRIVER
 M:	Minda Chen <minda.chen@starfivetech.com>
 S:	Supported
+F:	Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
 F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
+F:	drivers/phy/starfive/phy-jh7110-pcie.c
 F:	drivers/phy/starfive/phy-jh7110-usb.c
 
 STATIC BRANCH/CALL
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index 2c013c390dee..38eb0c0c8e91 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -12,6 +12,16 @@ config PHY_STARFIVE_DPHY_RX
 	  system. If M is selected, the module will be called
 	  phy-starfive-dphy-rx.
 
+config PHY_STARFIVE_JH7110_PCIE
+	tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
+	select GENERIC_PHY
+	select USB_PHY
+	help
+	  Enable this to support the StarFive PCIe 2.0 PHY,
+	  or used as USB 3.0 PHY.
+	  If M is selected, the module will be called
+	  phy-jh7110-pcie.ko.
+
 config PHY_STARFIVE_JH7110_USB
 	tristate "Starfive JH7110 USB 2.0 PHY support"
 	depends on USB_SUPPORT
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index 176443852f4d..03a55aad53a2 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_STARFIVE_DPHY_RX)      += phy-starfive-dphy-rx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE)	+= phy-jh7110-pcie.o
 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB)	+= phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 000000000000..cbe79c1f59d3
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define PCIE_KVCO_LEVEL_OFF		0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF	0x7c
+#define PCIE_KVCO_TUNE_SIGNAL_OFF	0x80
+#define PCIE_USB3_PHY_ENABLE		BIT(4)
+#define PHY_KVCO_FINE_TUNE_LEVEL	0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS	0xc
+
+#define USB_PDRSTN_SPLIT		BIT(17)
+
+#define PCIE_PHY_MODE			BIT(20)
+#define PCIE_PHY_MODE_MASK		GENMASK(21, 20)
+#define PCIE_USB3_BUS_WIDTH_MASK	GENMASK(3, 2)
+#define PCIE_USB3_BUS_WIDTH		BIT(3)
+#define PCIE_USB3_RATE_MASK		GENMASK(6, 5)
+#define PCIE_USB3_RX_STANDBY_MASK	BIT(7)
+#define PCIE_USB3_PHY_ENABLE		BIT(4)
+
+struct jh7110_pcie_phy {
+	struct phy *phy;
+	struct regmap *stg_syscon;
+	struct regmap *sys_syscon;
+	void __iomem *regs;
+	u32 sys_phy_connect;
+	u32 stg_pcie_mode;
+	u32 stg_pcie_usb;
+	enum phy_mode mode;
+};
+
+static int phy_usb3_mode_set(struct jh7110_pcie_phy *data)
+{
+	if (!data->stg_syscon || !data->sys_syscon) {
+		dev_err(&data->phy->dev, "doesn't support usb3 mode\n");
+		return -EINVAL;
+	}
+
+	regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
+			   PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
+	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+			   PCIE_USB3_BUS_WIDTH_MASK, 0);
+	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+			   PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
+
+	/* Connect usb 3.0 phy mode */
+	regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
+			   USB_PDRSTN_SPLIT, 0);
+
+	/* Configuare spread-spectrum mode: down-spread-spectrum */
+	writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
+
+	return 0;
+}
+
+static void phy_pcie_mode_set(struct jh7110_pcie_phy *data)
+{
+	u32 val;
+
+	/* default is PCIe mode */
+	if (!data->stg_syscon || !data->sys_syscon)
+		return;
+
+	regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
+			   PCIE_PHY_MODE_MASK, 0);
+	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+			   PCIE_USB3_BUS_WIDTH_MASK,
+			   PCIE_USB3_BUS_WIDTH);
+	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+			   PCIE_USB3_PHY_ENABLE, 0);
+
+	regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
+			   USB_PDRSTN_SPLIT, 0);
+
+	val = readl(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
+	val &= ~PCIE_USB3_PHY_ENABLE;
+	writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+	/* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+	writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+	writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+				    enum phy_mode mode, int submode)
+{
+	struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+
+	if (mode == phy->mode)
+		return 0;
+
+	switch (mode) {
+	case PHY_MODE_USB_HOST:
+	case PHY_MODE_USB_DEVICE:
+	case PHY_MODE_USB_OTG:
+		ret = phy_usb3_mode_set(phy);
+		if (ret)
+			return ret;
+		break;
+	case PHY_MODE_PCIE:
+		phy_pcie_mode_set(phy);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	dev_dbg(&_phy->dev, "Changing phy mode to %d\n", mode);
+	phy->mode = mode;
+
+	return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+	.set_mode	= jh7110_pcie_phy_set_mode,
+	.owner		= THIS_MODULE,
+};
+
+static int jh7110_pcie_phy_probe(struct platform_device *pdev)
+{
+	struct jh7110_pcie_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *phy_provider;
+	u32 args[2];
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	phy->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(phy->regs))
+		return PTR_ERR(phy->regs);
+
+	phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops);
+	if (IS_ERR(phy->phy))
+		return dev_err_probe(dev, PTR_ERR(phy->regs),
+				     "Failed to map phy base\n");
+
+	phy->sys_syscon =
+		syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+						     "starfive,sys-syscon",
+						     1, args);
+
+	if (!IS_ERR_OR_NULL(phy->sys_syscon))
+		phy->sys_phy_connect = args[0];
+	else
+		phy->sys_syscon = NULL;
+
+	phy->stg_syscon =
+		syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+						     "starfive,stg-syscon",
+						     2, args);
+
+	if (!IS_ERR_OR_NULL(phy->stg_syscon)) {
+		phy->stg_pcie_mode = args[0];
+		phy->stg_pcie_usb = args[1];
+	} else {
+		phy->stg_syscon = NULL;
+	}
+
+	phy_kvco_gain_set(phy);
+
+	phy_set_drvdata(phy->phy, phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id jh7110_pcie_phy_of_match[] = {
+	{ .compatible = "starfive,jh7110-pcie-phy" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match);
+
+static struct platform_driver jh7110_pcie_phy_driver = {
+	.probe	= jh7110_pcie_phy_probe,
+	.driver = {
+		.of_match_table	= jh7110_pcie_phy_of_match,
+		.name  = "jh7110-pcie-phy",
+	}
+};
+module_platform_driver(jh7110_pcie_phy_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver");
+MODULE_AUTHOR("Minda Chen <minda.chen@starfivetech.com>");
+MODULE_LICENSE("GPL");
-- 
2.17.1

[PATCH v6 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller

[Minda Chen]

StarFive JH7110 platforms USB have a wrapper module around
the Cadence USBSS-DRD controller. Add binding information doc
for that.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Peter Chen <peter.chen@kernel.org>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../bindings/usb/starfive,jh7110-usb.yaml     | 115 ++++++++++++++++++
 1 file changed, 115 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml

diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
new file mode 100644
index 000000000000..24aa9c10d6ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
+
+maintainers:
+  - Minda Chen <minda.chen@starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-usb
+
+  ranges: true
+
+  starfive,stg-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to System Register Controller stg_syscon node.
+          - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
+    description:
+      The phandle to System Register Controller syscon node and the offset
+      of STG_SYSCONSAIF__SYSCFG register for USB.
+
+  dr_mode:
+    enum: [host, otg, peripheral]
+
+  "#address-cells":
+    enum: [1, 2]
+
+  "#size-cells":
+    enum: [1, 2]
+
+  clocks:
+    items:
+      - description: link power management clock
+      - description: standby clock
+      - description: APB clock
+      - description: AXI clock
+      - description: UTMI APB clock
+
+  clock-names:
+    items:
+      - const: lpm
+      - const: stb
+      - const: apb
+      - const: axi
+      - const: utmi_apb
+
+  resets:
+    items:
+      - description: Power up reset
+      - description: APB clock reset
+      - description: AXI clock reset
+      - description: UTMI APB clock reset
+
+  reset-names:
+    items:
+      - const: pwrup
+      - const: apb
+      - const: axi
+      - const: utmi_apb
+
+patternProperties:
+  "^usb@[0-9a-f]+$":
+    $ref: cdns,usb3.yaml#
+    description: Required child node
+
+required:
+  - compatible
+  - ranges
+  - starfive,stg-syscon
+  - '#address-cells'
+  - '#size-cells'
+  - dr_mode
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    usb@10100000 {
+        compatible = "starfive,jh7110-usb";
+        ranges = <0x0 0x10100000 0x100000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        starfive,stg-syscon = <&stg_syscon 0x4>;
+        clocks = <&syscrg 4>,
+                 <&stgcrg 5>,
+                 <&stgcrg 1>,
+                 <&stgcrg 3>,
+                 <&stgcrg 2>;
+        clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+        resets = <&stgcrg 10>,
+                 <&stgcrg 8>,
+                 <&stgcrg 7>,
+                 <&stgcrg 9>;
+        reset-names = "pwrup", "apb", "axi", "utmi_apb";
+        dr_mode = "host";
+
+        usb@0 {
+            compatible = "cdns,usb3";
+            reg = <0x0 0x10000>,
+                  <0x10000 0x10000>,
+                  <0x20000 0x10000>;
+            reg-names = "otg", "xhci", "dev";
+            interrupts = <100>, <108>, <110>;
+            interrupt-names = "host", "peripheral", "otg";
+            maximum-speed = "super-speed";
+        };
+    };
-- 
2.17.1

[PATCH v6 6/7] usb: cdns3: Add StarFive JH7110 USB driver

[Minda Chen]

Adds Specific Glue layer to support USB peripherals on
StarFive JH7110 SoC.
There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child of this USB wrapper module device.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Acked-by: Peter Chen <peter.chen@kernel.org>
---
 MAINTAINERS                        |   6 +
 drivers/usb/cdns3/Kconfig          |  11 ++
 drivers/usb/cdns3/Makefile         |   1 +
 drivers/usb/cdns3/cdns3-starfive.c | 246 +++++++++++++++++++++++++++++
 4 files changed, 264 insertions(+)
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5519f81c8296..06c63f43bb17 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20168,6 +20168,12 @@ F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
 F:	drivers/phy/starfive/phy-jh7110-pcie.c
 F:	drivers/phy/starfive/phy-jh7110-usb.c
 
+STARFIVE JH71X0 USB DRIVERS
+M:	Minda Chen <minda.chen@starfivetech.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
+F:	drivers/usb/cdns3/cdns3-starfive.c
+
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
 M:	Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index b98ca0a1352a..0a514b591527 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -78,6 +78,17 @@ config USB_CDNS3_IMX
 
 	  For example, imx8qm and imx8qxp.
 
+config USB_CDNS3_STARFIVE
+	tristate "Cadence USB3 support on StarFive SoC platforms"
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	help
+	  Say 'Y' or 'M' here if you are building for StarFive SoCs
+	  platforms that contain Cadence USB3 controller core.
+
+	  e.g. JH7110.
+
+	  If you choose to build this driver as module it will
+	  be dynamically linked and module will be called cdns3-starfive.ko
 endif
 
 if USB_CDNS_SUPPORT
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 61edb2f89276..48dfae75b5aa 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -24,6 +24,7 @@ endif
 obj-$(CONFIG_USB_CDNS3_PCI_WRAP)		+= cdns3-pci-wrap.o
 obj-$(CONFIG_USB_CDNS3_TI)			+= cdns3-ti.o
 obj-$(CONFIG_USB_CDNS3_IMX)			+= cdns3-imx.o
+obj-$(CONFIG_USB_CDNS3_STARFIVE)		+= cdns3-starfive.o
 
 cdnsp-udc-pci-y					:= cdnsp-pci.o
 
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 000000000000..fc1f003b145d
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author:	Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/usb/otg.h>
+#include "core.h"
+
+#define USB_STRAP_HOST			BIT(17)
+#define USB_STRAP_DEVICE		BIT(18)
+#define USB_STRAP_MASK			GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST		BIT(19)
+#define USB_SUSPENDM_MASK		BIT(19)
+
+#define USB_MISC_CFG_MASK		GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS		BIT(20)
+#define USB_PLL_EN			BIT(22)
+#define USB_REFCLK_MODE			BIT(23)
+
+struct cdns_starfive {
+	struct device *dev;
+	struct regmap *stg_syscon;
+	struct reset_control *resets;
+	struct clk_bulk_data *clks;
+	int num_clks;
+	u32 stg_usb_mode;
+};
+
+static void cdns_mode_init(struct platform_device *pdev,
+			   struct cdns_starfive *data)
+{
+	enum usb_dr_mode mode;
+
+	regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+			   USB_MISC_CFG_MASK,
+			   USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+	/* dr mode setting */
+	mode = usb_get_dr_mode(&pdev->dev);
+
+	switch (mode) {
+	case USB_DR_MODE_HOST:
+		regmap_update_bits(data->stg_syscon,
+				   data->stg_usb_mode,
+				   USB_STRAP_MASK,
+				   USB_STRAP_HOST);
+		regmap_update_bits(data->stg_syscon,
+				   data->stg_usb_mode,
+				   USB_SUSPENDM_MASK,
+				   USB_SUSPENDM_HOST);
+		break;
+
+	case USB_DR_MODE_PERIPHERAL:
+		regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+				   USB_STRAP_MASK, USB_STRAP_DEVICE);
+		regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+				   USB_SUSPENDM_MASK, 0);
+		break;
+	default:
+		break;
+	}
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+	int ret;
+
+	ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+	if (ret)
+		return dev_err_probe(data->dev, ret,
+				     "failed to enable clocks\n");
+
+	ret = reset_control_deassert(data->resets);
+	if (ret) {
+		dev_err(data->dev, "failed to reset clocks\n");
+		goto err_clk_init;
+	}
+
+	return ret;
+
+err_clk_init:
+	clk_bulk_disable_unprepare(data->num_clks, data->clks);
+	return ret;
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+	reset_control_assert(data->resets);
+	clk_bulk_disable_unprepare(data->num_clks, data->clks);
+}
+
+static int cdns_starfive_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cdns_starfive *data;
+	unsigned int args;
+	int ret;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->dev = dev;
+
+	data->stg_syscon =
+		syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+						     "starfive,stg-syscon", 1, &args);
+
+	if (IS_ERR(data->stg_syscon))
+		return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
+				     "Failed to parse starfive,stg-syscon\n");
+
+	data->stg_usb_mode = args;
+
+	data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
+	if (data->num_clks < 0)
+		return dev_err_probe(data->dev, -ENODEV,
+				     "Failed to get clocks\n");
+
+	data->resets = devm_reset_control_array_get_exclusive(data->dev);
+	if (IS_ERR(data->resets))
+		return dev_err_probe(data->dev, PTR_ERR(data->resets),
+				     "Failed to get resets");
+
+	cdns_mode_init(pdev, data);
+	ret = cdns_clk_rst_init(data);
+	if (ret)
+		return ret;
+
+	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
+	if (ret) {
+		dev_err(dev, "Failed to create children\n");
+		cdns_clk_rst_deinit(data);
+		return ret;
+	}
+
+	device_set_wakeup_capable(dev, true);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static int cdns_starfive_remove_core(struct device *dev, void *c)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	platform_device_unregister(pdev);
+
+	return 0;
+}
+
+static int cdns_starfive_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	pm_runtime_get_sync(dev);
+	device_for_each_child(dev, NULL, cdns_starfive_remove_core);
+
+	pm_runtime_disable(dev);
+	pm_runtime_put_noidle(dev);
+	cdns_clk_rst_deinit(data);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int cdns_starfive_runtime_resume(struct device *dev)
+{
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	return clk_bulk_prepare_enable(data->num_clks, data->clks);
+}
+
+static int cdns_starfive_runtime_suspend(struct device *dev)
+{
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	clk_bulk_disable_unprepare(data->num_clks, data->clks);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int cdns_starfive_resume(struct device *dev)
+{
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	return cdns_clk_rst_init(data);
+}
+
+static int cdns_starfive_suspend(struct device *dev)
+{
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	cdns_clk_rst_deinit(data);
+
+	return 0;
+}
+#endif
+#endif
+
+static const struct dev_pm_ops cdns_starfive_pm_ops = {
+	SET_RUNTIME_PM_OPS(cdns_starfive_runtime_suspend,
+			   cdns_starfive_runtime_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
+};
+
+static const struct of_device_id cdns_starfive_of_match[] = {
+	{ .compatible = "starfive,jh7110-usb", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
+
+static struct platform_driver cdns_starfive_driver = {
+	.probe		= cdns_starfive_probe,
+	.remove		= cdns_starfive_remove,
+	.driver		= {
+		.name	= "cdns3-starfive",
+		.of_match_table	= cdns_starfive_of_match,
+		.pm	= &cdns_starfive_pm_ops,
+	},
+};
+module_platform_driver(cdns_starfive_driver);
+
+MODULE_ALIAS("platform:cdns3-starfive");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
-- 
2.17.1

[PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration for JH7110

[Minda Chen]

Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.
USB controller connect to PHY, The PHY dts configuration
are also added.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2.dtsi         |  5 ++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 53 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 1155b97b593d..934453bc80d5 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -221,3 +221,8 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&usb0 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 71a8e9acbe55..b65f06c5b1b7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -366,6 +366,59 @@
 			status = "disabled";
 		};
 
+		usb0: usb@10100000 {
+			compatible = "starfive,jh7110-usb";
+			ranges = <0x0 0x0 0x10100000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			starfive,stg-syscon = <&stg_syscon 0x4>;
+			clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
+				 <&stgcrg JH7110_STGCLK_USB0_STB>,
+				 <&stgcrg JH7110_STGCLK_USB0_APB>,
+				 <&stgcrg JH7110_STGCLK_USB0_AXI>,
+				 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
+			clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+			resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
+				 <&stgcrg JH7110_STGRST_USB0_APB>,
+				 <&stgcrg JH7110_STGRST_USB0_AXI>,
+				 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
+			reset-names = "pwrup", "apb", "axi", "utmi_apb";
+			status = "disabled";
+
+			usb_cdns3: usb@0 {
+				compatible = "cdns,usb3";
+				reg = <0x0 0x10000>,
+				      <0x10000 0x10000>,
+				      <0x20000 0x10000>;
+				reg-names = "otg", "xhci", "dev";
+				interrupts = <100>, <108>, <110>;
+				interrupt-names = "host", "peripheral", "otg";
+				phys = <&usbphy0>;
+				phy-names = "cdns3,usb2-phy";
+			};
+		};
+
+		usbphy0: phy@10200000 {
+			compatible = "starfive,jh7110-usb-phy";
+			reg = <0x0 0x10200000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+			clock-names = "125m", "app_125m";
+			#phy-cells = <0>;
+		};
+
+		pciephy0: phy@10210000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@10220000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		stgcrg: clock-controller@10230000 {
 			compatible = "starfive,jh7110-stgcrg";
 			reg = <0x0 0x10230000 0x0 0x10000>;
-- 
2.17.1

Re: [PATCH v6 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller

[Conor Dooley]

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On Thu, May 18, 2023 at 07:27:48PM +0800, Minda Chen wrote:
> StarFive JH7110 platforms USB have a wrapper module around
> the Cadence USBSS-DRD controller. Add binding information doc
> for that.
> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> Reviewed-by: Peter Chen <peter.chen@kernel.org>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../bindings/usb/starfive,jh7110-usb.yaml     | 115 ++++++++++++++++++
>  1 file changed, 115 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> new file mode 100644
> index 000000000000..24aa9c10d6ab
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller

I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
USBSS-DRD SoC controller"?

Otherwise, it looks like all the stuff from him and Rob have been sorted
out, so other than $title this is
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor..

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Re: [PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration for JH7110

[Conor Dooley]

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Greg,

On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote:
> Add USB wrapper layer and Cadence USB3 controller dts
> configuration for StarFive JH7110 SoC and VisionFive2
> Board.
> USB controller connect to PHY, The PHY dts configuration
> are also added.
> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 71a8e9acbe55..b65f06c5b1b7 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -366,6 +366,59 @@
>  			status = "disabled";
>  		};
>  
> +		usb0: usb@10100000 {
> +			compatible = "starfive,jh7110-usb";
> +			ranges = <0x0 0x0 0x10100000 0x100000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			starfive,stg-syscon = <&stg_syscon 0x4>;
> +			clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,

Please don't pick this patch, if the rest of the series is applicable,
as this will break building the dtb as stgcrg does not yet exist in any
maintainer tree.

Thanks,
Conor.

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Re: [PATCH v6 0/7] Add JH7110 USB and USB PHY driver support

[Roger Quadros]

On 18/05/2023 14:27, Minda Chen wrote:
> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
> The patch has been tested on the VisionFive 2 board.
> 
> This patchset should be applied after the patchset [1], [2] and [3]:
> [1] https://patchwork.kernel.org/project/linux-riscv/cover/20230518101234.143748-1-xingyu.wu@starfivetech.com/
> [2] https://patchwork.kernel.org/project/linux-clk/cover/20230512022036.97987-1-xingyu.wu@starfivetech.com
> [3] https://patchwork.kernel.org/project/linux-phy/cover/20230412084540.295411-1-changhuang.liang@starfivetech.com/
> 
> This patchset is base on v6.4-rc1
> 
> patch 1 is usb phy dt-binding document.
> patch 2 is Pcie PHY dt-binding document.
> patch 3 is USB 2.0 PHY driver.
> patch 4 is PCIe PHY driver.
> patch 5 is usb dt-binding document.
> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
> patch 7 is USB device tree configuration.
> 
> previous version
> ---
> version 1 patchset are split to different kernel organization. It is
> incorrect. But they were sent, and Emil sent comments. I think I should 
> reserve them in cover-letter. To read the change records and previous version, 
> please start with version 2. 
> 
> v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
> v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
> v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
> v4: https://patchwork.kernel.org/project/linux-usb/cover/20230406015216.27034-1-minda.chen@starfivetech.com/
> v5: https://patchwork.kernel.org/project/linux-usb/cover/20230420110052.3182-1-minda.chen@starfivetech.com/
> 
> changes
> v6:
>   1. (patch 3) remove the platform remove function.
>   2. (patch 4)
>      - add switch to pcie mode function.
>      - remove the redundant init/exit function.
>   3. (patch 5)
>      - dts split to wrapper layer and cdns node. The codes are
>        like v3.
>      - add cdns3 sub node dts-binding references.
>   4. (patch 6)
>      For stg-syscon iomem 0x10240000 - 0x10240010 actually is belonged
>      to usb, so USB contain its own registers. So do not merge the dts node.
>      The codes are like v3.
>      - remove the cdns3_platform_add function.
>      - remove phy ops because cdns3 contain all the phy ops.
>      - runtime suspend function just shutdown the clocks.
>   5. (patch 7)
>      - add cdns3 subnode again.
> 
> v5:
>   1. (patch 1) set correct model name and commit title.
>   2. (patch 2) change to '-item' in syscon property. change commit title.
>   3. (patch 5)
>      - change to '-item' in syscon configure.
>      - change commit title and doc title.
>   4. (patch 6)
>      - add clk and phy deinit function
>      - add clk deinit function if phy init failed.
>      - coding style changes and other format changes. 
> 
> v4:
>   1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>   2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>   3. (patch 3)
>      - split PCIe PHY driver to patch 4.
>      - replace dr_mode to phy mode in jh7110_usb2_phy.
>   4. (patch 4) 
>      - Makefile and Kconfig sorted by alphabet sequence.
>      - Add PCIe PHY stg and syscon PHY connection configuration
>        for USB 3.0.
>   5. (patch 5)
>      - commit message changed.
>      - merge wrapper dts node and cdns3 node in example.
>      - Add interrupts, reg, phy and dr_mode in property.
>      - Add reset-name in property example.
>   6. (patch 6)
>      - For dts node is merged, Using platform_device_alloc and
>        platform_device_add to generate cadence sub device.
>      - IOMEM and IRQ resource are passed to Cadence sub device.
>      - Add PHY ops process for PHY dts setting can not be passed to
>        Cadence USB driver.
>      - remove the stg and sys USB 3.0 PHY configuration.
>      - Change the suspend clock reset and clock enable sequence.
>      - Get all reset and clock resources before enable them in 
>        cdns_clk_rst_init.
>      - commit message changed.
>   7. (patch 7)
>      - merge wrapper dts node and cdns3 node in usb dts.
>      - move the stg and sys USB 3.0 PHY confiuration to
>        PCIe PHY dts node.
>      - commit message changed.
>      - Add reset-names dts.
> 
> v3:
>   1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc. 
>      USB PHY codes are moved to patch 3 and patch 4.
>   2. (patch 5)
>      - USB wrapper module dts document is moved to usb directory.
>      - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>      - Some dts format changes. dts binding check pass.
>   3. (patch 6)
>      - Remove the PHY codes. 
>      - Search 'dr_mode' and phy setting from Cadence subnode.
>   4. (patch 7)
>      - Add USB PHY dts configurion. 
>      - 'dr_mode' is moved to Cadence controller submode.
> 
> v2:
>   1. (patch 5) dt-binding changes. The document example is the same as dts config.
>   2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>   3. (patch 7) dts nodes sorted by the address after @
> 
> Minda Chen (7):
>   dt-bindings: phy: Add StarFive JH7110 USB PHY
>   dt-bindings: phy: Add StarFive JH7110 PCIe PHY
>   phy: starfive: Add JH7110 USB 2.0 PHY driver
>   phy: starfive: Add JH7110 PCIE 2.0 PHY driver
>   dt-bindings: usb: Add StarFive JH7110 USB controller
>   usb: cdns3: Add StarFive JH7110 USB driver
>   riscv: dts: starfive: Add USB dts configuration for JH7110
> 
>  .../phy/starfive,jh7110-pcie-phy.yaml         |  58 +++++
>  .../bindings/phy/starfive,jh7110-usb-phy.yaml |  50 ++++
>  .../bindings/usb/starfive,jh7110-usb.yaml     | 115 ++++++++
>  MAINTAINERS                                   |  14 +
>  .../jh7110-starfive-visionfive-2.dtsi         |   5 +
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      |  53 ++++
>  drivers/phy/starfive/Kconfig                  |  21 ++
>  drivers/phy/starfive/Makefile                 |   2 +
>  drivers/phy/starfive/phy-jh7110-pcie.c        | 204 +++++++++++++++
>  drivers/phy/starfive/phy-jh7110-usb.c         | 150 +++++++++++
>  drivers/usb/cdns3/Kconfig                     |  11 +
>  drivers/usb/cdns3/Makefile                    |   1 +
>  drivers/usb/cdns3/cdns3-starfive.c            | 246 ++++++++++++++++++
>  13 files changed, 930 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>  create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>  create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>  create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>  create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
> 

For this series:
Reviewed-by: Roger Quadros <rogerq@kernel.org>

Re: [PATCH v6 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller

[Minda Chen]

On 2023/5/26 5:34, Conor Dooley wrote:
> On Thu, May 18, 2023 at 07:27:48PM +0800, Minda Chen wrote:
>> StarFive JH7110 platforms USB have a wrapper module around
>> the Cadence USBSS-DRD controller. Add binding information doc
>> for that.
>> 
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> Reviewed-by: Peter Chen <peter.chen@kernel.org>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  .../bindings/usb/starfive,jh7110-usb.yaml     | 115 ++++++++++++++++++
>>  1 file changed, 115 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> new file mode 100644
>> index 000000000000..24aa9c10d6ab
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> @@ -0,0 +1,115 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
> 
> I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
> USBSS-DRD SoC controller"?
> 
The previous title describe whole USB controller for previous dts node is merged. Now the dts node is split. 
"starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
> Otherwise, it looks like all the stuff from him and Rob have been sorted
> out, so other than $title this is
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Thanks,
> Conor..
Thanks

Re: [PATCH v6 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 740 bytes --]

On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote:

> >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
> > 
> > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
> > USBSS-DRD SoC controller"?
> > 
> The previous title describe whole USB controller for previous dts node is
> merged. Now the dts node is split. 
> "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.

Okay, I must have misunderstood the conversation on the previous
version. Sorry about that.

> > Otherwise, it looks like all the stuff from him and Rob have been sorted
> > out, so other than $title this is
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


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Re: [PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration for JH7110

[Greg Kroah-Hartman]

On Thu, May 25, 2023 at 10:36:38PM +0100, Conor Dooley wrote:
> Greg,
> 
> On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote:
> > Add USB wrapper layer and Cadence USB3 controller dts
> > configuration for StarFive JH7110 SoC and VisionFive2
> > Board.
> > USB controller connect to PHY, The PHY dts configuration
> > are also added.
> > 
> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> 
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 71a8e9acbe55..b65f06c5b1b7 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -366,6 +366,59 @@
> >  			status = "disabled";
> >  		};
> >  
> > +		usb0: usb@10100000 {
> > +			compatible = "starfive,jh7110-usb";
> > +			ranges = <0x0 0x0 0x10100000 0x100000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			starfive,stg-syscon = <&stg_syscon 0x4>;
> > +			clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
> 
> Please don't pick this patch, if the rest of the series is applicable,
> as this will break building the dtb as stgcrg does not yet exist in any
> maintainer tree.

Ok, I'll just take patch 6/7 then.

thanks,

greg k-h

Re: [PATCH v6 6/7] usb: cdns3: Add StarFive JH7110 USB driver

[Greg Kroah-Hartman]

On Thu, May 18, 2023 at 07:27:49PM +0800, Minda Chen wrote:
> Adds Specific Glue layer to support USB peripherals on
> StarFive JH7110 SoC.
> There is a Cadence USB3 core for JH7110 SoCs, the cdns
> core is the child of this USB wrapper module device.
> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> Acked-by: Peter Chen <peter.chen@kernel.org>
> Reviewed-by: Roger Quadros <rogerq@kernel.org>
> ---
>  MAINTAINERS                        |   6 +
>  drivers/usb/cdns3/Kconfig          |  11 ++
>  drivers/usb/cdns3/Makefile         |   1 +
>  drivers/usb/cdns3/cdns3-starfive.c | 246 +++++++++++++++++++++++++++++
>  4 files changed, 264 insertions(+)
>  create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5519f81c8296..06c63f43bb17 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20168,6 +20168,12 @@ F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>  F:	drivers/phy/starfive/phy-jh7110-pcie.c
>  F:	drivers/phy/starfive/phy-jh7110-usb.c
>  
> +STARFIVE JH71X0 USB DRIVERS
> +M:	Minda Chen <minda.chen@starfivetech.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> +F:	drivers/usb/cdns3/cdns3-starfive.c

Does not apply anymore, please rebase and resend.

thanks,

greg k-h

Re: [PATCH v6 6/7] usb: cdns3: Add StarFive JH7110 USB driver

[Greg Kroah-Hartman]

On Mon, May 29, 2023 at 03:50:04PM +0100, Greg Kroah-Hartman wrote:
> On Thu, May 18, 2023 at 07:27:49PM +0800, Minda Chen wrote:
> > Adds Specific Glue layer to support USB peripherals on
> > StarFive JH7110 SoC.
> > There is a Cadence USB3 core for JH7110 SoCs, the cdns
> > core is the child of this USB wrapper module device.
> > 
> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > Acked-by: Peter Chen <peter.chen@kernel.org>
> > Reviewed-by: Roger Quadros <rogerq@kernel.org>
> > ---
> >  MAINTAINERS                        |   6 +
> >  drivers/usb/cdns3/Kconfig          |  11 ++
> >  drivers/usb/cdns3/Makefile         |   1 +
> >  drivers/usb/cdns3/cdns3-starfive.c | 246 +++++++++++++++++++++++++++++
> >  4 files changed, 264 insertions(+)
> >  create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 5519f81c8296..06c63f43bb17 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20168,6 +20168,12 @@ F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> >  F:	drivers/phy/starfive/phy-jh7110-pcie.c
> >  F:	drivers/phy/starfive/phy-jh7110-usb.c
> >  
> > +STARFIVE JH71X0 USB DRIVERS
> > +M:	Minda Chen <minda.chen@starfivetech.com>
> > +S:	Maintained
> > +F:	Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> > +F:	drivers/usb/cdns3/cdns3-starfive.c
> 
> Does not apply anymore, please rebase and resend.

Nevermind, I fixed it up.

Re: [PATCH v6 0/7] Add JH7110 USB and USB PHY driver support

[Minda Chen]

On 2023/5/26 17:03, Roger Quadros wrote:
> 
> 
> On 18/05/2023 14:27, Minda Chen wrote:
>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>> The patch has been tested on the VisionFive 2 board.
>> 
>> This patchset should be applied after the patchset [1], [2] and [3]:
>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/20230518101234.143748-1-xingyu.wu@starfivetech.com/
>> [2] https://patchwork.kernel.org/project/linux-clk/cover/20230512022036.97987-1-xingyu.wu@starfivetech.com
>> [3] https://patchwork.kernel.org/project/linux-phy/cover/20230412084540.295411-1-changhuang.liang@starfivetech.com/
>> 
>> This patchset is base on v6.4-rc1
>> 
>> patch 1 is usb phy dt-binding document.
>> patch 2 is Pcie PHY dt-binding document.
>> patch 3 is USB 2.0 PHY driver.
>> patch 4 is PCIe PHY driver.
>> patch 5 is usb dt-binding document.
>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>> patch 7 is USB device tree configuration.
>> 
>> previous version
>> ---
>> version 1 patchset are split to different kernel organization. It is
>> incorrect. But they were sent, and Emil sent comments. I think I should 
>> reserve them in cover-letter. To read the change records and previous version, 
>> please start with version 2. 
>> 
>> v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
>> v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
>> v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
>> v4: https://patchwork.kernel.org/project/linux-usb/cover/20230406015216.27034-1-minda.chen@starfivetech.com/
>> v5: https://patchwork.kernel.org/project/linux-usb/cover/20230420110052.3182-1-minda.chen@starfivetech.com/
>> 
>> changes
>> v6:
>>   1. (patch 3) remove the platform remove function.
>>   2. (patch 4)
>>      - add switch to pcie mode function.
>>      - remove the redundant init/exit function.
>>   3. (patch 5)
>>      - dts split to wrapper layer and cdns node. The codes are
>>        like v3.
>>      - add cdns3 sub node dts-binding references.
>>   4. (patch 6)
>>      For stg-syscon iomem 0x10240000 - 0x10240010 actually is belonged
>>      to usb, so USB contain its own registers. So do not merge the dts node.
>>      The codes are like v3.
>>      - remove the cdns3_platform_add function.
>>      - remove phy ops because cdns3 contain all the phy ops.
>>      - runtime suspend function just shutdown the clocks.
>>   5. (patch 7)
>>      - add cdns3 subnode again.
>> 
>> v5:
>>   1. (patch 1) set correct model name and commit title.
>>   2. (patch 2) change to '-item' in syscon property. change commit title.
>>   3. (patch 5)
>>      - change to '-item' in syscon configure.
>>      - change commit title and doc title.
>>   4. (patch 6)
>>      - add clk and phy deinit function
>>      - add clk deinit function if phy init failed.
>>      - coding style changes and other format changes. 
>> 
>> v4:
>>   1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>>   2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>>   3. (patch 3)
>>      - split PCIe PHY driver to patch 4.
>>      - replace dr_mode to phy mode in jh7110_usb2_phy.
>>   4. (patch 4) 
>>      - Makefile and Kconfig sorted by alphabet sequence.
>>      - Add PCIe PHY stg and syscon PHY connection configuration
>>        for USB 3.0.
>>   5. (patch 5)
>>      - commit message changed.
>>      - merge wrapper dts node and cdns3 node in example.
>>      - Add interrupts, reg, phy and dr_mode in property.
>>      - Add reset-name in property example.
>>   6. (patch 6)
>>      - For dts node is merged, Using platform_device_alloc and
>>        platform_device_add to generate cadence sub device.
>>      - IOMEM and IRQ resource are passed to Cadence sub device.
>>      - Add PHY ops process for PHY dts setting can not be passed to
>>        Cadence USB driver.
>>      - remove the stg and sys USB 3.0 PHY configuration.
>>      - Change the suspend clock reset and clock enable sequence.
>>      - Get all reset and clock resources before enable them in 
>>        cdns_clk_rst_init.
>>      - commit message changed.
>>   7. (patch 7)
>>      - merge wrapper dts node and cdns3 node in usb dts.
>>      - move the stg and sys USB 3.0 PHY confiuration to
>>        PCIe PHY dts node.
>>      - commit message changed.
>>      - Add reset-names dts.
>> 
>> v3:
>>   1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc. 
>>      USB PHY codes are moved to patch 3 and patch 4.
>>   2. (patch 5)
>>      - USB wrapper module dts document is moved to usb directory.
>>      - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>>      - Some dts format changes. dts binding check pass.
>>   3. (patch 6)
>>      - Remove the PHY codes. 
>>      - Search 'dr_mode' and phy setting from Cadence subnode.
>>   4. (patch 7)
>>      - Add USB PHY dts configurion. 
>>      - 'dr_mode' is moved to Cadence controller submode.
>> 
>> v2:
>>   1. (patch 5) dt-binding changes. The document example is the same as dts config.
>>   2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>>   3. (patch 7) dts nodes sorted by the address after @
>> 
>> Minda Chen (7):
>>   dt-bindings: phy: Add StarFive JH7110 USB PHY
>>   dt-bindings: phy: Add StarFive JH7110 PCIe PHY
>>   phy: starfive: Add JH7110 USB 2.0 PHY driver
>>   phy: starfive: Add JH7110 PCIE 2.0 PHY driver
>>   dt-bindings: usb: Add StarFive JH7110 USB controller
>>   usb: cdns3: Add StarFive JH7110 USB driver
>>   riscv: dts: starfive: Add USB dts configuration for JH7110
>> 
>>  .../phy/starfive,jh7110-pcie-phy.yaml         |  58 +++++
>>  .../bindings/phy/starfive,jh7110-usb-phy.yaml |  50 ++++
>>  .../bindings/usb/starfive,jh7110-usb.yaml     | 115 ++++++++
>>  MAINTAINERS                                   |  14 +
>>  .../jh7110-starfive-visionfive-2.dtsi         |   5 +
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi      |  53 ++++
>>  drivers/phy/starfive/Kconfig                  |  21 ++
>>  drivers/phy/starfive/Makefile                 |   2 +
>>  drivers/phy/starfive/phy-jh7110-pcie.c        | 204 +++++++++++++++
>>  drivers/phy/starfive/phy-jh7110-usb.c         | 150 +++++++++++
>>  drivers/usb/cdns3/Kconfig                     |  11 +
>>  drivers/usb/cdns3/Makefile                    |   1 +
>>  drivers/usb/cdns3/cdns3-starfive.c            | 246 ++++++++++++++++++
>>  13 files changed, 930 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>>  create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>  create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>>  create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>>  create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>> 
> 
> For this series:
> Reviewed-by: Roger Quadros <rogerq@kernel.org>

Thanks Roger， Coner and Greg.
Patch 6 (USB controller codes) are accepted. 

Thanks Rob and Krzysztof.
  Dts-binding doc are reviewed.

Hi Vinod , Kishon and Linux-PHY maintainer
  Could you take time to review USB PHY codes (patch 3 and patch4) ? Thanks

Re: [PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration for JH7110

[Conor Dooley]

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On Mon, May 29, 2023 at 03:46:21PM +0100, Greg Kroah-Hartman wrote:
> On Thu, May 25, 2023 at 10:36:38PM +0100, Conor Dooley wrote:
> > Greg,
> > 
> > On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote:
> > > Add USB wrapper layer and Cadence USB3 controller dts
> > > configuration for StarFive JH7110 SoC and VisionFive2
> > > Board.
> > > USB controller connect to PHY, The PHY dts configuration
> > > are also added.
> > > 
> > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > 
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > index 71a8e9acbe55..b65f06c5b1b7 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > @@ -366,6 +366,59 @@
> > >  			status = "disabled";
> > >  		};
> > >  
> > > +		usb0: usb@10100000 {
> > > +			compatible = "starfive,jh7110-usb";
> > > +			ranges = <0x0 0x0 0x10100000 0x100000>;
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			starfive,stg-syscon = <&stg_syscon 0x4>;
> > > +			clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
> > 
> > Please don't pick this patch, if the rest of the series is applicable,
> > as this will break building the dtb as stgcrg does not yet exist in any
> > maintainer tree.
> 
> Ok, I'll just take patch 6/7 then.

I think I missed this mail somehow. 5/7 had the binding for the driver
so probably that should've gone via the USB tree too?
Should apply on its own (no deps on the phy patches) & has dt-binding
maintainer reviews.

`b4 am -P 5 20230518112750.57924-6-minda.chen@starfivetech.com` if
that's your cup of tea.

Cheers,
Conor.

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Re: [PATCH v6 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller

[Minda Chen]

On 2023/5/26 21:13, Conor Dooley wrote:
> On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote:
> 
>> >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
>> > 
>> > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
>> > USBSS-DRD SoC controller"?
>> > 
>> The previous title describe whole USB controller for previous dts node is
>> merged. Now the dts node is split. 
>> "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
> 
> Okay, I must have misunderstood the conversation on the previous
> version. Sorry about that.
> 
>> > Otherwise, it looks like all the stuff from him and Rob have been sorted
>> > out, so other than $title this is
>> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 

Hi Greg
Can this patch can be applied to Linux-USB-next tree? Since this patch is reviewed by Conor.

List Below is Conor's previous E-mail.

   I think I missed this mail somehow. 5/7 had the binding for the driver
   so probably that should've gone via the USB tree too?
   Should apply on its own (no deps on the phy patches) & has dt-binding
   maintainer reviews.

   `b4 am -P 5 20230518112750.57924-6-minda.chen@starfivetech.com` if
   that's your cup of tea.

Re: [PATCH v6 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller

[Greg Kroah-Hartman]

On Sun, Jun 18, 2023 at 08:22:05PM +0800, Minda Chen wrote:
> 
> 
> On 2023/5/26 21:13, Conor Dooley wrote:
> > On Fri, May 26, 2023 at 06:24:48PM +0800, Minda Chen wrote:
> > 
> >> >> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
> >> > 
> >> > I think you told Krzysztof you'd rename this to "StarFive JH7110 Cadence
> >> > USBSS-DRD SoC controller"?
> >> > 
> >> The previous title describe whole USB controller for previous dts node is
> >> merged. Now the dts node is split. 
> >> "starfive,jh7110-usb" just contain starfive wrapper layer dts configuration.
> > 
> > Okay, I must have misunderstood the conversation on the previous
> > version. Sorry about that.
> > 
> >> > Otherwise, it looks like all the stuff from him and Rob have been sorted
> >> > out, so other than $title this is
> >> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> 
> Hi Greg
> Can this patch can be applied to Linux-USB-next tree? Since this patch is reviewed by Conor.
> 
> List Below is Conor's previous E-mail.
> 
>    I think I missed this mail somehow. 5/7 had the binding for the driver
>    so probably that should've gone via the USB tree too?
>    Should apply on its own (no deps on the phy patches) & has dt-binding
>    maintainer reviews.
> 
>    `b4 am -P 5 20230518112750.57924-6-minda.chen@starfivetech.com` if
>    that's your cup of tea.

Thanks, I missed that, now applied!

greg k-h