* [PATCH v2] xen: support 52 bit physical addresses in pv guests
@ 2017-10-27 17:49 Juergen Gross
2017-10-27 22:33 ` Boris Ostrovsky
2017-10-31 17:51 ` Boris Ostrovsky
0 siblings, 2 replies; 3+ messages in thread
From: Juergen Gross @ 2017-10-27 17:49 UTC (permalink / raw)
To: linux-kernel, xen-devel, x86
Cc: boris.ostrovsky, hpa, tglx, mingo, Juergen Gross
Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses have to be supported in order to be able to use any
memory on the machine even if the guest itself does not support 5 level
paging.
So when reading/writing a MFN from/to a pte don't use the kernel's
PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
V2:
- use __sme_clr() to clear any SME bit from MFN (Boris Ostrovsky)
---
arch/x86/include/asm/xen/page.h | 11 ++++++++++-
arch/x86/xen/mmu_pv.c | 4 ++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 07b6531813c4..90e91003fd9d 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -26,6 +26,15 @@ typedef struct xpaddr {
phys_addr_t paddr;
} xpaddr_t;
+#ifdef CONFIG_X86_64
+#define XEN_PHYSICAL_MASK __sme_clr((1UL << 52) - 1)
+#else
+#define XEN_PHYSICAL_MASK __PHYSICAL_MASK
+#endif
+
+#define XEN_PTE_MFN_MASK ((pteval_t)(((signed long)PAGE_MASK) & \
+ XEN_PHYSICAL_MASK))
+
#define XMADDR(x) ((xmaddr_t) { .maddr = (x) })
#define XPADDR(x) ((xpaddr_t) { .paddr = (x) })
@@ -277,7 +286,7 @@ static inline unsigned long bfn_to_local_pfn(unsigned long mfn)
static inline unsigned long pte_mfn(pte_t pte)
{
- return (pte.pte & PTE_PFN_MASK) >> PAGE_SHIFT;
+ return (pte.pte & XEN_PTE_MFN_MASK) >> PAGE_SHIFT;
}
static inline pte_t mfn_pte(unsigned long page_nr, pgprot_t pgprot)
diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
index 71495f1a86d7..9d9cc3870722 100644
--- a/arch/x86/xen/mmu_pv.c
+++ b/arch/x86/xen/mmu_pv.c
@@ -315,7 +315,7 @@ void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
static pteval_t pte_mfn_to_pfn(pteval_t val)
{
if (val & _PAGE_PRESENT) {
- unsigned long mfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT;
+ unsigned long mfn = (val & XEN_PTE_MFN_MASK) >> PAGE_SHIFT;
unsigned long pfn = mfn_to_pfn(mfn);
pteval_t flags = val & PTE_FLAGS_MASK;
@@ -1735,7 +1735,7 @@ static unsigned long __init m2p(phys_addr_t maddr)
{
phys_addr_t paddr;
- maddr &= PTE_PFN_MASK;
+ maddr &= XEN_PTE_MFN_MASK;
paddr = mfn_to_pfn(maddr >> PAGE_SHIFT) << PAGE_SHIFT;
return paddr;
--
2.12.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] xen: support 52 bit physical addresses in pv guests
2017-10-27 17:49 [PATCH v2] xen: support 52 bit physical addresses in pv guests Juergen Gross
@ 2017-10-27 22:33 ` Boris Ostrovsky
2017-10-31 17:51 ` Boris Ostrovsky
1 sibling, 0 replies; 3+ messages in thread
From: Boris Ostrovsky @ 2017-10-27 22:33 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, xen-devel, x86; +Cc: hpa, tglx, mingo
On 10/27/2017 01:49 PM, Juergen Gross wrote:
> Physical addresses on processors supporting 5 level paging can be up to
> 52 bits wide. For a Xen pv guest running on such a machine those
> physical addresses have to be supported in order to be able to use any
> memory on the machine even if the guest itself does not support 5 level
> paging.
>
> So when reading/writing a MFN from/to a pte don't use the kernel's
> PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] xen: support 52 bit physical addresses in pv guests
2017-10-27 17:49 [PATCH v2] xen: support 52 bit physical addresses in pv guests Juergen Gross
2017-10-27 22:33 ` Boris Ostrovsky
@ 2017-10-31 17:51 ` Boris Ostrovsky
1 sibling, 0 replies; 3+ messages in thread
From: Boris Ostrovsky @ 2017-10-31 17:51 UTC (permalink / raw)
To: Juergen Gross, linux-kernel, xen-devel, x86; +Cc: hpa, tglx, mingo
On 10/27/2017 01:49 PM, Juergen Gross wrote:
> Physical addresses on processors supporting 5 level paging can be up to
> 52 bits wide. For a Xen pv guest running on such a machine those
> physical addresses have to be supported in order to be able to use any
> memory on the machine even if the guest itself does not support 5 level
> paging.
>
> So when reading/writing a MFN from/to a pte don't use the kernel's
> PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs.
>
> Signed-off-by: Juergen Gross <jgross@suse.com>
Applied to for-linus-4.15
-boris
^ permalink raw reply [flat|nested] 3+ messages in thread
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